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3783
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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3783
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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/**
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******************************************************************************
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* @file stm32_hal_legacy.h
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* @author MCD Application Team
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* @brief This file contains aliases definition for the STM32Cube HAL constants
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* macros and functions maintained for legacy purpose.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32_HAL_LEGACY
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#define STM32_HAL_LEGACY
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define AES_FLAG_RDERR CRYP_FLAG_RDERR
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#define AES_FLAG_WRERR CRYP_FLAG_WRERR
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#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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/**
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* @}
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*/
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/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
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#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
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#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
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#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
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#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
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#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
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#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
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#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
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#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
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#define REGULAR_GROUP ADC_REGULAR_GROUP
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#define INJECTED_GROUP ADC_INJECTED_GROUP
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#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
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#define AWD_EVENT ADC_AWD_EVENT
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#define AWD1_EVENT ADC_AWD1_EVENT
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#define AWD2_EVENT ADC_AWD2_EVENT
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#define AWD3_EVENT ADC_AWD3_EVENT
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#define OVR_EVENT ADC_OVR_EVENT
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#define JQOVF_EVENT ADC_JQOVF_EVENT
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#define ALL_CHANNELS ADC_ALL_CHANNELS
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#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
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#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
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#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
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#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
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#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
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#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
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#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
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#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
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#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
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#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
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#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
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#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
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#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
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#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
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#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
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#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
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#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
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#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
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#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
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#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
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#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
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#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
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#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
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#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
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#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
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#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
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#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
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#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
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#if defined(STM32H7)
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#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
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#endif /* STM32H7 */
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/**
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* @}
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*/
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/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
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/**
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* @}
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*/
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/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
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#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
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#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
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#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
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#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
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#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
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#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
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#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
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#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
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#if defined(STM32L0)
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#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
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#endif
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#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
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#if defined(STM32F373xC) || defined(STM32F378xx)
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#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
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#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
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#endif /* STM32F373xC || STM32F378xx */
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#if defined(STM32L0) || defined(STM32L4)
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#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
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#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
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#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
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#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
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#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
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#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
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#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
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#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
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#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
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#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
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#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
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#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
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#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
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#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
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#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
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#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
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#if defined(STM32L0)
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/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
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/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
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/* to the second dedicated IO (only for COMP2). */
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#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
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#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
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#else
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#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
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#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
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#endif
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#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
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#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
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#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
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#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
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/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
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/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
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#if defined(COMP_CSR_LOCK)
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#define COMP_FLAG_LOCK COMP_CSR_LOCK
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#elif defined(COMP_CSR_COMP1LOCK)
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#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
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#elif defined(COMP_CSR_COMPxLOCK)
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#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
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#endif
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#if defined(STM32L4)
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#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
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#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
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#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
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#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
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#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
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#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
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#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
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#endif
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#if defined(STM32L0)
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#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
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#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
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#else
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#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
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#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
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#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
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#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
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#endif
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#endif
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/**
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* @}
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*/
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/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
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/**
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* @}
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*/
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/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
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#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
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/**
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* @}
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*/
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/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define DAC1_CHANNEL_1 DAC_CHANNEL_1
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#define DAC1_CHANNEL_2 DAC_CHANNEL_2
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#define DAC2_CHANNEL_1 DAC_CHANNEL_1
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#define DAC_WAVE_NONE 0x00000000U
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#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
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#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
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#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
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#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
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#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
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#if defined(STM32G4) || defined(STM32H7)
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#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
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#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
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#endif
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
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#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
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#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
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#endif
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/**
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* @}
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*/
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/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
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#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
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#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
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#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
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#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
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#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
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#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
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#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
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#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
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#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
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#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
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#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
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#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
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#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
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#define IS_HAL_REMAPDMA IS_DMA_REMAP
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#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
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#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
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#if defined(STM32L4)
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
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#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
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||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
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||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
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#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
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#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
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#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
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||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
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||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
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||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
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#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
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||||
#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
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||||
#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
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||||
#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
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||||
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||||
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||
|
||||
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
||||
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
|
||||
#endif
|
||||
|
||||
#endif /* STM32L4 */
|
||||
|
||||
#if defined(STM32G0)
|
||||
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
|
||||
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
|
||||
#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
|
||||
#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
|
||||
|
||||
#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
|
||||
#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
|
||||
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
|
||||
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
|
||||
|
||||
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
|
||||
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
|
||||
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
|
||||
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
|
||||
|
||||
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||
|
||||
#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
|
||||
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
|
||||
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
|
||||
|
||||
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
|
||||
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
|
||||
|
||||
#endif /* STM32H7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
|
||||
#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
|
||||
#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
|
||||
#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
|
||||
#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
|
||||
#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
|
||||
#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
|
||||
#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
|
||||
#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
|
||||
#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
|
||||
#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
|
||||
#define OBEX_PCROP OPTIONBYTE_PCROP
|
||||
#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
|
||||
#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
|
||||
#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
|
||||
#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
|
||||
#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
|
||||
#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
|
||||
#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
|
||||
#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
|
||||
#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
|
||||
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
|
||||
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
|
||||
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
|
||||
#define PAGESIZE FLASH_PAGE_SIZE
|
||||
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
|
||||
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
|
||||
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
|
||||
#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
|
||||
#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
|
||||
#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
|
||||
#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
|
||||
#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
|
||||
#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
|
||||
#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
|
||||
#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
|
||||
#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
|
||||
#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
|
||||
#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
|
||||
#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
|
||||
#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
|
||||
#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
|
||||
#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
|
||||
#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
|
||||
#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
|
||||
#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
|
||||
#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
|
||||
#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
|
||||
#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
|
||||
#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
|
||||
#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
|
||||
#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
|
||||
#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
|
||||
#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
|
||||
#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
|
||||
#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
|
||||
#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
|
||||
#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
|
||||
#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
|
||||
#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
|
||||
#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
|
||||
#define OB_WDG_SW OB_IWDG_SW
|
||||
#define OB_WDG_HW OB_IWDG_HW
|
||||
#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
|
||||
#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
|
||||
#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
|
||||
#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
|
||||
#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
|
||||
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
|
||||
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
|
||||
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
|
||||
#if defined(STM32G0)
|
||||
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
|
||||
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
|
||||
#else
|
||||
#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
|
||||
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
|
||||
#endif
|
||||
#if defined(STM32H7)
|
||||
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
|
||||
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
|
||||
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
|
||||
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
|
||||
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
|
||||
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
|
||||
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
|
||||
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
|
||||
#endif /* STM32H7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
|
||||
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
|
||||
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
|
||||
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
|
||||
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
|
||||
#endif /* STM32H7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
|
||||
#if defined(STM32G4)
|
||||
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
|
||||
#endif /* STM32G4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
|
||||
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
|
||||
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
|
||||
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
|
||||
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
|
||||
#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
|
||||
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
|
||||
#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
|
||||
#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
|
||||
#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
|
||||
#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define GET_GPIO_SOURCE GPIO_GET_INDEX
|
||||
#define GET_GPIO_INDEX GPIO_GET_INDEX
|
||||
|
||||
#if defined(STM32F4)
|
||||
#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
|
||||
#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
|
||||
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4)
|
||||
#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
|
||||
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
|
||||
#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
|
||||
#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
|
||||
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
|
||||
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
|
||||
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
|
||||
|
||||
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
|
||||
defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
|
||||
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
|
||||
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
|
||||
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
|
||||
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
|
||||
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
||||
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
||||
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
||||
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
|
||||
|
||||
#if defined(STM32L1)
|
||||
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
||||
#endif /* STM32L1 */
|
||||
|
||||
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
|
||||
#endif /* STM32F0 || STM32F3 || STM32F1 */
|
||||
|
||||
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
|
||||
|
||||
#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
|
||||
#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
|
||||
#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
|
||||
#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
|
||||
#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
|
||||
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
|
||||
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
|
||||
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
|
||||
|
||||
#if defined(STM32G4)
|
||||
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
|
||||
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
|
||||
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
|
||||
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
|
||||
#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
|
||||
#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
|
||||
#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
|
||||
#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
|
||||
#endif /* STM32G4 */
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#if defined(STM32F3)
|
||||
/** @brief Constants defining available sources associated to external events.
|
||||
*/
|
||||
#define HRTIM_EVENTSRC_1 (0x00000000U)
|
||||
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
|
||||
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
|
||||
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
|
||||
|
||||
/** @brief Constants defining the events that can be selected to configure the
|
||||
* set/reset crossbar of a timer output
|
||||
*/
|
||||
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
|
||||
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
|
||||
|
||||
/** @brief Constants defining the event filtering applied to external events
|
||||
* by a timer
|
||||
*/
|
||||
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
|
||||
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
|
||||
/** @brief Constants defining the DLL calibration periods (in micro seconds)
|
||||
*/
|
||||
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
|
||||
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
|
||||
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
|
||||
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
|
||||
|
||||
#endif /* STM32F3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
|
||||
#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
|
||||
#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
|
||||
#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
|
||||
#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
|
||||
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
|
||||
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
|
||||
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
|
||||
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
|
||||
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
|
||||
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
|
||||
#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
|
||||
#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define KR_KEY_RELOAD IWDG_KEY_RELOAD
|
||||
#define KR_KEY_ENABLE IWDG_KEY_ENABLE
|
||||
#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
|
||||
#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
|
||||
#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
|
||||
#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
|
||||
#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
|
||||
|
||||
#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
|
||||
#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
|
||||
#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
|
||||
|
||||
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
|
||||
#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
|
||||
#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
|
||||
#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
|
||||
|
||||
/* The following 3 definition have also been present in a temporary version of lptim.h */
|
||||
/* They need to be renamed also to the right name, just in case */
|
||||
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
|
||||
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
|
||||
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
|
||||
#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
|
||||
#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
|
||||
#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
|
||||
|
||||
#define NAND_AddressTypedef NAND_AddressTypeDef
|
||||
|
||||
#define __ARRAY_ADDRESS ARRAY_ADDRESS
|
||||
#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
|
||||
#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
|
||||
#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
|
||||
#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
|
||||
#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
|
||||
#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
|
||||
#define NOR_ERROR HAL_NOR_STATUS_ERROR
|
||||
#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
|
||||
|
||||
#define __NOR_WRITE NOR_WRITE
|
||||
#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
|
||||
#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
|
||||
#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
|
||||
#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
|
||||
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
|
||||
|
||||
#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
|
||||
#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
|
||||
|
||||
#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
|
||||
#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
|
||||
|
||||
#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
|
||||
#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
|
||||
|
||||
#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
|
||||
|
||||
#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
|
||||
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
|
||||
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
|
||||
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
|
||||
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define I2S_IT_TXE I2S_IT_TXP
|
||||
#define I2S_IT_RXNE I2S_IT_RXP
|
||||
|
||||
#define I2S_FLAG_TXE I2S_FLAG_TXP
|
||||
#define I2S_FLAG_RXNE I2S_FLAG_RXP
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Compact Flash-ATA registers description */
|
||||
#define CF_DATA ATA_DATA
|
||||
#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
|
||||
#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
|
||||
#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
|
||||
#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
|
||||
#define CF_CARD_HEAD ATA_CARD_HEAD
|
||||
#define CF_STATUS_CMD ATA_STATUS_CMD
|
||||
#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
|
||||
#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
|
||||
|
||||
/* Compact Flash-ATA commands */
|
||||
#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
|
||||
#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
|
||||
#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
|
||||
#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
|
||||
|
||||
#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
|
||||
#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
|
||||
#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
|
||||
#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
|
||||
#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FORMAT_BIN RTC_FORMAT_BIN
|
||||
#define FORMAT_BCD RTC_FORMAT_BCD
|
||||
|
||||
#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
|
||||
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
|
||||
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
|
||||
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
|
||||
|
||||
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
|
||||
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
|
||||
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
|
||||
#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
|
||||
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
|
||||
|
||||
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
|
||||
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
|
||||
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
|
||||
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
|
||||
|
||||
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
|
||||
#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
|
||||
#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
|
||||
|
||||
#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
|
||||
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
|
||||
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
|
||||
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
|
||||
|
||||
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
|
||||
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
|
||||
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
|
||||
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
|
||||
#endif /* STM32H7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
|
||||
#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
|
||||
|
||||
#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
|
||||
#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
|
||||
#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
|
||||
#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
|
||||
|
||||
#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
|
||||
#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
|
||||
|
||||
#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
|
||||
#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
|
||||
#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
|
||||
#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
|
||||
#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
|
||||
#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
|
||||
#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
|
||||
#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
|
||||
#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
|
||||
#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
|
||||
#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
|
||||
#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
|
||||
#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
|
||||
|
||||
#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
|
||||
#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
|
||||
|
||||
#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
|
||||
#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
|
||||
|
||||
#if defined(STM32H7)
|
||||
|
||||
#define SPI_FLAG_TXE SPI_FLAG_TXP
|
||||
#define SPI_FLAG_RXNE SPI_FLAG_RXP
|
||||
|
||||
#define SPI_IT_TXE SPI_IT_TXP
|
||||
#define SPI_IT_RXNE SPI_IT_RXP
|
||||
|
||||
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
|
||||
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
|
||||
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
|
||||
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
|
||||
|
||||
#endif /* STM32H7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
|
||||
#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
|
||||
|
||||
#define TIM_DMABase_CR1 TIM_DMABASE_CR1
|
||||
#define TIM_DMABase_CR2 TIM_DMABASE_CR2
|
||||
#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
|
||||
#define TIM_DMABase_DIER TIM_DMABASE_DIER
|
||||
#define TIM_DMABase_SR TIM_DMABASE_SR
|
||||
#define TIM_DMABase_EGR TIM_DMABASE_EGR
|
||||
#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
|
||||
#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
|
||||
#define TIM_DMABase_CCER TIM_DMABASE_CCER
|
||||
#define TIM_DMABase_CNT TIM_DMABASE_CNT
|
||||
#define TIM_DMABase_PSC TIM_DMABASE_PSC
|
||||
#define TIM_DMABase_ARR TIM_DMABASE_ARR
|
||||
#define TIM_DMABase_RCR TIM_DMABASE_RCR
|
||||
#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
|
||||
#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
|
||||
#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
|
||||
#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
|
||||
#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
|
||||
#define TIM_DMABase_DCR TIM_DMABASE_DCR
|
||||
#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
|
||||
#define TIM_DMABase_OR1 TIM_DMABASE_OR1
|
||||
#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
|
||||
#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
|
||||
#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
|
||||
#define TIM_DMABase_OR2 TIM_DMABASE_OR2
|
||||
#define TIM_DMABase_OR3 TIM_DMABASE_OR3
|
||||
#define TIM_DMABase_OR TIM_DMABASE_OR
|
||||
|
||||
#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
|
||||
#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
|
||||
#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
|
||||
#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
|
||||
#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
|
||||
#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
|
||||
#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
|
||||
#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
|
||||
#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
|
||||
|
||||
#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
|
||||
#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
|
||||
#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
|
||||
#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
|
||||
#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
|
||||
#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
|
||||
#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
|
||||
#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
|
||||
#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
|
||||
#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
|
||||
#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
|
||||
#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
|
||||
#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
|
||||
#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
|
||||
#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
|
||||
#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
|
||||
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
|
||||
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
|
||||
|
||||
#if defined(STM32L0)
|
||||
#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
|
||||
#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
|
||||
#endif
|
||||
|
||||
#if defined(STM32F3)
|
||||
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
|
||||
#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
|
||||
#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
|
||||
#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
|
||||
#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
|
||||
#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
|
||||
#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
|
||||
#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
|
||||
#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
|
||||
#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
|
||||
#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
|
||||
#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
|
||||
#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
|
||||
#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
|
||||
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
|
||||
#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
|
||||
#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
|
||||
#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
|
||||
#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
|
||||
|
||||
#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
|
||||
#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
|
||||
|
||||
#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
|
||||
#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
|
||||
#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
|
||||
#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
|
||||
|
||||
#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
|
||||
#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
|
||||
#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
|
||||
#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
|
||||
|
||||
#define __DIV_LPUART UART_DIV_LPUART
|
||||
|
||||
#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
|
||||
#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
|
||||
#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
|
||||
|
||||
#define USARTNACK_ENABLED USART_NACK_ENABLE
|
||||
#define USARTNACK_DISABLED USART_NACK_DISABLE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define CFR_BASE WWDG_CFR_BASE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
|
||||
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||
#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
|
||||
#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
|
||||
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
|
||||
#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
|
||||
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define VLAN_TAG ETH_VLAN_TAG
|
||||
#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
|
||||
#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
|
||||
#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
|
||||
#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
|
||||
#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
|
||||
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
|
||||
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
|
||||
|
||||
#define ETH_MMCCR 0x00000100U
|
||||
#define ETH_MMCRIR 0x00000104U
|
||||
#define ETH_MMCTIR 0x00000108U
|
||||
#define ETH_MMCRIMR 0x0000010CU
|
||||
#define ETH_MMCTIMR 0x00000110U
|
||||
#define ETH_MMCTGFSCCR 0x0000014CU
|
||||
#define ETH_MMCTGFMSCCR 0x00000150U
|
||||
#define ETH_MMCTGFCR 0x00000168U
|
||||
#define ETH_MMCRFCECR 0x00000194U
|
||||
#define ETH_MMCRFAECR 0x00000198U
|
||||
#define ETH_MMCRGUFCR 0x000001C4U
|
||||
|
||||
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
|
||||
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
|
||||
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
|
||||
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
|
||||
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
|
||||
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
|
||||
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
|
||||
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
|
||||
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
|
||||
#if defined(STM32F1)
|
||||
#else
|
||||
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
|
||||
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
|
||||
#endif
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
|
||||
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
|
||||
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
|
||||
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
|
||||
#define DCMI_IT_OVF DCMI_IT_OVR
|
||||
#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
|
||||
#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
|
||||
|
||||
#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
|
||||
#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
|
||||
#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
|
||||
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
|
||||
|| defined(STM32H7)
|
||||
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
|
||||
#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
|
||||
#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
|
||||
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
|
||||
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
|
||||
|
||||
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
|
||||
#define CM_RGB888 DMA2D_INPUT_RGB888
|
||||
#define CM_RGB565 DMA2D_INPUT_RGB565
|
||||
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
|
||||
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
|
||||
#define CM_L8 DMA2D_INPUT_L8
|
||||
#define CM_AL44 DMA2D_INPUT_AL44
|
||||
#define CM_AL88 DMA2D_INPUT_AL88
|
||||
#define CM_L4 DMA2D_INPUT_L4
|
||||
#define CM_A8 DMA2D_INPUT_A8
|
||||
#define CM_A4 DMA2D_INPUT_A4
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
|
||||
#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
|
||||
#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
|
||||
#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
|
||||
#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
|
||||
#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
|
||||
|
||||
/*HASH Algorithm Selection*/
|
||||
|
||||
#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
|
||||
#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
|
||||
#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
|
||||
#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
|
||||
|
||||
#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
|
||||
#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
|
||||
|
||||
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
|
||||
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
|
||||
|
||||
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
|
||||
|
||||
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
|
||||
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
|
||||
#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
|
||||
#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
|
||||
|
||||
#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
|
||||
#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
|
||||
#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
|
||||
#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
|
||||
|
||||
#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
|
||||
#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
|
||||
#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
|
||||
#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
|
||||
|
||||
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
|
||||
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
|
||||
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
|
||||
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
|
||||
|
||||
#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
|
||||
#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
|
||||
#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
|
||||
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
|
||||
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
|
||||
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
|
||||
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
|
||||
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
|
||||
#if defined(STM32L0)
|
||||
#else
|
||||
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
|
||||
#endif
|
||||
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
||||
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
|
||||
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
|
||||
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
|
||||
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
|
||||
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
|
||||
#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
|
||||
#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
|
||||
#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
|
||||
#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
|
||||
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
|
||||
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
|
||||
#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
|
||||
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
|
||||
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
||||
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
|
||||
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
|
||||
#if defined(STM32F4)
|
||||
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
|
||||
#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
|
||||
#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
|
||||
#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
|
||||
#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
|
||||
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
|
||||
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
|
||||
#endif /* STM32F4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32G0)
|
||||
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
|
||||
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
|
||||
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
|
||||
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
|
||||
#endif
|
||||
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
|
||||
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
|
||||
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
|
||||
#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
|
||||
#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
|
||||
#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
|
||||
#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
|
||||
#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
|
||||
#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
|
||||
#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
|
||||
#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
|
||||
#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
|
||||
#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
|
||||
#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
|
||||
#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
|
||||
#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
|
||||
|
||||
#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
|
||||
#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
|
||||
#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
|
||||
#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
|
||||
#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
|
||||
#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
|
||||
#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
|
||||
|
||||
#define CR_OFFSET_BB PWR_CR_OFFSET_BB
|
||||
#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
|
||||
#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
|
||||
#define CR_PMODE_BB CR_VOS_BB
|
||||
|
||||
#define DBP_BitNumber DBP_BIT_NUMBER
|
||||
#define PVDE_BitNumber PVDE_BIT_NUMBER
|
||||
#define PMODE_BitNumber PMODE_BIT_NUMBER
|
||||
#define EWUP_BitNumber EWUP_BIT_NUMBER
|
||||
#define FPDS_BitNumber FPDS_BIT_NUMBER
|
||||
#define ODEN_BitNumber ODEN_BIT_NUMBER
|
||||
#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
|
||||
#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
|
||||
#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
|
||||
#define BRE_BitNumber BRE_BIT_NUMBER
|
||||
|
||||
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
|
||||
#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
|
||||
#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
|
||||
#define HAL_TIM_DMAError TIM_DMAError
|
||||
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
||||
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
|
||||
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
|
||||
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
|
||||
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
|
||||
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
|
||||
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
|
||||
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
|
||||
#define HAL_LTDC_Relaod HAL_LTDC_Reload
|
||||
#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
|
||||
#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define AES_IT_CC CRYP_IT_CC
|
||||
#define AES_IT_ERR CRYP_IT_ERR
|
||||
#define AES_FLAG_CCF CRYP_FLAG_CCF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
|
||||
#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
|
||||
#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
|
||||
#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
|
||||
#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
|
||||
#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
|
||||
#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
|
||||
#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
|
||||
#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
|
||||
#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
|
||||
#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
|
||||
#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
|
||||
#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
|
||||
#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
|
||||
|
||||
#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
|
||||
#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
|
||||
#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
|
||||
#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
|
||||
#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __ADC_ENABLE __HAL_ADC_ENABLE
|
||||
#define __ADC_DISABLE __HAL_ADC_DISABLE
|
||||
#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
|
||||
#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
|
||||
#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
|
||||
#define __ADC_IS_ENABLED ADC_IS_ENABLE
|
||||
#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
|
||||
#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
|
||||
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
|
||||
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
|
||||
#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
|
||||
#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
|
||||
#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
|
||||
|
||||
#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
|
||||
#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
|
||||
#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
|
||||
#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
|
||||
#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
|
||||
#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
|
||||
#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
|
||||
#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
|
||||
#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
|
||||
#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
|
||||
#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
|
||||
#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
|
||||
#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
|
||||
#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
|
||||
#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
|
||||
#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
|
||||
#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
|
||||
#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
|
||||
#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
|
||||
#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
|
||||
|
||||
#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
|
||||
#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
|
||||
#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
|
||||
#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
|
||||
#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
|
||||
#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
|
||||
#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
|
||||
#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
|
||||
#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
|
||||
#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
|
||||
|
||||
#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
|
||||
#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
|
||||
#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
|
||||
#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
|
||||
#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
|
||||
#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
|
||||
#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
|
||||
#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
|
||||
|
||||
#define __HAL_ADC_SQR1 ADC_SQR1
|
||||
#define __HAL_ADC_SMPR1 ADC_SMPR1
|
||||
#define __HAL_ADC_SMPR2 ADC_SMPR2
|
||||
#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
|
||||
#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
|
||||
#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
|
||||
#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
|
||||
#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
|
||||
#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
|
||||
#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
|
||||
#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
|
||||
#define __HAL_ADC_JSQR ADC_JSQR
|
||||
|
||||
#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
|
||||
#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
|
||||
#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
|
||||
#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
|
||||
#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
|
||||
#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
|
||||
#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
|
||||
#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
|
||||
#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
|
||||
#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
|
||||
#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
|
||||
#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
|
||||
#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
|
||||
#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
|
||||
#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
|
||||
#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
|
||||
#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
|
||||
#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
|
||||
#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
|
||||
#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
|
||||
#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
|
||||
#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
|
||||
#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
|
||||
#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
|
||||
#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
|
||||
#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
|
||||
|
||||
#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
|
||||
#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
|
||||
#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
|
||||
#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
|
||||
#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
|
||||
#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
|
||||
#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
|
||||
#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
|
||||
#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
|
||||
#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
|
||||
#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
|
||||
#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
|
||||
#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
|
||||
#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
|
||||
|
||||
|
||||
#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
|
||||
#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
|
||||
#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
|
||||
#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
|
||||
#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
|
||||
#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
|
||||
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
|
||||
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
|
||||
#else
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
||||
#endif /* STM32H7 */
|
||||
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
|
||||
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
|
||||
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
|
||||
#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
|
||||
#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
|
||||
#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
|
||||
#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
|
||||
#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
|
||||
#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
|
||||
#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
|
||||
#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
|
||||
#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F3)
|
||||
#define COMP_START __HAL_COMP_ENABLE
|
||||
#define COMP_STOP __HAL_COMP_DISABLE
|
||||
#define COMP_LOCK __HAL_COMP_LOCK
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_IT())
|
||||
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_IT())
|
||||
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_IT())
|
||||
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_IT())
|
||||
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
|
||||
__HAL_COMP_COMP7_EXTI_ENABLE_IT())
|
||||
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
|
||||
__HAL_COMP_COMP7_EXTI_DISABLE_IT())
|
||||
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
|
||||
__HAL_COMP_COMP7_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
|
||||
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
|
||||
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
#else
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
|
||||
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
|
||||
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
|
||||
#endif
|
||||
|
||||
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
|
||||
|
||||
#if defined(STM32L0) || defined(STM32L4)
|
||||
/* Note: On these STM32 families, the only argument of this macro */
|
||||
/* is COMP_FLAG_LOCK. */
|
||||
/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
|
||||
/* argument. */
|
||||
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32L0) || defined(STM32L4)
|
||||
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
|
||||
((WAVE) == DAC_WAVE_NOISE)|| \
|
||||
((WAVE) == DAC_WAVE_TRIANGLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_WRPAREA IS_OB_WRPAREA
|
||||
#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
|
||||
#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
|
||||
#define IS_TYPEERASE IS_FLASH_TYPEERASE
|
||||
#define IS_NBSECTORS IS_FLASH_NBSECTORS
|
||||
#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
|
||||
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
|
||||
#if defined(STM32F1)
|
||||
#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
|
||||
#else
|
||||
#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
|
||||
#endif /* STM32F1 */
|
||||
#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
|
||||
#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
|
||||
#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
|
||||
#define __HAL_I2C_SPEED I2C_SPEED
|
||||
#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
|
||||
#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
|
||||
#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
|
||||
#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
|
||||
#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
|
||||
#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
|
||||
#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
|
||||
#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
|
||||
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __IRDA_DISABLE __HAL_IRDA_DISABLE
|
||||
#define __IRDA_ENABLE __HAL_IRDA_ENABLE
|
||||
|
||||
#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
|
||||
#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
|
||||
#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
|
||||
#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
|
||||
|
||||
#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
|
||||
#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
|
||||
#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
|
||||
#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
|
||||
#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
|
||||
#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
|
||||
#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
|
||||
#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
|
||||
#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
|
||||
#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
|
||||
#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
|
||||
#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
|
||||
#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
|
||||
#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
|
||||
#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
|
||||
#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
|
||||
#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
|
||||
#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
|
||||
#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
|
||||
#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
|
||||
#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
|
||||
#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
|
||||
#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
|
||||
#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
|
||||
#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
|
||||
#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
|
||||
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
|
||||
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
|
||||
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
|
||||
#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
|
||||
#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
|
||||
#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
|
||||
|
||||
#if defined (STM32F4)
|
||||
#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
|
||||
#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
|
||||
#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
|
||||
#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
|
||||
#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
|
||||
#else
|
||||
#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
|
||||
#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
|
||||
#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
|
||||
#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
|
||||
#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
|
||||
#endif /* STM32F4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
|
||||
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
|
||||
|
||||
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
|
||||
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
|
||||
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
|
||||
#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
|
||||
#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
|
||||
#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
|
||||
#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
|
||||
#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
|
||||
#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
|
||||
#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
|
||||
#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
|
||||
#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
|
||||
#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
|
||||
#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
|
||||
#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
|
||||
#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
|
||||
#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
|
||||
#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
|
||||
#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
|
||||
#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
|
||||
#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
|
||||
#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
|
||||
#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
|
||||
#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
|
||||
#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
|
||||
#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
|
||||
#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
|
||||
#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
|
||||
#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
|
||||
#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
|
||||
#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
|
||||
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
|
||||
#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
|
||||
#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
|
||||
#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
|
||||
#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
|
||||
#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
|
||||
#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
|
||||
#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
|
||||
#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
|
||||
#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
|
||||
#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
|
||||
#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
|
||||
#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
|
||||
#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
|
||||
#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
|
||||
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
|
||||
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
|
||||
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
|
||||
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
|
||||
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
|
||||
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
|
||||
#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
|
||||
#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
|
||||
#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
|
||||
#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
|
||||
#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
|
||||
#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
|
||||
#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
|
||||
#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
|
||||
#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
|
||||
#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
|
||||
#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
|
||||
#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
|
||||
#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
|
||||
#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
|
||||
#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
|
||||
#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
|
||||
#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
|
||||
#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
|
||||
#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
|
||||
#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
|
||||
#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
|
||||
#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
|
||||
#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
|
||||
#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
|
||||
#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
|
||||
#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
|
||||
#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
|
||||
#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
|
||||
#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
|
||||
#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
|
||||
#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
|
||||
#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
|
||||
#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
|
||||
#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
|
||||
#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
|
||||
#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
|
||||
#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
|
||||
#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
|
||||
#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
|
||||
#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
|
||||
#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
|
||||
#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
|
||||
#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
|
||||
#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
|
||||
#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
|
||||
#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
|
||||
#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
|
||||
#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
|
||||
#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
|
||||
#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
|
||||
#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
|
||||
#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
|
||||
#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
|
||||
#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
|
||||
#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
|
||||
#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
|
||||
#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
|
||||
#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
|
||||
#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
|
||||
#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
|
||||
#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
|
||||
#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
|
||||
#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
|
||||
#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
|
||||
#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
|
||||
#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
|
||||
#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
|
||||
#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
|
||||
#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
|
||||
#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
|
||||
#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
|
||||
#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
|
||||
#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
|
||||
#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
|
||||
#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
|
||||
#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
|
||||
#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
|
||||
#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
|
||||
#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
|
||||
#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
|
||||
#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
|
||||
#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
|
||||
#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
|
||||
#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
|
||||
#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
|
||||
#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
|
||||
#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
|
||||
#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
|
||||
#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
|
||||
#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
|
||||
#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
|
||||
#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
|
||||
#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
|
||||
#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
|
||||
#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
|
||||
#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
|
||||
#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
|
||||
#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
|
||||
#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
|
||||
#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
|
||||
#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
|
||||
#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
|
||||
#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
|
||||
#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
|
||||
#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
|
||||
#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
|
||||
#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
|
||||
#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
|
||||
#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
|
||||
#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
|
||||
#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
|
||||
#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
|
||||
#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
|
||||
#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
|
||||
#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
|
||||
#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
|
||||
#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
|
||||
#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
|
||||
#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
|
||||
#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
|
||||
#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
|
||||
#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
|
||||
#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
|
||||
#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
|
||||
#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
|
||||
#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
|
||||
#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
|
||||
#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
|
||||
#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
|
||||
#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
|
||||
#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
|
||||
#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
|
||||
#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
|
||||
#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
|
||||
#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
|
||||
#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
|
||||
#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
|
||||
#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
|
||||
#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
|
||||
#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
|
||||
#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
|
||||
#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
|
||||
#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
|
||||
#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
|
||||
#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
|
||||
#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
|
||||
#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
|
||||
#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
|
||||
#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
|
||||
#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
|
||||
#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
|
||||
#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
|
||||
#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
|
||||
#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
|
||||
#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
|
||||
#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
|
||||
#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
|
||||
#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
|
||||
#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
|
||||
#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
|
||||
#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
|
||||
#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
|
||||
#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
|
||||
#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
|
||||
#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
|
||||
#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
|
||||
#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
|
||||
#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
|
||||
#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
|
||||
#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
|
||||
#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
|
||||
#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
|
||||
#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
|
||||
#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
|
||||
#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
|
||||
#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
|
||||
#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
|
||||
#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
|
||||
#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
|
||||
#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
|
||||
#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
|
||||
#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
|
||||
#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
|
||||
#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
|
||||
#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
|
||||
#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
|
||||
#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
|
||||
#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
|
||||
#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
|
||||
#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
|
||||
#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
|
||||
#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
|
||||
#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
|
||||
#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
|
||||
#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
|
||||
#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
|
||||
#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
|
||||
#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
|
||||
#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
|
||||
#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
|
||||
#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
|
||||
#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
|
||||
#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
|
||||
#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
|
||||
#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
|
||||
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
|
||||
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
|
||||
|
||||
#if defined(STM32WB)
|
||||
#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
|
||||
#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
|
||||
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
|
||||
#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
|
||||
#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
|
||||
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
|
||||
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
|
||||
#define QSPI_IRQHandler QUADSPI_IRQHandler
|
||||
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
|
||||
|
||||
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
|
||||
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
|
||||
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
|
||||
#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
|
||||
#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
|
||||
#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
|
||||
#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
|
||||
#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
|
||||
#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
|
||||
#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
|
||||
#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
|
||||
#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
|
||||
#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
|
||||
#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
|
||||
#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
|
||||
#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
|
||||
#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
|
||||
#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
|
||||
#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
|
||||
#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
|
||||
#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
|
||||
#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
|
||||
#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
|
||||
#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
|
||||
#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
|
||||
#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
|
||||
#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
|
||||
#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
|
||||
#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
|
||||
#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
|
||||
#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
|
||||
#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
|
||||
#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
|
||||
#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
|
||||
#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
|
||||
#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
|
||||
#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
|
||||
#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
|
||||
#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
|
||||
#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
|
||||
#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
|
||||
#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
|
||||
#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
|
||||
#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
|
||||
#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
|
||||
#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
|
||||
#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
|
||||
#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
|
||||
#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
|
||||
#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
|
||||
#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
|
||||
#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
|
||||
#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
|
||||
#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
|
||||
#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
|
||||
#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
|
||||
#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
|
||||
#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
|
||||
#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
|
||||
#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
|
||||
#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
|
||||
#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
|
||||
#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
|
||||
#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
|
||||
#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
|
||||
#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
|
||||
#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
|
||||
#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
|
||||
#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
|
||||
#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
|
||||
#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
|
||||
#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
|
||||
#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
|
||||
#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
|
||||
#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
|
||||
#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
|
||||
#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
|
||||
#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
|
||||
#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
|
||||
#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
|
||||
#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
|
||||
#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
|
||||
#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
|
||||
#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
|
||||
#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
|
||||
#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
|
||||
#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
|
||||
#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
|
||||
#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
|
||||
#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
|
||||
#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
|
||||
#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
|
||||
#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
|
||||
#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
|
||||
#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
|
||||
#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
|
||||
#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
|
||||
#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
|
||||
#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
|
||||
#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
|
||||
#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
|
||||
#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
|
||||
#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
|
||||
#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
|
||||
#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
|
||||
#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
|
||||
#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
|
||||
#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
|
||||
#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
|
||||
#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
|
||||
#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
|
||||
#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
|
||||
#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
|
||||
#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
|
||||
#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
|
||||
#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
|
||||
#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
|
||||
#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
|
||||
#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
|
||||
#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
|
||||
#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
|
||||
#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
|
||||
#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
|
||||
#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
|
||||
#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
|
||||
#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
|
||||
#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
|
||||
#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
|
||||
#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
|
||||
#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
|
||||
#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
|
||||
#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
|
||||
#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
|
||||
#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
|
||||
#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
|
||||
#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
|
||||
#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
|
||||
#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
|
||||
#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
|
||||
#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
|
||||
#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
|
||||
#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
|
||||
#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
|
||||
#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
|
||||
#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
|
||||
#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
|
||||
#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
|
||||
#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
|
||||
#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
|
||||
#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
|
||||
#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
|
||||
#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
|
||||
#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
|
||||
#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
|
||||
#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
|
||||
#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
|
||||
#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
|
||||
#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
|
||||
#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
|
||||
#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
|
||||
#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
|
||||
#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
|
||||
#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
|
||||
#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
|
||||
#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
|
||||
#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
|
||||
#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
|
||||
#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
|
||||
#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
|
||||
#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
|
||||
#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
|
||||
#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
|
||||
#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
|
||||
#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
|
||||
#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
|
||||
#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
|
||||
#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
|
||||
#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
|
||||
#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
|
||||
#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
|
||||
#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
|
||||
#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
|
||||
#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
|
||||
#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
|
||||
#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
|
||||
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
|
||||
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
|
||||
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
|
||||
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
|
||||
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
|
||||
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
|
||||
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
|
||||
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
|
||||
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
|
||||
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
|
||||
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
|
||||
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
|
||||
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
|
||||
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
|
||||
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
|
||||
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
|
||||
#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
|
||||
#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
|
||||
#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
|
||||
#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
|
||||
#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
|
||||
#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
|
||||
#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
|
||||
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
|
||||
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
|
||||
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
|
||||
#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
|
||||
#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
|
||||
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
|
||||
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
|
||||
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
|
||||
#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
|
||||
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
|
||||
|
||||
#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
|
||||
#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
|
||||
|
||||
|
||||
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
|
||||
#endif
|
||||
|
||||
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
|
||||
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
|
||||
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
|
||||
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
|
||||
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
|
||||
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
|
||||
|
||||
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
|
||||
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
|
||||
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
|
||||
#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
|
||||
#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
|
||||
#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
|
||||
#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
|
||||
#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
|
||||
#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
|
||||
#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
|
||||
#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
|
||||
#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
|
||||
#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
|
||||
#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
|
||||
#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
|
||||
#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
|
||||
#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
|
||||
#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
|
||||
#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
|
||||
#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
|
||||
|
||||
#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
|
||||
#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
|
||||
#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
|
||||
#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
|
||||
#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
|
||||
#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
|
||||
#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
|
||||
#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
|
||||
#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
|
||||
#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
|
||||
#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
|
||||
#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
|
||||
#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
|
||||
#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
|
||||
#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
|
||||
#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
|
||||
#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
|
||||
#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
|
||||
#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
|
||||
#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
|
||||
#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
|
||||
#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
|
||||
#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
|
||||
#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
|
||||
#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
|
||||
#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
|
||||
#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
|
||||
#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
|
||||
#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
|
||||
#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
|
||||
#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
|
||||
#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
|
||||
#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
|
||||
#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
|
||||
#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
|
||||
#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
|
||||
#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
|
||||
#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
|
||||
#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
|
||||
#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
|
||||
#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
|
||||
#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
|
||||
#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
|
||||
#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
|
||||
#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
|
||||
#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
|
||||
#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
|
||||
#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
|
||||
#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
|
||||
#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
|
||||
#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
|
||||
#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
|
||||
#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
|
||||
#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
|
||||
#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
|
||||
#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
|
||||
#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
|
||||
#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
|
||||
#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
|
||||
#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
|
||||
#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
|
||||
#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
|
||||
#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
|
||||
#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
|
||||
#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
|
||||
#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
|
||||
#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
|
||||
#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
|
||||
#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
|
||||
#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
|
||||
#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
|
||||
#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
|
||||
#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
|
||||
#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
|
||||
#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
|
||||
#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
|
||||
#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
|
||||
#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
|
||||
#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
|
||||
#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
|
||||
#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
|
||||
#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
|
||||
#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
|
||||
#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
|
||||
#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
|
||||
#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
|
||||
#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
|
||||
#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
|
||||
#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
|
||||
#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
|
||||
#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
|
||||
#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
|
||||
#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
|
||||
#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
|
||||
#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
|
||||
#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
|
||||
#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
|
||||
#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
|
||||
#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
|
||||
#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
|
||||
#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
|
||||
#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
|
||||
#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
|
||||
#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
|
||||
#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
|
||||
#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
|
||||
#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
|
||||
#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
|
||||
#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
|
||||
#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
|
||||
#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
|
||||
#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
|
||||
#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
|
||||
#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
|
||||
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
|
||||
#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
|
||||
#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
|
||||
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
|
||||
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
|
||||
#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
|
||||
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
|
||||
#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
|
||||
#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
|
||||
#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
|
||||
#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
|
||||
#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
|
||||
#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
|
||||
#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
|
||||
#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
|
||||
#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
|
||||
#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
|
||||
#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
|
||||
#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
|
||||
#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
|
||||
#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
|
||||
#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
|
||||
#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
|
||||
#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
|
||||
#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
|
||||
#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
|
||||
#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
|
||||
#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
|
||||
|
||||
/* alias define maintained for legacy */
|
||||
#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
|
||||
#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
|
||||
|
||||
#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
|
||||
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
|
||||
#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
|
||||
#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
|
||||
#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
|
||||
#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
|
||||
#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
|
||||
#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
|
||||
#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
|
||||
#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
|
||||
#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
|
||||
#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
|
||||
#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
|
||||
#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
|
||||
#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
|
||||
#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
|
||||
#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
|
||||
#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
|
||||
#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
|
||||
#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
|
||||
|
||||
#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
|
||||
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
|
||||
#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
|
||||
#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
|
||||
#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
|
||||
#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
|
||||
#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
|
||||
#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
|
||||
#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
|
||||
#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
|
||||
#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
|
||||
#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
|
||||
#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
|
||||
#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
|
||||
#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
|
||||
#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
|
||||
#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
|
||||
#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
|
||||
#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
|
||||
#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
|
||||
|
||||
#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
|
||||
#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
|
||||
#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
|
||||
#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
|
||||
#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
|
||||
#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
|
||||
#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
|
||||
#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
|
||||
#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
|
||||
#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
|
||||
#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
|
||||
#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
|
||||
#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
|
||||
#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
|
||||
#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
|
||||
#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
|
||||
#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
|
||||
#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
|
||||
#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
|
||||
#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
|
||||
#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
|
||||
#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
|
||||
#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
|
||||
#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
|
||||
#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
|
||||
#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
|
||||
#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
|
||||
#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
|
||||
#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
|
||||
#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
|
||||
#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
|
||||
#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
|
||||
#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
|
||||
#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
|
||||
#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
|
||||
#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
|
||||
#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
|
||||
#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
|
||||
#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
|
||||
#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
|
||||
#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
|
||||
#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
|
||||
#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
|
||||
#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
|
||||
#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
|
||||
#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
|
||||
#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
|
||||
#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
|
||||
#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
|
||||
#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
|
||||
#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
|
||||
#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
|
||||
#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
|
||||
#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
|
||||
#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
|
||||
#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
|
||||
#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
|
||||
#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
|
||||
#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
|
||||
#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
|
||||
#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
|
||||
#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
|
||||
#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
|
||||
#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
|
||||
#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
|
||||
#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
|
||||
#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
|
||||
#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
|
||||
#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
|
||||
#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
|
||||
#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
|
||||
#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
|
||||
#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
|
||||
#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
|
||||
#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
|
||||
#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
|
||||
#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
|
||||
#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
|
||||
#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
|
||||
#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
|
||||
#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
|
||||
#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
|
||||
#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
|
||||
#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
|
||||
#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
|
||||
#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
|
||||
#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
|
||||
#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
|
||||
#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
|
||||
#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
|
||||
#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
|
||||
#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
|
||||
#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
|
||||
#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
|
||||
#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
|
||||
#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
|
||||
#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
|
||||
#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
|
||||
#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
|
||||
#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
|
||||
#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
|
||||
#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
|
||||
#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
|
||||
#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
|
||||
#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
|
||||
#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
|
||||
#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
|
||||
#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
|
||||
#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
|
||||
#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
|
||||
#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
|
||||
#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
|
||||
#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
|
||||
#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
|
||||
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
|
||||
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
|
||||
|
||||
#if defined(STM32L1)
|
||||
#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
|
||||
#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
|
||||
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
|
||||
#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
|
||||
#endif /* STM32L1 */
|
||||
|
||||
#if defined(STM32F4)
|
||||
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
|
||||
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
|
||||
#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
|
||||
#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
|
||||
#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
|
||||
#define Sdmmc1ClockSelection SdioClockSelection
|
||||
#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
|
||||
#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
|
||||
#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
|
||||
#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
|
||||
#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7) || defined(STM32L4)
|
||||
#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
|
||||
#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
|
||||
#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
|
||||
#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
|
||||
#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
|
||||
#define SdioClockSelection Sdmmc1ClockSelection
|
||||
#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
|
||||
#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
|
||||
#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
|
||||
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
|
||||
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
|
||||
#endif
|
||||
|
||||
#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
|
||||
#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
|
||||
|
||||
#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
|
||||
|
||||
#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
|
||||
#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
|
||||
#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
|
||||
#define IS_RCC_HCLK_DIV IS_RCC_PCLK
|
||||
#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
|
||||
|
||||
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
|
||||
|
||||
#define RCC_IT_CSSLSE RCC_IT_LSECSS
|
||||
#define RCC_IT_CSSHSE RCC_IT_CSS
|
||||
|
||||
#define RCC_PLLMUL_3 RCC_PLL_MUL3
|
||||
#define RCC_PLLMUL_4 RCC_PLL_MUL4
|
||||
#define RCC_PLLMUL_6 RCC_PLL_MUL6
|
||||
#define RCC_PLLMUL_8 RCC_PLL_MUL8
|
||||
#define RCC_PLLMUL_12 RCC_PLL_MUL12
|
||||
#define RCC_PLLMUL_16 RCC_PLL_MUL16
|
||||
#define RCC_PLLMUL_24 RCC_PLL_MUL24
|
||||
#define RCC_PLLMUL_32 RCC_PLL_MUL32
|
||||
#define RCC_PLLMUL_48 RCC_PLL_MUL48
|
||||
|
||||
#define RCC_PLLDIV_2 RCC_PLL_DIV2
|
||||
#define RCC_PLLDIV_3 RCC_PLL_DIV3
|
||||
#define RCC_PLLDIV_4 RCC_PLL_DIV4
|
||||
|
||||
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
|
||||
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
|
||||
#define RCC_MCO_NODIV RCC_MCODIV_1
|
||||
#define RCC_MCO_DIV1 RCC_MCODIV_1
|
||||
#define RCC_MCO_DIV2 RCC_MCODIV_2
|
||||
#define RCC_MCO_DIV4 RCC_MCODIV_4
|
||||
#define RCC_MCO_DIV8 RCC_MCODIV_8
|
||||
#define RCC_MCO_DIV16 RCC_MCODIV_16
|
||||
#define RCC_MCO_DIV32 RCC_MCODIV_32
|
||||
#define RCC_MCO_DIV64 RCC_MCODIV_64
|
||||
#define RCC_MCO_DIV128 RCC_MCODIV_128
|
||||
#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
|
||||
#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
|
||||
#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
|
||||
#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
|
||||
#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
|
||||
#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
|
||||
#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
|
||||
#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
#endif
|
||||
|
||||
#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
|
||||
#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
|
||||
#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
|
||||
#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
|
||||
#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
|
||||
#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
|
||||
#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
|
||||
#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
|
||||
|
||||
#define HSION_BitNumber RCC_HSION_BIT_NUMBER
|
||||
#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
|
||||
#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
|
||||
#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
|
||||
#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
|
||||
#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
|
||||
#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
|
||||
#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
|
||||
#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
|
||||
#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
|
||||
#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
|
||||
#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
|
||||
#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
|
||||
#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
|
||||
#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
|
||||
#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
|
||||
#define LSION_BitNumber RCC_LSION_BIT_NUMBER
|
||||
#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
|
||||
#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
|
||||
#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
|
||||
#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
|
||||
#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
|
||||
#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
|
||||
#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
|
||||
#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
|
||||
#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
|
||||
#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
|
||||
#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
|
||||
#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
|
||||
#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
|
||||
#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
|
||||
#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
|
||||
|
||||
#define CR_HSION_BB RCC_CR_HSION_BB
|
||||
#define CR_CSSON_BB RCC_CR_CSSON_BB
|
||||
#define CR_PLLON_BB RCC_CR_PLLON_BB
|
||||
#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
|
||||
#define CR_MSION_BB RCC_CR_MSION_BB
|
||||
#define CSR_LSION_BB RCC_CSR_LSION_BB
|
||||
#define CSR_LSEON_BB RCC_CSR_LSEON_BB
|
||||
#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
|
||||
#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
|
||||
#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
|
||||
#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
|
||||
#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
|
||||
#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
|
||||
#define CR_HSEON_BB RCC_CR_HSEON_BB
|
||||
#define CSR_RMVF_BB RCC_CSR_RMVF_BB
|
||||
#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
|
||||
#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
|
||||
|
||||
#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
|
||||
#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
|
||||
#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
|
||||
#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
|
||||
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
|
||||
|
||||
#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
|
||||
|
||||
#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
|
||||
#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
|
||||
|
||||
#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
|
||||
#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
|
||||
#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
|
||||
#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
|
||||
#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
|
||||
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
|
||||
|
||||
#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
|
||||
#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
|
||||
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
|
||||
#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
|
||||
#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
|
||||
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
|
||||
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
|
||||
#define DfsdmClockSelection Dfsdm1ClockSelection
|
||||
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
|
||||
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
|
||||
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
|
||||
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
|
||||
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
|
||||
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
|
||||
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
|
||||
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
|
||||
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
|
||||
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
|
||||
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
|
||||
|
||||
#if defined (STM32F1)
|
||||
#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
|
||||
|
||||
#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
|
||||
|
||||
#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
|
||||
|
||||
#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
|
||||
|
||||
#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
|
||||
#else
|
||||
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
|
||||
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
|
||||
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
|
||||
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
|
||||
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
#endif /* STM32F1 */
|
||||
|
||||
#define IS_ALARM IS_RTC_ALARM
|
||||
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
|
||||
#define IS_TAMPER IS_RTC_TAMPER
|
||||
#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
|
||||
#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
|
||||
#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
|
||||
#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
|
||||
#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
|
||||
#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
|
||||
#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
|
||||
#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
|
||||
#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
|
||||
#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
|
||||
#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
|
||||
|
||||
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
|
||||
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
|
||||
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
|
||||
|
||||
#if defined(STM32F4) || defined(STM32F2)
|
||||
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
|
||||
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
|
||||
#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
|
||||
#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
|
||||
#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
|
||||
#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
|
||||
#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
|
||||
#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
|
||||
#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
|
||||
#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
|
||||
#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
|
||||
#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
|
||||
#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
|
||||
#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
|
||||
#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
|
||||
#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
|
||||
#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
|
||||
#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
|
||||
#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
|
||||
#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
|
||||
/* alias CMSIS */
|
||||
#define SDMMC1_IRQn SDIO_IRQn
|
||||
#define SDMMC1_IRQHandler SDIO_IRQHandler
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7) || defined(STM32L4)
|
||||
#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
|
||||
#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
|
||||
#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
|
||||
#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
|
||||
#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
|
||||
#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
|
||||
#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
|
||||
#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
|
||||
#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
|
||||
#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
|
||||
#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
|
||||
#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
|
||||
#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
|
||||
#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
|
||||
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
|
||||
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
|
||||
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
|
||||
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
|
||||
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
|
||||
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
|
||||
/* alias CMSIS for compatibilities */
|
||||
#define SDIO_IRQn SDMMC1_IRQn
|
||||
#define SDIO_IRQHandler SDMMC1_IRQHandler
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
|
||||
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
|
||||
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
|
||||
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
|
||||
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7) || defined(STM32L5)
|
||||
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
|
||||
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
|
||||
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
|
||||
#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
|
||||
#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
|
||||
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
|
||||
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
|
||||
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
|
||||
#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
|
||||
#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
|
||||
#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
|
||||
#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
|
||||
#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
|
||||
#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
|
||||
|
||||
#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
|
||||
#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
|
||||
|
||||
#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
|
||||
#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
|
||||
#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
|
||||
#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
|
||||
#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
|
||||
#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
|
||||
#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
|
||||
#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
|
||||
#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
|
||||
#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
|
||||
#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
|
||||
#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
|
||||
#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
|
||||
|
||||
#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
|
||||
|
||||
#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
|
||||
#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
|
||||
#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
|
||||
#define __USART_ENABLE __HAL_USART_ENABLE
|
||||
#define __USART_DISABLE __HAL_USART_DISABLE
|
||||
|
||||
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
|
||||
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
|
||||
|
||||
#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
|
||||
#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
|
||||
#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
|
||||
#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
|
||||
#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
|
||||
#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
|
||||
#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
|
||||
#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
|
||||
#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
|
||||
#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
|
||||
#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
|
||||
|
||||
#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
|
||||
#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
|
||||
#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
|
||||
#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
|
||||
#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
|
||||
#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
|
||||
|
||||
#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
|
||||
#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
|
||||
#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
|
||||
#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
|
||||
#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
|
||||
#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
|
||||
|
||||
#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
|
||||
#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
|
||||
|
||||
#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
|
||||
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
|
||||
#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
|
||||
|
||||
#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
|
||||
#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
|
||||
|
||||
#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
|
||||
|
||||
#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
|
||||
#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
|
||||
#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
|
||||
#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
|
||||
#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
|
||||
#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
|
||||
#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
|
||||
#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
|
||||
#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
|
||||
#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
|
||||
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
|
||||
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
|
||||
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
|
||||
#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
|
||||
#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
|
||||
#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
|
||||
#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
|
||||
#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
|
||||
#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
|
||||
|
||||
#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
|
||||
#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
|
||||
#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_LTDC_LAYER LTDC_LAYER
|
||||
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
|
||||
#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
|
||||
#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
|
||||
#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
|
||||
#define SAI_STREOMODE SAI_STEREOMODE
|
||||
#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
|
||||
#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
|
||||
#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
|
||||
#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
|
||||
#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
|
||||
#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
|
||||
#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
|
||||
#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
|
||||
#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32H7)
|
||||
#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
|
||||
#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
|
||||
#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
|
||||
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
|
||||
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
|
||||
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
|
||||
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
|
||||
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
|
||||
#endif /* STM32L4 || STM32F4 || STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32_HAL_LEGACY */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
358
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
Normal file
358
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
Normal file
@@ -0,0 +1,358 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_H
|
||||
#define __STM32F1xx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_conf.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TICK_FREQ_10HZ = 100U,
|
||||
HAL_TICK_FREQ_100HZ = 10U,
|
||||
HAL_TICK_FREQ_1KHZ = 1U,
|
||||
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
|
||||
} HAL_TickFreqTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
extern __IO uint32_t uwTick;
|
||||
extern uint32_t uwTickPrio;
|
||||
extern HAL_TickFreqTypeDef uwTickFreq;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
|
||||
* @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
* Note: On devices STM32F10xx8 and STM32F10xxB,
|
||||
* STM32F101xC/D/E and STM32F103xC/D/E,
|
||||
* STM32F101xF/G and STM32F103xF/G
|
||||
* STM32F10xx4 and STM32F10xx6
|
||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
|
||||
* debug mode (not accessible by the user software in normal mode).
|
||||
* Refer to errata sheet of these devices for more details.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripherals on APB1 */
|
||||
/**
|
||||
* @brief TIM2 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
|
||||
|
||||
/**
|
||||
* @brief TIM3 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM4_STOP)
|
||||
/**
|
||||
* @brief TIM4 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM5_STOP)
|
||||
/**
|
||||
* @brief TIM5 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM6_STOP)
|
||||
/**
|
||||
* @brief TIM6 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM7_STOP)
|
||||
/**
|
||||
* @brief TIM7 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM12_STOP)
|
||||
/**
|
||||
* @brief TIM12 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM13_STOP)
|
||||
/**
|
||||
* @brief TIM13 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM14_STOP)
|
||||
/**
|
||||
* @brief TIM14 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief WWDG Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
|
||||
|
||||
/**
|
||||
* @brief IWDG Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
|
||||
|
||||
/**
|
||||
* @brief I2C1 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
|
||||
/**
|
||||
* @brief I2C2 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_CAN1_STOP)
|
||||
/**
|
||||
* @brief CAN1 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_CAN2_STOP)
|
||||
/**
|
||||
* @brief CAN2 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
|
||||
#endif
|
||||
|
||||
/* Peripherals on APB2 */
|
||||
#if defined (DBGMCU_CR_DBG_TIM1_STOP)
|
||||
/**
|
||||
* @brief TIM1 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM8_STOP)
|
||||
/**
|
||||
* @brief TIM8 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM9_STOP)
|
||||
/**
|
||||
* @brief TIM9 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM10_STOP)
|
||||
/**
|
||||
* @brief TIM10 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM11_STOP)
|
||||
/**
|
||||
* @brief TIM11 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM15_STOP)
|
||||
/**
|
||||
* @brief TIM15 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM16_STOP)
|
||||
/**
|
||||
* @brief TIM16 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
|
||||
#endif
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM17_STOP)
|
||||
/**
|
||||
* @brief TIM17 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetTickPrio(void);
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
uint32_t HAL_GetUIDw0(void);
|
||||
uint32_t HAL_GetUIDw1(void);
|
||||
uint32_t HAL_GetUIDw2(void);
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Variables HAL Private Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
850
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h
Normal file
850
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h
Normal file
@@ -0,0 +1,850 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_can.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CAN HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_CAN_H
|
||||
#define STM32F1xx_HAL_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (CAN1)
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Types CAN Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
|
||||
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
|
||||
HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */
|
||||
HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */
|
||||
HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */
|
||||
HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */
|
||||
|
||||
} HAL_CAN_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of @ref CAN_operating_mode */
|
||||
|
||||
uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
|
||||
is allowed to lengthen or shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
} CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
|
||||
For single CAN instance(14 dedicated filter banks),
|
||||
this parameter must be a number between Min_Data = 0 and Max_Data = 13.
|
||||
For dual CAN instances(28 filter banks shared),
|
||||
this parameter must be a number between Min_Data = 0 and Max_Data = 27. */
|
||||
|
||||
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint32_t FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be a value of @ref CAN_filter_activation */
|
||||
|
||||
uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
|
||||
For single CAN instances, this parameter is meaningless.
|
||||
For dual CAN instances, all filter banks with lower index are assigned to master
|
||||
CAN instance, whereas all filter banks with greater index are assigned to slave
|
||||
CAN instance.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
|
||||
|
||||
} CAN_FilterTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message header structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_identifier_type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
|
||||
|
||||
FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
|
||||
of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
|
||||
@note: Time Triggered Communication Mode must be enabled.
|
||||
@note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
} CAN_TxHeaderTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message header structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_identifier_type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
|
||||
|
||||
uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
|
||||
@note: Time Triggered Communication Mode must be enabled.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
|
||||
|
||||
} CAN_RxHeaderTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN handle Structure definition
|
||||
*/
|
||||
typedef struct __CAN_HandleTypeDef
|
||||
{
|
||||
CAN_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CAN_InitTypeDef Init; /*!< CAN required parameters */
|
||||
|
||||
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CAN Error code.
|
||||
This parameter can be a value of @ref CAN_Error_Code */
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */
|
||||
void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */
|
||||
void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */
|
||||
void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */
|
||||
void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */
|
||||
void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */
|
||||
void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */
|
||||
void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */
|
||||
void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */
|
||||
void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */
|
||||
void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */
|
||||
void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */
|
||||
void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
|
||||
} CAN_HandleTypeDef;
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
/**
|
||||
* @brief HAL CAN common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */
|
||||
HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */
|
||||
HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */
|
||||
HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */
|
||||
HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */
|
||||
HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */
|
||||
HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */
|
||||
HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */
|
||||
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
|
||||
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
|
||||
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
|
||||
HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */
|
||||
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
|
||||
|
||||
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
|
||||
HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */
|
||||
|
||||
} HAL_CAN_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CAN Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */
|
||||
|
||||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants CAN Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Error_Code CAN Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
|
||||
#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
|
||||
#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
|
||||
#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
|
||||
#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
|
||||
#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
|
||||
#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
|
||||
#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
|
||||
#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
|
||||
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
|
||||
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
|
||||
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
|
||||
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
|
||||
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
|
||||
#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
|
||||
#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_InitStatus CAN InitStatus
|
||||
* @{
|
||||
*/
|
||||
#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
|
||||
#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_operating_mode CAN Operating Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
|
||||
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
|
||||
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
|
||||
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode CAN Filter Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */
|
||||
#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale CAN Filter Scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */
|
||||
#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_activation CAN Filter Activation
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */
|
||||
#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type CAN Identifier Type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
|
||||
#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
|
||||
#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
|
||||
#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
|
||||
#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
|
||||
#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags CAN Flags
|
||||
* @{
|
||||
*/
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */
|
||||
#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */
|
||||
#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */
|
||||
#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */
|
||||
#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */
|
||||
#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */
|
||||
#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */
|
||||
#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */
|
||||
#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */
|
||||
#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */
|
||||
#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */
|
||||
#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */
|
||||
#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */
|
||||
#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */
|
||||
#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */
|
||||
#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */
|
||||
#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */
|
||||
#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */
|
||||
#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */
|
||||
#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
|
||||
#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
|
||||
#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
|
||||
#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */
|
||||
#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
|
||||
#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
|
||||
#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_Interrupts CAN Interrupts
|
||||
* @{
|
||||
*/
|
||||
/* Transmit Interrupt */
|
||||
#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
|
||||
#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
|
||||
#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
|
||||
#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
|
||||
#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
|
||||
#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
|
||||
#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
|
||||
#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
|
||||
#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
|
||||
#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
|
||||
#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Macros CAN Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CAN handle state
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_CAN_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
||||
#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the specified CAN interrupts.
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @param __INTERRUPT__ CAN Interrupt sources to enable.
|
||||
* This parameter can be any combination of @arg CAN_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified CAN interrupts.
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @param __INTERRUPT__ CAN Interrupt sources to disable.
|
||||
* This parameter can be any combination of @arg CAN_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __INTERRUPT__ specifies the CAN interrupt source to check.
|
||||
* This parameter can be a value of @arg CAN_Interrupts
|
||||
* @retval The state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified CAN flag is set or not.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of @arg CAN_flags
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
|
||||
|
||||
/** @brief Clear the specified CAN pending flag.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
|
||||
* @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
|
||||
* @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
|
||||
* @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
|
||||
* @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
|
||||
* @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
|
||||
* @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
|
||||
* @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
|
||||
* @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
|
||||
* @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKUI: Wake up Interrupt Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CAN_Exported_Functions CAN Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
|
||||
HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
|
||||
|
||||
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group3 Control functions
|
||||
* @brief Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Control functions **********************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
|
||||
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
|
||||
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
|
||||
uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
|
||||
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
|
||||
uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
|
||||
* @brief Interrupts management
|
||||
* @{
|
||||
*/
|
||||
/* Interrupts management ******************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
|
||||
HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
|
||||
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
|
||||
* @brief Callback functions
|
||||
* @{
|
||||
*/
|
||||
/* Callbacks functions ********************************************************/
|
||||
|
||||
void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
|
||||
* @brief CAN Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Types CAN Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Variables CAN Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Constants CAN Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FLAG_MASK (0x000000FFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros -----------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Macros CAN Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
|
||||
((MODE) == CAN_MODE_LOOPBACK)|| \
|
||||
((MODE) == CAN_MODE_SILENT) || \
|
||||
((MODE) == CAN_MODE_SILENT_LOOPBACK))
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
|
||||
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
|
||||
#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
|
||||
((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
|
||||
((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
|
||||
((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
|
||||
((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
|
||||
((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
|
||||
((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
|
||||
((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
|
||||
#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
|
||||
((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
|
||||
((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
|
||||
((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
|
||||
#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
|
||||
#if defined(CAN2)
|
||||
#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
|
||||
#endif
|
||||
#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
|
||||
((MODE) == CAN_FILTERMODE_IDLIST))
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
||||
((SCALE) == CAN_FILTERSCALE_32BIT))
|
||||
#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
|
||||
((ACTIVATION) == CAN_FILTER_ENABLE))
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
||||
((FIFO) == CAN_FILTER_FIFO1))
|
||||
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
|
||||
((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
|
||||
((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
|
||||
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
|
||||
((IDTYPE) == CAN_ID_EXT))
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
|
||||
#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
|
||||
#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \
|
||||
CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \
|
||||
CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \
|
||||
CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \
|
||||
CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \
|
||||
CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \
|
||||
CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macros -----------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* CAN1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_CAN_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
410
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
Normal file
410
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
Normal file
@@ -0,0 +1,410 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_CORTEX_H
|
||||
#define __STM32F1xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @brief MPU Region initialization structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
|
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
|
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
|
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
|
||||
}MPU_Region_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{
|
||||
*/
|
||||
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
|
||||
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
|
||||
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
|
||||
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
|
||||
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01)
|
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
|
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
|
||||
* @{
|
||||
*/
|
||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
|
||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
|
||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
|
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
|
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
|
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
|
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
|
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
|
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
|
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
|
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
|
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
|
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
|
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
|
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
|
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
|
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
|
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
|
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
|
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
|
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
|
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
|
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
|
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
|
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
|
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
|
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
|
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
|
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
|
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
|
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
|
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
|
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
|
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
|
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
|
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
|
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
|
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
|
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
|
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
|
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
|
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported Macros -----------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CORTEX_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
||||
((STATE) == MPU_REGION_DISABLE))
|
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
|
||||
|
||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
|
||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
||||
((TYPE) == MPU_TEX_LEVEL2))
|
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO))
|
||||
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7))
|
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB))
|
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
210
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
Normal file
210
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
Normal file
@@ -0,0 +1,210 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_DEF
|
||||
#define __STM32F1xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx.h"
|
||||
#include "Legacy/stm32_hal_legacy.h"
|
||||
#include <stddef.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00U,
|
||||
HAL_ERROR = 0x01U,
|
||||
HAL_BUSY = 0x02U,
|
||||
HAL_TIMEOUT = 0x03U
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00U,
|
||||
HAL_LOCKED = 0x01U
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U)
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0U)
|
||||
|
||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__ specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
|
||||
|
||||
#if (USE_RTOS == 1U)
|
||||
/* Reserved for future use */
|
||||
#error "USE_RTOS should be 0 in the current HAL release"
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0U)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0U)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler V5*/
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
/* ARM Compiler V4/V5 and V6
|
||||
--------------------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
||||
/* ARM V4/V5 and V6 & GNU Compiler
|
||||
-------------------------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32F1xx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
457
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
Normal file
457
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
Normal file
@@ -0,0 +1,457 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_DMA_H
|
||||
#define __STM32F1xx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
|
||||
}HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
|
||||
}HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Callback ID structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
|
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
|
||||
|
||||
}HAL_DMA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
|
||||
|
||||
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
|
||||
|
||||
uint32_t ChannelIndex; /*!< DMA Channel Index */
|
||||
|
||||
} DMA_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */
|
||||
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
|
||||
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
|
||||
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_mode DMA mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
|
||||
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
|
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
|
||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
|
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
|
||||
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
|
||||
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_GL1 0x00000001U
|
||||
#define DMA_FLAG_TC1 0x00000002U
|
||||
#define DMA_FLAG_HT1 0x00000004U
|
||||
#define DMA_FLAG_TE1 0x00000008U
|
||||
#define DMA_FLAG_GL2 0x00000010U
|
||||
#define DMA_FLAG_TC2 0x00000020U
|
||||
#define DMA_FLAG_HT2 0x00000040U
|
||||
#define DMA_FLAG_TE2 0x00000080U
|
||||
#define DMA_FLAG_GL3 0x00000100U
|
||||
#define DMA_FLAG_TC3 0x00000200U
|
||||
#define DMA_FLAG_HT3 0x00000400U
|
||||
#define DMA_FLAG_TE3 0x00000800U
|
||||
#define DMA_FLAG_GL4 0x00001000U
|
||||
#define DMA_FLAG_TC4 0x00002000U
|
||||
#define DMA_FLAG_HT4 0x00004000U
|
||||
#define DMA_FLAG_TE4 0x00008000U
|
||||
#define DMA_FLAG_GL5 0x00010000U
|
||||
#define DMA_FLAG_TC5 0x00020000U
|
||||
#define DMA_FLAG_HT5 0x00040000U
|
||||
#define DMA_FLAG_TE5 0x00080000U
|
||||
#define DMA_FLAG_GL6 0x00100000U
|
||||
#define DMA_FLAG_TC6 0x00200000U
|
||||
#define DMA_FLAG_HT6 0x00400000U
|
||||
#define DMA_FLAG_TE6 0x00800000U
|
||||
#define DMA_FLAG_GL7 0x01000000U
|
||||
#define DMA_FLAG_TC7 0x02000000U
|
||||
#define DMA_FLAG_HT7 0x04000000U
|
||||
#define DMA_FLAG_TE7 0x08000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DMA handle state.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
|
||||
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Enables the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DMA Channel interrupt is enabled or not.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval The state of DMA_IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Return the number of remaining data units in the current DMA Channel transfer.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The number of remaining data units in the current DMA Channel transfer.
|
||||
*/
|
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32f1xx_hal_dma_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DMA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||
((STATE) == DMA_PINC_DISABLE))
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||
((STATE) == DMA_MINC_DISABLE))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||
((MODE) == DMA_CIRCULAR))
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
277
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
Normal file
277
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
Normal file
@@ -0,0 +1,277 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_DMA_EX_H
|
||||
#define __STM32F1xx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/* Interrupt & Flag management */
|
||||
#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
|
||||
defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||
/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||||
DMA_FLAG_TC5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||||
DMA_FLAG_HT5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||||
DMA_FLAG_TE5)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
|
||||
DMA_FLAG_GL5)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
|
||||
(DMA1->ISR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
|
||||
(DMA1->IFCR = (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#else
|
||||
/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
DMA_FLAG_TC7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
DMA_FLAG_HT7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
DMA_FLAG_TE7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
|
||||
DMA_FLAG_GL7)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* @arg DMA_FLAG_GLx: Global interrupt flag
|
||||
* Where x can be 1_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the DMA Channel pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* @arg DMA_FLAG_GLx: Global interrupt flag
|
||||
* Where x can be 1_7 to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
|
||||
/* STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
|
||||
#endif /* __STM32F1xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
320
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
Normal file
320
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
Normal file
@@ -0,0 +1,320 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_exti.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of EXTI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_EXTI_H
|
||||
#define STM32F1xx_HAL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL EXTI common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_EXTI_COMMON_CB_ID = 0x00U
|
||||
} EXTI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Handle structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< Exti line number */
|
||||
void (* PendingCallback)(void); /*!< Exti pending callback */
|
||||
} EXTI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */
|
||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */
|
||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */
|
||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It
|
||||
can be a value of @ref EXTI_GPIOSel */
|
||||
} EXTI_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
|
||||
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
|
||||
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
|
||||
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
|
||||
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
|
||||
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
|
||||
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
|
||||
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
|
||||
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
|
||||
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
|
||||
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
|
||||
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
|
||||
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
|
||||
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
|
||||
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
|
||||
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
|
||||
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#if defined(EXTI_IMR_IM18)
|
||||
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */
|
||||
#endif /* EXTI_IMR_IM18 */
|
||||
#if defined(EXTI_IMR_IM19)
|
||||
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||
#endif /* EXTI_IMR_IM19 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_MODE_NONE 0x00000000u
|
||||
#define EXTI_MODE_INTERRUPT 0x00000001u
|
||||
#define EXTI_MODE_EVENT 0x00000002u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_TRIGGER_NONE 0x00000000u
|
||||
#define EXTI_TRIGGER_RISING 0x00000001u
|
||||
#define EXTI_TRIGGER_FALLING 0x00000002u
|
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_GPIOA 0x00000000u
|
||||
#define EXTI_GPIOB 0x00000001u
|
||||
#define EXTI_GPIOC 0x00000002u
|
||||
#define EXTI_GPIOD 0x00000003u
|
||||
#if defined (GPIOE)
|
||||
#define EXTI_GPIOE 0x00000004u
|
||||
#endif /* GPIOE */
|
||||
#if defined (GPIOF)
|
||||
#define EXTI_GPIOF 0x00000005u
|
||||
#endif /* GPIOF */
|
||||
#if defined (GPIOG)
|
||||
#define EXTI_GPIOG 0x00000006u
|
||||
#endif /* GPIOG */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI Line property definition
|
||||
*/
|
||||
#define EXTI_PROPERTY_SHIFT 24u
|
||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
||||
#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
|
||||
|
||||
/**
|
||||
* @brief EXTI bit usage
|
||||
*/
|
||||
#define EXTI_PIN_MASK 0x0000001Fu
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for interrupt & event mode
|
||||
*/
|
||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for trigger possibilities
|
||||
*/
|
||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
|
||||
/**
|
||||
* @brief EXTI Line number
|
||||
*/
|
||||
#if defined(EXTI_IMR_IM19)
|
||||
#define EXTI_LINE_NB 20UL
|
||||
#elif defined(EXTI_IMR_IM18)
|
||||
#define EXTI_LINE_NB 19UL
|
||||
#else /* EXTI_IMR_IM17 */
|
||||
#define EXTI_LINE_NB 18UL
|
||||
#endif /* EXTI_IMR_IM19 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
|
||||
|
||||
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
|
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
|
||||
|
||||
#if defined (GPIOG)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF) || \
|
||||
((__PORT__) == EXTI_GPIOG))
|
||||
#elif defined (GPIOF)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF))
|
||||
#elif defined (GPIOE)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE))
|
||||
#else
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD))
|
||||
#endif /* GPIOG */
|
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||
* @brief EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_EXTI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
328
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
Normal file
328
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
Normal file
@@ -0,0 +1,328 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of Flash HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_FLASH_H
|
||||
#define __STM32F1xx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
|
||||
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
|
||||
((__LATENCY__) == FLASH_LATENCY_1) || \
|
||||
((__LATENCY__) == FLASH_LATENCY_2))
|
||||
|
||||
#else
|
||||
#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PROC_NONE = 0U,
|
||||
FLASH_PROC_PAGEERASE = 1U,
|
||||
FLASH_PROC_MASSERASE = 2U,
|
||||
FLASH_PROC_PROGRAMHALFWORD = 3U,
|
||||
FLASH_PROC_PROGRAMWORD = 4U,
|
||||
FLASH_PROC_PROGRAMDOUBLEWORD = 5U
|
||||
} FLASH_ProcedureTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
|
||||
|
||||
__IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
|
||||
|
||||
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
|
||||
|
||||
__IO uint64_t Data; /*!< Internal variable to save data to be programmed */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< FLASH locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< FLASH error code
|
||||
This parameter can be a value of @ref FLASH_Error_Codes */
|
||||
} FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error_Codes FLASH Error Codes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
|
||||
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
|
||||
#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!<Program a half-word (16-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAM_WORD 0x02U /*!<Program a word (32-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
|
||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#else
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
|
||||
* @brief macros to handle FLASH half cycle
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH half cycle access.
|
||||
* @note half cycle access can only be used with a low-frequency clock of less than
|
||||
8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH half cycle access.
|
||||
* @note half cycle access can only be used with a low-frequency clock of less than
|
||||
8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
/** @defgroup FLASH_EM_Latency FLASH Latency
|
||||
* @brief macros to handle FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__ FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
/** @defgroup FLASH_Prefetch FLASH Prefetch
|
||||
* @brief macros to handle FLASH Prefetch buffer
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extended module */
|
||||
#include "stm32f1xx_hal_flash_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
|
||||
/* FLASH IRQ handler function */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
void HAL_FLASH_OB_Launch(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function -------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
#if defined(FLASH_BANK2_END)
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
|
||||
#endif /* FLASH_BANK2_END */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_FLASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
786
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
Normal file
786
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
Normal file
@@ -0,0 +1,786 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of Flash HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_FLASH_EX_H
|
||||
#define __STM32F1xx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
|
||||
#define OBR_REG_INDEX 1U
|
||||
#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
|
||||
|
||||
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
|
||||
|
||||
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
|
||||
|
||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
|
||||
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
|
||||
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
#if defined(FLASH_BANK2_END)
|
||||
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
|
||||
#endif /* FLASH_BANK2_END */
|
||||
|
||||
/* Low Density */
|
||||
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
|
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU))
|
||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
|
||||
|
||||
/* Medium Density */
|
||||
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
|
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
|
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
|
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU))))
|
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
|
||||
|
||||
/* High Density */
|
||||
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
|
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \
|
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))
|
||||
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
|
||||
|
||||
/* XL Density */
|
||||
#if defined(FLASH_BANK2_END)
|
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU))
|
||||
#endif /* FLASH_BANK2_END */
|
||||
|
||||
/* Connectivity Line */
|
||||
#if (defined(STM32F105xC) || defined(STM32F107xC))
|
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \
|
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU)))
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
|
||||
|
||||
#if defined(FLASH_BANK2_END)
|
||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
|
||||
((BANK) == FLASH_BANK_2) || \
|
||||
((BANK) == FLASH_BANK_BOTH))
|
||||
#else
|
||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
|
||||
#endif /* FLASH_BANK2_END */
|
||||
|
||||
/* Low Density */
|
||||
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
|
||||
((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
|
||||
|
||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
|
||||
|
||||
/* Medium Density */
|
||||
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
|
||||
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
|
||||
((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
|
||||
((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))
|
||||
|
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
|
||||
|
||||
/* High Density */
|
||||
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \
|
||||
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \
|
||||
((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
|
||||
|
||||
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
|
||||
|
||||
/* XL Density */
|
||||
#if defined(FLASH_BANK2_END)
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \
|
||||
((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
|
||||
|
||||
#endif /* FLASH_BANK2_END */
|
||||
|
||||
/* Connectivity Line */
|
||||
#if (defined(STM32F105xC) || defined(STM32F107xC))
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
|
||||
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
|
||||
((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
|
||||
This parameter can be a value of @ref FLASHEx_Type_Erase */
|
||||
|
||||
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
|
||||
This parameter must be a value of @ref FLASHEx_Banks */
|
||||
|
||||
uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
|
||||
This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
|
||||
(x = 1 or 2 depending on devices)*/
|
||||
|
||||
uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
|
||||
This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
|
||||
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Options bytes program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASHEx_OB_Type */
|
||||
|
||||
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASHEx_OB_WRP_State */
|
||||
|
||||
uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
|
||||
This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
|
||||
|
||||
uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
|
||||
This parameter must be a value of @ref FLASHEx_Banks */
|
||||
|
||||
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
|
||||
This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
|
||||
|
||||
#if defined(FLASH_BANK2_END)
|
||||
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
|
||||
IWDG / STOP / STDBY / BOOT1
|
||||
This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
|
||||
@ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
|
||||
#else
|
||||
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
|
||||
IWDG / STOP / STDBY
|
||||
This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
|
||||
@ref FLASHEx_OB_nRST_STDBY */
|
||||
#endif /* FLASH_BANK2_END */
|
||||
|
||||
uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
|
||||
This parameter can be a value of @ref FLASHEx_OB_Data_Address */
|
||||
|
||||
uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Constants FLASH Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Page_Size Page Size
|
||||
* @{
|
||||
*/
|
||||
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
|
||||
#define FLASH_PAGE_SIZE 0x400U
|
||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
|
||||
/* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
|
||||
|
||||
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
|
||||
#define FLASH_PAGE_SIZE 0x800U
|
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
|
||||
/* STM32F101xG || STM32F103xG */
|
||||
/* STM32F105xC || STM32F107xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Type_Erase Type Erase
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/
|
||||
#define FLASH_TYPEERASE_MASSERASE 0x02U /*!<Flash mass erase activation*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Banks Banks
|
||||
* @{
|
||||
*/
|
||||
#if defined(FLASH_BANK2_END)
|
||||
#define FLASH_BANK_1 1U /*!< Bank 1 */
|
||||
#define FLASH_BANK_2 2U /*!< Bank 2 */
|
||||
#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
|
||||
|
||||
#else
|
||||
#define FLASH_BANK_1 1U /*!< Bank 1 */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Type Option Bytes Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP 0x01U /*!<WRP option byte configuration*/
|
||||
#define OPTIONBYTE_RDP 0x02U /*!<RDP option byte configuration*/
|
||||
#define OPTIONBYTE_USER 0x04U /*!<USER option byte configuration*/
|
||||
#define OPTIONBYTE_DATA 0x08U /*!<DATA option byte configuration*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPSTATE_DISABLE 0x00U /*!<Disable the write protection of the desired pages*/
|
||||
#define OB_WRPSTATE_ENABLE 0x01U /*!<Enable the write protection of the desired pagess*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
|
||||
* @{
|
||||
*/
|
||||
/* STM32 Low and Medium density devices */
|
||||
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \
|
||||
|| defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
|
||||
|| defined(STM32F103xB)
|
||||
#define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */
|
||||
#define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */
|
||||
#define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */
|
||||
#define OB_WRP_PAGES12TO15 0x00000008U /*!< Write protection of page 12 to 15 */
|
||||
#define OB_WRP_PAGES16TO19 0x00000010U /*!< Write protection of page 16 to 19 */
|
||||
#define OB_WRP_PAGES20TO23 0x00000020U /*!< Write protection of page 20 to 23 */
|
||||
#define OB_WRP_PAGES24TO27 0x00000040U /*!< Write protection of page 24 to 27 */
|
||||
#define OB_WRP_PAGES28TO31 0x00000080U /*!< Write protection of page 28 to 31 */
|
||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
|
||||
/* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
|
||||
|
||||
/* STM32 Medium-density devices */
|
||||
#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
|
||||
#define OB_WRP_PAGES32TO35 0x00000100U /*!< Write protection of page 32 to 35 */
|
||||
#define OB_WRP_PAGES36TO39 0x00000200U /*!< Write protection of page 36 to 39 */
|
||||
#define OB_WRP_PAGES40TO43 0x00000400U /*!< Write protection of page 40 to 43 */
|
||||
#define OB_WRP_PAGES44TO47 0x00000800U /*!< Write protection of page 44 to 47 */
|
||||
#define OB_WRP_PAGES48TO51 0x00001000U /*!< Write protection of page 48 to 51 */
|
||||
#define OB_WRP_PAGES52TO55 0x00002000U /*!< Write protection of page 52 to 55 */
|
||||
#define OB_WRP_PAGES56TO59 0x00004000U /*!< Write protection of page 56 to 59 */
|
||||
#define OB_WRP_PAGES60TO63 0x00008000U /*!< Write protection of page 60 to 63 */
|
||||
#define OB_WRP_PAGES64TO67 0x00010000U /*!< Write protection of page 64 to 67 */
|
||||
#define OB_WRP_PAGES68TO71 0x00020000U /*!< Write protection of page 68 to 71 */
|
||||
#define OB_WRP_PAGES72TO75 0x00040000U /*!< Write protection of page 72 to 75 */
|
||||
#define OB_WRP_PAGES76TO79 0x00080000U /*!< Write protection of page 76 to 79 */
|
||||
#define OB_WRP_PAGES80TO83 0x00100000U /*!< Write protection of page 80 to 83 */
|
||||
#define OB_WRP_PAGES84TO87 0x00200000U /*!< Write protection of page 84 to 87 */
|
||||
#define OB_WRP_PAGES88TO91 0x00400000U /*!< Write protection of page 88 to 91 */
|
||||
#define OB_WRP_PAGES92TO95 0x00800000U /*!< Write protection of page 92 to 95 */
|
||||
#define OB_WRP_PAGES96TO99 0x01000000U /*!< Write protection of page 96 to 99 */
|
||||
#define OB_WRP_PAGES100TO103 0x02000000U /*!< Write protection of page 100 to 103 */
|
||||
#define OB_WRP_PAGES104TO107 0x04000000U /*!< Write protection of page 104 to 107 */
|
||||
#define OB_WRP_PAGES108TO111 0x08000000U /*!< Write protection of page 108 to 111 */
|
||||
#define OB_WRP_PAGES112TO115 0x10000000U /*!< Write protection of page 112 to 115 */
|
||||
#define OB_WRP_PAGES116TO119 0x20000000U /*!< Write protection of page 115 to 119 */
|
||||
#define OB_WRP_PAGES120TO123 0x40000000U /*!< Write protection of page 120 to 123 */
|
||||
#define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */
|
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
|
||||
|
||||
|
||||
/* STM32 High-density, XL-density and Connectivity line devices */
|
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \
|
||||
|| defined(STM32F101xG) || defined(STM32F103xG) \
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */
|
||||
#define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */
|
||||
#define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */
|
||||
#define OB_WRP_PAGES6TO7 0x00000008U /*!< Write protection of page 6 TO 7 */
|
||||
#define OB_WRP_PAGES8TO9 0x00000010U /*!< Write protection of page 8 TO 9 */
|
||||
#define OB_WRP_PAGES10TO11 0x00000020U /*!< Write protection of page 10 TO 11 */
|
||||
#define OB_WRP_PAGES12TO13 0x00000040U /*!< Write protection of page 12 TO 13 */
|
||||
#define OB_WRP_PAGES14TO15 0x00000080U /*!< Write protection of page 14 TO 15 */
|
||||
#define OB_WRP_PAGES16TO17 0x00000100U /*!< Write protection of page 16 TO 17 */
|
||||
#define OB_WRP_PAGES18TO19 0x00000200U /*!< Write protection of page 18 TO 19 */
|
||||
#define OB_WRP_PAGES20TO21 0x00000400U /*!< Write protection of page 20 TO 21 */
|
||||
#define OB_WRP_PAGES22TO23 0x00000800U /*!< Write protection of page 22 TO 23 */
|
||||
#define OB_WRP_PAGES24TO25 0x00001000U /*!< Write protection of page 24 TO 25 */
|
||||
#define OB_WRP_PAGES26TO27 0x00002000U /*!< Write protection of page 26 TO 27 */
|
||||
#define OB_WRP_PAGES28TO29 0x00004000U /*!< Write protection of page 28 TO 29 */
|
||||
#define OB_WRP_PAGES30TO31 0x00008000U /*!< Write protection of page 30 TO 31 */
|
||||
#define OB_WRP_PAGES32TO33 0x00010000U /*!< Write protection of page 32 TO 33 */
|
||||
#define OB_WRP_PAGES34TO35 0x00020000U /*!< Write protection of page 34 TO 35 */
|
||||
#define OB_WRP_PAGES36TO37 0x00040000U /*!< Write protection of page 36 TO 37 */
|
||||
#define OB_WRP_PAGES38TO39 0x00080000U /*!< Write protection of page 38 TO 39 */
|
||||
#define OB_WRP_PAGES40TO41 0x00100000U /*!< Write protection of page 40 TO 41 */
|
||||
#define OB_WRP_PAGES42TO43 0x00200000U /*!< Write protection of page 42 TO 43 */
|
||||
#define OB_WRP_PAGES44TO45 0x00400000U /*!< Write protection of page 44 TO 45 */
|
||||
#define OB_WRP_PAGES46TO47 0x00800000U /*!< Write protection of page 46 TO 47 */
|
||||
#define OB_WRP_PAGES48TO49 0x01000000U /*!< Write protection of page 48 TO 49 */
|
||||
#define OB_WRP_PAGES50TO51 0x02000000U /*!< Write protection of page 50 TO 51 */
|
||||
#define OB_WRP_PAGES52TO53 0x04000000U /*!< Write protection of page 52 TO 53 */
|
||||
#define OB_WRP_PAGES54TO55 0x08000000U /*!< Write protection of page 54 TO 55 */
|
||||
#define OB_WRP_PAGES56TO57 0x10000000U /*!< Write protection of page 56 TO 57 */
|
||||
#define OB_WRP_PAGES58TO59 0x20000000U /*!< Write protection of page 58 TO 59 */
|
||||
#define OB_WRP_PAGES60TO61 0x40000000U /*!< Write protection of page 60 TO 61 */
|
||||
#define OB_WRP_PAGES62TO127 0x80000000U /*!< Write protection of page 62 TO 127 */
|
||||
#define OB_WRP_PAGES62TO255 0x80000000U /*!< Write protection of page 62 TO 255 */
|
||||
#define OB_WRP_PAGES62TO511 0x80000000U /*!< Write protection of page 62 TO 511 */
|
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
|
||||
/* STM32F101xG || STM32F103xG */
|
||||
/* STM32F105xC || STM32F107xC */
|
||||
|
||||
#define OB_WRP_ALLPAGES 0xFFFFFFFFU /*!< Write protection of all Pages */
|
||||
|
||||
/* Low Density */
|
||||
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
|
||||
#define OB_WRP_PAGES0TO31MASK 0x000000FFU
|
||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
|
||||
|
||||
/* Medium Density */
|
||||
#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
|
||||
#define OB_WRP_PAGES0TO31MASK 0x000000FFU
|
||||
#define OB_WRP_PAGES32TO63MASK 0x0000FF00U
|
||||
#define OB_WRP_PAGES64TO95MASK 0x00FF0000U
|
||||
#define OB_WRP_PAGES96TO127MASK 0xFF000000U
|
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
|
||||
|
||||
/* High Density */
|
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
|
||||
#define OB_WRP_PAGES0TO15MASK 0x000000FFU
|
||||
#define OB_WRP_PAGES16TO31MASK 0x0000FF00U
|
||||
#define OB_WRP_PAGES32TO47MASK 0x00FF0000U
|
||||
#define OB_WRP_PAGES48TO255MASK 0xFF000000U
|
||||
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
|
||||
|
||||
/* XL Density */
|
||||
#if defined(STM32F101xG) || defined(STM32F103xG)
|
||||
#define OB_WRP_PAGES0TO15MASK 0x000000FFU
|
||||
#define OB_WRP_PAGES16TO31MASK 0x0000FF00U
|
||||
#define OB_WRP_PAGES32TO47MASK 0x00FF0000U
|
||||
#define OB_WRP_PAGES48TO511MASK 0xFF000000U
|
||||
#endif /* STM32F101xG || STM32F103xG */
|
||||
|
||||
/* Connectivity line devices */
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define OB_WRP_PAGES0TO15MASK 0x000000FFU
|
||||
#define OB_WRP_PAGES16TO31MASK 0x0000FF00U
|
||||
#define OB_WRP_PAGES32TO47MASK 0x00FF0000U
|
||||
#define OB_WRP_PAGES48TO127MASK 0xFF000000U
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 ((uint8_t)0xA5)
|
||||
#define OB_RDP_LEVEL_1 ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(FLASH_BANK2_END)
|
||||
/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */
|
||||
#define OB_BOOT1_SET ((uint16_t)0x0008) /*!< BOOT1 Set */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_BANK2_END */
|
||||
|
||||
/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
|
||||
* @{
|
||||
*/
|
||||
#define OB_DATA_ADDRESS_DATA0 0x1FFFF804U
|
||||
#define OB_DATA_ADDRESS_DATA1 0x1FFFF806U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flag_definition Flag definition
|
||||
* @brief Flag definition
|
||||
* @{
|
||||
*/
|
||||
#if defined(FLASH_BANK2_END)
|
||||
#define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */
|
||||
#define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */
|
||||
#define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */
|
||||
|
||||
#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */
|
||||
#define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */
|
||||
#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */
|
||||
|
||||
#define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16U) /*!< FLASH Bank2 Busy flag */
|
||||
#define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16U) /*!< FLASH Bank2 Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag */
|
||||
#define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16U) /*!< FLASH Bank2 End of Operation flag */
|
||||
|
||||
#else
|
||||
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
|
||||
|
||||
#endif
|
||||
#define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition Interrupt definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#if defined(FLASH_BANK2_END)
|
||||
#define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */
|
||||
#define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */
|
||||
|
||||
#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */
|
||||
#define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */
|
||||
|
||||
#define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */
|
||||
#define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2 */
|
||||
|
||||
#else
|
||||
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
|
||||
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt Interrupt
|
||||
* @brief macros to handle FLASH interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(FLASH_BANK2_END)
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
|
||||
* @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
|
||||
* @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
|
||||
* @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \
|
||||
/* Enable Bank1 IT */ \
|
||||
SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
|
||||
/* Enable Bank2 IT */ \
|
||||
SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
|
||||
* @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
|
||||
* @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
|
||||
* @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \
|
||||
/* Disable Bank1 IT */ \
|
||||
CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
|
||||
/* Disable Bank2 IT */ \
|
||||
CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__ specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
|
||||
* @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
|
||||
* @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
|
||||
* @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
|
||||
* @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
|
||||
* @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
|
||||
* @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
|
||||
* @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
|
||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
|
||||
(FLASH->OBR & FLASH_OBR_OPTERR) : \
|
||||
((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
|
||||
(FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
|
||||
(FLASH->SR2 & ((__FLAG__) >> 16U))))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag.
|
||||
* @param __FLAG__ specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
|
||||
* @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
|
||||
* @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
|
||||
* @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
|
||||
* @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
|
||||
* @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
|
||||
* @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
|
||||
* @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
|
||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
|
||||
/* Clear FLASH_FLAG_OPTVERR flag */ \
|
||||
if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
|
||||
{ \
|
||||
CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
|
||||
} \
|
||||
else { \
|
||||
/* Clear Flag in Bank1 */ \
|
||||
if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
|
||||
{ \
|
||||
FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
|
||||
} \
|
||||
/* Clear Flag in Bank2 */ \
|
||||
if (((__FLAG__) >> 16U) != RESET) \
|
||||
{ \
|
||||
FLASH->SR2 = ((__FLAG__) >> 16U); \
|
||||
} \
|
||||
} \
|
||||
} while(0U)
|
||||
#else
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
|
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
|
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__ specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
|
||||
* @arg @ref FLASH_FLAG_BSY FLASH Busy flag
|
||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
|
||||
(FLASH->OBR & FLASH_OBR_OPTERR) : \
|
||||
(FLASH->SR & (__FLAG__)))
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag.
|
||||
* @param __FLAG__ specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
|
||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
|
||||
/* Clear FLASH_FLAG_OPTVERR flag */ \
|
||||
if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
|
||||
{ \
|
||||
CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
|
||||
} \
|
||||
else { \
|
||||
/* Clear Flag in Bank1 */ \
|
||||
FLASH->SR = (__FLAG__); \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_FLASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
308
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
Normal file
308
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
Normal file
@@ -0,0 +1,308 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_GPIO_H
|
||||
#define STM32F1xx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode_define */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull_define */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed_define */
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0u,
|
||||
GPIO_PIN_SET
|
||||
} GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define GPIO pins define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode_define GPIO mode define
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0xX0yz00YZ
|
||||
* - X : GPIO mode or EXTI Mode
|
||||
* - y : External IT or Event trigger detection
|
||||
* - z : IO configuration on External IT or Event
|
||||
* - Y : Output type (Push Pull or Open Drain)
|
||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */
|
||||
#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed_define GPIO speed define
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
|
||||
#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull_define GPIO pull define
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extension module */
|
||||
#include "stm32f1xx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u))
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((MODE) == GPIO_MODE_AF_PP) ||\
|
||||
((MODE) == GPIO_MODE_AF_OD) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_IT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_ANALOG))
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
|
||||
((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
|
||||
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
|
||||
((PULL) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Functions GPIO Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_GPIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
894
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
Normal file
894
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
Normal file
@@ -0,0 +1,894 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_GPIO_EX_H
|
||||
#define STM32F1xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
|
||||
* @brief This section propose definition to use the Cortex EVENTOUT signal.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
|
||||
#define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
|
||||
#define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
|
||||
#define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
|
||||
#define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
|
||||
#define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
|
||||
#define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
|
||||
#define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
|
||||
#define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
|
||||
#define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
|
||||
#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
|
||||
#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
|
||||
#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
|
||||
#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
|
||||
#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
|
||||
#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
|
||||
|
||||
#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
|
||||
#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
|
||||
#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
|
||||
#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
|
||||
#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
|
||||
|
||||
#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
|
||||
((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
|
||||
((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
|
||||
((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
|
||||
((__PORT__) == AFIO_EVENTOUT_PORT_E))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
|
||||
* @brief This section propose definition to remap the alternate function to some other port/pins.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
|
||||
* @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
|
||||
* @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of I2C1 alternate function SCL and SDA.
|
||||
* @note ENABLE: Remap (SCL/PB8, SDA/PB9)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of I2C1 alternate function SCL and SDA.
|
||||
* @note DISABLE: No remap (SCL/PB6, SDA/PB7)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of USART1 alternate function TX and RX.
|
||||
* @note ENABLE: Remap (TX/PB6, RX/PB7)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of USART1 alternate function TX and RX.
|
||||
* @note DISABLE: No remap (TX/PA9, RX/PA10)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
|
||||
* @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
|
||||
* @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
|
||||
* @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
|
||||
* @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
|
||||
* @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
|
||||
* @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
|
||||
* @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
|
||||
* @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
|
||||
* @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
|
||||
* @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
|
||||
* @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
|
||||
* @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
|
||||
* @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
|
||||
* @note TIM3_ETR on PE0 is not re-mapped.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
|
||||
* @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
|
||||
* @note TIM3_ETR on PE0 is not re-mapped.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM3 alternate function channels 1 to 4
|
||||
* @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
|
||||
* @note TIM3_ETR on PE0 is not re-mapped.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
|
||||
* @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
|
||||
* @note TIM4_ETR on PE0 is not re-mapped.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
|
||||
* @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
|
||||
* @note TIM4_ETR on PE0 is not re-mapped.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP)
|
||||
|
||||
#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
|
||||
* @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
|
||||
* @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
|
||||
* @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP)
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
|
||||
* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
|
||||
* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
|
||||
* on 100-pin and 144-pin packages, no need for remapping).
|
||||
* @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
|
||||
* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
|
||||
* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
|
||||
* on 100-pin and 144-pin packages, no need for remapping).
|
||||
* @note DISABLE: No remapping of PD0 and PD1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP)
|
||||
|
||||
#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
|
||||
/**
|
||||
* @brief Enable the remapping of TIM5CH4.
|
||||
* @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
|
||||
* @note This function is available only in high density value line devices.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM5CH4.
|
||||
* @note DISABLE: TIM5_CH4 is connected to PA3
|
||||
* @note This function is available only in high density value line devices.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR_ETH_REMAP)
|
||||
/**
|
||||
* @brief Enable the remapping of Ethernet MAC connections with the PHY.
|
||||
* @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of Ethernet MAC connections with the PHY.
|
||||
* @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR_CAN2_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
|
||||
* @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
|
||||
* @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR_MII_RMII_SEL)
|
||||
/**
|
||||
* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
|
||||
* @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL)
|
||||
|
||||
/**
|
||||
* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
|
||||
* @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
|
||||
* @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
|
||||
* @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
|
||||
* @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
|
||||
* @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
|
||||
|
||||
#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
|
||||
* @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
|
||||
* @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
|
||||
* @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
|
||||
* @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the Serial wire JTAG configuration
|
||||
* @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the Serial wire JTAG configuration
|
||||
* @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST)
|
||||
|
||||
/**
|
||||
* @brief Enable the Serial wire JTAG configuration
|
||||
* @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable the Serial wire JTAG configuration
|
||||
* @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE)
|
||||
|
||||
#if defined(AFIO_MAPR_SPI3_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
|
||||
* @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
|
||||
* @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
|
||||
|
||||
/**
|
||||
* @brief Control of TIM2_ITR1 internal mapping.
|
||||
* @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
|
||||
|
||||
/**
|
||||
* @brief Control of TIM2_ITR1 internal mapping.
|
||||
* @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR_PTP_PPS_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
|
||||
* @note ENABLE: PTP_PPS is output on PB5 pin.
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
|
||||
* @note DISABLE: PTP_PPS not output on PB5 pin.
|
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_TIM9_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
|
||||
* @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
|
||||
* @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_TIM10_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM10_CH1.
|
||||
* @note ENABLE: Remap (TIM10_CH1 on PF6).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM10_CH1.
|
||||
* @note DISABLE: No remap (TIM10_CH1 on PB8).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_TIM11_REMAP)
|
||||
/**
|
||||
* @brief Enable the remapping of TIM11_CH1.
|
||||
* @note ENABLE: Remap (TIM11_CH1 on PF7).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM11_CH1.
|
||||
* @note DISABLE: No remap (TIM11_CH1 on PB9).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_TIM13_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM13_CH1.
|
||||
* @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM13_CH1.
|
||||
* @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_TIM14_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM14_CH1.
|
||||
* @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM14_CH1.
|
||||
* @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Controls the use of the optional FSMC_NADV signal.
|
||||
* @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Controls the use of the optional FSMC_NADV signal.
|
||||
* @note CONNECTED: The NADV signal is connected to the output (default).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_TIM15_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
|
||||
* @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
|
||||
* @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_TIM16_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM16_CH1.
|
||||
* @note ENABLE: Remap (TIM16_CH1 on PA6).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM16_CH1.
|
||||
* @note DISABLE: No remap (TIM16_CH1 on PB8).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_TIM17_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM17_CH1.
|
||||
* @note ENABLE: Remap (TIM17_CH1 on PA7).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM17_CH1.
|
||||
* @note DISABLE: No remap (TIM17_CH1 on PB9).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_CEC_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of CEC.
|
||||
* @note ENABLE: Remap (CEC on PB10).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of CEC.
|
||||
* @note DISABLE: No remap (CEC on PB8).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
|
||||
* @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
|
||||
* @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
|
||||
* @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
|
||||
* @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_TIM12_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
|
||||
* @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
|
||||
* @note This bit is available only in high density value line devices.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
|
||||
* @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
|
||||
* @note This bit is available only in high density value line devices.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
|
||||
#endif
|
||||
|
||||
#if defined(AFIO_MAPR2_MISC_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Miscellaneous features remapping.
|
||||
* This bit is set and cleared by software. It controls miscellaneous features.
|
||||
* The DMA2 channel 5 interrupt position in the vector table.
|
||||
* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
|
||||
* @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
|
||||
* selected as DAC Trigger 3, TIM15 triggers TIM1/3.
|
||||
* @note This bit is available only in high density value line devices.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
|
||||
|
||||
/**
|
||||
* @brief Miscellaneous features remapping.
|
||||
* This bit is set and cleared by software. It controls miscellaneous features.
|
||||
* The DMA2 channel 5 interrupt position in the vector table.
|
||||
* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
|
||||
* @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
|
||||
* event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
|
||||
* @note This bit is available only in high density value line devices.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
|
||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
||||
((__GPIOx__) == (GPIOC))? 2uL :3uL)
|
||||
#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
|
||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
||||
((__GPIOx__) == (GPIOC))? 2uL :\
|
||||
((__GPIOx__) == (GPIOD))? 3uL :4uL)
|
||||
#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
|
||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
||||
((__GPIOx__) == (GPIOC))? 2uL :\
|
||||
((__GPIOx__) == (GPIOD))? 3uL :\
|
||||
((__GPIOx__) == (GPIOE))? 4uL :\
|
||||
((__GPIOx__) == (GPIOF))? 5uL :6uL)
|
||||
#endif
|
||||
|
||||
#define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \
|
||||
tmpreg |= AFIO_MAPR_SWJ_CFG; \
|
||||
tmpreg |= REMAP_PIN; \
|
||||
AFIO->MAPR = tmpreg; \
|
||||
}while(0u)
|
||||
|
||||
#define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \
|
||||
tmpreg |= AFIO_MAPR_SWJ_CFG; \
|
||||
tmpreg &= ~REMAP_PIN; \
|
||||
AFIO->MAPR = tmpreg; \
|
||||
}while(0u)
|
||||
|
||||
#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \
|
||||
tmpreg &= ~REMAP_PIN_MASK; \
|
||||
tmpreg |= AFIO_MAPR_SWJ_CFG; \
|
||||
tmpreg |= REMAP_PIN; \
|
||||
AFIO->MAPR = tmpreg; \
|
||||
}while(0u)
|
||||
|
||||
#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \
|
||||
tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \
|
||||
tmpreg |= DBGAFR_SWJCFG; \
|
||||
AFIO->MAPR = tmpreg; \
|
||||
}while(0u)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup GPIOEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIOEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
|
||||
void HAL_GPIOEx_EnableEventout(void);
|
||||
void HAL_GPIOEx_DisableEventout(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_GPIO_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
388
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Normal file
388
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
Normal file
@@ -0,0 +1,388 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_PWR_H
|
||||
#define __STM32F1xx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
||||
This parameter can be a value of @ref PWR_PVD_detection_level */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWR_PVD_Mode */
|
||||
}PWR_PVDTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Internal constants --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup PWR_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
|
||||
#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
|
||||
#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
|
||||
#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
|
||||
#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
|
||||
#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
|
||||
#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
|
||||
#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode PWR PVD Mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
|
||||
#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON 0x00000000U
|
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
|
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag PWR Flag
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Macros PWR Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check PWR flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
|
||||
* was received from the WKUP pin or from the RTC alarm
|
||||
* An additional wakeup event is detected if the WKUP pin is enabled
|
||||
* (by setting the EWUP bit) when the WKUP pin level is already high.
|
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
|
||||
* resumed from StandBy mode.
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
|
||||
* For this reason, this bit is equal to 0 after Standby or reset
|
||||
* until the PVDE bit is set.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the PWR's pending flags.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger.
|
||||
* This parameter can be:
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* This parameter can be:
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
|
||||
* @retval EXTI PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Clear the PVD EXTI flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Macros PWR Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
||||
|
||||
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_NORMAL))
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
|
||||
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
||||
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
|
||||
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
void HAL_PWR_DeInit(void);
|
||||
void HAL_PWR_EnableBkUpAccess(void);
|
||||
void HAL_PWR_DisableBkUpAccess(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
||||
/* #define HAL_PWR_ConfigPVD 12*/
|
||||
void HAL_PWR_EnablePVD(void);
|
||||
void HAL_PWR_DisablePVD(void);
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
||||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
void HAL_PWR_EnableSleepOnExit(void);
|
||||
void HAL_PWR_DisableSleepOnExit(void);
|
||||
void HAL_PWR_EnableSEVOnPend(void);
|
||||
void HAL_PWR_DisableSEVOnPend(void);
|
||||
|
||||
|
||||
|
||||
void HAL_PWR_PVD_IRQHandler(void);
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F1xx_HAL_PWR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
1378
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
Normal file
1378
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
Normal file
@@ -0,0 +1,1378 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RCC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_RCC_H
|
||||
#define __STM32F1xx_HAL_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCC_Exported_Types RCC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief RCC PLL configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLState; /*!< PLLState: The new state of the PLL.
|
||||
This parameter can be a value of @ref RCC_PLL_Config */
|
||||
|
||||
uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
|
||||
This parameter must be a value of @ref RCC_PLL_Clock_Source */
|
||||
|
||||
uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
|
||||
This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
|
||||
} RCC_PLLInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RCC System, AHB and APB busses clock configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockType; /*!< The clock to be configured.
|
||||
This parameter can be a value of @ref RCC_System_Clock_Type */
|
||||
|
||||
uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
|
||||
This parameter can be a value of @ref RCC_System_Clock_Source */
|
||||
|
||||
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
|
||||
This parameter can be a value of @ref RCC_AHB_Clock_Source */
|
||||
|
||||
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
|
||||
|
||||
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
|
||||
} RCC_ClkInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RCC_Exported_Constants RCC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
|
||||
#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Oscillator_Type Oscillator Type
|
||||
* @{
|
||||
*/
|
||||
#define RCC_OSCILLATORTYPE_NONE 0x00000000U
|
||||
#define RCC_OSCILLATORTYPE_HSE 0x00000001U
|
||||
#define RCC_OSCILLATORTYPE_HSI 0x00000002U
|
||||
#define RCC_OSCILLATORTYPE_LSE 0x00000004U
|
||||
#define RCC_OSCILLATORTYPE_LSI 0x00000008U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSE_Config HSE Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
|
||||
#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
|
||||
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Config LSE Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
|
||||
#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
|
||||
#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSI_Config HSI Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
|
||||
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
|
||||
|
||||
#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSI_Config LSI Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
|
||||
#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Config PLL Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */
|
||||
#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
|
||||
#define RCC_PLL_ON 0x00000002U /*!< PLL activation */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Type System Clock Type
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
|
||||
#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
|
||||
#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
|
||||
#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source System Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
|
||||
#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
|
||||
#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
|
||||
#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
|
||||
#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
|
||||
#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
|
||||
#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
|
||||
#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
|
||||
#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
|
||||
#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
|
||||
#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
|
||||
#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
|
||||
#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
|
||||
#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
|
||||
#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
|
||||
#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
|
||||
#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */
|
||||
#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
|
||||
#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
|
||||
#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RCC_MCO_Index MCO Index
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO1 0x00000000U
|
||||
#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCODIV_1 0x00000000U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Interrupt Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
|
||||
#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
|
||||
#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
|
||||
#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
|
||||
#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
|
||||
#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag Flags
|
||||
* Elements values convention: XXXYYYYYb
|
||||
* - YYYYY : Flag position in the register
|
||||
* - XXX : Register index
|
||||
* - 001: CR register
|
||||
* - 010: BDCR register
|
||||
* - 011: CSR register
|
||||
* @{
|
||||
*/
|
||||
/* Flags in the CR register */
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */
|
||||
|
||||
/* Flags in the CSR register */
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */
|
||||
#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */
|
||||
#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
|
||||
|
||||
/* Flags in the BDCR register */
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCC_Exported_Macros RCC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
|
||||
* @brief Enable or disable the AHB1 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
|
||||
#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
|
||||
#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
|
||||
#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
|
||||
* @brief Get the enable or disable status of the AHB peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
|
||||
#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
|
||||
#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
|
||||
#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
|
||||
#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
|
||||
#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
|
||||
#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
|
||||
#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
|
||||
* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_BKP_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
|
||||
#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
|
||||
#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
|
||||
#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
|
||||
#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
|
||||
|
||||
#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
|
||||
#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
|
||||
* @brief Get the enable or disable status of the APB1 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
|
||||
#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
|
||||
#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
|
||||
#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
|
||||
#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
|
||||
#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
|
||||
#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
|
||||
#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
|
||||
#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
|
||||
#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
|
||||
#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
|
||||
#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
|
||||
#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
|
||||
#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
|
||||
* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
|
||||
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
|
||||
#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
|
||||
#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
|
||||
#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
|
||||
#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
|
||||
|
||||
#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
|
||||
#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
|
||||
#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
|
||||
* @brief Get the enable or disable status of the APB2 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
|
||||
#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
|
||||
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
|
||||
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
|
||||
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
|
||||
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
|
||||
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
|
||||
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
|
||||
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
|
||||
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
|
||||
#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
|
||||
#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
|
||||
#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
|
||||
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
|
||||
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
|
||||
#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
|
||||
#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
|
||||
#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
|
||||
* @brief Force or release APB1 peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
|
||||
#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
|
||||
#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
|
||||
#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
|
||||
#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
|
||||
#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
|
||||
|
||||
#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
|
||||
#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
|
||||
|
||||
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
|
||||
#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
|
||||
#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
|
||||
#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
|
||||
#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
|
||||
#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
|
||||
|
||||
#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
|
||||
#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
|
||||
* @brief Force or release APB2 peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
|
||||
#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
|
||||
#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
|
||||
#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
|
||||
#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
|
||||
#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
|
||||
#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
|
||||
|
||||
#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
|
||||
#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
|
||||
#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
|
||||
|
||||
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
|
||||
#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
|
||||
#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
|
||||
#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
|
||||
#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
|
||||
#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
|
||||
#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
|
||||
|
||||
#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
|
||||
#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
|
||||
#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSI_Configuration HSI Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
|
||||
* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
|
||||
* @note HSI can not be stopped if it is used as system clock source. In this case,
|
||||
* you have to select another source of the system clock then stop the HSI.
|
||||
* @note After enabling the HSI, the application software should wait on HSIRDY
|
||||
* flag to be set indicating that HSI clock is stable and can be used as
|
||||
* system clock source.
|
||||
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
|
||||
* clock cycles.
|
||||
*/
|
||||
#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
|
||||
#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
|
||||
|
||||
/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
|
||||
* @note The calibration is used to compensate for the variations in voltage
|
||||
* and temperature that influence the frequency of the internal HSI RC.
|
||||
* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
|
||||
* (default is RCC_HSICALIBRATION_DEFAULT).
|
||||
* This parameter must be a number between 0 and 0x1F.
|
||||
*/
|
||||
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
|
||||
(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSI_Configuration LSI Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
|
||||
* @note After enabling the LSI, the application software should wait on
|
||||
* LSIRDY flag to be set indicating that LSI clock is stable and can
|
||||
* be used to clock the IWDG and/or the RTC.
|
||||
*/
|
||||
#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
|
||||
|
||||
/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
|
||||
* @note LSI can not be disabled if the IWDG is running.
|
||||
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
|
||||
* clock cycles.
|
||||
*/
|
||||
#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSE_Configuration HSE Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro to configure the External High Speed oscillator (HSE).
|
||||
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
|
||||
* supported by this macro. User should request a transition to HSE Off
|
||||
* first and then HSE On or HSE Bypass.
|
||||
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
|
||||
* software should wait on HSERDY flag to be set indicating that HSE clock
|
||||
* is stable and can be used to clock the PLL and/or system clock.
|
||||
* @note HSE state can not be changed if it is used directly or through the
|
||||
* PLL as system clock. In this case, you have to select another source
|
||||
* of the system clock then change the HSE state (ex. disable it).
|
||||
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
|
||||
* @note This function reset the CSSON bit, so if the clock security system(CSS)
|
||||
* was previously enabled you have to enable it again after calling this
|
||||
* function.
|
||||
* @param __STATE__ specifies the new state of the HSE.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
|
||||
* 6 HSE oscillator clock cycles.
|
||||
* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
|
||||
* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
|
||||
*/
|
||||
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
|
||||
do{ \
|
||||
if ((__STATE__) == RCC_HSE_ON) \
|
||||
{ \
|
||||
SET_BIT(RCC->CR, RCC_CR_HSEON); \
|
||||
} \
|
||||
else if ((__STATE__) == RCC_HSE_OFF) \
|
||||
{ \
|
||||
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
|
||||
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
||||
} \
|
||||
else if ((__STATE__) == RCC_HSE_BYPASS) \
|
||||
{ \
|
||||
SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
||||
SET_BIT(RCC->CR, RCC_CR_HSEON); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
|
||||
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
||||
} \
|
||||
}while(0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Configuration LSE Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro to configure the External Low Speed oscillator (LSE).
|
||||
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
|
||||
* @note As the LSE is in the Backup domain and write access is denied to
|
||||
* this domain after reset, you have to enable write access using
|
||||
* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
|
||||
* (to be done once after reset).
|
||||
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
|
||||
* software should wait on LSERDY flag to be set indicating that LSE clock
|
||||
* is stable and can be used to clock the RTC.
|
||||
* @param __STATE__ specifies the new state of the LSE.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
|
||||
* 6 LSE oscillator clock cycles.
|
||||
* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
|
||||
* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
|
||||
*/
|
||||
#define __HAL_RCC_LSE_CONFIG(__STATE__) \
|
||||
do{ \
|
||||
if ((__STATE__) == RCC_LSE_ON) \
|
||||
{ \
|
||||
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
||||
} \
|
||||
else if ((__STATE__) == RCC_LSE_OFF) \
|
||||
{ \
|
||||
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
||||
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
||||
} \
|
||||
else if ((__STATE__) == RCC_LSE_BYPASS) \
|
||||
{ \
|
||||
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
||||
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
||||
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
||||
} \
|
||||
}while(0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Configuration PLL Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Macro to enable the main PLL.
|
||||
* @note After enabling the main PLL, the application software should wait on
|
||||
* PLLRDY flag to be set indicating that PLL clock is stable and can
|
||||
* be used as system clock source.
|
||||
* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
|
||||
*/
|
||||
#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
|
||||
|
||||
/** @brief Macro to disable the main PLL.
|
||||
* @note The main PLL can not be disabled if it is used as system clock source
|
||||
*/
|
||||
#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
|
||||
|
||||
/** @brief Macro to configure the main PLL clock source and multiplication factors.
|
||||
* @note This function must be used only when the main PLL is disabled.
|
||||
*
|
||||
* @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
|
||||
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
|
||||
* @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
|
||||
* @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
|
||||
@if STM32F105xC
|
||||
* @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
|
||||
@elseif STM32F107xC
|
||||
* @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
|
||||
@else
|
||||
* @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
|
||||
* @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
|
||||
* @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
|
||||
* @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
|
||||
* @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
|
||||
* @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
|
||||
* @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
|
||||
* @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
|
||||
* @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
|
||||
@endif
|
||||
* @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
|
||||
* @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
|
||||
*
|
||||
*/
|
||||
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
|
||||
MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
|
||||
|
||||
/** @brief Get oscillator clock selected as PLL input clock
|
||||
* @retval The clock source used for PLL entry. The returned value can be one
|
||||
* of the following:
|
||||
* @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
|
||||
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Get_Clock_source Get Clock source
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro to configure the system clock source.
|
||||
* @param __SYSCLKSOURCE__ specifies the system clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
|
||||
* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
|
||||
* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
|
||||
*/
|
||||
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the clock source used as system clock.
|
||||
* @retval The clock source used as system clock. The returned value can be one
|
||||
* of the following:
|
||||
* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
|
||||
* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
|
||||
* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(RCC_CFGR_MCO_3)
|
||||
/** @brief Macro to configure the MCO clock.
|
||||
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock
|
||||
* @param __MCODIV__ specifies the MCO clock prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
|
||||
*/
|
||||
#else
|
||||
/** @brief Macro to configure the MCO clock.
|
||||
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
|
||||
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
|
||||
* @param __MCODIV__ specifies the MCO clock prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
|
||||
*/
|
||||
#endif
|
||||
|
||||
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Macro to configure the RTC clock (RTCCLK).
|
||||
* @note As the RTC clock configuration bits are in the Backup domain and write
|
||||
* access is denied to this domain after reset, you have to enable write
|
||||
* access using the Power Backup Access macro before to configure
|
||||
* the RTC clock source (to be done once after reset).
|
||||
* @note Once the RTC clock is configured it can't be changed unless the
|
||||
* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
|
||||
* a Power On Reset (POR).
|
||||
*
|
||||
* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
|
||||
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
|
||||
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
|
||||
* work in STOP and STANDBY modes, and can be used as wakeup source.
|
||||
* However, when the HSE clock is used as RTC clock source, the RTC
|
||||
* cannot be used in STOP and STANDBY modes.
|
||||
* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
|
||||
* RTC clock source).
|
||||
*/
|
||||
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the RTC clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
|
||||
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
|
||||
|
||||
/** @brief Macro to enable the the RTC clock.
|
||||
* @note These macros must be used only after the RTC clock source was selected.
|
||||
*/
|
||||
#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
|
||||
|
||||
/** @brief Macro to disable the the RTC clock.
|
||||
* @note These macros must be used only after the RTC clock source was selected.
|
||||
*/
|
||||
#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
|
||||
|
||||
/** @brief Macro to force the Backup domain reset.
|
||||
* @note This function resets the RTC peripheral (including the backup registers)
|
||||
* and the RTC clock source selection in RCC_BDCR register.
|
||||
*/
|
||||
#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
|
||||
|
||||
/** @brief Macros to release the Backup domain reset.
|
||||
*/
|
||||
#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
|
||||
* @brief macros to manage the specified RCC Flags and interrupts.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Enable RCC interrupt.
|
||||
* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
||||
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
||||
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
||||
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
||||
* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
|
||||
@if STM32F105xx
|
||||
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
||||
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
||||
@elsif STM32F107xx
|
||||
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
||||
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
||||
@endif
|
||||
*/
|
||||
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable RCC interrupt.
|
||||
* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
||||
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
||||
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
||||
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
||||
* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
|
||||
@if STM32F105xx
|
||||
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
||||
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
||||
@elsif STM32F107xx
|
||||
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
||||
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
||||
@endif
|
||||
*/
|
||||
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Clear the RCC's interrupt pending bits.
|
||||
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
|
||||
* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
|
||||
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
|
||||
* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
|
||||
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
|
||||
@if STM32F105xx
|
||||
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
||||
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
||||
@elsif STM32F107xx
|
||||
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
||||
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
||||
@endif
|
||||
* @arg @ref RCC_IT_CSS Clock Security System interrupt
|
||||
*/
|
||||
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
|
||||
|
||||
/** @brief Check the RCC's interrupt has occurred or not.
|
||||
* @param __INTERRUPT__ specifies the RCC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
|
||||
* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
|
||||
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
|
||||
* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
|
||||
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
|
||||
@if STM32F105xx
|
||||
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
||||
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
||||
@elsif STM32F107xx
|
||||
* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
||||
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
||||
@endif
|
||||
* @arg @ref RCC_IT_CSS Clock Security System interrupt
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Set RMVF bit to clear the reset flags.
|
||||
* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
|
||||
* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
|
||||
*/
|
||||
#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
|
||||
|
||||
/** @brief Check RCC flag is set or not.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
|
||||
* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
|
||||
* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
|
||||
@if STM32F105xx
|
||||
* @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
|
||||
* @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
|
||||
@elsif STM32F107xx
|
||||
* @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
|
||||
* @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
|
||||
@endif
|
||||
* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
|
||||
* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
|
||||
* @arg @ref RCC_FLAG_PINRST Pin reset.
|
||||
* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
|
||||
* @arg @ref RCC_FLAG_SFTRST Software reset.
|
||||
* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
|
||||
* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
|
||||
* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
|
||||
((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
|
||||
RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include RCC HAL Extension module */
|
||||
#include "stm32f1xx_hal_rcc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RCC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_RCC_DeInit(void);
|
||||
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
||||
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
|
||||
void HAL_RCC_EnableCSS(void);
|
||||
void HAL_RCC_DisableCSS(void);
|
||||
uint32_t HAL_RCC_GetSysClockFreq(void);
|
||||
uint32_t HAL_RCC_GetHCLKFreq(void);
|
||||
uint32_t HAL_RCC_GetPCLK1Freq(void);
|
||||
uint32_t HAL_RCC_GetPCLK2Freq(void);
|
||||
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
||||
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
|
||||
|
||||
/* CSS NMI IRQ handler */
|
||||
void HAL_RCC_NMI_IRQHandler(void);
|
||||
|
||||
/* User Callbacks in non blocking mode (IT mode) */
|
||||
void HAL_RCC_CSSCallback(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Timeout RCC Timeout
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Disable Backup domain write protection state change timeout */
|
||||
#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
|
||||
/* LSE state change timeout */
|
||||
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
|
||||
#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */
|
||||
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
|
||||
#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
|
||||
#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
|
||||
#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Register_Offset Register offsets
|
||||
* @{
|
||||
*/
|
||||
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
|
||||
#define RCC_CR_OFFSET 0x00U
|
||||
#define RCC_CFGR_OFFSET 0x04U
|
||||
#define RCC_CIR_OFFSET 0x08U
|
||||
#define RCC_BDCR_OFFSET 0x20U
|
||||
#define RCC_CSR_OFFSET 0x24U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
|
||||
* @brief RCC registers bit address in the alias region
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
|
||||
#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
|
||||
#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
|
||||
#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
|
||||
#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
|
||||
|
||||
/* --- CR Register ---*/
|
||||
/* Alias word address of HSION bit */
|
||||
#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
|
||||
#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
|
||||
/* Alias word address of HSEON bit */
|
||||
#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
|
||||
#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
|
||||
/* Alias word address of CSSON bit */
|
||||
#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
|
||||
#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
|
||||
/* Alias word address of PLLON bit */
|
||||
#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
|
||||
#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
/* Alias word address of LSION bit */
|
||||
#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
|
||||
#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
|
||||
|
||||
/* Alias word address of RMVF bit */
|
||||
#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
|
||||
#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
|
||||
|
||||
/* --- BDCR Registers ---*/
|
||||
/* Alias word address of LSEON bit */
|
||||
#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
|
||||
#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
|
||||
|
||||
/* Alias word address of LSEON bit */
|
||||
#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
|
||||
#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
|
||||
|
||||
/* Alias word address of RTCEN bit */
|
||||
#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
|
||||
#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
|
||||
|
||||
/* Alias word address of BDRST bit */
|
||||
#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
|
||||
#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* CR register byte 2 (Bits[23:16]) base address */
|
||||
#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
|
||||
|
||||
/* CIR register byte 1 (Bits[15:8]) base address */
|
||||
#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
|
||||
|
||||
/* CIR register byte 2 (Bits[23:16]) base address */
|
||||
#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
|
||||
|
||||
/* Defines used for Flags */
|
||||
#define CR_REG_INDEX ((uint8_t)1)
|
||||
#define BDCR_REG_INDEX ((uint8_t)2)
|
||||
#define CSR_REG_INDEX ((uint8_t)3)
|
||||
|
||||
#define RCC_FLAG_MASK ((uint8_t)0x1F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
|
||||
#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
|
||||
#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
|
||||
#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
|
||||
((__SOURCE__) == RCC_PLLSOURCE_HSE))
|
||||
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
|
||||
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
|
||||
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
|
||||
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
|
||||
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
|
||||
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
|
||||
((__HSE__) == RCC_HSE_BYPASS))
|
||||
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
|
||||
((__LSE__) == RCC_LSE_BYPASS))
|
||||
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
|
||||
#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
|
||||
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
|
||||
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
|
||||
((__PLL__) == RCC_PLL_ON))
|
||||
|
||||
#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
|
||||
(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
|
||||
(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
|
||||
(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
|
||||
#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
|
||||
#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
|
||||
#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
|
||||
((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
|
||||
((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
|
||||
((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
|
||||
((__HCLK__) == RCC_SYSCLK_DIV512))
|
||||
#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
|
||||
((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
|
||||
((__PCLK__) == RCC_HCLK_DIV16))
|
||||
#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
|
||||
#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
|
||||
#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
|
||||
((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
|
||||
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_RCC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
1908
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
Normal file
1908
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
Normal file
@@ -0,0 +1,1908 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_rcc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RCC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_RCC_EX_H
|
||||
#define __STM32F1xx_HAL_RCC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
|
||||
/* Alias word address of PLLI2SON bit */
|
||||
#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos
|
||||
#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U)))
|
||||
/* Alias word address of PLL2ON bit */
|
||||
#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos
|
||||
#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U)))
|
||||
|
||||
#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */
|
||||
#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
|
||||
#define CR_REG_INDEX ((uint8_t)1)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
|
||||
((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
|
||||
|| defined(STM32F100xE)
|
||||
#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
|
||||
|
||||
#else
|
||||
#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
|
||||
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
|
||||
((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
|
||||
((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
|
||||
((__MUL__) == RCC_PLL_MUL6_5))
|
||||
|
||||
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
|
||||
|| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
|
||||
|| ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
|
||||
|| ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
|
||||
|| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
|
||||
|
||||
#else
|
||||
#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
|
||||
((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
|
||||
((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
|
||||
((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
|
||||
((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
|
||||
((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
|
||||
((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
|
||||
((__MUL__) == RCC_PLL_MUL16))
|
||||
|
||||
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
|
||||
|| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
|
||||
|| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC*/
|
||||
|
||||
#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \
|
||||
((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
|
||||
|
||||
#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
|
||||
|
||||
#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))
|
||||
|
||||
#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \
|
||||
((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \
|
||||
((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \
|
||||
((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \
|
||||
((__MUL__) == RCC_PLLI2S_MUL20))
|
||||
|
||||
#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
|
||||
((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
|
||||
|
||||
#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
|
||||
((__PLL__) == RCC_PLL2_ON))
|
||||
|
||||
#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \
|
||||
((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \
|
||||
((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \
|
||||
((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \
|
||||
((__MUL__) == RCC_PLL2_MUL20))
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
|
||||
|
||||
#elif defined(STM32F103xE) || defined(STM32F103xG)
|
||||
|
||||
#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
|
||||
|
||||
#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
|
||||
|
||||
|
||||
#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
||||
|| defined(STM32F103xB)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
|
||||
|
||||
#else
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
|
||||
#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
|
||||
|
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
/**
|
||||
* @brief RCC PLL2 configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLL2State; /*!< The new state of the PLL2.
|
||||
This parameter can be a value of @ref RCCEx_PLL2_Config */
|
||||
|
||||
uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
|
||||
This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
|
||||
This parameter can be a value of @ref RCCEx_Prediv2_Factor */
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
} RCC_PLL2InitTypeDef;
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/**
|
||||
* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OscillatorType; /*!< The oscillators to be configured.
|
||||
This parameter can be a value of @ref RCC_Oscillator_Type */
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
uint32_t Prediv1Source; /*!< The Prediv1 source value.
|
||||
This parameter can be a value of @ref RCCEx_Prediv1_Source */
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
uint32_t HSEState; /*!< The new state of the HSE.
|
||||
This parameter can be a value of @ref RCC_HSE_Config */
|
||||
|
||||
uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
|
||||
This parameter can be a value of @ref RCCEx_Prediv1_Factor */
|
||||
|
||||
uint32_t LSEState; /*!< The new state of the LSE.
|
||||
This parameter can be a value of @ref RCC_LSE_Config */
|
||||
|
||||
uint32_t HSIState; /*!< The new state of the HSI.
|
||||
This parameter can be a value of @ref RCC_HSI_Config */
|
||||
|
||||
uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
|
||||
|
||||
uint32_t LSIState; /*!< The new state of the LSI.
|
||||
This parameter can be a value of @ref RCC_LSI_Config */
|
||||
|
||||
RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
} RCC_OscInitTypeDef;
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
/**
|
||||
* @brief RCC PLLI2S configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
|
||||
This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
|
||||
This parameter can be a value of @ref RCCEx_Prediv2_Factor */
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
} RCC_PLLI2SInitTypeDef;
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/**
|
||||
* @brief RCC extended clocks structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
|
||||
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
|
||||
|
||||
uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
|
||||
This parameter can be a value of @ref RCC_RTC_Clock_Source */
|
||||
|
||||
uint32_t AdcClockSelection; /*!< ADC clock source
|
||||
This parameter can be a value of @ref RCCEx_ADC_Prescaler */
|
||||
|
||||
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
|
||||
|| defined(STM32F107xC)
|
||||
uint32_t I2s2ClockSelection; /*!< I2S2 clock source
|
||||
This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
|
||||
|
||||
uint32_t I2s3ClockSelection; /*!< I2S3 clock source
|
||||
This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
|
||||
This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC)
|
||||
uint32_t UsbClockSelection; /*!< USB clock source
|
||||
This parameter can be a value of @ref RCCEx_USB_Prescaler */
|
||||
|
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
} RCC_PeriphCLKInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PERIPHCLK_RTC 0x00000001U
|
||||
#define RCC_PERIPHCLK_ADC 0x00000002U
|
||||
#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\
|
||||
|| defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define RCC_PERIPHCLK_I2S2 0x00000004U
|
||||
#define RCC_PERIPHCLK_I2S3 0x00000008U
|
||||
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define RCC_PERIPHCLK_USB 0x00000010U
|
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
|
||||
#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
|
||||
#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
|
||||
#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
|
||||
|| defined(STM32F107xC)
|
||||
/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
|
||||
/** @defgroup RCCEx_USB_Prescaler USB Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
|
||||
#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
|
||||
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
/** @defgroup RCCEx_USB_Prescaler USB Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE
|
||||
#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
|
||||
#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
|
||||
#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
|
||||
#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
|
||||
#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
|
||||
#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
|
||||
#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
|
||||
#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
|
||||
#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
/** @defgroup RCCEx_Prediv1_Source Prediv1 Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
|
||||
#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HSE_PREDIV_DIV1 0x00000000U
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
|
||||
|| defined(STM32F100xE)
|
||||
#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
|
||||
#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
|
||||
#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
|
||||
#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
|
||||
#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
|
||||
#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
|
||||
#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
|
||||
#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
|
||||
#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
|
||||
#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
|
||||
#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
|
||||
#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
|
||||
#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
|
||||
#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
|
||||
#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
|
||||
#else
|
||||
#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
|
||||
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
|
||||
#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
|
||||
#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
|
||||
#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
|
||||
#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
|
||||
#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
|
||||
#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
|
||||
#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
|
||||
#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
|
||||
#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
|
||||
#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
|
||||
#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
|
||||
#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
|
||||
#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
|
||||
#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
|
||||
#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_PLL2_Config PLL Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLL2_NONE 0x00000000U
|
||||
#define RCC_PLL2_OFF 0x00000001U
|
||||
#define RCC_PLL2_ON 0x00000002U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
|
||||
#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
|
||||
#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
|
||||
#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
|
||||
#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
|
||||
#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
|
||||
#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
|
||||
#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
|
||||
#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#else
|
||||
#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
|
||||
#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
|
||||
#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
|
||||
#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
|
||||
#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
|
||||
#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
|
||||
#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
|
||||
#else
|
||||
#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
|
||||
#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
|
||||
#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
|
||||
#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
|
||||
#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
|
||||
#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
|
||||
#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
|
||||
#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
|
||||
#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
|
||||
#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
|
||||
#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
|
||||
#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
|
||||
#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
|
||||
#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
|
||||
#endif /* STM32F105xC || STM32F107xC*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
/** @defgroup RCCEx_Interrupt RCCEx Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
|
||||
#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_Flag RCCEx Flag
|
||||
* Elements values convention: 0XXYYYYYb
|
||||
* - YYYYY : Flag position in the register
|
||||
* - XX : Register index
|
||||
* - 01: CR register
|
||||
* @{
|
||||
*/
|
||||
/* Flags in the CR register */
|
||||
#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos))
|
||||
#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F105xC || STM32F107xC*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
|
||||
* @brief Enable or disable the AHB1 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
|
||||
|| defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
|
||||
|| defined (STM32F100xE)
|
||||
#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
|
||||
|
||||
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
|
||||
|| defined(STM32F103xG) || defined (STM32F100xE)
|
||||
#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
|
||||
|
||||
#if defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
|
||||
#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
|
||||
#endif /* STM32F103xE || STM32F103xG */
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
|
||||
#endif /* STM32F105xC || STM32F107xC*/
|
||||
|
||||
#if defined(STM32F107xC)
|
||||
#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
|
||||
#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
|
||||
#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
|
||||
|
||||
/**
|
||||
* @brief Enable ETHERNET clock.
|
||||
*/
|
||||
#define __HAL_RCC_ETH_CLK_ENABLE() do { \
|
||||
__HAL_RCC_ETHMAC_CLK_ENABLE(); \
|
||||
__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
|
||||
__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
|
||||
} while(0U)
|
||||
/**
|
||||
* @brief Disable ETHERNET clock.
|
||||
*/
|
||||
#define __HAL_RCC_ETH_CLK_DISABLE() do { \
|
||||
__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
|
||||
__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
|
||||
__HAL_RCC_ETHMAC_CLK_DISABLE(); \
|
||||
} while(0U)
|
||||
|
||||
#endif /* STM32F107xC*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
|
||||
* @brief Get the enable or disable status of the AHB1 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
|
||||
|| defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
|
||||
|| defined (STM32F100xE)
|
||||
#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
|
||||
#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
|
||||
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
|
||||
|| defined(STM32F103xG) || defined (STM32F100xE)
|
||||
#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
|
||||
#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
|
||||
#if defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
|
||||
#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
|
||||
#endif /* STM32F103xE || STM32F103xG */
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
|
||||
#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
|
||||
#endif /* STM32F105xC || STM32F107xC*/
|
||||
#if defined(STM32F107xC)
|
||||
#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
|
||||
#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
|
||||
#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
|
||||
#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
|
||||
#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
|
||||
#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
|
||||
#endif /* STM32F107xC*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
|
||||
* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
|
||||
|| defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
|
||||
#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
|
||||
#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
|
||||
|| defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
|
||||
#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
|
||||
#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
|
||||
#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
|
||||
#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_USB_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
|
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
|
||||
|
||||
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
|
||||
|| defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_UART4_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_UART5_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_DAC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
|
||||
#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
|
||||
#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
|
||||
#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
|
||||
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
|
||||
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
|
||||
#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F100xB) || defined (STM32F100xE)
|
||||
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_DAC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_CEC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
|
||||
#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
|
||||
#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
|
||||
#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
|
||||
#endif /* STM32F100xB || STM32F100xE */
|
||||
|
||||
#ifdef STM32F100xE
|
||||
#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_UART4_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_UART5_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
|
||||
#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
|
||||
#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
|
||||
#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
|
||||
#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
|
||||
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
|
||||
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
|
||||
#endif /* STM32F100xE */
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F101xG) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
|
||||
#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
|
||||
#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
|
||||
#endif /* STM32F101xG || STM32F103xG*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
|
||||
* @brief Get the enable or disable status of the APB1 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
|
||||
|| defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
|
||||
#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
|
||||
#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
|
||||
#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
|
||||
|| defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
|
||||
#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
|
||||
#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
|
||||
#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
|
||||
#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
|
||||
#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
|
||||
#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
|
||||
#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
|
||||
#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
|
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
|
||||
#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
|
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
|
||||
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
|
||||
|| defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
|
||||
#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
|
||||
#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
|
||||
#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
|
||||
#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
|
||||
#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
|
||||
#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
|
||||
#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
|
||||
#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
|
||||
#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
|
||||
#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
|
||||
#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
|
||||
#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
|
||||
#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
|
||||
#if defined(STM32F100xB) || defined (STM32F100xE)
|
||||
#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
|
||||
#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
|
||||
#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
|
||||
#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
|
||||
#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
|
||||
#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
|
||||
#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
|
||||
#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
|
||||
#endif /* STM32F100xB || STM32F100xE */
|
||||
#ifdef STM32F100xE
|
||||
#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
|
||||
#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
|
||||
#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
|
||||
#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
|
||||
#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
|
||||
#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
|
||||
#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
|
||||
#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
|
||||
#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
|
||||
#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
|
||||
#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
|
||||
#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
|
||||
#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
|
||||
#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
|
||||
#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
|
||||
#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
|
||||
#endif /* STM32F100xE */
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
|
||||
#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
#if defined(STM32F101xG) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
|
||||
#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
|
||||
#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
|
||||
#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
|
||||
#endif /* STM32F101xG || STM32F103xG*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
|
||||
* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
|
||||
|| defined(STM32F103xG)
|
||||
#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
|
||||
#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
|
||||
|
||||
#if defined(STM32F100xB) || defined(STM32F100xE)
|
||||
#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
|
||||
#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
|
||||
#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
|
||||
#endif /* STM32F100xB || STM32F100xE */
|
||||
|
||||
#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
|
||||
|| defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
|
||||
|| defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
|
||||
|| defined(STM32F107xC)
|
||||
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
|
||||
#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
|
||||
|| defined(STM32F103xG)
|
||||
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
|
||||
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
|
||||
|
||||
#if defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
|
||||
#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
|
||||
#endif /* STM32F103xE || STM32F103xG */
|
||||
|
||||
#if defined(STM32F100xE)
|
||||
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
|
||||
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
|
||||
#endif /* STM32F100xE */
|
||||
|
||||
#if defined(STM32F101xG) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
|
||||
#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
|
||||
#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
|
||||
#endif /* STM32F101xG || STM32F103xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
|
||||
* @brief Get the enable or disable status of the APB2 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
|
||||
|| defined(STM32F103xG)
|
||||
#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
|
||||
#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
|
||||
#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
|
||||
#if defined(STM32F100xB) || defined(STM32F100xE)
|
||||
#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
|
||||
#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
|
||||
#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
|
||||
#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
|
||||
#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
|
||||
#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
|
||||
#endif /* STM32F100xB || STM32F100xE */
|
||||
#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
|
||||
|| defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
|
||||
|| defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
|
||||
|| defined(STM32F107xC)
|
||||
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
|
||||
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
|
||||
#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
|
||||
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
|
||||
|| defined(STM32F103xG)
|
||||
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
|
||||
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
|
||||
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
|
||||
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
|
||||
#if defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
|
||||
#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
|
||||
#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
|
||||
#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
|
||||
#endif /* STM32F103xE || STM32F103xG */
|
||||
#if defined(STM32F100xE)
|
||||
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
|
||||
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
|
||||
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
|
||||
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
|
||||
#endif /* STM32F100xE */
|
||||
#if defined(STM32F101xG) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
|
||||
#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
|
||||
#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
|
||||
#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
|
||||
#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
|
||||
#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
|
||||
#endif /* STM32F101xG || STM32F103xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
|
||||
* @brief Force or release AHB peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
|
||||
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
|
||||
#if defined(STM32F107xC)
|
||||
#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
|
||||
#endif /* STM32F107xC */
|
||||
|
||||
#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
|
||||
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
|
||||
#if defined(STM32F107xC)
|
||||
#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
|
||||
#endif /* STM32F107xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
|
||||
* @brief Force or release APB1 peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
|
||||
|| defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
|
||||
#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
|
||||
|
||||
#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
|
||||
#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
|
||||
|| defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
|
||||
#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
|
||||
#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
|
||||
#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
|
||||
|
||||
#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
|
||||
#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
|
||||
#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
|
||||
#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
|
||||
#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
|
||||
#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
|
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
|
||||
|
||||
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
|
||||
|| defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
|
||||
#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
|
||||
#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
|
||||
#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
|
||||
#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
|
||||
#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
|
||||
#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
|
||||
|
||||
#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
|
||||
#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
|
||||
#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
|
||||
#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
|
||||
#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
|
||||
#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
|
||||
#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F100xB) || defined (STM32F100xE)
|
||||
#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
|
||||
#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
|
||||
#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
|
||||
#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
|
||||
|
||||
#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
|
||||
#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
|
||||
#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
|
||||
#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
|
||||
#endif /* STM32F100xB || STM32F100xE */
|
||||
|
||||
#if defined (STM32F100xE)
|
||||
#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
|
||||
#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
|
||||
#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
|
||||
#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
|
||||
#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
|
||||
#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
|
||||
#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
|
||||
|
||||
#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
|
||||
#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
|
||||
#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
|
||||
#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
|
||||
#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
|
||||
#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
|
||||
#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
|
||||
#endif /* STM32F100xE */
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
|
||||
|
||||
#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F101xG) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
|
||||
#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
|
||||
#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
|
||||
|
||||
#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
|
||||
#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
|
||||
#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
|
||||
#endif /* STM32F101xG || STM32F103xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
|
||||
* @brief Force or release APB2 peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
|
||||
|| defined(STM32F103xG)
|
||||
#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
|
||||
|
||||
#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
|
||||
#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
|
||||
|
||||
#if defined(STM32F100xB) || defined(STM32F100xE)
|
||||
#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
|
||||
#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
|
||||
#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
|
||||
|
||||
#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
|
||||
#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
|
||||
#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
|
||||
#endif /* STM32F100xB || STM32F100xE */
|
||||
|
||||
#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
|
||||
|| defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
|
||||
|| defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
|
||||
|| defined(STM32F107xC)
|
||||
#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
|
||||
|
||||
#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
|
||||
#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
|
||||
|| defined(STM32F103xG)
|
||||
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
|
||||
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
|
||||
|
||||
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
|
||||
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
|
||||
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
|
||||
|
||||
#if defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
|
||||
#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
|
||||
|
||||
#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
|
||||
#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
|
||||
#endif /* STM32F103xE || STM32F103xG */
|
||||
|
||||
#if defined(STM32F100xE)
|
||||
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
|
||||
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
|
||||
|
||||
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
|
||||
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
|
||||
#endif /* STM32F100xE */
|
||||
|
||||
#if defined(STM32F101xG) || defined(STM32F103xG)
|
||||
#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
|
||||
#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
|
||||
#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
|
||||
|
||||
#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
|
||||
#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
|
||||
#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
|
||||
#endif /* STM32F101xG || STM32F103xG*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_HSE_Configuration HSE Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
|
||||
|| defined(STM32F100xE)
|
||||
/**
|
||||
* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
|
||||
* @note Predivision factor can not be changed if PLL is used as system clock
|
||||
* In this case, you have to select another source of the system clock, disable the PLL and
|
||||
* then change the HSE predivision factor.
|
||||
* @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
|
||||
* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
|
||||
*/
|
||||
#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
|
||||
#else
|
||||
/**
|
||||
* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
|
||||
* @note Predivision factor can not be changed if PLL is used as system clock
|
||||
* In this case, you have to select another source of the system clock, disable the PLL and
|
||||
* then change the HSE predivision factor.
|
||||
* @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
|
||||
* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
|
||||
*/
|
||||
#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
|
||||
MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
|
||||
|| defined(STM32F100xE)
|
||||
/**
|
||||
* @brief Macro to get prediv1 factor for PLL.
|
||||
*/
|
||||
#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
|
||||
|
||||
#else
|
||||
/**
|
||||
* @brief Macro to get prediv1 factor for PLL.
|
||||
*/
|
||||
#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Macros to enable the main PLLI2S.
|
||||
* @note After enabling the main PLLI2S, the application software should wait on
|
||||
* PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
|
||||
* be used as system clock source.
|
||||
* @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
|
||||
*/
|
||||
#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
|
||||
|
||||
/** @brief Macros to disable the main PLLI2S.
|
||||
* @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
|
||||
*/
|
||||
#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
|
||||
|
||||
/** @brief macros to configure the main PLLI2S multiplication factor.
|
||||
* @note This function must be used only when the main PLLI2S is disabled.
|
||||
*
|
||||
* @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8
|
||||
* @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9
|
||||
* @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10
|
||||
* @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11
|
||||
* @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12
|
||||
* @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13
|
||||
* @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14
|
||||
* @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16
|
||||
* @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20
|
||||
*
|
||||
*/
|
||||
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
|
||||
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
|
||||
* @brief Macros to configure clock source of different peripherals.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
/** @brief Macro to configure the USB clock.
|
||||
* @param __USBCLKSOURCE__ specifies the USB clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
|
||||
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
|
||||
*/
|
||||
#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the USB clock (USBCLK).
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
|
||||
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
|
||||
|
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
|
||||
/** @brief Macro to configure the USB OTSclock.
|
||||
* @param __USBCLKSOURCE__ specifies the USB clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
|
||||
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
|
||||
*/
|
||||
#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the USB clock (USBCLK).
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
|
||||
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
|
||||
* @param __ADCCLKSOURCE__ specifies the ADC clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
|
||||
* @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
|
||||
* @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
|
||||
* @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
|
||||
*/
|
||||
#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
|
||||
* @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
|
||||
* @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
|
||||
* @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
|
||||
/** @addtogroup RCCEx_HSE_Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
|
||||
* @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
|
||||
* In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
|
||||
* then change the PREDIV2 factor.
|
||||
* @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.
|
||||
* This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
|
||||
*/
|
||||
#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
|
||||
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Macro to get prediv2 factor for PLL2 & PLL3.
|
||||
*/
|
||||
#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx_PLLI2S_Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Macros to enable the main PLL2.
|
||||
* @note After enabling the main PLL2, the application software should wait on
|
||||
* PLL2RDY flag to be set indicating that PLL2 clock is stable and can
|
||||
* be used as system clock source.
|
||||
* @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
|
||||
*/
|
||||
#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE)
|
||||
|
||||
/** @brief Macros to disable the main PLL2.
|
||||
* @note The main PLL2 can not be disabled if it is used indirectly as system clock source
|
||||
* @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
|
||||
*/
|
||||
#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE)
|
||||
|
||||
/** @brief macros to configure the main PLL2 multiplication factor.
|
||||
* @note This function must be used only when the main PLL2 is disabled.
|
||||
*
|
||||
* @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8
|
||||
* @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9
|
||||
* @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10
|
||||
* @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11
|
||||
* @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12
|
||||
* @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13
|
||||
* @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14
|
||||
* @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16
|
||||
* @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20
|
||||
*
|
||||
*/
|
||||
#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
|
||||
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_I2S_Configuration I2S Configuration
|
||||
* @brief Macros to configure clock source of I2S peripherals.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Macro to configure the I2S2 clock.
|
||||
* @param __I2S2CLKSOURCE__ specifies the I2S2 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
|
||||
* @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
|
||||
*/
|
||||
#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the I2S2 clock (I2S2CLK).
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
|
||||
* @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
|
||||
*/
|
||||
#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
|
||||
|
||||
/** @brief Macro to configure the I2S3 clock.
|
||||
* @param __I2S2CLKSOURCE__ specifies the I2S3 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
|
||||
* @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
|
||||
*/
|
||||
#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the I2S3 clock (I2S3CLK).
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
|
||||
* @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
|
||||
*/
|
||||
#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RCCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
||||
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
/** @addtogroup RCCEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
|
||||
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
|
||||
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F105xC || STM32F107xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_RCC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
2123
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
Normal file
2123
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
Normal file
@@ -0,0 +1,2123 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_tim.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of TIM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_TIM_H
|
||||
#define STM32F1xx_HAL_TIM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup TIM_Exported_Types TIM Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TIM Time base Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
|
||||
uint32_t CounterMode; /*!< Specifies the counter mode.
|
||||
This parameter can be a value of @ref TIM_Counter_Mode */
|
||||
|
||||
uint32_t Period; /*!< Specifies the period value to be loaded into the active
|
||||
Auto-Reload Register at the next update event.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t ClockDivision; /*!< Specifies the clock division.
|
||||
This parameter can be a value of @ref TIM_ClockDivision */
|
||||
|
||||
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
|
||||
reaches zero, an update event is generated and counting restarts
|
||||
from the RCR value (N).
|
||||
This means in PWM mode that (N+1) corresponds to:
|
||||
- the number of PWM periods in edge-aligned mode
|
||||
- the number of half PWM period in center-aligned mode
|
||||
GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
|
||||
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
|
||||
This parameter can be a value of @ref TIM_AutoReloadPreload */
|
||||
} TIM_Base_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Output Compare Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OCMode; /*!< Specifies the TIM mode.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
|
||||
|
||||
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
|
||||
uint32_t OCPolarity; /*!< Specifies the output polarity.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
|
||||
|
||||
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
|
||||
@note This parameter is valid only for timer instances supporting break feature. */
|
||||
|
||||
uint32_t OCFastMode; /*!< Specifies the Fast mode state.
|
||||
This parameter can be a value of @ref TIM_Output_Fast_State
|
||||
@note This parameter is valid only in PWM1 and PWM2 mode. */
|
||||
|
||||
|
||||
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
|
||||
@note This parameter is valid only for timer instances supporting break feature. */
|
||||
|
||||
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
|
||||
@note This parameter is valid only for timer instances supporting break feature. */
|
||||
} TIM_OC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM One Pulse Mode Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OCMode; /*!< Specifies the TIM mode.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
|
||||
|
||||
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
|
||||
uint32_t OCPolarity; /*!< Specifies the output polarity.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
|
||||
|
||||
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
|
||||
@note This parameter is valid only for timer instances supporting break feature. */
|
||||
|
||||
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
|
||||
@note This parameter is valid only for timer instances supporting break feature. */
|
||||
|
||||
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
|
||||
@note This parameter is valid only for timer instances supporting break feature. */
|
||||
|
||||
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint32_t ICSelection; /*!< Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
|
||||
uint32_t ICFilter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
} TIM_OnePulse_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Input Capture Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint32_t ICSelection; /*!< Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
|
||||
uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint32_t ICFilter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
} TIM_IC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Encoder Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Encoder_Mode */
|
||||
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
|
||||
|
||||
uint32_t IC1Selection; /*!< Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
|
||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
|
||||
|
||||
uint32_t IC2Selection; /*!< Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
|
||||
uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint32_t IC2Filter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
} TIM_Encoder_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Clock Configuration Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockSource; /*!< TIM clock sources
|
||||
This parameter can be a value of @ref TIM_Clock_Source */
|
||||
uint32_t ClockPolarity; /*!< TIM clock polarity
|
||||
This parameter can be a value of @ref TIM_Clock_Polarity */
|
||||
uint32_t ClockPrescaler; /*!< TIM clock prescaler
|
||||
This parameter can be a value of @ref TIM_Clock_Prescaler */
|
||||
uint32_t ClockFilter; /*!< TIM clock filter
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
} TIM_ClockConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Clear Input Configuration Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClearInputState; /*!< TIM clear Input state
|
||||
This parameter can be ENABLE or DISABLE */
|
||||
uint32_t ClearInputSource; /*!< TIM clear Input sources
|
||||
This parameter can be a value of @ref TIM_ClearInput_Source */
|
||||
uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
|
||||
This parameter can be a value of @ref TIM_ClearInput_Polarity */
|
||||
uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
|
||||
This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
|
||||
uint32_t ClearInputFilter; /*!< TIM Clear Input filter
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
} TIM_ClearInputConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Master configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
|
||||
This parameter can be a value of @ref TIM_Master_Mode_Selection */
|
||||
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
|
||||
This parameter can be a value of @ref TIM_Master_Slave_Mode
|
||||
@note When the Master/slave mode is enabled, the effect of
|
||||
an event on the trigger input (TRGI) is delayed to allow a
|
||||
perfect synchronization between the current timer and its
|
||||
slaves (through TRGO). It is not mandatory in case of timer
|
||||
synchronization mode. */
|
||||
} TIM_MasterConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Slave configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SlaveMode; /*!< Slave mode selection
|
||||
This parameter can be a value of @ref TIM_Slave_Mode */
|
||||
uint32_t InputTrigger; /*!< Input Trigger source
|
||||
This parameter can be a value of @ref TIM_Trigger_Selection */
|
||||
uint32_t TriggerPolarity; /*!< Input Trigger polarity
|
||||
This parameter can be a value of @ref TIM_Trigger_Polarity */
|
||||
uint32_t TriggerPrescaler; /*!< Input trigger prescaler
|
||||
This parameter can be a value of @ref TIM_Trigger_Prescaler */
|
||||
uint32_t TriggerFilter; /*!< Input trigger filter
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
} TIM_SlaveConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Break input(s) and Dead time configuration Structure definition
|
||||
* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
|
||||
* filter and polarity.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OffStateRunMode; /*!< TIM off state in run mode
|
||||
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
|
||||
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
|
||||
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||
uint32_t LockLevel; /*!< TIM Lock level
|
||||
This parameter can be a value of @ref TIM_Lock_level */
|
||||
uint32_t DeadTime; /*!< TIM dead Time
|
||||
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint32_t BreakState; /*!< TIM Break State
|
||||
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
|
||||
uint32_t BreakPolarity; /*!< TIM Break input polarity
|
||||
This parameter can be a value of @ref TIM_Break_Polarity */
|
||||
uint32_t BreakFilter; /*!< Specifies the break input filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
|
||||
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
||||
} TIM_BreakDeadTimeConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
|
||||
HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
|
||||
HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
|
||||
} HAL_TIM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Channel States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
|
||||
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
|
||||
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
|
||||
} HAL_TIM_ChannelStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA Burst States definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
|
||||
HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
|
||||
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
|
||||
} HAL_TIM_DMABurstStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Active channel structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
|
||||
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
|
||||
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
|
||||
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
|
||||
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
|
||||
} HAL_TIM_ActiveChannel;
|
||||
|
||||
/**
|
||||
* @brief TIM Time Base Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __TIM_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
{
|
||||
TIM_TypeDef *Instance; /*!< Register base address */
|
||||
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
|
||||
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
|
||||
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
|
||||
This array is accessed by a @ref DMA_Handle_index */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
|
||||
__IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */
|
||||
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
|
||||
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
|
||||
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
|
||||
void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
|
||||
void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
|
||||
void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
|
||||
void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
|
||||
void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
|
||||
void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
|
||||
void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
|
||||
void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
|
||||
void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
|
||||
void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
|
||||
void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
|
||||
void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
|
||||
void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
|
||||
void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
|
||||
void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
|
||||
void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
|
||||
void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
|
||||
void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
|
||||
void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
|
||||
void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
|
||||
void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
|
||||
void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
|
||||
void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
|
||||
void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
|
||||
void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
|
||||
void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
} TIM_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL TIM Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
|
||||
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
|
||||
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
|
||||
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
|
||||
, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
|
||||
, HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
|
||||
} HAL_TIM_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL TIM Callback pointer definition
|
||||
*/
|
||||
typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
|
||||
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported types -----------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup TIM_Exported_Constants TIM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
|
||||
#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
|
||||
* @{
|
||||
*/
|
||||
#define TIM_DMABASE_CR1 0x00000000U
|
||||
#define TIM_DMABASE_CR2 0x00000001U
|
||||
#define TIM_DMABASE_SMCR 0x00000002U
|
||||
#define TIM_DMABASE_DIER 0x00000003U
|
||||
#define TIM_DMABASE_SR 0x00000004U
|
||||
#define TIM_DMABASE_EGR 0x00000005U
|
||||
#define TIM_DMABASE_CCMR1 0x00000006U
|
||||
#define TIM_DMABASE_CCMR2 0x00000007U
|
||||
#define TIM_DMABASE_CCER 0x00000008U
|
||||
#define TIM_DMABASE_CNT 0x00000009U
|
||||
#define TIM_DMABASE_PSC 0x0000000AU
|
||||
#define TIM_DMABASE_ARR 0x0000000BU
|
||||
#define TIM_DMABASE_RCR 0x0000000CU
|
||||
#define TIM_DMABASE_CCR1 0x0000000DU
|
||||
#define TIM_DMABASE_CCR2 0x0000000EU
|
||||
#define TIM_DMABASE_CCR3 0x0000000FU
|
||||
#define TIM_DMABASE_CCR4 0x00000010U
|
||||
#define TIM_DMABASE_BDTR 0x00000011U
|
||||
#define TIM_DMABASE_DCR 0x00000012U
|
||||
#define TIM_DMABASE_DMAR 0x00000013U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Event_Source TIM Event Source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
|
||||
#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
|
||||
#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
|
||||
#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
|
||||
#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
|
||||
#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
|
||||
#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
|
||||
#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
|
||||
#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
|
||||
#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
|
||||
#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
|
||||
#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
|
||||
#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
|
||||
#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Counter_Mode TIM Counter Mode
|
||||
* @{
|
||||
*/
|
||||
#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
|
||||
#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
|
||||
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
|
||||
#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
|
||||
#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_ClockDivision TIM Clock Division
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
|
||||
#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
|
||||
#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_State TIM Output Compare State
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
|
||||
#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
|
||||
* @{
|
||||
*/
|
||||
#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
|
||||
#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Fast_State TIM Output Fast State
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
|
||||
#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
|
||||
#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
|
||||
#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
|
||||
#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
|
||||
#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
|
||||
#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
|
||||
#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
|
||||
#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
|
||||
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
||||
connected to IC1, IC2, IC3 or IC4, respectively */
|
||||
#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
||||
connected to IC2, IC1, IC4 or IC3, respectively */
|
||||
#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
|
||||
#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
|
||||
#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
|
||||
#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
|
||||
#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
|
||||
#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
|
||||
#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
|
||||
* @{
|
||||
*/
|
||||
#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
|
||||
#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
|
||||
#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
|
||||
#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
|
||||
#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
|
||||
#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
|
||||
#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
|
||||
#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Commutation_Source TIM Commutation Source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
|
||||
#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_DMA_sources TIM DMA Sources
|
||||
* @{
|
||||
*/
|
||||
#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
|
||||
#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
|
||||
#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
|
||||
#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
|
||||
#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
|
||||
#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
|
||||
#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Flag_definition TIM Flag Definition
|
||||
* @{
|
||||
*/
|
||||
#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
|
||||
#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
|
||||
#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
|
||||
#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
|
||||
#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
|
||||
#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
|
||||
#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
|
||||
#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
|
||||
#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
|
||||
#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
|
||||
#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
|
||||
#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Channel TIM Channel
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
|
||||
#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
|
||||
#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
|
||||
#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
|
||||
#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Clock_Source TIM Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
|
||||
#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
|
||||
#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
|
||||
#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
|
||||
#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
|
||||
#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
|
||||
#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
|
||||
#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
|
||||
#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
|
||||
#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
|
||||
#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
|
||||
#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
|
||||
#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
|
||||
#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
|
||||
#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
|
||||
#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
|
||||
#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
|
||||
#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
|
||||
#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
|
||||
#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
|
||||
#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
|
||||
#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
|
||||
#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup TIM_Lock_level TIM Lock level
|
||||
* @{
|
||||
*/
|
||||
#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
|
||||
#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
|
||||
#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
|
||||
#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
|
||||
#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
|
||||
#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
|
||||
* @{
|
||||
*/
|
||||
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
|
||||
#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
|
||||
(if none of the break inputs BRK and BRK2 is active) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
|
||||
#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
|
||||
#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
|
||||
#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
|
||||
#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
|
||||
#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
|
||||
#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
|
||||
#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
|
||||
* @{
|
||||
*/
|
||||
#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
|
||||
#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Slave_Mode TIM Slave mode
|
||||
* @{
|
||||
*/
|
||||
#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
|
||||
#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
|
||||
#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
|
||||
#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
|
||||
#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
|
||||
#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
|
||||
#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
|
||||
#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
|
||||
#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
|
||||
#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
|
||||
#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
|
||||
#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
|
||||
#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
|
||||
#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
|
||||
#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
|
||||
#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
|
||||
#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
|
||||
#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
|
||||
#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
|
||||
#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
|
||||
#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
|
||||
#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
|
||||
#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
|
||||
#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
|
||||
#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
|
||||
#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
|
||||
#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
|
||||
#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
|
||||
* @{
|
||||
*/
|
||||
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Handle_index TIM DMA Handle Index
|
||||
* @{
|
||||
*/
|
||||
#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
|
||||
#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
|
||||
#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
|
||||
#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
|
||||
#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
|
||||
#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
|
||||
#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
|
||||
#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
|
||||
#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
|
||||
#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported constants -------------------------------------------------*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup TIM_Exported_Macros TIM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset TIM handle state.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
|
||||
(__HANDLE__)->Base_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
|
||||
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
|
||||
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the TIM peripheral.
|
||||
* @param __HANDLE__ TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
|
||||
|
||||
/**
|
||||
* @brief Enable the TIM main Output.
|
||||
* @param __HANDLE__ TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
|
||||
|
||||
/**
|
||||
* @brief Disable the TIM peripheral.
|
||||
* @param __HANDLE__ TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_DISABLE(__HANDLE__) \
|
||||
do { \
|
||||
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
|
||||
{ \
|
||||
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
|
||||
{ \
|
||||
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the TIM main Output.
|
||||
* @param __HANDLE__ TIM handle
|
||||
* @retval None
|
||||
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
|
||||
*/
|
||||
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
|
||||
do { \
|
||||
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
|
||||
{ \
|
||||
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
|
||||
{ \
|
||||
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the TIM main Output.
|
||||
* @param __HANDLE__ TIM handle
|
||||
* @retval None
|
||||
* @note The Main Output Enable of a timer instance is disabled unconditionally
|
||||
*/
|
||||
#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
|
||||
|
||||
/** @brief Enable the specified TIM interrupt.
|
||||
* @param __HANDLE__ specifies the TIM Handle.
|
||||
* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_IT_UPDATE: Update interrupt
|
||||
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
|
||||
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
|
||||
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
|
||||
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
|
||||
* @arg TIM_IT_COM: Commutation interrupt
|
||||
* @arg TIM_IT_TRIGGER: Trigger interrupt
|
||||
* @arg TIM_IT_BREAK: Break interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified TIM interrupt.
|
||||
* @param __HANDLE__ specifies the TIM Handle.
|
||||
* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_IT_UPDATE: Update interrupt
|
||||
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
|
||||
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
|
||||
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
|
||||
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
|
||||
* @arg TIM_IT_COM: Commutation interrupt
|
||||
* @arg TIM_IT_TRIGGER: Trigger interrupt
|
||||
* @arg TIM_IT_BREAK: Break interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Enable the specified DMA request.
|
||||
* @param __HANDLE__ specifies the TIM Handle.
|
||||
* @param __DMA__ specifies the TIM DMA request to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_DMA_UPDATE: Update DMA request
|
||||
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
|
||||
* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
|
||||
* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
|
||||
* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
|
||||
* @arg TIM_DMA_COM: Commutation DMA request
|
||||
* @arg TIM_DMA_TRIGGER: Trigger DMA request
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
|
||||
|
||||
/** @brief Disable the specified DMA request.
|
||||
* @param __HANDLE__ specifies the TIM Handle.
|
||||
* @param __DMA__ specifies the TIM DMA request to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_DMA_UPDATE: Update DMA request
|
||||
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
|
||||
* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
|
||||
* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
|
||||
* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
|
||||
* @arg TIM_DMA_COM: Commutation DMA request
|
||||
* @arg TIM_DMA_TRIGGER: Trigger DMA request
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
|
||||
|
||||
/** @brief Check whether the specified TIM interrupt flag is set or not.
|
||||
* @param __HANDLE__ specifies the TIM Handle.
|
||||
* @param __FLAG__ specifies the TIM interrupt flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_FLAG_UPDATE: Update interrupt flag
|
||||
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
|
||||
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
|
||||
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
|
||||
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
|
||||
* @arg TIM_FLAG_COM: Commutation interrupt flag
|
||||
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
|
||||
* @arg TIM_FLAG_BREAK: Break interrupt flag
|
||||
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
|
||||
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
|
||||
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
|
||||
* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the specified TIM interrupt flag.
|
||||
* @param __HANDLE__ specifies the TIM Handle.
|
||||
* @param __FLAG__ specifies the TIM interrupt flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_FLAG_UPDATE: Update interrupt flag
|
||||
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
|
||||
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
|
||||
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
|
||||
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
|
||||
* @arg TIM_FLAG_COM: Commutation interrupt flag
|
||||
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
|
||||
* @arg TIM_FLAG_BREAK: Break interrupt flag
|
||||
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
|
||||
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
|
||||
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
|
||||
* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified TIM interrupt source is enabled or not.
|
||||
* @param __HANDLE__ TIM handle
|
||||
* @param __INTERRUPT__ specifies the TIM interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_IT_UPDATE: Update interrupt
|
||||
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
|
||||
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
|
||||
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
|
||||
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
|
||||
* @arg TIM_IT_COM: Commutation interrupt
|
||||
* @arg TIM_IT_TRIGGER: Trigger interrupt
|
||||
* @arg TIM_IT_BREAK: Break interrupt
|
||||
* @retval The state of TIM_IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
|
||||
== (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the TIM interrupt pending bits.
|
||||
* @param __HANDLE__ TIM handle
|
||||
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_IT_UPDATE: Update interrupt
|
||||
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
|
||||
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
|
||||
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
|
||||
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
|
||||
* @arg TIM_IT_COM: Commutation interrupt
|
||||
* @arg TIM_IT_TRIGGER: Trigger interrupt
|
||||
* @arg TIM_IT_BREAK: Break interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Indicates whether or not the TIM Counter is used as downcounter.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
|
||||
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
|
||||
mode.
|
||||
*/
|
||||
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
|
||||
|
||||
/**
|
||||
* @brief Set the TIM Prescaler on runtime.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __PRESC__ specifies the Prescaler new value.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
|
||||
|
||||
/**
|
||||
* @brief Set the TIM Counter Register value on runtime.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __COUNTER__ specifies the Counter register new value.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
|
||||
|
||||
/**
|
||||
* @brief Get the TIM Counter Register value on runtime.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
|
||||
*/
|
||||
#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
|
||||
|
||||
/**
|
||||
* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __AUTORELOAD__ specifies the Counter register new value.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
|
||||
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Get the TIM Autoreload Register value on runtime.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
|
||||
*/
|
||||
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
|
||||
|
||||
/**
|
||||
* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __CKD__ specifies the clock division value.
|
||||
* This parameter can be one of the following value:
|
||||
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
|
||||
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
|
||||
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
|
||||
(__HANDLE__)->Instance->CR1 |= (__CKD__); \
|
||||
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Get the TIM Clock Division value on runtime.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @retval The clock division can be one of the following values:
|
||||
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
|
||||
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
|
||||
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
|
||||
*/
|
||||
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
|
||||
|
||||
/**
|
||||
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __CHANNEL__ TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @param __ICPSC__ specifies the Input Capture4 prescaler new value.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_ICPSC_DIV1: no prescaler
|
||||
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
|
||||
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
|
||||
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
|
||||
do{ \
|
||||
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
|
||||
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Get the TIM Input Capture prescaler on runtime.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __CHANNEL__ TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
|
||||
* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
|
||||
* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
|
||||
* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
|
||||
* @retval The input capture prescaler can be one of the following values:
|
||||
* @arg TIM_ICPSC_DIV1: no prescaler
|
||||
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
|
||||
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
|
||||
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
|
||||
*/
|
||||
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
|
||||
(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
|
||||
|
||||
/**
|
||||
* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __CHANNEL__ TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @param __COMPARE__ specifies the Capture Compare register new value.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
|
||||
((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
|
||||
|
||||
/**
|
||||
* @brief Get the TIM Capture Compare Register value on runtime.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __CHANNEL__ TIM Channel associated with the capture compare register
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: get capture/compare 1 register value
|
||||
* @arg TIM_CHANNEL_2: get capture/compare 2 register value
|
||||
* @arg TIM_CHANNEL_3: get capture/compare 3 register value
|
||||
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
|
||||
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
|
||||
*/
|
||||
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
|
||||
((__HANDLE__)->Instance->CCR4))
|
||||
|
||||
/**
|
||||
* @brief Set the TIM Output compare preload.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __CHANNEL__ TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
|
||||
((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
|
||||
|
||||
/**
|
||||
* @brief Reset the TIM Output compare preload.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __CHANNEL__ TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
|
||||
((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
|
||||
|
||||
/**
|
||||
* @brief Enable fast mode for a given channel.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __CHANNEL__ TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @note When fast mode is enabled an active edge on the trigger input acts
|
||||
* like a compare match on CCx output. Delay to sample the trigger
|
||||
* input and to activate CCx output is reduced to 3 clock cycles.
|
||||
* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
|
||||
((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
|
||||
|
||||
/**
|
||||
* @brief Disable fast mode for a given channel.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __CHANNEL__ TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @note When fast mode is disabled CCx output behaves normally depending
|
||||
* on counter and CCRx values even when the trigger is ON. The minimum
|
||||
* delay to activate CCx output when an active edge occurs on the
|
||||
* trigger input is 5 clock cycles.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
|
||||
((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
|
||||
|
||||
/**
|
||||
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @note When the URS bit of the TIMx_CR1 register is set, only counter
|
||||
* overflow/underflow generates an update interrupt or DMA request (if
|
||||
* enabled)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
|
||||
|
||||
/**
|
||||
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @note When the URS bit of the TIMx_CR1 register is reset, any of the
|
||||
* following events generate an update interrupt or DMA request (if
|
||||
* enabled):
|
||||
* _ Counter overflow underflow
|
||||
* _ Setting the UG bit
|
||||
* _ Update generation through the slave mode controller
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
|
||||
|
||||
/**
|
||||
* @brief Set the TIM Capture x input polarity on runtime.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __CHANNEL__ TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @param __POLARITY__ Polarity for TIx source
|
||||
* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
|
||||
* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
|
||||
* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
|
||||
do{ \
|
||||
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
|
||||
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported macros ----------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup TIM_Private_Constants TIM Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* The counter of a timer instance is disabled only if all the CCx and CCxN
|
||||
channels have been disabled */
|
||||
#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
|
||||
#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private constants --------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup TIM_Private_Macros TIM Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
|
||||
((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
|
||||
|
||||
#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
|
||||
((__BASE__) == TIM_DMABASE_CR2) || \
|
||||
((__BASE__) == TIM_DMABASE_SMCR) || \
|
||||
((__BASE__) == TIM_DMABASE_DIER) || \
|
||||
((__BASE__) == TIM_DMABASE_SR) || \
|
||||
((__BASE__) == TIM_DMABASE_EGR) || \
|
||||
((__BASE__) == TIM_DMABASE_CCMR1) || \
|
||||
((__BASE__) == TIM_DMABASE_CCMR2) || \
|
||||
((__BASE__) == TIM_DMABASE_CCER) || \
|
||||
((__BASE__) == TIM_DMABASE_CNT) || \
|
||||
((__BASE__) == TIM_DMABASE_PSC) || \
|
||||
((__BASE__) == TIM_DMABASE_ARR) || \
|
||||
((__BASE__) == TIM_DMABASE_RCR) || \
|
||||
((__BASE__) == TIM_DMABASE_CCR1) || \
|
||||
((__BASE__) == TIM_DMABASE_CCR2) || \
|
||||
((__BASE__) == TIM_DMABASE_CCR3) || \
|
||||
((__BASE__) == TIM_DMABASE_CCR4) || \
|
||||
((__BASE__) == TIM_DMABASE_BDTR))
|
||||
|
||||
#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
|
||||
|
||||
#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
|
||||
((__MODE__) == TIM_COUNTERMODE_DOWN) || \
|
||||
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
|
||||
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
|
||||
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
|
||||
|
||||
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
|
||||
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
|
||||
((__DIV__) == TIM_CLOCKDIVISION_DIV4))
|
||||
|
||||
#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
|
||||
((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
|
||||
|
||||
#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
|
||||
((__STATE__) == TIM_OCFAST_ENABLE))
|
||||
|
||||
#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
|
||||
((__POLARITY__) == TIM_OCPOLARITY_LOW))
|
||||
|
||||
#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
|
||||
((__POLARITY__) == TIM_OCNPOLARITY_LOW))
|
||||
|
||||
#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
|
||||
((__STATE__) == TIM_OCIDLESTATE_RESET))
|
||||
|
||||
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
|
||||
((__STATE__) == TIM_OCNIDLESTATE_RESET))
|
||||
|
||||
#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
|
||||
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
|
||||
|
||||
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
|
||||
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
|
||||
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
|
||||
|
||||
#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
|
||||
((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
|
||||
((__SELECTION__) == TIM_ICSELECTION_TRC))
|
||||
|
||||
#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
|
||||
((__PRESCALER__) == TIM_ICPSC_DIV2) || \
|
||||
((__PRESCALER__) == TIM_ICPSC_DIV4) || \
|
||||
((__PRESCALER__) == TIM_ICPSC_DIV8))
|
||||
|
||||
#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
|
||||
((__MODE__) == TIM_OPMODE_REPETITIVE))
|
||||
|
||||
#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
|
||||
((__MODE__) == TIM_ENCODERMODE_TI2) || \
|
||||
((__MODE__) == TIM_ENCODERMODE_TI12))
|
||||
|
||||
#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
|
||||
|
||||
#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_ALL))
|
||||
|
||||
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_3))
|
||||
|
||||
#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
|
||||
|
||||
#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
|
||||
((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
|
||||
((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
|
||||
((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
|
||||
((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
|
||||
|
||||
#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
|
||||
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
|
||||
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
|
||||
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
|
||||
|
||||
#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
|
||||
|
||||
#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
|
||||
((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
|
||||
|
||||
#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
|
||||
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
|
||||
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
|
||||
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
|
||||
|
||||
#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
|
||||
|
||||
#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
|
||||
((__STATE__) == TIM_OSSR_DISABLE))
|
||||
|
||||
#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
|
||||
((__STATE__) == TIM_OSSI_DISABLE))
|
||||
|
||||
#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
|
||||
((__LEVEL__) == TIM_LOCKLEVEL_1) || \
|
||||
((__LEVEL__) == TIM_LOCKLEVEL_2) || \
|
||||
((__LEVEL__) == TIM_LOCKLEVEL_3))
|
||||
|
||||
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
|
||||
|
||||
|
||||
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
|
||||
((__STATE__) == TIM_BREAK_DISABLE))
|
||||
|
||||
#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
|
||||
((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
|
||||
|
||||
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
|
||||
((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
|
||||
|
||||
#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
|
||||
((__SOURCE__) == TIM_TRGO_ENABLE) || \
|
||||
((__SOURCE__) == TIM_TRGO_UPDATE) || \
|
||||
((__SOURCE__) == TIM_TRGO_OC1) || \
|
||||
((__SOURCE__) == TIM_TRGO_OC1REF) || \
|
||||
((__SOURCE__) == TIM_TRGO_OC2REF) || \
|
||||
((__SOURCE__) == TIM_TRGO_OC3REF) || \
|
||||
((__SOURCE__) == TIM_TRGO_OC4REF))
|
||||
|
||||
#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
|
||||
((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
|
||||
|
||||
#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
|
||||
((__MODE__) == TIM_SLAVEMODE_RESET) || \
|
||||
((__MODE__) == TIM_SLAVEMODE_GATED) || \
|
||||
((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
|
||||
((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
|
||||
|
||||
#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_PWM2))
|
||||
|
||||
#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
|
||||
((__MODE__) == TIM_OCMODE_ACTIVE) || \
|
||||
((__MODE__) == TIM_OCMODE_INACTIVE) || \
|
||||
((__MODE__) == TIM_OCMODE_TOGGLE) || \
|
||||
((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
|
||||
((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
|
||||
|
||||
#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
|
||||
((__SELECTION__) == TIM_TS_ITR1) || \
|
||||
((__SELECTION__) == TIM_TS_ITR2) || \
|
||||
((__SELECTION__) == TIM_TS_ITR3) || \
|
||||
((__SELECTION__) == TIM_TS_TI1F_ED) || \
|
||||
((__SELECTION__) == TIM_TS_TI1FP1) || \
|
||||
((__SELECTION__) == TIM_TS_TI2FP2) || \
|
||||
((__SELECTION__) == TIM_TS_ETRF))
|
||||
|
||||
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
|
||||
((__SELECTION__) == TIM_TS_ITR1) || \
|
||||
((__SELECTION__) == TIM_TS_ITR2) || \
|
||||
((__SELECTION__) == TIM_TS_ITR3) || \
|
||||
((__SELECTION__) == TIM_TS_NONE))
|
||||
|
||||
#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
|
||||
((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
|
||||
((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
|
||||
((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
|
||||
((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
|
||||
|
||||
#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
|
||||
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
|
||||
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
|
||||
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
|
||||
|
||||
#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
|
||||
|
||||
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
|
||||
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
|
||||
|
||||
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
|
||||
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
|
||||
|
||||
#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
|
||||
|
||||
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
|
||||
|
||||
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
|
||||
|
||||
#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
|
||||
|
||||
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
|
||||
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
|
||||
|
||||
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
|
||||
((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
|
||||
|
||||
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
|
||||
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
|
||||
|
||||
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
|
||||
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
|
||||
(__HANDLE__)->ChannelState[3])
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
|
||||
(__HANDLE__)->ChannelNState[3])
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macros -----------------------------------------------------*/
|
||||
|
||||
/* Include TIM HAL Extended module */
|
||||
#include "stm32f1xx_hal_tim_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TIM_Exported_Functions TIM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
|
||||
* @brief Time Base functions
|
||||
* @{
|
||||
*/
|
||||
/* Time Base functions ********************************************************/
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
|
||||
* @brief TIM Output Compare functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Output Compare functions *********************************************/
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
|
||||
* @brief TIM PWM functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer PWM functions ********************************************************/
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
|
||||
* @brief TIM Input Capture functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Input Capture functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
|
||||
* @brief TIM One Pulse functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer One Pulse functions **************************************************/
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
|
||||
* @brief TIM Encoder functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Encoder functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
|
||||
uint32_t *pData2, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
|
||||
* @brief IRQ handler management
|
||||
* @{
|
||||
*/
|
||||
/* Interrupt Handler functions ***********************************************/
|
||||
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Control functions *********************************************************/
|
||||
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
|
||||
uint32_t OutputChannel, uint32_t InputChannel);
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
|
||||
uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
|
||||
uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
|
||||
uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
|
||||
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
|
||||
* @brief TIM Callbacks functions
|
||||
* @{
|
||||
*/
|
||||
/* Callback in non blocking modes (Interrupt and DMA) *************************/
|
||||
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
|
||||
pTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Peripheral Channel state functions ************************************************/
|
||||
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private functions----------------------------------------------------------*/
|
||||
/** @defgroup TIM_Private_Functions TIM Private Functions
|
||||
* @{
|
||||
*/
|
||||
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
|
||||
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
|
||||
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
|
||||
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
||||
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
|
||||
|
||||
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMAError(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
|
||||
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
void TIM_ResetCallback(TIM_HandleTypeDef *htim);
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private functions --------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F1xx_HAL_TIM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
262
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
Normal file
262
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
Normal file
@@ -0,0 +1,262 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_tim_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of TIM HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F1xx_HAL_TIM_EX_H
|
||||
#define STM32F1xx_HAL_TIM_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TIM Hall sensor Configuration Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
} TIM_HallSensor_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported types -----------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Remap TIM Extended Remapping
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported constants -------------------------------------------------*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported macro -----------------------------------------------------*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macro ------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
||||
* @brief Timer Hall Sensor functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Hall Sensor functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
||||
* @brief Timer Complementary Output Compare functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary Output Compare functions *****************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
||||
* @brief Timer Complementary PWM functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary PWM functions ****************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
||||
* @brief Timer Complementary One Pulse functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary One Pulse functions **********************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
||||
TIM_MasterConfigTypeDef *sMasterConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
||||
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
||||
* @brief Extended Callbacks functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Callback **********************************************************/
|
||||
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
||||
* @brief Extended Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Peripheral State functions ***************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private functions----------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private functions --------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F1xx_HAL_TIM_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user