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42
Source/External/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm
vendored
Normal file
42
Source/External/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm
vendored
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@@ -0,0 +1,42 @@
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||||
;; TI File $Revision: /main/1 $
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;; Checkin $Date: July 30, 2007 10:29:23 $
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;;###########################################################################
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;;
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;; FILE: ADC_cal.asm
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;;
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;; TITLE: 2833x Boot Rom ADC Cal routine.
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;;
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;; Functions:
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;;
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;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers
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;; Notes:
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;;
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;;###########################################################################
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;; $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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;; $Release Date: August 1, 2008 $
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;;###########################################################################
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.def _ADC_cal
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.asg "0x711C", ADCREFSEL_LOC
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;-----------------------------------------------
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; _ADC_cal
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;-----------------------------------------------
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;-----------------------------------------------
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; This is the ADC cal routine.This routine is programmed into
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; reserved memory by the factory. 0xAAAA and 0xBBBB are place-
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; holders for calibration data.
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;The actual values programmed by TI are device specific.
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;
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; This function assumes that the clocks have been
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; enabled to the ADC module.
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;-----------------------------------------------
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.sect ".adc_cal"
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_ADC_cal
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MOVW DP, #ADCREFSEL_LOC >> 6
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MOV @28, #0xAAAA ; actual value may not be 0xAAAA
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MOV @29, #0xBBBB ; actual value may not be 0xBBBB
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LRETR
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;eof ----------
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64
Source/External/v120/DSP2833x_common/source/DSP2833x_Adc.c
vendored
Normal file
64
Source/External/v120/DSP2833x_common/source/DSP2833x_Adc.c
vendored
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@@ -0,0 +1,64 @@
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||||
// TI File $Revision: /main/5 $
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// Checkin $Date: October 23, 2007 13:34:09 $
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//###########################################################################
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//
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// FILE: DSP2833x_Adc.c
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//
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// TITLE: DSP2833x ADC Initialization & Support Functions.
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
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#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
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#define ADC_usDELAY 5000L
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//---------------------------------------------------------------------------
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// InitAdc:
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//---------------------------------------------------------------------------
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// This function initializes ADC to a known state.
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//
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void InitAdc(void)
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{
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extern void DSP28x_usDelay(Uint32 Count);
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// *IMPORTANT*
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// The ADC_cal function, which copies the ADC calibration values from TI reserved
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// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
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// Boot ROM. If the boot ROM code is bypassed during the debug process, the
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// following function MUST be called for the ADC to function according
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// to specification. The clocks to the ADC MUST be enabled before calling this
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// function.
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// See the device data manual and/or the ADC Reference
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// Manual for more information.
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
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ADC_cal();
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EDIS;
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// To powerup the ADC the ADCENCLK bit should be set first to enable
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// clocks, followed by powering up the bandgap, reference circuitry, and ADC core.
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// Before the first conversion is performed a 5ms delay must be observed
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// after power up to give all analog circuits time to power up and settle
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// Please note that for the delay function below to operate correctly the
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// CPU_RATE define statement in the DSP2833x_Examples.h file must
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// contain the correct CPU clock period in nanoseconds.
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AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits
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DELAY_US(ADC_usDELAY); // Delay before converting ADC channels
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//pause_us(50L);
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}
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//===========================================================================
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// End of file.
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//===========================================================================
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67
Source/External/v120/DSP2833x_common/source/DSP2833x_CSMPasswords.asm
vendored
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67
Source/External/v120/DSP2833x_common/source/DSP2833x_CSMPasswords.asm
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;// TI File $Revision: /main/3 $
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;// Checkin $Date: June 26, 2007 16:41:07 $
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;//###########################################################################
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;//
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;// FILE: DSP2833x_CSMPasswords.asm
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;//
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;// TITLE: DSP2833x Code Security Module Passwords.
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;//
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;// DESCRIPTION:
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;//
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;// This file is used to specify password values to
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;// program into the CSM password locations in Flash
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;// at 0x33FFF8 - 0x33FFFF.
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;//
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;// In addition, the reserved locations 0x33FF80 - 0X33fff5 are
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;// all programmed to 0x0000
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;//
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;//###########################################################################
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;//
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;// Original source based on D.A.
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;//
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;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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;// $Release Date: August 1, 2008 $
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;//###########################################################################
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; The "csmpasswords" section contains the actual CSM passwords that will be
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; linked and programmed into to the CSM password locations (PWL) in flash.
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; These passwords must be known in order to unlock the CSM module.
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; All 0xFFFF's (erased) is the default value for the password locations (PWL).
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; It is recommended that all passwords be left as 0xFFFF during code
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; development. Passwords of 0xFFFF do not activate code security and dummy
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; reads of the CSM PWL registers is all that is required to unlock the CSM.
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; When code development is complete, modify the passwords to activate the
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; code security module.
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.sect "csmpasswds"
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.int 0xFFFF ;PWL0 (LSW of 128-bit password)
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.int 0xFFFF ;PWL1
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.int 0xFFFF ;PWL2
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.int 0xFFFF ;PWL3
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.int 0xFFFF ;PWL4
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.int 0xFFFF ;PWL5
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.int 0xFFFF ;PWL6
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.int 0xFFFF ;PWL7 (MSW of 128-bit password)
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;----------------------------------------------------------------------
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||||
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||||
; For code security operation, all addresses between 0x33FF80 and
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; 0X33fff5 cannot be used as program code or data. These locations
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; must be programmed to 0x0000 when the code security password locations
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; (PWL) are programmed. If security is not a concern, then these addresses
|
||||
; can be used for code or data.
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||||
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; The section "csm_rsvd" can be used to program these locations to 0x0000.
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.sect "csm_rsvd"
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.loop (33FFF5h - 33FF80h + 1)
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.int 0x0000
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.endloop
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;//===========================================================================
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||||
;// End of file.
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;//===========================================================================
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||||
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||||
86
Source/External/v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm
vendored
Normal file
86
Source/External/v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm
vendored
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@@ -0,0 +1,86 @@
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;// TI File $Revision: /main/1 $
|
||||
;// Checkin $Date: August 18, 2006 13:45:55 $
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;//###########################################################################
|
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;//
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||||
;// FILE: DSP2833x_CodeStartBranch.asm
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;//
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;// TITLE: Branch for redirecting code execution after boot.
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;//
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;// For these examples, code_start is the first code that is executed after
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;// exiting the boot ROM code.
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||||
;//
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;// The codestart section in the linker cmd file is used to physically place
|
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;// this code at the correct memory location. This section should be placed
|
||||
;// at the location the BOOT ROM will re-direct the code to. For example,
|
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;// for boot to FLASH this code will be located at 0x3f7ff6.
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;//
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||||
;// In addition, the example DSP2833x projects are setup such that the codegen
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||||
;// entry point is also set to the code_start label. This is done by linker
|
||||
;// option -e in the project build options. When the debugger loads the code,
|
||||
;// it will automatically set the PC to the "entry point" address indicated by
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||||
;// the -e linker option. In this case the debugger is simply assigning the PC,
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||||
;// it is not the same as a full reset of the device.
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||||
;//
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;// The compiler may warn that the entry point for the project is other then
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;// _c_init00. _c_init00 is the C environment setup and is run before
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;// main() is entered. The code_start code will re-direct the execution
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;// to _c_init00 and thus there is no worry and this warning can be ignored.
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;//
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;//###########################################################################
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||||
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
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;// $Release Date: August 1, 2008 $
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;//###########################################################################
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||||
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||||
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||||
***********************************************************************
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||||
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||||
WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0
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.ref _c_int00
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.global code_start
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||||
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||||
***********************************************************************
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* Function: codestart section
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*
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* Description: Branch to code starting point
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***********************************************************************
|
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.sect "codestart"
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code_start:
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.if WD_DISABLE == 1
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LB wd_disable ;Branch to watchdog disable code
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.else
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LB _c_int00 ;Branch to start of boot.asm in RTS library
|
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.endif
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;end codestart section
|
||||
|
||||
|
||||
***********************************************************************
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* Function: wd_disable
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*
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||||
* Description: Disables the watchdog timer
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||||
***********************************************************************
|
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.if WD_DISABLE == 1
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.text
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wd_disable:
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SETC OBJMODE ;Set OBJMODE for 28x object code
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EALLOW ;Enable EALLOW protected register access
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MOVZ DP, #7029h>>6 ;Set data page for WDCR register
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||||
MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
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EDIS ;Disable EALLOW protected register access
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||||
LB _c_int00 ;Branch to start of boot.asm in RTS library
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.endif
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||||
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;end wd_disable
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||||
|
||||
|
||||
|
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.end
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||||
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||||
;//===========================================================================
|
||||
;// End of file.
|
||||
;//===========================================================================
|
||||
115
Source/External/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c
vendored
Normal file
115
Source/External/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c
vendored
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@@ -0,0 +1,115 @@
|
||||
// TI File $Revision: /main/3 $
|
||||
// Checkin $Date: March 16, 2007 08:37:30 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_CpuTimers.c
|
||||
//
|
||||
// TITLE: CPU 32-bit Timers Initialization & Support Functions.
|
||||
//
|
||||
// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
|
||||
// other realtime operating systems.
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||||
//
|
||||
// Do not use these two timers in your application if you ever plan
|
||||
// on integrating DSP-BIOS or another realtime OS.
|
||||
//
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // Examples Include File
|
||||
|
||||
struct CPUTIMER_VARS CpuTimer0;
|
||||
|
||||
// CpuTimer 1 and CpuTimer2 are used by DSP BIOS & other RTOS. Comment out if using DSP BIOS or other RTOS.
|
||||
struct CPUTIMER_VARS CpuTimer1;
|
||||
struct CPUTIMER_VARS CpuTimer2;
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitCpuTimers:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes all three CPU timers to a known state.
|
||||
//
|
||||
void InitCpuTimers(void)
|
||||
{
|
||||
// CPU Timer 0
|
||||
// Initialize address pointers to respective timer registers:
|
||||
CpuTimer0.RegsAddr = &CpuTimer0Regs;
|
||||
// Initialize timer period to maximum:
|
||||
CpuTimer0Regs.PRD.all = 0xFFFFFFFF;
|
||||
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||
CpuTimer0Regs.TPR.all = 0;
|
||||
CpuTimer0Regs.TPRH.all = 0;
|
||||
// Make sure timer is stopped:
|
||||
CpuTimer0Regs.TCR.bit.TSS = 1;
|
||||
// Reload all counter register with period value:
|
||||
CpuTimer0Regs.TCR.bit.TRB = 1;
|
||||
// Reset interrupt counters:
|
||||
CpuTimer0.InterruptCount = 0;
|
||||
|
||||
|
||||
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
|
||||
// Do not use these two timers if you ever plan on integrating
|
||||
// DSP-BIOS or another realtime OS.
|
||||
//
|
||||
// Initialize address pointers to respective timer registers:
|
||||
CpuTimer1.RegsAddr = &CpuTimer1Regs;
|
||||
CpuTimer2.RegsAddr = &CpuTimer2Regs;
|
||||
// Initialize timer period to maximum:
|
||||
CpuTimer1Regs.PRD.all = 0xFFFFFFFF;
|
||||
CpuTimer2Regs.PRD.all = 0xFFFFFFFF;
|
||||
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||
CpuTimer1Regs.TPR.all = 0;
|
||||
CpuTimer1Regs.TPRH.all = 0;
|
||||
CpuTimer2Regs.TPR.all = 0;
|
||||
CpuTimer2Regs.TPRH.all = 0;
|
||||
// Make sure timers are stopped:
|
||||
CpuTimer1Regs.TCR.bit.TSS = 1;
|
||||
CpuTimer2Regs.TCR.bit.TSS = 1;
|
||||
// Reload all counter register with period value:
|
||||
CpuTimer1Regs.TCR.bit.TRB = 1;
|
||||
CpuTimer2Regs.TCR.bit.TRB = 1;
|
||||
// Reset interrupt counters:
|
||||
CpuTimer1.InterruptCount = 0;
|
||||
CpuTimer2.InterruptCount = 0;
|
||||
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// ConfigCpuTimer:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the selected timer to the period specified
|
||||
// by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz"
|
||||
// and the period in "uSeconds". The timer is held in the stopped state
|
||||
// after configuration.
|
||||
//
|
||||
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
|
||||
{
|
||||
Uint32 temp;
|
||||
|
||||
// Initialize timer period:
|
||||
Timer->CPUFreqInMHz = Freq;
|
||||
Timer->PeriodInUSec = Period;
|
||||
temp = (long) (Freq * Period);
|
||||
Timer->RegsAddr->PRD.all = temp;
|
||||
|
||||
// Set pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||
Timer->RegsAddr->TPR.all = 0;
|
||||
Timer->RegsAddr->TPRH.all = 0;
|
||||
|
||||
// Initialize timer control register:
|
||||
Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer
|
||||
Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
|
||||
Timer->RegsAddr->TCR.bit.SOFT = 0;
|
||||
Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled
|
||||
Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt
|
||||
|
||||
// Reset interrupt counter:
|
||||
Timer->InterruptCount = 0;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
28
Source/External/v120/DSP2833x_common/source/DSP2833x_DBGIER.asm
vendored
Normal file
28
Source/External/v120/DSP2833x_common/source/DSP2833x_DBGIER.asm
vendored
Normal file
@@ -0,0 +1,28 @@
|
||||
;// TI File $Revision: /main/1 $
|
||||
;// Checkin $Date: August 18, 2006 13:46:03 $
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// FILE: DSP2833x_DBGIER.asm
|
||||
;//
|
||||
;// TITLE: Set the DBGIER register
|
||||
;//
|
||||
;// DESCRIPTION:
|
||||
;//
|
||||
;// Function to set the DBGIER register (for realtime emulation).
|
||||
;// Function Prototype: void SetDBGIER(Uint16)
|
||||
;// Useage: SetDBGIER(value);
|
||||
;// Input Parameters: Uint16 value = value to put in DBGIER register.
|
||||
;// Return Value: none
|
||||
;//
|
||||
;//###########################################################################
|
||||
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
;// $Release Date: August 1, 2008 $
|
||||
;//###########################################################################
|
||||
.global _SetDBGIER
|
||||
.text
|
||||
|
||||
_SetDBGIER:
|
||||
MOV *SP++,AL
|
||||
POP DBGIER
|
||||
LRETR
|
||||
|
||||
590
Source/External/v120/DSP2833x_common/source/DSP2833x_DMA.c
vendored
Normal file
590
Source/External/v120/DSP2833x_common/source/DSP2833x_DMA.c
vendored
Normal file
@@ -0,0 +1,590 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_DMA.c
|
||||
//
|
||||
// TITLE: DSP2833x Device DMA Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // Examples Include File
|
||||
|
||||
// This function initializes the DMA to a known state.
|
||||
//
|
||||
void DMAInitialize(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Perform a hard reset on DMA
|
||||
DmaRegs.DMACTRL.bit.HARDRESET = 1;
|
||||
asm (" nop"); // one NOP required after HARDRESET
|
||||
|
||||
// Allow DMA to run free on emulation suspend
|
||||
DmaRegs.DEBUGCTRL.bit.FREE = 1;
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||
{
|
||||
EALLOW;
|
||||
// Set up SOURCE address:
|
||||
DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||
DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||
|
||||
// Set up DESTINATION address:
|
||||
DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||
DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up BURST registers:
|
||||
DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||
DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||
DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up TRANSFER registers:
|
||||
DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||
DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up WRAP registers:
|
||||
DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||
DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||
|
||||
DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||
DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up MODE Register:
|
||||
DmaRegs.CH1.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||
DmaRegs.CH1.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||
DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||
DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||
DmaRegs.CH1.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||
DmaRegs.CH1.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||
DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||
DmaRegs.CH1.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||
DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||
DmaRegs.CH1.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||
|
||||
// Clear any spurious flags:
|
||||
DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||
DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||
DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||
|
||||
// Initialize PIE vector for CPU interrupt:
|
||||
PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
// This function starts DMA Channel 1.
|
||||
void StartDMACH1(void)
|
||||
{
|
||||
EALLOW;
|
||||
DmaRegs.CH1.CONTROL.bit.RUN = 1;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up SOURCE address:
|
||||
DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||
DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||
|
||||
// Set up DESTINATION address:
|
||||
DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||
DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up BURST registers:
|
||||
DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||
DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||
DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up TRANSFER registers:
|
||||
DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||
DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up WRAP registers:
|
||||
DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||
DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||
|
||||
DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||
DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up MODE Register:
|
||||
DmaRegs.CH2.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||
DmaRegs.CH2.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||
DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||
DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||
DmaRegs.CH2.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||
DmaRegs.CH2.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||
DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||
DmaRegs.CH2.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||
DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||
DmaRegs.CH2.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||
|
||||
// Clear any spurious flags:
|
||||
DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||
DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||
DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||
|
||||
// Initialize PIE vector for CPU interrupt:
|
||||
PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable DMA CH2 interrupt in PIE
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
// This function starts DMA Channel 2.
|
||||
void StartDMACH2(void)
|
||||
{
|
||||
EALLOW;
|
||||
DmaRegs.CH2.CONTROL.bit.RUN = 1;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up SOURCE address:
|
||||
DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||
DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||
|
||||
// Set up DESTINATION address:
|
||||
DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||
DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up BURST registers:
|
||||
DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||
DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||
DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up TRANSFER registers:
|
||||
DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||
DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up WRAP registers:
|
||||
DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||
DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||
|
||||
DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||
DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up MODE Register:
|
||||
DmaRegs.CH3.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||
DmaRegs.CH3.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||
DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||
DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||
DmaRegs.CH3.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||
DmaRegs.CH3.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||
DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||
DmaRegs.CH3.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||
DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||
DmaRegs.CH3.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||
|
||||
// Clear any spurious flags:
|
||||
DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||
DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||
DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||
|
||||
// Initialize PIE vector for CPU interrupt:
|
||||
PieCtrlRegs.PIEIER7.bit.INTx3 = 1; // Enable DMA CH3 interrupt in PIE
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
// This function starts DMA Channel 3.
|
||||
void StartDMACH3(void)
|
||||
{
|
||||
EALLOW;
|
||||
DmaRegs.CH3.CONTROL.bit.RUN = 1;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up SOURCE address:
|
||||
DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||
DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||
|
||||
// Set up DESTINATION address:
|
||||
DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||
DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up BURST registers:
|
||||
DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||
DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||
DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up TRANSFER registers:
|
||||
DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||
DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up WRAP registers:
|
||||
DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||
DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||
|
||||
DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||
DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up MODE Register:
|
||||
DmaRegs.CH4.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||
DmaRegs.CH4.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||
DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||
DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||
DmaRegs.CH4.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||
DmaRegs.CH4.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||
DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||
DmaRegs.CH4.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||
DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||
DmaRegs.CH4.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||
|
||||
// Clear any spurious flags:
|
||||
DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||
DmaRegs.CH4.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||
DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||
|
||||
// Initialize PIE vector for CPU interrupt:
|
||||
PieCtrlRegs.PIEIER7.bit.INTx4 = 1; // Enable DMA CH4 interrupt in PIE
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
// This function starts DMA Channel 4.
|
||||
void StartDMACH4(void)
|
||||
{
|
||||
EALLOW;
|
||||
DmaRegs.CH4.CONTROL.bit.RUN = 1;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up SOURCE address:
|
||||
DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||
DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||
|
||||
// Set up DESTINATION address:
|
||||
DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||
DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
|
||||
// Set up BURST registers:
|
||||
DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||
DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||
DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
|
||||
// Set up TRANSFER registers:
|
||||
DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||
DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
|
||||
// Set up WRAP registers:
|
||||
DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||
DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||
|
||||
DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||
DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up MODE Register:
|
||||
DmaRegs.CH5.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||
DmaRegs.CH5.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||
DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||
DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||
DmaRegs.CH5.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||
DmaRegs.CH5.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||
DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||
DmaRegs.CH5.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||
DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||
DmaRegs.CH5.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||
|
||||
// Clear any spurious flags:
|
||||
DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||
DmaRegs.CH5.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||
DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||
|
||||
// Initialize PIE vector for CPU interrupt:
|
||||
PieCtrlRegs.PIEIER7.bit.INTx5 = 1; // Enable DMA CH5 interrupt in PIE
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
// This function starts DMA Channel 5.
|
||||
void StartDMACH5(void)
|
||||
{
|
||||
EALLOW;
|
||||
DmaRegs.CH5.CONTROL.bit.RUN = 1;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up SOURCE address:
|
||||
DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
|
||||
DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
|
||||
|
||||
// Set up DESTINATION address:
|
||||
DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
|
||||
DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up BURST registers:
|
||||
DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
|
||||
DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
|
||||
DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up TRANSFER registers:
|
||||
DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
|
||||
DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up WRAP registers:
|
||||
DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
|
||||
DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap
|
||||
|
||||
DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
|
||||
DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Set up MODE Register:
|
||||
DmaRegs.CH6.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
|
||||
DmaRegs.CH6.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
|
||||
DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; // Oneshot enable
|
||||
DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; // Continous enable
|
||||
DmaRegs.CH6.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
|
||||
DmaRegs.CH6.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
|
||||
DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
|
||||
DmaRegs.CH6.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
|
||||
DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
|
||||
DmaRegs.CH6.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
|
||||
|
||||
// Clear any spurious flags:
|
||||
DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
|
||||
DmaRegs.CH6.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
|
||||
DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
|
||||
|
||||
// Initialize PIE vector for CPU interrupt:
|
||||
PieCtrlRegs.PIEIER7.bit.INTx6 = 1; // Enable DMA CH6 interrupt in PIE
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
// This function starts DMA Channel 6.
|
||||
void StartDMACH6(void)
|
||||
{
|
||||
EALLOW;
|
||||
DmaRegs.CH6.CONTROL.bit.RUN = 1;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
1187
Source/External/v120/DSP2833x_common/source/DSP2833x_DefaultIsr.c
vendored
Normal file
1187
Source/External/v120/DSP2833x_common/source/DSP2833x_DefaultIsr.c
vendored
Normal file
@@ -0,0 +1,1187 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: January 14, 2008 11:17:46 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_DefaultIsr.c
|
||||
//
|
||||
// TITLE: DSP2833x Device Default Interrupt Service Routines.
|
||||
//
|
||||
// This file contains shell ISR routines for the 2833x PIE vector table.
|
||||
// Typically these shell ISR routines can be used to populate the entire PIE
|
||||
// vector table during device debug. In this manner if an interrupt is taken
|
||||
// during firmware development, there will always be an ISR to catch it.
|
||||
//
|
||||
// As develpment progresses, these ISR rotuines can be eliminated and replaced
|
||||
// with the user's own ISR routines for each interrupt. Since these shell ISRs
|
||||
// include infinite loops they will typically not be included as-is in the final
|
||||
// production firmware.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
|
||||
// Connected to INT13 of CPU (use MINT13 mask):
|
||||
// Note CPU-Timer1 is reserved for TI use, however XINT13
|
||||
// ISR can be used by the user.
|
||||
interrupt void INT13_ISR(void) // INT13 or CPU-Timer1
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// Note CPU-Timer2 is reserved for TI use.
|
||||
interrupt void INT14_ISR(void) // CPU-Timer2
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void DATALOG_ISR(void) // Datalogging interrupt
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void RTOSINT_ISR(void) // RTOS interrupt
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void EMUINT_ISR(void) // Emulation interrupt
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void NMI_ISR(void) // Non-maskable interrupt
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm(" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
|
||||
interrupt void USER1_ISR(void) // User Defined trap 1
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
interrupt void USER2_ISR(void) // User Defined trap 2
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
|
||||
}
|
||||
|
||||
interrupt void USER3_ISR(void) // User Defined trap 3
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER4_ISR(void) // User Defined trap 4
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER5_ISR(void) // User Defined trap 5
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER6_ISR(void) // User Defined trap 6
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER7_ISR(void) // User Defined trap 7
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER8_ISR(void) // User Defined trap 8
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER9_ISR(void) // User Defined trap 9
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER10_ISR(void) // User Defined trap 10
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER11_ISR(void) // User Defined trap 11
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER12_ISR(void) // User Defined trap 12
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 1 - MUXed into CPU INT1
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT1.1
|
||||
interrupt void SEQ1INT_ISR(void) //SEQ1 ADC
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT1.2
|
||||
interrupt void SEQ2INT_ISR(void) //SEQ2 ADC
|
||||
{
|
||||
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
|
||||
asm(" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
// INT1.3 - Reserved
|
||||
|
||||
// INT1.4
|
||||
interrupt void XINT1_ISR(void)
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT1.5
|
||||
interrupt void XINT2_ISR(void)
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT1.6
|
||||
interrupt void ADCINT_ISR(void) // ADC
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT1.7
|
||||
interrupt void TINT0_ISR(void) // CPU-Timer 0
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
|
||||
// INT1.8
|
||||
interrupt void WAKEINT_ISR(void) // WD, LOW Power
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 2 - MUXed into CPU INT2
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT2.1
|
||||
interrupt void EPWM1_TZINT_ISR(void) // EPWM-1
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT2.2
|
||||
interrupt void EPWM2_TZINT_ISR(void) // EPWM-2
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT2.3
|
||||
interrupt void EPWM3_TZINT_ISR(void) // EPWM-3
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
|
||||
// INT2.4
|
||||
interrupt void EPWM4_TZINT_ISR(void) // EPWM-4
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
|
||||
// INT2.5
|
||||
interrupt void EPWM5_TZINT_ISR(void) // EPWM-5
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT2.6
|
||||
interrupt void EPWM6_TZINT_ISR(void) // EPWM-6
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT2.7 - Reserved
|
||||
// INT2.8 - Reserved
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 3 - MUXed into CPU INT3
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT 3.1
|
||||
interrupt void EPWM1_INT_ISR(void) // EPWM-1
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT3.2
|
||||
interrupt void EPWM2_INT_ISR(void) // EPWM-2
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT3.3
|
||||
interrupt void EPWM3_INT_ISR(void) // EPWM-3
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT3.4
|
||||
interrupt void EPWM4_INT_ISR(void) // EPWM-4
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT3.5
|
||||
interrupt void EPWM5_INT_ISR(void) // EPWM-5
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT3.6
|
||||
interrupt void EPWM6_INT_ISR(void) // EPWM-6
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT3.7 - Reserved
|
||||
// INT3.8 - Reserved
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 4 - MUXed into CPU INT4
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT 4.1
|
||||
interrupt void ECAP1_INT_ISR(void) // ECAP-1
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT4.2
|
||||
interrupt void ECAP2_INT_ISR(void) // ECAP-2
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT4.3
|
||||
interrupt void ECAP3_INT_ISR(void) // ECAP-3
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT4.4
|
||||
interrupt void ECAP4_INT_ISR(void) // ECAP-4
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT4.5
|
||||
interrupt void ECAP5_INT_ISR(void) // ECAP-5
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
// INT4.6
|
||||
interrupt void ECAP6_INT_ISR(void) // ECAP-6
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
// INT4.7 - Reserved
|
||||
// INT4.8 - Reserved
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 5 - MUXed into CPU INT5
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT 5.1
|
||||
interrupt void EQEP1_INT_ISR(void) // EQEP-1
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT5.2
|
||||
interrupt void EQEP2_INT_ISR(void) // EQEP-2
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT5.3 - Reserved
|
||||
// INT5.4 - Reserved
|
||||
// INT5.5 - Reserved
|
||||
// INT5.6 - Reserved
|
||||
// INT5.7 - Reserved
|
||||
// INT5.8 - Reserved
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 6 - MUXed into CPU INT6
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT6.1
|
||||
interrupt void SPIRXINTA_ISR(void) // SPI-A
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT6.2
|
||||
interrupt void SPITXINTA_ISR(void) // SPI-A
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT6.3
|
||||
interrupt void MRINTB_ISR(void) // McBSP-B
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT6.4
|
||||
interrupt void MXINTB_ISR(void) // McBSP-B
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT6.5
|
||||
interrupt void MRINTA_ISR(void) // McBSP-A
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT6.6
|
||||
interrupt void MXINTA_ISR(void) // McBSP-A
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT6.7 - Reserved
|
||||
// INT6.8 - Reserved
|
||||
|
||||
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 7 - MUXed into CPU INT7
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT7.1
|
||||
interrupt void DINTCH1_ISR(void) // DMA
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT7.2
|
||||
interrupt void DINTCH2_ISR(void) // DMA
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT7.3
|
||||
interrupt void DINTCH3_ISR(void) // DMA
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT7.4
|
||||
interrupt void DINTCH4_ISR(void) // DMA
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT7.5
|
||||
interrupt void DINTCH5_ISR(void) // DMA
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT7.6
|
||||
interrupt void DINTCH6_ISR(void) // DMA
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT7.7 - Reserved
|
||||
// INT7.8 - Reserved
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 8 - MUXed into CPU INT8
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT8.1
|
||||
interrupt void I2CINT1A_ISR(void) // I2C-A
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT8.2
|
||||
interrupt void I2CINT2A_ISR(void) // I2C-A
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
// INT8.3 - Reserved
|
||||
// INT8.4 - Reserved
|
||||
|
||||
// INT8.5
|
||||
interrupt void SCIRXINTC_ISR(void) // SCI-C
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT8.6
|
||||
interrupt void SCITXINTC_ISR(void) // SCI-C
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT8.7 - Reserved
|
||||
// INT8.8 - Reserved
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 9 - MUXed into CPU INT9
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT9.1
|
||||
interrupt void SCIRXINTA_ISR(void) // SCI-A
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT9.2
|
||||
interrupt void SCITXINTA_ISR(void) // SCI-A
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
|
||||
// INT9.3
|
||||
interrupt void SCIRXINTB_ISR(void) // SCI-B
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT9.4
|
||||
interrupt void SCITXINTB_ISR(void) // SCI-B
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT9.5
|
||||
interrupt void ECAN0INTA_ISR(void) // eCAN-A
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT9.6
|
||||
interrupt void ECAN1INTA_ISR(void) // eCAN-A
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT9.7
|
||||
interrupt void ECAN0INTB_ISR(void) // eCAN-B
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT9.8
|
||||
interrupt void ECAN1INTB_ISR(void) // eCAN-B
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 10 - MUXed into CPU INT10
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT10.1 - Reserved
|
||||
// INT10.2 - Reserved
|
||||
// INT10.3 - Reserved
|
||||
// INT10.4 - Reserved
|
||||
// INT10.5 - Reserved
|
||||
// INT10.6 - Reserved
|
||||
// INT10.7 - Reserved
|
||||
// INT10.8 - Reserved
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 11 - MUXed into CPU INT11
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT11.1 - Reserved
|
||||
// INT11.2 - Reserved
|
||||
// INT11.3 - Reserved
|
||||
// INT11.4 - Reserved
|
||||
// INT11.5 - Reserved
|
||||
// INT11.6 - Reserved
|
||||
// INT11.7 - Reserved
|
||||
// INT11.8 - Reserved
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 12 - MUXed into CPU INT12
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// INT12.1
|
||||
interrupt void XINT3_ISR(void) // External Interrupt
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT12.2
|
||||
interrupt void XINT4_ISR(void) // External Interrupt
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT12.3
|
||||
interrupt void XINT5_ISR(void) // External Interrupt
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
// INT12.4
|
||||
interrupt void XINT6_ISR(void) // External Interrupt
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT12.5
|
||||
interrupt void XINT7_ISR(void) // External Interrupt
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
// INT12.6 - Reserved
|
||||
// INT12.7
|
||||
interrupt void LVF_ISR(void) // Latched overflow
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
// INT12.8
|
||||
interrupt void LUF_ISR(void) // Latched underflow
|
||||
{
|
||||
// Insert ISR Code here
|
||||
|
||||
// To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Catch All Default ISRs:
|
||||
//
|
||||
|
||||
interrupt void PIE_RESERVED(void) // Reserved space. For test.
|
||||
{
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void rsvd_ISR(void) // For test
|
||||
{
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
|
||||
65
Source/External/v120/DSP2833x_common/source/DSP2833x_DisInt.asm
vendored
Normal file
65
Source/External/v120/DSP2833x_common/source/DSP2833x_DisInt.asm
vendored
Normal file
@@ -0,0 +1,65 @@
|
||||
;// TI File $Revision: /main/1 $
|
||||
;// Checkin $Date: August 18, 2006 13:46:09 $
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// FILE: DSP2833x_DisInt.asm
|
||||
;//
|
||||
;// TITLE: Disable and Restore INTM and DBGM
|
||||
;//
|
||||
;// Function Prototypes:
|
||||
;//
|
||||
;// Uint16 DSP28x_DisableInt();
|
||||
;// and void DSP28x_RestoreInt(Uint16 Stat0);
|
||||
;//
|
||||
;// Usage:
|
||||
;//
|
||||
;// DSP28x_DisableInt() sets both the INTM and DBGM
|
||||
;// bits to disable maskable interrupts. Before doing
|
||||
;// this, the current value of ST1 is stored on the stack
|
||||
;// so that the values can be restored later. The value
|
||||
;// of ST1 before the masks are set is returned to the
|
||||
;// user in AL. This is then used to restore their state
|
||||
;// via the DSP28x_RestoreInt(Uint16 ST1) function.
|
||||
;//
|
||||
;// Example
|
||||
;//
|
||||
;// Uint16 StatusReg1
|
||||
;// StatusReg1 = DSP28x_DisableInt();
|
||||
;//
|
||||
;// ... May also want to disable INTM here
|
||||
;//
|
||||
;// ... code here
|
||||
;//
|
||||
;// DSP28x_RestoreInt(StatusReg1);
|
||||
;//
|
||||
;// ... Restore INTM enable
|
||||
;//
|
||||
;//###########################################################################
|
||||
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
;// $Release Date: August 1, 2008 $
|
||||
;//###########################################################################
|
||||
|
||||
|
||||
|
||||
|
||||
.def _DSP28x_DisableInt
|
||||
.def _DSP28x_RestoreInt
|
||||
|
||||
|
||||
_DSP28x_DisableInt:
|
||||
PUSH ST1
|
||||
SETC INTM,DBGM
|
||||
MOV AL, *--SP
|
||||
LRETR
|
||||
|
||||
_DSP28x_RestoreInt:
|
||||
MOV *SP++, AL
|
||||
POP ST1
|
||||
LRETR
|
||||
|
||||
|
||||
;//===========================================================================
|
||||
;// End of file.
|
||||
;//===========================================================================
|
||||
|
||||
|
||||
404
Source/External/v120/DSP2833x_common/source/DSP2833x_ECan.c
vendored
Normal file
404
Source/External/v120/DSP2833x_common/source/DSP2833x_ECan.c
vendored
Normal file
@@ -0,0 +1,404 @@
|
||||
// TI File $Revision: /main/8 $
|
||||
// Checkin $Date: June 25, 2008 15:19:07 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_ECan.c
|
||||
//
|
||||
// TITLE: DSP2833x Enhanced CAN Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitECan:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the eCAN module to a known state.
|
||||
//
|
||||
void InitECan(void)
|
||||
{
|
||||
InitECana();
|
||||
#if DSP28_ECANB
|
||||
InitECanb();
|
||||
#endif // if DSP28_ECANB
|
||||
}
|
||||
|
||||
void InitECana(void) // Initialize eCAN-A module
|
||||
{
|
||||
/* Create a shadow register structure for the CAN control registers. This is
|
||||
needed, since only 32-bit access is allowed to these registers. 16-bit access
|
||||
to these registers could potentially corrupt the register contents or return
|
||||
false data. This is especially true while writing to/reading from a bit
|
||||
(or group of bits) among bits 16 - 31 */
|
||||
|
||||
struct ECAN_REGS ECanaShadow;
|
||||
|
||||
EALLOW; // EALLOW enables access to protected bits
|
||||
|
||||
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
|
||||
|
||||
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
|
||||
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
|
||||
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
|
||||
|
||||
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
|
||||
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
|
||||
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
|
||||
|
||||
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
|
||||
// HECC mode also enables time-stamping feature
|
||||
|
||||
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
|
||||
ECanaShadow.CANMC.bit.SCB = 1;
|
||||
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
|
||||
|
||||
/* Initialize all bits of 'Master Control Field' to zero */
|
||||
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
|
||||
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
|
||||
|
||||
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
|
||||
|
||||
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
|
||||
// as a matter of precaution.
|
||||
|
||||
ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
|
||||
|
||||
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
|
||||
|
||||
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
|
||||
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
|
||||
|
||||
|
||||
/* Configure bit timing parameters for eCANA*/
|
||||
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
|
||||
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
|
||||
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
|
||||
|
||||
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||
|
||||
do
|
||||
{
|
||||
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
|
||||
|
||||
ECanaShadow.CANBTC.all = 0;
|
||||
|
||||
#if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
|
||||
/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
|
||||
See Note at End of File */
|
||||
ECanaShadow.CANBTC.bit.BRPREG = 4;
|
||||
ECanaShadow.CANBTC.bit.TSEG2REG = 2;
|
||||
ECanaShadow.CANBTC.bit.TSEG1REG = 10;
|
||||
#endif
|
||||
#if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
|
||||
/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
|
||||
See Note at End of File */
|
||||
ECanaShadow.CANBTC.bit.BRPREG = 4;
|
||||
ECanaShadow.CANBTC.bit.TSEG2REG = 1;
|
||||
ECanaShadow.CANBTC.bit.TSEG1REG = 6;
|
||||
#endif
|
||||
|
||||
|
||||
ECanaShadow.CANBTC.bit.SAM = 1;
|
||||
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
|
||||
|
||||
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
|
||||
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
|
||||
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
|
||||
|
||||
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||
|
||||
do
|
||||
{
|
||||
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
|
||||
|
||||
/* Disable all Mailboxes */
|
||||
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
#if (DSP28_ECANB)
|
||||
void InitECanb(void) // Initialize eCAN-B module
|
||||
{
|
||||
/* Create a shadow register structure for the CAN control registers. This is
|
||||
needed, since only 32-bit access is allowed to these registers. 16-bit access
|
||||
to these registers could potentially corrupt the register contents or return
|
||||
false data. This is especially true while writing to/reading from a bit
|
||||
(or group of bits) among bits 16 - 31 */
|
||||
|
||||
struct ECAN_REGS ECanbShadow;
|
||||
|
||||
EALLOW; // EALLOW enables access to protected bits
|
||||
|
||||
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
|
||||
|
||||
ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
|
||||
ECanbShadow.CANTIOC.bit.TXFUNC = 1;
|
||||
ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;
|
||||
|
||||
ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
|
||||
ECanbShadow.CANRIOC.bit.RXFUNC = 1;
|
||||
ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;
|
||||
|
||||
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
|
||||
|
||||
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
|
||||
ECanbShadow.CANMC.bit.SCB = 1;
|
||||
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
|
||||
|
||||
/* Initialize all bits of 'Master Control Field' to zero */
|
||||
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
|
||||
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
|
||||
|
||||
ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;
|
||||
|
||||
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
|
||||
// as a matter of precaution.
|
||||
|
||||
ECanbRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
|
||||
|
||||
ECanbRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
|
||||
|
||||
ECanbRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
|
||||
ECanbRegs.CANGIF1.all = 0xFFFFFFFF;
|
||||
|
||||
|
||||
/* Configure bit timing parameters for eCANB*/
|
||||
|
||||
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
|
||||
ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
|
||||
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
|
||||
|
||||
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||
|
||||
do
|
||||
{
|
||||
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||
} while(ECanbShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be cleared..
|
||||
|
||||
|
||||
ECanbShadow.CANBTC.all = 0;
|
||||
|
||||
#if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
|
||||
/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
|
||||
See Note at end of file */
|
||||
ECanbShadow.CANBTC.bit.BRPREG = 4;
|
||||
ECanbShadow.CANBTC.bit.TSEG2REG = 2;
|
||||
ECanbShadow.CANBTC.bit.TSEG1REG = 10;
|
||||
#endif
|
||||
#if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
|
||||
/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
|
||||
See Note at end of file */
|
||||
ECanbShadow.CANBTC.bit.BRPREG = 4;
|
||||
ECanbShadow.CANBTC.bit.TSEG2REG = 1;
|
||||
ECanbShadow.CANBTC.bit.TSEG1REG = 6;
|
||||
#endif
|
||||
|
||||
ECanbShadow.CANBTC.bit.SAM = 1;
|
||||
ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;
|
||||
|
||||
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
|
||||
ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
|
||||
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
|
||||
|
||||
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||
|
||||
do
|
||||
{
|
||||
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||
} while(ECanbShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
|
||||
|
||||
|
||||
/* Disable all Mailboxes */
|
||||
ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // if DSP28_ECANB
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitECanGpio:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes GPIO pins to function as eCAN pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// Only one GPIO pin should be enabled for CANTXA/B operation.
|
||||
// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
|
||||
void InitECanGpio(void)
|
||||
{
|
||||
InitECanaGpio();
|
||||
#if (DSP28_ECANB)
|
||||
InitECanbGpio();
|
||||
#endif // if DSP28_ECANB
|
||||
}
|
||||
|
||||
void InitECanaGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected CAN pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA)
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (CANTXA)
|
||||
|
||||
/* Set qualification for selected CAN pins to asynch only */
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA)
|
||||
|
||||
|
||||
/* Configure eCAN-A pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAN functional pins.
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 for CANRXA operation
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 for CANTXA operation
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
#if (DSP28_ECANB)
|
||||
void InitECanbGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected CAN pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up for GPIO8 (CANTXB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up for GPIO12 (CANTXB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up for GPIO16 (CANTXB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up for GPIO20 (CANTXB)
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10 (CANRXB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13 (CANRXB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17 (CANRXB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21 (CANRXB)
|
||||
|
||||
/* Set qualification for selected CAN pins to asynch only */
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB)
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)
|
||||
|
||||
/* Configure eCAN-B pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAN functional pins.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB operation
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB operation
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB operation
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB operation
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB operation
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB operation
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB operation
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB operation
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // if DSP28_ECANB
|
||||
|
||||
/*
|
||||
Note: Bit timing parameters must be chosen based on the network parameters such
|
||||
as the sampling point desired and the propagation delay of the network.
|
||||
The propagation delay is a function of length of the cable, delay introduced by
|
||||
the transceivers and opto/galvanic-isolators (if any).
|
||||
|
||||
The parameters used in this file must be changed taking into account the above
|
||||
mentioned factors in order to arrive at the bit-timing parameters suitable
|
||||
for a network.
|
||||
|
||||
*/
|
||||
255
Source/External/v120/DSP2833x_common/source/DSP2833x_ECap.c
vendored
Normal file
255
Source/External/v120/DSP2833x_common/source/DSP2833x_ECap.c
vendored
Normal file
@@ -0,0 +1,255 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: March 15, 2007 16:54:36 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_ECap.c
|
||||
//
|
||||
// TITLE: DSP2833x eCAP Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitECap:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the eCAP(s) to a known state.
|
||||
//
|
||||
void InitECap(void)
|
||||
{
|
||||
// Initialize eCAP1/2/3
|
||||
|
||||
//tbd...
|
||||
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitECapGpio:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes GPIO pins to function as ECAP pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// For each eCAP peripheral
|
||||
// Only one GPIO pin should be enabled for ECAP operation.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
void InitECapGpio()
|
||||
{
|
||||
|
||||
InitECap1Gpio();
|
||||
#if (DSP28_ECAP2)
|
||||
InitECap2Gpio();
|
||||
#endif // endif DSP28_ECAP2
|
||||
#if (DSP28_ECAP3)
|
||||
InitECap3Gpio();
|
||||
#endif // endif DSP28_ECAP3
|
||||
#if (DSP28_ECAP4)
|
||||
InitECap4Gpio();
|
||||
#endif // endif DSP28_ECAP4
|
||||
#if (DSP28_ECAP5)
|
||||
InitECap5Gpio();
|
||||
#endif // endif DSP28_ECAP5
|
||||
#if (DSP28_ECAP6)
|
||||
InitECap6Gpio();
|
||||
#endif // endif DSP28_ECAP6
|
||||
}
|
||||
|
||||
void InitECap1Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (CAP1)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (CAP1)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on GPIO34 (CAP1)
|
||||
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0; // Synch to SYSCLKOUT GPIO5 (CAP1)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT GPIO24 (CAP1)
|
||||
// GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; // Synch to SYSCLKOUT GPIO34 (CAP1)
|
||||
|
||||
/* Configure eCAP-1 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAP1 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Configure GPIO5 as CAP1
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO24 as CAP1
|
||||
// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 1; // Configure GPIO24 as CAP1
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
#if DSP28_ECAP2
|
||||
void InitECap2Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (CAP2)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (CAP2)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pull-up on GPIO37 (CAP2)
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLKOUT GPIO7 (CAP2)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Synch to SYSCLKOUT GPIO25 (CAP2)
|
||||
// GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; // Synch to SYSCLKOUT GPIO37 (CAP2)
|
||||
|
||||
/* Configure eCAP-2 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAP2 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // Configure GPIO7 as CAP2
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO25 as CAP2
|
||||
// GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // Configure GPIO37 as CAP2
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_ECAP2
|
||||
|
||||
#if DSP28_ECAP3
|
||||
void InitECap3Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (CAP3)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (CAP3)
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Synch to SYSCLKOUT GPIO9 (CAP3)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Synch to SYSCLKOUT GPIO26 (CAP3)
|
||||
|
||||
/* Configure eCAP-3 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAP3 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 3; // Configure GPIO9 as CAP3
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO26 as CAP3
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_ECAP3
|
||||
|
||||
|
||||
#if DSP28_ECAP4
|
||||
void InitECap4Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (CAP4)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (CAP4)
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Synch to SYSCLKOUT GPIO11 (CAP4)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Synch to SYSCLKOUT GPIO27 (CAP4)
|
||||
|
||||
/* Configure eCAP-4 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAP4 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as CAP4
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO27 as CAP4
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_ECAP4
|
||||
|
||||
|
||||
#if DSP28_ECAP5
|
||||
void InitECap5Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (CAP5)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO48 = 0; // Enable pull-up on GPIO48 (CAP5)
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Synch to SYSCLKOUT GPIO3 (CAP5)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0; // Synch to SYSCLKOUT GPIO48 (CAP5)
|
||||
|
||||
/* Configure eCAP-5 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAP5 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as CAP5
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 1; // Configure GPIO48 as CAP5
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_ECAP5
|
||||
|
||||
|
||||
#if DSP28_ECAP6
|
||||
void InitECap6Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (CAP6)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0; // Enable pull-up on GPIO49 (CAP6)
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Synch to SYSCLKOUT GPIO1 (CAP6)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0; // Synch to SYSCLKOUT GPIO49 (CAP6)
|
||||
|
||||
/* Configure eCAP-5 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAP6 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; // Configure GPIO1 as CAP6
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 1; // Configure GPIO49 as CAP6
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_ECAP6
|
||||
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
316
Source/External/v120/DSP2833x_common/source/DSP2833x_EPwm.c
vendored
Normal file
316
Source/External/v120/DSP2833x_common/source/DSP2833x_EPwm.c
vendored
Normal file
@@ -0,0 +1,316 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:46:19 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_EPwm.c
|
||||
//
|
||||
// TITLE: DSP2833x ePWM Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitEPwm:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the ePWM(s) to a known state.
|
||||
//
|
||||
void InitEPwm(void)
|
||||
{
|
||||
// Initialize ePWM1/2/3/4/5/6
|
||||
|
||||
//tbd...
|
||||
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitEPwmGpio:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes GPIO pins to function as ePWM pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
|
||||
void InitEPwmGpio(void)
|
||||
{
|
||||
InitEPwm1Gpio();
|
||||
InitEPwm2Gpio();
|
||||
InitEPwm3Gpio();
|
||||
#if DSP28_EPWM4
|
||||
InitEPwm4Gpio();
|
||||
#endif // endif DSP28_EPWM4
|
||||
#if DSP28_EPWM5
|
||||
InitEPwm5Gpio();
|
||||
#endif // endif DSP28_EPWM5
|
||||
#if DSP28_EPWM6
|
||||
InitEPwm6Gpio();
|
||||
#endif // endif DSP28_EPWM6
|
||||
}
|
||||
|
||||
void InitEPwm1Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (EPWM1B)
|
||||
|
||||
/* Configure ePWM-1 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be ePWM1 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void InitEPwm2Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pull-up on GPIO2 (EPWM2A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (EPWM3B)
|
||||
|
||||
/* Configure ePWM-2 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be ePWM2 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void InitEPwm3Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pull-up on GPIO4 (EPWM3A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (EPWM3B)
|
||||
|
||||
/* Configure ePWM-3 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be ePWM3 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
#if DSP28_EPWM4
|
||||
void InitEPwm4Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWM4A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (EPWM4B)
|
||||
|
||||
/* Configure ePWM-4 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be ePWM4 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_EPWM4
|
||||
|
||||
|
||||
#if DSP28_EPWM5
|
||||
void InitEPwm5Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up on GPIO8 (EPWM5A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (EPWM5B)
|
||||
|
||||
/* Configure ePWM-5 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be ePWM5 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_EPWM5
|
||||
|
||||
|
||||
#if DSP28_EPWM6
|
||||
void InitEPwm6Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up on GPIO10 (EPWM6A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (EPWM6B)
|
||||
|
||||
/* Configure ePWM-6 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be ePWM6 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_EPWM6
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitEPwmSyncGpio:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes GPIO pins to function as ePWM Synch pins
|
||||
//
|
||||
|
||||
void InitEPwmSyncGpio(void)
|
||||
{
|
||||
|
||||
EALLOW;
|
||||
|
||||
/* Configure EPWMSYNCI */
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWMSYNCI)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on GPIO32 (EPWMSYNCI)
|
||||
|
||||
/* Set qualification for selected pins to asynch only */
|
||||
// This will select synch to SYSCLKOUT for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Synch to SYSCLKOUT GPIO6 (EPWMSYNCI)
|
||||
// GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0; // Synch to SYSCLKOUT GPIO32 (EPWMSYNCI)
|
||||
|
||||
/* Configure EPwmSync pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be EPwmSync functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 2; // Enable pull-up on GPIO6 (EPWMSYNCI)
|
||||
// GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2; // Enable pull-up on GPIO32 (EPWMSYNCI)
|
||||
|
||||
|
||||
|
||||
/* Configure EPWMSYNC0 */
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWMSYNC0)
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on GPIO33 (EPWMSYNC0)
|
||||
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3; // Enable pull-up on GPIO6 (EPWMSYNC0)
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2; // Enable pull-up on GPIO33 (EPWMSYNC0)
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitTzGpio:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes GPIO pins to function as Trip Zone (TZ) pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
|
||||
void InitTzGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (TZ1)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (TZ2)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (TZ3)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (TZ4)
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (TZ5)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up on GPIO28 (TZ5)
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (TZ6)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up on GPIO29 (TZ6)
|
||||
|
||||
/* Set qualification for selected pins to asynch only */
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Asynch input GPIO12 (TZ1)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (TZ2)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (TZ3)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (TZ4)
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (TZ5)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (TZ5)
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (TZ6)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3; // Asynch input GPIO29 (TZ6)
|
||||
|
||||
|
||||
/* Configure TZ pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be TZ functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as TZ1
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as TZ2
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as TZ3
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as TZ4
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as TZ5
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // Configure GPIO28 as TZ5
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as TZ6
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // Configure GPIO29 as TZ6
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
154
Source/External/v120/DSP2833x_common/source/DSP2833x_EQep.c
vendored
Normal file
154
Source/External/v120/DSP2833x_common/source/DSP2833x_EQep.c
vendored
Normal file
@@ -0,0 +1,154 @@
|
||||
// TI File $Revision: /main/3 $
|
||||
// Checkin $Date: July 27, 2007 11:55:20 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_EQep.c
|
||||
//
|
||||
// TITLE: DSP2833x eQEP Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitEQep:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the eQEP(s) to a known state.
|
||||
//
|
||||
void InitEQep(void)
|
||||
{
|
||||
// Initialize eQEP1/2
|
||||
|
||||
//tbd...
|
||||
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitEQepGpio:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes GPIO pins to function as eQEP pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// For each eQEP peripheral
|
||||
// Only one GPIO pin should be enabled for EQEPxA operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxB operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxS operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxI operation.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
void InitEQepGpio()
|
||||
{
|
||||
#if DSP28_EQEP1
|
||||
InitEQep1Gpio();
|
||||
#endif // endif DSP28_EQEP1
|
||||
#if DSP28_EQEP2
|
||||
InitEQep2Gpio();
|
||||
#endif // endif DSP28_EQEP2
|
||||
}
|
||||
|
||||
#if DSP28_EQEP1
|
||||
void InitEQep1Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (EQEP1A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (EQEP1B)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (EQEP1S)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (EQEP1I)
|
||||
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pull-up on GPIO50 (EQEP1A)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pull-up on GPIO51 (EQEP1B)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO52 = 0; // Enable pull-up on GPIO52 (EQEP1S)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0; // Enable pull-up on GPIO53 (EQEP1I)
|
||||
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync to SYSCLKOUT GPIO20 (EQEP1A)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync to SYSCLKOUT GPIO21 (EQEP1B)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync to SYSCLKOUT GPIO22 (EQEP1S)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync to SYSCLKOUT GPIO23 (EQEP1I)
|
||||
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Sync to SYSCLKOUT GPIO50 (EQEP1A)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Sync to SYSCLKOUT GPIO51 (EQEP1B)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; // Sync to SYSCLKOUT GPIO52 (EQEP1S)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; // Sync to SYSCLKOUT GPIO53 (EQEP1I)
|
||||
|
||||
/* Configure eQEP-1 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eQEP1 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I
|
||||
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // if DSP28_EQEP1
|
||||
|
||||
|
||||
|
||||
#if DSP28_EQEP2
|
||||
void InitEQep2Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (EQEP2A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (EQEP2B)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (EQEP2I)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (EQEP2S)
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync to SYSCLKOUT GPIO24 (EQEP2A)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync to SYSCLKOUT GPIO25 (EQEP2B)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync to SYSCLKOUT GPIO26 (EQEP2I)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync to SYSCLKOUT GPIO27 (EQEP2S)
|
||||
|
||||
/* Configure eQEP-2 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eQEP2 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2I
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2S
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_EQEP2
|
||||
|
||||
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
69
Source/External/v120/DSP2833x_common/source/DSP2833x_Gpio.c
vendored
Normal file
69
Source/External/v120/DSP2833x_common/source/DSP2833x_Gpio.c
vendored
Normal file
@@ -0,0 +1,69 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:46:25 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Gpio.c
|
||||
//
|
||||
// TITLE: DSP2833x General Purpose I/O Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitGpio:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the Gpio to a known (default) state.
|
||||
//
|
||||
// For more details on configuring GPIO's as peripheral functions,
|
||||
// refer to the individual peripheral examples and/or GPIO setup example.
|
||||
void InitGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Each GPIO pin can be:
|
||||
// a) a GPIO input/output
|
||||
// b) peripheral function 1
|
||||
// c) peripheral function 2
|
||||
// d) peripheral function 3
|
||||
// By default, all are GPIO Inputs
|
||||
GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15
|
||||
GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31
|
||||
GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO39
|
||||
GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO48-GPIO63
|
||||
GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79
|
||||
GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95
|
||||
|
||||
GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs
|
||||
GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs
|
||||
GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are inputs
|
||||
|
||||
// Each input can have different qualification
|
||||
// a) input synchronized to SYSCLKOUT
|
||||
// b) input qualified by a sampling window
|
||||
// c) input sent asynchronously (valid for peripheral inputs only)
|
||||
GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 Synch to SYSCLKOUT
|
||||
|
||||
// Pull-ups can be enabled or disabled.
|
||||
GpioCtrlRegs.GPAPUD.all = 0x0000; // Pullup's enabled GPIO0-GPIO31
|
||||
GpioCtrlRegs.GPBPUD.all = 0x0000; // Pullup's enabled GPIO32-GPIO63
|
||||
GpioCtrlRegs.GPCPUD.all = 0x0000; // Pullup's enabled GPIO64-GPIO79
|
||||
|
||||
//GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31
|
||||
//GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34
|
||||
//GpioCtrlRegs.GPCPUD.all = 0xFFFF // Pullup's disabled GPIO64-GPIO79
|
||||
|
||||
EDIS;
|
||||
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
76
Source/External/v120/DSP2833x_common/source/DSP2833x_I2C.c
vendored
Normal file
76
Source/External/v120/DSP2833x_common/source/DSP2833x_I2C.c
vendored
Normal file
@@ -0,0 +1,76 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:46:27 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_I2C.c
|
||||
//
|
||||
// TITLE: DSP2833x SCI Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitI2C:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the I2C to a known state.
|
||||
//
|
||||
void InitI2C(void)
|
||||
{
|
||||
// Initialize I2C-A:
|
||||
|
||||
//tbd...
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitI2CGpio:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes GPIO pins to function as I2C pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// Only one GPIO pin should be enabled for SDAA operation.
|
||||
// Only one GPIO pin shoudl be enabled for SCLA operation.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
void InitI2CGpio()
|
||||
{
|
||||
|
||||
EALLOW;
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA)
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA)
|
||||
|
||||
/* Set qualification for selected pins to asynch only */
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA)
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA)
|
||||
|
||||
/* Configure SCI pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be I2C functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
349
Source/External/v120/DSP2833x_common/source/DSP2833x_Mcbsp.c
vendored
Normal file
349
Source/External/v120/DSP2833x_common/source/DSP2833x_Mcbsp.c
vendored
Normal file
@@ -0,0 +1,349 @@
|
||||
// TI File $Revision: /main/16 $
|
||||
// Checkin $Date: October 3, 2007 14:50:19 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_McBSP.c
|
||||
//
|
||||
// TITLE: DSP2833x Device McBSP Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate
|
||||
// generator (SRG) cycles required for the Mcbsp initialization routine.
|
||||
// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock
|
||||
// generator (CLKG) cycles required for the Mcbsp initialization routine.
|
||||
// For the functions defined in Mcbsp.c, MCBSP_INIT_DELAY and MCBSP_CLKG_DELAY
|
||||
// are based off of either a 150 MHz SYSCLKOUT (default) or a 100 MHz SYSCLKOUT.
|
||||
//
|
||||
// CPU_FRQ_100MHZ and CPU_FRQ_150MHZ are defined in DSP2833x_Examples.h
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#if CPU_FRQ_150MHZ // For 150 MHz SYSCLKOUT(default)
|
||||
#define CPU_SPD 150E6
|
||||
#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) for examples
|
||||
#endif
|
||||
#if CPU_FRQ_100MHZ // For 100 MHz SYSCLKOUT
|
||||
#define CPU_SPD 100E6
|
||||
#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) for examples
|
||||
#endif
|
||||
|
||||
#define CLKGDV_VAL 1
|
||||
#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ) // # of CPU cycles in 2 SRG cycles-init delay
|
||||
#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL))) // # of CPU cycles in 2 CLKG cycles-init delay
|
||||
//---------------------------------------------------------------------------
|
||||
// InitMcbsp:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the McBSP to a known state.
|
||||
//
|
||||
|
||||
void delay_loop(void); // Delay function used for SRG initialization
|
||||
void clkg_delay_loop(void); // Delay function used for CLKG initialization
|
||||
|
||||
void InitMcbsp(void)
|
||||
{
|
||||
InitMcbspa();
|
||||
#if DSP28_MCBSPB
|
||||
InitMcbspb();
|
||||
#endif // end DSP28_MCBSPB
|
||||
}
|
||||
|
||||
void InitMcbspa(void)
|
||||
{
|
||||
// McBSP-A register settings
|
||||
|
||||
McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
|
||||
McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
|
||||
McbspaRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode.
|
||||
|
||||
|
||||
McbspaRegs.MFFINT.all=0x0; // Disable all interrupts
|
||||
|
||||
McbspaRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive)
|
||||
McbspaRegs.RCR1.all=0x0;
|
||||
|
||||
McbspaRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit)
|
||||
McbspaRegs.XCR1.all=0x0;
|
||||
|
||||
McbspaRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source
|
||||
McbspaRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source
|
||||
|
||||
McbspaRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
|
||||
McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods
|
||||
|
||||
McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
|
||||
McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1)
|
||||
|
||||
delay_loop(); // Wait at least 2 SRG clock cycles
|
||||
|
||||
McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
|
||||
clkg_delay_loop(); // Wait at least 2 CLKG cycles
|
||||
McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
|
||||
McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
|
||||
McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
|
||||
|
||||
}
|
||||
|
||||
|
||||
#if (DSP28_MCBSPB)
|
||||
void InitMcbspb(void)
|
||||
{
|
||||
|
||||
// McBSP-B register settings
|
||||
|
||||
McbspbRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
|
||||
McbspbRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
|
||||
McbspbRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode.
|
||||
|
||||
McbspbRegs.MFFINT.all=0x0; // Disable all interrupts
|
||||
|
||||
McbspbRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive)
|
||||
McbspbRegs.RCR1.all=0x0;
|
||||
|
||||
McbspbRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit)
|
||||
McbspbRegs.XCR1.all=0x0;
|
||||
|
||||
McbspbRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
|
||||
McbspbRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods
|
||||
|
||||
McbspbRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
|
||||
McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1)
|
||||
|
||||
McbspbRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source
|
||||
McbspbRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source
|
||||
delay_loop(); // Wait at least 2 SRG clock cycles
|
||||
McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
|
||||
clkg_delay_loop(); // Wait at least 2 CLKG cycles
|
||||
McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset
|
||||
McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset
|
||||
McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
|
||||
|
||||
}
|
||||
|
||||
|
||||
#endif // end DSP28_MCBSPB
|
||||
|
||||
// McBSP-A Data Lengths
|
||||
void InitMcbspa8bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1=0; // 8-bit word
|
||||
McbspaRegs.XCR1.bit.XWDLEN1=0; // 8-bit word
|
||||
}
|
||||
|
||||
void InitMcbspa12bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1=1; // 12-bit word
|
||||
McbspaRegs.XCR1.bit.XWDLEN1=1; // 12-bit word
|
||||
}
|
||||
|
||||
void InitMcbspa16bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1=2; // 16-bit word
|
||||
McbspaRegs.XCR1.bit.XWDLEN1=2; // 16-bit word
|
||||
}
|
||||
|
||||
void InitMcbspa20bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1=3; // 20-bit word
|
||||
McbspaRegs.XCR1.bit.XWDLEN1=3; // 20-bit word
|
||||
}
|
||||
|
||||
void InitMcbspa24bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1=4; // 24-bit word
|
||||
McbspaRegs.XCR1.bit.XWDLEN1=4; // 24-bit word
|
||||
}
|
||||
|
||||
void InitMcbspa32bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word
|
||||
McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word
|
||||
}
|
||||
|
||||
// McBSP-B Data Lengths
|
||||
#if (DSP28_MCBSPB)
|
||||
|
||||
void InitMcbspb8bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1=0; // 8-bit word
|
||||
McbspbRegs.XCR1.bit.XWDLEN1=0; // 8-bit word
|
||||
}
|
||||
|
||||
void InitMcbspb12bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1=1; // 12-bit word
|
||||
McbspbRegs.XCR1.bit.XWDLEN1=1; // 12-bit word
|
||||
}
|
||||
|
||||
void InitMcbspb16bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1=2; // 16-bit word
|
||||
McbspbRegs.XCR1.bit.XWDLEN1=2; // 16-bit word
|
||||
}
|
||||
|
||||
void InitMcbspb20bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1=3; // 20-bit word
|
||||
McbspbRegs.XCR1.bit.XWDLEN1=3; // 20-bit word
|
||||
}
|
||||
|
||||
void InitMcbspb24bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1=4; // 24-bit word
|
||||
McbspbRegs.XCR1.bit.XWDLEN1=4; // 24-bit word
|
||||
}
|
||||
|
||||
void InitMcbspb32bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1=5; // 32-bit word
|
||||
McbspbRegs.XCR1.bit.XWDLEN1=5; // 32-bit word
|
||||
}
|
||||
|
||||
#endif //end DSP28_MCBSPB
|
||||
|
||||
|
||||
|
||||
void InitMcbspGpio(void)
|
||||
{
|
||||
InitMcbspaGpio();
|
||||
#if DSP28_MCBSPB
|
||||
InitMcbspbGpio();
|
||||
#endif // end DSP28_MCBSPB
|
||||
}
|
||||
|
||||
void InitMcbspaGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Configure McBSP-A pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be McBSP functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; // GPIO20 is MDXA pin
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; // GPIO21 is MDRA pin
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; // GPIO22 is MCLKXA pin
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; // GPIO7 is MCLKRA pin (Comment as needed)
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; // GPIO58 is MCLKRA pin (Comment as needed)
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; // GPIO23 is MFSXA pin
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // GPIO5 is MFSRA pin (Comment as needed)
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; // GPIO59 is MFSRA pin (Comment as needed)
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (MDXA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (MDRA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (MCLKXA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (MCLKRA) (Comment as needed)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (MCLKRA) (Comment as needed)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (MFSXA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (MFSRA) (Comment as needed)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (MFSRA) (Comment as needed)
|
||||
|
||||
/* Set qualification for selected input pins to asynch only */
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch input GPIO21 (MDRA)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; // Asynch input GPIO22 (MCLKXA)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; // Asynch input GPIO7 (MCLKRA) (Comment as needed)
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58(MCLKRA) (Comment as needed)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (MFSXA)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (MFSRA) (Comment as needed)
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (MFSRA) (Comment as needed)
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
#if DSP28_MCBSPB
|
||||
void InitMcbspbGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
/* Configure McBSP-A pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be McBSP functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // GPIO12 is MDXB pin (Comment as needed)
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; // GPIO24 is MDXB pin (Comment as needed)
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // GPIO13 is MDRB pin (Comment as needed)
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; // GPIO25 is MDRB pin (Comment as needed)
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // GPIO14 is MCLKXB pin (Comment as needed)
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; // GPIO26 is MCLKXB pin (Comment as needed)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3; // GPIO3 is MCLKRB pin (Comment as needed)
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1; // GPIO60 is MCLKRB pin (Comment as needed)
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // GPIO15 is MFSXB pin (Comment as needed)
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; // GPIO27 is MFSXB pin (Comment as needed)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; // GPIO1 is MFSRB pin (Comment as needed)
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1; // GPIO61 is MFSRB pin (Comment as needed)
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (MDXB) (Comment as needed)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (MDXB) (Comment as needed)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (MDRB) (Comment as needed)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (MDRB) (Comment as needed)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (MCLKXB) (Comment as needed)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (MCLKXB) (Comment as needed)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (MCLKRB) (Comment as needed)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; // Enable pull-up on GPIO60 (MCLKRB) (Comment as needed)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (MFSXB) (Comment as needed)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (MFSXB) (Comment as needed)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (MFSRB) (Comment as needed)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pull-up on GPIO61 (MFSRB) (Comment as needed)
|
||||
|
||||
|
||||
/* Set qualification for selected input pins to asynch only */
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO25 (MDRB) (Comment as needed)
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (MDRB) (Comment as needed)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO26(MCLKXB) (Comment as needed)
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (MCLKXB) (Comment as needed)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (MCLKRB) (Comment as needed)
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO60 (MCLKRB) (Comment as needed)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO27 (MFSXB) (Comment as needed)
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (MFSXB) (Comment as needed)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; // Asynch input GPIO1 (MFSRB) (Comment as needed)
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO61 (MFSRB) (Comment as needed)
|
||||
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // end DSP28_MCBSPB
|
||||
|
||||
void delay_loop(void)
|
||||
{
|
||||
long i;
|
||||
for (i = 0; i < MCBSP_INIT_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles
|
||||
}
|
||||
|
||||
void clkg_delay_loop(void)
|
||||
{
|
||||
long i;
|
||||
for (i = 0; i < MCBSP_CLKG_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles
|
||||
}
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
45
Source/External/v120/DSP2833x_common/source/DSP2833x_MemCopy.c
vendored
Normal file
45
Source/External/v120/DSP2833x_common/source/DSP2833x_MemCopy.c
vendored
Normal file
@@ -0,0 +1,45 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:46:33 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_MemCopy.c
|
||||
//
|
||||
// TITLE: Memory Copy Utility
|
||||
//
|
||||
// ASSUMPTIONS:
|
||||
//
|
||||
//
|
||||
//
|
||||
// DESCRIPTION:
|
||||
//
|
||||
// This function will copy the specified memory contents from
|
||||
// one location to another.
|
||||
//
|
||||
// Uint16 *SourceAddr Pointer to the first word to be moved
|
||||
// SourceAddr < SourceEndAddr
|
||||
// Uint16* SourceEndAddr Pointer to the last word to be moved
|
||||
// Uint16* DestAddr Pointer to the first destination word
|
||||
//
|
||||
// No checks are made for invalid memory locations or that the
|
||||
// end address is > then the first start address.
|
||||
//
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h"
|
||||
|
||||
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr)
|
||||
{
|
||||
while(SourceAddr < SourceEndAddr)
|
||||
{
|
||||
*DestAddr++ = *SourceAddr++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
83
Source/External/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c
vendored
Normal file
83
Source/External/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c
vendored
Normal file
@@ -0,0 +1,83 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:46:35 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_PieCtrl.c
|
||||
//
|
||||
// TITLE: DSP2833x Device PIE Control Register Initialization Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitPieCtrl:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the PIE control registers to a known state.
|
||||
//
|
||||
void InitPieCtrl(void)
|
||||
{
|
||||
// Disable Interrupts at the CPU level:
|
||||
DINT;
|
||||
|
||||
// Disable the PIE
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
|
||||
|
||||
// Clear all PIEIER registers:
|
||||
PieCtrlRegs.PIEIER1.all = 0;
|
||||
PieCtrlRegs.PIEIER2.all = 0;
|
||||
PieCtrlRegs.PIEIER3.all = 0;
|
||||
PieCtrlRegs.PIEIER4.all = 0;
|
||||
PieCtrlRegs.PIEIER5.all = 0;
|
||||
PieCtrlRegs.PIEIER6.all = 0;
|
||||
PieCtrlRegs.PIEIER7.all = 0;
|
||||
PieCtrlRegs.PIEIER8.all = 0;
|
||||
PieCtrlRegs.PIEIER9.all = 0;
|
||||
PieCtrlRegs.PIEIER10.all = 0;
|
||||
PieCtrlRegs.PIEIER11.all = 0;
|
||||
PieCtrlRegs.PIEIER12.all = 0;
|
||||
|
||||
// Clear all PIEIFR registers:
|
||||
PieCtrlRegs.PIEIFR1.all = 0;
|
||||
PieCtrlRegs.PIEIFR2.all = 0;
|
||||
PieCtrlRegs.PIEIFR3.all = 0;
|
||||
PieCtrlRegs.PIEIFR4.all = 0;
|
||||
PieCtrlRegs.PIEIFR5.all = 0;
|
||||
PieCtrlRegs.PIEIFR6.all = 0;
|
||||
PieCtrlRegs.PIEIFR7.all = 0;
|
||||
PieCtrlRegs.PIEIFR8.all = 0;
|
||||
PieCtrlRegs.PIEIFR9.all = 0;
|
||||
PieCtrlRegs.PIEIFR10.all = 0;
|
||||
PieCtrlRegs.PIEIFR11.all = 0;
|
||||
PieCtrlRegs.PIEIFR12.all = 0;
|
||||
|
||||
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// EnableInterrupts:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function enables the PIE module and CPU interrupts
|
||||
//
|
||||
void EnableInterrupts()
|
||||
{
|
||||
|
||||
// Enable the PIE
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enables PIE to drive a pulse into the CPU
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF;
|
||||
|
||||
// Enable Interrupts at the CPU level
|
||||
EINT;
|
||||
|
||||
}
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
204
Source/External/v120/DSP2833x_common/source/DSP2833x_PieVect.c
vendored
Normal file
204
Source/External/v120/DSP2833x_common/source/DSP2833x_PieVect.c
vendored
Normal file
@@ -0,0 +1,204 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:46:38 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_PieVect.c
|
||||
//
|
||||
// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
const struct PIE_VECT_TABLE PieVectTableInit = {
|
||||
|
||||
PIE_RESERVED, // 0 Reserved space
|
||||
PIE_RESERVED, // 1 Reserved space
|
||||
PIE_RESERVED, // 2 Reserved space
|
||||
PIE_RESERVED, // 3 Reserved space
|
||||
PIE_RESERVED, // 4 Reserved space
|
||||
PIE_RESERVED, // 5 Reserved space
|
||||
PIE_RESERVED, // 6 Reserved space
|
||||
PIE_RESERVED, // 7 Reserved space
|
||||
PIE_RESERVED, // 8 Reserved space
|
||||
PIE_RESERVED, // 9 Reserved space
|
||||
PIE_RESERVED, // 10 Reserved space
|
||||
PIE_RESERVED, // 11 Reserved space
|
||||
PIE_RESERVED, // 12 Reserved space
|
||||
|
||||
|
||||
// Non-Peripheral Interrupts
|
||||
INT13_ISR, // XINT13 or CPU-Timer 1
|
||||
INT14_ISR, // CPU-Timer2
|
||||
DATALOG_ISR, // Datalogging interrupt
|
||||
RTOSINT_ISR, // RTOS interrupt
|
||||
EMUINT_ISR, // Emulation interrupt
|
||||
NMI_ISR, // Non-maskable interrupt
|
||||
ILLEGAL_ISR, // Illegal operation TRAP
|
||||
USER1_ISR, // User Defined trap 1
|
||||
USER2_ISR, // User Defined trap 2
|
||||
USER3_ISR, // User Defined trap 3
|
||||
USER4_ISR, // User Defined trap 4
|
||||
USER5_ISR, // User Defined trap 5
|
||||
USER6_ISR, // User Defined trap 6
|
||||
USER7_ISR, // User Defined trap 7
|
||||
USER8_ISR, // User Defined trap 8
|
||||
USER9_ISR, // User Defined trap 9
|
||||
USER10_ISR, // User Defined trap 10
|
||||
USER11_ISR, // User Defined trap 11
|
||||
USER12_ISR, // User Defined trap 12
|
||||
|
||||
// Group 1 PIE Vectors
|
||||
SEQ1INT_ISR, // 1.1 ADC
|
||||
SEQ2INT_ISR, // 1.2 ADC
|
||||
rsvd_ISR, // 1.3
|
||||
XINT1_ISR, // 1.4
|
||||
XINT2_ISR, // 1.5
|
||||
ADCINT_ISR, // 1.6 ADC
|
||||
TINT0_ISR, // 1.7 Timer 0
|
||||
WAKEINT_ISR, // 1.8 WD, Low Power
|
||||
|
||||
// Group 2 PIE Vectors
|
||||
EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone
|
||||
EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone
|
||||
EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone
|
||||
EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone
|
||||
EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone
|
||||
EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone
|
||||
rsvd_ISR, // 2.7
|
||||
rsvd_ISR, // 2.8
|
||||
|
||||
// Group 3 PIE Vectors
|
||||
EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt
|
||||
EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt
|
||||
EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt
|
||||
EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt
|
||||
EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt
|
||||
EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt
|
||||
rsvd_ISR, // 3.7
|
||||
rsvd_ISR, // 3.8
|
||||
|
||||
// Group 4 PIE Vectors
|
||||
ECAP1_INT_ISR, // 4.1 ECAP-1
|
||||
ECAP2_INT_ISR, // 4.2 ECAP-2
|
||||
ECAP3_INT_ISR, // 4.3 ECAP-3
|
||||
ECAP4_INT_ISR, // 4.4 ECAP-4
|
||||
ECAP5_INT_ISR, // 4.5 ECAP-5
|
||||
ECAP6_INT_ISR, // 4.6 ECAP-6
|
||||
rsvd_ISR, // 4.7
|
||||
rsvd_ISR, // 4.8
|
||||
|
||||
// Group 5 PIE Vectors
|
||||
EQEP1_INT_ISR, // 5.1 EQEP-1
|
||||
EQEP2_INT_ISR, // 5.2 EQEP-2
|
||||
rsvd_ISR, // 5.3
|
||||
rsvd_ISR, // 5.4
|
||||
rsvd_ISR, // 5.5
|
||||
rsvd_ISR, // 5.6
|
||||
rsvd_ISR, // 5.7
|
||||
rsvd_ISR, // 5.8
|
||||
|
||||
|
||||
// Group 6 PIE Vectors
|
||||
SPIRXINTA_ISR, // 6.1 SPI-A
|
||||
SPITXINTA_ISR, // 6.2 SPI-A
|
||||
MRINTA_ISR, // 6.3 McBSP-A
|
||||
MXINTA_ISR, // 6.4 McBSP-A
|
||||
MRINTB_ISR, // 6.5 McBSP-B
|
||||
MXINTB_ISR, // 6.6 McBSP-B
|
||||
rsvd_ISR, // 6.7
|
||||
rsvd_ISR, // 6.8
|
||||
|
||||
|
||||
// Group 7 PIE Vectors
|
||||
DINTCH1_ISR, // 7.1 DMA channel 1
|
||||
DINTCH2_ISR, // 7.2 DMA channel 2
|
||||
DINTCH3_ISR, // 7.3 DMA channel 3
|
||||
DINTCH4_ISR, // 7.4 DMA channel 4
|
||||
DINTCH5_ISR, // 7.5 DMA channel 5
|
||||
DINTCH6_ISR, // 7.6 DMA channel 6
|
||||
rsvd_ISR, // 7.7
|
||||
rsvd_ISR, // 7.8
|
||||
|
||||
// Group 8 PIE Vectors
|
||||
I2CINT1A_ISR, // 8.1 I2C
|
||||
I2CINT2A_ISR, // 8.2 I2C
|
||||
rsvd_ISR, // 8.3
|
||||
rsvd_ISR, // 8.4
|
||||
SCIRXINTC_ISR, // 8.5 SCI-C
|
||||
SCITXINTC_ISR, // 8.6 SCI-C
|
||||
rsvd_ISR, // 8.7
|
||||
rsvd_ISR, // 8.8
|
||||
|
||||
// Group 9 PIE Vectors
|
||||
SCIRXINTA_ISR, // 9.1 SCI-A
|
||||
SCITXINTA_ISR, // 9.2 SCI-A
|
||||
SCIRXINTB_ISR, // 9.3 SCI-B
|
||||
SCITXINTB_ISR, // 9.4 SCI-B
|
||||
ECAN0INTA_ISR, // 9.5 eCAN-A
|
||||
ECAN1INTA_ISR, // 9.6 eCAN-A
|
||||
ECAN0INTB_ISR, // 9.7 eCAN-B
|
||||
ECAN1INTB_ISR, // 9.8 eCAN-B
|
||||
|
||||
// Group 10 PIE Vectors
|
||||
rsvd_ISR, // 10.1
|
||||
rsvd_ISR, // 10.2
|
||||
rsvd_ISR, // 10.3
|
||||
rsvd_ISR, // 10.4
|
||||
rsvd_ISR, // 10.5
|
||||
rsvd_ISR, // 10.6
|
||||
rsvd_ISR, // 10.7
|
||||
rsvd_ISR, // 10.8
|
||||
|
||||
// Group 11 PIE Vectors
|
||||
rsvd_ISR, // 11.1
|
||||
rsvd_ISR, // 11.2
|
||||
rsvd_ISR, // 11.3
|
||||
rsvd_ISR, // 11.4
|
||||
rsvd_ISR, // 11.5
|
||||
rsvd_ISR, // 11.6
|
||||
rsvd_ISR, // 11.7
|
||||
rsvd_ISR, // 11.8
|
||||
|
||||
// Group 12 PIE Vectors
|
||||
XINT3_ISR, // 12.1
|
||||
XINT4_ISR, // 12.2
|
||||
XINT5_ISR, // 12.3
|
||||
XINT6_ISR, // 12.4
|
||||
XINT7_ISR, // 12.5
|
||||
rsvd_ISR, // 12.6
|
||||
LVF_ISR, // 12.7
|
||||
LUF_ISR, // 12.8
|
||||
};
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitPieVectTable:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the PIE vector table to a known state.
|
||||
// This function must be executed after boot time.
|
||||
//
|
||||
|
||||
void InitPieVectTable(void)
|
||||
{
|
||||
int16 i;
|
||||
Uint32 *Source = (void *) &PieVectTableInit;
|
||||
Uint32 *Dest = (void *) &PieVectTable;
|
||||
|
||||
EALLOW;
|
||||
for(i=0; i < 128; i++)
|
||||
*Dest++ = *Source++;
|
||||
EDIS;
|
||||
|
||||
// Enable the PIE Vector Table
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
1863
Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c
vendored
Normal file
1863
Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedDefaultIsr.c
vendored
Normal file
@@ -0,0 +1,1863 @@
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: January 14, 2008 11:28:12 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_SWPrioritizedDefaultIsr.c
|
||||
//
|
||||
// TITLE: DSP2833x Device Default Software Prioritized Interrupt Service Routines.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
|
||||
|
||||
// Connected to INT13 of CPU (use MINT13 mask):
|
||||
// Note CPU-Timer1 is reserved for TI use, however XINT13
|
||||
// ISR can be used by the user.
|
||||
#if (INT13PL != 0)
|
||||
interrupt void INT13_ISR(void) // INT13 or CPU-Timer1
|
||||
{
|
||||
IER |= MINT13; // Set "global" priority
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to INT14 of CPU (use MINT14 mask):
|
||||
#if (INT14PL != 0)
|
||||
interrupt void INT14_ISR(void) // CPU-Timer2
|
||||
{
|
||||
IER |= MINT14; // Set "global" priority
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to INT15 of CPU (use MINT15 mask):
|
||||
#if (INT15PL != 0)
|
||||
interrupt void DATALOG_ISR(void) // Datalogging interrupt
|
||||
{
|
||||
IER |= MINT15; // Set "global" priority
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to INT16 of CPU (use MINT16 mask):
|
||||
#if (INT16PL != 0)
|
||||
interrupt void RTOSINT_ISR(void) // RTOS interrupt
|
||||
{
|
||||
IER |= MINT16; // Set "global" priority
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to EMUINT of CPU (non-maskable):
|
||||
interrupt void EMUINT_ISR(void) // Emulation interrupt
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
|
||||
// Connected to NMI of CPU (non-maskable):
|
||||
interrupt void NMI_ISR(void) // Non-maskable interrupt
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
|
||||
interrupt void USER1_ISR(void) // User Defined trap 1
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER2_ISR(void) // User Defined trap 2
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER3_ISR(void) // User Defined trap 3
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER4_ISR(void) // User Defined trap 4
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER5_ISR(void) // User Defined trap 5
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER6_ISR(void) // User Defined trap 6
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER7_ISR(void) // User Defined trap 7
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER8_ISR(void) // User Defined trap 8
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER9_ISR(void) // User Defined trap 9
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER10_ISR(void) // User Defined trap 10
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER11_ISR(void) // User Defined trap 11
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void USER12_ISR(void) // User Defined trap 12
|
||||
{
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 1 - MUXed into CPU INT1
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER1_1 (use MINT1 and MG11 masks):
|
||||
#if (G11PL != 0)
|
||||
interrupt void SEQ1INT_ISR( void ) // ADC
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= M_INT1;
|
||||
IER &= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER1_2 (use MINT1 and MG12 masks):
|
||||
#if (G12PL != 0)
|
||||
interrupt void SEQ2INT_ISR( void ) // ADC
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= M_INT1;
|
||||
IER &= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Connected to PIEIER1_4 (use MINT1 and MG14 masks):
|
||||
#if (G14PL != 0)
|
||||
interrupt void XINT1_ISR(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER1_5 (use MINT1 and MG15 masks):
|
||||
#if (G15PL != 0)
|
||||
interrupt void XINT2_ISR(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Connected to PIEIER1_6 (use MINT1 and MG16 masks):
|
||||
#if (G16PL != 0)
|
||||
interrupt void ADCINT_ISR(void) // ADC
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= M_INT1;
|
||||
IER &= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER1_7 (use MINT1 and MG17 masks):
|
||||
#if (G17PL != 0)
|
||||
interrupt void TINT0_ISR(void) // CPU-Timer 0
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= M_INT1;
|
||||
IER &= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER1_8 (use MINT1 and MG18 masks):
|
||||
#if (G18PL != 0)
|
||||
interrupt void WAKEINT_ISR(void) // WD/LPM
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
||||
IER |= M_INT1;
|
||||
IER &= MINT1; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 2 - MUXed into CPU INT2
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER2_1 (use MINT2 and MG21 masks):
|
||||
#if (G21PL != 0)
|
||||
interrupt void EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_2 (use MINT2 and MG22 masks):
|
||||
#if (G22PL != 0)
|
||||
interrupt void EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_3 (use MINT2 and MG23 masks):
|
||||
#if (G23PL != 0)
|
||||
interrupt void EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_4 (use MINT2 and MG24 masks):
|
||||
#if (G24PL != 0)
|
||||
interrupt void EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_5 (use MINT2 and MG25 masks):
|
||||
#if (G25PL != 0)
|
||||
interrupt void EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_6 (use MINT2 and MG26 masks):
|
||||
#if (G26PL != 0)
|
||||
interrupt void EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 3 - MUXed into CPU INT3
|
||||
// -----------------------------------------------------------
|
||||
|
||||
|
||||
// Connected to PIEIER3_1 (use MINT3 and MG31 masks):
|
||||
#if (G31PL != 0)
|
||||
interrupt void EPWM1_INT_ISR(void) // ePWM1 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_2 (use MINT3 and MG32 masks):
|
||||
#if (G32PL != 0)
|
||||
interrupt void EPWM2_INT_ISR(void) // ePWM2 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_3 (use MINT3 and MG33 masks):
|
||||
#if (G33PL != 0)
|
||||
interrupt void EPWM3_INT_ISR(void) // ePWM3 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_4 (use MINT3 and MG34 masks):
|
||||
#if (G34PL != 0)
|
||||
interrupt void EPWM4_INT_ISR(void) // ePWM4 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_5 (use MINT3 and MG35 masks):
|
||||
#if (G35PL != 0)
|
||||
interrupt void EPWM5_INT_ISR(void) // ePWM5 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_6 (use MINT3 and MG36 masks):
|
||||
#if (G36PL != 0)
|
||||
interrupt void EPWM6_INT_ISR(void) // ePWM6 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 4 - MUXed into CPU INT4
|
||||
// -----------------------------------------------------------
|
||||
|
||||
|
||||
// Connected to PIEIER4_1 (use MINT4 and MG41 masks):
|
||||
#if (G41PL != 0)
|
||||
interrupt void ECAP1_INT_ISR(void) // eCAP1 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_2 (use MINT4 and MG42 masks):
|
||||
#if (G42PL != 0)
|
||||
interrupt void ECAP2_INT_ISR(void) // eCAP2 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_3 (use MINT4 and MG43 masks):
|
||||
#if (G43PL != 0)
|
||||
interrupt void ECAP3_INT_ISR(void) // eCAP3 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_4 (use MINT4 and MG44 masks):
|
||||
#if (G44PL != 0)
|
||||
interrupt void ECAP4_INT_ISR(void) // eCAP4 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_5 (use MINT4 and MG45 masks):
|
||||
#if (G45PL != 0)
|
||||
interrupt void ECAP5_INT_ISR(void) // eCAP5 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_6 (use MINT4 and MG46 masks):
|
||||
#if (G46PL != 0)
|
||||
interrupt void ECAP6_INT_ISR(void) // eCAP6 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 5 - MUXed into CPU INT5
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER5_1 (use MINT5 and MG51 masks):
|
||||
#if (G51PL != 0)
|
||||
interrupt void EQEP1_INT_ISR(void) // eQEP1 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
|
||||
IER |= M_INT5;
|
||||
IER &= MINT5; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER5.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER5_2 (use MINT5 and MG52 masks):
|
||||
#if (G52PL != 0)
|
||||
interrupt void EQEP2_INT_ISR(void) // eQEP2 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
|
||||
IER |= M_INT5;
|
||||
IER &= MINT5; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER5.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 6 - MUXed into CPU INT6
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER6_1 (use MINT6 and MG61 masks):
|
||||
#if (G61PL != 0)
|
||||
interrupt void SPIRXINTA_ISR(void) // SPI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_2 (use MINT6 and MG62 masks):
|
||||
#if (G62PL != 0)
|
||||
interrupt void SPITXINTA_ISR(void) // SPI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_3 (use MINT6 and MG63 masks):
|
||||
#if (G63PL != 0)
|
||||
interrupt void MRINTB_ISR(void) // McBSP-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_4 (use MINT6 and MG64 masks):
|
||||
#if (G64PL != 0)
|
||||
interrupt void MXINTB_ISR(void) // McBSP-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// Connected to PIEIER6_5 (use MINT6 and MG65 masks):
|
||||
#if (G65PL != 0)
|
||||
interrupt void MRINTA_ISR(void) // McBSP-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_6 (use MINT6 and MG66 masks):
|
||||
#if (G66PL != 0)
|
||||
interrupt void MXINTA_ISR(void) // McBSP-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 7 - MUXed into CPU INT7
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER7_1 (use MINT7 and MG71 masks):
|
||||
#if (G71PL != 0)
|
||||
interrupt void DINTCH1_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_2 (use MINT7 and MG72 masks):
|
||||
#if (G72PL != 0)
|
||||
interrupt void DINTCH2_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_3 (use MINT7 and MG73 masks):
|
||||
#if (G73PL != 0)
|
||||
interrupt void DINTCH3_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_4 (use MINT7 and MG74 masks):
|
||||
#if (G74PL != 0)
|
||||
interrupt void DINTCH4_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// Connected to PIEIER7_5 (use MINT7 and MG75 masks):
|
||||
#if (G75PL != 0)
|
||||
interrupt void DINTCH5_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_6 (use MINT7 and MG76 masks):
|
||||
#if (G76PL != 0)
|
||||
interrupt void DINTCH6_ISR(void) // DMA
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 8 - MUXed into CPU INT8
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER8_1 (use MINT8 and MG81 masks):
|
||||
#if (G81PL != 0)
|
||||
interrupt void I2CINT1A_ISR(void) // I2C-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG81; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER8_2 (use MINT8 and MG82 masks):
|
||||
#if (G82PL != 0)
|
||||
interrupt void I2CINT2A_ISR(void) // I2C-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER8_5 (use MINT8 and MG85 masks):
|
||||
#if (G85PL != 0)
|
||||
interrupt void SCIRXINTC_ISR(void) // SCI-C
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG85; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER8_6 (use MINT8 and MG86 masks):
|
||||
#if (G82PL != 0)
|
||||
interrupt void SCITXINTC_ISR(void) // SCI-C
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 9 - MUXed into CPU INT9
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER9_1 (use MINT9 and MG91 masks):
|
||||
#if (G91PL != 0)
|
||||
interrupt void SCIRXINTA_ISR(void) // SCI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_2 (use MINT9 and MG92 masks):
|
||||
#if (G92PL != 0)
|
||||
interrupt void SCITXINTA_ISR(void) // SCI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Connected to PIEIER9_3 (use MINT9 and MG93 masks):
|
||||
#if (G93PL != 0)
|
||||
interrupt void SCIRXINTB_ISR(void) // SCI-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_4 (use MINT9 and MG94 masks):
|
||||
#if (G94PL != 0)
|
||||
interrupt void SCITXINTB_ISR(void) // SCI-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_5 (use MINT9 and MG95 masks):
|
||||
#if (G95PL != 0)
|
||||
interrupt void ECAN0INTA_ISR(void) // eCAN-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_6 (use MINT9 and MG96 masks):
|
||||
#if (G96PL != 0)
|
||||
interrupt void ECAN1INTA_ISR(void) // eCAN-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_7 (use MINT9 and MG97 masks):
|
||||
#if (G97PL != 0)
|
||||
interrupt void ECAN0INTB_ISR(void) // eCAN-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_8 (use MINT9 and MG98 masks):
|
||||
#if (G98PL != 0)
|
||||
interrupt void ECAN1INTB_ISR(void) // eCAN-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 10 - MUXed into CPU INT10
|
||||
// -----------------------------------------------------------
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 11 - MUXed into CPU INT11
|
||||
// -----------------------------------------------------------
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 12 - MUXed into CPU INT12
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER9_1 (use MINT12 and MG121 masks):
|
||||
#if (G121PL != 0)
|
||||
interrupt void XINT3_ISR(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_2 (use MINT12 and MG122 masks):
|
||||
#if (G122PL != 0)
|
||||
interrupt void XINT4_ISR(void)
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Connected to PIEIER12_3 (use MINT12 and MG123 masks):
|
||||
#if (G123PL != 0)
|
||||
interrupt void XINT5_ISR(void) // SCI-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_4 (use MINT12 and MG124 masks):
|
||||
#if (G124PL != 0)
|
||||
interrupt void XINT6_ISR(void) // SCI-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_5 (use MINT12 and MG125 masks):
|
||||
#if (G125PL != 0)
|
||||
interrupt void XINT7_ISR(void) // eCAN-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_7 (use MINT12 and MG127 masks):
|
||||
#if (G127PL != 0)
|
||||
interrupt void LVF_ISR(void) // FPU
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_8 (use MINT12 and MG128 masks):
|
||||
#if (G128PL != 0)
|
||||
interrupt void LUF_ISR(void) // FPU
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Next two lines for debug only to halt the processor here
|
||||
// Remove after inserting ISR Code
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Catch All Default ISRs:
|
||||
//
|
||||
|
||||
interrupt void PIE_RESERVED(void) // Reserved space. For test.
|
||||
{
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void INT_NOTUSED_ISR(void) // Reserved space. For test.
|
||||
{
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void rsvd_ISR(void) // For test
|
||||
{
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
511
Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c
vendored
Normal file
511
Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c
vendored
Normal file
@@ -0,0 +1,511 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: April 4, 2007 14:25:31 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_SWPiroritizedPieVect.c
|
||||
//
|
||||
// TITLE: DSP2833x Devices SW Prioritized PIE Vector Table Initialization.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// Original Source by A.T.
|
||||
//
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
|
||||
const struct PIE_VECT_TABLE PieVectTableInit = {
|
||||
|
||||
PIE_RESERVED, // Reserved space
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
PIE_RESERVED, // reserved
|
||||
|
||||
// Non-Peripheral Interrupts:
|
||||
#if (INT13PL != 0)
|
||||
INT13_ISR, // XINT13
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (INT14PL != 0)
|
||||
INT14_ISR, // CPU-Timer2
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (INT15PL != 0)
|
||||
DATALOG_ISR, // Datalogging interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (INT16PL != 0)
|
||||
RTOSINT_ISR, // RTOS interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR, // reserved interrupt
|
||||
NMI_ISR, // Non-maskable interrupt
|
||||
ILLEGAL_ISR, // Illegal operation TRAP
|
||||
USER1_ISR, // User Defined trap 1
|
||||
USER2_ISR, // User Defined trap 2
|
||||
USER3_ISR, // User Defined trap 3
|
||||
USER4_ISR, // User Defined trap 4
|
||||
USER5_ISR, // User Defined trap 5
|
||||
USER6_ISR, // User Defined trap 6
|
||||
USER7_ISR, // User Defined trap 7
|
||||
USER8_ISR, // User Defined trap 8
|
||||
USER9_ISR, // User Defined trap 9
|
||||
USER10_ISR, // User Defined trap 10
|
||||
USER11_ISR, // User Defined trap 11
|
||||
USER12_ISR, // User Defined trap 12
|
||||
|
||||
// Group 1 PIE Vectors:
|
||||
#if (G11PL != 0)
|
||||
SEQ1INT_ISR, // ADC
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12PL != 0)
|
||||
SEQ2INT_ISR, // ADC
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
|
||||
#if (G14PL != 0)
|
||||
XINT1_ISR, // External
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G15PL != 0)
|
||||
XINT2_ISR, // External
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G16PL != 0)
|
||||
ADCINT_ISR, // ADC
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G17PL != 0)
|
||||
TINT0_ISR, // Timer 0
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G18PL != 0)
|
||||
WAKEINT_ISR, // WD & Low Power
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
// Group 2 PIE Vectors:
|
||||
#if (G21PL != 0)
|
||||
EPWM1_TZINT_ISR, // ePWM1 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G22PL != 0)
|
||||
EPWM2_TZINT_ISR, // ePWM2 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G23PL != 0)
|
||||
EPWM3_TZINT_ISR, // ePWM3 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G24PL != 0)
|
||||
EPWM4_TZINT_ISR, // ePWM4 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G25PL != 0)
|
||||
EPWM5_TZINT_ISR, // ePWM5 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G26PL != 0)
|
||||
EPWM6_TZINT_ISR, // ePWM6 Trip Zone
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 3 PIE Vectors:
|
||||
#if (G31PL != 0)
|
||||
EPWM1_INT_ISR, // ePWM1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G32PL != 0)
|
||||
EPWM2_INT_ISR, // ePWM2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G33PL != 0)
|
||||
EPWM3_INT_ISR, // ePWM3 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G34PL != 0)
|
||||
EPWM4_INT_ISR, // ePWM4 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G35PL != 0)
|
||||
EPWM5_INT_ISR, // ePWM5 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G36PL != 0)
|
||||
EPWM6_INT_ISR, // ePWM6 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 4 PIE Vectors:
|
||||
#if (G41PL != 0)
|
||||
ECAP1_INT_ISR, // eCAP1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G42PL != 0)
|
||||
ECAP2_INT_ISR, // eCAP2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G43PL != 0)
|
||||
ECAP3_INT_ISR, // eCAP3 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G44PL != 0)
|
||||
ECAP4_INT_ISR, // eCAP4 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G45PL != 0)
|
||||
ECAP5_INT_ISR, // eCAP5 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G46PL != 0)
|
||||
ECAP6_INT_ISR, // eCAP6 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 5 PIE Vectors:
|
||||
#if (G51PL != 0)
|
||||
EQEP1_INT_ISR, // eQEP1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G52PL != 0)
|
||||
EQEP2_INT_ISR, // eQEP2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 6 PIE Vectors:
|
||||
#if (G61PL != 0)
|
||||
SPIRXINTA_ISR, // SPI-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G62PL != 0)
|
||||
SPITXINTA_ISR, // SPI-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G63PL != 0)
|
||||
MRINTB_ISR, // McBSP-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G64PL != 0)
|
||||
MXINTB_ISR, // McBSP-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G65PL != 0)
|
||||
MRINTA_ISR, // McBSP-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G66PL != 0)
|
||||
MXINTA_ISR, // McBSP-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 7 PIE Vectors:
|
||||
#if (G71PL != 0)
|
||||
DINTCH1_ISR, // DMA-Channel 1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G72PL != 0)
|
||||
DINTCH2_ISR, // DMA-Channel 2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G73PL != 0)
|
||||
DINTCH3_ISR, // DMA-Channel 3 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G74PL != 0)
|
||||
DINTCH4_ISR, // DMA-Channel 4 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G75PL != 0)
|
||||
DINTCH5_ISR, // DMA-Channel 5 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G76PL != 0)
|
||||
DINTCH6_ISR, // DMA-Channel 6 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 8 PIE Vectors:
|
||||
#if (G81PL != 0)
|
||||
I2CINT1A_ISR, // I2C-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G82PL != 0)
|
||||
I2CINT2A_ISR, // I2C-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
#if (G85PL != 0)
|
||||
SCIRXINTC_ISR, // SCI-C
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G86PL != 0)
|
||||
SCITXINTC_ISR, // SCI-C
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 9 PIE Vectors:
|
||||
#if (G91PL != 0)
|
||||
SCIRXINTA_ISR, // SCI-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G92PL != 0)
|
||||
SCITXINTA_ISR, // SCI-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G93PL != 0)
|
||||
SCIRXINTB_ISR, // SCI-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G94PL != 0)
|
||||
SCITXINTB_ISR, // SCI-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G95PL != 0)
|
||||
ECAN0INTA_ISR, // eCAN-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G96PL != 0)
|
||||
ECAN1INTA_ISR, // eCAN-A
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G97PL != 0)
|
||||
ECAN0INTB_ISR, // eCAN-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G98PL != 0)
|
||||
ECAN1INTB_ISR, // eCAN-B
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
// Group 10 PIE Vectors
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 11 PIE Vectors
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
rsvd_ISR,
|
||||
|
||||
// Group 12 PIE Vectors
|
||||
#if (G121PL != 0)
|
||||
XINT3_ISR, // External interrupt 3
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G122PL != 0)
|
||||
XINT4_ISR, // External interrupt 4
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G123PL != 0)
|
||||
XINT5_ISR, // External interrupt 5
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G124PL != 0)
|
||||
XINT6_ISR, // External interrupt 6
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G125PL != 0)
|
||||
XINT7_ISR, // External interrupt 7
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
rsvd_ISR,
|
||||
|
||||
#if (G127PL != 0)
|
||||
LVF_ISR, // Latched overflow flag
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G128PL != 0)
|
||||
LUF_ISR, // Latched underflow flag
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitPieVectTable:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the PIE vector table to a known state.
|
||||
// This function must be executed after boot time.
|
||||
//
|
||||
|
||||
void InitPieVectTable(void)
|
||||
{
|
||||
int16 i;
|
||||
Uint32 *Source = (void *) &PieVectTableInit;
|
||||
Uint32 *Dest = (void *) &PieVectTable;
|
||||
|
||||
EALLOW;
|
||||
for(i=0; i < 128; i++) {
|
||||
*Dest++ = *Source++;
|
||||
}
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
168
Source/External/v120/DSP2833x_common/source/DSP2833x_Sci.c
vendored
Normal file
168
Source/External/v120/DSP2833x_common/source/DSP2833x_Sci.c
vendored
Normal file
@@ -0,0 +1,168 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: March 1, 2007 16:06:07 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Sci.c
|
||||
//
|
||||
// TITLE: DSP2833x SCI Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitSci:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the SCI(s) to a known state.
|
||||
//
|
||||
void InitSci(void)
|
||||
{
|
||||
// Initialize SCI-A:
|
||||
|
||||
//tbd...
|
||||
|
||||
|
||||
// Initialize SCI-B:
|
||||
|
||||
//tbd...
|
||||
|
||||
// Initialize SCI-C:
|
||||
|
||||
//tbd...
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitSciGpio:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes GPIO pins to function as SCI pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// Only one GPIO pin should be enabled for SCITXDA/B operation.
|
||||
// Only one GPIO pin shoudl be enabled for SCIRXDA/B operation.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
void InitSciGpio()
|
||||
{
|
||||
InitSciaGpio();
|
||||
#if DSP28_SCIB
|
||||
InitScibGpio();
|
||||
#endif // if DSP28_SCIB
|
||||
#if DSP28_SCIC
|
||||
InitScicGpio();
|
||||
#endif // if DSP28_SCIC
|
||||
}
|
||||
|
||||
void InitSciaGpio()
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA)
|
||||
|
||||
/* Set qualification for selected pins to asynch only */
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA)
|
||||
|
||||
/* Configure SCI-A pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be SCI functional pins.
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 for SCIRXDA operation
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 for SCITXDA operation
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
#if DSP28_SCIB
|
||||
void InitScibGpio()
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up for GPIO9 (SCITXDB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up for GPIO14 (SCITXDB)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (SCITXDB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up for GPIO22 (SCITXDB)
|
||||
|
||||
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up for GPIO11 (SCIRXDB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up for GPIO15 (SCIRXDB)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (SCIRXDB)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up for GPIO23 (SCIRXDB)
|
||||
|
||||
/* Set qualification for selected pins to asynch only */
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB)
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB)
|
||||
|
||||
/* Configure SCI-B pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be SCI functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; // Configure GPIO9 for SCITXDB operation
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // Configure GPIO14 for SCITXDB operation
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; // Configure GPIO18 for SCITXDB operation
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; // Configure GPIO22 for SCITXDB operation
|
||||
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; // Configure GPIO11 for SCIRXDB operation
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // Configure GPIO15 for SCIRXDB operation
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; // Configure GPIO19 for SCIRXDB operation
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; // Configure GPIO23 for SCIRXDB operation
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // if DSP28_SCIB
|
||||
|
||||
#if DSP28_SCIC
|
||||
void InitScicGpio()
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up for GPIO62 (SCIRXDC)
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up for GPIO63 (SCITXDC)
|
||||
|
||||
/* Set qualification for selected pins to asynch only */
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input GPIO62 (SCIRXDC)
|
||||
|
||||
/* Configure SCI-C pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be SCI functional pins.
|
||||
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 for SCIRXDC operation
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 for SCITXDC operation
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // if DSP28_SCIC
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
107
Source/External/v120/DSP2833x_common/source/DSP2833x_Spi.c
vendored
Normal file
107
Source/External/v120/DSP2833x_common/source/DSP2833x_Spi.c
vendored
Normal file
@@ -0,0 +1,107 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:46:44 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Spi.c
|
||||
//
|
||||
// TITLE: DSP2833x SPI Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitSPI:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the SPI(s) to a known state.
|
||||
//
|
||||
void InitSpi(void)
|
||||
{
|
||||
// Initialize SPI-A/B/C/D
|
||||
|
||||
//tbd...
|
||||
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitSpiGpio:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes GPIO pins to function as SPI pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// For each SPI peripheral
|
||||
// Only one GPIO pin should be enabled for SPISOMO operation.
|
||||
// Only one GPIO pin should be enabled for SPISOMI operation.
|
||||
// Only one GPIO pin should be enabled for SPICLKA operation.
|
||||
// Only one GPIO pin should be enabled for SPISTEA operation.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
void InitSpiGpio()
|
||||
{
|
||||
|
||||
InitSpiaGpio();
|
||||
}
|
||||
|
||||
void InitSpiaGpio()
|
||||
{
|
||||
|
||||
EALLOW;
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA)
|
||||
|
||||
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA)
|
||||
|
||||
/* Set qualification for selected pins to asynch only */
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA)
|
||||
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA)
|
||||
|
||||
|
||||
/* Configure SPI-A pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be SPI functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA
|
||||
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
415
Source/External/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c
vendored
Normal file
415
Source/External/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c
vendored
Normal file
@@ -0,0 +1,415 @@
|
||||
// TI File $Revision: /main/7 $
|
||||
// Checkin $Date: September 20, 2007 13:30:31 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_SysCtrl.c
|
||||
//
|
||||
// TITLE: DSP2833x Device System Control Initialization & Support Functions.
|
||||
//
|
||||
// DESCRIPTION:
|
||||
//
|
||||
// Example initialization of system resources.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
|
||||
#include "DSP2833x_Device.h" // Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // Examples Include File
|
||||
|
||||
#include "RS485.h"
|
||||
#include "message.h"
|
||||
|
||||
// Functions that will be run from RAM need to be assigned to
|
||||
// a different section. This section will then be mapped to a load and
|
||||
// run address using the linker cmd file.
|
||||
|
||||
#pragma CODE_SECTION(InitFlash, "ramfuncs");
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitSysCtrl:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the System Control registers to a known state.
|
||||
// - Disables the watchdog
|
||||
// - Set the PLLCR for proper SYSCLKOUT frequency
|
||||
// - Set the pre-scaler for the high and low frequency peripheral clocks
|
||||
// - Enable the clocks to the peripherals
|
||||
|
||||
long SYSCLKOUT, LSPCLK, HSPCLK;
|
||||
|
||||
void InitSysCtrl(void)
|
||||
{
|
||||
|
||||
// Disable the watchdog
|
||||
DisableDog();
|
||||
|
||||
// Initialize the PLL control: PLLCR and DIVSEL
|
||||
// DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
|
||||
InitPll(DSP28_PLLCR,DSP28_DIVSEL);
|
||||
|
||||
// Initialize the peripheral clocks
|
||||
InitPeripheralClocks();
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitFlash:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the Flash Control registers
|
||||
|
||||
// CAUTION
|
||||
// This function MUST be executed out of RAM. Executing it
|
||||
// out of OTP/Flash will yield unpredictable results
|
||||
|
||||
void InitFlash(void)
|
||||
{
|
||||
EALLOW;
|
||||
//Enable Flash Pipeline mode to improve performance
|
||||
//of code executed from Flash.
|
||||
FlashRegs.FOPT.bit.ENPIPE = 1;
|
||||
|
||||
// CAUTION
|
||||
//Minimum waitstates required for the flash operating
|
||||
//at a given CPU rate must be characterized by TI.
|
||||
//Refer to the datasheet for the latest information.
|
||||
#if CPU_FRQ_150MHZ
|
||||
//Set the Paged Waitstate for the Flash
|
||||
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;
|
||||
|
||||
//Set the Random Waitstate for the Flash
|
||||
FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
|
||||
|
||||
//Set the Waitstate for the OTP
|
||||
FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;
|
||||
#endif
|
||||
|
||||
#if CPU_FRQ_100MHZ
|
||||
//Set the Paged Waitstate for the Flash
|
||||
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
|
||||
|
||||
//Set the Random Waitstate for the Flash
|
||||
FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
|
||||
|
||||
//Set the Waitstate for the OTP
|
||||
FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
|
||||
#endif
|
||||
// CAUTION
|
||||
//ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
|
||||
FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
|
||||
FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
|
||||
EDIS;
|
||||
|
||||
//Force a pipeline flush to ensure that the write to
|
||||
//the last register configured occurs before returning.
|
||||
|
||||
asm(" RPT #7 || NOP");
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: ServiceDog:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function resets the watchdog timer.
|
||||
// Enable this function for using ServiceDog in the application
|
||||
|
||||
void ServiceDog(void)
|
||||
{
|
||||
if(SysCtrlRegs.PLLCR.bit.DIV == DSP28_PLLCR)
|
||||
if(SysCtrlRegs.PLLSTS.bit.DIVSEL == DSP28_DIVSEL)
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.WDKEY = 0x0055;
|
||||
SysCtrlRegs.WDKEY = 0x00AA;
|
||||
EDIS;
|
||||
return;
|
||||
} }
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: DisableDog:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function disables the watchdog timer.
|
||||
|
||||
void DisableDog(void)
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.WDCR= 0x0068;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: InitPll:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the PLLCR register.
|
||||
|
||||
void InitPll(Uint16 divval, Uint16 divsel)
|
||||
{
|
||||
long clkVal;
|
||||
|
||||
// Make sure the PLL is not running in limp mode
|
||||
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
|
||||
{
|
||||
// Missing external clock has been detected
|
||||
// Replace this line with a call to an appropriate
|
||||
// SystemShutdown(); function.
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
// DIVSEL MUST be 0 before PLLCR can be changed from
|
||||
// 0x0000. It is set to 0 by an external reset XRSn
|
||||
// This puts us in 1/4
|
||||
if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
// Change the PLLCR
|
||||
// if (SysCtrlRegs.PLLCR.bit.DIV != val)
|
||||
{
|
||||
|
||||
EALLOW;
|
||||
// Before setting PLLCR turn off missing clock detect logic
|
||||
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
|
||||
SysCtrlRegs.PLLCR.bit.DIV = divval;
|
||||
EDIS;
|
||||
|
||||
clkVal = (divval)?divval:1;
|
||||
clkVal = XCLKIN * clkVal;
|
||||
|
||||
// Optional: Wait for PLL to lock.
|
||||
// During this time the CPU will switch to OSCCLK/2 until
|
||||
// the PLL is stable. Once the PLL is stable the CPU will
|
||||
// switch to the new PLL value.
|
||||
//
|
||||
// This time-to-lock is monitored by a PLL lock counter.
|
||||
//
|
||||
// Code is not required to sit and wait for the PLL to lock.
|
||||
// However, if the code does anything that is timing critical,
|
||||
// and requires the correct clock be locked, then it is best to
|
||||
// wait until this switching has completed.
|
||||
|
||||
// Wait for the PLL lock bit to be set.
|
||||
|
||||
// The watchdog should be disabled before this loop, or fed within
|
||||
// the loop via ServiceDog().
|
||||
|
||||
// Uncomment to disable the watchdog
|
||||
DisableDog();
|
||||
|
||||
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
|
||||
{
|
||||
// Uncomment to service the watchdog
|
||||
// ServiceDog();
|
||||
}
|
||||
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
// If switching to 1/2
|
||||
if((divsel == 1)||(divsel == 2))
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
if(divsel == 0) clkVal /= 4;
|
||||
if(divsel == 1) clkVal /= 4;
|
||||
if(divsel == 2) clkVal /= 2;
|
||||
|
||||
// If switching to 1/1
|
||||
// * First go to 1/2 and let the power settle
|
||||
// The time required will depend on the system, this is only an example
|
||||
// * Then switch to 1/1
|
||||
|
||||
if((divval == 0) && (divsel == 3))
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
|
||||
DELAY_US(50L);
|
||||
// pause_us(50L);
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
SYSCLKOUT = clkVal;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------------
|
||||
// Example: InitPeripheralClocks:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the clocks to the peripheral modules.
|
||||
// First the high and low clock prescalers are set
|
||||
// Second the clocks are enabled to each peripheral.
|
||||
// To reduce power, leave clocks to unused peripherals disabled
|
||||
//
|
||||
// Note: If a peripherals clock is not enabled then you cannot
|
||||
// read or write to the registers for that peripheral
|
||||
|
||||
void InitPeripheralClocks(void)
|
||||
{
|
||||
long Val;
|
||||
|
||||
EALLOW;
|
||||
|
||||
// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
|
||||
|
||||
#if CLKMULT == 0
|
||||
SysCtrlRegs.HISPCP.all = 0x0000;
|
||||
#endif
|
||||
#if CLKMULT == 1
|
||||
SysCtrlRegs.HISPCP.all = 0x0000;
|
||||
#endif
|
||||
#if CLKMULT == 2
|
||||
SysCtrlRegs.HISPCP.all = 0x0001;
|
||||
#endif
|
||||
#if CLKMULT == 3
|
||||
SysCtrlRegs.HISPCP.all = 0x0002;
|
||||
#endif
|
||||
#if CLKMULT == 4
|
||||
SysCtrlRegs.HISPCP.all = 0x0002;
|
||||
#endif
|
||||
#if CLKMULT == 5
|
||||
SysCtrlRegs.HISPCP.all = 0x0003;
|
||||
#endif
|
||||
|
||||
SysCtrlRegs.LOSPCP.all = 0x0000;
|
||||
|
||||
Val = (SysCtrlRegs.HISPCP.all)?
|
||||
SysCtrlRegs.HISPCP.all*2 : 1;
|
||||
Val = SYSCLKOUT / Val;
|
||||
|
||||
HSPCLK = Val;
|
||||
|
||||
Val = (SysCtrlRegs.LOSPCP.all)?
|
||||
SysCtrlRegs.LOSPCP.all*2 : 1;
|
||||
Val = SYSCLKOUT / Val;
|
||||
LSPCLK = Val;
|
||||
|
||||
// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
|
||||
// XTIMCLK = SYSCLKOUT/2
|
||||
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
|
||||
// XCLKOUT = XTIMCLK/2
|
||||
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
|
||||
// Enable XCLKOUT
|
||||
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
|
||||
|
||||
// Peripheral clock enables set for the selected peripherals.
|
||||
// If you are not using a peripheral leave the clock off
|
||||
// to save on power.
|
||||
//
|
||||
// Note: not all peripherals are available on all 2833x derivates.
|
||||
// Refer to the datasheet for your particular device.
|
||||
//
|
||||
// This function is not written to be an example of efficient code.
|
||||
|
||||
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
|
||||
|
||||
// *IMPORTANT*
|
||||
// The ADC_cal function, which copies the ADC calibration values from TI reserved
|
||||
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
|
||||
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
|
||||
// following function MUST be called for the ADC to function according
|
||||
// to specification. The clocks to the ADC MUST be enabled before calling this
|
||||
// function.
|
||||
// See the device data manual and/or the ADC Reference
|
||||
// Manual for more information.
|
||||
|
||||
ADC_cal();
|
||||
|
||||
|
||||
SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C
|
||||
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
|
||||
SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
|
||||
SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C
|
||||
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
|
||||
SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
|
||||
SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B
|
||||
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
|
||||
SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B
|
||||
|
||||
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
|
||||
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
|
||||
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
|
||||
SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
|
||||
SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
|
||||
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
|
||||
|
||||
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock
|
||||
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
|
||||
SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: CsmUnlock:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function unlocks the CSM. User must replace 0xFFFF's with current
|
||||
// password for the DSP. Returns 1 if unlock is successful.
|
||||
|
||||
#define STATUS_FAIL 0
|
||||
#define STATUS_SUCCESS 1
|
||||
|
||||
Uint16 CsmUnlock()
|
||||
{
|
||||
volatile Uint16 temp;
|
||||
|
||||
// Load the key registers with the current password. The 0xFFFF's are dummy
|
||||
// passwords. User should replace them with the correct password for the DSP.
|
||||
|
||||
EALLOW;
|
||||
CsmRegs.KEY0 = 0xFFFF;
|
||||
CsmRegs.KEY1 = 0xFFFF;
|
||||
CsmRegs.KEY2 = 0xFFFF;
|
||||
CsmRegs.KEY3 = 0xFFFF;
|
||||
CsmRegs.KEY4 = 0xFFFF;
|
||||
CsmRegs.KEY5 = 0xFFFF;
|
||||
CsmRegs.KEY6 = 0xFFFF;
|
||||
CsmRegs.KEY7 = 0xFFFF;
|
||||
EDIS;
|
||||
|
||||
// Perform a dummy read of the password locations
|
||||
// if they match the key values, the CSM will unlock
|
||||
|
||||
temp = CsmPwl.PSWD0;
|
||||
temp = CsmPwl.PSWD1;
|
||||
temp = CsmPwl.PSWD2;
|
||||
temp = CsmPwl.PSWD3;
|
||||
temp = CsmPwl.PSWD4;
|
||||
temp = CsmPwl.PSWD5;
|
||||
temp = CsmPwl.PSWD6;
|
||||
temp = CsmPwl.PSWD7;
|
||||
|
||||
// If the CSM unlocked, return succes, otherwise return
|
||||
// failure.
|
||||
if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS;
|
||||
else return STATUS_FAIL;
|
||||
|
||||
}
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
242
Source/External/v120/DSP2833x_common/source/DSP2833x_Xintf.c
vendored
Normal file
242
Source/External/v120/DSP2833x_common/source/DSP2833x_Xintf.c
vendored
Normal file
@@ -0,0 +1,242 @@
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: August 16, 2007 11:06:26 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Xintf.c
|
||||
//
|
||||
// TITLE: DSP2833x Device External Interface Init & Support Functions.
|
||||
//
|
||||
// DESCRIPTION:
|
||||
//
|
||||
// Example initialization function for the external interface (XINTF).
|
||||
// This example configures the XINTF to its default state. For an
|
||||
// example of how this function being used refer to the
|
||||
// examples/run_from_xintf project.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// InitXINTF:
|
||||
//---------------------------------------------------------------------------
|
||||
// This function initializes the External Interface the default reset state.
|
||||
//
|
||||
// Do not modify the timings of the XINTF while running from the XINTF. Doing
|
||||
// so can yield unpredictable results
|
||||
|
||||
|
||||
void InitXintf(void)
|
||||
{
|
||||
// This shows how to write to the XINTF registers. The
|
||||
// values used here are the default state after reset.
|
||||
// Different hardware will require a different configuration.
|
||||
|
||||
// For an example of an XINTF configuration used with the
|
||||
// F28335 eZdsp, refer to the examples/run_from_xintf project.
|
||||
|
||||
// Any changes to XINTF timing should only be made by code
|
||||
// running outside of the XINTF.
|
||||
|
||||
// All Zones---------------------------------
|
||||
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
|
||||
EALLOW;
|
||||
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
|
||||
// No write buffering
|
||||
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
|
||||
// XCLKOUT is enabled
|
||||
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
|
||||
// XCLKOUT = XTIMCLK/2
|
||||
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
|
||||
|
||||
|
||||
// Zone 0------------------------------------
|
||||
// When using ready, ACTIVE must be 1 or greater
|
||||
// Lead must always be 1 or greater
|
||||
// Zone write timing
|
||||
XintfRegs.XTIMING0.bit.XWRLEAD = 3;
|
||||
XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
|
||||
XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
|
||||
// Zone read timing
|
||||
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
|
||||
XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
|
||||
XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
|
||||
|
||||
// double all Zone read/write lead/active/trail timing
|
||||
XintfRegs.XTIMING0.bit.X2TIMING = 1;
|
||||
|
||||
// Zone will sample XREADY signal
|
||||
XintfRegs.XTIMING0.bit.USEREADY = 1;
|
||||
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
|
||||
|
||||
// Size must be either:
|
||||
// 0,1 = x32 or
|
||||
// 1,1 = x16 other values are reserved
|
||||
XintfRegs.XTIMING0.bit.XSIZE = 3;
|
||||
|
||||
// Zone 6------------------------------------
|
||||
// When using ready, ACTIVE must be 1 or greater
|
||||
// Lead must always be 1 or greater
|
||||
// Zone write timing
|
||||
XintfRegs.XTIMING6.bit.XWRLEAD = 3;
|
||||
XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
|
||||
XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
|
||||
// Zone read timing
|
||||
XintfRegs.XTIMING6.bit.XRDLEAD = 3;
|
||||
XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
|
||||
XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
|
||||
|
||||
// double all Zone read/write lead/active/trail timing
|
||||
XintfRegs.XTIMING6.bit.X2TIMING = 1;
|
||||
|
||||
// Zone will sample XREADY signal
|
||||
XintfRegs.XTIMING6.bit.USEREADY = 1;
|
||||
XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous
|
||||
|
||||
// Size must be either:
|
||||
// 0,1 = x32 or
|
||||
// 1,1 = x16 other values are reserved
|
||||
XintfRegs.XTIMING6.bit.XSIZE = 3;
|
||||
|
||||
|
||||
// Zone 7------------------------------------
|
||||
// When using ready, ACTIVE must be 1 or greater
|
||||
// Lead must always be 1 or greater
|
||||
// Zone write timing
|
||||
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
|
||||
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
|
||||
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
|
||||
// Zone read timing
|
||||
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
|
||||
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
|
||||
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
|
||||
|
||||
// double all Zone read/write lead/active/trail timing
|
||||
XintfRegs.XTIMING7.bit.X2TIMING = 1;
|
||||
|
||||
// Zone will sample XREADY signal
|
||||
XintfRegs.XTIMING7.bit.USEREADY = 1;
|
||||
XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
|
||||
|
||||
// Size must be either:
|
||||
// 0,1 = x32 or
|
||||
// 1,1 = x16 other values are reserved
|
||||
XintfRegs.XTIMING7.bit.XSIZE = 3;
|
||||
|
||||
// Bank switching
|
||||
// Assume Zone 7 is slow, so add additional BCYC cycles
|
||||
// when ever switching from Zone 7 to another Zone.
|
||||
// This will help avoid bus contention.
|
||||
XintfRegs.XBANK.bit.BANK = 7;
|
||||
XintfRegs.XBANK.bit.BCYC = 7;
|
||||
EDIS;
|
||||
//Force a pipeline flush to ensure that the write to
|
||||
//the last register configured occurs before returning.
|
||||
|
||||
InitXintf16Gpio();
|
||||
// InitXintf32Gpio();
|
||||
|
||||
asm(" RPT #7 || NOP");
|
||||
|
||||
}
|
||||
|
||||
void InitXintf32Gpio()
|
||||
{
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16
|
||||
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input
|
||||
|
||||
|
||||
InitXintf16Gpio();
|
||||
}
|
||||
|
||||
void InitXintf16Gpio()
|
||||
{
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0
|
||||
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7
|
||||
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19
|
||||
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0
|
||||
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
76
Source/External/v120/DSP2833x_common/source/DSP2833x_usDelay.asm
vendored
Normal file
76
Source/External/v120/DSP2833x_common/source/DSP2833x_usDelay.asm
vendored
Normal file
@@ -0,0 +1,76 @@
|
||||
;// TI File $Revision: /main/4 $
|
||||
;// Checkin $Date: July 30, 2007 10:28:57 $
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// FILE: DSP2833x_usDelay.asm
|
||||
;//
|
||||
;// TITLE: Simple delay function
|
||||
;//
|
||||
;// DESCRIPTION:
|
||||
;//
|
||||
;// This is a simple delay function that can be used to insert a specified
|
||||
;// delay into code.
|
||||
;//
|
||||
;// This function is only accurate if executed from internal zero-waitstate
|
||||
;// SARAM. If it is executed from waitstate memory then the delay will be
|
||||
;// longer then specified.
|
||||
;//
|
||||
;// To use this function:
|
||||
;//
|
||||
;// 1 - update the CPU clock speed in the DSP2833x_Examples.h
|
||||
;// file. For example:
|
||||
;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed
|
||||
;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed
|
||||
;//
|
||||
;// 2 - Call this function by using the DELAY_US(A) macro
|
||||
;// that is defined in the DSP2833x_Examples.h file. This macro
|
||||
;// will convert the number of microseconds specified
|
||||
;// into a loop count for use with this function.
|
||||
;// This count will be based on the CPU frequency you specify.
|
||||
;//
|
||||
;// 3 - For the most accurate delay
|
||||
;// - Execute this function in 0 waitstate RAM.
|
||||
;// - Disable interrupts before calling the function
|
||||
;// If you do not disable interrupts, then think of
|
||||
;// this as an "at least" delay function as the actual
|
||||
;// delay may be longer.
|
||||
;//
|
||||
;// The C assembly call from the DELAY_US(time) macro will
|
||||
;// look as follows:
|
||||
;//
|
||||
;// extern void Delay(long LoopCount);
|
||||
;//
|
||||
;// MOV AL,#LowLoopCount
|
||||
;// MOV AH,#HighLoopCount
|
||||
;// LCR _Delay
|
||||
;//
|
||||
;// Or as follows (if count is less then 16-bits):
|
||||
;//
|
||||
;// MOV ACC,#LoopCount
|
||||
;// LCR _Delay
|
||||
;//
|
||||
;//
|
||||
;//###########################################################################
|
||||
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
;// $Release Date: August 1, 2008 $
|
||||
;//###########################################################################
|
||||
|
||||
.def _DSP28x_usDelay
|
||||
.sect ".text"
|
||||
|
||||
.global __DSP28x_usDelay
|
||||
_DSP28x_usDelay:
|
||||
SUB ACC,#1
|
||||
BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0
|
||||
LRETR
|
||||
|
||||
;There is a 9/10 cycle overhead and each loop
|
||||
;takes five cycles. The LoopCount is given by
|
||||
;the following formula:
|
||||
; DELAY_CPU_CYCLES = 9 + 5*LoopCount
|
||||
; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
|
||||
; The macro DELAY_US(A) performs this calculation for you
|
||||
;
|
||||
;//===========================================================================
|
||||
;// End of file.
|
||||
;//===========================================================================
|
||||
Reference in New Issue
Block a user