From a0d433f87e20b893526e182622c5c9a794d5abb5 Mon Sep 17 00:00:00 2001 From: Dimas Date: Wed, 11 Jun 2025 17:15:08 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9D=D0=B0=D1=87=D0=B0=D0=BB=D0=BE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .mxproject | 36 + Core/Inc/can.h | 55 + Core/Inc/crc16.h | 10 + Core/Inc/eeprom.h | 20 + Core/Inc/gpio.h | 165 + Core/Inc/lampa.h | 30 + Core/Inc/main.h | 73 + Core/Inc/message.h | 25 + Core/Inc/package.h | 57 + Core/Inc/stm32f1xx_hal_conf.h | 391 + Core/Inc/stm32f1xx_it.h | 72 + Core/Inc/struc.h | 153 + Core/Inc/tim.h | 52 + Core/Src/can.c | 275 + Core/Src/crc16.c | 196 + Core/Src/eeprom.c | 49 + Core/Src/gpio.c | 95 + Core/Src/lampa.c | 85 + Core/Src/main.c | 416 + Core/Src/message.c | 132 + Core/Src/stm32f1xx_hal_msp.c | 88 + Core/Src/stm32f1xx_it.c | 248 + Core/Src/syscalls.c | 156 + Core/Src/sysmem.c | 80 + Core/Src/system_stm32f1xx.c | 408 + Core/Src/tim.c | 129 + Core/Startup/startup_stm32f103rctx.s | 468 + .../Device/ST/STM32F1xx/Include/stm32f103xe.h | 11761 +++++++++ .../Device/ST/STM32F1xx/Include/stm32f1xx.h | 220 + .../ST/STM32F1xx/Include/system_stm32f1xx.h | 98 + Drivers/CMSIS/Device/ST/STM32F1xx/License.md | 83 + Drivers/CMSIS/Include/cmsis_armcc.h | 865 + Drivers/CMSIS/Include/cmsis_armclang.h | 1869 ++ Drivers/CMSIS/Include/cmsis_compiler.h | 266 + Drivers/CMSIS/Include/cmsis_gcc.h | 2085 ++ Drivers/CMSIS/Include/cmsis_iccarm.h | 935 + Drivers/CMSIS/Include/cmsis_version.h | 39 + Drivers/CMSIS/Include/core_armv8mbl.h | 1918 ++ Drivers/CMSIS/Include/core_armv8mml.h | 2927 +++ Drivers/CMSIS/Include/core_cm0.h | 949 + Drivers/CMSIS/Include/core_cm0plus.h | 1083 + Drivers/CMSIS/Include/core_cm1.h | 976 + Drivers/CMSIS/Include/core_cm23.h | 1993 ++ Drivers/CMSIS/Include/core_cm3.h | 1941 ++ Drivers/CMSIS/Include/core_cm33.h | 3002 +++ Drivers/CMSIS/Include/core_cm4.h | 2129 ++ Drivers/CMSIS/Include/core_cm7.h | 2671 ++ Drivers/CMSIS/Include/core_sc000.h | 1022 + Drivers/CMSIS/Include/core_sc300.h | 1915 ++ Drivers/CMSIS/Include/mpu_armv7.h | 270 + Drivers/CMSIS/Include/mpu_armv8.h | 333 + Drivers/CMSIS/Include/tz_context.h | 70 + Drivers/CMSIS/LICENSE.txt | 201 + .../Inc/Legacy/stm32_hal_legacy.h | 3783 +++ .../STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h | 358 + .../Inc/stm32f1xx_hal_can.h | 850 + .../Inc/stm32f1xx_hal_cortex.h | 410 + .../Inc/stm32f1xx_hal_def.h | 210 + .../Inc/stm32f1xx_hal_dma.h | 457 + .../Inc/stm32f1xx_hal_dma_ex.h | 277 + .../Inc/stm32f1xx_hal_exti.h | 320 + .../Inc/stm32f1xx_hal_flash.h | 328 + .../Inc/stm32f1xx_hal_flash_ex.h | 786 + .../Inc/stm32f1xx_hal_gpio.h | 308 + .../Inc/stm32f1xx_hal_gpio_ex.h | 894 + .../Inc/stm32f1xx_hal_pwr.h | 388 + .../Inc/stm32f1xx_hal_rcc.h | 1378 ++ .../Inc/stm32f1xx_hal_rcc_ex.h | 1908 ++ .../Inc/stm32f1xx_hal_tim.h | 2123 ++ .../Inc/stm32f1xx_hal_tim_ex.h | 262 + Drivers/STM32F1xx_HAL_Driver/License.md | 3 + .../STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c | 606 + .../Src/stm32f1xx_hal_can.c | 2436 ++ .../Src/stm32f1xx_hal_cortex.c | 505 + .../Src/stm32f1xx_hal_dma.c | 899 + .../Src/stm32f1xx_hal_exti.c | 559 + .../Src/stm32f1xx_hal_flash.c | 967 + .../Src/stm32f1xx_hal_flash_ex.c | 1127 + .../Src/stm32f1xx_hal_gpio.c | 587 + .../Src/stm32f1xx_hal_gpio_ex.c | 127 + .../Src/stm32f1xx_hal_pwr.c | 621 + .../Src/stm32f1xx_hal_rcc.c | 1403 ++ .../Src/stm32f1xx_hal_rcc_ex.c | 863 + .../Src/stm32f1xx_hal_tim.c | 7421 ++++++ .../Src/stm32f1xx_hal_tim_ex.c | 2296 ++ .../uksvep_2_2_v1_STM32F103RC_1.0.0.dbgconf | 36 + MDK-ARM/EventRecorderStub.scvd | 9 + MDK-ARM/JLinkLog.txt | 20283 ++++++++++++++++ MDK-ARM/JLinkSettings.ini | 39 + MDK-ARM/RTE/_uksvep_2_2_v1/RTE_Components.h | 21 + MDK-ARM/startup_stm32f103xe.lst | 1461 ++ MDK-ARM/startup_stm32f103xe.s | 356 + MDK-ARM/uksvep_2_2_v1.uvguix.dimas | 3842 +++ MDK-ARM/uksvep_2_2_v1.uvguix.test | 3628 +++ MDK-ARM/uksvep_2_2_v1.uvguix.yura | 3655 +++ MDK-ARM/uksvep_2_2_v1.uvoptx | 644 + MDK-ARM/uksvep_2_2_v1.uvprojx | 1608 ++ MDK-ARM/uksvep_2_2_v1/ExtDll.iex | 2 + MDK-ARM/uksvep_2_2_v1/can.crf | Bin 0 -> 621420 bytes MDK-ARM/uksvep_2_2_v1/can.d | 34 + MDK-ARM/uksvep_2_2_v1/can.o | Bin 0 -> 705320 bytes MDK-ARM/uksvep_2_2_v1/crc16.crf | Bin 0 -> 4812 bytes MDK-ARM/uksvep_2_2_v1/crc16.d | 3 + MDK-ARM/uksvep_2_2_v1/crc16.o | Bin 0 -> 16144 bytes MDK-ARM/uksvep_2_2_v1/ecan.crf | Bin 0 -> 621927 bytes MDK-ARM/uksvep_2_2_v1/ecan.d | 37 + MDK-ARM/uksvep_2_2_v1/ecan.o | Bin 0 -> 704256 bytes MDK-ARM/uksvep_2_2_v1/eeprom.crf | Bin 0 -> 612350 bytes MDK-ARM/uksvep_2_2_v1/eeprom.d | 30 + MDK-ARM/uksvep_2_2_v1/eeprom.o | Bin 0 -> 683884 bytes MDK-ARM/uksvep_2_2_v1/gpio.crf | Bin 0 -> 616334 bytes MDK-ARM/uksvep_2_2_v1/gpio.d | 31 + MDK-ARM/uksvep_2_2_v1/gpio.o | Bin 0 -> 687128 bytes MDK-ARM/uksvep_2_2_v1/lampa.crf | Bin 0 -> 621592 bytes MDK-ARM/uksvep_2_2_v1/lampa.d | 36 + MDK-ARM/uksvep_2_2_v1/lampa.o | Bin 0 -> 699300 bytes MDK-ARM/uksvep_2_2_v1/main.crf | Bin 0 -> 624302 bytes MDK-ARM/uksvep_2_2_v1/main.d | 38 + MDK-ARM/uksvep_2_2_v1/main.o | Bin 0 -> 706388 bytes MDK-ARM/uksvep_2_2_v1/message.crf | Bin 0 -> 617853 bytes MDK-ARM/uksvep_2_2_v1/message.d | 34 + MDK-ARM/uksvep_2_2_v1/message.o | Bin 0 -> 694692 bytes MDK-ARM/uksvep_2_2_v1/startup_stm32f103xe.d | 1 + MDK-ARM/uksvep_2_2_v1/startup_stm32f103xe.o | Bin 0 -> 6780 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal.crf | Bin 0 -> 613309 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal.o | Bin 0 -> 715484 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_adc.crf | Bin 0 -> 617174 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_adc.d | 30 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_adc.o | Bin 0 -> 726652 bytes .../uksvep_2_2_v1/stm32f1xx_hal_adc_ex.crf | Bin 0 -> 612260 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_adc_ex.d | 30 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_adc_ex.o | Bin 0 -> 706444 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_can.crf | Bin 0 -> 622519 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_can.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_can.o | Bin 0 -> 738132 bytes .../uksvep_2_2_v1/stm32f1xx_hal_cortex.crf | Bin 0 -> 612765 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_cortex.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_cortex.o | Bin 0 -> 705544 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_dma.crf | Bin 0 -> 624373 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_dma.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_dma.o | Bin 0 -> 704364 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_exti.crf | Bin 0 -> 614917 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_exti.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_exti.o | Bin 0 -> 694972 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_flash.crf | Bin 0 -> 616714 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_flash.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_flash.o | Bin 0 -> 702828 bytes .../uksvep_2_2_v1/stm32f1xx_hal_flash_ex.crf | Bin 0 -> 617938 bytes .../uksvep_2_2_v1/stm32f1xx_hal_flash_ex.d | 29 + .../uksvep_2_2_v1/stm32f1xx_hal_flash_ex.o | Bin 0 -> 702268 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_gpio.crf | Bin 0 -> 615822 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_gpio.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_gpio.o | Bin 0 -> 694540 bytes .../uksvep_2_2_v1/stm32f1xx_hal_gpio_ex.crf | Bin 0 -> 611965 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_gpio_ex.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_gpio_ex.o | Bin 0 -> 684452 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_msp.crf | Bin 0 -> 612195 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_msp.d | 30 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_msp.o | Bin 0 -> 682240 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_pwr.crf | Bin 0 -> 614763 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_pwr.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_pwr.o | Bin 0 -> 705712 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_rcc.crf | Bin 0 -> 624106 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_rcc.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_rcc.o | Bin 0 -> 705048 bytes .../uksvep_2_2_v1/stm32f1xx_hal_rcc_ex.crf | Bin 0 -> 614675 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_rcc_ex.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_rcc_ex.o | Bin 0 -> 686512 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_tim.crf | Bin 0 -> 677180 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_tim.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_tim.o | Bin 0 -> 880240 bytes .../uksvep_2_2_v1/stm32f1xx_hal_tim_ex.crf | Bin 0 -> 637585 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_tim_ex.d | 29 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_tim_ex.o | Bin 0 -> 755660 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_uart.crf | Bin 0 -> 620941 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_uart.d | 30 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_hal_uart.o | Bin 0 -> 764992 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_it.crf | Bin 0 -> 612519 bytes MDK-ARM/uksvep_2_2_v1/stm32f1xx_it.d | 31 + MDK-ARM/uksvep_2_2_v1/stm32f1xx_it.o | Bin 0 -> 696964 bytes MDK-ARM/uksvep_2_2_v1/system_stm32f1xx.crf | Bin 0 -> 612177 bytes MDK-ARM/uksvep_2_2_v1/system_stm32f1xx.d | 29 + MDK-ARM/uksvep_2_2_v1/system_stm32f1xx.o | Bin 0 -> 683456 bytes MDK-ARM/uksvep_2_2_v1/tim.crf | Bin 0 -> 613131 bytes MDK-ARM/uksvep_2_2_v1/tim.d | 33 + MDK-ARM/uksvep_2_2_v1/tim.o | Bin 0 -> 689964 bytes MDK-ARM/uksvep_2_2_v1/uksvep_2_2_v1.axf | Bin 0 -> 660816 bytes .../uksvep_2_2_v1/uksvep_2_2_v1.build_log.htm | 85 + MDK-ARM/uksvep_2_2_v1/uksvep_2_2_v1.hex | 661 + MDK-ARM/uksvep_2_2_v1/uksvep_2_2_v1.htm | 1202 + MDK-ARM/uksvep_2_2_v1/uksvep_2_2_v1.lnp | 31 + MDK-ARM/uksvep_2_2_v1/uksvep_2_2_v1.map | 1811 ++ MDK-ARM/uksvep_2_2_v1/uksvep_2_2_v1.sct | 16 + .../uksvep_2_2_v1_uksvep_2_2_v1.dep | 714 + uksvep_2_2_v1.ioc | 277 + 196 files changed, 122289 insertions(+) create mode 100644 .mxproject create mode 100644 Core/Inc/can.h create mode 100644 Core/Inc/crc16.h create mode 100644 Core/Inc/eeprom.h create mode 100644 Core/Inc/gpio.h create mode 100644 Core/Inc/lampa.h create mode 100644 Core/Inc/main.h create mode 100644 Core/Inc/message.h create mode 100644 Core/Inc/package.h create mode 100644 Core/Inc/stm32f1xx_hal_conf.h create mode 100644 Core/Inc/stm32f1xx_it.h create mode 100644 Core/Inc/struc.h create mode 100644 Core/Inc/tim.h create mode 100644 Core/Src/can.c create mode 100644 Core/Src/crc16.c create mode 100644 Core/Src/eeprom.c create mode 100644 Core/Src/gpio.c create mode 100644 Core/Src/lampa.c create mode 100644 Core/Src/main.c create mode 100644 Core/Src/message.c create mode 100644 Core/Src/stm32f1xx_hal_msp.c create mode 100644 Core/Src/stm32f1xx_it.c create mode 100644 Core/Src/syscalls.c create mode 100644 Core/Src/sysmem.c create mode 100644 Core/Src/system_stm32f1xx.c create mode 100644 Core/Src/tim.c create mode 100644 Core/Startup/startup_stm32f103rctx.s create mode 100644 Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h create mode 100644 Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h create mode 100644 Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h create mode 100644 Drivers/CMSIS/Device/ST/STM32F1xx/License.md create mode 100644 Drivers/CMSIS/Include/cmsis_armcc.h create mode 100644 Drivers/CMSIS/Include/cmsis_armclang.h create mode 100644 Drivers/CMSIS/Include/cmsis_compiler.h create mode 100644 Drivers/CMSIS/Include/cmsis_gcc.h create mode 100644 Drivers/CMSIS/Include/cmsis_iccarm.h create mode 100644 Drivers/CMSIS/Include/cmsis_version.h create mode 100644 Drivers/CMSIS/Include/core_armv8mbl.h create mode 100644 Drivers/CMSIS/Include/core_armv8mml.h create mode 100644 Drivers/CMSIS/Include/core_cm0.h create mode 100644 Drivers/CMSIS/Include/core_cm0plus.h create mode 100644 Drivers/CMSIS/Include/core_cm1.h create mode 100644 Drivers/CMSIS/Include/core_cm23.h create mode 100644 Drivers/CMSIS/Include/core_cm3.h create mode 100644 Drivers/CMSIS/Include/core_cm33.h create mode 100644 Drivers/CMSIS/Include/core_cm4.h create mode 100644 Drivers/CMSIS/Include/core_cm7.h create mode 100644 Drivers/CMSIS/Include/core_sc000.h create mode 100644 Drivers/CMSIS/Include/core_sc300.h create mode 100644 Drivers/CMSIS/Include/mpu_armv7.h create mode 100644 Drivers/CMSIS/Include/mpu_armv8.h create mode 100644 Drivers/CMSIS/Include/tz_context.h create mode 100644 Drivers/CMSIS/LICENSE.txt create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h create mode 100644 Drivers/STM32F1xx_HAL_Driver/License.md create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c create mode 100644 Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c create mode 100644 MDK-ARM/DebugConfig/uksvep_2_2_v1_STM32F103RC_1.0.0.dbgconf create mode 100644 MDK-ARM/EventRecorderStub.scvd create mode 100644 MDK-ARM/JLinkLog.txt create mode 100644 MDK-ARM/JLinkSettings.ini create mode 100644 MDK-ARM/RTE/_uksvep_2_2_v1/RTE_Components.h create mode 100644 MDK-ARM/startup_stm32f103xe.lst create mode 100644 MDK-ARM/startup_stm32f103xe.s create mode 100644 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MDK-ARM/uksvep_2_2_v1/uksvep_2_2_v1_uksvep_2_2_v1.dep create mode 100644 uksvep_2_2_v1.ioc diff --git a/.mxproject b/.mxproject new file mode 100644 index 0000000..5693451 --- /dev/null +++ b/.mxproject @@ -0,0 +1,36 @@ +[PreviousLibFiles] +LibFiles=Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_can.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_can.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_can.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f103xe.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[PreviousUsedCubeIDEFiles] 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+HeaderPath=Drivers\STM32F1xx_HAL_Driver\Inc;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F1xx\Include;Drivers\CMSIS\Include;Core\Inc; +CDefines=USE_HAL_DRIVER;STM32F103xE;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousUsedKeilFiles] +SourceFiles=..\Core\Src\main.c;..\Core\Src\gpio.c;..\Core\Src\can.c;..\Core\Src\tim.c;..\Core\Src\stm32f1xx_it.c;..\Core\Src\stm32f1xx_hal_msp.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_can.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;..\Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;..\Core\Src\system_stm32f1xx.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_can.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;..\Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;..\Core\Src\system_stm32f1xx.c;;; +HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc; +CDefines=USE_HAL_DRIVER;STM32F103xE;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=6 +HeaderFiles#0=..\Core\Inc\gpio.h +HeaderFiles#1=..\Core\Inc\can.h +HeaderFiles#2=..\Core\Inc\tim.h +HeaderFiles#3=..\Core\Inc\stm32f1xx_it.h +HeaderFiles#4=..\Core\Inc\stm32f1xx_hal_conf.h +HeaderFiles#5=..\Core\Inc\main.h +HeaderFolderListSize=1 +HeaderPath#0=..\Core\Inc +HeaderFiles=; +SourceFileListSize=6 +SourceFiles#0=..\Core\Src\gpio.c +SourceFiles#1=..\Core\Src\can.c +SourceFiles#2=..\Core\Src\tim.c +SourceFiles#3=..\Core\Src\stm32f1xx_it.c +SourceFiles#4=..\Core\Src\stm32f1xx_hal_msp.c +SourceFiles#5=..\Core\Src\main.c +SourceFolderListSize=1 +SourcePath#0=..\Core\Src +SourceFiles=; + diff --git a/Core/Inc/can.h b/Core/Inc/can.h new file mode 100644 index 0000000..2232145 --- /dev/null +++ b/Core/Inc/can.h @@ -0,0 +1,55 @@ +/** + ****************************************************************************** + * @file can.h + * @brief This file contains all the function prototypes for + * the can.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2025 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CAN_H__ +#define __CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern CAN_HandleTypeDef hcan; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_CAN_Init(void); + +/* USER CODE BEGIN Prototypes */ + +void Setup_CAN_addr(uint8_t mode); +int CAN_send(uint16_t data[], int Addr, int Qua); + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/crc16.h b/Core/Inc/crc16.h new file mode 100644 index 0000000..f4757f6 --- /dev/null +++ b/Core/Inc/crc16.h @@ -0,0 +1,10 @@ +#include "stdint.h" + +typedef unsigned short WORD; +typedef unsigned char byte; + + +unsigned int get_crc_ccitt(unsigned int crc, unsigned int *buf, unsigned long size ); +unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size ); +unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size ); +int get_crc16(uint16_t *buf, int size ); diff --git a/Core/Inc/eeprom.h b/Core/Inc/eeprom.h new file mode 100644 index 0000000..6488e10 --- /dev/null +++ b/Core/Inc/eeprom.h @@ -0,0 +1,20 @@ +#ifndef __EEPROM_H +#define __EEPROM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stm32f1xx_hal.h" + +#define FLASH_EEPROM_BASE 0x0801F800 +#define FLASH_STARTO 0xBABEFACE + +void putIntoEeprom(uint16_t, uint16_t*); +uint16_t watInTheFlash(uint32_t); + +#ifdef __cplusplus +} +#endif + +#endif /* __EEPROM_H */ diff --git a/Core/Inc/gpio.h b/Core/Inc/gpio.h new file mode 100644 index 0000000..35e5ecd --- /dev/null +++ b/Core/Inc/gpio.h @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2025 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ +#define IN_01_Pin GPIO_PIN_3 +#define IN_01_GPIO_Port GPIOA +#define IN_02_Pin GPIO_PIN_2 +#define IN_02_GPIO_Port GPIOA +#define IN_03_Pin GPIO_PIN_1 +#define IN_03_GPIO_Port GPIOA +#define IN_04_Pin GPIO_PIN_0 +#define IN_04_GPIO_Port GPIOA +#define IN_05_Pin GPIO_PIN_15 +#define IN_05_GPIO_Port GPIOC +#define IN_06_Pin GPIO_PIN_13 +#define IN_06_GPIO_Port GPIOC +#define IN_07_Pin GPIO_PIN_15 +#define IN_07_GPIO_Port GPIOB +#define IN_08_Pin GPIO_PIN_14 +#define IN_08_GPIO_Port GPIOB +#define IN_09_Pin GPIO_PIN_13 +#define IN_09_GPIO_Port GPIOB +#define IN_10_Pin GPIO_PIN_12 +#define IN_10_GPIO_Port GPIOB +#define IN_11_Pin GPIO_PIN_1 +#define IN_11_GPIO_Port GPIOB +#define IN_12_Pin GPIO_PIN_0 +#define IN_12_GPIO_Port GPIOB +#define IN_13_Pin GPIO_PIN_5 +#define IN_13_GPIO_Port GPIOA +#define IN_14_Pin GPIO_PIN_4 +#define IN_14_GPIO_Port GPIOA + +#define J0_Pin GPIO_PIN_6 +#define J0_GPIO_Port GPIOA +#define J1_Pin GPIO_PIN_7 +#define J1_GPIO_Port GPIOA +#define J2_Pin GPIO_PIN_4 +#define J2_GPIO_Port GPIOC +#define J3_Pin GPIO_PIN_5 +#define J3_GPIO_Port GPIOC +#define Jselect_Pin GPIO_PIN_14 +#define Jselect_GPIO_Port GPIOC + +#define LED0_Pin GPIO_PIN_5 +#define LED0_GPIO_Port GPIOB +#define LED1_Pin GPIO_PIN_6 +#define LED1_GPIO_Port GPIOB +#define LED2_Pin GPIO_PIN_2 +#define LED2_GPIO_Port GPIOC +#define LED3_Pin GPIO_PIN_3 +#define LED3_GPIO_Port GPIOC + +#define PVT4_Pin GPIO_PIN_6 +#define PVT4_GPIO_Port GPIOC +#define PVT3_Pin GPIO_PIN_7 +#define PVT3_GPIO_Port GPIOC +#define PVT2_Pin GPIO_PIN_8 +#define PVT2_GPIO_Port GPIOC +#define PVT1_Pin GPIO_PIN_9 +#define PVT1_GPIO_Port GPIOC + +#define BOOT1_Pin GPIO_PIN_2 +#define BOOT1_GPIO_Port GPIOB + +#define LED_0_OFF HAL_GPIO_WritePin(LED0_GPIO_Port, LED0_Pin, GPIO_PIN_SET) //Set or clear the selected data port bit +#define LED_0_ON HAL_GPIO_WritePin(LED0_GPIO_Port, LED0_Pin, GPIO_PIN_RESET) //??? ?????? ?? ?????????? +#define LED_0_TGL HAL_GPIO_TogglePin(LED0_GPIO_Port, LED0_Pin) + +#define LED_1_OFF HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET) //Set or clear the selected data port bit +#define LED_1_ON HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET) //??? ?????? ?? ?????????? +#define LED_1_TGL HAL_GPIO_TogglePin(LED1_GPIO_Port, LED1_Pin) + +#define LED_2_ON HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET) //Set or clear the selected data port bit +#define LED_2_OFF HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET) //??? ?????? ?? ?????????? +#define LED_2_TGL HAL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin) + +#define LED_3_ON HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_SET) //Set or clear the selected data port bit +#define LED_3_OFF HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET) //??? ?????? ?? ?????????? +#define LED_3_TGL HAL_GPIO_TogglePin(LED3_GPIO_Port, LED3_Pin) + +#define Pvt1_ON HAL_GPIO_WritePin(PVT1_GPIO_Port, PVT1_Pin, GPIO_PIN_SET) //Set or clear the selected data port bit +#define Pvt1_OFF HAL_GPIO_WritePin(PVT1_GPIO_Port, PVT1_Pin, GPIO_PIN_RESET) //??? ?????? ?? ?????????? +#define Pvt1_TGL HAL_GPIO_TogglePin(PVT1_GPIO_Port, PVT1_Pin) + +#define Pvt2_ON HAL_GPIO_WritePin(PVT2_GPIO_Port, PVT2_Pin, GPIO_PIN_SET) //set - ????????????? ???, reset - ??????? ??? +#define Pvt2_OFF HAL_GPIO_WritePin(PVT2_GPIO_Port, PVT2_Pin, GPIO_PIN_RESET) //????? ??????? ? main.h ??????? ?????? ????????????? +#define Pvt2_TGL HAL_GPIO_TogglePin(PVT2_GPIO_Port, PVT2_Pin) + +#define Pvt3_ON HAL_GPIO_WritePin(PVT3_GPIO_Port, PVT3_Pin, GPIO_PIN_SET) +#define Pvt3_OFF HAL_GPIO_WritePin(PVT3_GPIO_Port, PVT3_Pin, GPIO_PIN_RESET) +#define Pvt3_TGL HAL_GPIO_TogglePin(PVT3_GPIO_Port, PVT3_Pin) + +#define Pvt4_ON HAL_GPIO_WritePin(PVT4_GPIO_Port, PVT4_Pin, GPIO_PIN_SET) +#define Pvt4_OFF HAL_GPIO_WritePin(PVT4_GPIO_Port, PVT4_Pin, GPIO_PIN_RESET) +#define Pvt4_TGL HAL_GPIO_TogglePin(PVT4_GPIO_Port, PVT4_Pin) + +#define IN_01 HAL_GPIO_ReadPin(IN_01_GPIO_Port, IN_01_Pin) // ???????? ??1 (??????? ???????????? ???????????) +#define IN_02 HAL_GPIO_ReadPin(IN_02_GPIO_Port, IN_02_Pin) // ???????? ??2 (??????? ???????????? ?????????) +#define IN_03 HAL_GPIO_ReadPin(IN_03_GPIO_Port, IN_03_Pin) // ???????? ??3 (??????? ??. ??????, ???? ?????????, ????) +#define IN_04 HAL_GPIO_ReadPin(IN_04_GPIO_Port, IN_04_Pin) // ???????? ??4 (??????? ???????? ???? ? ?????????? +) +#define IN_05 HAL_GPIO_ReadPin(IN_05_GPIO_Port, IN_05_Pin) // ???????? ??5 (??????? ???????? ???? ? ?????????? –) +#define IN_06 HAL_GPIO_ReadPin(IN_06_GPIO_Port, IN_06_Pin) // ???????? ??6 (??????? ?????????) +#define IN_07 HAL_GPIO_ReadPin(IN_07_GPIO_Port, IN_07_Pin) // ???????? 3? ??????? 380 ? + +#define IN_08 HAL_GPIO_ReadPin(IN_08_GPIO_Port, IN_08_Pin) // ????? ?????????? +#define IN_09 HAL_GPIO_ReadPin(IN_09_GPIO_Port, IN_09_Pin) // ?????? ?????????? +#define IN_10 HAL_GPIO_ReadPin(IN_10_GPIO_Port, IN_10_Pin) // ?????? ? ???? 24 ? + +#define IN_11 HAL_GPIO_ReadPin(IN_11_GPIO_Port, IN_11_Pin) // ???????? ??????? ??? +#define IN_12 HAL_GPIO_ReadPin(IN_12_GPIO_Port, IN_12_Pin) // ?????? +#define IN_13 HAL_GPIO_ReadPin(IN_13_GPIO_Port, IN_13_Pin) // ?????? +#define IN_14 HAL_GPIO_ReadPin(IN_14_GPIO_Port, IN_14_Pin) // ???????? ??????? ??? + +#define J0 HAL_GPIO_ReadPin(J0_GPIO_Port, J0_Pin) //Read the specified input port pin +#define J1 HAL_GPIO_ReadPin(J1_GPIO_Port, J1_Pin) +#define J2 HAL_GPIO_ReadPin(J2_GPIO_Port, J2_Pin) +#define J3 HAL_GPIO_ReadPin(J3_GPIO_Port, J3_Pin) + +#define Jselect HAL_GPIO_ReadPin(Jselect_GPIO_Port, Jselect_Pin) + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/lampa.h b/Core/Inc/lampa.h new file mode 100644 index 0000000..24c930b --- /dev/null +++ b/Core/Inc/lampa.h @@ -0,0 +1,30 @@ +#ifndef __LAMPA_H +#define __LAMPA_H + +/* +* ΠŸΡ€ΠΈΠΌΠ΅Π½ΡΠ΅Ρ‚ΡΡ ΠΌΠ΅Ρ‚ΠΎΠ΄ Π‘Π»ΠΎΠΉ Π°ΠΏΠΏΠ°Ρ€Π°Ρ‚Π½Ρ‹Ρ… абстракции(HAL) Ρ‚Π°ΠΊ ΠΎΠ½ послСдний(ΠΌΠΎΠ΄Π½Ρ‹ΠΉ), +* Ρ‚ΡƒΡ‚ описано Π±ΠΈΠ±Π»ΠΈΠΎΡ‚Π΅Ρ‡Π½Ρ‹Π΅ Π²Ρ‹Π·ΠΎΠ²Ρ‹ +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "main.h" +#include "stdbool.h" + + +#define Delay 1000 +#define numUno 1 +#define numNul 0 + +void ReadEnteres(void); +uint16_t ReadJumpers(void); +uint16_t TestJumper(void); +void ReadSeanus(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Core/Inc/main.h b/Core/Inc/main.h new file mode 100644 index 0000000..a0d06c7 --- /dev/null +++ b/Core/Inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +void Millisecond(void); + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/message.h b/Core/Inc/message.h new file mode 100644 index 0000000..01afb7b --- /dev/null +++ b/Core/Inc/message.h @@ -0,0 +1,25 @@ +#ifndef MESSAGE_H +#define MESSAGE_H + +#include "stdint.h" +#include "struc.h" + +typedef unsigned char CHAR; + +#define Modbus_LEN 0x000080 +#define Modbus ((WORDE *)modbus) + +extern uint16_t Mode; + +extern uint16_t modbus[],archiv[],county[],espero[]; + +extern LONGE* outputs; + +extern uint16_t Maska[][8]; + + +void Save_params(void); +void Load_params(void); +void Default_params(void); + +#endif //MESSAGE_H diff --git a/Core/Inc/package.h b/Core/Inc/package.h new file mode 100644 index 0000000..705747e --- /dev/null +++ b/Core/Inc/package.h @@ -0,0 +1,57 @@ +#ifndef PACKAGE +#define PACKAGE + +#define PROTOKOL 3 + +#define m_FAST 0 +#define m_SLOW 1 + +#define keys 0x0 + +#define Inputs Modbus[0x0] +#define Alarms Modbus[0x1] +#define Errors Modbus[0x2] + +#define Alarm_mask Modbus[0x8] +#define Error_mask Modbus[0x9] + +#define Error_mask Modbus[0x9] + +#define Jumpers Modbus[0x10] +#define Buttons Modbus[0x11] +#define jumpers modbus[0x10] +#define buttons modbus[0x11] + +#define Squazh_U (modbus+0x20) + +#define Sleep_time modbus[0x48] + +#define Squazh_L (modbus+0x30) + +#define Cancount (modbus+0x60) // ΠΏΠ°ΡƒΠ·Π° ΠΌΠ΅ΠΆΠ΄Ρƒ I посылками CAN +#define CanWait (modbus+0x62) // максимальнаа ΠΏΠ°ΡƒΠ·Π° +#define CanRestart (modbus+0x64) // пСрСзапуск посылки +#define CanRepeat modbus[0x66] // сколько Ρ€Π°Π· ΠΏΠΎΠ²Ρ‚ΠΎΡ€Π°Ρ‚ΡŒ Π½Π°Π΄ΠΎ + +#define Brightness modbus[0x68] // Π°Ρ€ΠΊΠΎΡΡ‚ΡŒ сигнальной Π»Π°ΠΌΠΏΠΎΡ‡ΠΊΠΈ + +#define cancyclo 0x78 // Π΅Π³ΠΎ адрСс +#define CanCycle (modbus+0x78) // счСтчик Ρ†ΠΈΠΊΠ»ΠΎΠ² CAN +#define CanRound (modbus+0x7A) // счСтчик Π΅Ρ‰Π΅ Π±ΠΎΠ»Π΅Π΅ ΠΏΠΎΠ»Π½Ρ‹Ρ… Ρ†ΠΈΠΊΠ»ΠΎΠ² CAN + +#define Protokol modbus[125] +#define LastMode Modbus[126].all + +#define Commands Modbus[127].all +#define cTestLamp Modbus[127].bit.bit0 +#define cDefParam Modbus[127].bit.bit1 +#define cSaveParam Modbus[127].bit.bit2 +#define cLoadParam Modbus[127].bit.bit3 + +#define cExtLamp Modbus[127].bit.bit6 +#define cExtLite Modbus[127].bit.bit7 + +#define cReset Modbus[127].bit.bitF + +#endif //PACKAGE + diff --git a/Core/Inc/stm32f1xx_hal_conf.h b/Core/Inc/stm32f1xx_hal_conf.h new file mode 100644 index 0000000..8ee9c3a --- /dev/null +++ b/Core/Inc/stm32f1xx_hal_conf.h @@ -0,0 +1,391 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_CONF_H +#define __STM32F1xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED + /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +#define HAL_CAN_MODULE_ENABLED +/*#define HAL_CAN_LEGACY_MODULE_ENABLED */ +/*#define HAL_CEC_MODULE_ENABLED */ +/*#define HAL_CORTEX_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_DMA_MODULE_ENABLED */ +/*#define HAL_ETH_MODULE_ENABLED */ +/*#define HAL_FLASH_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_PCCARD_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_PWR_MODULE_ENABLED */ +/*#define HAL_RCC_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_SDRAM_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ + +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB 8U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY 0x000000FFU +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY 0x00000FFFU + +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32f1xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32f1xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32f1xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32f1xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32f1xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED +#include "stm32f1xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32f1xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED +#include "stm32f1xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32f1xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32f1xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32f1xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32f1xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32f1xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32f1xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32f1xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32f1xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32f1xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32f1xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32f1xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32f1xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED +#include "stm32f1xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32f1xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32f1xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32f1xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32f1xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32f1xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32f1xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32f1xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32f1xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32f1xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32f1xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32f1xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32f1xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t* file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/stm32f1xx_it.h b/Core/Inc/stm32f1xx_it.h new file mode 100644 index 0000000..39b3625 --- /dev/null +++ b/Core/Inc/stm32f1xx_it.h @@ -0,0 +1,72 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f1xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_IT_H +#define __STM32F1xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void USB_HP_CAN1_TX_IRQHandler(void); +void USB_LP_CAN1_RX0_IRQHandler(void); +void TIM4_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/struc.h b/Core/Inc/struc.h new file mode 100644 index 0000000..09e14b4 --- /dev/null +++ b/Core/Inc/struc.h @@ -0,0 +1,153 @@ +#ifndef __STRUC_H +#define __STRUC_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef union +{ + struct + { + unsigned char bit0: 1; + unsigned char bit1: 1; + unsigned char bit2: 1; + unsigned char bit3: 1; + unsigned char bit4: 1; + unsigned char bit5: 1; + unsigned char bit6: 1; + unsigned char bit7: 1; + + } bit; + + struct + { + unsigned char quad_0 :4; + unsigned char quad_1 :4; + + } qua; + + unsigned char all; + +} BAITE; + +typedef union +{ + struct + { + unsigned short int bit0: 1; + unsigned short int bit1: 1; + unsigned short int bit2: 1; + unsigned short int bit3: 1; + unsigned short int bit4: 1; + unsigned short int bit5: 1; + unsigned short int bit6: 1; + unsigned short int bit7: 1; + unsigned short int bit8: 1; + unsigned short int bit9: 1; + unsigned short int bitA: 1; + unsigned short int bitB: 1; + unsigned short int bitC: 1; + unsigned short int bitD: 1; + unsigned short int bitE: 1; + unsigned short int bitF: 1; + + } bit; + + struct + { + unsigned short int quad_0 :4; + unsigned short int quad_1 :4; + unsigned short int quad_2 :4; + unsigned short int quad_3 :4; + + } qua; + + struct + { + unsigned short int byte_0 :8; + unsigned short int byte_1 :8; + + } byt; + + unsigned short int all; + +} WORDE; + +typedef union +{ + struct + { + unsigned int bit00: 1; + unsigned int bit01: 1; + unsigned int bit02: 1; + unsigned int bit03: 1; + unsigned int bit04: 1; + unsigned int bit05: 1; + unsigned int bit06: 1; + unsigned int bit07: 1; + unsigned int bit08: 1; + unsigned int bit09: 1; + unsigned int bit0A: 1; + unsigned int bit0B: 1; + unsigned int bit0C: 1; + unsigned int bit0D: 1; + unsigned int bit0E: 1; + unsigned int bit0F: 1; + unsigned int bit10: 1; + unsigned int bit11: 1; + unsigned int bit12: 1; + unsigned int bit13: 1; + unsigned int bit14: 1; + unsigned int bit15: 1; + unsigned int bit16: 1; + unsigned int bit17: 1; + unsigned int bit18: 1; + unsigned int bit19: 1; + unsigned int bit1A: 1; + unsigned int bit1B: 1; + unsigned int bit1C: 1; + unsigned int bit1D: 1; + unsigned int bit1E: 1; + unsigned int bit1F: 1; + + } bit; + + struct + { + unsigned int quad_0 :4; + unsigned int quad_1 :4; + unsigned int quad_2 :4; + unsigned int quad_3 :4; + unsigned int quad_4 :4; + unsigned int quad_5 :4; + unsigned int quad_6 :4; + unsigned int quad_7 :4; + + } qua; + + struct + { + unsigned int byte_0 :8; + unsigned int byte_1 :8; + unsigned int byte_2 :8; + unsigned int byte_3 :8; + + } byt; + + struct + { + unsigned int word_0 :16; + unsigned int word_1 :16; + + } wrd; + + unsigned int all; + +} LONGE; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Core/Inc/tim.h b/Core/Inc/tim.h new file mode 100644 index 0000000..948c1ca --- /dev/null +++ b/Core/Inc/tim.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2025 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern TIM_HandleTypeDef htim4; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_TIM4_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/can.c b/Core/Src/can.c new file mode 100644 index 0000000..9013900 --- /dev/null +++ b/Core/Src/can.c @@ -0,0 +1,275 @@ +/** + ****************************************************************************** + * @file can.c + * @brief This file provides code for the configuration + * of the CAN instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2025 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "can.h" + +/* USER CODE BEGIN 0 */ + +#include "gpio.h" +#include "message.h" + +void CAN_filterConfig(void); + +CAN_TxHeaderTypeDef TxHeader; +CAN_RxHeaderTypeDef RxHeader; + +CAN_FilterTypeDef sFilterConfig; + +CAN_TxHeaderTypeDef msgHeaderSend; +uint8_t msgDataSend[8]; +uint32_t mailBoxNum = 0; + +uint8_t TxData[8]; +uint8_t RxData[8]; +uint32_t TxMailbox; + +uint32_t TX_box_ID = 0; +uint32_t RX_box_ID = 0; +uint32_t BC_box_ID = 0; + + +/* USER CODE END 0 */ + +CAN_HandleTypeDef hcan; + +/* CAN init function */ +void MX_CAN_Init(void) +{ + + /* USER CODE BEGIN CAN_Init 0 */ + + /* USER CODE END CAN_Init 0 */ + + /* USER CODE BEGIN CAN_Init 1 */ + + /* USER CODE END CAN_Init 1 */ + hcan.Instance = CAN1; + hcan.Init.Prescaler = 10; + hcan.Init.Mode = CAN_MODE_NORMAL; + hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; + hcan.Init.TimeSeg1 = CAN_BS1_13TQ; + hcan.Init.TimeSeg2 = CAN_BS2_2TQ; + hcan.Init.TimeTriggeredMode = DISABLE; + hcan.Init.AutoBusOff = DISABLE; + hcan.Init.AutoWakeUp = DISABLE; + hcan.Init.AutoRetransmission = DISABLE; + hcan.Init.ReceiveFifoLocked = DISABLE; + hcan.Init.TransmitFifoPriority = DISABLE; + if (HAL_CAN_Init(&hcan) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CAN_Init 2 */ + + CAN_filterConfig(); + + msgHeaderSend.StdId = 0x200; + msgHeaderSend.ExtId = TX_box_ID; + msgHeaderSend.DLC = 8; + msgHeaderSend.TransmitGlobalTime = DISABLE; + msgHeaderSend.RTR = CAN_RTR_DATA; + msgHeaderSend.IDE = CAN_ID_EXT; + +// CAN start + if (HAL_CAN_Start(&hcan) != HAL_OK) + { + Error_Handler(); + } + +// CAN notifications (interrupts) + if (HAL_CAN_ActivateNotification(&hcan, CAN_IT_RX_FIFO0_MSG_PENDING | CAN_IT_TX_MAILBOX_EMPTY) != HAL_OK) + { + Error_Handler(); + } + + + + + + /* USER CODE END CAN_Init 2 */ + +} + +void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(canHandle->Instance==CAN1) + { + /* USER CODE BEGIN CAN1_MspInit 0 */ + + /* USER CODE END CAN1_MspInit 0 */ + /* CAN1 clock enable */ + __HAL_RCC_CAN1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**CAN GPIO Configuration + PA11 ------> CAN_RX + PA12 ------> CAN_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* CAN1 interrupt Init */ + HAL_NVIC_SetPriority(USB_HP_CAN1_TX_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn); + HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn); + /* USER CODE BEGIN CAN1_MspInit 1 */ + + /* USER CODE END CAN1_MspInit 1 */ + } +} + +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle) +{ + + if(canHandle->Instance==CAN1) + { + /* USER CODE BEGIN CAN1_MspDeInit 0 */ + + /* USER CODE END CAN1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CAN1_CLK_DISABLE(); + + /**CAN GPIO Configuration + PA11 ------> CAN_RX + PA12 ------> CAN_TX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + + /* CAN1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn); + HAL_NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn); + /* USER CODE BEGIN CAN1_MspDeInit 1 */ + + /* USER CODE END CAN1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +void Setup_CAN_addr(uint8_t mode) +{ + BC_box_ID = 0x1F<<20; + RX_box_ID = mode<<20; + TX_box_ID = RX_box_ID | (1L<<28); +} + +void CAN_filterConfig(void) +{ + + sFilterConfig.FilterBank = 0; + sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK; + sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT; + sFilterConfig.FilterIdHigh = 0x0000; + sFilterConfig.FilterIdLow = 0x0000; + sFilterConfig.FilterMaskIdHigh = 0x0000; + sFilterConfig.FilterMaskIdLow = 0x0000; + sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0; + sFilterConfig.FilterActivation = ENABLE; + sFilterConfig.SlaveStartFilterBank = 14; + + if (HAL_CAN_ConfigFilter(&hcan, &sFilterConfig) != HAL_OK) + { + Error_Handler(); +} } + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ +// HAL_GPIO_TogglePin(LED_2_GPIO_Port, LED_2_Pin); +} + + +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan_i) +{ + CAN_RxHeaderTypeDef msgHeader; + uint8_t msgData[8]; + + unsigned int adr,qua; + unsigned short Data[4]; + + if (HAL_CAN_GetRxMessage(hcan_i, CAN_RX_FIFO0, &msgHeader, msgData) != HAL_OK) + { + /* Reception Error */ + Error_Handler(); + } + + if((msgHeader.ExtId & 0xFF00000) != RX_box_ID) + if((msgHeader.ExtId & 0xFF00000) != BC_box_ID) return; + + adr = msgHeader.ExtId & 0xFFFF; + qua = msgHeader.DLC/2; + + Data[0] = msgData[0]; Data[0] = (Data[0]<<8) | msgData[1]; + Data[1] = msgData[2]; Data[1] = (Data[1]<<8) | msgData[3]; + Data[2] = msgData[4]; Data[2] = (Data[2]<<8) | msgData[5]; + Data[3] = msgData[6]; Data[3] = (Data[3]<<8) | msgData[7]; + + if(qua ) if(adr < Modbus_LEN) modbus[adr] = Data[0]; adr++; + if(qua>1) if(adr < Modbus_LEN) modbus[adr] = Data[1]; adr++; + if(qua>2) if(adr < Modbus_LEN) modbus[adr] = Data[2]; adr++; + if(qua>3) if(adr < Modbus_LEN) modbus[adr] = Data[3]; + + LED_1_TGL; +} + +int CAN_send(uint16_t data[], int Addr, int Qua) +{ + int wait = 1000; + + while(wait-- && (HAL_CAN_GetTxMailboxesFreeLevel(&hcan) == 0)); + + if (HAL_CAN_GetTxMailboxesFreeLevel(&hcan) != 0) + { + msgHeaderSend.ExtId = TX_box_ID | (Addr & 0xFFFF); + msgHeaderSend.DLC = Qua*2; + + msgDataSend[0] = (data[Addr ]>>8) & 0x00ff; + msgDataSend[1] = (data[Addr ] ) & 0x00ff; + msgDataSend[2] = (data[Addr+1]>>8) & 0x00ff; + msgDataSend[3] = (data[Addr+1] ) & 0x00ff; + msgDataSend[4] = (data[Addr+2]>>8) & 0x00ff; + msgDataSend[5] = (data[Addr+2] ) & 0x00ff; + msgDataSend[6] = (data[Addr+3]>>8) & 0x00ff; + msgDataSend[7] = (data[Addr+3] ) & 0x00ff; + + HAL_CAN_AddTxMessage(&hcan, &msgHeaderSend, msgDataSend, &mailBoxNum); + + LED_0_TGL; + return 1; + } + else + { + HAL_CAN_Stop(&hcan); + HAL_CAN_Start(&hcan); + return 0; +} } + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/crc16.c b/Core/Src/crc16.c new file mode 100644 index 0000000..188f47e --- /dev/null +++ b/Core/Src/crc16.c @@ -0,0 +1,196 @@ +#include "crc16.h" +#define MAKE_TABS 0 /* Builds tables below */ +#define FAST_CRC 1 /* If fast CRC should be used */ +#define ONLY_CRC16 1 + +#define Poln 0xA001 + + +#if FAST_CRC & !MAKE_TABS + +#if !ONLY_CRC16 + +static WORD crc_ccitt_tab[] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; +#endif + +WORD crc_16_tab[] = { + 0x0000, 0xc0c1, 0xc181, 0x0140, 0xc301, 0x03c0, 0x0280, 0xc241, + 0xc601, 0x06c0, 0x0780, 0xc741, 0x0500, 0xc5c1, 0xc481, 0x0440, + 0xcc01, 0x0cc0, 0x0d80, 0xcd41, 0x0f00, 0xcfc1, 0xce81, 0x0e40, + 0x0a00, 0xcac1, 0xcb81, 0x0b40, 0xc901, 0x09c0, 0x0880, 0xc841, + 0xd801, 0x18c0, 0x1980, 0xd941, 0x1b00, 0xdbc1, 0xda81, 0x1a40, + 0x1e00, 0xdec1, 0xdf81, 0x1f40, 0xdd01, 0x1dc0, 0x1c80, 0xdc41, + 0x1400, 0xd4c1, 0xd581, 0x1540, 0xd701, 0x17c0, 0x1680, 0xd641, + 0xd201, 0x12c0, 0x1380, 0xd341, 0x1100, 0xd1c1, 0xd081, 0x1040, + 0xf001, 0x30c0, 0x3180, 0xf141, 0x3300, 0xf3c1, 0xf281, 0x3240, + 0x3600, 0xf6c1, 0xf781, 0x3740, 0xf501, 0x35c0, 0x3480, 0xf441, + 0x3c00, 0xfcc1, 0xfd81, 0x3d40, 0xff01, 0x3fc0, 0x3e80, 0xfe41, + 0xfa01, 0x3ac0, 0x3b80, 0xfb41, 0x3900, 0xf9c1, 0xf881, 0x3840, + 0x2800, 0xe8c1, 0xe981, 0x2940, 0xeb01, 0x2bc0, 0x2a80, 0xea41, + 0xee01, 0x2ec0, 0x2f80, 0xef41, 0x2d00, 0xedc1, 0xec81, 0x2c40, + 0xe401, 0x24c0, 0x2580, 0xe541, 0x2700, 0xe7c1, 0xe681, 0x2640, + 0x2200, 0xe2c1, 0xe381, 0x2340, 0xe101, 0x21c0, 0x2080, 0xe041, + 0xa001, 0x60c0, 0x6180, 0xa141, 0x6300, 0xa3c1, 0xa281, 0x6240, + 0x6600, 0xa6c1, 0xa781, 0x6740, 0xa501, 0x65c0, 0x6480, 0xa441, + 0x6c00, 0xacc1, 0xad81, 0x6d40, 0xaf01, 0x6fc0, 0x6e80, 0xae41, + 0xaa01, 0x6ac0, 0x6b80, 0xab41, 0x6900, 0xa9c1, 0xa881, 0x6840, + 0x7800, 0xb8c1, 0xb981, 0x7940, 0xbb01, 0x7bc0, 0x7a80, 0xba41, + 0xbe01, 0x7ec0, 0x7f80, 0xbf41, 0x7d00, 0xbdc1, 0xbc81, 0x7c40, + 0xb401, 0x74c0, 0x7580, 0xb541, 0x7700, 0xb7c1, 0xb681, 0x7640, + 0x7200, 0xb2c1, 0xb381, 0x7340, 0xb101, 0x71c0, 0x7080, 0xb041, + 0x5000, 0x90c1, 0x9181, 0x5140, 0x9301, 0x53c0, 0x5280, 0x9241, + 0x9601, 0x56c0, 0x5780, 0x9741, 0x5500, 0x95c1, 0x9481, 0x5440, + 0x9c01, 0x5cc0, 0x5d80, 0x9d41, 0x5f00, 0x9fc1, 0x9e81, 0x5e40, + 0x5a00, 0x9ac1, 0x9b81, 0x5b40, 0x9901, 0x59c0, 0x5880, 0x9841, + 0x8801, 0x48c0, 0x4980, 0x8941, 0x4b00, 0x8bc1, 0x8a81, 0x4a40, + 0x4e00, 0x8ec1, 0x8f81, 0x4f40, 0x8d01, 0x4dc0, 0x4c80, 0x8c41, + 0x4400, 0x84c1, 0x8581, 0x4540, 0x8701, 0x47c0, 0x4680, 0x8641, + 0x8201, 0x42c0, 0x4380, 0x8341, 0x4100, 0x81c1, 0x8081, 0x4040 +}; +#endif + + +#if !ONLY_CRC16 + +/* CRC-CCITT is based on the polynomial x^16 + x^12 + x^5 + 1. Bits */ +/* are sent MSB to LSB. */ +unsigned int get_crc_ccitt(unsigned int crc,unsigned int *buf,unsigned long size ) +{ +#if !(FAST_CRC & !MAKE_TABS) + register int i; +#endif + + while (size--) { +#if FAST_CRC & !MAKE_TABS + crc = (crc << 8) ^ crc_ccitt_tab[ (crc >> 8) ^ *buf++ ]; +#else + crc ^= (WORD)(*buf++) << 8; + for (i = 0; i < 8; i++) { + if (crc & 0x8000) + crc = (crc << 1) ^ 0x1021; + else + crc <<= 1; + } +#endif + } return crc; +} +#endif + + +/* CRC-16 is based on the polynomial x^16 + x^15 + x^2 + 1. Bits are */ +/* sent LSB to MSB. */ +unsigned int get_crc_16(unsigned int crc,unsigned int *buf,unsigned long size ) +{ +#if !(FAST_CRC & !MAKE_TABS) + register unsigned int i; + register unsigned int ch; +#endif + + while (size--) { +#if FAST_CRC & !MAKE_TABS + + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ *buf++) & 0xff ]; + crc = crc & 0xffff; +#else + ch = *buf++; + for (i = 0; i < 8; i++) { + if ((crc ^ ch) & 1) + crc = (crc >> 1) ^ 0xa001; + else + crc >>= 1; + ch >>= 1; + } +#endif + } return (crc & 0xffff); +} + + + +unsigned int get_crc_16b(unsigned int crc,unsigned int *buf,unsigned long size ) +{ + +unsigned int x, dword, byte; +unsigned long i; + + + + for (i = 0; i < size; i++) + { + x = i % 2; + + dword = buf[i/2]; +// dword = *buf; + + + if (x == 0) + { + byte = ((dword >> 8)&0xFF); + } + + if (x == 1) + { + byte = (dword & 0xFF); + } + + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ (byte) ) & 0xff ]; + crc = crc & 0xffff; + +// crc = crc + ((byte) & 0xff); + + } + + return (crc & 0xffff); +} + +int get_crc16(uint16_t *buf, int size ) +{ + int crc16,i,j; + + crc16=0xFFFF; + for(i=0;i>1)^Poln; + else crc16=crc16>>1; + + crc16=crc16^((buf[i]>>8)&0xFF); + for (j=0;j<8;j++) + if(crc16&1) crc16=(crc16>>1)^Poln; + else crc16=crc16>>1; + } + return crc16; +} diff --git a/Core/Src/eeprom.c b/Core/Src/eeprom.c new file mode 100644 index 0000000..59ef802 --- /dev/null +++ b/Core/Src/eeprom.c @@ -0,0 +1,49 @@ +#include "eeprom.h" + + +void putIntoEeprom(uint16_t lenght, uint16_t* param) +{ +uint32_t adr = FLASH_EEPROM_BASE; +//uint32_t p = FLASH_STARTO; +HAL_StatusTypeDef flash_ok = HAL_ERROR; + + while(flash_ok != HAL_OK) + {flash_ok = HAL_FLASH_Unlock();} + + FLASH_EraseInitTypeDef erase; + uint32_t pageError = 0x0; + erase.TypeErase = FLASH_TYPEERASE_PAGES; + erase.PageAddress = FLASH_EEPROM_BASE; + erase.NbPages = 0x01; + flash_ok = HAL_FLASHEx_Erase(&erase, &pageError); + + flash_ok = HAL_ERROR; + while(flash_ok != HAL_OK) + {flash_ok = HAL_FLASH_Lock();} + + + flash_ok = HAL_ERROR; + while(flash_ok != HAL_OK) + {flash_ok = HAL_FLASH_Unlock();} + + flash_ok = HAL_ERROR; + while(flash_ok != HAL_OK) + { + for(int i=0; i<(lenght); i++) + { + flash_ok = HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, adr, *param); + param++; + adr += 0x2; + } + } + + flash_ok = HAL_ERROR; + while(flash_ok != HAL_OK) + {flash_ok = HAL_FLASH_Lock();} +} + +uint16_t watInTheFlash(uint32_t adress) +{ + return (*(uint32_t*) adress); +} + diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c new file mode 100644 index 0000000..f8c95e3 --- /dev/null +++ b/Core/Src/gpio.c @@ -0,0 +1,95 @@ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2025 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins + PA8 ------> RCC_MCO +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + +// INPUT C + GPIO_InitStruct.Pin = IN_06_Pin|Jselect_Pin|IN_05_Pin|J2_Pin|J3_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + +// OUTPUT C + GPIO_InitStruct.Pin = LED2_Pin|LED3_Pin|PVT4_Pin|PVT3_Pin|PVT2_Pin|PVT1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + +// INPUT A + GPIO_InitStruct.Pin = IN_04_Pin|IN_03_Pin|IN_02_Pin|IN_01_Pin|IN_14_Pin|IN_13_Pin|J0_Pin|J1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + +// INPUT B + GPIO_InitStruct.Pin = IN_12_Pin|IN_11_Pin|IN_10_Pin|IN_09_Pin|IN_08_Pin|IN_07_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +// OUTPUT B + GPIO_InitStruct.Pin = LED0_Pin|LED1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pin : PA8 */ + GPIO_InitStruct.Pin = GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure peripheral I/O remapping */ + __HAL_AFIO_REMAP_PD01_ENABLE(); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/lampa.c b/Core/Src/lampa.c new file mode 100644 index 0000000..e46cbc4 --- /dev/null +++ b/Core/Src/lampa.c @@ -0,0 +1,85 @@ + +#include "gpio.h" +#include "lampa.h" +#include "struc.h" +#include "message.h" +#include "package.h" + +void ReadEnteres(void) +{ + WORDE input; + + input.bit.bit0 = !IN_06; // ΠšΠΎΠ½Ρ‚Ρ€ΠΎΠ»ΡŒ ИП1 (ΠΏΠΈΡ‚Π°Π½ΠΈΠ΅ ΡƒΠΏΡ€Π°Π²Π»ΡΡŽΡ‰Π΅Π³ΠΎ ΠΊΠΎΠ½Ρ‚Ρ€ΠΎΠ»Π»Π΅Ρ€Π°) + input.bit.bit1 = !IN_05; // ΠšΠΎΠ½Ρ‚Ρ€ΠΎΠ»ΡŒ ИП2 (ΠΏΠΈΡ‚Π°Π½ΠΈΠ΅ ΠΏΠ΅Ρ€ΠΈΡ„Π΅Ρ€ΠΈΠΉΠ½Ρ‹Ρ… устройств) + input.bit.bit2 = !IN_04; // ΠšΠΎΠ½Ρ‚Ρ€ΠΎΠ»ΡŒ ИП3 (ΠΏΠΈΡ‚Π°Π½ΠΈΠ΅ эл. Π·Π°ΠΌΠΊΠΎΠ², Π»Π°ΠΌΠΏ освСщСния, УКБИ) + input.bit.bit3 = !IN_03; // ΠšΠΎΠ½Ρ‚Ρ€ΠΎΠ»ΡŒ ИП4 (ΠΏΠΈΡ‚Π°Π½ΠΈΠ΅ Π΄Π°Ρ‚Ρ‡ΠΈΠΊΠΎΠ² Ρ‚ΠΎΠΊΠ° ΠΈ напряТСния +) + input.bit.bit4 = !IN_02; // ΠšΠΎΠ½Ρ‚Ρ€ΠΎΠ»ΡŒ ИП5 (ΠΏΠΈΡ‚Π°Π½ΠΈΠ΅ Π΄Π°Ρ‚Ρ‡ΠΈΠΊΠΎΠ² Ρ‚ΠΎΠΊΠ° ΠΈ напряТСния –) + input.bit.bit5 = !IN_01; // ΠšΠΎΠ½Ρ‚Ρ€ΠΎΠ»ΡŒ ИП6 (ΠΏΠΈΡ‚Π°Π½ΠΈΠ΅ Π΄Ρ€Π°ΠΉΠ²Π΅Ρ€ΠΎΠ²) + + input.bit.bit6 = !IN_07; // ΠšΠΎΠ½Ρ‚Ρ€ΠΎΠ»ΡŒ 3Ρ… Ρ„Π°Π·Π½ΠΎΠ³ΠΎ 380 Π’ + input.bit.bit7 = !IN_08; // Заряд накопитСля + input.bit.bit8 = !IN_09; // Разряд накопитСля + input.bit.bit9 = IN_10; // Авария Π² сСти 24 Π’ + + input.bit.bitD = (Squazh_U[3] > Squazh_L[3]); + input.bit.bitC = (Squazh_U[2] > Squazh_L[2]); + input.bit.bitB = (Squazh_U[1] > Squazh_L[1]); + input.bit.bitA = (Squazh_U[0] > Squazh_L[0]); +/* + input.bit.bitA = !IN_11; // ΠšΠΎΠ½Ρ‚Ρ€ΠΎΠ»ΡŒ питания Π›Π‘Π£ + input.bit.bitB = !IN_12; // ΠšΠΎΠ½Ρ‚Ρ€ΠΎΠ»ΡŒ питания Π‘Π’Πž + input.bit.bitC = !IN_13; // Ρ€Π΅Π·Π΅Ρ€Π² + input.bit.bitD = !IN_14; // ΠšΠΎΠ½Ρ‚Ρ€ΠΎΠ»ΡŒ питания БКК +*/ + Inputs.all = input.all; + Alarms.all = ~Inputs.all & Alarm_mask.all; + Alarms.bit.bit7 = 0; // Заряд накопитСля + Alarms.bit.bit8 = Inputs.bit.bit8; // Разряд накопитСля + Alarms.bit.bit9 = Inputs.bit.bit9; // Авария Π² сСти 24 Π’ + Errors.all = ~Inputs.all & Error_mask.all; + Errors.bit.bit9 = Inputs.bit.bit9; // Авария Π² сСти 24 Π’ +} + +uint16_t ReadJumpers(void) +{ + WORDE input; + + input.all = 0; + + input.bit.bit0 = !J0; + input.bit.bit1 = !J1; + input.bit.bit2 = !J2; + input.bit.bit3 = !J3; + + return input.all; +} + +uint16_t TestJumper(void) +{ + return !Jselect; +} + +void ReadSeanus(void) +{ + static uint32_t cownt=0; + static uint32_t sum_u[4]={0,0,0,0}; +// static float flt_u[4]={0,0,0,0}; + uint8_t i; + + sum_u[0] += !IN_11; + sum_u[1] += !IN_12; + sum_u[2] += !IN_13; + sum_u[3] += !IN_14; + + if(++cownt>=10000) + { + cownt=0; + + for(i=0;i<4;i++) + { +// flt_u[i] +=((float)sum_u[i]-flt_u[i])/10+1; + Squazh_U[i]=sum_u[i]/100; + sum_u[i] = 0; +} } } + + diff --git a/Core/Src/main.c b/Core/Src/main.c new file mode 100644 index 0000000..7bbee1b --- /dev/null +++ b/Core/Src/main.c @@ -0,0 +1,416 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "can.h" +#include "tim.h" +#include "gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +#include "package.h" +#include "message.h" +#include "lampa.h" + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +static long Falling_asleep; +int CanGO=0; + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +int Isit(int num, int i) +{ + int res, pls; + + if((num<0)||(num>=0x80)) return 0; + res = Maska[0][num/0x10]; if(i) + res|= Maska[1][num/0x10]; + res &= (1<<(num&0x0F)); + pls = (espero[num]>CanRestart[i]/3); + pls = pls || county[num]; + res = res && pls; + + return res; +} + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + int i,j,n,mask,qua; + static int cancount[2]={1,2},cancell[2]={0,0},candid[2]={0,0}; + static unsigned int masca[8]; + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_CAN_Init(); + MX_TIM4_Init(); + /* USER CODE BEGIN 2 */ + + Mode = ReadJumpers(); + Setup_CAN_addr(Mode); + LastMode = Mode; + Load_params(); + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + if( CanGO) + { CanGO=0; + + for(i=0;i<0x80;i++) + if(espero[i]<30000) espero[i]++; + + for(i=0;i<2;i++) + if(cancount[i]) cancount[i]--; + } + + for(i=0;i<2;i++) + if( Cancount[i]) + if(!cancount[i]) + { + while(1) + { + if( cancell[i]>= 0x80) + { cancell[i]=0; + + if( candid[i]) + { candid[i]=0; + CanCycle[i]++; + cancount[i] = CanWait[i]; + continue; + } } + + mask = Maska[i][cancell[i]/0x10] >> (cancell[i]&0x0F); + if(!mask) cancell[i] = (cancell[i] + 0x10) & 0xFFF0 ; + else + { + while(!(mask & 1)) + { + cancell[i]++; mask >>= 1; + } + break; + } } + + + if(espero[cancell[i]]>CanRestart[i]) + county[cancell[i]]=1; + + if(modbus[cancell[i]] != archiv[cancell[i]]) + + county[cancell[i]] = (cancell[i]==keys) ? CanRepeat:1; + + if (county[cancell[i]]) + { + for(j= 3; j>0 && !Isit(cancell[i]+j,i); j--); + for(n=j-3; n<0 && !Isit(cancell[i]+n,i); n++); + + qua = 1 + j - n; + cancell[i]+= n; + + for(j=0;j= CANPOWSE) + { + CanPowse = 0; CanGO = 1; + } + + if(Alarms.bit.bit8) // Πΰηπδ αΰςΰπεθ + { + if (Falling_asleep) Falling_asleep--; + } + else Falling_asleep = 1000L * Sleep_time; + + if(work_diod) LED_2_ON; + else LED_2_OFF; + + if(norm_diod) LED_3_ON; + else LED_3_OFF; + + TST = TestJumper() | cTestLamp; + + if(++count_bright == 10) //maximum_bright + { count_bright = 0 ; + + if(power_lamp) Pvt1_ON; + else Pvt1_OFF; + } + + if(count_bright >= Brightness) + if(!TST) Pvt1_OFF; //ξςκλώχενθε λΰμοξχκθ + + if(TST & !preTest) + { + count_blink = BLINK_TIME; + count_mode = 0; + } + preTest = TST; + + if(++count_blink >= BLINK_TIME) + { + count_blink=0; + count_mode++; + blink_over = (count_mode & 1)?1:0; + blink_alarm = (count_mode & 7)?1:0; + } + + power_lamp= 1; + norm_diod= 1; + work_diod = 1; + + if(TST) + { + power_lamp= blink_over; + norm_diod= blink_over; + work_diod= !blink_over; + } + else + { + if(Alarms.all) + { + norm_diod= blink_alarm; + power_lamp=blink_alarm; + } + if(Errors.all) + { + power_lamp= blink_over; + norm_diod= blink_over; + } } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL10; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + Error_Handler(); + } + HAL_RCC_MCOConfig(RCC_MCO, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/message.c b/Core/Src/message.c new file mode 100644 index 0000000..2eb8bac --- /dev/null +++ b/Core/Src/message.c @@ -0,0 +1,132 @@ +#include "stm32f1xx_hal.h" + +#include "struc.h" +#include "crc16.h" +#include "package.h" +#include "message.h" +#include "eeprom.h" + +uint16_t params[Modbus_LEN+1], + modbus[Modbus_LEN], + archiv[Modbus_LEN], + county[Modbus_LEN], + espero[Modbus_LEN]; + +uint16_t Mode; + +LONGE* outputs; + +void Init_packMask(void); + +uint16_t Maska[2][8]; + +void Default_params() +{ + unsigned int i; + + for(i=0;i
© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_AFIO_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /** ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State + */ + __HAL_AFIO_REMAP_SWJ_ENABLE(); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/stm32f1xx_it.c b/Core/Src/stm32f1xx_it.c new file mode 100644 index 0000000..f9d60c9 --- /dev/null +++ b/Core/Src/stm32f1xx_it.c @@ -0,0 +1,248 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f1xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2022 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f1xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern CAN_HandleTypeDef hcan; +extern TIM_HandleTypeDef htim4; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M3 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + Millisecond(); + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F1xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f1xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles USB high priority or CAN TX interrupts. + */ +void USB_HP_CAN1_TX_IRQHandler(void) +{ + /* USER CODE BEGIN USB_HP_CAN1_TX_IRQn 0 */ + + /* USER CODE END USB_HP_CAN1_TX_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan); + /* USER CODE BEGIN USB_HP_CAN1_TX_IRQn 1 */ + + /* USER CODE END USB_HP_CAN1_TX_IRQn 1 */ +} + +/** + * @brief This function handles USB low priority or CAN RX0 interrupts. + */ +void USB_LP_CAN1_RX0_IRQHandler(void) +{ + /* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 0 */ + + /* USER CODE END USB_LP_CAN1_RX0_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan); + /* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 1 */ + + /* USER CODE END USB_LP_CAN1_RX0_IRQn 1 */ +} + +/** + * @brief This function handles TIM4 global interrupt. + */ +void TIM4_IRQHandler(void) +{ + /* USER CODE BEGIN TIM4_IRQn 0 */ + + /* USER CODE END TIM4_IRQn 0 */ + HAL_TIM_IRQHandler(&htim4); + /* USER CODE BEGIN TIM4_IRQn 1 */ + + /* USER CODE END TIM4_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/syscalls.c b/Core/Src/syscalls.c new file mode 100644 index 0000000..bc0dd6c --- /dev/null +++ b/Core/Src/syscalls.c @@ -0,0 +1,156 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + +return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _open(char *path, int flags, ...) +{ + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + return -1; +} + +int _stat(char *file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + errno = ENOMEM; + return -1; +} diff --git a/Core/Src/sysmem.c b/Core/Src/sysmem.c new file mode 100644 index 0000000..d7cc52c --- /dev/null +++ b/Core/Src/sysmem.c @@ -0,0 +1,80 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/Core/Src/system_stm32f1xx.c b/Core/Src/system_stm32f1xx.c new file mode 100644 index 0000000..bc96aae --- /dev/null +++ b/Core/Src/system_stm32f1xx.c @@ -0,0 +1,408 @@ +/** + ****************************************************************************** + * @file system_stm32f1xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f1xx_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on + * the product used), refer to "HSE_VALUE". + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f1xx_system + * @{ + */ + +/** @addtogroup STM32F1xx_System_Private_Includes + * @{ + */ + +#include "stm32f1xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Defines + * @{ + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/*!< Uncomment the following line if you need to use external SRAM */ +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +/** + * @} + */ + +/** @addtogroup STM32F1xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; +#endif /* STM32F105xC */ + +#if defined(STM32F100xB) || defined(STM32F100xE) + uint32_t prediv1factor = 0U; +#endif /* STM32F100xB or STM32F100xE */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00U: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04U: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08U: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#if !defined(STM32F105xC) && !defined(STM32F107xC) + pllmull = ( pllmull >> 18U) + 2U; + + if (pllsource == 0x00U) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; + } + else + { + #if defined(STM32F100xB) || defined(STM32F100xE) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18U; + + if (pllmull != 0x0DU) + { + pllmull += 2U; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13U / 2U; + } + + if (pllsource == 0x00U) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; + + if (prediv1source == 0U) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F105xC */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +/** + * @brief Setup the external memory controller. Called in startup_stm32f1xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f1xx_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmpreg; + /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114U; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0U; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); + + (void)(tmpreg); + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BBU; + GPIOD->CRH = 0xBBBBBBBBU; + + GPIOE->CRL = 0xB44444BBU; + GPIOE->CRH = 0xBBBBBBBBU; + + GPIOF->CRL = 0x44BBBBBBU; + GPIOF->CRH = 0xBBBB4444U; + + GPIOG->CRL = 0x44BBBBBBU; + GPIOG->CRH = 0x444B4B44U; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4U] = 0x00001091U; + FSMC_Bank1->BTCR[5U] = 0x00110212U; +} +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/tim.c b/Core/Src/tim.c new file mode 100644 index 0000000..9cd0c39 --- /dev/null +++ b/Core/Src/tim.c @@ -0,0 +1,129 @@ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2025 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +#include "lampa.h" + +/* USER CODE END 0 */ + +TIM_HandleTypeDef htim4; + +/* TIM4 init function */ +void MX_TIM4_Init(void) +{ + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + htim4.Init.Prescaler = 0; + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + htim4.Init.Period = 799; + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM4_Init 2 */ + + HAL_TIM_Base_MspInit(&htim4); + + HAL_TIM_Base_Start_IT(&htim4); + + /* USER CODE END TIM4_Init 2 */ + +} + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* TIM4 clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + + /* TIM4 interrupt Init */ + HAL_NVIC_SetPriority(TIM4_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TIM4_IRQn); + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspDeInit 0 */ + + /* USER CODE END TIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM4_CLK_DISABLE(); + + /* TIM4 interrupt Deinit */ + HAL_NVIC_DisableIRQ(TIM4_IRQn); + /* USER CODE BEGIN TIM4_MspDeInit 1 */ + + /* USER CODE END TIM4_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + + if(htim->Instance == TIM4) //check if the interrupt comes from TIM1 + + ReadSeanus(); + +} + + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Startup/startup_stm32f103rctx.s b/Core/Startup/startup_stm32f103rctx.s new file mode 100644 index 0000000..11d37f3 --- /dev/null +++ b/Core/Startup/startup_stm32f103rctx.s @@ -0,0 +1,468 @@ +/** + *************** (C) COPYRIGHT 2017 STMicroelectronics ************************ + * @file startup_stm32f103xe.s + * @author MCD Application Team + * @brief STM32F103xE Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Configure external SRAM mounted on STM3210E-EVAL board + * to be used as data memory (optional, to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h new file mode 100644 index 0000000..1001fd8 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h @@ -0,0 +1,11761 @@ +/** + ****************************************************************************** + * @file stm32f103xe.h + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F1xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f103xe + * @{ + */ + +#ifndef __STM32F103xE_H +#define __STM32F103xE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ + #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ + __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ + uint32_t RESERVED[16]; + __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ +} ADC_Common_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t DR4; + __IO uint32_t DR5; + __IO uint32_t DR6; + __IO uint32_t DR7; + __IO uint32_t DR8; + __IO uint32_t DR9; + __IO uint32_t DR10; + __IO uint32_t RTCCR; + __IO uint32_t CR; + __IO uint32_t CSR; + uint32_t RESERVED13[2]; + __IO uint32_t DR11; + __IO uint32_t DR12; + __IO uint32_t DR13; + __IO uint32_t DR14; + __IO uint32_t DR15; + __IO uint32_t DR16; + __IO uint32_t DR17; + __IO uint32_t DR18; + __IO uint32_t DR19; + __IO uint32_t DR20; + __IO uint32_t DR21; + __IO uint32_t DR22; + __IO uint32_t DR23; + __IO uint32_t DR24; + __IO uint32_t DR25; + __IO uint32_t DR26; + __IO uint32_t DR27; + __IO uint32_t DR28; + __IO uint32_t DR29; + __IO uint32_t DR30; + __IO uint32_t DR31; + __IO uint32_t DR32; + __IO uint32_t DR33; + __IO uint32_t DR34; + __IO uint32_t DR35; + __IO uint32_t DR36; + __IO uint32_t DR37; + __IO uint32_t DR38; + __IO uint32_t DR39; + __IO uint32_t DR40; + __IO uint32_t DR41; + __IO uint32_t DR42; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ + uint32_t RESERVED1; /*!< Reserved, 0x78 */ + uint32_t RESERVED2; /*!< Reserved, 0x7C */ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED3; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank2_3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; + __IO uint32_t SR4; + __IO uint32_t PMEM4; + __IO uint32_t PATT4; + __IO uint32_t PIO4; +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t OAR1; + __IO uint32_t OAR2; + __IO uint32_t DR; + __IO uint32_t SR1; + __IO uint32_t SR2; + __IO uint32_t CCR; + __IO uint32_t TRISE; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t CRH; + __IO uint32_t CRL; + __IO uint32_t PRLH; + __IO uint32_t PRLL; + __IO uint32_t DIVH; + __IO uint32_t DIVL; + __IO uint32_t CNTH; + __IO uint32_t CNTL; + __IO uint32_t ALRH; + __IO uint32_t ALRL; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SR; + __IO uint32_t DR; + __IO uint32_t CRCPR; + __IO uint32_t RXCRCR; + __IO uint32_t TXCRCR; + __IO uint32_t I2SCFGR; + __IO uint32_t I2SPR; +} SPI_TypeDef; + +/** + * @brief TIM Timers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +}TIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ +} USB_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0807FFFFUL /*!< FLASH END address of bank1 */ +#define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ + +#define FSMC_BASE 0x60000000UL /*!< FSMC base address */ +#define FSMC_R_BASE 0xA0000000UL /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) +#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) +#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00UL) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x00002000UL) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) +#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) +#define ADC3_BASE (APB2PERIPH_BASE + 0x00003C00UL) + +#define SDIO_BASE (PERIPH_BASE + 0x00018000UL) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) +#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */ +#define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ + + +#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */ +#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */ +#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */ +#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */ +#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */ + +#define FSMC_BANK2 (FSMC_BASE + 0x10000000UL) /*!< FSMC Bank2 base address */ +#define FSMC_BANK3 (FSMC_BASE + 0x20000000UL) /*!< FSMC Bank3 base address */ +#define FSMC_BANK4 (FSMC_BASE + 0x30000000UL) /*!< FSMC Bank4 base address */ + +#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000UL) /*!< FSMC Bank1 registers base address */ +#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104UL) /*!< FSMC Bank1E registers base address */ +#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x00000060UL) /*!< FSMC Bank2/Bank3 registers base address */ +#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x000000A0UL) /*!< FSMC Bank4 registers base address */ + +#define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ + +/* USB device FS */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ + + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM5 ((TIM_TypeDef *)TIM5_BASE) +#define TIM6 ((TIM_TypeDef *)TIM6_BASE) +#define TIM7 ((TIM_TypeDef *)TIM7_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define SPI3 ((SPI_TypeDef *)SPI3_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define UART4 ((USART_TypeDef *)UART4_BASE) +#define UART5 ((USART_TypeDef *)UART5_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define USB ((USB_TypeDef *)USB_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define DAC1 ((DAC_TypeDef *)DAC_BASE) +#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */ +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define ADC3 ((ADC_TypeDef *)ADC3_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define TIM8 ((TIM_TypeDef *)TIM8_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE) +#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) + + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS_Pos (0U) +#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ +#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ +#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ +#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ +#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ +#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ +#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ +#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ + +/* Legacy defines */ +#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 +#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 +#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 +#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 +#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 +#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 +#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 +#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 + +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_EWUP_Pos (8U) +#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D_Pos (0U) +#define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D_Pos (0U) +#define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D_Pos (0U) +#define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D_Pos (0U) +#define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D_Pos (0U) +#define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D_Pos (0U) +#define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D_Pos (0U) +#define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D_Pos (0U) +#define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D_Pos (0U) +#define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D_Pos (0U) +#define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D_Pos (0U) +#define BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D_Pos (0U) +#define BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D_Pos (0U) +#define BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D_Pos (0U) +#define BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D_Pos (0U) +#define BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D_Pos (0U) +#define BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D_Pos (0U) +#define BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D_Pos (0U) +#define BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D_Pos (0U) +#define BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D_Pos (0U) +#define BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D_Pos (0U) +#define BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D_Pos (0U) +#define BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D_Pos (0U) +#define BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D_Pos (0U) +#define BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D_Pos (0U) +#define BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D_Pos (0U) +#define BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D_Pos (0U) +#define BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D_Pos (0U) +#define BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D_Pos (0U) +#define BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D_Pos (0U) +#define BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D_Pos (0U) +#define BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D_Pos (0U) +#define BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D_Pos (0U) +#define BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D_Pos (0U) +#define BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D_Pos (0U) +#define BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D_Pos (0U) +#define BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D_Pos (0U) +#define BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D_Pos (0U) +#define BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D_Pos (0U) +#define BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D_Pos (0U) +#define BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D_Pos (0U) +#define BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D_Pos (0U) +#define BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */ + +#define RTC_BKP_NUMBER 42 + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL_Pos (0U) +#define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ +#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ +#define BKP_RTCCR_CCO_Pos (7U) +#define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ +#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE_Pos (8U) +#define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ +#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS_Pos (9U) +#define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ +#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE_Pos (0U) +#define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */ +#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ +#define BKP_CR_TPAL_Pos (1U) +#define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ +#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE_Pos (0U) +#define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ +#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ +#define BKP_CSR_CTI_Pos (1U) +#define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ +#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE_Pos (2U) +#define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ +#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF_Pos (8U) +#define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ +#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ +#define BKP_CSR_TIF_Pos (9U) +#define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ +#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY_Pos (1U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM_Pos (3U) +#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ +#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL_Pos (8U) +#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ +#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ + +#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ + +#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ + +#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ + +#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ + +#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE_Pos (14U) +#define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ +#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ + +#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE_Pos (17U) +#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ +#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL_Pos (18U) +#define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ + +#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */ +#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ + +#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ +#define RCC_CFGR_PLLMULL3_Pos (18U) +#define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ +#define RCC_CFGR_PLLMULL4_Pos (19U) +#define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ +#define RCC_CFGR_PLLMULL5_Pos (18U) +#define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ +#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ +#define RCC_CFGR_PLLMULL6_Pos (20U) +#define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ +#define RCC_CFGR_PLLMULL7_Pos (18U) +#define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ +#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ +#define RCC_CFGR_PLLMULL8_Pos (19U) +#define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ +#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ +#define RCC_CFGR_PLLMULL9_Pos (18U) +#define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ +#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ +#define RCC_CFGR_PLLMULL10_Pos (21U) +#define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ +#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ +#define RCC_CFGR_PLLMULL11_Pos (18U) +#define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ +#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ +#define RCC_CFGR_PLLMULL12_Pos (19U) +#define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ +#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ +#define RCC_CFGR_PLLMULL13_Pos (18U) +#define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ +#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ +#define RCC_CFGR_PLLMULL14_Pos (20U) +#define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ +#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ +#define RCC_CFGR_PLLMULL15_Pos (18U) +#define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ +#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ +#define RCC_CFGR_PLLMULL16_Pos (19U) +#define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ +#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ +#define RCC_CFGR_USBPRE_Pos (22U) +#define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ + +/*!< MCO configuration */ +#define RCC_CFGR_MCO_Pos (24U) +#define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ + +#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ +#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ +#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ + + /* Reference defines */ + #define RCC_CFGR_MCOSEL RCC_CFGR_MCO + #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 + #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 + #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 + #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK + #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK + #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI + #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE + #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF_Pos (0U) +#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF_Pos (1U) +#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF_Pos (2U) +#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF_Pos (3U) +#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF_Pos (4U) +#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF_Pos (7U) +#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ +#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE_Pos (8U) +#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE_Pos (9U) +#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ +#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE_Pos (10U) +#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ +#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE_Pos (11U) +#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ +#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE_Pos (12U) +#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ +#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC_Pos (16U) +#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ +#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC_Pos (17U) +#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ +#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC_Pos (18U) +#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ +#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC_Pos (19U) +#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ +#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC_Pos (20U) +#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ +#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC_Pos (23U) +#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ +#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ + + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST_Pos (0U) +#define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST_Pos (2U) +#define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST_Pos (3U) +#define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST_Pos (4U) +#define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST_Pos (5U) +#define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST_Pos (9U) +#define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ + +#define RCC_APB2RSTR_ADC2RST_Pos (10U) +#define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ + +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ + + +#define RCC_APB2RSTR_IOPERST_Pos (6U) +#define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ +#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ + +#define RCC_APB2RSTR_IOPFRST_Pos (7U) +#define RCC_APB2RSTR_IOPFRST_Msk (0x1UL << RCC_APB2RSTR_IOPFRST_Pos) /*!< 0x00000080 */ +#define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /*!< I/O port F reset */ +#define RCC_APB2RSTR_IOPGRST_Pos (8U) +#define RCC_APB2RSTR_IOPGRST_Msk (0x1UL << RCC_APB2RSTR_IOPGRST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /*!< I/O port G reset */ +#define RCC_APB2RSTR_TIM8RST_Pos (13U) +#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 Timer reset */ +#define RCC_APB2RSTR_ADC3RST_Pos (15U) +#define RCC_APB2RSTR_ADC3RST_Msk (0x1UL << RCC_APB2RSTR_ADC3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB2RSTR_ADC3RST RCC_APB2RSTR_ADC3RST_Msk /*!< ADC3 interface reset */ + + + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST_Pos (1U) +#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ + +#define RCC_APB1RSTR_CAN1RST_Pos (25U) +#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ + +#define RCC_APB1RSTR_BKPRST_Pos (27U) +#define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ + +#define RCC_APB1RSTR_TIM4RST_Pos (2U) +#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ +#define RCC_APB1RSTR_SPI2RST_Pos (14U) +#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ +#define RCC_APB1RSTR_USART3RST_Pos (18U) +#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ +#define RCC_APB1RSTR_I2C2RST_Pos (22U) +#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ + +#define RCC_APB1RSTR_USBRST_Pos (23U) +#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ + +#define RCC_APB1RSTR_TIM5RST_Pos (3U) +#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */ +#define RCC_APB1RSTR_TIM6RST_Pos (4U) +#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ +#define RCC_APB1RSTR_TIM7RST_Pos (5U) +#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ +#define RCC_APB1RSTR_SPI3RST_Pos (15U) +#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */ +#define RCC_APB1RSTR_UART4RST_Pos (19U) +#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */ +#define RCC_APB1RSTR_UART5RST_Pos (20U) +#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */ + + + + +#define RCC_APB1RSTR_DACRST_Pos (29U) +#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN_Pos (0U) +#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN_Pos (2U) +#define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN_Pos (4U) +#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ +#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN_Pos (6U) +#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ +#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ + +#define RCC_AHBENR_DMA2EN_Pos (1U) +#define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ + +#define RCC_AHBENR_FSMCEN_Pos (8U) +#define RCC_AHBENR_FSMCEN_Msk (0x1UL << RCC_AHBENR_FSMCEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */ +#define RCC_AHBENR_SDIOEN_Pos (10U) +#define RCC_AHBENR_SDIOEN_Msk (0x1UL << RCC_AHBENR_SDIOEN_Pos) /*!< 0x00000400 */ +#define RCC_AHBENR_SDIOEN RCC_AHBENR_SDIOEN_Msk /*!< SDIO clock enable */ + + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN_Pos (0U) +#define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN_Pos (2U) +#define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ +#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN_Pos (3U) +#define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ +#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN_Pos (4U) +#define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN_Pos (5U) +#define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN_Pos (9U) +#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ + +#define RCC_APB2ENR_ADC2EN_Pos (10U) +#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ +#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ + +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ + + +#define RCC_APB2ENR_IOPEEN_Pos (6U) +#define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ + +#define RCC_APB2ENR_IOPFEN_Pos (7U) +#define RCC_APB2ENR_IOPFEN_Msk (0x1UL << RCC_APB2ENR_IOPFEN_Pos) /*!< 0x00000080 */ +#define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /*!< I/O port F clock enable */ +#define RCC_APB2ENR_IOPGEN_Pos (8U) +#define RCC_APB2ENR_IOPGEN_Msk (0x1UL << RCC_APB2ENR_IOPGEN_Pos) /*!< 0x00000100 */ +#define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /*!< I/O port G clock enable */ +#define RCC_APB2ENR_TIM8EN_Pos (13U) +#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 Timer clock enable */ +#define RCC_APB2ENR_ADC3EN_Pos (15U) +#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk /*!< DMA1 clock enable */ + + + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN_Pos (1U) +#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ + +#define RCC_APB1ENR_CAN1EN_Pos (25U) +#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ + +#define RCC_APB1ENR_BKPEN_Pos (27U) +#define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ + +#define RCC_APB1ENR_TIM4EN_Pos (2U) +#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ +#define RCC_APB1ENR_SPI2EN_Pos (14U) +#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ +#define RCC_APB1ENR_USART3EN_Pos (18U) +#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ +#define RCC_APB1ENR_I2C2EN_Pos (22U) +#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ + +#define RCC_APB1ENR_USBEN_Pos (23U) +#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ + +#define RCC_APB1ENR_TIM5EN_Pos (3U) +#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */ +#define RCC_APB1ENR_TIM6EN_Pos (4U) +#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ +#define RCC_APB1ENR_TIM7EN_Pos (5U) +#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ +#define RCC_APB1ENR_SPI3EN_Pos (15U) +#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */ +#define RCC_APB1ENR_UART4EN_Pos (19U) +#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */ +#define RCC_APB1ENR_UART5EN_Pos (20U) +#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */ + + + + +#define RCC_APB1ENR_DACEN_Pos (29U) +#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ +#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_BDRST_Pos (16U) +#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF_Pos (24U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ + + + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE_Pos (0U) +#define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ +#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0_Pos (0U) +#define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ + +#define GPIO_CRL_MODE1_Pos (4U) +#define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ +#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ +#define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ + +#define GPIO_CRL_MODE2_Pos (8U) +#define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ +#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ +#define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ + +#define GPIO_CRL_MODE3_Pos (12U) +#define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ +#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ +#define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ + +#define GPIO_CRL_MODE4_Pos (16U) +#define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ +#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ +#define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ + +#define GPIO_CRL_MODE5_Pos (20U) +#define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ +#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ +#define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ + +#define GPIO_CRL_MODE6_Pos (24U) +#define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ +#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ +#define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ + +#define GPIO_CRL_MODE7_Pos (28U) +#define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ +#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ +#define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ + +#define GPIO_CRL_CNF_Pos (2U) +#define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0_Pos (2U) +#define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ +#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ +#define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ + +#define GPIO_CRL_CNF1_Pos (6U) +#define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ +#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ +#define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ + +#define GPIO_CRL_CNF2_Pos (10U) +#define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ +#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ +#define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ + +#define GPIO_CRL_CNF3_Pos (14U) +#define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ +#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ +#define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ + +#define GPIO_CRL_CNF4_Pos (18U) +#define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ +#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ +#define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ + +#define GPIO_CRL_CNF5_Pos (22U) +#define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ +#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ +#define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ + +#define GPIO_CRL_CNF6_Pos (26U) +#define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ +#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ +#define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ + +#define GPIO_CRL_CNF7_Pos (30U) +#define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ +#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ +#define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE_Pos (0U) +#define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ +#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8_Pos (0U) +#define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ +#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ +#define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ + +#define GPIO_CRH_MODE9_Pos (4U) +#define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ +#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ +#define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ + +#define GPIO_CRH_MODE10_Pos (8U) +#define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ +#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ +#define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ + +#define GPIO_CRH_MODE11_Pos (12U) +#define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ +#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ +#define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ + +#define GPIO_CRH_MODE12_Pos (16U) +#define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ +#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ +#define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ + +#define GPIO_CRH_MODE13_Pos (20U) +#define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ +#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ +#define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ + +#define GPIO_CRH_MODE14_Pos (24U) +#define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ +#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ +#define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ + +#define GPIO_CRH_MODE15_Pos (28U) +#define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ +#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ +#define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ + +#define GPIO_CRH_CNF_Pos (2U) +#define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8_Pos (2U) +#define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ +#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ +#define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ + +#define GPIO_CRH_CNF9_Pos (6U) +#define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ +#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ +#define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ + +#define GPIO_CRH_CNF10_Pos (10U) +#define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ +#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ +#define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ + +#define GPIO_CRH_CNF11_Pos (14U) +#define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ +#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ +#define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ + +#define GPIO_CRH_CNF12_Pos (18U) +#define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ +#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ +#define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ + +#define GPIO_CRH_CNF13_Pos (22U) +#define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ +#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ +#define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ + +#define GPIO_CRH_CNF14_Pos (26U) +#define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ +#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ +#define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ + +#define GPIO_CRH_CNF15_Pos (30U) +#define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ +#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ +#define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN_Pos (0U) +#define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ +#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ +#define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ +#define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ +#define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1_Pos (0U) +#define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ +#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2_Pos (1U) +#define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ +#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3_Pos (0U) +#define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ +#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4_Pos (2U) +#define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ +#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5_Pos (0U) +#define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ +#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6_Pos (1U) +#define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ +#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7_Pos (0U) +#define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ +#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8_Pos (3U) +#define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ +#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9_Pos (0U) +#define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ +#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10_Pos (1U) +#define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ +#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11_Pos (0U) +#define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ +#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12_Pos (2U) +#define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ +#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13_Pos (0U) +#define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ +#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14_Pos (1U) +#define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ +#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15_Pos (0U) +#define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ +#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT_Pos (4U) +#define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ +#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ +#define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ +#define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB_Pos (4U) +#define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC_Pos (5U) +#define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD_Pos (4U) +#define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE_Pos (6U) +#define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ + +#define AFIO_EVCR_EVOE_Pos (7U) +#define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ +#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP_Pos (0U) +#define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ +#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP_Pos (1U) +#define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ +#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP_Pos (2U) +#define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ +#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP_Pos (3U) +#define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ +#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ +#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ +#define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ +#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ +#define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ +#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ +#define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ +#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ +#define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP_Pos (12U) +#define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ +#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ +#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ +#define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) +#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP_Pos (15U) +#define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ +#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U) +#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */ +#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos (17U) +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk (0x1UL << AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos) /*!< 0x00020000 */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos (18U) +#define AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk (0x1UL << AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos) /*!< 0x00040000 */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos (19U) +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk (0x1UL << AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos) /*!< 0x00080000 */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos (20U) +#define AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk (0x1UL << AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos) /*!< 0x00100000 */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk /*!< ADC 2 External Trigger Regular Conversion remapping */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ +#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ +#define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ +#define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ + +#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) +#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ +#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0_Pos (0U) +#define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1_Pos (4U) +#define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2_Pos (8U) +#define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3_Pos (12U) +#define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) +#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) +#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) +#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) +#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4_Pos (0U) +#define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5_Pos (4U) +#define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6_Pos (8U) +#define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7_Pos (12U) +#define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) +#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) +#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) +#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) +#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8_Pos (0U) +#define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9_Pos (4U) +#define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10_Pos (8U) +#define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11_Pos (12U) +#define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) +#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) +#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) +#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) +#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12_Pos (0U) +#define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13_Pos (4U) +#define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14_Pos (8U) +#define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15_Pos (12U) +#define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) +#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) +#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) +#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) +#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ + +/****************** Bit definition for AFIO_MAPR2 register ******************/ + + +#define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U) +#define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1UL << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */ +#define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /*!< FSMC NADV remapping */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0_Pos (0U) +#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1_Pos (1U) +#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2_Pos (2U) +#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3_Pos (3U) +#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4_Pos (4U) +#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5_Pos (5U) +#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6_Pos (6U) +#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7_Pos (7U) +#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8_Pos (8U) +#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9_Pos (9U) +#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10_Pos (10U) +#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11_Pos (11U) +#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12_Pos (12U) +#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13_Pos (13U) +#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14_Pos (14U) +#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15_Pos (15U) +#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16_Pos (16U) +#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17_Pos (17U) +#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18_Pos (18U) +#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ + +/* References Defines */ +#define EXTI_IMR_IM0 EXTI_IMR_MR0 +#define EXTI_IMR_IM1 EXTI_IMR_MR1 +#define EXTI_IMR_IM2 EXTI_IMR_MR2 +#define EXTI_IMR_IM3 EXTI_IMR_MR3 +#define EXTI_IMR_IM4 EXTI_IMR_MR4 +#define EXTI_IMR_IM5 EXTI_IMR_MR5 +#define EXTI_IMR_IM6 EXTI_IMR_MR6 +#define EXTI_IMR_IM7 EXTI_IMR_MR7 +#define EXTI_IMR_IM8 EXTI_IMR_MR8 +#define EXTI_IMR_IM9 EXTI_IMR_MR9 +#define EXTI_IMR_IM10 EXTI_IMR_MR10 +#define EXTI_IMR_IM11 EXTI_IMR_MR11 +#define EXTI_IMR_IM12 EXTI_IMR_MR12 +#define EXTI_IMR_IM13 EXTI_IMR_MR13 +#define EXTI_IMR_IM14 EXTI_IMR_MR14 +#define EXTI_IMR_IM15 EXTI_IMR_MR15 +#define EXTI_IMR_IM16 EXTI_IMR_MR16 +#define EXTI_IMR_IM17 EXTI_IMR_MR17 +#define EXTI_IMR_IM18 EXTI_IMR_MR18 +#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0_Pos (0U) +#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1_Pos (1U) +#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2_Pos (2U) +#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3_Pos (3U) +#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4_Pos (4U) +#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5_Pos (5U) +#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6_Pos (6U) +#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7_Pos (7U) +#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8_Pos (8U) +#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9_Pos (9U) +#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10_Pos (10U) +#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11_Pos (11U) +#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12_Pos (12U) +#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13_Pos (13U) +#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14_Pos (14U) +#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15_Pos (15U) +#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16_Pos (16U) +#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17_Pos (17U) +#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18_Pos (18U) +#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ + +/* References Defines */ +#define EXTI_EMR_EM0 EXTI_EMR_MR0 +#define EXTI_EMR_EM1 EXTI_EMR_MR1 +#define EXTI_EMR_EM2 EXTI_EMR_MR2 +#define EXTI_EMR_EM3 EXTI_EMR_MR3 +#define EXTI_EMR_EM4 EXTI_EMR_MR4 +#define EXTI_EMR_EM5 EXTI_EMR_MR5 +#define EXTI_EMR_EM6 EXTI_EMR_MR6 +#define EXTI_EMR_EM7 EXTI_EMR_MR7 +#define EXTI_EMR_EM8 EXTI_EMR_MR8 +#define EXTI_EMR_EM9 EXTI_EMR_MR9 +#define EXTI_EMR_EM10 EXTI_EMR_MR10 +#define EXTI_EMR_EM11 EXTI_EMR_MR11 +#define EXTI_EMR_EM12 EXTI_EMR_MR12 +#define EXTI_EMR_EM13 EXTI_EMR_MR13 +#define EXTI_EMR_EM14 EXTI_EMR_MR14 +#define EXTI_EMR_EM15 EXTI_EMR_MR15 +#define EXTI_EMR_EM16 EXTI_EMR_MR16 +#define EXTI_EMR_EM17 EXTI_EMR_MR17 +#define EXTI_EMR_EM18 EXTI_EMR_MR18 + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0_Pos (0U) +#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1_Pos (1U) +#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2_Pos (2U) +#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3_Pos (3U) +#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4_Pos (4U) +#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5_Pos (5U) +#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6_Pos (6U) +#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7_Pos (7U) +#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8_Pos (8U) +#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9_Pos (9U) +#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10_Pos (10U) +#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11_Pos (11U) +#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12_Pos (12U) +#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13_Pos (13U) +#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14_Pos (14U) +#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15_Pos (15U) +#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16_Pos (16U) +#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17_Pos (17U) +#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18_Pos (18U) +#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ + +/* References Defines */ +#define EXTI_RTSR_RT0 EXTI_RTSR_TR0 +#define EXTI_RTSR_RT1 EXTI_RTSR_TR1 +#define EXTI_RTSR_RT2 EXTI_RTSR_TR2 +#define EXTI_RTSR_RT3 EXTI_RTSR_TR3 +#define EXTI_RTSR_RT4 EXTI_RTSR_TR4 +#define EXTI_RTSR_RT5 EXTI_RTSR_TR5 +#define EXTI_RTSR_RT6 EXTI_RTSR_TR6 +#define EXTI_RTSR_RT7 EXTI_RTSR_TR7 +#define EXTI_RTSR_RT8 EXTI_RTSR_TR8 +#define EXTI_RTSR_RT9 EXTI_RTSR_TR9 +#define EXTI_RTSR_RT10 EXTI_RTSR_TR10 +#define EXTI_RTSR_RT11 EXTI_RTSR_TR11 +#define EXTI_RTSR_RT12 EXTI_RTSR_TR12 +#define EXTI_RTSR_RT13 EXTI_RTSR_TR13 +#define EXTI_RTSR_RT14 EXTI_RTSR_TR14 +#define EXTI_RTSR_RT15 EXTI_RTSR_TR15 +#define EXTI_RTSR_RT16 EXTI_RTSR_TR16 +#define EXTI_RTSR_RT17 EXTI_RTSR_TR17 +#define EXTI_RTSR_RT18 EXTI_RTSR_TR18 + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0_Pos (0U) +#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1_Pos (1U) +#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2_Pos (2U) +#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3_Pos (3U) +#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4_Pos (4U) +#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5_Pos (5U) +#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6_Pos (6U) +#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7_Pos (7U) +#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8_Pos (8U) +#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9_Pos (9U) +#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10_Pos (10U) +#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11_Pos (11U) +#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12_Pos (12U) +#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13_Pos (13U) +#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14_Pos (14U) +#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15_Pos (15U) +#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16_Pos (16U) +#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17_Pos (17U) +#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18_Pos (18U) +#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ + +/* References Defines */ +#define EXTI_FTSR_FT0 EXTI_FTSR_TR0 +#define EXTI_FTSR_FT1 EXTI_FTSR_TR1 +#define EXTI_FTSR_FT2 EXTI_FTSR_TR2 +#define EXTI_FTSR_FT3 EXTI_FTSR_TR3 +#define EXTI_FTSR_FT4 EXTI_FTSR_TR4 +#define EXTI_FTSR_FT5 EXTI_FTSR_TR5 +#define EXTI_FTSR_FT6 EXTI_FTSR_TR6 +#define EXTI_FTSR_FT7 EXTI_FTSR_TR7 +#define EXTI_FTSR_FT8 EXTI_FTSR_TR8 +#define EXTI_FTSR_FT9 EXTI_FTSR_TR9 +#define EXTI_FTSR_FT10 EXTI_FTSR_TR10 +#define EXTI_FTSR_FT11 EXTI_FTSR_TR11 +#define EXTI_FTSR_FT12 EXTI_FTSR_TR12 +#define EXTI_FTSR_FT13 EXTI_FTSR_TR13 +#define EXTI_FTSR_FT14 EXTI_FTSR_TR14 +#define EXTI_FTSR_FT15 EXTI_FTSR_TR15 +#define EXTI_FTSR_FT16 EXTI_FTSR_TR16 +#define EXTI_FTSR_FT17 EXTI_FTSR_TR17 +#define EXTI_FTSR_FT18 EXTI_FTSR_TR18 + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0_Pos (0U) +#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1_Pos (1U) +#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2_Pos (2U) +#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3_Pos (3U) +#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4_Pos (4U) +#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5_Pos (5U) +#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6_Pos (6U) +#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7_Pos (7U) +#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8_Pos (8U) +#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9_Pos (9U) +#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10_Pos (10U) +#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11_Pos (11U) +#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12_Pos (12U) +#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13_Pos (13U) +#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14_Pos (14U) +#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15_Pos (15U) +#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16_Pos (16U) +#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17_Pos (17U) +#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18_Pos (18U) +#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ + +/* References Defines */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 +#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4_Pos (4U) +#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5_Pos (5U) +#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6_Pos (6U) +#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7_Pos (7U) +#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8_Pos (8U) +#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9_Pos (9U) +#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10_Pos (10U) +#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11_Pos (11U) +#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12_Pos (12U) +#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13_Pos (13U) +#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14_Pos (14U) +#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15_Pos (15U) +#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16_Pos (16U) +#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17_Pos (17U) +#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18_Pos (18U) +#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ +#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ + +/* References Defines */ +#define EXTI_PR_PIF0 EXTI_PR_PR0 +#define EXTI_PR_PIF1 EXTI_PR_PR1 +#define EXTI_PR_PIF2 EXTI_PR_PR2 +#define EXTI_PR_PIF3 EXTI_PR_PR3 +#define EXTI_PR_PIF4 EXTI_PR_PR4 +#define EXTI_PR_PIF5 EXTI_PR_PR5 +#define EXTI_PR_PIF6 EXTI_PR_PR6 +#define EXTI_PR_PIF7 EXTI_PR_PR7 +#define EXTI_PR_PIF8 EXTI_PR_PR8 +#define EXTI_PR_PIF9 EXTI_PR_PR9 +#define EXTI_PR_PIF10 EXTI_PR_PR10 +#define EXTI_PR_PIF11 EXTI_PR_PR11 +#define EXTI_PR_PIF12 EXTI_PR_PR12 +#define EXTI_PR_PIF13 EXTI_PR_PR13 +#define EXTI_PR_PIF14 EXTI_PR_PR14 +#define EXTI_PR_PIF15 EXTI_PR_PR15 +#define EXTI_PR_PIF16 EXTI_PR_PR16 +#define EXTI_PR_PIF17 EXTI_PR_PR17 +#define EXTI_PR_PIF18 EXTI_PR_PR18 + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register *******************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register ******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register *******************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register *******************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_SR_EOS_Pos (1U) +#define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */ +#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_SR_JEOS_Pos (2U) +#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ +#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_SR_JSTRT_Pos (3U) +#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ +#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ +#define ADC_SR_STRT_Pos (4U) +#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ +#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ + +/* Legacy defines */ +#define ADC_SR_EOC (ADC_SR_EOS) +#define ADC_SR_JEOC (ADC_SR_JEOS) + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH_Pos (0U) +#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ +#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ + +#define ADC_CR1_EOSIE_Pos (5U) +#define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ +#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_CR1_AWDIE_Pos (6U) +#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ +#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_CR1_JEOSIE_Pos (7U) +#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ +#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_CR1_SCAN_Pos (8U) +#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ +#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ +#define ADC_CR1_AWDSGL_Pos (9U) +#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ +#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CR1_JAUTO_Pos (10U) +#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ +#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ +#define ADC_CR1_DISCEN_Pos (11U) +#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ +#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CR1_JDISCEN_Pos (12U) +#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ +#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CR1_DISCNUM_Pos (13U) +#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ +#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ +#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ +#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ + +#define ADC_CR1_DUALMOD_Pos (16U) +#define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ +#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ +#define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ +#define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ +#define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ +#define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ + +#define ADC_CR1_JAWDEN_Pos (22U) +#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ +#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CR1_AWDEN_Pos (23U) +#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +/* Legacy defines */ +#define ADC_CR1_EOCIE (ADC_CR1_EOSIE) +#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON_Pos (0U) +#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ +#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ +#define ADC_CR2_CONT_Pos (1U) +#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ +#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CR2_CAL_Pos (2U) +#define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ +#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ +#define ADC_CR2_RSTCAL_Pos (3U) +#define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ +#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ +#define ADC_CR2_DMA_Pos (8U) +#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ +#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ +#define ADC_CR2_ALIGN_Pos (11U) +#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CR2_JEXTSEL_Pos (12U) +#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ +#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ +#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ +#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ + +#define ADC_CR2_JEXTTRIG_Pos (15U) +#define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ + +#define ADC_CR2_EXTSEL_Pos (17U) +#define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ +#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ +#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ +#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ + +#define ADC_CR2_EXTTRIG_Pos (20U) +#define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ +#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ +#define ADC_CR2_JSWSTART_Pos (21U) +#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ +#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR2_SWSTART_Pos (22U) +#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ +#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR2_TSVREFE_Pos (23U) +#define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ +#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10_Pos (0U) +#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP11_Pos (3U) +#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP12_Pos (6U) +#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP13_Pos (9U) +#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP14_Pos (12U) +#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP15_Pos (15U) +#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP16_Pos (18U) +#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP17_Pos (21U) +#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0_Pos (0U) +#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP1_Pos (3U) +#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP2_Pos (6U) +#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP3_Pos (9U) +#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP4_Pos (12U) +#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP5_Pos (15U) +#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP6_Pos (18U) +#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP7_Pos (21U) +#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP8_Pos (24U) +#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP9_Pos (27U) +#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1_Pos (0U) +#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2_Pos (0U) +#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3_Pos (0U) +#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4_Pos (0U) +#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13_Pos (0U) +#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ +#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ + +#define ADC_SQR1_SQ14_Pos (5U) +#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ +#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ +#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ + +#define ADC_SQR1_SQ15_Pos (10U) +#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ +#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ +#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ + +#define ADC_SQR1_SQ16_Pos (15U) +#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ +#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ +#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ + +#define ADC_SQR1_L_Pos (20U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7_Pos (0U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ8_Pos (5U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ + +#define ADC_SQR2_SQ9_Pos (10U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ + +#define ADC_SQR2_SQ10_Pos (15U) +#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ +#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ +#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ + +#define ADC_SQR2_SQ11_Pos (20U) +#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ +#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ +#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ + +#define ADC_SQR2_SQ12_Pos (25U) +#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ +#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1_Pos (0U) +#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ2_Pos (5U) +#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ +#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ + +#define ADC_SQR3_SQ3_Pos (10U) +#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ +#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ +#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ + +#define ADC_SQR3_SQ4_Pos (15U) +#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ +#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ +#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ + +#define ADC_SQR3_SQ5_Pos (20U) +#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ +#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ +#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ + +#define ADC_SQR3_SQ6_Pos (25U) +#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ +#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1_Pos (0U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ + +#define ADC_JSQR_JSQ2_Pos (5U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ + +#define ADC_JSQR_JSQ3_Pos (10U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ + +#define ADC_JSQR_JSQ4_Pos (15U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JL_Pos (20U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_ADC2DATA_Pos (16U) +#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ +#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1_Pos (1U) +#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ +#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1_Pos (2U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1_Pos (3U) +#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ + +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ + +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ + +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2_Pos (17U) +#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ +#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2_Pos (18U) +#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ +#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2_Pos (19U) +#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ +#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ +#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ +#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ + +#define DAC_CR_WAVE2_Pos (22U) +#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ +#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ +#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ + +#define DAC_CR_MAMP2_Pos (24U) +#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ +#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ +#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ +#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ +#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ + +#define DAC_CR_DMAEN2_Pos (28U) +#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ +#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ + + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2_Pos (1U) +#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ +#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR_Pos (4U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR_Pos (0U) +#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR_Pos (4U) +#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR_Pos (0U) +#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR_Pos (0U) +#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR_Pos (16U) +#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR_Pos (4U) +#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR_Pos (20U) +#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR_Pos (0U) +#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR_Pos (8U) +#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR_Pos (0U) +#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ + + + +/*****************************************************************************/ +/* */ +/* Timers (TIM) */ +/* */ +/*****************************************************************************/ +/******************* Bit definition for TIM_CR1 register *******************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f1xx + * @{ + */ + +#ifndef __STM32F1XX_H +#define __STM32F1XX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F1) +#define STM32F1 +#endif /* STM32F1 */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ + !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ + !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) + /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ + /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ + /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ + /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ + /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ + /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ + /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ + /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ + /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ + /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ + /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ + /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ + /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ + /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V4.3.2 + */ +#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ +#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F1_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F100xB) + #include "stm32f100xb.h" +#elif defined(STM32F100xE) + #include "stm32f100xe.h" +#elif defined(STM32F101x6) + #include "stm32f101x6.h" +#elif defined(STM32F101xB) + #include "stm32f101xb.h" +#elif defined(STM32F101xE) + #include "stm32f101xe.h" +#elif defined(STM32F101xG) + #include "stm32f101xg.h" +#elif defined(STM32F102x6) + #include "stm32f102x6.h" +#elif defined(STM32F102xB) + #include "stm32f102xb.h" +#elif defined(STM32F103x6) + #include "stm32f103x6.h" +#elif defined(STM32F103xB) + #include "stm32f103xb.h" +#elif defined(STM32F103xE) + #include "stm32f103xe.h" +#elif defined(STM32F103xG) + #include "stm32f103xg.h" +#elif defined(STM32F105xC) + #include "stm32f105xc.h" +#elif defined(STM32F107xC) + #include "stm32f107xc.h" +#else + #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0U, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f1xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F1xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h new file mode 100644 index 0000000..187fdde --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h @@ -0,0 +1,98 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.h + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/License.md b/Drivers/CMSIS/Device/ST/STM32F1xx/License.md new file mode 100644 index 0000000..72fbf79 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32F1xx/License.md @@ -0,0 +1,83 @@ +Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..162a400 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..94212eb --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..2d9db15 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..11c4af0 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..660f612 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..251e4ed --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..3a3148e --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2927 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..f929bba --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..424011a --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1083 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..0ed678e --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 23. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..acbc5df --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1993 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..74bff64 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1941 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..6cd2db7 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3002 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..7d56873 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..a14dc62 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..9b67c92 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..3e8a471 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..0142203 --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..62571da --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Drivers/CMSIS/LICENSE.txt b/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 0000000..8dada3e --- /dev/null +++ b/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the events that can be selected to configure the + * set/reset crossbar of a timer output + */ +#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) +#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) +#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) +#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) +#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) +#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) +#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) +#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) +#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) + +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) + +/** @brief Constants defining the event filtering applied to external events + * by a timer + */ +#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) + #define I2S_IT_TXE I2S_IT_TXP + #define I2S_IT_RXNE I2S_IT_RXP + + #define I2S_FLAG_TXE I2S_FLAG_TXP + #define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + + #define SPI_FLAG_TXE SPI_FLAG_TXP + #define SPI_FLAG_RXNE SPI_FLAG_RXP + + #define SPI_IT_TXE SPI_IT_TXP + #define SPI_IT_RXNE SPI_IT_RXP + + #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET + #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET + #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET + #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) + #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h new file mode 100644 index 0000000..35092c0 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h @@ -0,0 +1,358 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_H +#define __STM32F1xx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_conf.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode + * @brief Freeze/Unfreeze Peripherals in Debug mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @{ + */ + +/* Peripherals on APB1 */ +/** + * @brief TIM2 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) + +/** + * @brief TIM3 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) + +#if defined (DBGMCU_CR_DBG_TIM4_STOP) +/** + * @brief TIM4 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM5_STOP) +/** + * @brief TIM5 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM6_STOP) +/** + * @brief TIM6 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM7_STOP) +/** + * @brief TIM7 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM12_STOP) +/** + * @brief TIM12 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM13_STOP) +/** + * @brief TIM13 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM14_STOP) +/** + * @brief TIM14 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) +#endif + +/** + * @brief WWDG Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) + +/** + * @brief IWDG Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) + +/** + * @brief I2C1 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) + +#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) +/** + * @brief I2C2 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) +#endif + +#if defined (DBGMCU_CR_DBG_CAN1_STOP) +/** + * @brief CAN1 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) +#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_CAN2_STOP) +/** + * @brief CAN2 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) +#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) +#endif + +/* Peripherals on APB2 */ +#if defined (DBGMCU_CR_DBG_TIM1_STOP) +/** + * @brief TIM1 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM8_STOP) +/** + * @brief TIM8 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM9_STOP) +/** + * @brief TIM9 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM10_STOP) +/** + * @brief TIM10 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM11_STOP) +/** + * @brief TIM11 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) +#endif + + +#if defined (DBGMCU_CR_DBG_TIM15_STOP) +/** + * @brief TIM15 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM16_STOP) +/** + * @brief TIM16 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM17_STOP) +/** + * @brief TIM17 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) +#endif + +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions + * @{ + */ +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h new file mode 100644 index 0000000..3777cae --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h @@ -0,0 +1,850 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_can.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_CAN_H +#define STM32F1xx_HAL_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#if defined (CAN1) +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ + +} HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + For single CAN instance(14 dedicated filter banks), + this parameter must be a number between Min_Data = 0 and Max_Data = 13. + For dual CAN instances(28 filter banks shared), + this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be a value of @ref CAN_filter_activation */ + + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + For single CAN instances, this parameter is meaningless. + For dual CAN instances, all filter banks with lower index are assigned to master + CAN instance, whereas all filter banks with greater index are assigned to slave + CAN instance. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ + +} CAN_FilterTypeDef; + +/** + * @brief CAN Tx message header structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_TxHeaderTypeDef; + +/** + * @brief CAN Rx message header structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ + + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + +} CAN_RxHeaderTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct __CAN_HandleTypeDef +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */ + void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */ + void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */ + void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */ + void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */ + void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */ + void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */ + void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */ + void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */ + void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */ + void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */ + void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */ + void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */ + + void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */ + void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */ + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +} CAN_HandleTypeDef; + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL CAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */ + HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */ + HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */ + HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */ + HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */ + HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */ + HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */ + HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */ + HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */ + HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */ + HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */ + HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */ + HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */ + + HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */ + HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */ + +} HAL_CAN_CallbackIDTypeDef; + +/** + * @brief HAL CAN Callback pointer definition + */ +typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */ + +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ + +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN InitStatus + * @{ + */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width + * @{ + */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 + * @{ + */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 + * @{ + */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_activation CAN Filter Activation + * @{ + */ +#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ +#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_identifier_type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number + * @{ + */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ +/** + * @} + */ + +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes + * @{ + */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ + +/* Error Flags */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ +/** + * @} + */ + + +/** @defgroup CAN_Interrupts CAN Interrupts + * @{ + */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macros CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. + * @retval None + */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_CAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) +#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */ + +/** + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)); +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ + +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ + +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CAN_Private_Types CAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_FLAG_MASK (0x000000FFU) +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#if defined(CAN2) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#endif +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ + ((ACTIVATION) == CAN_FILTER_ENABLE)) +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + + +#endif /* CAN1 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_CAN_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h new file mode 100644 index 0000000..a365b02 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h @@ -0,0 +1,410 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_CORTEX_H +#define __STM32F1xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk +#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) + +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1U) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h new file mode 100644 index 0000000..155c017 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h @@ -0,0 +1,210 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_DEF +#define __STM32F1xx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) + +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) +/* Reserved for future use */ +#error "USE_RTOS should be 0 in the current HAL release" +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif +#ifndef __packed +#define __packed __attribute__((packed)) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#if defined (__CC_ARM) /* ARM Compiler V5*/ +#define __ALIGN_BEGIN __align(4) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F1xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h new file mode 100644 index 0000000..9a407f4 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h @@ -0,0 +1,457 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_DMA_H +#define __STM32F1xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ + +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ + +} DMA_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ + +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ +#define DMA_FLAG_GL1 0x00000001U +#define DMA_FLAG_TC1 0x00000002U +#define DMA_FLAG_HT1 0x00000004U +#define DMA_FLAG_TE1 0x00000008U +#define DMA_FLAG_GL2 0x00000010U +#define DMA_FLAG_TC2 0x00000020U +#define DMA_FLAG_HT2 0x00000040U +#define DMA_FLAG_TE2 0x00000080U +#define DMA_FLAG_GL3 0x00000100U +#define DMA_FLAG_TC3 0x00000200U +#define DMA_FLAG_HT3 0x00000400U +#define DMA_FLAG_TE3 0x00000800U +#define DMA_FLAG_GL4 0x00001000U +#define DMA_FLAG_TC4 0x00002000U +#define DMA_FLAG_HT4 0x00004000U +#define DMA_FLAG_TE4 0x00008000U +#define DMA_FLAG_GL5 0x00010000U +#define DMA_FLAG_TC5 0x00020000U +#define DMA_FLAG_HT5 0x00040000U +#define DMA_FLAG_TE5 0x00080000U +#define DMA_FLAG_GL6 0x00100000U +#define DMA_FLAG_TC6 0x00200000U +#define DMA_FLAG_HT6 0x00400000U +#define DMA_FLAG_TE6 0x00800000U +#define DMA_FLAG_GL7 0x01000000U +#define DMA_FLAG_TC7 0x02000000U +#define DMA_FLAG_HT7 0x04000000U +#define DMA_FLAG_TE7 0x08000000U +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) + + +/* Interrupt & Flag management */ + +/** + * @brief Enables the specified DMA Channel interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Channel interrupt is enabled or not. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Return the number of remaining data units in the current DMA Channel transfer. + * @param __HANDLE__: DMA handle + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32f1xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h new file mode 100644 index 0000000..2de1a2d --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h @@ -0,0 +1,277 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_DMA_EX_H +#define __STM32F1xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros + * @{ + */ +/* Interrupt & Flag management */ +#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \ + defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices + * @{ + */ + +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ + (DMA1->ISR & (__FLAG__))) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ + (DMA1->IFCR = (__FLAG__))) + +/** + * @} + */ + +#else +/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices + * @{ + */ + +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) + +/** + * @brief Return the current DMA Channel half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) + +/** + * @brief Return the current DMA Channel transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + DMA_FLAG_GL7) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GLx: Global interrupt flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GLx: Global interrupt flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +/** + * @} + */ + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */ + /* STM32F103xG || STM32F105xC || STM32F107xC */ + +#endif /* __STM32F1xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h new file mode 100644 index 0000000..af1f732 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h @@ -0,0 +1,320 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_EXTI_H +#define STM32F1xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ + +/** + * @brief HAL EXTI common Callback ID enumeration definition + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#if defined(EXTI_IMR_IM18) +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */ +#endif /* EXTI_IMR_IM18 */ +#if defined(EXTI_IMR_IM19) +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#endif /* EXTI_IMR_IM19 */ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#if defined (GPIOE) +#define EXTI_GPIOE 0x00000004u +#endif /* GPIOE */ +#if defined (GPIOF) +#define EXTI_GPIOF 0x00000005u +#endif /* GPIOF */ +#if defined (GPIOG) +#define EXTI_GPIOG 0x00000006u +#endif /* GPIOG */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR_IM19) +#define EXTI_LINE_NB 20UL +#elif defined(EXTI_IMR_IM18) +#define EXTI_LINE_NB 19UL +#else /* EXTI_IMR_IM17 */ +#define EXTI_LINE_NB 18UL +#endif /* EXTI_IMR_IM19 */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) + +#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) + +#if defined (GPIOG) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG)) +#elif defined (GPIOF) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF)) +#elif defined (GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD)) +#endif /* GPIOG */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h new file mode 100644 index 0000000..52e480b --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h @@ -0,0 +1,328 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of Flash HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_FLASH_H +#define __STM32F1xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) + +#if defined(FLASH_ACR_LATENCY) +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1) || \ + ((__LATENCY__) == FLASH_LATENCY_2)) + +#else +#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) +#endif /* FLASH_ACR_LATENCY */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_PAGEERASE = 1U, + FLASH_PROC_MASSERASE = 2U, + FLASH_PROC_PROGRAMHALFWORD = 3U, + FLASH_PROC_PROGRAMWORD = 4U, + FLASH_PROC_PROGRAMDOUBLEWORD = 5U +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ + + __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ + + __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ + + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + __IO uint32_t ErrorCode; /*!< FLASH error code + This parameter can be a value of @ref FLASH_Error_Codes */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Codes FLASH Error Codes + * @{ + */ + +#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ +#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ +#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ + +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA) + +/** + * @brief Disable the FLASH half cycle access. + * @note half cycle access can only be used with a low-frequency clock of less than + 8 MHz that can be obtained with the use of HSI or HSE but not of PLL. + * @retval None + */ +#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) + +/** + * @} + */ + +#if defined(FLASH_ACR_LATENCY) +/** @defgroup FLASH_EM_Latency FLASH Latency + * @brief macros to handle FLASH Latency + * @{ + */ + +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval None + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) + + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @} + */ + +#endif /* FLASH_ACR_LATENCY */ +/** @defgroup FLASH_Prefetch FLASH Prefetch + * @brief macros to handle FLASH Prefetch buffer + * @{ + */ +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32f1xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); + +/* FLASH IRQ handler function */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +void HAL_FLASH_OB_Launch(void); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_FLASH_GetError(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private function -------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +#if defined(FLASH_BANK2_END) +HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); +#endif /* FLASH_BANK2_END */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h new file mode 100644 index 0000000..0a5b24a --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h @@ -0,0 +1,786 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of Flash HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_FLASH_EX_H +#define __STM32F1xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ + +#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U +#define OBR_REG_INDEX 1U +#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP)) + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) + +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#if defined(FLASH_BANK2_END) +#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) +#endif /* FLASH_BANK2_END */ + +/* Low Density */ +#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU)) +#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ + +/* Medium Density */ +#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU)))) +#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ + +/* High Density */ +#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU))) +#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ + +/* XL Density */ +#if defined(FLASH_BANK2_END) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU)) +#endif /* FLASH_BANK2_END */ + +/* Connectivity Line */ +#if (defined(STM32F105xC) || defined(STM32F107xC)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU))) +#endif /* STM32F105xC || STM32F107xC */ + +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) + +#if defined(FLASH_BANK2_END) +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#else +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) +#endif /* FLASH_BANK2_END */ + +/* Low Density */ +#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU))) + +#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ + +/* Medium Density */ +#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \ + ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ + ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) + +#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ + +/* High Density */ +#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \ + ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) + +#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ + +/* XL Density */ +#if defined(FLASH_BANK2_END) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \ + ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU))) + +#endif /* FLASH_BANK2_END */ + +/* Connectivity Line */ +#if (defined(STM32F105xC) || defined(STM32F107xC)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ + ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) + +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled + This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END + (x = 1 or 2 depending on devices)*/ + + uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. + This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Options bytes program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASHEx_OB_Type */ + + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_OB_WRP_State */ + + uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected + This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ + + uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. + This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ + +#if defined(FLASH_BANK2_END) + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + IWDG / STOP / STDBY / BOOT1 + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */ +#else + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + IWDG / STOP / STDBY + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + @ref FLASHEx_OB_nRST_STDBY */ +#endif /* FLASH_BANK2_END */ + + uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed + This parameter can be a value of @ref FLASHEx_OB_Data_Address */ + + uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ +} FLASH_OBProgramInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Constants FLASH Constants + * @{ + */ + +/** @defgroup FLASHEx_Page_Size Page Size + * @{ + */ +#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) +#define FLASH_PAGE_SIZE 0x400U +#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ + /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ + +#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) +#define FLASH_PAGE_SIZE 0x800U +#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ + /* STM32F101xG || STM32F103xG */ + /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Type_Erase Type Erase + * @{ + */ +#define FLASH_TYPEERASE_PAGES 0x00U /*!CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ + /* Enable Bank2 IT */ \ + SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ + } while(0U) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 + * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 + * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 + * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ + /* Disable Bank1 IT */ \ + CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ + /* Disable Bank2 IT */ \ + CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ + } while(0U) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 + * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 + * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 + * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 + * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 + * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 + * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 + * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ + (FLASH->OBR & FLASH_OBR_OPTERR) : \ + ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \ + (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \ + (FLASH->SR2 & ((__FLAG__) >> 16U)))) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 + * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 + * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 + * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 + * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 + * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 + * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 + * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ + /* Clear FLASH_FLAG_OPTVERR flag */ \ + if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ + { \ + CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ + } \ + else { \ + /* Clear Flag in Bank1 */ \ + if (((__FLAG__) & SR_FLAG_MASK) != RESET) \ + { \ + FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \ + } \ + /* Clear Flag in Bank2 */ \ + if (((__FLAG__) >> 16U) != RESET) \ + { \ + FLASH->SR2 = ((__FLAG__) >> 16U); \ + } \ + } \ + } while(0U) +#else +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_BSY FLASH Busy flag + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ + (FLASH->OBR & FLASH_OBR_OPTERR) : \ + (FLASH->SR & (__FLAG__))) +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ + /* Clear FLASH_FLAG_OPTVERR flag */ \ + if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ + { \ + CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ + } \ + else { \ + /* Clear Flag in Bank1 */ \ + FLASH->SR = (__FLAG__); \ + } \ + } while(0U) + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); + +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_FLASH_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h new file mode 100644 index 0000000..a344f8f --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h @@ -0,0 +1,308 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_GPIO_H +#define STM32F1xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0u, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +#define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ + +#define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */ + +/** + * @} + */ + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ + +/** + * @} + */ + +/** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32f1xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \ + ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h new file mode 100644 index 0000000..5f6c3fd --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h @@ -0,0 +1,894 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_GPIO_EX_H +#define STM32F1xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration + * @brief This section propose definition to use the Cortex EVENTOUT signal. + * @{ + */ + +/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin + * @{ + */ + +#define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ +#define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ +#define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ +#define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ +#define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ +#define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ +#define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ +#define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ +#define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ +#define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ +#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ +#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ +#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ +#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ +#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ +#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ + +#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_15)) +/** + * @} + */ + +/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port + * @{ + */ + +#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ +#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ +#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ +#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ +#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ + +#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \ + ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \ + ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \ + ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \ + ((__PORT__) == AFIO_EVENTOUT_PORT_E)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping + * @brief This section propose definition to remap the alternate function to some other port/pins. + * @{ + */ + +/** + * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. + * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) + * @retval None + */ +#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP) + +/** + * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. + * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) + * @retval None + */ +#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP) + +/** + * @brief Enable the remapping of I2C1 alternate function SCL and SDA. + * @note ENABLE: Remap (SCL/PB8, SDA/PB9) + * @retval None + */ +#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP) + +/** + * @brief Disable the remapping of I2C1 alternate function SCL and SDA. + * @note DISABLE: No remap (SCL/PB6, SDA/PB7) + * @retval None + */ +#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP) + +/** + * @brief Enable the remapping of USART1 alternate function TX and RX. + * @note ENABLE: Remap (TX/PB6, RX/PB7) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP) + +/** + * @brief Disable the remapping of USART1 alternate function TX and RX. + * @note DISABLE: No remap (TX/PA9, RX/PA10) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP) + +/** + * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. + * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP) + +/** + * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. + * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP) + +/** + * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. + * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. + * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) + +/** + * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. + * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) + * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) + * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) + +/** + * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) + * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP) + +/** + * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 + * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) + * @note TIM3_ETR on PE0 is not re-mapped. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 + * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) + * @note TIM3_ETR on PE0 is not re-mapped. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) + +/** + * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 + * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) + * @note TIM3_ETR on PE0 is not re-mapped. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. + * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) + * @note TIM4_ETR on PE0 is not re-mapped. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP) + +/** + * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. + * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) + * @note TIM4_ETR on PE0 is not re-mapped. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP) + +#if defined(AFIO_MAPR_CAN_REMAP_REMAP1) + +/** + * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. + * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 + * @retval None + */ +#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP) + +/** + * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. + * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) + * @retval None + */ +#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP) + +/** + * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. + * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 + * @retval None + */ +#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP) + +#endif + +/** + * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used + * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and + * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available + * on 100-pin and 144-pin packages, no need for remapping). + * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. + * @retval None + */ +#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP) + +/** + * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used + * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and + * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available + * on 100-pin and 144-pin packages, no need for remapping). + * @note DISABLE: No remapping of PD0 and PD1 + * @retval None + */ +#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP) + +#if defined(AFIO_MAPR_TIM5CH4_IREMAP) +/** + * @brief Enable the remapping of TIM5CH4. + * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. + * @note This function is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP) + +/** + * @brief Disable the remapping of TIM5CH4. + * @note DISABLE: TIM5_CH4 is connected to PA3 + * @note This function is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP) +#endif + +#if defined(AFIO_MAPR_ETH_REMAP) +/** + * @brief Enable the remapping of Ethernet MAC connections with the PHY. + * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP) + +/** + * @brief Disable the remapping of Ethernet MAC connections with the PHY. + * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP) +#endif + +#if defined(AFIO_MAPR_CAN2_REMAP) + +/** + * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. + * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP) + +/** + * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. + * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP) +#endif + +#if defined(AFIO_MAPR_MII_RMII_SEL) +/** + * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. + * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL) + +/** + * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. + * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL) +#endif + +/** + * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). + * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) + +/** + * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). + * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) + +/** + * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). + * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) + +/** + * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). + * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) + +#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) + +/** + * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). + * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) + +/** + * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). + * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) +#endif + +#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) + +/** + * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) + +/** + * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) +#endif + +/** + * @brief Enable the Serial wire JTAG configuration + * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State + * @retval None + */ +#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET) + +/** + * @brief Enable the Serial wire JTAG configuration + * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST + * @retval None + */ +#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST) + +/** + * @brief Enable the Serial wire JTAG configuration + * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled + * @retval None + */ + +#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE) + +/** + * @brief Disable the Serial wire JTAG configuration + * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled + * @retval None + */ +#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE) + +#if defined(AFIO_MAPR_SPI3_REMAP) + +/** + * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. + * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP) + +/** + * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. + * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP) +#endif + +#if defined(AFIO_MAPR_TIM2ITR1_IREMAP) + +/** + * @brief Control of TIM2_ITR1 internal mapping. + * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP) + +/** + * @brief Control of TIM2_ITR1 internal mapping. + * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP) +#endif + +#if defined(AFIO_MAPR_PTP_PPS_REMAP) + +/** + * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @note ENABLE: PTP_PPS is output on PB5 pin. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP) + +/** + * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @note DISABLE: PTP_PPS not output on PB5 pin. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM9_REMAP) + +/** + * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. + * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) + +/** + * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. + * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM10_REMAP) + +/** + * @brief Enable the remapping of TIM10_CH1. + * @note ENABLE: Remap (TIM10_CH1 on PF6). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) + +/** + * @brief Disable the remapping of TIM10_CH1. + * @note DISABLE: No remap (TIM10_CH1 on PB8). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM11_REMAP) +/** + * @brief Enable the remapping of TIM11_CH1. + * @note ENABLE: Remap (TIM11_CH1 on PF7). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) + +/** + * @brief Disable the remapping of TIM11_CH1. + * @note DISABLE: No remap (TIM11_CH1 on PB9). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM13_REMAP) + +/** + * @brief Enable the remapping of TIM13_CH1. + * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) + +/** + * @brief Disable the remapping of TIM13_CH1. + * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM14_REMAP) + +/** + * @brief Enable the remapping of TIM14_CH1. + * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) + +/** + * @brief Disable the remapping of TIM14_CH1. + * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) +#endif + +#if defined(AFIO_MAPR2_FSMC_NADV_REMAP) + +/** + * @brief Controls the use of the optional FSMC_NADV signal. + * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. + * @retval None + */ +#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) + +/** + * @brief Controls the use of the optional FSMC_NADV signal. + * @note CONNECTED: The NADV signal is connected to the output (default). + * @retval None + */ +#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM15_REMAP) + +/** + * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. + * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) + +/** + * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. + * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM16_REMAP) + +/** + * @brief Enable the remapping of TIM16_CH1. + * @note ENABLE: Remap (TIM16_CH1 on PA6). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) + +/** + * @brief Disable the remapping of TIM16_CH1. + * @note DISABLE: No remap (TIM16_CH1 on PB8). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM17_REMAP) + +/** + * @brief Enable the remapping of TIM17_CH1. + * @note ENABLE: Remap (TIM17_CH1 on PA7). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) + +/** + * @brief Disable the remapping of TIM17_CH1. + * @note DISABLE: No remap (TIM17_CH1 on PB9). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) +#endif + +#if defined(AFIO_MAPR2_CEC_REMAP) + +/** + * @brief Enable the remapping of CEC. + * @note ENABLE: Remap (CEC on PB10). + * @retval None + */ +#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) + +/** + * @brief Disable the remapping of CEC. + * @note DISABLE: No remap (CEC on PB8). + * @retval None + */ +#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM1_DMA_REMAP) + +/** + * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. + * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) + +/** + * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. + * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) + +/** + * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. + * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) + +/** + * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. + * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM12_REMAP) + +/** + * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. + * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). + * @note This bit is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) + +/** + * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. + * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). + * @note This bit is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) +#endif + +#if defined(AFIO_MAPR2_MISC_REMAP) + +/** + * @brief Miscellaneous features remapping. + * This bit is set and cleared by software. It controls miscellaneous features. + * The DMA2 channel 5 interrupt position in the vector table. + * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). + * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is + * selected as DAC Trigger 3, TIM15 triggers TIM1/3. + * @note This bit is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) + +/** + * @brief Miscellaneous features remapping. + * This bit is set and cleared by software. It controls miscellaneous features. + * The DMA2 channel 5 interrupt position in the vector table. + * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). + * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO + * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. + * @note This bit is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros + * @{ + */ +#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :3uL) +#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :4uL) +#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL :\ + ((__GPIOx__) == (GPIOF))? 5uL :6uL) +#endif + +#define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ + tmpreg |= AFIO_MAPR_SWJ_CFG; \ + tmpreg |= REMAP_PIN; \ + AFIO->MAPR = tmpreg; \ + }while(0u) + +#define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ + tmpreg |= AFIO_MAPR_SWJ_CFG; \ + tmpreg &= ~REMAP_PIN; \ + AFIO->MAPR = tmpreg; \ + }while(0u) + +#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \ + tmpreg &= ~REMAP_PIN_MASK; \ + tmpreg |= AFIO_MAPR_SWJ_CFG; \ + tmpreg |= REMAP_PIN; \ + AFIO->MAPR = tmpreg; \ + }while(0u) + +#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \ + tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \ + tmpreg |= DBGAFR_SWJCFG; \ + AFIO->MAPR = tmpreg; \ + }while(0u) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GPIOEx_Exported_Functions + * @{ + */ + +/** @addtogroup GPIOEx_Exported_Functions_Group1 + * @{ + */ +void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource); +void HAL_GPIOEx_EnableEventout(void); +void HAL_GPIOEx_DisableEventout(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h new file mode 100644 index 0000000..9696c00 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h @@ -0,0 +1,388 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_PWR_H +#define __STM32F1xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + + +/** + * @} + */ + + +/* Internal constants --------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Constants + * @{ + */ + +#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 + +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ + +/** + * @} + */ + + +/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins + * @{ + */ + +#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP + +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON 0x00000000U +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS + +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) + +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) + +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) + +/** + * @brief Enable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +/* #define HAL_PWR_ConfigPVD 12*/ +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + + + +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F1xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h new file mode 100644 index 0000000..782e33a --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h @@ -0,0 +1,1378 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_RCC_H +#define __STM32F1xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< PLLState: The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ +} RCC_PLLInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ + +#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ + +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U +#define RCC_OSCILLATORTYPE_HSE 0x00000001U +#define RCC_OSCILLATORTYPE_HSI 0x00000002U +#define RCC_OSCILLATORTYPE_LSE 0x00000004U +#define RCC_OSCILLATORTYPE_LSI 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ + +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ + +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ + +/** + * @} + */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ +#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ +#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ +/** + * @} + */ + + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 0x00000000U +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ + +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 0x00000000U + +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ +#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR register + * - 011: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) +#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) +#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) +#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) +#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) +#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) +#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_BKP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) + +#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) +#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_AFIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) +#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) + +#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) + +#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) + +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) + +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) + +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) +#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ + (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) + +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macro to enable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + */ +#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) + +/** @brief Macro to disable the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) + +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON turn ON the HSE oscillator + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if ((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if ((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macro to enable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) + +/** @brief Macro to disable the main PLL. + * @note The main PLL can not be disabled if it is used as system clock source + */ +#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) + +/** @brief Macro to configure the main PLL clock source and multiplication factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 + * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 + @if STM32F105xC + * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 + @elseif STM32F107xC + * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 + @else + * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 + * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 + * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 + * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 + * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 + * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 + * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 + * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 + * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 + @endif + * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 + * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) + +/** @brief Get oscillator clock selected as PLL input clock + * @retval The clock source used for PLL entry. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) + +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) + +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +#if defined(RCC_CFGR_MCO_3) +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source + */ +#else +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source + */ +#endif + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) + + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration +* @{ +*/ + +/** @brief Macro to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** @brief Macro to enable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) + +/** @brief Macro to disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) + +/** @brief Macro to force the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) + +/** @brief Macros to release the Backup domain reset. + */ +#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + * @arg @ref RCC_IT_CSS Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + * @arg @ref RCC_IT_CSS Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. + @if STM32F105xx + * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. + * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. + @elsif STM32F107xx + * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. + * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. + @endif + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. + * @arg @ref RCC_FLAG_PINRST Pin reset. + * @arg @ref RCC_FLAG_PORRST POR/PDR reset. + * @arg @ref RCC_FLAG_SFTRST Software reset. + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. + * @arg @ref RCC_FLAG_LPWRRST Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ + ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ + RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32f1xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); + +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/** @defgroup RCC_Timeout RCC Timeout + * @{ + */ + +/* Disable Backup domain write protection state change timeout */ +#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ +/* LSE state change timeout */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ + +/** + * @} + */ + +/** @defgroup RCC_Register_Offset Register offsets + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00U +#define RCC_CFGR_OFFSET 0x04U +#define RCC_CIR_OFFSET 0x08U +#define RCC_BDCR_OFFSET 0x20U +#define RCC_CSR_OFFSET 0x24U + +/** + * @} + */ + +/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) +#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) +#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) +#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) +#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) + +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos +#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) +/* Alias word address of HSEON bit */ +#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos +#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) +/* Alias word address of CSSON bit */ +#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos +#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) +/* Alias word address of PLLON bit */ +#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos +#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos +#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) + +/* Alias word address of RMVF bit */ +#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos +#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) + +/* --- BDCR Registers ---*/ +/* Alias word address of LSEON bit */ +#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos +#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) + +/* Alias word address of LSEON bit */ +#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos +#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) + +/* Alias word address of RTCEN bit */ +#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos +#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) + +/* Alias word address of BDRST bit */ +#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos +#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) + +/** + * @} + */ + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) + +/* Defines used for Flags */ +#define CR_REG_INDEX ((uint8_t)1) +#define BDCR_REG_INDEX ((uint8_t)2) +#define CSR_REG_INDEX ((uint8_t)3) + +#define RCC_FLAG_MASK ((uint8_t)0x1F) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +/** + * @} + */ + +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) + +#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) +#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h new file mode 100644 index 0000000..822ca9b --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h @@ -0,0 +1,1908 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_RCC_EX_H +#define __STM32F1xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/** @addtogroup RCCEx_Private_Constants + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + +/* Alias word address of PLLI2SON bit */ +#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos +#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) +/* Alias word address of PLL2ON bit */ +#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos +#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) + +#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ +#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ + +#endif /* STM32F105xC || STM32F107xC */ + + +#define CR_REG_INDEX ((uint8_t)1) + +/** + * @} + */ + +/** @addtogroup RCCEx_Private_Macros + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \ + ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) + +#else +#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ + ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ + ((__MUL__) == RCC_PLL_MUL6_5)) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) + +#else +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ + ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ + ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ + ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ + ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ + ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ + ((__MUL__) == RCC_PLL_MUL16)) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) + +#endif /* STM32F105xC || STM32F107xC*/ + +#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \ + ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) + +#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) + +#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) + +#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \ + ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \ + ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \ + ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \ + ((__MUL__) == RCC_PLLI2S_MUL20)) + +#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) + +#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \ + ((__PLL__) == RCC_PLL2_ON)) + +#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \ + ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \ + ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \ + ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \ + ((__MUL__) == RCC_PLL2_MUL20)) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + +#elif defined(STM32F103xE) || defined(STM32F103xG) + +#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) + +#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + + +#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + +#else + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) + +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + +#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** + * @brief RCC PLL2 configuration structure definition + */ +typedef struct +{ + uint32_t PLL2State; /*!< The new state of the PLL2. + This parameter can be a value of @ref RCCEx_PLL2_Config */ + + uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock + This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. + This parameter can be a value of @ref RCCEx_Prediv2_Factor */ + +#endif /* STM32F105xC || STM32F107xC */ +} RCC_PLL2InitTypeDef; + +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t Prediv1Source; /*!< The Prediv1 source value. + This parameter can be a value of @ref RCCEx_Prediv1_Source */ +#endif /* STM32F105xC || STM32F107xC */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) + This parameter can be a value of @ref RCCEx_Prediv1_Factor */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ +#endif /* STM32F105xC || STM32F107xC */ +} RCC_OscInitTypeDef; + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** + * @brief RCC PLLI2S configuration structure definition + */ +typedef struct +{ + uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock + This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. + This parameter can be a value of @ref RCCEx_Prediv2_Factor */ + +#endif /* STM32F105xC || STM32F107xC */ +} RCC_PLLI2SInitTypeDef; +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< specifies the RTC clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t AdcClockSelection; /*!< ADC clock source + This parameter can be a value of @ref RCCEx_ADC_Prescaler */ + +#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) + uint32_t I2s2ClockSelection; /*!< I2S2 clock source + This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ + + uint32_t I2s3ClockSelection; /*!< I2S3 clock source + This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters + This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ + +#endif /* STM32F105xC || STM32F107xC */ +#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Prescaler */ + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +} RCC_PeriphCLKInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_RTC 0x00000001U +#define RCC_PERIPHCLK_ADC 0x00000002U +#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_PERIPHCLK_I2S2 0x00000004U +#define RCC_PERIPHCLK_I2S3 0x00000008U +#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_PERIPHCLK_USB 0x00000010U +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler + * @{ + */ +#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 +#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 +#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 +#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 + +/** + * @} + */ + +#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source + * @{ + */ +#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source + * @{ + */ +#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + +/** @defgroup RCCEx_USB_Prescaler USB Prescaler + * @{ + */ +#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE +#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U + +/** + * @} + */ + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_USB_Prescaler USB Prescaler + * @{ + */ +#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE +#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U + +/** + * @} + */ + +/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor + * @{ + */ + +#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ +#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ +#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ +#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ +#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ +#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ +#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ +#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ +#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Prediv1_Source Prediv1 Source + * @{ + */ + +#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE +#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor + * @{ + */ + +#define RCC_HSE_PREDIV_DIV1 0x00000000U + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 +#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 +#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 +#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 +#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 +#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 +#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 +#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 +#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 +#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 +#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 +#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 +#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 +#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 +#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 +#else +#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor + * @{ + */ + +#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ +#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ +#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ +#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ +#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ +#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ +#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ +#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ +#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ +#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ +#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ +#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ +#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ +#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ +#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ +#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ + +/** + * @} + */ + +/** @defgroup RCCEx_PLL2_Config PLL Config + * @{ + */ +#define RCC_PLL2_NONE 0x00000000U +#define RCC_PLL2_OFF 0x00000001U +#define RCC_PLL2_ON 0x00000002U + +/** + * @} + */ + +/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor + * @{ + */ + +#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ +#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ +#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ +#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ +#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ +#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ +#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ +#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ +#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ + +/** + * @} + */ + +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#else +#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 +#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 +#endif /* STM32F105xC || STM32F107xC */ +#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 +#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 +#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 +#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 +#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 +#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 +#else +#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 +#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 +#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 +#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 +#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 +#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 +#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) +#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) +#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) +#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) +#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) +#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) +#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) +#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) +#endif /* STM32F105xC || STM32F107xC*/ +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Interrupt RCCEx Interrupt + * @{ + */ +#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) +#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) +/** + * @} + */ + +/** @defgroup RCCEx_Flag RCCEx Flag + * Elements values convention: 0XXYYYYYb + * - YYYYY : Flag position in the register + * - XX : Register index + * - 01: CR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC*/ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ + || defined (STM32F100xE) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined (STM32F100xE) +#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ + +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) + + +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ + UNUSED(tmpreg); \ + } while(0U) + + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) +#endif /* STM32F105xC || STM32F107xC*/ + +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) + +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0U) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0U) + +#endif /* STM32F107xC*/ + +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ + || defined (STM32F100xE) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined (STM32F100xE) +#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) +#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) +#endif /* STM32F103xE || STM32F103xG */ +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) +#endif /* STM32F105xC || STM32F107xC*/ +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) +#endif /* STM32F107xC*/ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ + || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined (STM32F100xE) +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#endif /* STM32F100xB || STM32F100xE */ + +#ifdef STM32F100xE +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#endif /* STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#endif /* STM32F101xG || STM32F103xG*/ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ + || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) +#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ +#if defined(STM32F100xB) || defined (STM32F100xE) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) +#endif /* STM32F100xB || STM32F100xE */ +#ifdef STM32F100xE +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#endif /* STM32F100xE */ +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#endif /* STM32F105xC || STM32F107xC */ +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#endif /* STM32F101xG || STM32F103xG*/ + +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ + || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ + || defined(STM32F103xG) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xB) || defined(STM32F100xE) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) +#endif /* STM32F100xB || STM32F100xE */ + +#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ + || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ + || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) +#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ + +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xE) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) +#endif /* STM32F100xE */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +#endif /* STM32F101xG || STM32F103xG */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ + || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ + || defined(STM32F103xG) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ +#if defined(STM32F100xB) || defined(STM32F100xE) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) +#endif /* STM32F100xB || STM32F100xE */ +#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ + || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ + || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) +#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#endif /* STM32F103xE || STM32F103xG */ +#if defined(STM32F100xE) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) +#endif /* STM32F100xE */ +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +#endif /* STM32F101xG || STM32F103xG */ + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) +#endif /* STM32F107xC */ + +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) +#endif /* STM32F107xC */ + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ + +#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) + +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ + || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) + +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) +#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined (STM32F100xE) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#endif /* STM32F100xB || STM32F100xE */ + +#if defined (STM32F100xE) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) + +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#endif /* STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) + +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) + +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#endif /* STM32F101xG || STM32F103xG */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ + +#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ + || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ + || defined(STM32F103xG) +#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) + +#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) +#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xB) || defined(STM32F100xE) +#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) +#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) + +#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) +#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) +#endif /* STM32F100xB || STM32F100xE */ + +#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ + || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ + || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) + +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) +#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) + +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ + +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) + +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xE) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) + +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) +#endif /* STM32F100xE */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) + +#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +#endif /* STM32F101xG || STM32F103xG*/ + +/** + * @} + */ + +/** @defgroup RCCEx_HSE_Configuration HSE Configuration + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +/** + * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. + * @note Predivision factor can not be changed if PLL is used as system clock + * In this case, you have to select another source of the system clock, disable the PLL and + * then change the HSE predivision factor. + * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. + * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. + */ +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) +#else +/** + * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. + * @note Predivision factor can not be changed if PLL is used as system clock + * In this case, you have to select another source of the system clock, disable the PLL and + * then change the HSE predivision factor. + * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. + * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. + */ +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ + MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) + +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +/** + * @brief Macro to get prediv1 factor for PLL. + */ +#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) + +#else +/** + * @brief Macro to get prediv1 factor for PLL. + */ +#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) + +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration + * @{ + */ + +/** @brief Macros to enable the main PLLI2S. + * @note After enabling the main PLLI2S, the application software should wait on + * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can + * be used as system clock source. + * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) + +/** @brief Macros to disable the main PLLI2S. + * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) + +/** @brief macros to configure the main PLLI2S multiplication factor. + * @note This function must be used only when the main PLLI2S is disabled. + * + * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 + * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 + * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 + * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 + * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 + * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 + * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 + * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 + * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 + * + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) + +/** + * @} + */ + +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration + * @brief Macros to configure clock source of different peripherals. + * @{ + */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +/** @brief Macro to configure the USB clock. + * @param __USBCLKSOURCE__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) + +/** @brief Macro to get the USB clock (USBCLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + +/** @brief Macro to configure the USB OTSclock. + * @param __USBCLKSOURCE__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) + +/** @brief Macro to get the USB clock (USBCLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) + +#endif /* STM32F105xC || STM32F107xC */ + +/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). + * @param __ADCCLKSOURCE__ specifies the ADC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock + */ +#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) + +/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + +/** @addtogroup RCCEx_HSE_Configuration + * @{ + */ + +/** + * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. + * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock + * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and + * then change the PREDIV2 factor. + * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. + * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. + */ +#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) + +/** + * @brief Macro to get prediv2 factor for PLL2 & PLL3. + */ +#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) + +/** + * @} + */ + +/** @addtogroup RCCEx_PLLI2S_Configuration + * @{ + */ + +/** @brief Macros to enable the main PLL2. + * @note After enabling the main PLL2, the application software should wait on + * PLL2RDY flag to be set indicating that PLL2 clock is stable and can + * be used as system clock source. + * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE) + +/** @brief Macros to disable the main PLL2. + * @note The main PLL2 can not be disabled if it is used indirectly as system clock source + * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE) + +/** @brief macros to configure the main PLL2 multiplication factor. + * @note This function must be used only when the main PLL2 is disabled. + * + * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 + * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 + * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 + * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 + * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 + * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 + * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 + * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 + * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 + * + */ +#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) + +/** + * @} + */ + +/** @defgroup RCCEx_I2S_Configuration I2S Configuration + * @brief Macros to configure clock source of I2S peripherals. + * @{ + */ + +/** @brief Macro to configure the I2S2 clock. + * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) + +/** @brief Macro to get the I2S2 clock (I2S2CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) + +/** @brief Macro to configure the I2S3 clock. + * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) + +/** @brief Macro to get the I2S3 clock (I2S3CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) + +/** + * @} + */ + +#endif /* STM32F105xC || STM32F107xC */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); + +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); +HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h new file mode 100644 index 0000000..632976a --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h @@ -0,0 +1,2123 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_TIM_H +#define STM32F1xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t BreakFilter; /*!< Specifies the break input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event + (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__HANDLE__)->Instance->CCR4)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + (__HANDLE__)->ChannelState[3]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32f1xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h new file mode 100644 index 0000000..1979d73 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h @@ -0,0 +1,262 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_TIM_EX_H +#define STM32F1xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F1xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/License.md b/Drivers/STM32F1xx_HAL_Driver/License.md new file mode 100644 index 0000000..017be72 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/License.md @@ -0,0 +1,3 @@ +# Copyright (c) 2016 STMicroelectronics + +This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause). \ No newline at end of file diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c new file mode 100644 index 0000000..cd0fdea --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c @@ -0,0 +1,606 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @brief STM32F1xx HAL Driver version number V1.1.7 + */ +#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32F1xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */ +#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\ + |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32F1xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK 0x00000FFFU + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) de-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configure the Flash prefetch. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0) +#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \ + defined(STM32F102x6) || defined(STM32F102xB) || \ + defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ + defined(STM32F105xC) || defined(STM32F107xC) + + /* Prefetch buffer is not available on value line devices */ + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + +#if defined(STM32F105xC) || defined(STM32F107xC) + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); +#endif + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Returns the HAL revision + * @retval version 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F1xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Returns the device identifier. + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * Note: On all STM32F1 devices: + * If the system tick timer interrupt is enabled during the Stop mode + * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup + * the system from Stop mode. + * Workaround: To debug the Stop mode, disable the system tick timer + * interrupt. + * Refer to errata sheet of these devices for more details. + * Note: On all STM32F1 devices: + * If the system tick timer interrupt is enabled during the Stop mode + * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup + * the system from Stop mode. + * Workaround: To debug the Stop mode, disable the system tick timer + * interrupt. + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c new file mode 100644 index 0000000..5134348 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c @@ -0,0 +1,2436 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_can.c + * @author MCD Application Team + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function open-drain + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be trigged by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + + By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + example @ref HAL_CAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit() + or @ref HAL_CAN_Init() function. + + When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#if defined(CAN1) + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Reset callbacks to legacy functions */ + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ + hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ + hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hcan->MspInitCallback == NULL) + { + hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hcan->MspInitCallback(hcan); + } + +#else + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspInit(hcan); + } +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) +{ + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Stop the CAN module */ + (void)HAL_CAN_Stop(hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->MspDeInitCallback == NULL) + { + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: CLOCK, NVIC */ + hcan->MspDeInitCallback(hcan); + +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspDeInit(hcan); +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a CAN CallBack. + * To be used instead of the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = pCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = pCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = pCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = pCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a CAN CallBack. + * CAN callabck is redirected to the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = HAL_CAN_SleepCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = HAL_CAN_ErrorCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) +{ + uint32_t filternbrbitpos; + CAN_TypeDef *can_ip = hcan->Instance; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + +#if defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); +#else + /* CAN1 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + +#if defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + +#endif + /* Convert filter number into bit position */ + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + +@endverbatim + * @{ + */ + +/** + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_READY) + { + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_LISTENING) + { + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + uint32_t timeout = 1000000U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do + { + /* Increment counter */ + count++; + + /* Check if timeout is reached */ + if (count > timeout) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + status = 1U; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) +{ + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + uint32_t tsr = READ_REG(hcan->Instance->TSR); + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((tsr & CAN_TSR_TME0) != 0U) || + ((tsr & CAN_TSR_TME1) != 0U) || + ((tsr & CAN_TSR_TME2) != 0U)) + { + /* Select an empty transmit mailbox */ + transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Check transmit mailbox value */ + if (transmitmailbox > 2U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; + + return HAL_ERROR; + } + + /* Store the Tx mailbox */ + *pTxMailbox = (uint32_t)1 << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) + { + freelevel++; + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } + } + + /* Return status */ + return status; +} + +/** + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. + */ +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +{ + uint32_t timestamp = 0U; + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != 0U) + { + /* Transmission Mailbox 0 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != 0U) + { + /* Transmission Mailbox 1 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != 0U) + { + /* Transmission Mailbox 2 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) + { + if ((rf0rflags & CAN_RF0R_FULL0) != 0U) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) + { + /* Receive FIFO 0 mesage pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) + { + if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) + { + if ((rf1rflags & CAN_RF1R_FULL1) != 0U) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) + { + /* Receive FIFO 1 mesage pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) + { + if ((msrflags & CAN_MSR_SLAKI) != 0U) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->SleepCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != 0U) + { + if ((msrflags & CAN_MSR_WKUI) != 0U) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->WakeUpFromRxMsgCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != 0U) + { + if ((msrflags & CAN_MSR_ERRI) != 0U) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + ((esrflags & CAN_ESR_EWGF) != 0U)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + ((esrflags & CAN_ESR_EPVF) != 0U)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + ((esrflags & CAN_ESR_BOFF) != 0U)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + ((esrflags & CAN_ESR_LEC) != 0U)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + } + + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) + { + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Call Error callback function */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->ErrorCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_ErrorCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + else + { + /* Neither sleep mode request nor sleep mode acknowledge */ + } + } + + /* Return CAN state */ + return state; +} + +/** + * @brief Return the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +{ + /* Return CAN error code */ + return hcan->ErrorCode; +} + +/** + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Reset CAN error code */ + hcan->ErrorCode = 0U; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + status = HAL_ERROR; + } + + /* Return the status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CAN_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* CAN1 */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c new file mode 100644 index 0000000..e66ccee --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c @@ -0,0 +1,505 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M3 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value 0x0F. + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f1xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup: The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h)) + * @param PreemptPriority: The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority: the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00U; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0U; +} + +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != RESET) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00U; + MPU->RASR = 0x00U; + } +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @param PriorityGroup: the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c new file mode 100644 index 0000000..62a1d28 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c @@ -0,0 +1,899 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to the Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Channel, program the required configuration through the following parameters: + Channel request, Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode + using HAL_DMA_Init() function. + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e. a member of DMA handle structure). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + + /* Check the DMA handle allocation */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + +#if defined (DMA2) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->DmaBaseAddress = DMA2; + } +#else + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; +#endif /* DMA2 */ + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR)); + + /* Prepare the DMA Channel configuration */ + tmp |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* Write to DMA Channel CR register */ + hdma->Instance->CCR = tmp; + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + + /* Reset DMA Channel Number of Data to Transfer register */ + hdma->Instance->CNDTR = 0U; + + /* Reset DMA Channel peripheral address register */ + hdma->Instance->CPAR = 0U; + + /* Reset DMA Channel memory address register */ + hdma->Instance->CMAR = 0U; + +#if defined (DMA2) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->DmaBaseAddress = DMA2; + } +#else + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; +#endif /* DMA2 */ + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief Input and Output operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if(NULL != hdma->XferHalfCpltCallback) + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + } + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + } + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel: Specifies the DMA level complete. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart = 0U; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); + } + else + { + /* Half Transfer Complete flag */ + temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) + { + if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management **************************************/ + else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + return; +} + +/** + * @brief Register callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID: User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback: pointer to private callbacsk function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID: User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the DMA hande state. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + /* Return DMA handle state */ + return hdma->State; +} + +/** + * @brief Return the DMA error code. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c new file mode 100644 index 0000000..33c130a --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c @@ -0,0 +1,559 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + EXTI->RTSR |= maskline; + } + else + { + EXTI->RTSR &= ~maskline; + } + + /* Configure falling trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + EXTI->FTSR |= maskline; + } + else + { + EXTI->FTSR &= ~maskline; + } + + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = AFIO->EXTICR[linepos >> 2u]; + regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + AFIO->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + EXTI->IMR |= maskline; + } + else + { + EXTI->IMR &= ~maskline; + } + + /* Configure event mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + EXTI->EMR |= maskline; + } + else + { + EXTI->EMR &= ~maskline; + } + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + + /* Check if selected line is enable */ + if ((EXTI->IMR & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + /* Check if selected line is enable */ + if ((EXTI->EMR & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + /* Check if configuration of selected line is enable */ + if ((EXTI->RTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + /* Check if configuration of selected line is enable */ + if ((EXTI->FTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = AFIO->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = ((regval << (AFIO_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + } + else + { + pExtiConfig->GPIOSel = 0x00u; + } + } + else + { + /* No Trigger selected */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + EXTI->IMR = (EXTI->IMR & ~maskline); + + /* 2] Clear event mode */ + EXTI->EMR = (EXTI->EMR & ~maskline); + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + EXTI->RTSR = (EXTI->RTSR & ~maskline); + EXTI->FTSR = (EXTI->FTSR & ~maskline); + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = AFIO->EXTICR[linepos >> 2u]; + regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + AFIO->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t maskline; + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regval = (EXTI->PR & maskline); + if (regval != 0x00u) + { + /* Clear pending bit */ + EXTI->PR = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t regval; + uint32_t maskline; + uint32_t linepos; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* return 1 if bit is set else 0 */ + regval = ((EXTI->PR & maskline) >> linepos); + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Clear Pending bit */ + EXTI->PR = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Generate Software interrupt */ + EXTI->SWIER = maskline; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c new file mode 100644 index 0000000..2a628e8 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c @@ -0,0 +1,967 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) Option Bytes programming + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F1xx devices. + + (#) FLASH Memory I/O Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase page, erase all pages + (++) Program functions: half word, word and doubleword + (#) FLASH Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Lock and Unlock the Option Bytes + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Launch the Option Bytes loader + (++) Erase Option Bytes + (++) Program the data Option Bytes + (++) Get the Write protection. + (++) Get the user option bytes. + + (#) Interrupts and flags management functions : this group + includes all needed functions to: + (++) Handle FLASH interrupts + (++) Wait for last FLASH operation according to its status + (++) Get error flag status + + [..] In addition to these function, this driver includes a set of macros allowing + to handle the following operations: + + (+) Set/Get the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the half cycle access + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro ---------------------------- ---------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_SetErrorCode(void); +extern void FLASH_PageErase(uint32_t PageAddress); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim +@endverbatim + * @{ + */ + +/** + * @brief Program halfword, word or double word at a specified address + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @note FLASH should be previously erased before new programmation (only exception to this + * is when 0x0000 is programmed) + * + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: Specifies the address to be programmed. + * @param Data: Specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint8_t index = 0; + uint8_t nbiterations = 0; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + +#if defined(FLASH_BANK2_END) + if(Address <= FLASH_BANK1_END) + { +#endif /* FLASH_BANK2_END */ + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); +#if defined(FLASH_BANK2_END) + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_BANK2_END */ + + if(status == HAL_OK) + { + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /* Program halfword (16-bit) at a specified address. */ + nbiterations = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /* Program word (32-bit = 2*16-bit) at a specified address. */ + nbiterations = 2U; + } + else + { + /* Program double word (64-bit = 4*16-bit) at a specified address. */ + nbiterations = 4U; + } + + for (index = 0U; index < nbiterations; index++) + { + FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); + +#if defined(FLASH_BANK2_END) + if(Address <= FLASH_BANK1_END) + { +#endif /* FLASH_BANK2_END */ + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); +#if defined(FLASH_BANK2_END) + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); + } +#endif /* FLASH_BANK2_END */ + /* In case of error, stop programation procedure */ + if (status != HAL_OK) + { + break; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program halfword, word or double word at a specified address with interrupt enabled. + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: Specifies the address to be programmed. + * @param Data: Specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + +#if defined(FLASH_BANK2_END) + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } + + if(Address <= FLASH_BANK1_END) + { + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1); + + }else + { + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); + } +#else + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); +#endif /* FLASH_BANK2_END */ + + pFlash.Address = Address; + pFlash.Data = Data; + + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; + /* Program halfword (16-bit) at a specified address. */ + pFlash.DataRemaining = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; + /* Program word (32-bit : 2*16-bit) at a specified address. */ + pFlash.DataRemaining = 2U; + } + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; + /* Program double word (64-bit : 4*16-bit) at a specified address. */ + pFlash.DataRemaining = 4U; + } + + /* Program halfword (16-bit) at a specified address. */ + FLASH_Program_HalfWord(Address, (uint16_t)Data); + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0U; + + /* Check FLASH operation error flags */ +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \ + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))) +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) +#endif /* FLASH_BANK2_END */ + { + /* Return the faulty address */ + addresstmp = pFlash.Address; + /* Reset address */ + pFlash.Address = 0xFFFFFFFFU; + + /* Save the Error code */ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1); +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); +#endif /* FLASH_BANK2_END */ + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still pages to erase */ + if(pFlash.DataRemaining != 0U) + { + addresstmp = pFlash.Address; + /*Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + addresstmp = pFlash.Address + FLASH_PAGE_SIZE; + pFlash.Address = addresstmp; + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + FLASH_PageErase(addresstmp); + } + else + { + /* No more pages to Erase, user callback can be called. */ + /* Reset Sector and stop Erase pages procedure */ + pFlash.Address = addresstmp = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* Operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + +#if defined(FLASH_BANK2_END) + /* Stop Mass Erase procedure if no pending mass erase on other bank */ + if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) + { +#endif /* FLASH_BANK2_END */ + /* MassErase ended. Return the selected bank */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0U); + + /* Stop Mass Erase procedure*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } +#if defined(FLASH_BANK2_END) + } +#endif /* FLASH_BANK2_END */ + else + { + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0U) + { + /* Increment address to 16-bit */ + pFlash.Address += 2U; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16U); + + /* Operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + } + else + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); + } + + /* Reset Address and stop Program procedure */ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + } + +#if defined(FLASH_BANK2_END) + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still pages to erase*/ + if(pFlash.DataRemaining != 0U) + { + /* Indicate user which page address has been erased*/ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + + /* Increment page address to next page */ + pFlash.Address += FLASH_PAGE_SIZE; + addresstmp = pFlash.Address; + + /* Operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); + + FLASH_PageErase(addresstmp); + } + else + { + /*No more pages to Erase*/ + + /*Reset Address and stop Erase pages procedure*/ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* Operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); + + if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER)) + { + /* MassErase ended. Return the selected bank*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0U); + + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + else + { + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0U) + { + /* Increment address to 16-bit */ + pFlash.Address += 2U; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16U); + + /* Operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + } + else + { + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U); + } + + /* Reset Address and stop Program procedure*/ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + } +#endif + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { +#if defined(FLASH_BANK2_END) + /* Operation is completed, disable the PG, PER and MER Bits for both bank */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER)); + + /* Disable End of FLASH Operation and Error source interrupts for both banks */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); +#else + /* Operation is completed, disable the PG, PER and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + + /* Disable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); +#endif /* FLASH_BANK2_END */ + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which has been erased + * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which returned an error + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } +#if defined(FLASH_BANK2_END) + if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) + { + /* Authorize the FLASH BANK2 Registers access */ + WRITE_REG(FLASH->KEYR2, FLASH_KEY1); + WRITE_REG(FLASH->KEYR2, FLASH_KEY2); + + /* Verify Flash BANK2 is unlocked */ + if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) + { + status = HAL_ERROR; + } + } +#endif /* FLASH_BANK2_END */ + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + +#if defined(FLASH_BANK2_END) + /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ + SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); + +#endif /* FLASH_BANK2_END */ + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @note This function will reset automatically the MCU. + * @retval None + */ +void HAL_FLASH_OB_Launch(void) +{ + /* Initiates a system reset request to launch the option byte loading */ + HAL_NVIC_SystemReset(); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + * @brief Peripheral errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be: + * @ref FLASH_Error_Codes + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @param Address specify the address to be programmed. + * @param Data specify the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined(FLASH_BANK2_END) + if(Address <= FLASH_BANK1_END) + { +#endif /* FLASH_BANK2_END */ + /* Proceed to program the new data */ + SET_BIT(FLASH->CR, FLASH_CR_PG); +#if defined(FLASH_BANK2_END) + } + else + { + /* Proceed to program the new data */ + SET_BIT(FLASH->CR2, FLASH_CR2_PG); + } +#endif /* FLASH_BANK2_END */ + + /* Write data in the address */ + *(__IO uint16_t*)Address = Data; +} + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* There is no error flag set */ + return HAL_OK; +} + +#if defined(FLASH_BANK2_END) +/** + * @brief Wait for a FLASH BANK2 operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) +{ + /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset. + Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* If there is an error flag set */ + return HAL_OK; + +} +#endif /* FLASH_BANK2_END */ + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + uint32_t flags = 0U; + +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) +#endif /* FLASH_BANK2_END */ + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; +#if defined(FLASH_BANK2_END) + flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; +#else + flags |= FLASH_FLAG_WRPERR; +#endif /* FLASH_BANK2_END */ + } +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) +#endif /* FLASH_BANK2_END */ + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; +#if defined(FLASH_BANK2_END) + flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; +#else + flags |= FLASH_FLAG_PGERR; +#endif /* FLASH_BANK2_END */ + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); + } + + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(flags); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c new file mode 100644 index 0000000..27b07b8 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c @@ -0,0 +1,1127 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * + Extended Initialization/de-initialization functions + * + Extended I/O operation functions + * + Extended Peripheral Control functions + * + @verbatim + ============================================================================== + ##### Flash peripheral extended features ##### + ============================================================================== + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F1xxx devices. It includes + + (++) Set/Reset the write protection + (++) Program the user Option Bytes + (++) Get the Read protection Level + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @addtogroup FLASH + * @{ + */ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos +#define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos +#define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +/* Erase operations */ +static void FLASH_MassErase(uint32_t Banks); +void FLASH_PageErase(uint32_t PageAddress); + +/* Option bytes control */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); +static uint32_t FLASH_OB_GetWRP(void); +static uint32_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetUser(void); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions + * @brief FLASH Memory Erasing functions + * +@verbatim + ============================================================================== + ##### FLASH Erasing Programming functions ##### + ============================================================================== + + [..] The FLASH Memory Erasing functions, includes the following functions: + (+) @ref HAL_FLASHEx_Erase: return only when erase has been done + (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback + is called with parameter 0xFFFFFFFF + + [..] Any operation of erase should follow these steps: + (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page. + (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). + +@endverbatim + * @{ + */ + + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError pointer to variable that + * contains the configuration information on faulty page in case of error + * (0xFFFFFFFF means that all the pages have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t address = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { +#if defined(FLASH_BANK2_END) + if (pEraseInit->Banks == FLASH_BANK_BOTH) + { + /* Mass Erase requested for Bank1 and Bank2 */ + /* Wait for last operation to be completed */ + if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \ + (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) + { + /*Mass erase to be done*/ + FLASH_MassErase(FLASH_BANK_BOTH); + + /* Wait for last operation to be completed */ + if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \ + (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) + { + status = HAL_OK; + } + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); + } + } + else if (pEraseInit->Banks == FLASH_BANK_2) + { + /* Mass Erase requested for Bank2 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Mass erase to be done*/ + FLASH_MassErase(FLASH_BANK_2); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); + } + } + else +#endif /* FLASH_BANK2_END */ + { + /* Mass Erase requested for Bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Mass erase to be done*/ + FLASH_MassErase(FLASH_BANK_1); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + } + } + } + else + { + /* Page Erase is requested */ + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + +#if defined(FLASH_BANK2_END) + /* Page Erase requested on address located on bank2 */ + if(pEraseInit->PageAddress > FLASH_BANK1_END) + { + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + /* Erase by page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + } + else +#endif /* FLASH_BANK2_END */ + { + /* Page Erase requested on address located on bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + /* Erase page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + +#if defined(FLASH_BANK2_END) + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); + +#endif + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + FLASH_MassErase(pEraseInit->Banks); + } + else + { + /* Erase by page to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + pFlash.DataRemaining = pEraseInit->NbPages; + pFlash.Address = pEraseInit->PageAddress; + + /*Erase 1st page and wait for IT*/ + FLASH_PageErase(pEraseInit->PageAddress); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + ============================================================================== + ##### Option Bytes Programming functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + option bytes operations. + +@endverbatim + * @{ + */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) +{ + uint8_t rdptmp = OB_RDP_LEVEL_0; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Get the actual read protection Option Byte value */ + rdptmp = FLASH_OB_GetRDP(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Restore the last read protection Option Byte value */ + status = FLASH_OB_RDP_LevelConfig(rdptmp); + } + } + + /* Return the erase status */ + return status; +} + +/** + * @brief Program option bytes + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /* Enable of Write protection on the selected page */ + status = FLASH_OB_EnableWRP(pOBInit->WRPPage); + } + else + { + /* Disable of Write protection on the selected page */ + status = FLASH_OB_DisableWRP(pOBInit->WRPPage); + } + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* DATA configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) + { + status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + + /*Get WRP*/ + pOBInit->WRPPage = FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); +} + +/** + * @brief Get the Option byte user data + * @param DATAAdress Address of the option byte DATA + * This parameter can be one of the following values: + * @arg @ref OB_DATA_ADDRESS_DATA0 + * @arg @ref OB_DATA_ADDRESS_DATA1 + * @retval Value programmed in USER data + */ +uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) +{ + uint32_t value = 0; + + if (DATAAdress == OB_DATA_ADDRESS_DATA0) + { + /* Get value programmed in OB USER Data0 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; + } + else + { + /* Get value programmed in OB USER Data1 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; + } + + return value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Full erase of FLASH memory Bank + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg @ref FLASH_BANK_1 Bank1 to be erased + @if STM32F101xG + * @arg @ref FLASH_BANK_2 Bank2 to be erased + * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased + @endif + @if STM32F103xG + * @arg @ref FLASH_BANK_2 Bank2 to be erased + * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased + @endif + * + * @retval None + */ +static void FLASH_MassErase(uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined(FLASH_BANK2_END) + if(Banks == FLASH_BANK_BOTH) + { + /* bank1 & bank2 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR2, FLASH_CR2_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + SET_BIT(FLASH->CR2, FLASH_CR2_STRT); + } + else if(Banks == FLASH_BANK_2) + { + /*Only bank2 will be erased*/ + SET_BIT(FLASH->CR2, FLASH_CR2_MER); + SET_BIT(FLASH->CR2, FLASH_CR2_STRT); + } + else + { +#endif /* FLASH_BANK2_END */ +#if !defined(FLASH_BANK2_END) + /* Prevent unused argument(s) compilation warning */ + UNUSED(Banks); +#endif /* FLASH_BANK2_END */ + /* Only bank1 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +#if defined(FLASH_BANK2_END) + } +#endif /* FLASH_BANK2_END */ +} + +/** + * @brief Enable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write protected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFF; +#if defined(FLASH_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFF; +#endif /* FLASH_WRP1_WRP1 */ +#if defined(FLASH_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFF; +#endif /* FLASH_WRP2_WRP2 */ +#if defined(FLASH_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFF; +#endif /* FLASH_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be protected ******/ + WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES64TO95MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); +#endif /* OB_WRP_PAGES64TO95MASK */ +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES96TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO255MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO511MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES96TO127MASK */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + /* Enable write protection */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 &= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP0_WRP0 */ + +#if defined(FLASH_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 &= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP1_WRP1 */ + +#if defined(FLASH_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 &= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP2_WRP2 */ + +#if defined(FLASH_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 &= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Disable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write unprotected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFF; +#if defined(FLASH_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFF; +#endif /* FLASH_WRP1_WRP1 */ +#if defined(FLASH_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFF; +#endif /* FLASH_WRP2_WRP2 */ +#if defined(FLASH_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFF; +#endif /* FLASH_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be unprotected ******/ + WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES64TO95MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); +#endif /* OB_WRP_PAGES64TO95MASK */ +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES96TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO255MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO511MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES96TO127MASK */ + + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 |= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP0_WRP0 */ + +#if defined(FLASH_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 |= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP1_WRP1 */ + +#if defined(FLASH_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 |= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP2_WRP2 */ + +#if defined(FLASH_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 |= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + return status; +} + +/** + * @brief Set the read protection level. + * @param ReadProtectLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + + WRITE_REG(OB->RDP, ReadProtectLevel); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Program the FLASH User Option Byte. + * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), + * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). + * And BFBF2(Bit5) for STM32F101xG and STM32F103xG . + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); + assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); + assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); +#if defined(FLASH_BANK2_END) + assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); +#endif /* FLASH_BANK2_END */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_BANK2_END) + OB->USER = (UserConfig | 0xF0U); +#else + OB->USER = (UserConfig | 0x88U); +#endif /* FLASH_BANK2_END */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param Address specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data specifies the data to be programmed. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enables the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval The FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (uint32_t)(READ_REG(FLASH->WRPR)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH RDP level + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t readstatus = OB_RDP_LEVEL_0; + uint32_t tmp_reg = 0U; + + /* Read RDP level bits */ + tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); + + if (tmp_reg == FLASH_OBR_RDPRT) + { + readstatus = OB_RDP_LEVEL_1; + } + else + { + readstatus = OB_RDP_LEVEL_0; + } + + return readstatus; +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), + * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). + * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG . + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Erase the specified FLASH memory page + * @param PageAddress FLASH page to erase + * The value of this parameter depend on device used within the same series + * + * @retval None + */ +void FLASH_PageErase(uint32_t PageAddress) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined(FLASH_BANK2_END) + if(PageAddress > FLASH_BANK1_END) + { + /* Proceed to erase the page */ + SET_BIT(FLASH->CR2, FLASH_CR2_PER); + WRITE_REG(FLASH->AR2, PageAddress); + SET_BIT(FLASH->CR2, FLASH_CR2_STRT); + } + else + { +#endif /* FLASH_BANK2_END */ + /* Proceed to erase the page */ + SET_BIT(FLASH->CR, FLASH_CR_PER); + WRITE_REG(FLASH->AR, PageAddress); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +#if defined(FLASH_BANK2_END) + } +#endif /* FLASH_BANK2_END */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c new file mode 100644 index 0000000..6ba68a9 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c @@ -0,0 +1,587 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) Alternate function mode + (+) External interrupt/event lines + + [..] + During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 20 edge detectors in connectivity + line devices, or 19 edge detectors in other devices for generating event/interrupt requests. + Each input line can be independently configured to select the type (event or interrupt) and + the corresponding trigger event (rising or falling or both). Each line can also masked + independently. A pending register maintains the status line of the interrupt requests + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PD0 and PD1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE 0x00000003u +#define EXTI_MODE 0x10000000u +#define GPIO_MODE_IT 0x00010000u +#define GPIO_MODE_EVT 0x00020000u +#define RISING_EDGE 0x00100000u +#define FALLING_EDGE 0x00200000u +#define GPIO_OUTPUT_TYPE 0x00000010u + +#define GPIO_NUMBER 16u + +/* Definitions for bit manipulation of CRL and CRH register */ +#define GPIO_CR_MODE_INPUT 0x00000000u /*!< 00: Input mode (reset state) */ +#define GPIO_CR_CNF_ANALOG 0x00000000u /*!< 00: Analog mode */ +#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004u /*!< 01: Floating input (reset state) */ +#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008u /*!< 10: Input with pull-up / pull-down */ +#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000u /*!< 00: General purpose output push-pull */ +#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004u /*!< 01: General purpose output Open-drain */ +#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008u /*!< 10: Alternate function output Push-pull */ +#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000Cu /*!< 11: Alternate function output Open-drain */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00u; + uint32_t ioposition; + uint32_t iocurrent; + uint32_t temp; + uint32_t config = 0x00u; + __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ + uint32_t registeroffset; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + { + /* Get the IO position */ + ioposition = (0x01uL << position); + + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + + if (iocurrent == ioposition) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + + /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ + switch (GPIO_Init->Mode) + { + /* If we are configuring the pin in OUTPUT push-pull mode */ + case GPIO_MODE_OUTPUT_PP: + /* Check the GPIO speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; + break; + + /* If we are configuring the pin in OUTPUT open-drain mode */ + case GPIO_MODE_OUTPUT_OD: + /* Check the GPIO speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; + break; + + /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */ + case GPIO_MODE_AF_PP: + /* Check the GPIO speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; + break; + + /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */ + case GPIO_MODE_AF_OD: + /* Check the GPIO speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; + break; + + /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */ + case GPIO_MODE_INPUT: + case GPIO_MODE_IT_RISING: + case GPIO_MODE_IT_FALLING: + case GPIO_MODE_IT_RISING_FALLING: + case GPIO_MODE_EVT_RISING: + case GPIO_MODE_EVT_FALLING: + case GPIO_MODE_EVT_RISING_FALLING: + /* Check the GPIO pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + if (GPIO_Init->Pull == GPIO_NOPULL) + { + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; + } + else if (GPIO_Init->Pull == GPIO_PULLUP) + { + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; + + /* Set the corresponding ODR bit */ + GPIOx->BSRR = ioposition; + } + else /* GPIO_PULLDOWN */ + { + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; + + /* Reset the corresponding ODR bit */ + GPIOx->BRR = ioposition; + } + break; + + /* If we are configuring the pin in INPUT analog mode */ + case GPIO_MODE_ANALOG: + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; + break; + + /* Parameters are checked with assert_param */ + default: + break; + } + + /* Check if the current bit belongs to first half or last half of the pin count number + in order to address CRH or CRL register*/ + configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; + registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); + + /* Apply the new configuration of the pin to the register */ + MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + /* Enable AFIO Clock */ + __HAL_RCC_AFIO_CLK_ENABLE(); + temp = AFIO->EXTICR[position >> 2u]; + CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); + AFIO->EXTICR[position >> 2u] = temp; + + + /* Configure the interrupt mask */ + if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + SET_BIT(EXTI->IMR, iocurrent); + } + else + { + CLEAR_BIT(EXTI->IMR, iocurrent); + } + + /* Configure the event mask */ + if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + SET_BIT(EXTI->EMR, iocurrent); + } + else + { + CLEAR_BIT(EXTI->EMR, iocurrent); + } + + /* Enable or disable the rising trigger */ + if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + SET_BIT(EXTI->RTSR, iocurrent); + } + else + { + CLEAR_BIT(EXTI->RTSR, iocurrent); + } + + /* Enable or disable the falling trigger */ + if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + SET_BIT(EXTI->FTSR, iocurrent); + } + else + { + CLEAR_BIT(EXTI->FTSR, iocurrent); + } + } + } + + position++; + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; + __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ + uint32_t registeroffset; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0u) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + + if (iocurrent) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = AFIO->EXTICR[position >> 2u]; + tmp &= 0x0FuL << (4u * (position & 0x03u)); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + { + tmp = 0x0FuL << (4u * (position & 0x03u)); + CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp); + + /* Clear EXTI line configuration */ + CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); + } + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Check if the current bit belongs to first half or last half of the pin count number + in order to address CRH or CRL register */ + configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; + registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); + + /* CRL/CRH default value is floating input(0x04) shifted to correct position */ + MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset); + + /* ODR default value is 0 */ + CLEAR_BIT(GPIOx->ODR, iocurrent); + } + + position++; + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the GPIOs. + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState: specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; + } +} + +/** + * @brief Toggles the specified GPIO pin + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Ouput Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** +* @brief Locks GPIO Pins configuration registers. +* @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence +* has been applied on a port bit, it is no longer possible to modify the value of the port bit until +* the next reset. +* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral +* @param GPIO_Pin: specifies the port bit to be locked. +* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). +* @retval None +*/ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + SET_BIT(tmp, GPIO_Pin); + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin: Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callbacks. + * @param GPIO_Pin: Specifies the pins connected EXTI line + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c new file mode 100644 index 0000000..e6dea5b --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c @@ -0,0 +1,127 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_gpio_ex.c + * @author MCD Application Team + * @brief GPIO Extension HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. + * + Extended features functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral extension features ##### + ============================================================================== + [..] GPIO module on STM32F1 family, manage also the AFIO register: + (+) Possibility to use the EVENTOUT Cortex feature + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to use EVENTOUT Cortex feature + (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() + (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() + (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions + * @{ + */ + +/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + ============================================================================== + ##### Extended features functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() + (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() + (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() + +@endverbatim + * @{ + */ + +/** + * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. + * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. + * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT. + * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. + * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. + * @retval None + */ +void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) +{ + /* Verify the parameters */ + assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); + assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); + + /* Apply the new configuration */ + MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource)); +} + +/** + * @brief Enables the Event Output. + * @retval None + */ +void HAL_GPIOEx_EnableEventout(void) +{ + SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); +} + +/** + * @brief Disables the Event Output. + * @retval None + */ +void HAL_GPIOEx_DisableEventout(void) +{ + CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c new file mode 100644 index 0000000..a9bf56b --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c @@ -0,0 +1,621 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT 0x00010000U +#define PVD_MODE_EVT 0x00020000U +#define PVD_RISING_EDGE 0x00000001U +#define PVD_FALLING_EDGE 0x00000002U +/** + * @} + */ + + +/** @defgroup PWR_register_alias_address PWR Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) +#define PWR_CR_OFFSET 0x00U +#define PWR_CSR_OFFSET 0x04U +#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) +#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) +/** + * @} + */ + +/** @defgroup PWR_CR_register_alias PWR CR Register alias address + * @{ + */ +/* --- CR Register ---*/ +/* Alias word address of LPSDSR bit */ +#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos +#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) + +/* Alias word address of DBP bit */ +#define DBP_BIT_NUMBER PWR_CR_DBP_Pos +#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) + +/* Alias word address of PVDE bit */ +#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos +#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) + +/** + * @} + */ + +/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address + * @{ + */ + +/* --- CSR Register ---*/ +/* Alias word address of EWUP1 bit */ +#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) +/** + * @} + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup PWR_Private_Functions PWR Private Functions + * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section) + * @{ + */ +static void PWR_OverloadWfe(void); + +/* Private functions ---------------------------------------------------------*/ +__NOINLINE +static void PWR_OverloadWfe(void) +{ + __asm volatile( "wfe" ); + __asm volatile( "nop" ); +} + +/** + * @} + */ + + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers ). + * @note If the HSE divided by 128 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + /* Enable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers). + * @note If the HSE divided by 128 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + /* Disable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pin is used to wake up the system from Standby mode. This pin is + forced in input pull-down configuration and is active on rising edges. + (+) There is one WakeUp pin: + WakeUp Pin 1 on PA.00. + + [..] + + *** Low Power modes configuration *** + ===================================== + [..] + The device features 3 low-power modes: + (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like + NVIC, SysTick, etc. are kept running + (+) Stop mode: All clocks are stopped + (+) Standby mode: 1.8V domain powered off + + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + (+) Exit: + (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode. + (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend) + (+++) Any EXTI Line (Internal or External) configured in Event mode + + *** Stop mode *** + ================= + [..] + The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral + clock gating. The voltage regulator can be configured either in normal or low-power mode. + In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC + oscillators are disabled. SRAM and register contents are preserved. + In Stop mode, all I/O pins keep the same state as in Run mode. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx ) + function with: + (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON. + (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. + (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction + (+) Exit: + (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured + (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode. + + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based on the + Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is + consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also + switched off. SRAM and register contents are lost except for registers in the Backup domain + and Standby circuitry + + (+) Entry: + (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in + NRSTpin, IWDG Reset + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, + without depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + *** PWR Workarounds linked to Silicon Limitation *** + ==================================================== + [..] + Below the list of all silicon limitations known on STM32F1xx prouct. + + (#)Workarounds Implemented inside PWR HAL Driver + (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + /* Enable the power voltage detector */ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + /* Disable the power voltage detector */ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Enable the EWUPx pin */ + *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Disable the EWUPx pin */ + *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; +} + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software + * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. + * When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + /* No check on Regulator because parameter not used in SLEEP mode */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters Stop mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by using an interrupt or a wakeup event, + * HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator: Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ + CLEAR_BIT(PWR->CR, PWR_CR_PDDS); + + /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + PWR_OverloadWfe(); /* WFE redefine locally */ + PWR_OverloadWfe(); /* WFE redefine locally */ + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enters Standby mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - TAMPER pin if configured for tamper or calibration out. + * - WKUP pin (PA0) if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + SET_BIT(PWR->CR, PWR_CR_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Enables CORTEX M3 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disables CORTEX M3 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c new file mode 100644 index 0000000..fb3c5be --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c @@ -0,0 +1,1403 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, + and all peripherals are off except internal SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals whose clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC +* @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +static void RCC_Delay(uint32_t mdelay); + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring different output clocks: + (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clocks automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M3 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, + HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 128. + (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly. This clock is derived of the main PLL through PLL Multiplier. + (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK + (+@) IWDG clock which is always the LSI clock. + + (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz. + For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. + @endverbatim + * @{ + */ + +/* + Additional consideration on the SYSCLK based on Latency settings: + +-----------------------------------------------+ + | Latency | SYSCLK clock frequency (MHz) | + |---------------|-------------------------------| + |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + |---------------|-------------------------------| + |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + |---------------|-------------------------------| + |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | + +-----------------------------------------------+ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL, PLL2 and PLL3 are OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS and MCO1 OFF + * - All interrupts disabled + * - All flags are cleared + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM bits to the reset value */ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Second step is to clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Ensure to reset PLLSRC and PLLMUL bits */ + CLEAR_REG(RCC->CFGR); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset HSEON & CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + +#if defined(RCC_PLL2_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLL2ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); + + /* Wait till PLL2 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLL2_SUPPORT */ + +#if defined(RCC_PLLI2S_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLL3ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); + + /* Wait till PLL3 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_CFGR2_PREDIV1) + /* Reset CFGR2 register */ + CLEAR_REG(RCC->CFGR2); +#endif /* RCC_CFGR2_PREDIV1 */ + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); + + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS) + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t pll_config; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* To have a fully stabilized clock in the specified range, a software delay of 1ms + should be added.*/ + RCC_Delay(1); + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Require to disable power clock if necessary */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + +#if defined(RCC_CR_PLL2ON) + /*-------------------------------- PLL2 Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); + if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) + { + /* This bit can not be cleared if the PLL2 clock is used indirectly as system + clock (i.e. it is used as PLL clock entry that is used as system clock). */ + if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ + (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ + ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) + { + return HAL_ERROR; + } + else + { + if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); + assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLLI2S is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); + + /* Configure the main PLL2 multiplication factors. */ + __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); + + /* Enable the main PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Set PREDIV1 source to HSE */ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); + + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + +#endif /* RCC_CR_PLL2ON */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv factor --------------------------------*/ + /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ + if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) + { + /* Check the parameter */ + assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); +#if defined(RCC_CFGR2_PREDIV1SRC) + assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); + + /* Set PREDIV1 source */ + SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); +#endif /* RCC_CFGR2_PREDIV1SRC */ + + /* Set PREDIV1 Value */ + __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); + } + + /* Configure the main PLL clock source and multiplication factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLMUL); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) + { + return HAL_ERROR; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * The value of this parameter depend on device used within the same series + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + +#if defined(FLASH_ACR_LATENCY) + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } +} + +#endif /* FLASH_ACR_LATENCY */ +/*-------------------------- HCLK Configuration --------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + +#if defined(FLASH_ACR_LATENCY) + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } +} +#endif /* FLASH_ACR_LATENCY */ + +/*-------------------------- PCLK1 Configuration ---------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick(uwTickPrio); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + + @endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + @if STM32F105xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source + @endif + @if STM32F107xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source + @endif + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio = {0U}; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(RCC_MCOx); + UNUSED(RCC_MCODiv); + + /* Configure the MCO1 pin in alternate function mode */ + gpio.Mode = GPIO_MODE_AF_PP; + gpio.Speed = GPIO_SPEED_FREQ_HIGH; + gpio.Pull = GPIO_NOPULL; + gpio.Pin = MCO1_PIN; + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + + /* Configure the MCO clock source */ + __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) + * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. + * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ +#if defined(RCC_CFGR2_PREDIV1SRC) + const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +#else + const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; +#if defined(RCC_CFGR2_PREDIV1) + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +#else + const uint8_t aPredivFactorTable[2] = {1, 2}; +#endif /*RCC_CFGR2_PREDIV1*/ + +#endif + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + uint32_t sysclockfreq = 0U; +#if defined(RCC_CFGR2_PREDIV1SRC) + uint32_t prediv2 = 0U, pll2mul = 0U; +#endif /*RCC_CFGR2_PREDIV1SRC*/ + + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; + if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + { +#if defined(RCC_CFGR2_PREDIV1) + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; +#else + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; +#endif /*RCC_CFGR2_PREDIV1*/ +#if defined(RCC_CFGR2_PREDIV1SRC) + + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) + { + /* PLL2 selected as Prediv1 source */ + /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; + pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); + } + else + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); + } + + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ + /* In this case need to divide pllclk by 2 */ + if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) + { + pllclk = pllclk / 2; + } +#else + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); +#endif /*RCC_CFGR2_PREDIV1SRC*/ + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); + } + sysclockfreq = pllclk; + break; + } + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + +#if defined(RCC_CFGR2_PREDIV1SRC) + /* Get the Prediv1 source --------------------------------------------------*/ + RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); +#endif /* RCC_CFGR2_PREDIV1SRC */ + + /* Get the HSE configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL); +#if defined(RCC_CR_PLL2ON) + /* Get the PLL2 configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON) + { + RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON; + } + else + { + RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF; + } + RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2(); + RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL); +#endif /* RCC_CR_PLL2ON */ +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * contains the current clock configuration. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(pFLatency != NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + +#if defined(FLASH_ACR_LATENCY) + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +#else + /* For VALUE lines devices, only LATENCY_0 can be set*/ + *pFLatency = (uint32_t)FLASH_LATENCY_0; +#endif +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief This function provides delay (in milliseconds) based on CPU cycles method. + * @param mdelay: specifies the delay time length, in milliseconds. + * @retval None + */ +static void RCC_Delay(uint32_t mdelay) +{ + __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); + do + { + __NOP(); + } + while (Delay --); +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c new file mode 100644 index 0000000..883ab76 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c @@ -0,0 +1,863 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/** @defgroup RCCEx RCCEx + * @brief RCC Extension HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(RTC clock). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on + * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to + * manually disable it. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U, temp_reg = 0U; +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t pllactive = 0U; +#endif /* STM32F105xC || STM32F107xC */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------------- RTC/LCD Configuration ------------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + FlagStatus pwrclkchanged = RESET; + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = temp_reg; + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + + /* Require to disable power clock if necessary */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*------------------------------ ADC clock Configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + } + +#if defined(STM32F105xC) || defined(STM32F107xC) + /*------------------------------ I2S2 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + + /* Configure the I2S2 clock source */ + __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + } + + /*------------------------------ I2S3 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); + + /* Configure the I2S3 clock source */ + __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); + } + + /*------------------------------ PLL I2S Configuration ----------------------*/ + /* Check that PLLI2S need to be enabled */ + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) + { + /* Update flag to indicate that PLL I2S should be active */ + pllactive = 1; + } + + /* Check if PLL I2S need to be enabled */ + if (pllactive == 1) + { + /* Enable PLL I2S only if not active */ + if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); + assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLL2 is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); + + /* Configure the main PLLI2S multiplication factors. */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); + + /* Enable the main PLLI2S. */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ + if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) + { + return HAL_ERROR; + } + } + } +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + /*------------------------------ USB clock Configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + /* Check the parameters */ + assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + + return HAL_OK; +} + +/** + * @brief Get the PeriphClkInit according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t srcclk = 0U; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; + + /* Get the RTC configuration -----------------------------------------------*/ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + /* Source clock is LSE or LSI*/ + PeriphClkInit->RTCClockSelection = srcclk; + + /* Get the ADC clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC; + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + +#if defined(STM32F105xC) || defined(STM32F107xC) + /* Get the I2S2 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; + PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); + + /* Get the I2S3 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; + PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE(); + +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F103xE) || defined(STM32F103xG) + /* Get the I2S2 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; + PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK; + + /* Get the I2S3 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; + PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK; + +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + /* Get the USB clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +} + +/** + * @brief Returns the peripheral clock frequency + * @note Returns 0 if peripheral clock is unknown + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + @if STM32F103xE + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + @endif + @if STM32F103xG + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + @endif + @if STM32F105xC + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F107xC + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F102xx + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F103xx + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ +#if defined(STM32F105xC) || defined(STM32F107xC) + const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; + uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; +#endif /* STM32F105xC || STM32F107xC */ +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \ + defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; + const uint8_t aPredivFactorTable[2] = {1, 2}; + + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + uint32_t temp_reg = 0U, frequency = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + { +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + case RCC_PERIPHCLK_USB: + { + /* Get RCC configuration ------------------------------------------------------*/ + temp_reg = RCC->CFGR; + + /* Check if PLL is enabled */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) + { + pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; + if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + { +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) + prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; +#else + prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) + { + /* PLL2 selected as Prediv1 source */ + /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; + pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); + } + else + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); + } + + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ + /* In this case need to divide pllclk by 2 */ + if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) + { + pllclk = pllclk / 2; + } +#else + if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); + } +#endif /* STM32F105xC || STM32F107xC */ + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); + } + + /* Calcul of the USB frequency*/ +#if defined(STM32F105xC) || defined(STM32F107xC) + /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ + if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) + { + /* Prescaler of 2 selected for USB */ + frequency = pllclk; + } + else + { + /* Prescaler of 3 selected for USB */ + frequency = (2 * pllclk) / 3; + } +#else + /* USBCLK = PLLCLK / USB prescaler */ + if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) + { + /* No prescaler selected for USB */ + frequency = pllclk; + } + else + { + /* Prescaler of 1.5 selected for USB */ + frequency = (pllclk * 2) / 3; + } +#endif + } + break; + } +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) + case RCC_PERIPHCLK_I2S2: + { +#if defined(STM32F103xE) || defined(STM32F103xG) + /* SYSCLK used as source clock for I2S2 */ + frequency = HAL_RCC_GetSysClockFreq(); +#else + if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) + { + /* SYSCLK used as source clock for I2S2 */ + frequency = HAL_RCC_GetSysClockFreq(); + } + else + { + /* Check if PLLI2S is enabled */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) + { + /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; + frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); + } + } +#endif /* STM32F103xE || STM32F103xG */ + break; + } + case RCC_PERIPHCLK_I2S3: + { +#if defined(STM32F103xE) || defined(STM32F103xG) + /* SYSCLK used as source clock for I2S3 */ + frequency = HAL_RCC_GetSysClockFreq(); +#else + if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) + { + /* SYSCLK used as source clock for I2S3 */ + frequency = HAL_RCC_GetSysClockFreq(); + } + else + { + /* Check if PLLI2S is enabled */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) + { + /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; + frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); + } + } +#endif /* STM32F103xE || STM32F103xG */ + break; + } +#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + case RCC_PERIPHCLK_RTC: + { + /* Get RCC BDCR configuration ------------------------------------------------------*/ + temp_reg = RCC->BDCR; + + /* Check if LSE is ready if RTC clock selection is LSE */ + if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready if RTC clock selection is LSI */ + else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + { + frequency = LSI_VALUE; + } + else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + { + frequency = HSE_VALUE / 128U; + } + /* Clock not enabled for RTC*/ + else + { + /* nothing to do: frequency already initialized to 0U */ + } + break; + } + case RCC_PERIPHCLK_ADC: + { + frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); + break; + } + default: + { + break; + } + } + return (frequency); +} + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function + * @brief PLLI2S Management functions + * +@verbatim + =============================================================================== + ##### Extended PLLI2S Management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PLLI2S + activation or deactivation +@endverbatim + * @{ + */ + +/** + * @brief Enable PLLI2S + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart = 0U; + + /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/ + if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL)); + assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLL2 is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Disable the main PLLI2S. */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value); + + + /* Configure the main PLLI2S multiplication factors. */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL); + + /* Enable the main PLLI2S. */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */ + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S + * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart = 0U; + + /* Disable PLL I2S as not requested by I2S2 or I2S3*/ + if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) + { + /* Disable the main PLLI2S. */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/ + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function + * @brief PLL2 Management functions + * +@verbatim + =============================================================================== + ##### Extended PLL2 Management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PLL2 + activation or deactivation +@endverbatim + * @{ + */ + +/** + * @brief Enable PLL2 + * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that + * contains the configuration information for the PLL2 + * @note The PLL2 configuration not modified if used indirectly as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) +{ + uint32_t tickstart = 0U; + + /* This bit can not be cleared if the PLL2 clock is used indirectly as system + clock (i.e. it is used as PLL clock entry that is used as system clock). */ + if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ + (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ + ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) + { + return HAL_ERROR; + } + else + { + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL)); + assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLLI2S is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value); + + /* Configure the main PLL2 multiplication factors. */ + __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL); + + /* Enable the main PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLL2 + * @note PLL2 is not disabled if used indirectly as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) +{ + uint32_t tickstart = 0U; + + /* This bit can not be cleared if the PLL2 clock is used indirectly as system + clock (i.e. it is used as PLL clock entry that is used as system clock). */ + if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ + (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ + ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) + { + return HAL_ERROR; + } + else + { + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c new file mode 100644 index 0000000..2a018bd --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c @@ -0,0 +1,7421 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_TIM_RegisterCallback() to register a callback. + @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_ALL: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + default: + break; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + default: + break; + } + + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances + * supporting a break input. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + break; + } + return HAL_OK; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P); + tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P); + tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c new file mode 100644 index 0000000..84522da --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c @@ -0,0 +1,2296 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + UNUSED(Remap); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/MDK-ARM/DebugConfig/uksvep_2_2_v1_STM32F103RC_1.0.0.dbgconf b/MDK-ARM/DebugConfig/uksvep_2_2_v1_STM32F103RC_1.0.0.dbgconf new file mode 100644 index 0000000..66e10b6 --- /dev/null +++ b/MDK-ARM/DebugConfig/uksvep_2_2_v1_STM32F103RC_1.0.0.dbgconf @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/MDK-ARM/EventRecorderStub.scvd b/MDK-ARM/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/MDK-ARM/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/MDK-ARM/JLinkLog.txt b/MDK-ARM/JLinkLog.txt new file mode 100644 index 0000000..ca3e0d1 --- /dev/null +++ b/MDK-ARM/JLinkLog.txt @@ -0,0 +1,20283 @@ +T3F74 26219:235.269 SEGGER J-Link V7.64c Log File +T3F74 26219:235.372 DLL Compiled: Apr 20 2022 16:08:48 +T3F74 26219:235.391 Logging started @ 2025-06-11 13:54 +T3F74 26219:235.407 - 563.488ms +T3F74 26219:235.428 JLINK_SetWarnOutHandler(...) +T3F74 26219:235.444 - 0.024ms +T3F74 26219:235.464 JLINK_OpenEx(...) +T3F74 26219:237.503 Firmware: J-Link Ultra V4 compiled Sep 22 2022 15:00:10 +T3F74 26219:238.005 Firmware: J-Link Ultra V4 compiled Sep 22 2022 15:00:10 +T3F74 26219:238.289 Decompressing FW timestamp took 250 us +T3F74 26219:241.531 Hardware: V4.00 +T3F74 26219:241.569 S/N: 504302699 +T3F74 26219:241.591 OEM: SEGGER +T3F74 26219:241.614 Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB +T3F74 26219:243.127 TELNET listener socket opened on port 19021 +T3F74 26219:249.531 WEBSRV WEBSRV_Init(): Starting webserver thread(s) +T3F74 26219:249.710 WEBSRV Webserver running on local port 19080 +T3F74 26219:260.364 - 24.940ms returns "O.K." +T3F74 26219:260.436 JLINK_GetEmuCaps() +T3F74 26219:260.453 - 0.025ms returns 0xB9FF7BBF +T3F74 26219:260.476 JLINK_TIF_GetAvailable(...) +T3F74 26219:261.528 - 1.070ms +T3F74 26219:261.566 JLINK_SetErrorOutHandler(...) +T3F74 26219:261.583 - 0.025ms +T3F74 26219:261.913 JLINK_ExecCommand("ProjectFile = "D:\ProjectSTM32\GIT\UKSVEP_23550_2\MDK-ARM\JLinkSettings.ini"", ...). +T3F74 26219:263.496 - 1.594ms returns 0x00 +T3F74 26219:263.585 JLINK_ExecCommand("Device = STM32F103RC", ...). +T3F74 26219:264.254 Device "STM32F103RC" selected. +T3F74 26219:265.069 - 1.478ms returns 0x00 +T3F74 26219:265.098 JLINK_ExecCommand("DisableConnectionTimeout", ...). +T3F74 26219:265.121 - 0.011ms returns 0x01 +T3F74 26219:265.143 JLINK_GetHardwareVersion() +T3F74 26219:265.159 - 0.024ms returns 40000 +T3F74 26219:265.179 JLINK_GetDLLVersion() +T3F74 26219:265.195 - 0.023ms returns 76403 +T3F74 26219:265.214 JLINK_GetOEMString(...) +T3F74 26219:265.233 JLINK_GetFirmwareString(...) +T3F74 26219:265.249 - 0.023ms +T3F74 26219:265.382 JLINK_GetDLLVersion() +T3F74 26219:265.399 - 0.025ms returns 76403 +T3F74 26219:265.418 JLINK_GetCompileDateTime() +T3F74 26219:265.434 - 0.023ms +T3F74 26219:265.483 JLINK_GetFirmwareString(...) +T3F74 26219:265.499 - 0.024ms +T3F74 26219:265.546 JLINK_GetHardwareVersion() +T3F74 26219:265.562 - 0.024ms returns 40000 +T3F74 26219:265.610 JLINK_GetSN() +T3F74 26219:265.626 - 0.024ms returns 504302699 +T3F74 26219:265.673 JLINK_GetOEMString(...) +T3F74 26219:265.751 JLINK_TIF_Select(JLINKARM_TIF_JTAG) +T3F74 26219:267.607 - 1.869ms returns 0x00 +T3F74 26219:267.635 JLINK_HasError() +T3F74 26219:267.656 JLINK_SetSpeed(3000) +T3F74 26219:267.861 - 0.213ms +T3F74 26219:267.883 JLINK_GetIdData(pIdData) +T3F74 26219:268.243 InitTarget() start +T3F74 26219:268.267 J-Link Script File: Executing InitTarget() +T3F74 26219:269.338 TotalIRLen = 4, IRPrint = 0x01 +T3F74 26219:269.980 JTAG chain detection found 1 devices: +T3F74 26219:270.035 #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP +T3F74 26219:276.673 InitTarget() end +T3F74 26219:277.405 TotalIRLen = 4, IRPrint = 0x01 +T3F74 26219:277.917 JTAG chain detection found 1 devices: +T3F74 26219:277.972 #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP +T3F74 26219:278.914 DPv0 detected +T3F74 26219:278.959 Scanning AP map to find all available APs +T3F74 26219:279.516 AP[1]: Stopped AP scan as end of AP map has been reached +T3F74 26219:279.561 AP[0]: AHB-AP (IDR: 0x24770011) +T3F74 26219:279.605 Iterating through AP map to find AHB-AP to use +T3F74 26219:280.414 AP[0]: Core found +T3F74 26219:280.467 AP[0]: AHB-AP ROM base: 0xE00FF000 +T3F74 26219:280.901 CPUID register: 0x410FC241. Implementer code: 0x41 (ARM) +T3F74 26219:280.959 Found Cortex-M4 r0p1, Little endian. +T3F74 26219:281.046 Identified core does not match configuration. (Found: Cortex-M4, Configured: Cortex-M3) +T3F74 26219:281.513 -- Max. mem block: 0x0000DCF8 +T3F74 26219:281.737 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T3F74 26219:282.495 CPU_ReadMem(4 bytes @ 0xE0002000) +T3F74 26219:282.896 FPUnit: 6 code (BP) slots and 2 literal slots +T3F74 26219:282.978 CPU_ReadMem(4 bytes @ 0xE000EDFC) +T3F74 26219:283.365 CPU_WriteMem(4 bytes @ 0xE000EDFC) +T3F74 26219:283.739 CPU_ReadMem(4 bytes @ 0xE0001000) +T3F74 26219:284.115 CPU_WriteMem(4 bytes @ 0xE0001000) +T3F74 26219:284.489 CPU_ReadMem(4 bytes @ 0xE000ED88) +T3F74 26219:284.881 CPU_WriteMem(4 bytes @ 0xE000ED88) +T3F74 26219:285.370 CPU_ReadMem(4 bytes @ 0xE000ED88) +T3F74 26219:285.746 CPU_WriteMem(4 bytes @ 0xE000ED88) +T3F74 26219:286.152 CoreSight components: +T3F74 26219:286.207 ROMTbl[0] @ E00FF000 +T3F74 26219:286.232 CPU_ReadMem(64 bytes @ 0xE00FF000) +T3F74 26219:287.123 CPU_ReadMem(32 bytes @ 0xE000EFE0) +T3F74 26219:287.641 [0][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7 +T3F74 26219:287.662 CPU_ReadMem(32 bytes @ 0xE0001FE0) +T3F74 26219:288.278 [0][1]: E0001000 CID B105E00D PID 003BB002 DWT +T3F74 26219:288.304 CPU_ReadMem(32 bytes @ 0xE0002FE0) +T3F74 26219:288.901 [0][2]: E0002000 CID B105E00D PID 002BB003 FPB +T3F74 26219:288.926 CPU_ReadMem(32 bytes @ 0xE0000FE0) +T3F74 26219:289.673 [0][3]: E0000000 CID B105E00D PID 003BB001 ITM +T3F74 26219:289.701 CPU_ReadMem(32 bytes @ 0xE0040FE0) +T3F74 26219:290.267 [0][4]: E0040000 CID B105900D PID 000BB9A1 TPIU +T3F74 26219:290.289 CPU_ReadMem(32 bytes @ 0xE0041FE0) +T3F74 26219:290.891 [0][5]: E0041000 CID B105900D PID 000BB925 ETM +T3F74 26219:290.933 pIdData->ScanLen=4 +T3F74 26219:290.952 +T3F74 26219:290.967 pIdData->NumDevices=1 +T3F74 26219:290.995 +T3F74 26219:291.010 pIdData->aId[0]=0x4BA00477 +T3F74 26219:291.032 +T3F74 26219:291.047 pIdData->aIrRead[0]=0 +T3F74 26219:291.069 +T3F74 26219:291.088 pIdData->aScanLen[0]=0 +T3F74 26219:291.110 +T3F74 26219:291.125 pIdData->aScanRead[0]=0 +T3F74 26219:291.147 +T3F74 26219:291.162 - 23.286ms +T3F74 26219:291.197 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) +T3F74 26219:291.213 - 0.024ms returns 1268778103 +T3F74 26219:291.235 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) +T3F74 26219:291.251 - 0.023ms returns 0 +T3F74 26219:291.272 JLINK_GetDLLVersion() +T3F74 26219:291.288 - 0.023ms returns 76403 +T3F74 26219:291.310 JLINK_CORE_GetFound() +T3F74 26219:291.326 - 0.023ms returns 0xE0000FF +T3F74 26219:291.348 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) +T3F74 26219:291.365 Value=0xE00FF000 +T3F74 26219:291.387 - 0.047ms returns 0 +T3F74 26219:291.463 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) +T3F74 26219:291.481 Value=0xE00FF000 +T3F74 26219:291.503 - 0.047ms returns 0 +T3F74 26219:291.521 JLINK_GetDebugInfo(0x101 = JLINKARM_DEBUG_INFO_ETM_ADDR_INDEX) +T3F74 26219:291.538 Value=0xE0041000 +T3F74 26219:291.560 - 0.046ms returns 0 +T3F74 26219:291.580 JLINK_ReadMemEx(0xE0041FD0, 0x20 Bytes, Flags = 0x02000004) +T3F74 26219:291.604 CPU_ReadMem(32 bytes @ 0xE0041FD0) +T3F74 26219:292.793 Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T3F74 26219:292.822 - 1.248ms returns 32 (0x20) +T3F74 26219:292.840 JLINK_GetDebugInfo(0x102 = JLINKARM_DEBUG_INFO_MTB_ADDR_INDEX) +T3F74 26219:292.855 Value=0x00000000 +T3F74 26219:292.874 - 0.040ms returns 0 +T3F74 26219:292.889 JLINK_GetDebugInfo(0x103 = JLINKARM_DEBUG_INFO_TPIU_ADDR_INDEX) +T3F74 26219:292.903 Value=0xE0040000 +T3F74 26219:292.921 - 0.039ms returns 0 +T3F74 26219:292.936 JLINK_GetDebugInfo(0x104 = JLINKARM_DEBUG_INFO_ITM_ADDR_INDEX) +T3F74 26219:292.950 Value=0xE0000000 +T3F74 26219:292.969 - 0.041ms returns 0 +T3F74 26219:292.986 JLINK_GetDebugInfo(0x105 = JLINKARM_DEBUG_INFO_DWT_ADDR_INDEX) +T3F74 26219:293.002 Value=0xE0001000 +T3F74 26219:293.020 - 0.042ms returns 0 +T3F74 26219:293.044 JLINK_GetDebugInfo(0x106 = JLINKARM_DEBUG_INFO_FPB_ADDR_INDEX) +T3F74 26219:293.060 Value=0xE0002000 +T3F74 26219:293.083 - 0.046ms returns 0 +T3F74 26219:293.100 JLINK_GetDebugInfo(0x107 = JLINKARM_DEBUG_INFO_NVIC_ADDR_INDEX) +T3F74 26219:293.116 Value=0xE000E000 +T3F74 26219:293.138 - 0.045ms returns 0 +T3F74 26219:293.156 JLINK_GetDebugInfo(0x10C = JLINKARM_DEBUG_INFO_DBG_ADDR_INDEX) +T3F74 26219:293.172 Value=0xE000EDF0 +T3F74 26219:293.202 - 0.054ms returns 0 +T3F74 26219:293.220 JLINK_GetDebugInfo(0x01 = Unknown) +T3F74 26219:293.236 Value=0x00000001 +T3F74 26219:293.258 - 0.045ms returns 0 +T3F74 26219:293.279 JLINK_ReadMemU32(0xE000ED00, 0x1 Items) +T3F74 26219:293.301 CPU_ReadMem(4 bytes @ 0xE000ED00) +T3F74 26219:294.462 Data: 41 C2 0F 41 +T3F74 26219:294.541 Debug reg: CPUID +T3F74 26219:294.582 - 1.310ms returns 1 (0x1) +T3F74 26219:294.601 JLINK_GetDebugInfo(0x10F = JLINKARM_DEBUG_INFO_HAS_CORTEX_M_SECURITY_EXT_INDEX) +T3F74 26219:294.615 Value=0x00000000 +T3F74 26219:294.634 - 0.040ms returns 0 +T3F74 26219:294.649 JLINK_HasError() +T3F74 26219:294.668 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL) +T3F74 26219:294.682 - 0.020ms returns JLINKARM_CM3_RESET_TYPE_NORMAL +T3F74 26219:294.699 JLINK_Reset() +T3F74 26219:294.718 CPU is running +T3F74 26219:294.739 CPU_WriteMem(4 bytes @ 0xE000EDF0) +T3F74 26219:295.864 CPU is running +T3F74 26219:295.924 CPU_WriteMem(4 bytes @ 0xE000EDFC) +T3F74 26219:296.428 Reset: Halt core after reset via DEMCR.VC_CORERESET. +T3F74 26219:296.485 Reset: Reset device via AIRCR.SYSRESETREQ. +T3F74 26219:296.513 CPU is running +T3F74 26219:296.534 CPU_WriteMem(4 bytes @ 0xE000ED0C) +T3F74 26219:348.670 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T3F74 26219:349.800 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T3F74 26219:350.238 CPU is running +T3F74 26219:350.264 CPU_WriteMem(4 bytes @ 0xE000EDF0) +T3F74 26219:350.613 CPU is running +T3F74 26219:350.638 CPU_WriteMem(4 bytes @ 0xE000EDFC) +T3F74 26219:356.719 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T3F74 26219:360.418 CPU_WriteMem(4 bytes @ 0xE000EDFC) +T3F74 26219:360.867 CPU_WriteMem(4 bytes @ 0xE0001028) +T3F74 26219:361.242 CPU_WriteMem(4 bytes @ 0xE0001038) +T3F74 26219:361.643 CPU_WriteMem(4 bytes @ 0xE0001048) +T3F74 26219:361.993 CPU_WriteMem(4 bytes @ 0xE0001058) +T3F74 26219:362.369 CPU_WriteMem(4 bytes @ 0xE0002000) +T3F74 26219:362.748 CPU_ReadMem(4 bytes @ 0xE000EDFC) +T3F74 26219:363.231 CPU_ReadMem(4 bytes @ 0xE0001000) +T3F74 26219:363.608 - 68.918ms +T3F74 26219:363.688 JLINK_HasError() +T3F74 26219:363.717 JLINK_ReadReg(R15 (PC)) +T3F74 26219:363.736 - 0.027ms returns 0x080001CC +T3F74 26219:363.755 JLINK_ReadReg(XPSR) +T3F74 26219:363.772 - 0.025ms returns 0x01000000 +T3F74 26219:363.794 JLINK_Halt() +T3F74 26219:363.811 - 0.024ms returns 0x00 +T3F74 26219:363.830 JLINK_ReadMemU32(0xE000EDF0, 0x1 Items) +T3F74 26219:363.853 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T3F74 26219:364.230 Data: 03 00 03 00 +T3F74 26219:364.255 Debug reg: DHCSR +T3F74 26219:364.278 - 0.456ms returns 1 (0x1) +T3F74 26219:364.299 JLINK_WriteU32_64(0xE000EDF0, 0xA05F0003) +T3F74 26219:364.316 Debug reg: DHCSR +T3F74 26219:364.736 CPU_WriteMem(4 bytes @ 0xE000EDF0) +T3F74 26219:365.745 - 1.466ms returns 0 (0x00000000) +T3F74 26219:365.783 JLINK_WriteU32_64(0xE000EDFC, 0x01000000) +T3F74 26219:365.804 Debug reg: DEMCR +T3F74 26219:365.845 CPU_WriteMem(4 bytes @ 0xE000EDFC) +T3F74 26219:366.259 - 0.490ms returns 0 (0x00000000) +T3F74 26219:366.474 JLINK_GetHWStatus(...) +T3F74 26219:367.559 - 1.105ms returns 0 +T3F74 26219:368.237 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) +T3F74 26219:368.269 - 0.041ms returns 0x06 +T3F74 26219:368.291 JLINK_GetNumBPUnits(Type = 0xF0) +T3F74 26219:368.308 - 0.025ms returns 0x2000 +T3F74 26219:368.329 JLINK_GetNumWPUnits() +T3F74 26219:368.347 - 0.025ms returns 4 +T3F74 26219:368.502 JLINK_GetSpeed() +T3F74 26219:368.522 - 0.028ms returns 2997 +T3F74 26219:368.602 JLINK_ReadMemU32(0xE000E004, 0x1 Items) +T3F74 26219:368.637 CPU_ReadMem(4 bytes @ 0xE000E004) +T3F74 26219:369.808 Data: 02 00 00 00 +T3F74 26219:369.840 - 1.246ms returns 1 (0x1) +T3F74 26219:369.863 JLINK_ReadMemU32(0xE000E004, 0x1 Items) +T3F74 26219:369.885 CPU_ReadMem(4 bytes @ 0xE000E004) +T3F74 26219:370.367 Data: 02 00 00 00 +T3F74 26219:370.399 - 0.544ms returns 1 (0x1) +T3F74 26219:370.423 JLINK_WriteMemEx(0xE0001000, 0x0000001C Bytes, Flags = 0x02000004) +T3F74 26219:370.441 Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T3F74 26219:370.486 CPU_WriteMem(28 bytes @ 0xE0001000) +T3F74 26219:370.984 - 0.570ms returns 0x1C +T3F74 26219:371.007 JLINK_HasError() +T3F74 26219:371.027 JLINK_ReadReg(R15 (PC)) +T3F74 26219:371.044 - 0.026ms returns 0x080001CC +T3F74 26219:371.064 JLINK_ReadReg(XPSR) +T3F74 26219:371.081 - 0.025ms returns 0x01000000 +T3F74 26219:384.174 JLINK_ReadMemEx(0xE0001004, 0x4 Bytes, Flags = 0x02000000) +T3F74 26219:384.213 Data: 00 00 00 00 +T3F74 26219:384.238 Debug reg: DWT_CYCCNT +T3F74 26219:384.260 - 0.095ms returns 4 (0x4) +T3F74 26219:482.995 JLINK_HasError() +T3F74 26219:483.039 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL) +T3F74 26219:483.057 - 0.026ms returns JLINKARM_CM3_RESET_TYPE_NORMAL +T3F74 26219:483.076 JLINK_Reset() +T3F74 26219:483.105 CPU_WriteMem(4 bytes @ 0xE000EDF0) +T3F74 26219:484.281 CPU_WriteMem(4 bytes @ 0xE000EDFC) +T3F74 26219:484.775 Reset: Halt core after reset via DEMCR.VC_CORERESET. +T3F74 26219:484.831 Reset: Reset device via AIRCR.SYSRESETREQ. +T3F74 26219:484.857 CPU_WriteMem(4 bytes @ 0xE000ED0C) +T3F74 26219:536.745 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T3F74 26219:537.990 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T3F74 26219:538.470 CPU_WriteMem(4 bytes @ 0xE000EDF0) +T3F74 26219:538.842 CPU_WriteMem(4 bytes @ 0xE000EDFC) +T3F74 26219:544.366 CPU_ReadMem(4 bytes @ 0xE000EDF0) +T3F74 26219:548.346 CPU_WriteMem(4 bytes @ 0xE000EDFC) +T3F74 26219:549.588 CPU_WriteMem(4 bytes @ 0xE0001028) +T3F74 26219:550.091 CPU_WriteMem(4 bytes @ 0xE0001038) +T3F74 26219:550.465 CPU_WriteMem(4 bytes @ 0xE0001048) +T3F74 26219:550.842 CPU_WriteMem(4 bytes @ 0xE0001058) +T3F74 26219:551.210 CPU_WriteMem(4 bytes @ 0xE0002000) +T3F74 26219:551.583 CPU_ReadMem(4 bytes @ 0xE000EDFC) +T3F74 26219:551.977 CPU_ReadMem(4 bytes @ 0xE0001000) +T3F74 26219:552.465 - 69.397ms +T3F74 26219:552.552 JLINK_HasError() +T3F74 26219:552.572 JLINK_ReadReg(R15 (PC)) +T3F74 26219:552.591 - 0.027ms returns 0x080001CC +T3F74 26219:552.610 JLINK_ReadReg(XPSR) +T3F74 26219:552.626 - 0.024ms returns 0x01000000 +T3F74 26219:553.373 JLINK_ReadMemEx(0x08000130, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:553.402 CPU_ReadMem(128 bytes @ 0x08000100) +T3F74 26219:555.802 -- Updating C cache (128 bytes @ 0x08000100) +T3F74 26219:555.836 -- Read from C cache (60 bytes @ 0x08000130) +T3F74 26219:555.861 Data: 00 F0 02 F8 00 F0 3A F8 0A A0 90 E8 00 0C 82 44 ... +T3F74 26219:555.884 - 2.519ms returns 60 (0x3C) +T3F74 26219:555.906 JLINK_ReadMemEx(0x08000130, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:555.924 -- Read from C cache (2 bytes @ 0x08000130) +T3F74 26219:555.947 Data: 00 F0 +T3F74 26219:555.970 - 0.072ms returns 2 (0x2) +T3F74 26219:556.094 JLINK_ReadMemEx(0x08000132, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:556.112 -- Read from C cache (2 bytes @ 0x08000132) +T3F74 26219:556.135 Data: 02 F8 +T3F74 26219:556.157 - 0.070ms returns 2 (0x2) +T3F74 26219:556.177 JLINK_ReadMemEx(0x08000134, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:556.195 -- Read from C cache (60 bytes @ 0x08000134) +T3F74 26219:556.219 Data: 00 F0 3A F8 0A A0 90 E8 00 0C 82 44 83 44 AA F1 ... +T3F74 26219:556.241 - 0.070ms returns 60 (0x3C) +T3F74 26219:556.258 JLINK_ReadMemEx(0x08000134, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:556.275 -- Read from C cache (2 bytes @ 0x08000134) +T3F74 26219:556.298 Data: 00 F0 +T3F74 26219:556.320 - 0.069ms returns 2 (0x2) +T3F74 26219:556.338 JLINK_ReadMemEx(0x08000136, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:556.355 -- Read from C cache (2 bytes @ 0x08000136) +T3F74 26219:556.377 Data: 3A F8 +T3F74 26219:556.399 - 0.069ms returns 2 (0x2) +T3F74 26219:556.417 JLINK_ReadMemEx(0x08000138, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:556.434 -- Read from C cache (60 bytes @ 0x08000138) +T3F74 26219:556.458 Data: 0A A0 90 E8 00 0C 82 44 83 44 AA F1 01 07 DA 45 ... +T3F74 26219:556.480 - 0.070ms returns 60 (0x3C) +T3F74 26219:556.498 JLINK_ReadMemEx(0x08000138, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:556.589 -- Read from C cache (2 bytes @ 0x08000138) +T3F74 26219:556.615 Data: 0A A0 +T3F74 26219:556.638 - 0.148ms returns 2 (0x2) +T3F74 26219:556.657 JLINK_ReadMemEx(0x0800013A, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:556.674 -- Read from C cache (2 bytes @ 0x0800013A) +T3F74 26219:556.697 Data: 90 E8 +T3F74 26219:556.721 - 0.074ms returns 2 (0x2) +T3F74 26219:556.742 JLINK_ReadMemEx(0x0800013A, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:556.759 -- Read from C cache (2 bytes @ 0x0800013A) +T3F74 26219:556.782 Data: 90 E8 +T3F74 26219:556.804 - 0.070ms returns 2 (0x2) +T3F74 26219:556.829 JLINK_ReadMemEx(0x0800013C, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:556.843 -- Read from C cache (60 bytes @ 0x0800013C) +T3F74 26219:556.863 Data: 00 0C 82 44 83 44 AA F1 01 07 DA 45 01 D1 00 F0 ... +T3F74 26219:556.882 - 0.060ms returns 60 (0x3C) +T3F74 26219:556.898 JLINK_ReadMemEx(0x0800013C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:556.912 -- Read from C cache (2 bytes @ 0x0800013C) +T3F74 26219:556.931 Data: 00 0C +T3F74 26219:556.950 - 0.059ms returns 2 (0x2) +T3F74 26219:556.966 JLINK_ReadMemEx(0x0800013E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:556.981 -- Read from C cache (2 bytes @ 0x0800013E) +T3F74 26219:557.000 Data: 82 44 +T3F74 26219:557.019 - 0.059ms returns 2 (0x2) +T3F74 26219:557.035 JLINK_ReadMemEx(0x08000140, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:557.049 -- Read from C cache (60 bytes @ 0x08000140) +T3F74 26219:557.069 Data: 83 44 AA F1 01 07 DA 45 01 D1 00 F0 2F F8 AF F2 ... +T3F74 26219:557.088 - 0.060ms returns 60 (0x3C) +T3F74 26219:557.103 JLINK_ReadMemEx(0x08000140, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:557.118 -- Read from C cache (2 bytes @ 0x08000140) +T3F74 26219:557.137 Data: 83 44 +T3F74 26219:557.156 - 0.059ms returns 2 (0x2) +T3F74 26219:557.172 JLINK_ReadMemEx(0x08000140, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:557.186 -- Read from C cache (60 bytes @ 0x08000140) +T3F74 26219:557.207 Data: 83 44 AA F1 01 07 DA 45 01 D1 00 F0 2F F8 AF F2 ... +T3F74 26219:557.225 - 0.060ms returns 60 (0x3C) +T3F74 26219:557.241 JLINK_ReadMemEx(0x08000140, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:557.256 -- Read from C cache (2 bytes @ 0x08000140) +T3F74 26219:557.275 Data: 83 44 +T3F74 26219:557.294 - 0.059ms returns 2 (0x2) +T3F74 26219:557.309 JLINK_ReadMemEx(0x08000142, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:557.324 -- Read from C cache (2 bytes @ 0x08000142) +T3F74 26219:557.343 Data: AA F1 +T3F74 26219:557.362 - 0.059ms returns 2 (0x2) +T3F74 26219:557.377 JLINK_ReadMemEx(0x08000142, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:557.392 -- Read from C cache (2 bytes @ 0x08000142) +T3F74 26219:557.411 Data: AA F1 +T3F74 26219:557.430 - 0.059ms returns 2 (0x2) +T3F74 26219:557.445 JLINK_ReadMemEx(0x08000144, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:557.468 -- Read from C cache (60 bytes @ 0x08000144) +T3F74 26219:557.488 Data: 01 07 DA 45 01 D1 00 F0 2F F8 AF F2 09 0E BA E8 ... +T3F74 26219:557.508 - 0.069ms returns 60 (0x3C) +T3F74 26219:557.524 JLINK_ReadMemEx(0x08000144, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:557.538 -- Read from C cache (2 bytes @ 0x08000144) +T3F74 26219:557.557 Data: 01 07 +T3F74 26219:557.576 - 0.059ms returns 2 (0x2) +T3F74 26219:557.592 JLINK_ReadMemEx(0x08000146, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:557.606 -- Read from C cache (2 bytes @ 0x08000146) +T3F74 26219:557.625 Data: DA 45 +T3F74 26219:557.644 - 0.059ms returns 2 (0x2) +T3F74 26219:557.659 JLINK_ReadMemEx(0x08000148, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:557.676 CPU_ReadMem(64 bytes @ 0x08000180) +T3F74 26219:559.282 -- Updating C cache (64 bytes @ 0x08000180) +T3F74 26219:559.304 -- Read from C cache (60 bytes @ 0x08000148) +T3F74 26219:559.325 Data: 01 D1 00 F0 2F F8 AF F2 09 0E BA E8 0F 00 13 F0 ... +T3F74 26219:559.344 - 1.690ms returns 60 (0x3C) +T3F74 26219:559.360 JLINK_ReadMemEx(0x08000148, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:559.375 -- Read from C cache (2 bytes @ 0x08000148) +T3F74 26219:559.443 Data: 01 D1 +T3F74 26219:559.463 - 0.109ms returns 2 (0x2) +T3F74 26219:559.479 JLINK_ReadMemEx(0x08000148, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:559.494 -- Read from C cache (60 bytes @ 0x08000148) +T3F74 26219:559.514 Data: 01 D1 00 F0 2F F8 AF F2 09 0E BA E8 0F 00 13 F0 ... +T3F74 26219:559.533 - 0.060ms returns 60 (0x3C) +T3F74 26219:559.548 JLINK_ReadMemEx(0x08000148, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:559.563 -- Read from C cache (2 bytes @ 0x08000148) +T3F74 26219:559.582 Data: 01 D1 +T3F74 26219:559.601 - 0.059ms returns 2 (0x2) +T3F74 26219:559.617 JLINK_ReadMemEx(0x0800014A, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:559.631 -- Read from C cache (2 bytes @ 0x0800014A) +T3F74 26219:559.651 Data: 00 F0 +T3F74 26219:559.669 - 0.059ms returns 2 (0x2) +T3F74 26219:559.685 JLINK_ReadMemEx(0x0800014A, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:559.700 -- Read from C cache (2 bytes @ 0x0800014A) +T3F74 26219:559.719 Data: 00 F0 +T3F74 26219:559.738 - 0.059ms returns 2 (0x2) +T3F74 26219:559.753 JLINK_ReadMemEx(0x0800014C, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:559.768 -- Read from C cache (60 bytes @ 0x0800014C) +T3F74 26219:559.788 Data: 2F F8 AF F2 09 0E BA E8 0F 00 13 F0 01 0F 18 BF ... +T3F74 26219:559.807 - 0.060ms returns 60 (0x3C) +T3F74 26219:559.822 JLINK_ReadMemEx(0x0800014C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:559.837 -- Read from C cache (2 bytes @ 0x0800014C) +T3F74 26219:559.856 Data: 2F F8 +T3F74 26219:559.875 - 0.059ms returns 2 (0x2) +T3F74 26219:559.891 JLINK_ReadMemEx(0x0800014E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:559.905 -- Read from C cache (2 bytes @ 0x0800014E) +T3F74 26219:559.924 Data: AF F2 +T3F74 26219:559.943 - 0.059ms returns 2 (0x2) +T3F74 26219:559.958 JLINK_ReadMemEx(0x08000150, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:559.972 -- Read from C cache (60 bytes @ 0x08000150) +T3F74 26219:559.993 Data: 09 0E BA E8 0F 00 13 F0 01 0F 18 BF FB 1A 43 F0 ... +T3F74 26219:560.011 - 0.059ms returns 60 (0x3C) +T3F74 26219:560.027 JLINK_ReadMemEx(0x08000150, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:560.041 -- Read from C cache (2 bytes @ 0x08000150) +T3F74 26219:560.060 Data: 09 0E +T3F74 26219:560.079 - 0.059ms returns 2 (0x2) +T3F74 26219:560.095 JLINK_ReadMemEx(0x08000152, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:560.109 -- Read from C cache (2 bytes @ 0x08000152) +T3F74 26219:560.128 Data: BA E8 +T3F74 26219:560.147 - 0.059ms returns 2 (0x2) +T3F74 26219:560.163 JLINK_ReadMemEx(0x08000154, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:560.177 -- Read from C cache (60 bytes @ 0x08000154) +T3F74 26219:560.197 Data: 0F 00 13 F0 01 0F 18 BF FB 1A 43 F0 01 03 18 47 ... +T3F74 26219:560.216 - 0.060ms returns 60 (0x3C) +T3F74 26219:560.231 JLINK_ReadMemEx(0x08000154, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:560.245 -- Read from C cache (2 bytes @ 0x08000154) +T3F74 26219:560.269 Data: 0F 00 +T3F74 26219:560.288 - 0.064ms returns 2 (0x2) +T3F74 26219:560.304 JLINK_ReadMemEx(0x08000156, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:560.319 -- Read from C cache (2 bytes @ 0x08000156) +T3F74 26219:560.338 Data: 13 F0 +T3F74 26219:560.357 - 0.059ms returns 2 (0x2) +T3F74 26219:560.372 JLINK_ReadMemEx(0x08000158, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:560.386 -- Read from C cache (60 bytes @ 0x08000158) +T3F74 26219:560.407 Data: 01 0F 18 BF FB 1A 43 F0 01 03 18 47 1C 27 00 00 ... +T3F74 26219:560.425 - 0.060ms returns 60 (0x3C) +T3F74 26219:560.441 JLINK_ReadMemEx(0x08000158, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:560.455 -- Read from C cache (2 bytes @ 0x08000158) +T3F74 26219:560.474 Data: 01 0F +T3F74 26219:560.493 - 0.059ms returns 2 (0x2) +T3F74 26219:560.508 JLINK_ReadMemEx(0x0800015A, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:560.523 -- Read from C cache (2 bytes @ 0x0800015A) +T3F74 26219:560.542 Data: 18 BF +T3F74 26219:560.561 - 0.059ms returns 2 (0x2) +T3F74 26219:560.576 JLINK_ReadMemEx(0x0800015C, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:560.597 -- Read from C cache (60 bytes @ 0x0800015C) +T3F74 26219:560.618 Data: FB 1A 43 F0 01 03 18 47 1C 27 00 00 3C 27 00 00 ... +T3F74 26219:560.636 - 0.066ms returns 60 (0x3C) +T3F74 26219:560.652 JLINK_ReadMemEx(0x0800015C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:560.666 -- Read from C cache (2 bytes @ 0x0800015C) +T3F74 26219:560.685 Data: FB 1A +T3F74 26219:560.704 - 0.059ms returns 2 (0x2) +T3F74 26219:560.720 JLINK_ReadMemEx(0x0800015C, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:560.735 -- Read from C cache (60 bytes @ 0x0800015C) +T3F74 26219:560.755 Data: FB 1A 43 F0 01 03 18 47 1C 27 00 00 3C 27 00 00 ... +T3F74 26219:560.774 - 0.060ms returns 60 (0x3C) +T3F74 26219:560.789 JLINK_ReadMemEx(0x0800015C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:560.803 -- Read from C cache (2 bytes @ 0x0800015C) +T3F74 26219:560.823 Data: FB 1A +T3F74 26219:560.842 - 0.059ms returns 2 (0x2) +T3F74 26219:560.857 JLINK_ReadMemEx(0x0800015E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:560.871 -- Read from C cache (2 bytes @ 0x0800015E) +T3F74 26219:560.890 Data: 43 F0 +T3F74 26219:560.909 - 0.059ms returns 2 (0x2) +T3F74 26219:560.925 JLINK_ReadMemEx(0x0800015E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:560.939 -- Read from C cache (2 bytes @ 0x0800015E) +T3F74 26219:560.959 Data: 43 F0 +T3F74 26219:560.978 - 0.059ms returns 2 (0x2) +T3F74 26219:560.993 JLINK_ReadMemEx(0x08000160, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:561.007 -- Read from C cache (60 bytes @ 0x08000160) +T3F74 26219:561.027 Data: 01 03 18 47 1C 27 00 00 3C 27 00 00 10 3A 24 BF ... +T3F74 26219:561.046 - 0.059ms returns 60 (0x3C) +T3F74 26219:561.061 JLINK_ReadMemEx(0x08000160, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:561.076 -- Read from C cache (2 bytes @ 0x08000160) +T3F74 26219:561.095 Data: 01 03 +T3F74 26219:561.114 - 0.059ms returns 2 (0x2) +T3F74 26219:561.129 JLINK_ReadMemEx(0x08000162, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:561.144 -- Read from C cache (2 bytes @ 0x08000162) +T3F74 26219:561.163 Data: 18 47 +T3F74 26219:561.182 - 0.059ms returns 2 (0x2) +T3F74 26219:561.198 JLINK_ReadMemEx(0x08000164, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:561.217 -- Read from C cache (60 bytes @ 0x08000164) +T3F74 26219:561.237 Data: 1C 27 00 00 3C 27 00 00 10 3A 24 BF 78 C8 78 C1 ... +T3F74 26219:561.259 - 0.069ms returns 60 (0x3C) +T3F74 26219:561.276 JLINK_ReadMemEx(0x08000164, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:561.290 -- Read from C cache (2 bytes @ 0x08000164) +T3F74 26219:561.309 Data: 1C 27 +T3F74 26219:561.328 - 0.059ms returns 2 (0x2) +T3F74 26219:561.344 JLINK_ReadMemEx(0x0800016C, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:561.359 -- Read from C cache (60 bytes @ 0x0800016C) +T3F74 26219:561.379 Data: 10 3A 24 BF 78 C8 78 C1 FA D8 52 07 24 BF 30 C8 ... +T3F74 26219:561.398 - 0.060ms returns 60 (0x3C) +T3F74 26219:561.413 JLINK_ReadMemEx(0x0800016C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:561.428 -- Read from C cache (2 bytes @ 0x0800016C) +T3F74 26219:561.447 Data: 10 3A +T3F74 26219:561.466 - 0.059ms returns 2 (0x2) +T3F74 26219:561.482 JLINK_ReadMemEx(0x0800016E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:561.496 -- Read from C cache (2 bytes @ 0x0800016E) +T3F74 26219:561.515 Data: 24 BF +T3F74 26219:561.534 - 0.059ms returns 2 (0x2) +T3F74 26219:561.550 JLINK_ReadMemEx(0x0800016E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:561.564 -- Read from C cache (2 bytes @ 0x0800016E) +T3F74 26219:561.584 Data: 24 BF +T3F74 26219:561.602 - 0.059ms returns 2 (0x2) +T3F74 26219:561.618 JLINK_ReadMemEx(0x08000170, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:561.632 -- Read from C cache (60 bytes @ 0x08000170) +T3F74 26219:561.652 Data: 78 C8 78 C1 FA D8 52 07 24 BF 30 C8 30 C1 44 BF ... +T3F74 26219:561.671 - 0.060ms returns 60 (0x3C) +T3F74 26219:561.688 JLINK_ReadMemEx(0x08000170, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:561.702 -- Read from C cache (2 bytes @ 0x08000170) +T3F74 26219:561.728 Data: 78 C8 +T3F74 26219:561.747 - 0.065ms returns 2 (0x2) +T3F74 26219:561.763 JLINK_ReadMemEx(0x08000170, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:561.778 -- Read from C cache (60 bytes @ 0x08000170) +T3F74 26219:561.798 Data: 78 C8 78 C1 FA D8 52 07 24 BF 30 C8 30 C1 44 BF ... +T3F74 26219:561.816 - 0.059ms returns 60 (0x3C) +T3F74 26219:561.832 JLINK_ReadMemEx(0x08000170, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:561.846 -- Read from C cache (2 bytes @ 0x08000170) +T3F74 26219:561.865 Data: 78 C8 +T3F74 26219:561.884 - 0.059ms returns 2 (0x2) +T3F74 26219:561.900 JLINK_ReadMemEx(0x08000172, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:561.914 -- Read from C cache (2 bytes @ 0x08000172) +T3F74 26219:561.933 Data: 78 C1 +T3F74 26219:561.952 - 0.059ms returns 2 (0x2) +T3F74 26219:561.968 JLINK_ReadMemEx(0x08000172, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:561.982 -- Read from C cache (2 bytes @ 0x08000172) +T3F74 26219:562.002 Data: 78 C1 +T3F74 26219:562.021 - 0.059ms returns 2 (0x2) +T3F74 26219:562.036 JLINK_ReadMemEx(0x08000174, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:562.051 -- Read from C cache (60 bytes @ 0x08000174) +T3F74 26219:562.071 Data: FA D8 52 07 24 BF 30 C8 30 C1 44 BF 04 68 0C 60 ... +T3F74 26219:562.089 - 0.059ms returns 60 (0x3C) +T3F74 26219:562.105 JLINK_ReadMemEx(0x08000174, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:562.119 -- Read from C cache (2 bytes @ 0x08000174) +T3F74 26219:562.138 Data: FA D8 +T3F74 26219:562.157 - 0.059ms returns 2 (0x2) +T3F74 26219:562.173 JLINK_ReadMemEx(0x08000174, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:562.187 -- Read from C cache (60 bytes @ 0x08000174) +T3F74 26219:562.207 Data: FA D8 52 07 24 BF 30 C8 30 C1 44 BF 04 68 0C 60 ... +T3F74 26219:562.226 - 0.059ms returns 60 (0x3C) +T3F74 26219:562.241 JLINK_ReadMemEx(0x08000174, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:562.257 -- Read from C cache (2 bytes @ 0x08000174) +T3F74 26219:562.277 Data: FA D8 +T3F74 26219:562.296 - 0.061ms returns 2 (0x2) +T3F74 26219:562.312 JLINK_ReadMemEx(0x08000176, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:562.326 -- Read from C cache (2 bytes @ 0x08000176) +T3F74 26219:562.345 Data: 52 07 +T3F74 26219:562.364 - 0.059ms returns 2 (0x2) +T3F74 26219:562.380 JLINK_ReadMemEx(0x08000176, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:562.394 -- Read from C cache (2 bytes @ 0x08000176) +T3F74 26219:562.414 Data: 52 07 +T3F74 26219:562.433 - 0.059ms returns 2 (0x2) +T3F74 26219:562.448 JLINK_ReadMemEx(0x08000178, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:562.462 -- Read from C cache (60 bytes @ 0x08000178) +T3F74 26219:562.482 Data: 24 BF 30 C8 30 C1 44 BF 04 68 0C 60 70 47 00 00 ... +T3F74 26219:562.501 - 0.059ms returns 60 (0x3C) +T3F74 26219:562.516 JLINK_ReadMemEx(0x08000178, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:562.531 -- Read from C cache (2 bytes @ 0x08000178) +T3F74 26219:562.550 Data: 24 BF +T3F74 26219:562.569 - 0.059ms returns 2 (0x2) +T3F74 26219:562.585 JLINK_ReadMemEx(0x08000178, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:562.600 -- Read from C cache (60 bytes @ 0x08000178) +T3F74 26219:562.620 Data: 24 BF 30 C8 30 C1 44 BF 04 68 0C 60 70 47 00 00 ... +T3F74 26219:562.638 - 0.059ms returns 60 (0x3C) +T3F74 26219:562.654 JLINK_ReadMemEx(0x08000178, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:562.668 -- Read from C cache (2 bytes @ 0x08000178) +T3F74 26219:562.688 Data: 24 BF +T3F74 26219:562.707 - 0.059ms returns 2 (0x2) +T3F74 26219:562.722 JLINK_ReadMemEx(0x0800017A, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:562.737 -- Read from C cache (2 bytes @ 0x0800017A) +T3F74 26219:562.756 Data: 30 C8 +T3F74 26219:562.775 - 0.059ms returns 2 (0x2) +T3F74 26219:562.790 JLINK_ReadMemEx(0x0800017A, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:562.805 -- Read from C cache (2 bytes @ 0x0800017A) +T3F74 26219:562.824 Data: 30 C8 +T3F74 26219:562.843 - 0.059ms returns 2 (0x2) +T3F74 26219:562.858 JLINK_ReadMemEx(0x0800017C, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:562.878 -- Read from C cache (60 bytes @ 0x0800017C) +T3F74 26219:562.899 Data: 30 C1 44 BF 04 68 0C 60 70 47 00 00 00 23 00 24 ... +T3F74 26219:562.918 - 0.066ms returns 60 (0x3C) +T3F74 26219:562.933 JLINK_ReadMemEx(0x0800017C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:562.948 -- Read from C cache (2 bytes @ 0x0800017C) +T3F74 26219:562.967 Data: 30 C1 +T3F74 26219:562.986 - 0.059ms returns 2 (0x2) +T3F74 26219:563.002 JLINK_ReadMemEx(0x0800017C, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:563.016 -- Read from C cache (60 bytes @ 0x0800017C) +T3F74 26219:563.036 Data: 30 C1 44 BF 04 68 0C 60 70 47 00 00 00 23 00 24 ... +T3F74 26219:563.055 - 0.059ms returns 60 (0x3C) +T3F74 26219:563.070 JLINK_ReadMemEx(0x0800017C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:563.084 -- Read from C cache (2 bytes @ 0x0800017C) +T3F74 26219:563.103 Data: 30 C1 +T3F74 26219:563.122 - 0.059ms returns 2 (0x2) +T3F74 26219:563.138 JLINK_ReadMemEx(0x0800017E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:563.152 -- Read from C cache (2 bytes @ 0x0800017E) +T3F74 26219:563.171 Data: 44 BF +T3F74 26219:563.190 - 0.059ms returns 2 (0x2) +T3F74 26219:563.206 JLINK_ReadMemEx(0x0800017E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:563.220 -- Read from C cache (2 bytes @ 0x0800017E) +T3F74 26219:563.240 Data: 44 BF +T3F74 26219:563.259 - 0.061ms returns 2 (0x2) +T3F74 26219:563.276 JLINK_ReadMemEx(0x08000180, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:563.290 -- Read from C cache (60 bytes @ 0x08000180) +T3F74 26219:563.310 Data: 04 68 0C 60 70 47 00 00 00 23 00 24 00 25 00 26 ... +T3F74 26219:563.329 - 0.059ms returns 60 (0x3C) +T3F74 26219:563.344 JLINK_ReadMemEx(0x08000180, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:563.359 -- Read from C cache (2 bytes @ 0x08000180) +T3F74 26219:563.378 Data: 04 68 +T3F74 26219:563.397 - 0.059ms returns 2 (0x2) +T3F74 26219:563.412 JLINK_ReadMemEx(0x08000180, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:563.427 -- Read from C cache (60 bytes @ 0x08000180) +T3F74 26219:563.447 Data: 04 68 0C 60 70 47 00 00 00 23 00 24 00 25 00 26 ... +T3F74 26219:563.466 - 0.060ms returns 60 (0x3C) +T3F74 26219:563.481 JLINK_ReadMemEx(0x08000180, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:563.496 -- Read from C cache (2 bytes @ 0x08000180) +T3F74 26219:563.515 Data: 04 68 +T3F74 26219:563.534 - 0.059ms returns 2 (0x2) +T3F74 26219:563.549 JLINK_ReadMemEx(0x08000182, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:563.564 -- Read from C cache (2 bytes @ 0x08000182) +T3F74 26219:563.583 Data: 0C 60 +T3F74 26219:563.602 - 0.059ms returns 2 (0x2) +T3F74 26219:563.618 JLINK_ReadMemEx(0x08000182, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:563.632 -- Read from C cache (2 bytes @ 0x08000182) +T3F74 26219:563.651 Data: 0C 60 +T3F74 26219:563.670 - 0.062ms returns 2 (0x2) +T3F74 26219:563.689 JLINK_ReadMemEx(0x08000184, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:563.703 -- Read from C cache (60 bytes @ 0x08000184) +T3F74 26219:563.723 Data: 70 47 00 00 00 23 00 24 00 25 00 26 10 3A 28 BF ... +T3F74 26219:563.742 - 0.059ms returns 60 (0x3C) +T3F74 26219:563.757 JLINK_ReadMemEx(0x08000184, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:563.772 -- Read from C cache (2 bytes @ 0x08000184) +T3F74 26219:563.791 Data: 70 47 +T3F74 26219:563.810 - 0.059ms returns 2 (0x2) +T3F74 26219:563.825 JLINK_ReadMemEx(0x08000184, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:563.840 -- Read from C cache (60 bytes @ 0x08000184) +T3F74 26219:563.860 Data: 70 47 00 00 00 23 00 24 00 25 00 26 10 3A 28 BF ... +T3F74 26219:563.879 - 0.060ms returns 60 (0x3C) +T3F74 26219:563.894 JLINK_ReadMemEx(0x08000184, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:563.909 -- Read from C cache (2 bytes @ 0x08000184) +T3F74 26219:563.928 Data: 70 47 +T3F74 26219:563.947 - 0.059ms returns 2 (0x2) +T3F74 26219:563.962 JLINK_ReadMemEx(0x08000186, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:563.977 -- Read from C cache (2 bytes @ 0x08000186) +T3F74 26219:564.002 Data: 00 00 +T3F74 26219:564.021 - 0.065ms returns 2 (0x2) +T3F74 26219:564.036 JLINK_ReadMemEx(0x08000186, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:564.051 -- Read from C cache (2 bytes @ 0x08000186) +T3F74 26219:564.070 Data: 00 00 +T3F74 26219:564.089 - 0.059ms returns 2 (0x2) +T3F74 26219:564.105 JLINK_ReadMemEx(0x08000188, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:564.120 CPU_ReadMem(64 bytes @ 0x080001C0) +T3F74 26219:565.747 -- Updating C cache (64 bytes @ 0x080001C0) +T3F74 26219:565.780 -- Read from C cache (60 bytes @ 0x08000188) +T3F74 26219:565.805 Data: 00 23 00 24 00 25 00 26 10 3A 28 BF 78 C1 FB D8 ... +T3F74 26219:565.827 - 1.730ms returns 60 (0x3C) +T3F74 26219:565.848 JLINK_ReadMemEx(0x08000188, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:565.867 -- Read from C cache (2 bytes @ 0x08000188) +T3F74 26219:565.890 Data: 00 23 +T3F74 26219:565.912 - 0.072ms returns 2 (0x2) +T3F74 26219:565.932 JLINK_ReadMemEx(0x08000188, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:565.950 -- Read from C cache (60 bytes @ 0x08000188) +T3F74 26219:565.973 Data: 00 23 00 24 00 25 00 26 10 3A 28 BF 78 C1 FB D8 ... +T3F74 26219:565.995 - 0.070ms returns 60 (0x3C) +T3F74 26219:566.013 JLINK_ReadMemEx(0x08000188, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:566.030 -- Read from C cache (2 bytes @ 0x08000188) +T3F74 26219:566.053 Data: 00 23 +T3F74 26219:566.078 - 0.072ms returns 2 (0x2) +T3F74 26219:566.096 JLINK_ReadMemEx(0x0800018A, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:566.113 -- Read from C cache (2 bytes @ 0x0800018A) +T3F74 26219:566.136 Data: 00 24 +T3F74 26219:566.160 - 0.072ms returns 2 (0x2) +T3F74 26219:566.178 JLINK_ReadMemEx(0x0800018A, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:566.195 -- Read from C cache (2 bytes @ 0x0800018A) +T3F74 26219:566.218 Data: 00 24 +T3F74 26219:566.240 - 0.069ms returns 2 (0x2) +T3F74 26219:566.258 JLINK_ReadMemEx(0x0800018C, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:566.275 -- Read from C cache (60 bytes @ 0x0800018C) +T3F74 26219:566.299 Data: 00 25 00 26 10 3A 28 BF 78 C1 FB D8 52 07 28 BF ... +T3F74 26219:566.320 - 0.070ms returns 60 (0x3C) +T3F74 26219:566.338 JLINK_ReadMemEx(0x0800018C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:566.355 -- Read from C cache (2 bytes @ 0x0800018C) +T3F74 26219:566.378 Data: 00 25 +T3F74 26219:566.400 - 0.069ms returns 2 (0x2) +T3F74 26219:566.418 JLINK_ReadMemEx(0x0800018C, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:566.435 -- Read from C cache (60 bytes @ 0x0800018C) +T3F74 26219:566.459 Data: 00 25 00 26 10 3A 28 BF 78 C1 FB D8 52 07 28 BF ... +T3F74 26219:566.481 - 0.070ms returns 60 (0x3C) +T3F74 26219:566.499 JLINK_ReadMemEx(0x0800018C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:566.515 -- Read from C cache (2 bytes @ 0x0800018C) +T3F74 26219:566.543 Data: 00 25 +T3F74 26219:566.565 - 0.074ms returns 2 (0x2) +T3F74 26219:566.585 JLINK_ReadMemEx(0x0800018E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:566.602 -- Read from C cache (2 bytes @ 0x0800018E) +T3F74 26219:566.625 Data: 00 26 +T3F74 26219:566.647 - 0.069ms returns 2 (0x2) +T3F74 26219:566.665 JLINK_ReadMemEx(0x0800018E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:566.682 -- Read from C cache (2 bytes @ 0x0800018E) +T3F74 26219:566.705 Data: 00 26 +T3F74 26219:566.727 - 0.069ms returns 2 (0x2) +T3F74 26219:566.745 JLINK_ReadMemEx(0x08000190, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:566.763 -- Read from C cache (60 bytes @ 0x08000190) +T3F74 26219:566.786 Data: 10 3A 28 BF 78 C1 FB D8 52 07 28 BF 30 C1 48 BF ... +T3F74 26219:566.808 - 0.071ms returns 60 (0x3C) +T3F74 26219:566.826 JLINK_ReadMemEx(0x08000190, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:566.843 -- Read from C cache (2 bytes @ 0x08000190) +T3F74 26219:566.871 Data: 10 3A +T3F74 26219:566.890 - 0.070ms returns 2 (0x2) +T3F74 26219:566.905 JLINK_ReadMemEx(0x08000190, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:566.920 -- Read from C cache (60 bytes @ 0x08000190) +T3F74 26219:566.950 Data: 10 3A 28 BF 78 C1 FB D8 52 07 28 BF 30 C1 48 BF ... +T3F74 26219:566.969 - 0.070ms returns 60 (0x3C) +T3F74 26219:566.985 JLINK_ReadMemEx(0x08000190, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:566.999 -- Read from C cache (2 bytes @ 0x08000190) +T3F74 26219:567.018 Data: 10 3A +T3F74 26219:567.037 - 0.059ms returns 2 (0x2) +T3F74 26219:567.053 JLINK_ReadMemEx(0x08000192, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:567.067 -- Read from C cache (2 bytes @ 0x08000192) +T3F74 26219:567.086 Data: 28 BF +T3F74 26219:567.105 - 0.059ms returns 2 (0x2) +T3F74 26219:567.121 JLINK_ReadMemEx(0x08000192, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:567.135 -- Read from C cache (2 bytes @ 0x08000192) +T3F74 26219:567.155 Data: 28 BF +T3F74 26219:567.173 - 0.059ms returns 2 (0x2) +T3F74 26219:567.189 JLINK_ReadMemEx(0x08000194, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:567.203 -- Read from C cache (60 bytes @ 0x08000194) +T3F74 26219:567.223 Data: 78 C1 FB D8 52 07 28 BF 30 C1 48 BF 0B 60 70 47 ... +T3F74 26219:567.242 - 0.060ms returns 60 (0x3C) +T3F74 26219:567.257 JLINK_ReadMemEx(0x08000194, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:567.272 -- Read from C cache (2 bytes @ 0x08000194) +T3F74 26219:567.291 Data: 78 C1 +T3F74 26219:567.310 - 0.059ms returns 2 (0x2) +T3F74 26219:567.325 JLINK_ReadMemEx(0x08000194, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:567.340 -- Read from C cache (60 bytes @ 0x08000194) +T3F74 26219:567.360 Data: 78 C1 FB D8 52 07 28 BF 30 C1 48 BF 0B 60 70 47 ... +T3F74 26219:567.379 - 0.059ms returns 60 (0x3C) +T3F74 26219:567.394 JLINK_ReadMemEx(0x08000194, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:567.408 -- Read from C cache (2 bytes @ 0x08000194) +T3F74 26219:567.428 Data: 78 C1 +T3F74 26219:567.447 - 0.059ms returns 2 (0x2) +T3F74 26219:567.462 JLINK_ReadMemEx(0x08000196, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:567.476 -- Read from C cache (2 bytes @ 0x08000196) +T3F74 26219:567.496 Data: FB D8 +T3F74 26219:567.515 - 0.069ms returns 2 (0x2) +T3F74 26219:567.540 JLINK_ReadMemEx(0x08000196, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:567.555 -- Read from C cache (2 bytes @ 0x08000196) +T3F74 26219:567.576 Data: FB D8 +T3F74 26219:567.596 - 0.062ms returns 2 (0x2) +T3F74 26219:567.612 JLINK_ReadMemEx(0x08000198, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:567.626 -- Read from C cache (60 bytes @ 0x08000198) +T3F74 26219:567.646 Data: 52 07 28 BF 30 C1 48 BF 0B 60 70 47 1F B5 1F BD ... +T3F74 26219:567.665 - 0.059ms returns 60 (0x3C) +T3F74 26219:567.680 JLINK_ReadMemEx(0x08000198, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:567.694 -- Read from C cache (2 bytes @ 0x08000198) +T3F74 26219:567.714 Data: 52 07 +T3F74 26219:567.732 - 0.059ms returns 2 (0x2) +T3F74 26219:567.748 JLINK_ReadMemEx(0x08000198, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:567.763 -- Read from C cache (60 bytes @ 0x08000198) +T3F74 26219:567.782 Data: 52 07 28 BF 30 C1 48 BF 0B 60 70 47 1F B5 1F BD ... +T3F74 26219:567.801 - 0.059ms returns 60 (0x3C) +T3F74 26219:567.816 JLINK_ReadMemEx(0x08000198, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:567.831 -- Read from C cache (2 bytes @ 0x08000198) +T3F74 26219:567.850 Data: 52 07 +T3F74 26219:567.869 - 0.058ms returns 2 (0x2) +T3F74 26219:567.884 JLINK_ReadMemEx(0x0800019A, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:567.898 -- Read from C cache (2 bytes @ 0x0800019A) +T3F74 26219:567.918 Data: 28 BF +T3F74 26219:567.936 - 0.059ms returns 2 (0x2) +T3F74 26219:567.952 JLINK_ReadMemEx(0x0800019A, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:567.966 -- Read from C cache (2 bytes @ 0x0800019A) +T3F74 26219:567.985 Data: 28 BF +T3F74 26219:568.007 - 0.061ms returns 2 (0x2) +T3F74 26219:568.022 JLINK_ReadMemEx(0x0800019C, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:568.036 -- Read from C cache (60 bytes @ 0x0800019C) +T3F74 26219:568.056 Data: 30 C1 48 BF 0B 60 70 47 1F B5 1F BD 10 B5 10 BD ... +T3F74 26219:568.075 - 0.059ms returns 60 (0x3C) +T3F74 26219:568.090 JLINK_ReadMemEx(0x0800019C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:568.110 -- Read from C cache (2 bytes @ 0x0800019C) +T3F74 26219:568.130 Data: 30 C1 +T3F74 26219:568.148 - 0.065ms returns 2 (0x2) +T3F74 26219:568.164 JLINK_ReadMemEx(0x0800019C, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:568.179 -- Read from C cache (60 bytes @ 0x0800019C) +T3F74 26219:568.198 Data: 30 C1 48 BF 0B 60 70 47 1F B5 1F BD 10 B5 10 BD ... +T3F74 26219:568.217 - 0.059ms returns 60 (0x3C) +T3F74 26219:568.232 JLINK_ReadMemEx(0x0800019C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:568.247 -- Read from C cache (2 bytes @ 0x0800019C) +T3F74 26219:568.266 Data: 30 C1 +T3F74 26219:568.285 - 0.059ms returns 2 (0x2) +T3F74 26219:568.300 JLINK_ReadMemEx(0x0800019E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:568.314 -- Read from C cache (2 bytes @ 0x0800019E) +T3F74 26219:568.333 Data: 48 BF +T3F74 26219:568.352 - 0.058ms returns 2 (0x2) +T3F74 26219:568.368 JLINK_ReadMemEx(0x0800019E, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:568.382 -- Read from C cache (2 bytes @ 0x0800019E) +T3F74 26219:568.401 Data: 48 BF +T3F74 26219:568.420 - 0.058ms returns 2 (0x2) +T3F74 26219:568.435 JLINK_ReadMemEx(0x080001A0, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:568.449 -- Read from C cache (60 bytes @ 0x080001A0) +T3F74 26219:568.477 Data: 0B 60 70 47 1F B5 1F BD 10 B5 10 BD 00 F0 6B F8 ... +T3F74 26219:568.496 - 0.067ms returns 60 (0x3C) +T3F74 26219:568.511 JLINK_ReadMemEx(0x080001A0, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:568.534 -- Read from C cache (2 bytes @ 0x080001A0) +T3F74 26219:568.553 Data: 0B 60 +T3F74 26219:568.580 - 0.076ms returns 2 (0x2) +T3F74 26219:568.600 JLINK_ReadMemEx(0x080001A0, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:568.617 -- Read from C cache (60 bytes @ 0x080001A0) +T3F74 26219:568.641 Data: 0B 60 70 47 1F B5 1F BD 10 B5 10 BD 00 F0 6B F8 ... +T3F74 26219:568.662 - 0.069ms returns 60 (0x3C) +T3F74 26219:568.680 JLINK_ReadMemEx(0x080001A0, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:568.700 -- Read from C cache (2 bytes @ 0x080001A0) +T3F74 26219:568.723 Data: 0B 60 +T3F74 26219:568.745 - 0.072ms returns 2 (0x2) +T3F74 26219:568.763 JLINK_ReadMemEx(0x080001A2, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:568.779 -- Read from C cache (2 bytes @ 0x080001A2) +T3F74 26219:568.802 Data: 70 47 +T3F74 26219:568.824 - 0.068ms returns 2 (0x2) +T3F74 26219:568.842 JLINK_ReadMemEx(0x080001A2, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:568.859 -- Read from C cache (2 bytes @ 0x080001A2) +T3F74 26219:568.881 Data: 70 47 +T3F74 26219:568.903 - 0.069ms returns 2 (0x2) +T3F74 26219:568.921 JLINK_ReadMemEx(0x080001A4, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:568.938 -- Read from C cache (60 bytes @ 0x080001A4) +T3F74 26219:568.961 Data: 1F B5 1F BD 10 B5 10 BD 00 F0 6B F8 11 46 FF F7 ... +T3F74 26219:568.983 - 0.069ms returns 60 (0x3C) +T3F74 26219:569.001 JLINK_ReadMemEx(0x080001A4, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:569.018 -- Read from C cache (2 bytes @ 0x080001A4) +T3F74 26219:569.041 Data: 1F B5 +T3F74 26219:569.063 - 0.069ms returns 2 (0x2) +T3F74 26219:569.081 JLINK_ReadMemEx(0x080001A4, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:569.098 -- Read from C cache (60 bytes @ 0x080001A4) +T3F74 26219:569.122 Data: 1F B5 1F BD 10 B5 10 BD 00 F0 6B F8 11 46 FF F7 ... +T3F74 26219:569.143 - 0.069ms returns 60 (0x3C) +T3F74 26219:569.161 JLINK_ReadMemEx(0x080001A4, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:569.178 -- Read from C cache (2 bytes @ 0x080001A4) +T3F74 26219:569.200 Data: 1F B5 +T3F74 26219:569.222 - 0.068ms returns 2 (0x2) +T3F74 26219:569.240 JLINK_ReadMemEx(0x080001A6, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:569.257 -- Read from C cache (2 bytes @ 0x080001A6) +T3F74 26219:569.279 Data: 1F BD +T3F74 26219:569.301 - 0.069ms returns 2 (0x2) +T3F74 26219:569.320 JLINK_ReadMemEx(0x080001A6, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:569.337 -- Read from C cache (2 bytes @ 0x080001A6) +T3F74 26219:569.359 Data: 1F BD +T3F74 26219:569.388 - 0.075ms returns 2 (0x2) +T3F74 26219:569.406 JLINK_ReadMemEx(0x080001A8, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:569.423 -- Read from C cache (60 bytes @ 0x080001A8) +T3F74 26219:569.446 Data: 10 B5 10 BD 00 F0 6B F8 11 46 FF F7 F7 FF 02 F0 ... +T3F74 26219:569.468 - 0.069ms returns 60 (0x3C) +T3F74 26219:569.486 JLINK_ReadMemEx(0x080001A8, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:569.502 -- Read from C cache (2 bytes @ 0x080001A8) +T3F74 26219:569.525 Data: 10 B5 +T3F74 26219:569.547 - 0.068ms returns 2 (0x2) +T3F74 26219:569.565 JLINK_ReadMemEx(0x080001A8, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:569.583 -- Read from C cache (60 bytes @ 0x080001A8) +T3F74 26219:569.606 Data: 10 B5 10 BD 00 F0 6B F8 11 46 FF F7 F7 FF 02 F0 ... +T3F74 26219:569.628 - 0.071ms returns 60 (0x3C) +T3F74 26219:569.646 JLINK_ReadMemEx(0x080001A8, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:569.663 -- Read from C cache (2 bytes @ 0x080001A8) +T3F74 26219:569.685 Data: 10 B5 +T3F74 26219:569.707 - 0.068ms returns 2 (0x2) +T3F74 26219:569.725 JLINK_ReadMemEx(0x080001AA, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:569.742 -- Read from C cache (2 bytes @ 0x080001AA) +T3F74 26219:569.764 Data: 10 BD +T3F74 26219:569.786 - 0.068ms returns 2 (0x2) +T3F74 26219:569.804 JLINK_ReadMemEx(0x080001AA, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:569.823 -- Read from C cache (2 bytes @ 0x080001AA) +T3F74 26219:569.845 Data: 10 BD +T3F74 26219:569.867 - 0.070ms returns 2 (0x2) +T3F74 26219:569.885 JLINK_ReadMemEx(0x080001AC, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:569.902 -- Read from C cache (60 bytes @ 0x080001AC) +T3F74 26219:569.930 Data: 00 F0 6B F8 11 46 FF F7 F7 FF 02 F0 85 F9 00 F0 ... +T3F74 26219:569.949 - 0.070ms returns 60 (0x3C) +T3F74 26219:569.964 JLINK_ReadMemEx(0x080001AC, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:569.978 -- Read from C cache (2 bytes @ 0x080001AC) +T3F74 26219:569.998 Data: 00 F0 +T3F74 26219:570.016 - 0.059ms returns 2 (0x2) +T3F74 26219:570.032 JLINK_ReadMemEx(0x080001AC, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:570.047 -- Read from C cache (60 bytes @ 0x080001AC) +T3F74 26219:570.067 Data: 00 F0 6B F8 11 46 FF F7 F7 FF 02 F0 85 F9 00 F0 ... +T3F74 26219:570.085 - 0.059ms returns 60 (0x3C) +T3F74 26219:570.100 JLINK_ReadMemEx(0x080001AC, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:570.114 -- Read from C cache (2 bytes @ 0x080001AC) +T3F74 26219:570.134 Data: 00 F0 +T3F74 26219:570.152 - 0.058ms returns 2 (0x2) +T3F74 26219:570.168 JLINK_ReadMemEx(0x080001AE, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:570.182 -- Read from C cache (2 bytes @ 0x080001AE) +T3F74 26219:570.201 Data: 6B F8 +T3F74 26219:570.220 - 0.059ms returns 2 (0x2) +T3F74 26219:570.236 JLINK_ReadMemEx(0x080001B0, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:570.250 -- Read from C cache (60 bytes @ 0x080001B0) +T3F74 26219:570.270 Data: 11 46 FF F7 F7 FF 02 F0 85 F9 00 F0 89 F8 03 B4 ... +T3F74 26219:570.288 - 0.059ms returns 60 (0x3C) +T3F74 26219:570.304 JLINK_ReadMemEx(0x080001B0, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:570.318 -- Read from C cache (2 bytes @ 0x080001B0) +T3F74 26219:570.337 Data: 11 46 +T3F74 26219:570.356 - 0.059ms returns 2 (0x2) +T3F74 26219:570.372 JLINK_ReadMemEx(0x080001B2, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:570.386 -- Read from C cache (2 bytes @ 0x080001B2) +T3F74 26219:570.405 Data: FF F7 +T3F74 26219:570.424 - 0.058ms returns 2 (0x2) +T3F74 26219:570.439 JLINK_ReadMemEx(0x080001B2, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:570.453 -- Read from C cache (2 bytes @ 0x080001B2) +T3F74 26219:570.473 Data: FF F7 +T3F74 26219:570.492 - 0.059ms returns 2 (0x2) +T3F74 26219:570.507 JLINK_ReadMemEx(0x080001B4, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:570.530 -- Read from C cache (60 bytes @ 0x080001B4) +T3F74 26219:570.550 Data: F7 FF 02 F0 85 F9 00 F0 89 F8 03 B4 FF F7 F2 FF ... +T3F74 26219:570.568 - 0.068ms returns 60 (0x3C) +T3F74 26219:570.585 JLINK_ReadMemEx(0x080001B4, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:570.604 -- Read from C cache (2 bytes @ 0x080001B4) +T3F74 26219:570.624 Data: F7 FF +T3F74 26219:570.643 - 0.065ms returns 2 (0x2) +T3F74 26219:570.659 JLINK_ReadMemEx(0x080001B6, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:570.673 -- Read from C cache (2 bytes @ 0x080001B6) +T3F74 26219:570.692 Data: 02 F0 +T3F74 26219:570.711 - 0.059ms returns 2 (0x2) +T3F74 26219:570.726 JLINK_ReadMemEx(0x080001B8, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:570.741 -- Read from C cache (60 bytes @ 0x080001B8) +T3F74 26219:570.761 Data: 85 F9 00 F0 89 F8 03 B4 FF F7 F2 FF 03 BC 00 F0 ... +T3F74 26219:570.780 - 0.059ms returns 60 (0x3C) +T3F74 26219:570.795 JLINK_ReadMemEx(0x080001B8, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:570.809 -- Read from C cache (2 bytes @ 0x080001B8) +T3F74 26219:570.828 Data: 85 F9 +T3F74 26219:570.847 - 0.058ms returns 2 (0x2) +T3F74 26219:570.862 JLINK_ReadMemEx(0x080001BA, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:570.877 -- Read from C cache (2 bytes @ 0x080001BA) +T3F74 26219:570.896 Data: 00 F0 +T3F74 26219:570.915 - 0.059ms returns 2 (0x2) +T3F74 26219:570.930 JLINK_ReadMemEx(0x080001BC, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:570.944 -- Read from C cache (60 bytes @ 0x080001BC) +T3F74 26219:570.964 Data: 89 F8 03 B4 FF F7 F2 FF 03 BC 00 F0 91 F8 00 00 ... +T3F74 26219:570.983 - 0.059ms returns 60 (0x3C) +T3F74 26219:570.998 JLINK_ReadMemEx(0x080001BC, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:571.012 -- Read from C cache (2 bytes @ 0x080001BC) +T3F74 26219:571.031 Data: 89 F8 +T3F74 26219:571.050 - 0.058ms returns 2 (0x2) +T3F74 26219:571.066 JLINK_ReadMemEx(0x080001BE, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:571.080 -- Read from C cache (2 bytes @ 0x080001BE) +T3F74 26219:571.099 Data: 03 B4 +T3F74 26219:571.118 - 0.058ms returns 2 (0x2) +T3F74 26219:571.133 JLINK_ReadMemEx(0x080001C0, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:571.147 -- Read from C cache (60 bytes @ 0x080001C0) +T3F74 26219:571.167 Data: FF F7 F2 FF 03 BC 00 F0 91 F8 00 00 09 48 80 47 ... +T3F74 26219:571.186 - 0.059ms returns 60 (0x3C) +T3F74 26219:571.201 JLINK_ReadMemEx(0x080001C0, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:571.216 -- Read from C cache (2 bytes @ 0x080001C0) +T3F74 26219:571.235 Data: FF F7 +T3F74 26219:571.253 - 0.058ms returns 2 (0x2) +T3F74 26219:571.269 JLINK_ReadMemEx(0x080001C0, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:571.284 -- Read from C cache (60 bytes @ 0x080001C0) +T3F74 26219:571.303 Data: FF F7 F2 FF 03 BC 00 F0 91 F8 00 00 09 48 80 47 ... +T3F74 26219:571.322 - 0.059ms returns 60 (0x3C) +T3F74 26219:571.337 JLINK_ReadMemEx(0x080001C0, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:571.352 -- Read from C cache (2 bytes @ 0x080001C0) +T3F74 26219:571.371 Data: FF F7 +T3F74 26219:571.390 - 0.058ms returns 2 (0x2) +T3F74 26219:571.405 JLINK_ReadMemEx(0x080001C2, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:571.419 -- Read from C cache (2 bytes @ 0x080001C2) +T3F74 26219:571.439 Data: F2 FF +T3F74 26219:571.457 - 0.059ms returns 2 (0x2) +T3F74 26219:571.473 JLINK_ReadMemEx(0x080001C4, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:571.488 -- Read from C cache (60 bytes @ 0x080001C4) +T3F74 26219:571.507 Data: 03 BC 00 F0 91 F8 00 00 09 48 80 47 09 48 00 47 ... +T3F74 26219:571.535 - 0.068ms returns 60 (0x3C) +T3F74 26219:571.550 JLINK_ReadMemEx(0x080001C4, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:571.564 -- Read from C cache (2 bytes @ 0x080001C4) +T3F74 26219:571.585 Data: 03 BC +T3F74 26219:571.604 - 0.060ms returns 2 (0x2) +T3F74 26219:571.619 JLINK_ReadMemEx(0x080001C6, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:571.633 -- Read from C cache (2 bytes @ 0x080001C6) +T3F74 26219:571.652 Data: 00 F0 +T3F74 26219:571.671 - 0.058ms returns 2 (0x2) +T3F74 26219:571.687 JLINK_ReadMemEx(0x080001C6, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:571.701 -- Read from C cache (2 bytes @ 0x080001C6) +T3F74 26219:571.720 Data: 00 F0 +T3F74 26219:571.739 - 0.061ms returns 2 (0x2) +T3F74 26219:571.758 JLINK_ReadMemEx(0x080001C8, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:571.774 CPU_ReadMem(64 bytes @ 0x08000200) +T3F74 26219:573.337 -- Updating C cache (64 bytes @ 0x08000200) +T3F74 26219:573.365 -- Read from C cache (60 bytes @ 0x080001C8) +T3F74 26219:573.387 Data: 91 F8 00 00 09 48 80 47 09 48 00 47 FE E7 FE E7 ... +T3F74 26219:573.406 - 1.654ms returns 60 (0x3C) +T3F74 26219:573.424 JLINK_ReadMemEx(0x080001C8, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:573.440 -- Read from C cache (2 bytes @ 0x080001C8) +T3F74 26219:573.459 Data: 91 F8 +T3F74 26219:573.478 - 0.061ms returns 2 (0x2) +T3F74 26219:573.495 JLINK_ReadMemEx(0x080001CA, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:573.510 -- Read from C cache (2 bytes @ 0x080001CA) +T3F74 26219:573.529 Data: 00 00 +T3F74 26219:573.548 - 0.059ms returns 2 (0x2) +T3F74 26219:573.563 JLINK_ReadMemEx(0x080001CC, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:573.578 -- Read from C cache (60 bytes @ 0x080001CC) +T3F74 26219:573.600 Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ... +T3F74 26219:573.619 - 0.063ms returns 60 (0x3C) +T3F74 26219:573.642 JLINK_ReadMemEx(0x080001CC, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:573.661 -- Read from C cache (2 bytes @ 0x080001CC) +T3F74 26219:573.689 Data: 09 48 +T3F74 26219:573.711 - 0.076ms returns 2 (0x2) +T3F74 26219:573.798 JLINK_ReadMemEx(0x080001CC, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:573.850 -- Read from C cache (60 bytes @ 0x080001CC) +T3F74 26219:573.880 Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ... +T3F74 26219:573.902 - 0.112ms returns 60 (0x3C) +T3F74 26219:573.922 JLINK_ReadMemEx(0x080001CC, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:573.939 -- Read from C cache (2 bytes @ 0x080001CC) +T3F74 26219:573.962 Data: 09 48 +T3F74 26219:573.994 - 0.081ms returns 2 (0x2) +T3F74 26219:574.014 JLINK_ReadMemEx(0x080001CE, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:574.032 -- Read from C cache (2 bytes @ 0x080001CE) +T3F74 26219:574.054 Data: 80 47 +T3F74 26219:574.077 - 0.071ms returns 2 (0x2) +T3F74 26219:574.102 JLINK_ReadMemEx(0x080001CE, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:574.120 -- Read from C cache (2 bytes @ 0x080001CE) +T3F74 26219:574.144 Data: 80 47 +T3F74 26219:574.166 - 0.071ms returns 2 (0x2) +T3F74 26219:574.185 JLINK_ReadMemEx(0x080001D0, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:574.202 -- Read from C cache (60 bytes @ 0x080001D0) +T3F74 26219:574.225 Data: 09 48 00 47 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 ... +T3F74 26219:574.248 - 0.071ms returns 60 (0x3C) +T3F74 26219:574.266 JLINK_ReadMemEx(0x080001D0, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:574.283 -- Read from C cache (2 bytes @ 0x080001D0) +T3F74 26219:574.305 Data: 09 48 +T3F74 26219:574.328 - 0.069ms returns 2 (0x2) +T3F74 26219:574.350 JLINK_ReadMemEx(0x080001D0, 0x3C Bytes, Flags = 0x02000000) +T3F74 26219:574.367 -- Read from C cache (60 bytes @ 0x080001D0) +T3F74 26219:574.390 Data: 09 48 00 47 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 ... +T3F74 26219:574.412 - 0.070ms returns 60 (0x3C) +T3F74 26219:574.430 JLINK_ReadMemEx(0x080001D0, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:574.447 -- Read from C cache (2 bytes @ 0x080001D0) +T3F74 26219:574.470 Data: 09 48 +T3F74 26219:574.492 - 0.069ms returns 2 (0x2) +T3F74 26219:574.510 JLINK_ReadMemEx(0x080001D2, 0x2 Bytes, Flags = 0x02000000) +T3F74 26219:574.527 -- Read from C cache (2 bytes @ 0x080001D2) +T3F74 26219:574.549 Data: 00 47 +T3F74 26219:574.571 - 0.069ms returns 2 (0x2) +T3F74 26219:984.473 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26219:984.526 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26219:985.926 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26219:985.989 - 1.524ms returns 16 (0x10) +T3F74 26219:986.068 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26219:986.115 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26219:987.235 Data: 00 00 00 00 +T3F74 26219:987.335 - 1.275ms returns 4 (0x4) +T3F74 26219:987.359 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26219:987.381 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26219:987.911 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T3F74 26219:987.935 - 0.584ms returns 20 (0x14) +T3F74 26219:987.956 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26219:987.975 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26219:988.406 Data: 00 00 00 00 +T3F74 26219:988.426 - 0.477ms returns 4 (0x4) +T3F74 26219:988.444 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26219:988.460 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26219:988.901 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26219:988.921 - 0.484ms returns 12 (0xC) +T3F74 26219:988.938 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26219:988.954 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26219:989.401 Data: 00 00 00 00 +T3F74 26219:989.421 - 0.489ms returns 4 (0x4) +T3F74 26219:989.438 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26219:989.454 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26219:989.900 Data: 00 00 00 00 +T3F74 26219:989.920 - 0.489ms returns 4 (0x4) +T3F74 26219:989.937 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26219:989.953 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26219:990.399 Data: 00 00 00 00 +T3F74 26219:990.420 - 0.489ms returns 4 (0x4) +T3F74 26224:460.127 JLINK_ReadMemEx(0x080001C6, 0x2 Bytes, Flags = 0x02000000) +T3F74 26224:460.178 -- Read from C cache (2 bytes @ 0x080001C6) +T3F74 26224:460.203 Data: 00 F0 +T3F74 26224:460.226 - 0.107ms returns 2 (0x2) +T3F74 26224:460.246 JLINK_ReadMemEx(0x080001C8, 0x3C Bytes, Flags = 0x02000000) +T3F74 26224:460.263 -- Read from C cache (60 bytes @ 0x080001C8) +T3F74 26224:460.287 Data: 91 F8 00 00 09 48 80 47 09 48 00 47 FE E7 FE E7 ... +T3F74 26224:460.310 - 0.072ms returns 60 (0x3C) +T3F74 26224:460.328 JLINK_ReadMemEx(0x080001C8, 0x2 Bytes, Flags = 0x02000000) +T3F74 26224:460.345 -- Read from C cache (2 bytes @ 0x080001C8) +T3F74 26224:460.368 Data: 91 F8 +T3F74 26224:460.390 - 0.070ms returns 2 (0x2) +T3F74 26224:460.429 JLINK_ReadMemEx(0x080001CA, 0x2 Bytes, Flags = 0x02000000) +T3F74 26224:460.447 -- Read from C cache (2 bytes @ 0x080001CA) +T3F74 26224:460.470 Data: 00 00 +T3F74 26224:460.493 - 0.071ms returns 2 (0x2) +T3F74 26224:460.511 JLINK_ReadMemEx(0x080001CC, 0x3C Bytes, Flags = 0x02000000) +T3F74 26224:460.528 -- Read from C cache (60 bytes @ 0x080001CC) +T3F74 26224:460.552 Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ... +T3F74 26224:460.574 - 0.071ms returns 60 (0x3C) +T3F74 26224:460.592 JLINK_ReadMemEx(0x080001CC, 0x2 Bytes, Flags = 0x02000000) +T3F74 26224:460.609 -- Read from C cache (2 bytes @ 0x080001CC) +T3F74 26224:460.632 Data: 09 48 +T3F74 26224:460.654 - 0.069ms returns 2 (0x2) +T3F74 26224:460.678 JLINK_ReadMemEx(0x080001CC, 0x3C Bytes, Flags = 0x02000000) +T3F74 26224:460.696 -- Read from C cache (60 bytes @ 0x080001CC) +T3F74 26224:460.720 Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ... +T3F74 26224:460.743 - 0.072ms returns 60 (0x3C) +T3F74 26224:460.762 JLINK_ReadMemEx(0x080001CC, 0x2 Bytes, Flags = 0x02000000) +T3F74 26224:460.778 -- Read from C cache (2 bytes @ 0x080001CC) +T3F74 26224:460.801 Data: 09 48 +T3F74 26224:460.823 - 0.069ms returns 2 (0x2) +T3F74 26224:460.846 JLINK_ReadMemEx(0x080001CE, 0x2 Bytes, Flags = 0x02000000) +T3F74 26224:460.868 -- Read from C cache (2 bytes @ 0x080001CE) +T3F74 26224:460.888 Data: 80 47 +T3F74 26224:460.906 - 0.068ms returns 2 (0x2) +T3F74 26225:428.640 JLINK_HasError() +T3F74 26225:428.688 JLINK_ReadReg(R0) +T3F74 26225:429.829 - 1.169ms returns 0x00000000 +T3F74 26225:429.873 JLINK_ReadReg(R1) +T3F74 26225:429.890 - 0.025ms returns 0x00000000 +T3F74 26225:429.909 JLINK_ReadReg(R2) +T3F74 26225:429.926 - 0.025ms returns 0x00000000 +T3F74 26225:429.945 JLINK_ReadReg(R3) +T3F74 26225:429.961 - 0.024ms returns 0x00000000 +T3F74 26225:430.072 JLINK_ReadReg(R4) +T3F74 26225:430.095 - 0.031ms returns 0x00000000 +T3F74 26225:430.114 JLINK_ReadReg(R5) +T3F74 26225:430.130 - 0.024ms returns 0x00000000 +T3F74 26225:430.149 JLINK_ReadReg(R6) +T3F74 26225:430.165 - 0.024ms returns 0x00000000 +T3F74 26225:430.183 JLINK_ReadReg(R7) +T3F74 26225:430.200 - 0.024ms returns 0x00000000 +T3F74 26225:430.218 JLINK_ReadReg(R8) +T3F74 26225:430.234 - 0.024ms returns 0x00000000 +T3F74 26225:430.253 JLINK_ReadReg(R9) +T3F74 26225:430.269 - 0.024ms returns 0x00000000 +T3F74 26225:430.287 JLINK_ReadReg(R10) +T3F74 26225:430.303 - 0.024ms returns 0x00000000 +T3F74 26225:430.322 JLINK_ReadReg(R11) +T3F74 26225:430.338 - 0.024ms returns 0x00000000 +T3F74 26225:430.356 JLINK_ReadReg(R12) +T3F74 26225:430.372 - 0.024ms returns 0x00000000 +T3F74 26225:430.390 JLINK_ReadReg(R13 (SP)) +T3F74 26225:430.407 - 0.024ms returns 0x20000D00 +T3F74 26225:430.426 JLINK_ReadReg(R14) +T3F74 26225:430.442 - 0.024ms returns 0xFFFFFFFF +T3F74 26225:430.460 JLINK_ReadReg(R15 (PC)) +T3F74 26225:430.477 - 0.024ms returns 0x080001CC +T3F74 26225:430.495 JLINK_ReadReg(XPSR) +T3F74 26225:430.511 - 0.024ms returns 0x01000000 +T3F74 26225:430.530 JLINK_ReadReg(MSP) +T3F74 26225:430.546 - 0.024ms returns 0x20000D00 +T3F74 26225:430.564 JLINK_ReadReg(PSP) +T3F74 26225:430.580 - 0.024ms returns 0x00000000 +T3F74 26225:430.599 JLINK_ReadReg(CFBP) +T3F74 26225:430.615 - 0.024ms returns 0x00000000 +T3F74 26225:430.635 JLINK_ReadReg(FPSCR) +T3F74 26225:434.941 - 4.324ms returns 0x00000000 +T3F74 26225:434.973 JLINK_ReadReg(FPS0) +T3F74 26225:434.991 - 0.026ms returns 0x00000000 +T3F74 26225:435.010 JLINK_ReadReg(FPS1) +T3F74 26225:435.026 - 0.024ms returns 0x00000000 +T3F74 26225:435.047 JLINK_ReadReg(FPS2) +T3F74 26225:435.063 - 0.024ms returns 0x00000000 +T3F74 26225:435.082 JLINK_ReadReg(FPS3) +T3F74 26225:435.098 - 0.024ms returns 0x00000000 +T3F74 26225:435.117 JLINK_ReadReg(FPS4) +T3F74 26225:435.132 - 0.024ms returns 0x00000000 +T3F74 26225:435.151 JLINK_ReadReg(FPS5) +T3F74 26225:435.167 - 0.024ms returns 0x00000000 +T3F74 26225:435.186 JLINK_ReadReg(FPS6) +T3F74 26225:435.202 - 0.024ms returns 0x00000000 +T3F74 26225:435.220 JLINK_ReadReg(FPS7) +T3F74 26225:435.236 - 0.024ms returns 0x00000000 +T3F74 26225:435.255 JLINK_ReadReg(FPS8) +T3F74 26225:435.271 - 0.024ms returns 0x00000000 +T3F74 26225:435.289 JLINK_ReadReg(FPS9) +T3F74 26225:435.305 - 0.024ms returns 0x00000000 +T3F74 26225:435.324 JLINK_ReadReg(FPS10) +T3F74 26225:435.340 - 0.024ms returns 0x00000000 +T3F74 26225:435.358 JLINK_ReadReg(FPS11) +T3F74 26225:435.374 - 0.024ms returns 0x00000000 +T3F74 26225:435.393 JLINK_ReadReg(FPS12) +T3F74 26225:435.409 - 0.024ms returns 0x00000000 +T3F74 26225:435.427 JLINK_ReadReg(FPS13) +T3F74 26225:435.443 - 0.024ms returns 0x00000000 +T3F74 26225:435.462 JLINK_ReadReg(FPS14) +T3F74 26225:435.478 - 0.024ms returns 0x00000000 +T3F74 26225:435.496 JLINK_ReadReg(FPS15) +T3F74 26225:435.518 - 0.029ms returns 0x00000000 +T3F74 26225:435.536 JLINK_ReadReg(FPS16) +T3F74 26225:435.552 - 0.024ms returns 0x00000000 +T3F74 26225:435.571 JLINK_ReadReg(FPS17) +T3F74 26225:435.587 - 0.024ms returns 0x00000000 +T3F74 26225:435.605 JLINK_ReadReg(FPS18) +T3F74 26225:435.621 - 0.024ms returns 0x00000000 +T3F74 26225:435.640 JLINK_ReadReg(FPS19) +T3F74 26225:435.656 - 0.024ms returns 0x00000000 +T3F74 26225:435.674 JLINK_ReadReg(FPS20) +T3F74 26225:435.690 - 0.024ms returns 0x00000000 +T3F74 26225:435.709 JLINK_ReadReg(FPS21) +T3F74 26225:435.725 - 0.023ms returns 0x00000000 +T3F74 26225:435.743 JLINK_ReadReg(FPS22) +T3F74 26225:435.759 - 0.024ms returns 0x00000000 +T3F74 26225:435.777 JLINK_ReadReg(FPS23) +T3F74 26225:435.793 - 0.023ms returns 0x00000000 +T3F74 26225:435.811 JLINK_ReadReg(FPS24) +T3F74 26225:435.827 - 0.024ms returns 0x00000000 +T3F74 26225:435.846 JLINK_ReadReg(FPS25) +T3F74 26225:435.862 - 0.024ms returns 0x00000000 +T3F74 26225:435.880 JLINK_ReadReg(FPS26) +T3F74 26225:435.896 - 0.023ms returns 0x00000000 +T3F74 26225:435.914 JLINK_ReadReg(FPS27) +T3F74 26225:435.930 - 0.024ms returns 0x00000000 +T3F74 26225:436.021 JLINK_ReadReg(FPS28) +T3F74 26225:436.053 - 0.041ms returns 0x00000000 +T3F74 26225:436.073 JLINK_ReadReg(FPS29) +T3F74 26225:436.089 - 0.026ms returns 0x00000000 +T3F74 26225:436.109 JLINK_ReadReg(FPS30) +T3F74 26225:436.126 - 0.024ms returns 0x00000000 +T3F74 26225:436.144 JLINK_ReadReg(FPS31) +T3F74 26225:436.160 - 0.024ms returns 0x00000000 +T3F74 26225:436.184 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26225:436.213 CPU_ReadMem(64 bytes @ 0x20000040) +T3F74 26225:437.874 -- Updating C cache (64 bytes @ 0x20000040) +T3F74 26225:437.900 -- Read from C cache (4 bytes @ 0x20000058) +T3F74 26225:437.920 Data: 40 4C 20 60 +T3F74 26225:437.940 - 1.762ms returns 4 (0x4) +T3F74 26225:438.395 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26225:438.416 -- Read from C cache (4 bytes @ 0x20000058) +T3F74 26225:438.439 Data: 40 4C 20 60 +T3F74 26225:438.461 - 0.074ms returns 4 (0x4) +T3F74 26225:438.512 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26225:438.531 -- Read from C cache (4 bytes @ 0x20000058) +T3F74 26225:438.554 Data: 40 4C 20 60 +T3F74 26225:438.576 - 0.072ms returns 4 (0x4) +T3F74 26225:443.145 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26225:443.177 -- Read from C cache (4 bytes @ 0x2000005C) +T3F74 26225:443.198 Data: 06 20 60 60 +T3F74 26225:443.219 - 0.080ms returns 4 (0x4) +T3F74 26225:443.411 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26225:443.427 -- Read from C cache (4 bytes @ 0x2000005C) +T3F74 26225:443.447 Data: 06 20 60 60 +T3F74 26225:443.466 - 0.061ms returns 4 (0x4) +T3F74 26225:443.505 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26225:443.521 -- Read from C cache (4 bytes @ 0x2000005C) +T3F74 26225:443.541 Data: 06 20 60 60 +T3F74 26225:443.560 - 0.061ms returns 4 (0x4) +T062C 26226:085.292 JLINK_ReadMemEx(0x080001CC, 0x2 Bytes, Flags = 0x02000000) +T062C 26226:085.343 -- Read from C cache (2 bytes @ 0x080001CC) +T062C 26226:085.367 Data: 09 48 +T062C 26226:085.391 - 0.106ms returns 2 (0x2) +T062C 26226:085.410 JLINK_HasError() +T062C 26226:085.437 JLINK_SetBPEx(Addr = 0x080024C4, Type = 0xFFFFFFF2) +T062C 26226:085.457 - 0.029ms returns 0x00000001 +T062C 26226:085.476 JLINK_HasError() +T062C 26226:085.494 JLINK_HasError() +T062C 26226:085.513 JLINK_Go() +T062C 26226:086.636 CPU_ReadMem(4 bytes @ 0xE0001000) +T062C 26226:087.109 CPU_WriteMem(4 bytes @ 0xE0002008) +T062C 26226:087.161 CPU_WriteMem(4 bytes @ 0xE000200C) +T062C 26226:087.185 CPU_WriteMem(4 bytes @ 0xE0002010) +T062C 26226:087.211 CPU_WriteMem(4 bytes @ 0xE0002014) +T062C 26226:087.234 CPU_WriteMem(4 bytes @ 0xE0002018) +T062C 26226:087.258 CPU_WriteMem(4 bytes @ 0xE000201C) +T062C 26226:088.480 CPU_WriteMem(4 bytes @ 0xE0001004) +T062C 26226:089.464 - 3.968ms +T062C 26226:190.287 JLINK_HasError() +T062C 26226:190.339 JLINK_IsHalted() +T062C 26226:193.548 - 3.230ms returns TRUE +T062C 26226:193.583 JLINK_HasError() +T062C 26226:193.602 JLINK_Halt() +T062C 26226:193.619 - 0.024ms returns 0x00 +T062C 26226:193.637 JLINK_IsHalted() +T062C 26226:193.653 - 0.024ms returns TRUE +T062C 26226:193.672 JLINK_IsHalted() +T062C 26226:193.690 - 0.026ms returns TRUE +T062C 26226:193.708 JLINK_IsHalted() +T062C 26226:193.724 - 0.023ms returns TRUE +T062C 26226:193.743 JLINK_HasError() +T062C 26226:193.762 JLINK_ReadReg(R15 (PC)) +T062C 26226:193.782 - 0.028ms returns 0x080024C4 +T062C 26226:193.801 JLINK_ReadReg(XPSR) +T062C 26226:193.817 - 0.024ms returns 0x21000000 +T062C 26226:193.839 JLINK_HasError() +T062C 26226:193.862 JLINK_ClrBPEx(BPHandle = 0x00000001) +T062C 26226:193.879 - 0.025ms returns 0x00 +T062C 26226:193.898 JLINK_HasError() +T062C 26226:193.918 JLINK_HasError() +T062C 26226:193.936 JLINK_ReadMemU32(0xE000ED30, 0x1 Items) +T062C 26226:193.961 CPU_ReadMem(4 bytes @ 0xE000ED30) +T062C 26226:195.137 Data: 02 00 00 00 +T062C 26226:195.173 - 1.245ms returns 1 (0x1) +T062C 26226:195.199 JLINK_ReadMemU32(0xE0001028, 0x1 Items) +T062C 26226:195.364 CPU_ReadMem(4 bytes @ 0xE0001028) +T062C 26226:196.459 Data: 00 00 00 00 +T062C 26226:196.494 Debug reg: DWT_FUNC[0] +T062C 26226:196.517 - 1.327ms returns 1 (0x1) +T062C 26226:196.552 JLINK_ReadMemU32(0xE0001038, 0x1 Items) +T062C 26226:196.575 CPU_ReadMem(4 bytes @ 0xE0001038) +T062C 26226:197.086 Data: 00 02 00 00 +T062C 26226:197.124 Debug reg: DWT_FUNC[1] +T062C 26226:197.147 - 0.603ms returns 1 (0x1) +T062C 26226:197.172 JLINK_ReadMemU32(0xE0001048, 0x1 Items) +T062C 26226:197.195 CPU_ReadMem(4 bytes @ 0xE0001048) +T062C 26226:197.578 Data: 00 00 00 00 +T062C 26226:197.606 Debug reg: DWT_FUNC[2] +T062C 26226:197.634 - 0.470ms returns 1 (0x1) +T062C 26226:197.657 JLINK_ReadMemU32(0xE0001058, 0x1 Items) +T062C 26226:197.677 CPU_ReadMem(4 bytes @ 0xE0001058) +T062C 26226:198.076 Data: 00 00 00 00 +T062C 26226:198.101 Debug reg: DWT_FUNC[3] +T062C 26226:198.123 - 0.474ms returns 1 (0x1) +T062C 26226:198.199 JLINK_HasError() +T062C 26226:198.224 JLINK_ReadReg(R0) +T062C 26226:198.241 - 0.026ms returns 0x20000700 +T062C 26226:198.261 JLINK_ReadReg(R1) +T062C 26226:198.277 - 0.024ms returns 0x20000900 +T062C 26226:198.296 JLINK_ReadReg(R2) +T062C 26226:198.312 - 0.024ms returns 0x20000900 +T062C 26226:198.331 JLINK_ReadReg(R3) +T062C 26226:198.347 - 0.024ms returns 0x20000900 +T062C 26226:198.366 JLINK_ReadReg(R4) +T062C 26226:198.383 - 0.024ms returns 0x00000000 +T062C 26226:198.401 JLINK_ReadReg(R5) +T062C 26226:198.417 - 0.024ms returns 0x200006A0 +T062C 26226:198.436 JLINK_ReadReg(R6) +T062C 26226:198.452 - 0.024ms returns 0x00000000 +T062C 26226:198.470 JLINK_ReadReg(R7) +T062C 26226:198.486 - 0.024ms returns 0x00000000 +T062C 26226:198.505 JLINK_ReadReg(R8) +T062C 26226:198.521 - 0.024ms returns 0x00000000 +T062C 26226:198.539 JLINK_ReadReg(R9) +T062C 26226:198.555 - 0.024ms returns 0x00000000 +T062C 26226:198.573 JLINK_ReadReg(R10) +T062C 26226:198.589 - 0.023ms returns 0x080028A0 +T062C 26226:198.607 JLINK_ReadReg(R11) +T062C 26226:198.623 - 0.023ms returns 0x00000000 +T062C 26226:198.642 JLINK_ReadReg(R12) +T062C 26226:198.658 - 0.024ms returns 0x200006E0 +T062C 26226:198.676 JLINK_ReadReg(R13 (SP)) +T062C 26226:198.693 - 0.024ms returns 0x20000D00 +T062C 26226:198.711 JLINK_ReadReg(R14) +T062C 26226:198.727 - 0.024ms returns 0x080001BB +T062C 26226:198.746 JLINK_ReadReg(R15 (PC)) +T062C 26226:198.762 - 0.024ms returns 0x080024C4 +T062C 26226:198.781 JLINK_ReadReg(XPSR) +T062C 26226:198.797 - 0.024ms returns 0x21000000 +T062C 26226:198.815 JLINK_ReadReg(MSP) +T062C 26226:198.831 - 0.024ms returns 0x20000D00 +T062C 26226:198.850 JLINK_ReadReg(PSP) +T062C 26226:198.866 - 0.024ms returns 0x00000000 +T062C 26226:198.885 JLINK_ReadReg(CFBP) +T062C 26226:198.901 - 0.024ms returns 0x00000000 +T062C 26226:198.919 JLINK_ReadReg(FPSCR) +T062C 26226:203.235 - 4.338ms returns 0x00000000 +T062C 26226:203.275 JLINK_ReadReg(FPS0) +T062C 26226:203.297 - 0.032ms returns 0x00000000 +T062C 26226:203.319 JLINK_ReadReg(FPS1) +T062C 26226:203.337 - 0.026ms returns 0x00000000 +T062C 26226:203.358 JLINK_ReadReg(FPS2) +T062C 26226:203.376 - 0.028ms returns 0x00000000 +T062C 26226:203.400 JLINK_ReadReg(FPS3) +T062C 26226:203.419 - 0.027ms returns 0x00000000 +T062C 26226:203.440 JLINK_ReadReg(FPS4) +T062C 26226:203.458 - 0.026ms returns 0x00000000 +T062C 26226:203.478 JLINK_ReadReg(FPS5) +T062C 26226:203.496 - 0.029ms returns 0x00000000 +T062C 26226:203.519 JLINK_ReadReg(FPS6) +T062C 26226:203.542 - 0.033ms returns 0x00000000 +T062C 26226:203.567 JLINK_ReadReg(FPS7) +T062C 26226:203.587 - 0.030ms returns 0x00000000 +T062C 26226:203.610 JLINK_ReadReg(FPS8) +T062C 26226:203.631 - 0.031ms returns 0x00000000 +T062C 26226:203.652 JLINK_ReadReg(FPS9) +T062C 26226:203.668 - 0.024ms returns 0x00000000 +T062C 26226:203.687 JLINK_ReadReg(FPS10) +T062C 26226:203.703 - 0.024ms returns 0x00000000 +T062C 26226:203.721 JLINK_ReadReg(FPS11) +T062C 26226:203.737 - 0.024ms returns 0x00000000 +T062C 26226:203.756 JLINK_ReadReg(FPS12) +T062C 26226:203.772 - 0.024ms returns 0x00000000 +T062C 26226:203.790 JLINK_ReadReg(FPS13) +T062C 26226:203.894 - 0.112ms returns 0x00000000 +T062C 26226:203.913 JLINK_ReadReg(FPS14) +T062C 26226:203.929 - 0.024ms returns 0x00000000 +T062C 26226:203.948 JLINK_ReadReg(FPS15) +T062C 26226:203.964 - 0.024ms returns 0x00000000 +T062C 26226:203.982 JLINK_ReadReg(FPS16) +T062C 26226:203.999 - 0.024ms returns 0x00000000 +T062C 26226:204.017 JLINK_ReadReg(FPS17) +T062C 26226:204.033 - 0.024ms returns 0x00000000 +T062C 26226:204.052 JLINK_ReadReg(FPS18) +T062C 26226:204.068 - 0.024ms returns 0x00000000 +T062C 26226:204.086 JLINK_ReadReg(FPS19) +T062C 26226:204.102 - 0.024ms returns 0x00000000 +T062C 26226:204.121 JLINK_ReadReg(FPS20) +T062C 26226:204.140 - 0.027ms returns 0x00000000 +T062C 26226:204.159 JLINK_ReadReg(FPS21) +T062C 26226:204.175 - 0.024ms returns 0x00000000 +T062C 26226:204.194 JLINK_ReadReg(FPS22) +T062C 26226:204.213 - 0.027ms returns 0x00000000 +T062C 26226:204.231 JLINK_ReadReg(FPS23) +T062C 26226:204.247 - 0.024ms returns 0x00000000 +T062C 26226:204.266 JLINK_ReadReg(FPS24) +T062C 26226:204.282 - 0.024ms returns 0x00000000 +T062C 26226:204.301 JLINK_ReadReg(FPS25) +T062C 26226:204.316 - 0.023ms returns 0x00000000 +T062C 26226:204.335 JLINK_ReadReg(FPS26) +T062C 26226:204.351 - 0.024ms returns 0x00000000 +T062C 26226:204.369 JLINK_ReadReg(FPS27) +T062C 26226:204.385 - 0.024ms returns 0x00000000 +T062C 26226:204.404 JLINK_ReadReg(FPS28) +T062C 26226:204.420 - 0.024ms returns 0x00000000 +T062C 26226:204.438 JLINK_ReadReg(FPS29) +T062C 26226:204.455 - 0.024ms returns 0x00000000 +T062C 26226:204.473 JLINK_ReadReg(FPS30) +T062C 26226:204.489 - 0.024ms returns 0x00000000 +T062C 26226:204.507 JLINK_ReadReg(FPS31) +T062C 26226:204.523 - 0.024ms returns 0x00000000 +T3F74 26226:213.416 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26226:213.457 CPU_ReadMem(64 bytes @ 0x20000040) +T3F74 26226:214.979 -- Updating C cache (64 bytes @ 0x20000040) +T3F74 26226:215.006 -- Read from C cache (4 bytes @ 0x20000058) +T3F74 26226:215.026 Data: 00 00 00 00 +T3F74 26226:215.046 - 1.637ms returns 4 (0x4) +T3F74 26226:215.406 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26226:215.427 -- Read from C cache (4 bytes @ 0x2000005C) +T3F74 26226:215.447 Data: 00 00 00 00 +T3F74 26226:215.466 - 0.066ms returns 4 (0x4) +T3F74 26226:218.902 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26226:218.930 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26226:220.076 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26226:220.101 - 1.206ms returns 16 (0x10) +T3F74 26226:220.121 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26226:220.140 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26226:220.575 Data: 00 00 00 00 +T3F74 26226:220.599 - 0.486ms returns 4 (0x4) +T3F74 26226:220.621 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26226:220.640 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26226:221.199 Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... +T3F74 26226:221.225 - 0.612ms returns 20 (0x14) +T3F74 26226:221.246 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26226:221.266 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26226:221.692 Data: 00 00 00 00 +T3F74 26226:221.713 - 0.474ms returns 4 (0x4) +T3F74 26226:221.730 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26226:221.747 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26226:222.192 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26226:222.223 - 0.500ms returns 12 (0xC) +T3F74 26226:222.241 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26226:222.269 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26226:222.698 Data: 00 00 00 00 +T3F74 26226:222.722 - 0.489ms returns 4 (0x4) +T3F74 26226:222.742 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26226:222.762 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26226:223.196 Data: 00 00 00 00 +T3F74 26226:223.231 - 0.497ms returns 4 (0x4) +T3F74 26226:223.252 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26226:223.283 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26226:223.699 Data: 00 00 00 00 +T3F74 26226:223.724 - 0.480ms returns 4 (0x4) +T062C 26231:530.626 JLINK_ReadMemEx(0x080024C4, 0x2 Bytes, Flags = 0x02000000) +T062C 26231:530.685 CPU_ReadMem(64 bytes @ 0x080024C0) +T062C 26231:532.370 -- Updating C cache (64 bytes @ 0x080024C0) +T062C 26231:532.449 -- Read from C cache (2 bytes @ 0x080024C4) +T062C 26231:532.473 Data: FE F7 +T062C 26231:532.495 - 1.877ms returns 2 (0x2) +T062C 26231:532.517 JLINK_HasError() +T062C 26231:532.536 JLINK_HasError() +T062C 26231:532.554 JLINK_Go() +T062C 26231:533.691 CPU_ReadMem(4 bytes @ 0xE0001000) +T062C 26231:534.122 CPU_WriteMem(4 bytes @ 0xE0002008) +T062C 26231:534.994 - 2.449ms +T062C 26231:635.881 JLINK_HasError() +T062C 26231:635.934 JLINK_IsHalted() +T062C 26231:637.019 - 1.104ms returns FALSE +T062C 26231:737.550 JLINK_HasError() +T062C 26231:737.596 JLINK_IsHalted() +T062C 26231:738.623 - 1.045ms returns FALSE +T062C 26231:839.256 JLINK_HasError() +T062C 26231:839.300 JLINK_IsHalted() +T062C 26231:840.369 - 1.086ms returns FALSE +T062C 26231:941.096 JLINK_HasError() +T062C 26231:941.181 JLINK_IsHalted() +T062C 26231:942.203 - 1.041ms returns FALSE +T062C 26232:042.453 JLINK_HasError() +T062C 26232:042.530 JLINK_IsHalted() +T062C 26232:043.649 - 1.137ms returns FALSE +T062C 26232:144.181 JLINK_HasError() +T062C 26232:144.221 JLINK_HasError() +T062C 26232:144.240 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26232:144.271 CPU_ReadMem(4 bytes @ 0xE0001004) +T062C 26232:145.325 Data: 8D 12 74 01 +T062C 26232:145.399 Debug reg: DWT_CYCCNT +T062C 26232:145.425 - 1.193ms returns 1 (0x1) +T3F74 26232:148.040 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26232:148.080 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26232:149.222 Data: 00 00 80 00 +T3F74 26232:149.256 - 1.225ms returns 4 (0x4) +T3F74 26232:149.975 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26232:149.999 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26232:151.053 Data: 00 00 F0 01 +T3F74 26232:151.084 - 1.117ms returns 4 (0x4) +T3F74 26232:155.444 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26232:155.496 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26232:156.715 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26232:156.751 - 1.315ms returns 16 (0x10) +T3F74 26232:156.778 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26232:156.801 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26232:157.291 Data: 1F 00 00 00 +T3F74 26232:157.316 - 0.547ms returns 4 (0x4) +T3F74 26232:157.337 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26232:157.357 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26232:157.942 Data: 00 00 00 00 00 00 00 00 00 00 00 00 0D 02 00 00 ... +T3F74 26232:157.969 - 0.639ms returns 20 (0x14) +T3F74 26232:157.990 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26232:158.011 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26232:158.412 Data: 1F 03 00 00 +T3F74 26232:158.436 - 0.453ms returns 4 (0x4) +T3F74 26232:158.456 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26232:158.475 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26232:158.914 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26232:158.938 - 0.489ms returns 12 (0xC) +T3F74 26232:158.958 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26232:158.977 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26232:159.413 Data: 00 00 00 00 +T3F74 26232:159.436 - 0.486ms returns 4 (0x4) +T3F74 26232:159.457 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26232:159.476 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26232:159.912 Data: 00 00 00 00 +T3F74 26232:159.936 - 0.486ms returns 4 (0x4) +T3F74 26232:159.956 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26232:159.975 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26232:160.411 Data: 00 00 00 00 +T3F74 26232:160.436 - 0.492ms returns 4 (0x4) +T062C 26232:206.659 JLINK_IsHalted() +T062C 26232:207.805 - 1.169ms returns FALSE +T062C 26232:308.813 JLINK_HasError() +T062C 26232:308.900 JLINK_IsHalted() +T062C 26232:310.109 - 1.250ms returns FALSE +T062C 26232:410.345 JLINK_HasError() +T062C 26232:410.428 JLINK_IsHalted() +T062C 26232:411.598 - 1.188ms returns FALSE +T062C 26232:512.550 JLINK_HasError() +T062C 26232:512.632 JLINK_IsHalted() +T062C 26232:513.752 - 1.138ms returns FALSE +T062C 26232:614.821 JLINK_HasError() +T062C 26232:614.894 JLINK_IsHalted() +T062C 26232:616.130 - 1.277ms returns FALSE +T062C 26232:716.930 JLINK_HasError() +T062C 26232:716.967 JLINK_HasError() +T062C 26232:716.985 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26232:717.014 Data: 8D 12 74 01 +T062C 26232:717.038 Debug reg: DWT_CYCCNT +T062C 26232:717.061 - 0.083ms returns 1 (0x1) +T3F74 26232:722.848 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26232:722.880 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26232:724.065 Data: 00 00 80 00 +T3F74 26232:724.098 - 1.259ms returns 4 (0x4) +T3F74 26232:724.498 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26232:724.520 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26232:725.679 Data: 00 00 F0 01 +T3F74 26232:725.744 - 1.253ms returns 4 (0x4) +T3F74 26232:729.248 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26232:729.275 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26232:730.529 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26232:730.563 - 1.323ms returns 16 (0x10) +T3F74 26232:730.586 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26232:730.609 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26232:731.088 Data: 1E 00 00 00 +T3F74 26232:731.112 - 0.533ms returns 4 (0x4) +T3F74 26232:731.132 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26232:731.151 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26232:731.840 Data: 00 00 00 00 00 00 00 00 00 00 00 00 27 00 00 00 ... +T3F74 26232:731.866 - 0.742ms returns 20 (0x14) +T3F74 26232:731.891 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26232:731.912 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26232:732.339 Data: 1F 03 00 00 +T3F74 26232:732.363 - 0.479ms returns 4 (0x4) +T3F74 26232:732.383 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26232:732.402 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26232:732.832 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26232:732.852 - 0.476ms returns 12 (0xC) +T3F74 26232:732.870 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26232:732.885 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26232:733.332 Data: 00 00 00 00 +T3F74 26232:733.352 - 0.489ms returns 4 (0x4) +T3F74 26232:733.369 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26232:733.385 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26232:733.831 Data: 00 00 00 00 +T3F74 26232:733.851 - 0.489ms returns 4 (0x4) +T3F74 26232:733.868 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26232:733.884 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26232:734.332 Data: 00 00 00 00 +T3F74 26232:734.352 - 0.490ms returns 4 (0x4) +T062C 26232:753.315 JLINK_IsHalted() +T062C 26232:754.516 - 1.219ms returns FALSE +T062C 26232:855.549 JLINK_HasError() +T062C 26232:855.633 JLINK_IsHalted() +T062C 26232:856.849 - 1.234ms returns FALSE +T062C 26232:957.030 JLINK_HasError() +T062C 26232:957.102 JLINK_IsHalted() +T062C 26232:958.240 - 1.157ms returns FALSE +T062C 26233:058.637 JLINK_HasError() +T062C 26233:058.721 JLINK_IsHalted() +T062C 26233:059.925 - 1.223ms returns FALSE +T062C 26233:160.927 JLINK_HasError() +T062C 26233:160.972 JLINK_IsHalted() +T062C 26233:162.045 - 1.091ms returns FALSE +T062C 26233:262.714 JLINK_HasError() +T062C 26233:262.808 JLINK_HasError() +T062C 26233:262.863 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26233:262.894 Data: 8D 12 74 01 +T062C 26233:262.918 Debug reg: DWT_CYCCNT +T062C 26233:262.940 - 0.087ms returns 1 (0x1) +T3F74 26233:265.626 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26233:265.701 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26233:266.806 Data: 00 00 80 00 +T3F74 26233:266.840 - 1.222ms returns 4 (0x4) +T3F74 26233:266.883 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26233:266.908 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26233:267.407 Data: 00 00 F0 01 +T3F74 26233:267.432 - 0.557ms returns 4 (0x4) +T3F74 26233:271.122 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26233:271.156 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26233:272.415 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26233:272.450 - 1.335ms returns 16 (0x10) +T3F74 26233:272.474 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26233:272.497 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26233:273.015 Data: 1E 00 00 00 +T3F74 26233:273.039 - 0.573ms returns 4 (0x4) +T3F74 26233:273.060 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26233:273.079 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26233:273.649 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1B 00 00 00 ... +T3F74 26233:273.673 - 0.621ms returns 20 (0x14) +T3F74 26233:273.693 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26233:273.712 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26233:274.137 Data: 1F 03 00 00 +T3F74 26233:274.160 - 0.475ms returns 4 (0x4) +T3F74 26233:274.180 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26233:274.199 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26233:274.650 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26233:274.673 - 0.501ms returns 12 (0xC) +T3F74 26233:274.693 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26233:274.712 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26233:275.142 Data: 00 00 00 00 +T3F74 26233:275.166 - 0.480ms returns 4 (0x4) +T3F74 26233:275.186 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26233:275.205 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26233:275.645 Data: 00 00 00 00 +T3F74 26233:275.668 - 0.490ms returns 4 (0x4) +T3F74 26233:275.688 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26233:275.708 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26233:276.145 Data: 00 00 00 00 +T3F74 26233:276.168 - 0.488ms returns 4 (0x4) +T062C 26233:289.649 JLINK_IsHalted() +T062C 26233:290.784 - 1.160ms returns FALSE +T062C 26233:391.807 JLINK_HasError() +T062C 26233:391.877 JLINK_IsHalted() +T062C 26233:392.887 - 1.029ms returns FALSE +T062C 26233:493.147 JLINK_HasError() +T062C 26233:493.235 JLINK_IsHalted() +T062C 26233:494.484 - 1.297ms returns FALSE +T062C 26233:595.452 JLINK_HasError() +T062C 26233:595.539 JLINK_IsHalted() +T062C 26233:596.682 - 1.160ms returns FALSE +T062C 26233:696.911 JLINK_HasError() +T062C 26233:696.951 JLINK_IsHalted() +T062C 26233:697.993 - 1.060ms returns FALSE +T062C 26233:798.729 JLINK_HasError() +T062C 26233:798.798 JLINK_HasError() +T062C 26233:798.827 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26233:798.862 Data: 8D 12 74 01 +T062C 26233:798.887 Debug reg: DWT_CYCCNT +T062C 26233:798.910 - 0.090ms returns 1 (0x1) +T3F74 26233:802.833 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26233:802.878 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26233:803.958 Data: 00 00 80 00 +T3F74 26233:803.994 - 1.170ms returns 4 (0x4) +T3F74 26233:804.033 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26233:804.056 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26233:804.559 Data: 00 00 F0 01 +T3F74 26233:804.580 - 0.553ms returns 4 (0x4) +T3F74 26233:807.808 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26233:807.840 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26233:809.070 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26233:809.095 - 1.293ms returns 16 (0x10) +T3F74 26233:809.115 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26233:809.133 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26233:809.560 Data: 1E 00 00 00 +T3F74 26233:809.580 - 0.472ms returns 4 (0x4) +T3F74 26233:809.598 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26233:809.625 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26233:810.061 Data: 00 00 00 00 00 00 00 00 00 00 00 00 A1 00 00 00 ... +T3F74 26233:810.081 - 0.490ms returns 20 (0x14) +T3F74 26233:810.099 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26233:810.115 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26233:810.559 Data: 1F 03 00 00 +T3F74 26233:810.579 - 0.487ms returns 4 (0x4) +T3F74 26233:810.597 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26233:810.613 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26233:811.059 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26233:811.079 - 0.489ms returns 12 (0xC) +T3F74 26233:811.097 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26233:811.113 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26233:811.558 Data: 00 00 00 00 +T3F74 26233:811.579 - 0.488ms returns 4 (0x4) +T3F74 26233:811.596 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26233:811.612 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26233:812.071 Data: 00 00 00 00 +T3F74 26233:812.097 - 0.509ms returns 4 (0x4) +T3F74 26233:812.119 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26233:812.139 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26233:812.564 Data: 00 00 00 00 +T3F74 26233:812.588 - 0.477ms returns 4 (0x4) +T062C 26233:824.436 JLINK_IsHalted() +T062C 26233:825.572 - 1.146ms returns FALSE +T062C 26233:925.765 JLINK_HasError() +T062C 26233:925.850 JLINK_IsHalted() +T062C 26233:926.939 - 1.103ms returns FALSE +T062C 26234:027.138 JLINK_HasError() +T062C 26234:027.225 JLINK_IsHalted() +T062C 26234:028.414 - 1.237ms returns FALSE +T062C 26234:128.993 JLINK_HasError() +T062C 26234:129.039 JLINK_IsHalted() +T062C 26234:130.163 - 1.143ms returns FALSE +T062C 26234:230.417 JLINK_HasError() +T062C 26234:230.502 JLINK_IsHalted() +T062C 26234:231.613 - 1.124ms returns FALSE +T062C 26234:331.875 JLINK_HasError() +T062C 26234:331.930 JLINK_HasError() +T062C 26234:331.953 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26234:331.990 Data: 8D 12 74 01 +T062C 26234:332.019 Debug reg: DWT_CYCCNT +T062C 26234:332.047 - 0.103ms returns 1 (0x1) +T3F74 26234:337.927 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26234:337.984 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26234:339.068 Data: 00 00 80 00 +T3F74 26234:339.103 - 1.184ms returns 4 (0x4) +T3F74 26234:339.143 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26234:339.166 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26234:339.621 Data: 00 00 F0 01 +T3F74 26234:339.645 - 0.510ms returns 4 (0x4) +T3F74 26234:343.619 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26234:343.654 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26234:344.917 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26234:344.963 - 1.352ms returns 16 (0x10) +T3F74 26234:345.038 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26234:345.062 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26234:345.496 Data: 1E 00 00 00 +T3F74 26234:345.530 - 0.500ms returns 4 (0x4) +T3F74 26234:345.553 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26234:345.575 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26234:346.119 Data: 00 00 00 00 00 00 00 00 00 00 00 00 0F 02 00 00 ... +T3F74 26234:346.143 - 0.597ms returns 20 (0x14) +T3F74 26234:346.163 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26234:346.183 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26234:346.619 Data: 1F 03 00 00 +T3F74 26234:346.643 - 0.487ms returns 4 (0x4) +T3F74 26234:346.663 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26234:346.682 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26234:347.119 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26234:347.142 - 0.487ms returns 12 (0xC) +T3F74 26234:347.163 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26234:347.182 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26234:347.638 Data: 00 00 00 00 +T3F74 26234:347.688 - 0.533ms returns 4 (0x4) +T3F74 26234:347.715 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26234:347.737 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26234:348.142 Data: 00 00 00 00 +T3F74 26234:348.168 - 0.461ms returns 4 (0x4) +T3F74 26234:348.189 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26234:348.209 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26234:348.747 Data: 00 00 00 00 +T3F74 26234:348.773 - 0.592ms returns 4 (0x4) +T062C 26234:362.973 JLINK_IsHalted() +T062C 26234:364.016 - 1.062ms returns FALSE +T062C 26234:464.232 JLINK_HasError() +T062C 26234:464.319 JLINK_IsHalted() +T062C 26234:465.517 - 1.215ms returns FALSE +T062C 26234:566.010 JLINK_HasError() +T062C 26234:566.095 JLINK_IsHalted() +T062C 26234:567.133 - 1.056ms returns FALSE +T062C 26234:668.481 JLINK_HasError() +T062C 26234:668.568 JLINK_IsHalted() +T062C 26234:669.780 - 1.228ms returns FALSE +T062C 26234:770.406 JLINK_HasError() +T062C 26234:770.448 JLINK_IsHalted() +T062C 26234:771.588 - 1.158ms returns FALSE +T062C 26234:871.948 JLINK_HasError() +T062C 26234:871.990 JLINK_HasError() +T062C 26234:872.009 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26234:872.045 Data: 8D 12 74 01 +T062C 26234:872.077 Debug reg: DWT_CYCCNT +T062C 26234:872.100 - 0.099ms returns 1 (0x1) +T3F74 26234:876.321 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26234:876.400 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26234:877.457 Data: 00 00 80 00 +T3F74 26234:877.493 - 1.182ms returns 4 (0x4) +T3F74 26234:877.540 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26234:877.567 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26234:878.078 Data: 00 00 F0 01 +T3F74 26234:878.123 - 0.591ms returns 4 (0x4) +T3F74 26234:882.375 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26234:882.425 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26234:883.797 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26234:883.842 - 1.478ms returns 16 (0x10) +T3F74 26234:883.875 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26234:883.917 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26234:885.053 Data: 1E 00 00 00 +T3F74 26234:885.088 - 1.221ms returns 4 (0x4) +T3F74 26234:885.117 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26234:885.140 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26234:885.673 Data: 00 00 00 00 00 00 00 00 00 00 00 00 BB 00 00 00 ... +T3F74 26234:885.698 - 0.589ms returns 20 (0x14) +T3F74 26234:885.721 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26234:885.741 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26234:886.172 Data: 1F 03 00 00 +T3F74 26234:886.196 - 0.483ms returns 4 (0x4) +T3F74 26234:886.220 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26234:886.250 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26234:886.694 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26234:886.723 - 0.512ms returns 12 (0xC) +T3F74 26234:886.774 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26234:886.805 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26234:887.301 Data: 00 00 00 00 +T3F74 26234:887.329 - 0.563ms returns 4 (0x4) +T3F74 26234:887.355 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26234:887.377 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26234:887.825 Data: 00 00 00 00 +T3F74 26234:887.851 - 0.504ms returns 4 (0x4) +T3F74 26234:887.876 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26234:887.899 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26234:888.301 Data: 00 00 00 00 +T3F74 26234:888.327 - 0.459ms returns 4 (0x4) +T062C 26234:902.608 JLINK_IsHalted() +T062C 26234:903.695 - 1.102ms returns FALSE +T062C 26235:003.906 JLINK_HasError() +T062C 26235:003.953 JLINK_IsHalted() +T062C 26235:005.056 - 1.134ms returns FALSE +T062C 26235:105.985 JLINK_HasError() +T062C 26235:106.027 JLINK_IsHalted() +T062C 26235:107.160 - 1.152ms returns FALSE +T062C 26235:208.005 JLINK_HasError() +T062C 26235:208.051 JLINK_IsHalted() +T062C 26235:209.144 - 1.109ms returns FALSE +T062C 26235:309.963 JLINK_HasError() +T062C 26235:310.010 JLINK_IsHalted() +T062C 26235:311.129 - 1.128ms returns FALSE +T062C 26235:411.562 JLINK_HasError() +T062C 26235:411.610 JLINK_HasError() +T062C 26235:411.628 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26235:411.659 Data: 8D 12 74 01 +T062C 26235:411.683 Debug reg: DWT_CYCCNT +T062C 26235:411.705 - 0.084ms returns 1 (0x1) +T3F74 26235:414.481 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26235:414.571 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26235:415.801 Data: 00 00 80 00 +T3F74 26235:415.837 - 1.364ms returns 4 (0x4) +T3F74 26235:415.884 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26235:415.907 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26235:416.358 Data: 00 00 F0 01 +T3F74 26235:416.382 - 0.506ms returns 4 (0x4) +T3F74 26235:420.042 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26235:420.075 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26235:421.342 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26235:421.421 - 1.388ms returns 16 (0x10) +T3F74 26235:421.445 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26235:421.468 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26235:422.000 Data: 1F 00 00 00 +T3F74 26235:422.027 - 0.589ms returns 4 (0x4) +T3F74 26235:422.048 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26235:422.069 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26235:422.603 Data: 00 00 00 00 00 00 00 00 00 00 00 00 25 01 00 00 ... +T3F74 26235:422.627 - 0.587ms returns 20 (0x14) +T3F74 26235:422.648 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26235:422.667 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26235:423.100 Data: 1F 03 00 00 +T3F74 26235:423.124 - 0.484ms returns 4 (0x4) +T3F74 26235:423.145 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26235:423.164 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26235:423.600 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26235:423.625 - 0.488ms returns 12 (0xC) +T3F74 26235:423.648 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26235:423.668 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26235:424.109 Data: 00 00 00 00 +T3F74 26235:424.146 - 0.506ms returns 4 (0x4) +T3F74 26235:424.178 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26235:424.202 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26235:424.600 Data: 00 00 00 00 +T3F74 26235:424.624 - 0.455ms returns 4 (0x4) +T3F74 26235:424.649 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26235:424.668 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26235:425.103 Data: 00 00 00 00 +T3F74 26235:425.127 - 0.486ms returns 4 (0x4) +T062C 26235:445.250 JLINK_IsHalted() +T062C 26235:446.368 - 1.137ms returns FALSE +T062C 26235:546.844 JLINK_HasError() +T062C 26235:546.890 JLINK_IsHalted() +T062C 26235:548.067 - 1.219ms returns FALSE +T062C 26235:648.628 JLINK_HasError() +T062C 26235:648.675 JLINK_IsHalted() +T062C 26235:649.865 - 1.209ms returns FALSE +T062C 26235:750.000 JLINK_HasError() +T062C 26235:750.047 JLINK_IsHalted() +T062C 26235:751.073 - 1.043ms returns FALSE +T062C 26235:851.677 JLINK_HasError() +T062C 26235:851.724 JLINK_IsHalted() +T062C 26235:852.808 - 1.099ms returns FALSE +T062C 26235:953.156 JLINK_HasError() +T062C 26235:953.206 JLINK_HasError() +T062C 26235:953.228 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26235:953.260 Data: 8D 12 74 01 +T062C 26235:953.285 Debug reg: DWT_CYCCNT +T062C 26235:953.309 - 0.099ms returns 1 (0x1) +T3F74 26235:955.784 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26235:955.821 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26235:956.922 Data: 00 00 80 00 +T3F74 26235:956.959 - 1.182ms returns 4 (0x4) +T3F74 26235:957.001 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26235:957.025 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26235:957.533 Data: 00 00 F0 01 +T3F74 26235:957.560 - 0.573ms returns 4 (0x4) +T3F74 26235:961.142 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26235:961.173 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26235:962.422 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26235:962.462 - 1.329ms returns 16 (0x10) +T3F74 26235:962.487 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26235:962.510 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26235:963.030 Data: 1E 00 00 00 +T3F74 26235:963.054 - 0.575ms returns 4 (0x4) +T3F74 26235:963.077 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26235:963.097 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26235:963.657 Data: 00 00 00 00 00 00 00 00 00 00 00 00 DF 01 00 00 ... +T3F74 26235:963.681 - 0.611ms returns 20 (0x14) +T3F74 26235:963.701 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26235:963.720 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26235:964.154 Data: 1F 03 00 00 +T3F74 26235:964.177 - 0.484ms returns 4 (0x4) +T3F74 26235:964.197 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26235:964.216 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26235:964.654 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26235:964.678 - 0.488ms returns 12 (0xC) +T3F74 26235:964.698 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26235:964.717 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26235:965.153 Data: 00 00 00 00 +T3F74 26235:965.177 - 0.486ms returns 4 (0x4) +T3F74 26235:965.197 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26235:965.216 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26235:965.655 Data: 00 00 00 00 +T3F74 26235:965.679 - 0.490ms returns 4 (0x4) +T3F74 26235:965.699 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26235:965.717 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26235:966.153 Data: 00 00 00 00 +T3F74 26235:966.177 - 0.485ms returns 4 (0x4) +T062C 26235:986.399 JLINK_IsHalted() +T062C 26235:987.542 - 1.156ms returns FALSE +T062C 26236:088.613 JLINK_HasError() +T062C 26236:088.702 JLINK_IsHalted() +T062C 26236:090.020 - 1.336ms returns FALSE +T062C 26236:191.055 JLINK_HasError() +T062C 26236:191.105 JLINK_IsHalted() +T062C 26236:192.150 - 1.077ms returns FALSE +T062C 26236:293.120 JLINK_HasError() +T062C 26236:293.200 JLINK_IsHalted() +T062C 26236:294.258 - 1.086ms returns FALSE +T062C 26236:394.458 JLINK_HasError() +T062C 26236:394.550 JLINK_IsHalted() +T062C 26236:395.686 - 1.181ms returns FALSE +T062C 26236:496.728 JLINK_HasError() +T062C 26236:496.779 JLINK_HasError() +T062C 26236:496.804 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26236:496.839 Data: 8D 12 74 01 +T062C 26236:496.868 Debug reg: DWT_CYCCNT +T062C 26236:496.897 - 0.102ms returns 1 (0x1) +T3F74 26236:503.329 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26236:503.379 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26236:504.502 Data: 00 00 80 00 +T3F74 26236:504.531 - 1.210ms returns 4 (0x4) +T3F74 26236:504.569 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26236:504.590 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26236:505.082 Data: 00 00 F0 01 +T3F74 26236:505.107 - 0.546ms returns 4 (0x4) +T3F74 26236:508.580 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26236:508.607 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26236:509.844 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26236:509.873 - 1.301ms returns 16 (0x10) +T3F74 26236:509.896 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26236:509.917 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26236:510.332 Data: 1E 00 00 00 +T3F74 26236:510.356 - 0.467ms returns 4 (0x4) +T3F74 26236:510.376 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26236:510.395 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26236:510.987 Data: 00 00 00 00 00 00 00 00 00 00 00 00 5D 02 00 00 ... +T3F74 26236:511.014 - 0.645ms returns 20 (0x14) +T3F74 26236:511.035 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26236:511.056 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26236:511.456 Data: 1F 03 00 00 +T3F74 26236:511.480 - 0.452ms returns 4 (0x4) +T3F74 26236:511.500 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26236:511.519 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26236:511.956 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26236:511.979 - 0.487ms returns 12 (0xC) +T3F74 26236:511.999 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26236:512.018 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26236:512.455 Data: 00 00 00 00 +T3F74 26236:512.479 - 0.487ms returns 4 (0x4) +T3F74 26236:512.499 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26236:512.518 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26236:512.955 Data: 00 00 00 00 +T3F74 26236:512.978 - 0.487ms returns 4 (0x4) +T3F74 26236:512.998 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26236:513.017 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26236:513.455 Data: 00 00 00 00 +T3F74 26236:513.479 - 0.488ms returns 4 (0x4) +T062C 26236:527.231 JLINK_IsHalted() +T062C 26236:528.352 - 1.152ms returns FALSE +T062C 26236:628.642 JLINK_HasError() +T062C 26236:628.686 JLINK_IsHalted() +T062C 26236:629.833 - 1.161ms returns FALSE +T062C 26236:730.027 JLINK_HasError() +T062C 26236:730.115 JLINK_IsHalted() +T062C 26236:731.274 - 1.178ms returns FALSE +T062C 26236:832.088 JLINK_HasError() +T062C 26236:832.138 JLINK_IsHalted() +T062C 26236:833.260 - 1.141ms returns FALSE +T062C 26236:934.010 JLINK_HasError() +T062C 26236:934.068 JLINK_IsHalted() +T062C 26236:935.168 - 1.120ms returns FALSE +T062C 26237:036.307 JLINK_HasError() +T062C 26237:036.377 JLINK_HasError() +T062C 26237:036.396 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26237:036.425 Data: 8D 12 74 01 +T062C 26237:036.449 Debug reg: DWT_CYCCNT +T062C 26237:036.472 - 0.084ms returns 1 (0x1) +T3F74 26237:041.633 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26237:041.678 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26237:042.869 Data: 00 00 80 00 +T3F74 26237:042.927 - 1.301ms returns 4 (0x4) +T3F74 26237:042.961 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26237:042.981 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26237:043.385 Data: 00 00 F0 01 +T3F74 26237:043.405 - 0.451ms returns 4 (0x4) +T3F74 26237:046.559 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26237:046.596 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26237:047.777 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26237:047.804 - 1.253ms returns 16 (0x10) +T3F74 26237:047.827 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26237:047.848 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26237:048.267 Data: 1E 00 00 00 +T3F74 26237:048.291 - 0.472ms returns 4 (0x4) +T3F74 26237:048.312 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26237:048.331 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26237:048.891 Data: 00 00 00 00 00 00 00 00 00 00 00 00 55 02 00 00 ... +T3F74 26237:048.915 - 0.611ms returns 20 (0x14) +T3F74 26237:048.935 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26237:048.954 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26237:049.490 Data: 1F 03 00 00 +T3F74 26237:049.527 - 0.600ms returns 4 (0x4) +T3F74 26237:049.554 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26237:049.577 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26237:050.046 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26237:050.075 - 0.529ms returns 12 (0xC) +T3F74 26237:050.098 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26237:050.119 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26237:050.718 Data: 00 00 00 00 +T3F74 26237:050.744 - 0.654ms returns 4 (0x4) +T3F74 26237:050.765 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26237:050.786 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26237:051.277 Data: 00 00 00 00 +T3F74 26237:051.313 - 0.555ms returns 4 (0x4) +T3F74 26237:051.341 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26237:051.371 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26237:051.949 Data: 00 00 00 00 +T3F74 26237:051.974 - 0.641ms returns 4 (0x4) +T062C 26237:065.092 JLINK_IsHalted() +T062C 26237:066.214 - 1.141ms returns FALSE +T062C 26237:166.498 JLINK_HasError() +T062C 26237:166.596 JLINK_IsHalted() +T062C 26237:167.786 - 1.201ms returns FALSE +T062C 26237:268.665 JLINK_HasError() +T062C 26237:268.713 JLINK_IsHalted() +T062C 26237:269.824 - 1.138ms returns FALSE +T062C 26237:370.841 JLINK_HasError() +T062C 26237:370.884 JLINK_IsHalted() +T062C 26237:371.979 - 1.109ms returns FALSE +T062C 26237:472.842 JLINK_HasError() +T062C 26237:472.885 JLINK_IsHalted() +T062C 26237:474.031 - 1.171ms returns FALSE +T062C 26237:574.659 JLINK_HasError() +T062C 26237:574.702 JLINK_HasError() +T062C 26237:574.725 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26237:574.762 Data: 8D 12 74 01 +T062C 26237:574.793 Debug reg: DWT_CYCCNT +T062C 26237:574.822 - 0.108ms returns 1 (0x1) +T3F74 26237:588.033 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26237:588.086 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26237:589.217 Data: 00 00 80 00 +T3F74 26237:589.249 - 1.225ms returns 4 (0x4) +T3F74 26237:589.288 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26237:589.311 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26237:589.816 Data: 00 00 F0 01 +T3F74 26237:589.841 - 0.561ms returns 4 (0x4) +T3F74 26237:595.647 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26237:595.692 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26237:596.951 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26237:596.982 - 1.342ms returns 16 (0x10) +T3F74 26237:597.006 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26237:597.028 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26237:597.447 Data: 1F 00 00 00 +T3F74 26237:597.485 - 0.487ms returns 4 (0x4) +T3F74 26237:597.511 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26237:597.533 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26237:598.062 Data: 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 ... +T3F74 26237:598.086 - 0.583ms returns 20 (0x14) +T3F74 26237:598.107 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26237:598.126 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26237:598.562 Data: 1F 03 00 00 +T3F74 26237:598.586 - 0.487ms returns 4 (0x4) +T3F74 26237:598.606 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26237:598.627 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26237:599.062 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26237:599.086 - 0.487ms returns 12 (0xC) +T3F74 26237:599.106 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26237:599.125 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26237:599.562 Data: 00 00 00 00 +T3F74 26237:599.586 - 0.488ms returns 4 (0x4) +T3F74 26237:599.607 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26237:599.630 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26237:600.071 Data: 00 00 00 00 +T3F74 26237:600.107 - 0.508ms returns 4 (0x4) +T3F74 26237:600.132 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26237:600.154 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26237:600.596 Data: 00 00 00 00 +T3F74 26237:600.637 - 0.515ms returns 4 (0x4) +T062C 26237:636.507 JLINK_IsHalted() +T062C 26237:637.609 - 1.116ms returns FALSE +T062C 26237:738.345 JLINK_HasError() +T062C 26237:738.387 JLINK_IsHalted() +T062C 26237:739.465 - 1.106ms returns FALSE +T062C 26237:840.011 JLINK_HasError() +T062C 26237:840.062 JLINK_IsHalted() +T062C 26237:841.180 - 1.149ms returns FALSE +T062C 26237:942.073 JLINK_HasError() +T062C 26237:942.125 JLINK_IsHalted() +T062C 26237:943.196 - 1.102ms returns FALSE +T062C 26238:044.123 JLINK_HasError() +T062C 26238:044.175 JLINK_IsHalted() +T062C 26238:045.274 - 1.117ms returns FALSE +T062C 26238:145.430 JLINK_HasError() +T062C 26238:145.517 JLINK_HasError() +T062C 26238:145.561 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26238:145.623 Data: 8D 12 74 01 +T062C 26238:145.683 Debug reg: DWT_CYCCNT +T062C 26238:145.702 - 0.147ms returns 1 (0x1) +T3F74 26238:148.249 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26238:148.283 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26238:149.519 Data: 00 00 80 00 +T3F74 26238:149.600 - 1.379ms returns 4 (0x4) +T3F74 26238:149.662 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26238:149.685 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26238:150.868 Data: 00 00 F0 01 +T3F74 26238:150.901 - 1.247ms returns 4 (0x4) +T3F74 26238:154.538 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26238:154.580 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26238:155.764 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26238:155.797 - 1.269ms returns 16 (0x10) +T3F74 26238:155.823 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26238:155.846 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26238:156.237 Data: 1F 00 00 00 +T3F74 26238:156.258 - 0.441ms returns 4 (0x4) +T3F74 26238:156.290 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26238:156.307 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26238:156.871 Data: 00 00 00 00 00 00 00 00 00 00 00 00 5F 01 00 00 ... +T3F74 26238:156.895 - 0.612ms returns 20 (0x14) +T3F74 26238:156.918 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26238:156.937 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26238:157.371 Data: 1F 03 00 00 +T3F74 26238:157.395 - 0.485ms returns 4 (0x4) +T3F74 26238:157.426 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26238:157.445 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26238:157.867 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26238:157.890 - 0.473ms returns 12 (0xC) +T3F74 26238:157.914 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26238:157.933 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26238:158.368 Data: 00 00 00 00 +T3F74 26238:158.394 - 0.487ms returns 4 (0x4) +T3F74 26238:158.424 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26238:158.443 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26238:158.861 Data: 00 00 00 00 +T3F74 26238:158.884 - 0.468ms returns 4 (0x4) +T3F74 26238:158.907 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26238:158.926 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26238:159.375 Data: 00 00 00 00 +T3F74 26238:159.398 - 0.499ms returns 4 (0x4) +T062C 26238:172.246 JLINK_IsHalted() +T062C 26238:173.488 - 1.285ms returns FALSE +T062C 26238:273.739 JLINK_HasError() +T062C 26238:273.826 JLINK_IsHalted() +T062C 26238:275.138 - 1.353ms returns FALSE +T062C 26238:375.239 JLINK_HasError() +T062C 26238:375.284 JLINK_IsHalted() +T062C 26238:376.350 - 1.084ms returns FALSE +T062C 26238:476.921 JLINK_HasError() +T062C 26238:477.008 JLINK_IsHalted() +T062C 26238:478.090 - 1.101ms returns FALSE +T062C 26238:579.164 JLINK_HasError() +T062C 26238:579.209 JLINK_IsHalted() +T062C 26238:580.334 - 1.147ms returns FALSE +T062C 26238:680.530 JLINK_HasError() +T062C 26238:680.613 JLINK_HasError() +T062C 26238:680.658 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26238:680.714 Data: 8D 12 74 01 +T062C 26238:680.735 Debug reg: DWT_CYCCNT +T062C 26238:680.754 - 0.102ms returns 1 (0x1) +T3F74 26238:683.171 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26238:683.204 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26238:684.449 Data: 00 00 80 00 +T3F74 26238:684.529 - 1.387ms returns 4 (0x4) +T3F74 26238:684.590 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26238:684.613 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26238:685.867 Data: 00 00 F0 01 +T3F74 26238:685.901 - 1.319ms returns 4 (0x4) +T3F74 26238:689.097 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26238:689.125 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26238:690.346 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26238:690.374 - 1.284ms returns 16 (0x10) +T3F74 26238:690.395 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26238:690.420 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26238:690.786 Data: 1E 00 00 00 +T3F74 26238:690.806 - 0.418ms returns 4 (0x4) +T3F74 26238:690.824 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26238:690.840 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26238:691.294 Data: 00 00 00 00 00 00 00 00 00 00 00 00 3D 02 00 00 ... +T3F74 26238:691.314 - 0.497ms returns 20 (0x14) +T3F74 26238:691.331 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26238:691.347 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26238:691.787 Data: 1F 03 00 00 +T3F74 26238:691.807 - 0.482ms returns 4 (0x4) +T3F74 26238:691.824 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26238:691.840 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26238:692.398 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26238:692.438 - 0.645ms returns 12 (0xC) +T3F74 26238:692.490 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26238:692.511 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26238:693.045 Data: 00 00 00 00 +T3F74 26238:693.071 - 0.589ms returns 4 (0x4) +T3F74 26238:693.092 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26238:693.113 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26238:693.543 Data: 00 00 00 00 +T3F74 26238:693.567 - 0.482ms returns 4 (0x4) +T3F74 26238:693.587 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26238:693.606 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26238:694.070 Data: 00 00 00 00 +T3F74 26238:694.090 - 0.509ms returns 4 (0x4) +T062C 26238:713.381 JLINK_IsHalted() +T062C 26238:714.427 - 1.064ms returns FALSE +T062C 26238:815.215 JLINK_HasError() +T062C 26238:815.294 JLINK_IsHalted() +T062C 26238:816.527 - 1.251ms returns FALSE +T062C 26238:916.721 JLINK_HasError() +T062C 26238:916.804 JLINK_IsHalted() +T062C 26238:917.984 - 1.198ms returns FALSE +T062C 26239:018.739 JLINK_HasError() +T062C 26239:018.824 JLINK_IsHalted() +T062C 26239:020.082 - 1.276ms returns FALSE +T062C 26239:120.982 JLINK_HasError() +T062C 26239:121.031 JLINK_IsHalted() +T062C 26239:122.147 - 1.146ms returns FALSE +T062C 26239:222.810 JLINK_HasError() +T062C 26239:222.854 JLINK_HasError() +T062C 26239:222.873 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26239:222.904 Data: 8D 12 74 01 +T062C 26239:222.928 Debug reg: DWT_CYCCNT +T062C 26239:222.951 - 0.085ms returns 1 (0x1) +T3F74 26239:225.179 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26239:225.213 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26239:226.383 Data: 00 00 80 00 +T3F74 26239:226.410 - 1.239ms returns 4 (0x4) +T3F74 26239:226.444 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26239:226.465 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26239:226.848 Data: 00 00 F0 01 +T3F74 26239:226.872 - 0.435ms returns 4 (0x4) +T3F74 26239:230.073 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26239:230.100 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26239:231.277 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26239:231.305 - 1.239ms returns 16 (0x10) +T3F74 26239:231.325 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26239:231.345 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26239:231.719 Data: 1E 00 00 00 +T3F74 26239:231.739 - 0.420ms returns 4 (0x4) +T3F74 26239:231.757 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26239:231.773 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26239:232.248 Data: 00 00 00 00 00 00 00 00 00 00 00 00 BD 00 00 00 ... +T3F74 26239:232.268 - 0.518ms returns 20 (0x14) +T3F74 26239:232.285 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26239:232.301 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26239:232.718 Data: 1F 03 00 00 +T3F74 26239:232.738 - 0.459ms returns 4 (0x4) +T3F74 26239:232.755 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26239:232.771 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26239:233.219 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26239:233.239 - 0.497ms returns 12 (0xC) +T3F74 26239:233.267 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26239:233.283 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26239:233.718 Data: 00 00 00 00 +T3F74 26239:233.738 - 0.478ms returns 4 (0x4) +T3F74 26239:233.755 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26239:233.771 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26239:234.218 Data: 00 00 00 00 +T3F74 26239:234.238 - 0.489ms returns 4 (0x4) +T3F74 26239:234.255 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26239:234.271 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26239:234.717 Data: 00 00 00 00 +T3F74 26239:234.737 - 0.488ms returns 4 (0x4) +T062C 26239:246.050 JLINK_IsHalted() +T062C 26239:247.102 - 1.070ms returns FALSE +T062C 26239:347.302 JLINK_HasError() +T062C 26239:347.462 JLINK_IsHalted() +T062C 26239:348.652 - 1.206ms returns FALSE +T062C 26239:448.860 JLINK_HasError() +T062C 26239:448.940 JLINK_IsHalted() +T062C 26239:450.193 - 1.295ms returns FALSE +T062C 26239:550.435 JLINK_HasError() +T062C 26239:550.510 JLINK_IsHalted() +T062C 26239:551.780 - 1.288ms returns FALSE +T062C 26239:652.145 JLINK_HasError() +T062C 26239:652.189 JLINK_IsHalted() +T062C 26239:653.305 - 1.135ms returns FALSE +T062C 26239:754.099 JLINK_HasError() +T062C 26239:754.185 JLINK_HasError() +T062C 26239:754.230 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26239:754.296 Data: 8D 12 74 01 +T062C 26239:754.316 Debug reg: DWT_CYCCNT +T062C 26239:754.335 - 0.111ms returns 1 (0x1) +T3F74 26239:756.819 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26239:756.856 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26239:758.030 Data: 00 00 80 00 +T3F74 26239:758.065 - 1.254ms returns 4 (0x4) +T3F74 26239:758.105 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26239:758.128 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26239:758.534 Data: 00 00 F0 01 +T3F74 26239:758.558 - 0.461ms returns 4 (0x4) +T3F74 26239:761.542 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26239:761.568 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26239:762.871 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26239:762.929 - 1.395ms returns 16 (0x10) +T3F74 26239:762.956 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26239:762.979 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26239:763.410 Data: 1E 00 00 00 +T3F74 26239:763.434 - 0.486ms returns 4 (0x4) +T3F74 26239:763.457 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26239:763.477 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26239:764.028 Data: 00 00 00 00 00 00 00 00 00 00 00 00 65 00 00 00 ... +T3F74 26239:764.056 - 0.606ms returns 20 (0x14) +T3F74 26239:764.087 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26239:764.103 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26239:764.524 Data: 1F 03 00 00 +T3F74 26239:764.548 - 0.468ms returns 4 (0x4) +T3F74 26239:764.570 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26239:764.590 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26239:765.035 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26239:765.058 - 0.496ms returns 12 (0xC) +T3F74 26239:765.081 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26239:765.102 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26239:765.524 Data: 00 00 00 00 +T3F74 26239:765.547 - 0.474ms returns 4 (0x4) +T3F74 26239:765.570 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26239:765.589 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26239:766.055 Data: 00 00 00 00 +T3F74 26239:766.079 - 0.516ms returns 4 (0x4) +T3F74 26239:766.101 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26239:766.120 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26239:766.527 Data: 00 00 00 00 +T3F74 26239:766.551 - 0.457ms returns 4 (0x4) +T062C 26239:778.852 JLINK_IsHalted() +T062C 26239:779.933 - 1.099ms returns FALSE +T062C 26239:880.395 JLINK_HasError() +T062C 26239:880.440 JLINK_IsHalted() +T062C 26239:881.546 - 1.141ms returns FALSE +T062C 26239:982.025 JLINK_HasError() +T062C 26239:982.064 JLINK_IsHalted() +T062C 26239:983.133 - 1.083ms returns FALSE +T062C 26240:084.111 JLINK_HasError() +T062C 26240:084.184 JLINK_IsHalted() +T062C 26240:085.380 - 1.226ms returns FALSE +T062C 26240:186.117 JLINK_HasError() +T062C 26240:186.165 JLINK_IsHalted() +T062C 26240:187.251 - 1.105ms returns FALSE +T062C 26240:288.108 JLINK_HasError() +T062C 26240:288.154 JLINK_HasError() +T062C 26240:288.173 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26240:288.203 Data: 8D 12 74 01 +T062C 26240:288.227 Debug reg: DWT_CYCCNT +T062C 26240:288.249 - 0.083ms returns 1 (0x1) +T3F74 26240:290.805 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26240:290.853 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26240:291.975 Data: 00 00 80 00 +T3F74 26240:292.019 - 1.222ms returns 4 (0x4) +T3F74 26240:292.065 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26240:292.089 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26240:292.579 Data: 00 00 F0 01 +T3F74 26240:292.603 - 0.546ms returns 4 (0x4) +T3F74 26240:296.110 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26240:296.146 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26240:297.344 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26240:297.378 - 1.276ms returns 16 (0x10) +T3F74 26240:297.403 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26240:297.426 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26240:297.828 Data: 1E 00 00 00 +T3F74 26240:297.852 - 0.457ms returns 4 (0x4) +T3F74 26240:297.873 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26240:297.892 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26240:298.453 Data: 00 00 00 00 00 00 00 00 00 00 00 00 BF 01 00 00 ... +T3F74 26240:298.476 - 0.611ms returns 20 (0x14) +T3F74 26240:298.497 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26240:298.516 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26240:298.953 Data: 1F 03 00 00 +T3F74 26240:298.976 - 0.489ms returns 4 (0x4) +T3F74 26240:298.998 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26240:299.017 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26240:299.452 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26240:299.476 - 0.485ms returns 12 (0xC) +T3F74 26240:299.496 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26240:299.515 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26240:299.952 Data: 00 00 00 00 +T3F74 26240:299.975 - 0.498ms returns 4 (0x4) +T3F74 26240:300.007 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26240:300.025 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26240:300.452 Data: 00 00 00 00 +T3F74 26240:300.475 - 0.476ms returns 4 (0x4) +T3F74 26240:300.500 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26240:300.519 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26240:300.953 Data: 00 00 00 00 +T3F74 26240:300.976 - 0.486ms returns 4 (0x4) +T062C 26240:313.528 JLINK_IsHalted() +T062C 26240:314.587 - 1.077ms returns FALSE +T062C 26240:414.810 JLINK_HasError() +T062C 26240:414.900 JLINK_IsHalted() +T062C 26240:416.107 - 1.226ms returns FALSE +T062C 26240:516.337 JLINK_HasError() +T062C 26240:516.409 JLINK_IsHalted() +T062C 26240:517.657 - 1.265ms returns FALSE +T062C 26240:618.346 JLINK_HasError() +T062C 26240:618.398 JLINK_IsHalted() +T062C 26240:619.662 - 1.282ms returns FALSE +T062C 26240:720.511 JLINK_HasError() +T062C 26240:720.595 JLINK_IsHalted() +T062C 26240:721.688 - 1.116ms returns FALSE +T062C 26240:821.989 JLINK_HasError() +T062C 26240:822.034 JLINK_HasError() +T062C 26240:822.053 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26240:822.083 Data: 8D 12 74 01 +T062C 26240:822.107 Debug reg: DWT_CYCCNT +T062C 26240:822.129 - 0.083ms returns 1 (0x1) +T3F74 26240:824.846 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26240:824.880 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26240:826.036 Data: 00 00 80 00 +T3F74 26240:826.071 - 1.232ms returns 4 (0x4) +T3F74 26240:826.116 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26240:826.144 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26240:826.634 Data: 00 00 F0 01 +T3F74 26240:826.658 - 0.550ms returns 4 (0x4) +T3F74 26240:829.993 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26240:830.021 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26240:831.280 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26240:831.309 - 1.322ms returns 16 (0x10) +T3F74 26240:831.329 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26240:831.349 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26240:831.752 Data: 1F 00 00 00 +T3F74 26240:831.773 - 0.450ms returns 4 (0x4) +T3F74 26240:831.790 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26240:831.806 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26240:832.269 Data: 00 00 00 00 00 00 00 00 00 00 00 00 5F 01 00 00 ... +T3F74 26240:832.293 - 0.510ms returns 20 (0x14) +T3F74 26240:832.313 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26240:832.332 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26240:832.762 Data: 1F 03 00 00 +T3F74 26240:832.785 - 0.480ms returns 4 (0x4) +T3F74 26240:832.805 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26240:832.824 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26240:833.262 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26240:833.286 - 0.488ms returns 12 (0xC) +T3F74 26240:833.306 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26240:833.329 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26240:833.755 Data: 00 00 00 00 +T3F74 26240:833.776 - 0.476ms returns 4 (0x4) +T3F74 26240:833.793 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26240:833.809 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26240:834.250 Data: 00 00 00 00 +T3F74 26240:834.270 - 0.484ms returns 4 (0x4) +T3F74 26240:834.287 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26240:834.303 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26240:834.751 Data: 00 00 00 00 +T3F74 26240:834.771 - 0.490ms returns 4 (0x4) +T062C 26240:853.658 JLINK_IsHalted() +T062C 26240:854.770 - 1.132ms returns FALSE +T062C 26240:954.942 JLINK_HasError() +T062C 26240:955.028 JLINK_IsHalted() +T062C 26240:956.223 - 1.223ms returns FALSE +T062C 26241:057.014 JLINK_HasError() +T062C 26241:057.088 JLINK_IsHalted() +T062C 26241:058.241 - 1.173ms returns FALSE +T062C 26241:159.022 JLINK_HasError() +T062C 26241:159.095 JLINK_IsHalted() +T062C 26241:160.333 - 1.255ms returns FALSE +T062C 26241:260.953 JLINK_HasError() +T062C 26241:261.023 JLINK_IsHalted() +T062C 26241:262.293 - 1.287ms returns FALSE +T062C 26241:362.688 JLINK_HasError() +T062C 26241:362.734 JLINK_HasError() +T062C 26241:362.753 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26241:362.782 Data: 8D 12 74 01 +T062C 26241:362.806 Debug reg: DWT_CYCCNT +T062C 26241:362.828 - 0.082ms returns 1 (0x1) +T3F74 26241:365.071 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26241:365.105 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26241:366.292 Data: 00 00 80 00 +T3F74 26241:366.351 - 1.286ms returns 4 (0x4) +T3F74 26241:366.385 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26241:366.405 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26241:366.807 Data: 00 00 F0 01 +T3F74 26241:366.828 - 0.450ms returns 4 (0x4) +T3F74 26241:370.369 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26241:370.400 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26241:371.633 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26241:371.667 - 1.306ms returns 16 (0x10) +T3F74 26241:371.691 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26241:371.713 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26241:372.195 Data: 1E 00 00 00 +T3F74 26241:372.219 - 0.536ms returns 4 (0x4) +T3F74 26241:372.240 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26241:372.259 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26241:372.843 Data: 00 00 00 00 00 00 00 00 00 00 00 00 ED 01 00 00 ... +T3F74 26241:372.874 - 0.640ms returns 20 (0x14) +T3F74 26241:372.891 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26241:372.907 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26241:373.313 Data: 1F 03 00 00 +T3F74 26241:373.337 - 0.454ms returns 4 (0x4) +T3F74 26241:373.358 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26241:373.377 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26241:373.814 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26241:373.838 - 0.487ms returns 12 (0xC) +T3F74 26241:373.858 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26241:373.877 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26241:374.315 Data: 00 00 00 00 +T3F74 26241:374.339 - 0.489ms returns 4 (0x4) +T3F74 26241:374.359 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26241:374.378 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26241:374.808 Data: 00 00 00 00 +T3F74 26241:374.828 - 0.475ms returns 4 (0x4) +T3F74 26241:374.845 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26241:374.861 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26241:375.308 Data: 00 00 00 00 +T3F74 26241:375.328 - 0.490ms returns 4 (0x4) +T062C 26241:394.521 JLINK_IsHalted() +T062C 26241:395.570 - 1.066ms returns FALSE +T062C 26241:496.032 JLINK_HasError() +T062C 26241:496.113 JLINK_IsHalted() +T062C 26241:497.295 - 1.231ms returns FALSE +T062C 26241:597.960 JLINK_HasError() +T062C 26241:597.987 JLINK_IsHalted() +T062C 26241:599.123 - 1.154ms returns FALSE +T062C 26241:699.434 JLINK_HasError() +T062C 26241:699.508 JLINK_IsHalted() +T062C 26241:700.659 - 1.169ms returns FALSE +T062C 26241:801.521 JLINK_HasError() +T062C 26241:801.566 JLINK_IsHalted() +T062C 26241:802.645 - 1.110ms returns FALSE +T062C 26241:902.864 JLINK_HasError() +T062C 26241:902.916 JLINK_HasError() +T062C 26241:902.934 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26241:902.966 Data: 8D 12 74 01 +T062C 26241:902.990 Debug reg: DWT_CYCCNT +T062C 26241:903.012 - 0.085ms returns 1 (0x1) +T3F74 26241:908.137 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26241:908.181 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26241:909.313 Data: 00 00 80 00 +T3F74 26241:909.338 - 1.208ms returns 4 (0x4) +T3F74 26241:909.371 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26241:909.391 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26241:909.868 Data: 00 00 F0 01 +T3F74 26241:909.892 - 0.529ms returns 4 (0x4) +T3F74 26241:913.151 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26241:913.179 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26241:914.418 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26241:914.447 - 1.302ms returns 16 (0x10) +T3F74 26241:914.467 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26241:914.486 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26241:914.861 Data: 1E 00 00 00 +T3F74 26241:914.881 - 0.421ms returns 4 (0x4) +T3F74 26241:914.899 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26241:914.915 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26241:915.358 Data: 00 00 00 00 00 00 00 00 00 00 00 00 69 01 00 00 ... +T3F74 26241:915.378 - 0.486ms returns 20 (0x14) +T3F74 26241:915.396 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26241:915.412 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26241:915.892 Data: 1F 03 00 00 +T3F74 26241:915.912 - 0.523ms returns 4 (0x4) +T3F74 26241:915.929 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26241:915.945 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26241:916.358 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26241:916.378 - 0.455ms returns 12 (0xC) +T3F74 26241:916.395 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26241:916.411 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26241:916.990 Data: 00 00 00 00 +T3F74 26241:917.037 - 0.651ms returns 4 (0x4) +T3F74 26241:917.065 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26241:917.095 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26241:917.638 Data: 00 00 00 00 +T3F74 26241:917.668 - 0.611ms returns 4 (0x4) +T3F74 26241:917.690 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26241:917.711 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26241:918.111 Data: 00 00 00 00 +T3F74 26241:918.135 - 0.452ms returns 4 (0x4) +T062C 26241:931.200 JLINK_IsHalted() +T062C 26241:932.249 - 1.060ms returns FALSE +T062C 26242:032.839 JLINK_HasError() +T062C 26242:032.886 JLINK_IsHalted() +T062C 26242:033.988 - 1.119ms returns FALSE +T062C 26242:134.203 JLINK_HasError() +T062C 26242:134.285 JLINK_IsHalted() +T062C 26242:135.426 - 1.182ms returns FALSE +T062C 26242:235.895 JLINK_HasError() +T062C 26242:235.979 JLINK_IsHalted() +T062C 26242:237.227 - 1.267ms returns FALSE +T062C 26242:337.373 JLINK_HasError() +T062C 26242:337.452 JLINK_IsHalted() +T062C 26242:338.573 - 1.139ms returns FALSE +T062C 26242:439.104 JLINK_HasError() +T062C 26242:439.151 JLINK_HasError() +T062C 26242:439.169 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26242:439.199 Data: 8D 12 74 01 +T062C 26242:439.232 Debug reg: DWT_CYCCNT +T062C 26242:439.257 - 0.095ms returns 1 (0x1) +T3F74 26242:441.487 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26242:441.522 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26242:442.670 Data: 00 00 80 00 +T3F74 26242:442.705 - 1.226ms returns 4 (0x4) +T3F74 26242:442.743 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26242:442.766 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26242:443.175 Data: 00 00 F0 01 +T3F74 26242:443.199 - 0.463ms returns 4 (0x4) +T3F74 26242:446.208 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26242:446.235 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26242:447.468 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26242:447.497 - 1.295ms returns 16 (0x10) +T3F74 26242:447.517 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26242:447.537 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26242:447.911 Data: 1E 00 00 00 +T3F74 26242:447.932 - 0.421ms returns 4 (0x4) +T3F74 26242:447.949 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26242:447.966 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26242:448.546 Data: 00 00 00 00 00 00 00 00 00 00 00 00 85 02 00 00 ... +T3F74 26242:448.570 - 0.628ms returns 20 (0x14) +T3F74 26242:448.590 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26242:448.609 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26242:449.042 Data: 1F 03 00 00 +T3F74 26242:449.065 - 0.483ms returns 4 (0x4) +T3F74 26242:449.085 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26242:449.106 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26242:449.542 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26242:449.565 - 0.487ms returns 12 (0xC) +T3F74 26242:449.585 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26242:449.604 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26242:450.040 Data: 00 00 00 00 +T3F74 26242:450.064 - 0.487ms returns 4 (0x4) +T3F74 26242:450.084 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26242:450.104 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26242:450.545 Data: 00 00 00 00 +T3F74 26242:450.571 - 0.495ms returns 4 (0x4) +T3F74 26242:450.593 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26242:450.613 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26242:451.046 Data: 00 00 00 00 +T3F74 26242:451.069 - 0.484ms returns 4 (0x4) +T062C 26242:462.410 JLINK_IsHalted() +T062C 26242:463.552 - 1.161ms returns FALSE +T062C 26242:563.712 JLINK_HasError() +T062C 26242:563.762 JLINK_IsHalted() +T062C 26242:564.796 - 1.053ms returns FALSE +T062C 26242:666.000 JLINK_HasError() +T062C 26242:666.074 JLINK_IsHalted() +T062C 26242:667.265 - 1.239ms returns FALSE +T062C 26242:767.772 JLINK_HasError() +T062C 26242:767.850 JLINK_IsHalted() +T062C 26242:769.097 - 1.265ms returns FALSE +T062C 26242:869.947 JLINK_HasError() +T062C 26242:869.993 JLINK_IsHalted() +T062C 26242:871.167 - 1.189ms returns FALSE +T062C 26242:971.952 JLINK_HasError() +T062C 26242:971.993 JLINK_HasError() +T062C 26242:972.012 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26242:972.074 Data: 8D 12 74 01 +T062C 26242:972.120 Debug reg: DWT_CYCCNT +T062C 26242:972.159 - 0.157ms returns 1 (0x1) +T3F74 26242:976.250 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26242:976.315 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26242:977.552 Data: 00 00 80 00 +T3F74 26242:977.601 - 1.364ms returns 4 (0x4) +T3F74 26242:977.668 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26242:977.701 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26242:978.274 Data: 00 00 F0 01 +T3F74 26242:978.327 - 0.672ms returns 4 (0x4) +T3F74 26242:984.318 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26242:984.409 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26242:985.685 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26242:985.731 - 1.423ms returns 16 (0x10) +T3F74 26242:985.763 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26242:985.797 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26242:986.392 Data: 1E 00 00 00 +T3F74 26242:986.432 - 0.681ms returns 4 (0x4) +T3F74 26242:986.467 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26242:986.499 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26242:987.138 Data: 00 00 00 00 00 00 00 00 00 00 00 00 17 03 00 00 ... +T3F74 26242:987.176 - 0.721ms returns 20 (0x14) +T3F74 26242:987.208 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26242:987.239 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26242:987.771 Data: 1F 03 00 00 +T3F74 26242:987.817 - 0.620ms returns 4 (0x4) +T3F74 26242:987.849 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26242:987.878 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26242:988.388 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26242:988.425 - 0.586ms returns 12 (0xC) +T3F74 26242:988.453 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26242:988.511 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26242:989.002 Data: 00 00 00 00 +T3F74 26242:989.045 - 0.605ms returns 4 (0x4) +T3F74 26242:989.080 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26242:989.112 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26242:989.630 Data: 00 00 00 00 +T3F74 26242:989.665 - 0.595ms returns 4 (0x4) +T3F74 26242:989.691 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26242:989.719 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26242:990.275 Data: 00 00 00 00 +T3F74 26242:990.322 - 0.643ms returns 4 (0x4) +T062C 26243:013.040 JLINK_IsHalted() +T062C 26243:014.177 - 1.152ms returns FALSE +T062C 26243:115.017 JLINK_HasError() +T062C 26243:115.105 JLINK_IsHalted() +T062C 26243:116.279 - 1.192ms returns FALSE +T062C 26243:217.004 JLINK_HasError() +T062C 26243:217.046 JLINK_IsHalted() +T062C 26243:218.078 - 1.042ms returns FALSE +T062C 26243:318.948 JLINK_HasError() +T062C 26243:319.005 JLINK_IsHalted() +T062C 26243:320.059 - 1.083ms returns FALSE +T062C 26243:420.980 JLINK_HasError() +T062C 26243:421.033 JLINK_IsHalted() +T062C 26243:422.053 - 1.034ms returns FALSE +T062C 26243:522.983 JLINK_HasError() +T062C 26243:523.398 JLINK_HasError() +T062C 26243:523.428 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26243:523.472 Data: 8D 12 74 01 +T062C 26243:523.501 Debug reg: DWT_CYCCNT +T062C 26243:523.532 - 0.113ms returns 1 (0x1) +T3F74 26243:528.861 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26243:528.923 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26243:530.135 Data: 00 00 80 00 +T3F74 26243:530.173 - 1.320ms returns 4 (0x4) +T3F74 26243:530.254 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26243:530.279 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26243:531.416 Data: 00 00 F0 01 +T3F74 26243:531.446 - 1.200ms returns 4 (0x4) +T3F74 26243:535.143 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26243:535.176 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26243:536.415 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26243:536.445 - 1.309ms returns 16 (0x10) +T3F74 26243:536.468 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26243:536.489 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26243:536.897 Data: 1E 00 00 00 +T3F74 26243:536.921 - 0.462ms returns 4 (0x4) +T3F74 26243:536.943 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26243:536.962 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26243:537.523 Data: 00 00 00 00 00 00 00 00 00 00 00 00 CB 02 00 00 ... +T3F74 26243:537.547 - 0.612ms returns 20 (0x14) +T3F74 26243:537.567 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26243:537.586 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26243:538.023 Data: 1F 03 00 00 +T3F74 26243:538.048 - 0.488ms returns 4 (0x4) +T3F74 26243:538.069 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26243:538.088 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26243:538.522 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26243:538.546 - 0.485ms returns 12 (0xC) +T3F74 26243:538.566 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26243:538.585 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26243:539.081 Data: 00 00 00 00 +T3F74 26243:539.115 - 0.559ms returns 4 (0x4) +T3F74 26243:539.142 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26243:539.164 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26243:539.648 Data: 00 00 00 00 +T3F74 26243:539.672 - 0.538ms returns 4 (0x4) +T3F74 26243:539.692 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26243:539.711 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26243:540.273 Data: 00 00 00 00 +T3F74 26243:540.298 - 0.613ms returns 4 (0x4) +T062C 26243:553.304 JLINK_IsHalted() +T062C 26243:554.418 - 1.140ms returns FALSE +T062C 26243:654.635 JLINK_HasError() +T062C 26243:654.685 JLINK_IsHalted() +T062C 26243:655.786 - 1.115ms returns FALSE +T062C 26243:756.734 JLINK_HasError() +T062C 26243:756.817 JLINK_IsHalted() +T062C 26243:757.884 - 1.085ms returns FALSE +T062C 26243:858.320 JLINK_HasError() +T062C 26243:858.369 JLINK_IsHalted() +T062C 26243:859.503 - 1.156ms returns FALSE +T062C 26243:960.314 JLINK_HasError() +T062C 26243:960.370 JLINK_IsHalted() +T062C 26243:961.514 - 1.184ms returns FALSE +T062C 26244:062.344 JLINK_HasError() +T062C 26244:062.394 JLINK_HasError() +T062C 26244:062.443 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26244:062.482 Data: 8D 12 74 01 +T062C 26244:062.513 Debug reg: DWT_CYCCNT +T062C 26244:062.544 - 0.111ms returns 1 (0x1) +T3F74 26244:068.913 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26244:068.974 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26244:070.106 Data: 00 00 80 00 +T3F74 26244:070.147 - 1.243ms returns 4 (0x4) +T3F74 26244:070.192 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26244:070.218 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26244:070.715 Data: 00 00 F0 01 +T3F74 26244:070.748 - 0.567ms returns 4 (0x4) +T3F74 26244:074.912 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26244:074.981 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26244:076.225 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26244:076.254 - 1.351ms returns 16 (0x10) +T3F74 26244:076.279 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26244:076.306 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26244:076.745 Data: 1E 00 00 00 +T3F74 26244:076.794 - 0.527ms returns 4 (0x4) +T3F74 26244:076.834 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26244:076.864 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26244:077.464 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D9 01 00 00 ... +T3F74 26244:077.500 - 0.677ms returns 20 (0x14) +T3F74 26244:077.532 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26244:077.562 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26244:078.083 Data: 1F 03 00 00 +T3F74 26244:078.109 - 0.585ms returns 4 (0x4) +T3F74 26244:078.131 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26244:078.163 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26244:078.723 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26244:078.749 - 0.626ms returns 12 (0xC) +T3F74 26244:078.771 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26244:078.792 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26244:079.204 Data: 00 00 00 00 +T3F74 26244:079.231 - 0.468ms returns 4 (0x4) +T3F74 26244:079.252 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26244:079.272 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26244:079.701 Data: 00 00 00 00 +T3F74 26244:079.725 - 0.480ms returns 4 (0x4) +T3F74 26244:079.745 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26244:079.764 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26244:080.201 Data: 00 00 00 00 +T3F74 26244:080.225 - 0.489ms returns 4 (0x4) +T062C 26244:094.731 JLINK_IsHalted() +T062C 26244:095.859 - 1.156ms returns FALSE +T062C 26244:196.320 JLINK_HasError() +T062C 26244:196.363 JLINK_IsHalted() +T062C 26244:197.454 - 1.105ms returns FALSE +T062C 26244:298.449 JLINK_HasError() +T062C 26244:298.513 JLINK_IsHalted() +T062C 26244:299.557 - 1.062ms returns FALSE +T062C 26244:400.498 JLINK_HasError() +T062C 26244:400.571 JLINK_IsHalted() +T062C 26244:401.751 - 1.223ms returns FALSE +T062C 26244:502.447 JLINK_HasError() +T062C 26244:502.543 JLINK_IsHalted() +T062C 26244:503.663 - 1.131ms returns FALSE +T062C 26244:604.407 JLINK_HasError() +T062C 26244:604.461 JLINK_HasError() +T062C 26244:604.480 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26244:604.510 Data: 8D 12 74 01 +T062C 26244:604.535 Debug reg: DWT_CYCCNT +T062C 26244:604.557 - 0.084ms returns 1 (0x1) +T3F74 26244:607.218 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26244:607.263 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26244:608.403 Data: 00 00 80 00 +T3F74 26244:608.432 - 1.222ms returns 4 (0x4) +T3F74 26244:608.469 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26244:608.492 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26244:608.963 Data: 00 00 F0 01 +T3F74 26244:608.986 - 0.525ms returns 4 (0x4) +T3F74 26244:612.479 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26244:612.511 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26244:613.703 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26244:613.737 - 1.266ms returns 16 (0x10) +T3F74 26244:613.761 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26244:613.784 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26244:614.256 Data: 1E 00 00 00 +T3F74 26244:614.281 - 0.527ms returns 4 (0x4) +T3F74 26244:614.301 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26244:614.321 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26244:614.898 Data: 00 00 00 00 00 00 00 00 00 00 00 00 8D 01 00 00 ... +T3F74 26244:614.926 - 0.633ms returns 20 (0x14) +T3F74 26244:614.948 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26244:614.968 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26244:615.380 Data: 1F 03 00 00 +T3F74 26244:615.404 - 0.463ms returns 4 (0x4) +T3F74 26244:615.424 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26244:615.443 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26244:615.879 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26244:615.903 - 0.486ms returns 12 (0xC) +T3F74 26244:615.923 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26244:615.942 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26244:616.380 Data: 00 00 00 00 +T3F74 26244:616.403 - 0.488ms returns 4 (0x4) +T3F74 26244:616.424 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26244:616.443 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26244:616.879 Data: 00 00 00 00 +T3F74 26244:616.902 - 0.486ms returns 4 (0x4) +T3F74 26244:616.922 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26244:616.941 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26244:617.380 Data: 00 00 00 00 +T3F74 26244:617.404 - 0.497ms returns 4 (0x4) +T062C 26244:630.201 JLINK_IsHalted() +T062C 26244:631.329 - 1.151ms returns FALSE +T062C 26244:732.159 JLINK_HasError() +T062C 26244:732.207 JLINK_IsHalted() +T062C 26244:733.284 - 1.107ms returns FALSE +T062C 26244:833.996 JLINK_HasError() +T062C 26244:834.055 JLINK_IsHalted() +T062C 26244:835.170 - 1.133ms returns FALSE +T062C 26244:935.884 JLINK_HasError() +T062C 26244:935.947 JLINK_IsHalted() +T062C 26244:937.141 - 1.208ms returns FALSE +T062C 26245:037.885 JLINK_HasError() +T062C 26245:037.940 JLINK_IsHalted() +T062C 26245:038.987 - 1.066ms returns FALSE +T062C 26245:139.910 JLINK_HasError() +T062C 26245:139.955 JLINK_HasError() +T062C 26245:139.971 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26245:139.997 Data: 8D 12 74 01 +T062C 26245:140.018 Debug reg: DWT_CYCCNT +T062C 26245:140.037 - 0.072ms returns 1 (0x1) +T3F74 26245:142.863 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26245:142.898 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26245:143.968 Data: 00 00 80 00 +T3F74 26245:144.003 - 1.148ms returns 4 (0x4) +T3F74 26245:144.043 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26245:144.066 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26245:144.564 Data: 00 00 F0 01 +T3F74 26245:144.588 - 0.553ms returns 4 (0x4) +T3F74 26245:147.643 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26245:147.671 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26245:148.845 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26245:148.873 - 1.239ms returns 16 (0x10) +T3F74 26245:148.896 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26245:148.919 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26245:149.308 Data: 1E 00 00 00 +T3F74 26245:149.333 - 0.444ms returns 4 (0x4) +T3F74 26245:149.354 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26245:149.373 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26245:149.934 Data: 00 00 00 00 00 00 00 00 00 00 00 00 0F 02 00 00 ... +T3F74 26245:149.959 - 0.612ms returns 20 (0x14) +T3F74 26245:149.979 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26245:149.999 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26245:150.433 Data: 1F 03 00 00 +T3F74 26245:150.457 - 0.486ms returns 4 (0x4) +T3F74 26245:150.478 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26245:150.497 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26245:150.934 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26245:150.958 - 0.488ms returns 12 (0xC) +T3F74 26245:150.979 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26245:150.998 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26245:151.433 Data: 00 00 00 00 +T3F74 26245:151.457 - 0.486ms returns 4 (0x4) +T3F74 26245:151.478 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26245:151.497 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26245:151.934 Data: 00 00 00 00 +T3F74 26245:151.959 - 0.489ms returns 4 (0x4) +T3F74 26245:151.979 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26245:151.999 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26245:152.432 Data: 00 00 00 00 +T3F74 26245:152.456 - 0.485ms returns 4 (0x4) +T062C 26245:165.847 JLINK_IsHalted() +T062C 26245:166.958 - 1.131ms returns FALSE +T062C 26245:267.989 JLINK_HasError() +T062C 26245:268.075 JLINK_IsHalted() +T062C 26245:269.185 - 1.129ms returns FALSE +T062C 26245:369.873 JLINK_HasError() +T062C 26245:369.921 JLINK_IsHalted() +T062C 26245:371.042 - 1.136ms returns FALSE +T062C 26245:471.869 JLINK_HasError() +T062C 26245:471.923 JLINK_IsHalted() +T062C 26245:473.047 - 1.159ms returns FALSE +T062C 26245:573.934 JLINK_HasError() +T062C 26245:574.021 JLINK_IsHalted() +T062C 26245:575.151 - 1.157ms returns FALSE +T062C 26245:675.586 JLINK_HasError() +T062C 26245:675.734 JLINK_HasError() +T062C 26245:675.787 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26245:675.849 Data: 8D 12 74 01 +T062C 26245:675.910 Debug reg: DWT_CYCCNT +T062C 26245:675.941 - 0.167ms returns 1 (0x1) +T3F74 26245:679.660 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26245:679.726 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26245:680.802 Data: 00 00 80 00 +T3F74 26245:680.849 - 1.198ms returns 4 (0x4) +T3F74 26245:680.905 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26245:681.009 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26245:682.143 Data: 00 00 F0 01 +T3F74 26245:682.174 - 1.277ms returns 4 (0x4) +T3F74 26245:687.637 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26245:687.730 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26245:689.026 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26245:689.064 - 1.439ms returns 16 (0x10) +T3F74 26245:689.095 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26245:689.122 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26245:689.620 Data: 1E 00 00 00 +T3F74 26245:689.653 - 0.569ms returns 4 (0x4) +T3F74 26245:689.681 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26245:689.706 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26245:690.239 Data: 00 00 00 00 00 00 00 00 00 00 00 00 BD 00 00 00 ... +T3F74 26245:690.266 - 0.593ms returns 20 (0x14) +T3F74 26245:690.288 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26245:690.309 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26245:690.752 Data: 1F 03 00 00 +T3F74 26245:690.778 - 0.498ms returns 4 (0x4) +T3F74 26245:690.800 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26245:690.821 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26245:691.234 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26245:691.260 - 0.467ms returns 12 (0xC) +T3F74 26245:691.282 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26245:691.302 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26245:691.936 Data: 00 00 00 00 +T3F74 26245:691.990 - 0.716ms returns 4 (0x4) +T3F74 26245:692.050 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26245:692.086 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26245:693.116 Data: 00 00 00 00 +T3F74 26245:693.152 - 1.110ms returns 4 (0x4) +T3F74 26245:693.177 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26245:693.199 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26245:693.754 Data: 00 00 00 00 +T3F74 26245:693.778 - 0.609ms returns 4 (0x4) +T062C 26245:707.504 JLINK_IsHalted() +T062C 26245:708.634 - 1.155ms returns FALSE +T062C 26245:809.323 JLINK_HasError() +T062C 26245:809.372 JLINK_IsHalted() +T062C 26245:810.490 - 1.127ms returns FALSE +T062C 26245:911.306 JLINK_HasError() +T062C 26245:911.355 JLINK_IsHalted() +T062C 26245:912.479 - 1.135ms returns FALSE +T062C 26246:013.343 JLINK_HasError() +T062C 26246:013.391 JLINK_IsHalted() +T062C 26246:014.524 - 1.160ms returns FALSE +T062C 26246:115.299 JLINK_HasError() +T062C 26246:115.363 JLINK_IsHalted() +T062C 26246:116.456 - 1.125ms returns FALSE +T062C 26246:217.314 JLINK_HasError() +T062C 26246:217.374 JLINK_HasError() +T062C 26246:217.403 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26246:217.441 Data: 8D 12 74 01 +T062C 26246:217.474 Debug reg: DWT_CYCCNT +T062C 26246:217.513 - 0.119ms returns 1 (0x1) +T3F74 26246:220.875 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26246:220.939 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26246:222.092 Data: 00 00 80 00 +T3F74 26246:222.140 - 1.278ms returns 4 (0x4) +T3F74 26246:222.194 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26246:222.227 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26246:222.727 Data: 00 00 F0 01 +T3F74 26246:222.790 - 0.607ms returns 4 (0x4) +T3F74 26246:228.005 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26246:228.061 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26246:229.344 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26246:229.382 - 1.386ms returns 16 (0x10) +T3F74 26246:229.409 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26246:229.434 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26246:229.919 Data: 1F 00 00 00 +T3F74 26246:229.945 - 0.553ms returns 4 (0x4) +T3F74 26246:229.981 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26246:230.003 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26246:230.569 Data: 00 00 00 00 00 00 00 00 00 00 00 00 8D 01 00 00 ... +T3F74 26246:230.597 - 0.625ms returns 20 (0x14) +T3F74 26246:230.621 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26246:230.644 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26246:231.231 Data: 1F 03 00 00 +T3F74 26246:231.283 - 0.672ms returns 4 (0x4) +T3F74 26246:231.314 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26246:231.369 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26246:232.734 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26246:232.772 - 1.469ms returns 12 (0xC) +T3F74 26246:232.826 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26246:232.853 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26246:233.326 Data: 00 00 00 00 +T3F74 26246:233.366 - 0.550ms returns 4 (0x4) +T3F74 26246:233.394 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26246:233.422 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26246:233.968 Data: 00 00 00 00 +T3F74 26246:234.003 - 0.621ms returns 4 (0x4) +T3F74 26246:234.034 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26246:234.062 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26246:234.572 Data: 00 00 00 00 +T3F74 26246:234.606 - 0.582ms returns 4 (0x4) +T062C 26246:266.414 JLINK_IsHalted() +T062C 26246:267.575 - 1.193ms returns FALSE +T062C 26246:368.305 JLINK_HasError() +T062C 26246:368.352 JLINK_IsHalted() +T062C 26246:369.430 - 1.090ms returns FALSE +T062C 26246:470.267 JLINK_HasError() +T062C 26246:470.311 JLINK_IsHalted() +T062C 26246:471.419 - 1.138ms returns FALSE +T062C 26246:571.857 JLINK_HasError() +T062C 26246:571.943 JLINK_IsHalted() +T062C 26246:573.252 - 1.358ms returns FALSE +T062C 26246:673.849 JLINK_HasError() +T062C 26246:673.933 JLINK_IsHalted() +T062C 26246:675.159 - 1.244ms returns FALSE +T062C 26246:775.305 JLINK_HasError() +T062C 26246:775.351 JLINK_HasError() +T062C 26246:775.373 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26246:775.402 Data: 8D 12 74 01 +T062C 26246:775.426 Debug reg: DWT_CYCCNT +T062C 26246:775.449 - 0.083ms returns 1 (0x1) +T3F74 26246:778.019 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26246:778.056 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26246:779.099 Data: 00 00 80 00 +T3F74 26246:779.120 - 1.108ms returns 4 (0x4) +T3F74 26246:779.149 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26246:779.166 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26246:779.624 Data: 00 00 F0 01 +T3F74 26246:779.692 - 0.554ms returns 4 (0x4) +T3F74 26246:782.954 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26246:782.988 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26246:784.235 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26246:784.269 - 1.324ms returns 16 (0x10) +T3F74 26246:784.294 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26246:784.323 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26246:784.715 Data: 1E 00 00 00 +T3F74 26246:784.736 - 0.449ms returns 4 (0x4) +T3F74 26246:784.754 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26246:784.771 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26246:785.215 Data: 00 00 00 00 00 00 00 00 00 00 00 00 93 00 00 00 ... +T3F74 26246:785.236 - 0.489ms returns 20 (0x14) +T3F74 26246:785.254 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26246:785.271 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26246:785.714 Data: 1F 03 00 00 +T3F74 26246:785.735 - 0.488ms returns 4 (0x4) +T3F74 26246:785.753 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26246:785.769 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26246:786.215 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26246:786.236 - 0.490ms returns 12 (0xC) +T3F74 26246:786.253 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26246:786.270 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26246:786.709 Data: 00 00 00 00 +T3F74 26246:786.730 - 0.483ms returns 4 (0x4) +T3F74 26246:786.748 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26246:786.764 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26246:787.218 Data: 00 00 00 00 +T3F74 26246:787.239 - 0.498ms returns 4 (0x4) +T3F74 26246:787.256 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26246:787.273 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26246:787.709 Data: 00 00 00 00 +T3F74 26246:787.730 - 0.480ms returns 4 (0x4) +T062C 26246:807.498 JLINK_IsHalted() +T062C 26246:808.615 - 1.135ms returns FALSE +T062C 26246:908.818 JLINK_HasError() +T062C 26246:908.904 JLINK_IsHalted() +T062C 26246:909.964 - 1.069ms returns FALSE +T062C 26247:010.696 JLINK_HasError() +T062C 26247:010.782 JLINK_IsHalted() +T062C 26247:012.045 - 1.305ms returns FALSE +T062C 26247:112.726 JLINK_HasError() +T062C 26247:112.809 JLINK_IsHalted() +T062C 26247:114.017 - 1.250ms returns FALSE +T062C 26247:215.150 JLINK_HasError() +T062C 26247:215.205 JLINK_IsHalted() +T062C 26247:216.300 - 1.109ms returns FALSE +T062C 26247:317.163 JLINK_HasError() +T062C 26247:317.248 JLINK_HasError() +T062C 26247:317.267 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26247:317.298 Data: 8D 12 74 01 +T062C 26247:317.323 Debug reg: DWT_CYCCNT +T062C 26247:317.344 - 0.085ms returns 1 (0x1) +T3F74 26247:320.615 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26247:320.654 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26247:321.844 Data: 00 00 80 00 +T3F74 26247:321.879 - 1.272ms returns 4 (0x4) +T3F74 26247:321.920 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26247:321.944 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26247:322.396 Data: 00 00 F0 01 +T3F74 26247:322.421 - 0.508ms returns 4 (0x4) +T3F74 26247:325.951 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26247:325.983 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26247:327.160 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26247:327.188 - 1.244ms returns 16 (0x10) +T3F74 26247:327.211 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26247:327.232 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26247:327.877 Data: 1E 00 00 00 +T3F74 26247:327.902 - 0.699ms returns 4 (0x4) +T3F74 26247:327.923 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26247:327.942 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26247:328.394 Data: 00 00 00 00 00 00 00 00 00 00 00 00 C3 01 00 00 ... +T3F74 26247:328.418 - 0.503ms returns 20 (0x14) +T3F74 26247:328.438 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26247:328.458 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26247:328.894 Data: 1F 03 00 00 +T3F74 26247:328.918 - 0.487ms returns 4 (0x4) +T3F74 26247:328.938 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26247:328.957 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26247:329.394 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26247:329.417 - 0.487ms returns 12 (0xC) +T3F74 26247:329.437 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26247:329.456 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26247:329.894 Data: 00 00 00 00 +T3F74 26247:329.917 - 0.488ms returns 4 (0x4) +T3F74 26247:329.937 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26247:329.956 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26247:330.392 Data: 00 00 00 00 +T3F74 26247:330.416 - 0.487ms returns 4 (0x4) +T3F74 26247:330.436 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26247:330.455 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26247:330.892 Data: 00 00 00 00 +T3F74 26247:330.916 - 0.487ms returns 4 (0x4) +T062C 26247:344.305 JLINK_IsHalted() +T062C 26247:345.529 - 1.242ms returns FALSE +T062C 26247:446.149 JLINK_HasError() +T062C 26247:446.193 JLINK_IsHalted() +T062C 26247:447.254 - 1.079ms returns FALSE +T062C 26247:548.221 JLINK_HasError() +T062C 26247:548.267 JLINK_IsHalted() +T062C 26247:549.387 - 1.137ms returns FALSE +T062C 26247:649.820 JLINK_HasError() +T062C 26247:649.881 JLINK_IsHalted() +T062C 26247:651.008 - 1.142ms returns FALSE +T062C 26247:751.880 JLINK_HasError() +T062C 26247:751.967 JLINK_IsHalted() +T062C 26247:753.104 - 1.154ms returns FALSE +T062C 26247:853.687 JLINK_HasError() +T062C 26247:853.730 JLINK_HasError() +T062C 26247:853.746 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26247:853.771 Data: 8D 12 74 01 +T062C 26247:853.792 Debug reg: DWT_CYCCNT +T062C 26247:853.811 - 0.071ms returns 1 (0x1) +T3F74 26247:856.422 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26247:856.459 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26247:857.591 Data: 00 00 80 00 +T3F74 26247:857.624 - 1.211ms returns 4 (0x4) +T3F74 26247:857.667 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26247:857.690 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26247:858.074 Data: 00 00 F0 01 +T3F74 26247:858.098 - 0.438ms returns 4 (0x4) +T3F74 26247:861.846 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26247:861.880 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26247:863.084 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26247:863.113 - 1.275ms returns 16 (0x10) +T3F74 26247:863.136 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26247:863.156 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26247:863.573 Data: 1E 00 00 00 +T3F74 26247:863.597 - 0.469ms returns 4 (0x4) +T3F74 26247:863.617 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26247:863.636 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26247:864.198 Data: 00 00 00 00 00 00 00 00 00 00 00 00 FB 00 00 00 ... +T3F74 26247:864.221 - 0.612ms returns 20 (0x14) +T3F74 26247:864.242 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26247:864.261 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26247:864.699 Data: 1F 03 00 00 +T3F74 26247:864.723 - 0.489ms returns 4 (0x4) +T3F74 26247:864.743 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26247:864.762 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26247:865.198 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26247:865.222 - 0.486ms returns 12 (0xC) +T3F74 26247:865.242 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26247:865.261 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26247:865.698 Data: 00 00 00 00 +T3F74 26247:865.721 - 0.487ms returns 4 (0x4) +T3F74 26247:865.741 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26247:865.760 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26247:866.196 Data: 00 00 00 00 +T3F74 26247:866.219 - 0.486ms returns 4 (0x4) +T3F74 26247:866.239 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26247:866.258 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26247:866.710 Data: 00 00 00 00 +T3F74 26247:866.734 - 0.502ms returns 4 (0x4) +T062C 26247:878.293 JLINK_IsHalted() +T062C 26247:879.335 - 1.061ms returns FALSE +T062C 26247:979.728 JLINK_HasError() +T062C 26247:979.773 JLINK_IsHalted() +T062C 26247:980.838 - 1.093ms returns FALSE +T062C 26248:081.732 JLINK_HasError() +T062C 26248:081.781 JLINK_IsHalted() +T062C 26248:082.878 - 1.117ms returns FALSE +T062C 26248:183.728 JLINK_HasError() +T062C 26248:183.768 JLINK_IsHalted() +T062C 26248:184.926 - 1.175ms returns FALSE +T062C 26248:285.746 JLINK_HasError() +T062C 26248:285.870 JLINK_IsHalted() +T062C 26248:286.940 - 1.082ms returns FALSE +T062C 26248:387.770 JLINK_HasError() +T062C 26248:387.815 JLINK_HasError() +T062C 26248:387.834 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26248:387.865 Data: 8D 12 74 01 +T062C 26248:387.890 Debug reg: DWT_CYCCNT +T062C 26248:387.913 - 0.087ms returns 1 (0x1) +T3F74 26248:390.824 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26248:390.867 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26248:391.889 Data: 00 00 80 00 +T3F74 26248:391.917 - 1.101ms returns 4 (0x4) +T3F74 26248:391.952 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26248:391.974 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26248:392.374 Data: 00 00 F0 01 +T3F74 26248:392.398 - 0.453ms returns 4 (0x4) +T3F74 26248:396.176 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26248:396.211 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26248:397.449 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26248:397.486 - 1.318ms returns 16 (0x10) +T3F74 26248:397.515 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26248:397.539 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26248:398.043 Data: 1E 00 00 00 +T3F74 26248:398.081 - 0.576ms returns 4 (0x4) +T3F74 26248:398.108 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26248:398.131 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26248:398.626 Data: 00 00 00 00 00 00 00 00 00 00 00 00 59 00 00 00 ... +T3F74 26248:398.654 - 0.557ms returns 20 (0x14) +T3F74 26248:398.680 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26248:398.703 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26248:399.127 Data: 1F 03 00 00 +T3F74 26248:399.157 - 0.485ms returns 4 (0x4) +T3F74 26248:399.180 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26248:399.201 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26248:399.627 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26248:399.652 - 0.483ms returns 12 (0xC) +T3F74 26248:399.676 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26248:399.696 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26248:400.159 Data: 00 00 00 00 +T3F74 26248:400.192 - 0.525ms returns 4 (0x4) +T3F74 26248:400.220 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26248:400.243 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26248:400.756 Data: 00 00 00 00 +T3F74 26248:400.786 - 0.574ms returns 4 (0x4) +T3F74 26248:400.809 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26248:400.830 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26248:401.251 Data: 00 00 00 00 +T3F74 26248:401.276 - 0.475ms returns 4 (0x4) +T062C 26248:415.120 JLINK_IsHalted() +T062C 26248:416.269 - 1.174ms returns FALSE +T062C 26248:516.753 JLINK_HasError() +T062C 26248:516.799 JLINK_IsHalted() +T062C 26248:517.874 - 1.084ms returns FALSE +T062C 26248:619.340 JLINK_HasError() +T062C 26248:619.432 JLINK_IsHalted() +T062C 26248:620.724 - 1.342ms returns FALSE +T062C 26248:720.977 JLINK_HasError() +T062C 26248:721.050 JLINK_IsHalted() +T062C 26248:722.254 - 1.222ms returns FALSE +T062C 26248:822.736 JLINK_HasError() +T062C 26248:822.769 JLINK_IsHalted() +T062C 26248:823.854 - 1.127ms returns FALSE +T062C 26248:924.097 JLINK_HasError() +T062C 26248:924.178 JLINK_HasError() +T062C 26248:924.222 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26248:924.275 Data: 8D 12 74 01 +T062C 26248:924.295 Debug reg: DWT_CYCCNT +T062C 26248:924.314 - 0.099ms returns 1 (0x1) +T3F74 26248:926.811 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26248:926.844 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26248:928.032 Data: 00 00 80 00 +T3F74 26248:928.069 - 1.266ms returns 4 (0x4) +T3F74 26248:928.120 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26248:928.143 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26248:928.598 Data: 00 00 F0 01 +T3F74 26248:928.623 - 0.511ms returns 4 (0x4) +T3F74 26248:931.903 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26248:931.932 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26248:933.112 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26248:933.140 - 1.244ms returns 16 (0x10) +T3F74 26248:933.160 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26248:933.180 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26248:933.554 Data: 1F 00 00 00 +T3F74 26248:933.574 - 0.420ms returns 4 (0x4) +T3F74 26248:933.592 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26248:933.608 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26248:934.055 Data: 00 00 00 00 00 00 00 00 00 00 00 00 4F 02 00 00 ... +T3F74 26248:934.075 - 0.490ms returns 20 (0x14) +T3F74 26248:934.092 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26248:934.114 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26248:934.553 Data: 1F 03 00 00 +T3F74 26248:934.574 - 0.488ms returns 4 (0x4) +T3F74 26248:934.591 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26248:934.607 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26248:935.054 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26248:935.074 - 0.489ms returns 12 (0xC) +T3F74 26248:935.091 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26248:935.107 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26248:935.553 Data: 00 00 00 00 +T3F74 26248:935.573 - 0.489ms returns 4 (0x4) +T3F74 26248:935.590 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26248:935.606 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26248:936.054 Data: 00 00 00 00 +T3F74 26248:936.074 - 0.490ms returns 4 (0x4) +T3F74 26248:936.091 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26248:936.107 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26248:936.553 Data: 00 00 00 00 +T3F74 26248:936.573 - 0.488ms returns 4 (0x4) +T062C 26248:955.544 JLINK_IsHalted() +T062C 26248:956.715 - 1.189ms returns FALSE +T062C 26249:056.917 JLINK_HasError() +T062C 26249:056.996 JLINK_IsHalted() +T062C 26249:058.259 - 1.281ms returns FALSE +T062C 26249:159.037 JLINK_HasError() +T062C 26249:159.110 JLINK_IsHalted() +T062C 26249:160.266 - 1.174ms returns FALSE +T062C 26249:260.986 JLINK_HasError() +T062C 26249:261.059 JLINK_IsHalted() +T062C 26249:262.222 - 1.208ms returns FALSE +T062C 26249:362.676 JLINK_HasError() +T062C 26249:362.724 JLINK_IsHalted() +T062C 26249:363.765 - 1.060ms returns FALSE +T062C 26249:464.535 JLINK_HasError() +T062C 26249:464.611 JLINK_HasError() +T062C 26249:464.630 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26249:464.660 Data: 8D 12 74 01 +T062C 26249:464.684 Debug reg: DWT_CYCCNT +T062C 26249:464.705 - 0.083ms returns 1 (0x1) +T3F74 26249:467.293 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26249:467.330 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26249:468.516 Data: 00 00 80 00 +T3F74 26249:468.597 - 1.329ms returns 4 (0x4) +T3F74 26249:468.655 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26249:468.678 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26249:469.819 Data: 00 00 F0 01 +T3F74 26249:469.898 - 1.262ms returns 4 (0x4) +T3F74 26249:473.281 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26249:473.312 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26249:474.495 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26249:474.523 - 1.248ms returns 16 (0x10) +T3F74 26249:474.543 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26249:474.563 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26249:474.977 Data: 1E 00 00 00 +T3F74 26249:474.998 - 0.461ms returns 4 (0x4) +T3F74 26249:475.015 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26249:475.031 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26249:475.478 Data: 00 00 00 00 00 00 00 00 00 00 00 00 3B 01 00 00 ... +T3F74 26249:475.499 - 0.490ms returns 20 (0x14) +T3F74 26249:475.516 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26249:475.532 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26249:475.917 Data: 1F 03 00 00 +T3F74 26249:475.955 - 0.448ms returns 4 (0x4) +T3F74 26249:475.980 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26249:476.004 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26249:476.521 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26249:476.556 - 0.583ms returns 12 (0xC) +T3F74 26249:476.581 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26249:476.604 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26249:477.109 Data: 00 00 00 00 +T3F74 26249:477.133 - 0.559ms returns 4 (0x4) +T3F74 26249:477.153 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26249:477.172 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26249:477.609 Data: 00 00 00 00 +T3F74 26249:477.632 - 0.487ms returns 4 (0x4) +T3F74 26249:477.659 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26249:477.682 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26249:478.121 Data: 00 00 00 00 +T3F74 26249:478.154 - 0.503ms returns 4 (0x4) +T062C 26249:498.189 JLINK_IsHalted() +T062C 26249:499.263 - 1.094ms returns FALSE +T062C 26249:600.490 JLINK_HasError() +T062C 26249:600.579 JLINK_IsHalted() +T062C 26249:601.808 - 1.271ms returns FALSE +T062C 26249:702.082 JLINK_HasError() +T062C 26249:702.158 JLINK_IsHalted() +T062C 26249:703.456 - 1.315ms returns FALSE +T062C 26249:803.575 JLINK_HasError() +T062C 26249:803.608 JLINK_IsHalted() +T062C 26249:804.719 - 1.129ms returns FALSE +T062C 26249:905.009 JLINK_HasError() +T062C 26249:905.080 JLINK_IsHalted() +T062C 26249:906.300 - 1.269ms returns FALSE +T062C 26250:006.451 JLINK_HasError() +T062C 26250:006.481 JLINK_HasError() +T062C 26250:006.497 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26250:006.522 Data: 8D 12 74 01 +T062C 26250:006.542 Debug reg: DWT_CYCCNT +T062C 26250:006.561 - 0.070ms returns 1 (0x1) +T3F74 26250:009.155 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26250:009.191 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26250:010.321 Data: 00 00 80 00 +T3F74 26250:010.357 - 1.211ms returns 4 (0x4) +T3F74 26250:010.401 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26250:010.425 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26250:010.918 Data: 00 00 F0 01 +T3F74 26250:010.943 - 0.549ms returns 4 (0x4) +T3F74 26250:014.340 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26250:014.371 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26250:015.586 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26250:015.615 - 1.281ms returns 16 (0x10) +T3F74 26250:015.635 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26250:015.655 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26250:016.030 Data: 1F 00 00 00 +T3F74 26250:016.050 - 0.422ms returns 4 (0x4) +T3F74 26250:016.068 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26250:016.084 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26250:016.558 Data: 00 00 00 00 00 00 00 00 00 00 00 00 DB 02 00 00 ... +T3F74 26250:016.593 - 0.534ms returns 20 (0x14) +T3F74 26250:016.619 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26250:016.642 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26250:017.054 Data: 1F 03 00 00 +T3F74 26250:017.083 - 0.471ms returns 4 (0x4) +T3F74 26250:017.105 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26250:017.125 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26250:017.666 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26250:017.690 - 0.600ms returns 12 (0xC) +T3F74 26250:017.715 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26250:017.732 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26250:018.160 Data: 00 00 00 00 +T3F74 26250:018.180 - 0.471ms returns 4 (0x4) +T3F74 26250:018.197 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26250:018.213 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26250:018.660 Data: 00 00 00 00 +T3F74 26250:018.680 - 0.490ms returns 4 (0x4) +T3F74 26250:018.697 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26250:018.713 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26250:019.159 Data: 00 00 00 00 +T3F74 26250:019.179 - 0.489ms returns 4 (0x4) +T062C 26250:037.583 JLINK_IsHalted() +T062C 26250:038.671 - 1.106ms returns FALSE +T062C 26250:138.747 JLINK_HasError() +T062C 26250:138.790 JLINK_IsHalted() +T062C 26250:140.020 - 1.272ms returns FALSE +T062C 26250:240.265 JLINK_HasError() +T062C 26250:240.344 JLINK_IsHalted() +T062C 26250:241.551 - 1.225ms returns FALSE +T062C 26250:342.931 JLINK_HasError() +T062C 26250:343.094 JLINK_IsHalted() +T062C 26250:344.248 - 1.165ms returns FALSE +T062C 26250:444.858 JLINK_HasError() +T062C 26250:444.942 JLINK_IsHalted() +T062C 26250:446.202 - 1.279ms returns FALSE +T062C 26250:546.635 JLINK_HasError() +T062C 26250:546.714 JLINK_HasError() +T062C 26250:546.759 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26250:546.839 Data: 8D 12 74 01 +T062C 26250:546.876 Debug reg: DWT_CYCCNT +T062C 26250:546.894 - 0.142ms returns 1 (0x1) +T3F74 26250:549.400 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26250:549.434 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26250:550.637 Data: 00 00 80 00 +T3F74 26250:550.717 - 1.338ms returns 4 (0x4) +T3F74 26250:550.769 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26250:550.792 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26250:551.935 Data: 00 00 F0 01 +T3F74 26250:552.014 - 1.274ms returns 4 (0x4) +T3F74 26250:555.035 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26250:555.063 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26250:556.229 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26250:556.256 - 1.228ms returns 16 (0x10) +T3F74 26250:556.278 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26250:556.298 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26250:556.720 Data: 1F 00 00 00 +T3F74 26250:556.744 - 0.474ms returns 4 (0x4) +T3F74 26250:556.764 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26250:556.783 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26250:557.338 Data: 00 00 00 00 00 00 00 00 00 00 00 00 87 02 00 00 ... +T3F74 26250:557.358 - 0.600ms returns 20 (0x14) +T3F74 26250:557.375 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26250:557.392 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26250:557.839 Data: 1F 03 00 00 +T3F74 26250:557.859 - 0.490ms returns 4 (0x4) +T3F74 26250:557.876 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26250:557.892 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26250:558.337 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26250:558.357 - 0.487ms returns 12 (0xC) +T3F74 26250:558.374 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26250:558.390 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26250:558.833 Data: 00 00 00 00 +T3F74 26250:558.853 - 0.486ms returns 4 (0x4) +T3F74 26250:558.871 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26250:558.887 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26250:559.338 Data: 00 00 00 00 +T3F74 26250:559.359 - 0.494ms returns 4 (0x4) +T3F74 26250:559.376 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26250:559.392 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26250:559.833 Data: 00 00 00 00 +T3F74 26250:559.854 - 0.484ms returns 4 (0x4) +T062C 26250:572.483 JLINK_IsHalted() +T062C 26250:573.597 - 1.131ms returns FALSE +T062C 26250:673.871 JLINK_HasError() +T062C 26250:673.955 JLINK_IsHalted() +T062C 26250:674.964 - 1.026ms returns FALSE +T062C 26250:775.366 JLINK_HasError() +T062C 26250:775.443 JLINK_IsHalted() +T062C 26250:776.577 - 1.141ms returns FALSE +T062C 26250:876.708 JLINK_HasError() +T062C 26250:876.782 JLINK_IsHalted() +T062C 26250:877.915 - 1.147ms returns FALSE +T062C 26250:978.700 JLINK_HasError() +T062C 26250:978.783 JLINK_IsHalted() +T062C 26250:979.892 - 1.128ms returns FALSE +T062C 26251:080.583 JLINK_HasError() +T062C 26251:080.614 JLINK_HasError() +T062C 26251:080.630 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26251:080.657 Data: 8D 12 74 01 +T062C 26251:080.678 Debug reg: DWT_CYCCNT +T062C 26251:080.697 - 0.073ms returns 1 (0x1) +T3F74 26251:083.228 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26251:083.266 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26251:084.312 Data: 00 00 80 00 +T3F74 26251:084.348 - 1.128ms returns 4 (0x4) +T3F74 26251:084.393 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26251:084.416 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26251:084.894 Data: 00 00 F0 01 +T3F74 26251:084.914 - 0.528ms returns 4 (0x4) +T3F74 26251:087.918 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26251:087.945 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26251:089.158 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26251:089.185 - 1.275ms returns 16 (0x10) +T3F74 26251:089.288 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26251:089.314 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26251:089.768 Data: 1E 00 00 00 +T3F74 26251:089.788 - 0.507ms returns 4 (0x4) +T3F74 26251:089.806 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26251:089.874 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26251:090.393 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E3 01 00 00 ... +T3F74 26251:090.413 - 0.613ms returns 20 (0x14) +T3F74 26251:090.430 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26251:090.446 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26251:090.893 Data: 1F 03 00 00 +T3F74 26251:090.913 - 0.489ms returns 4 (0x4) +T3F74 26251:090.930 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26251:090.946 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26251:091.392 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26251:091.411 - 0.488ms returns 12 (0xC) +T3F74 26251:091.428 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26251:091.444 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26251:091.892 Data: 00 00 00 00 +T3F74 26251:091.912 - 0.491ms returns 4 (0x4) +T3F74 26251:091.930 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26251:091.946 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26251:092.387 Data: 00 00 00 00 +T3F74 26251:092.407 - 0.483ms returns 4 (0x4) +T3F74 26251:092.424 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26251:092.440 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26251:092.894 Data: 00 00 00 00 +T3F74 26251:092.914 - 0.496ms returns 4 (0x4) +T062C 26251:111.327 JLINK_IsHalted() +T062C 26251:112.402 - 1.093ms returns FALSE +T062C 26251:213.217 JLINK_HasError() +T062C 26251:213.297 JLINK_IsHalted() +T062C 26251:214.389 - 1.100ms returns FALSE +T062C 26251:315.580 JLINK_HasError() +T062C 26251:315.613 JLINK_IsHalted() +T062C 26251:316.731 - 1.136ms returns FALSE +T062C 26251:416.926 JLINK_HasError() +T062C 26251:416.999 JLINK_IsHalted() +T062C 26251:418.190 - 1.225ms returns FALSE +T062C 26251:518.576 JLINK_HasError() +T062C 26251:518.622 JLINK_IsHalted() +T062C 26251:519.735 - 1.127ms returns FALSE +T062C 26251:620.251 JLINK_HasError() +T062C 26251:620.332 JLINK_HasError() +T062C 26251:620.377 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26251:620.438 Data: 8D 12 74 01 +T062C 26251:620.493 Debug reg: DWT_CYCCNT +T062C 26251:620.515 - 0.146ms returns 1 (0x1) +T3F74 26251:622.936 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26251:622.970 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26251:624.183 Data: 00 00 80 00 +T3F74 26251:624.270 - 1.354ms returns 4 (0x4) +T3F74 26251:624.353 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26251:624.377 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26251:625.531 Data: 00 00 F0 01 +T3F74 26251:625.609 - 1.276ms returns 4 (0x4) +T3F74 26251:628.840 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26251:628.869 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26251:630.124 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26251:630.152 - 1.319ms returns 16 (0x10) +T3F74 26251:630.173 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26251:630.192 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26251:630.703 Data: 1E 00 00 00 +T3F74 26251:630.727 - 0.562ms returns 4 (0x4) +T3F74 26251:630.747 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26251:630.766 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26251:631.340 Data: 00 00 00 00 00 00 00 00 00 00 00 00 37 00 00 00 ... +T3F74 26251:631.364 - 0.624ms returns 20 (0x14) +T3F74 26251:631.384 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26251:631.403 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26251:631.828 Data: 1F 03 00 00 +T3F74 26251:631.852 - 0.476ms returns 4 (0x4) +T3F74 26251:631.872 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26251:631.893 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26251:632.320 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26251:632.350 - 0.484ms returns 12 (0xC) +T3F74 26251:632.367 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26251:632.383 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26251:632.849 Data: 00 00 00 00 +T3F74 26251:632.869 - 0.508ms returns 4 (0x4) +T3F74 26251:632.886 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26251:632.902 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26251:633.315 Data: 00 00 00 00 +T3F74 26251:633.335 - 0.455ms returns 4 (0x4) +T3F74 26251:633.352 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26251:633.368 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26251:633.815 Data: 00 00 00 00 +T3F74 26251:633.835 - 0.490ms returns 4 (0x4) +T062C 26251:645.863 JLINK_IsHalted() +T062C 26251:647.012 - 1.197ms returns FALSE +T062C 26251:747.226 JLINK_HasError() +T062C 26251:747.307 JLINK_IsHalted() +T062C 26251:748.501 - 1.212ms returns FALSE +T062C 26251:848.700 JLINK_HasError() +T062C 26251:848.777 JLINK_IsHalted() +T062C 26251:850.042 - 1.313ms returns FALSE +T062C 26251:950.867 JLINK_HasError() +T062C 26251:950.940 JLINK_IsHalted() +T062C 26251:952.148 - 1.226ms returns FALSE +T062C 26252:052.341 JLINK_HasError() +T062C 26252:052.423 JLINK_IsHalted() +T062C 26252:053.642 - 1.240ms returns FALSE +T062C 26252:154.354 JLINK_HasError() +T062C 26252:154.438 JLINK_HasError() +T062C 26252:154.487 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26252:154.513 Data: 8D 12 74 01 +T062C 26252:154.533 Debug reg: DWT_CYCCNT +T062C 26252:154.552 - 0.072ms returns 1 (0x1) +T3F74 26252:157.054 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26252:157.088 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26252:158.228 Data: 00 00 80 00 +T3F74 26252:158.289 - 1.242ms returns 4 (0x4) +T3F74 26252:158.323 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26252:158.343 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26252:158.751 Data: 00 00 F0 01 +T3F74 26252:158.771 - 0.454ms returns 4 (0x4) +T3F74 26252:161.788 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26252:161.815 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26252:163.146 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26252:163.184 - 1.403ms returns 16 (0x10) +T3F74 26252:163.208 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26252:163.231 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26252:163.626 Data: 1F 00 00 00 +T3F74 26252:163.650 - 0.450ms returns 4 (0x4) +T3F74 26252:163.670 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26252:163.690 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26252:164.255 Data: 00 00 00 00 00 00 00 00 00 00 00 00 93 01 00 00 ... +T3F74 26252:164.280 - 0.617ms returns 20 (0x14) +T3F74 26252:164.301 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26252:164.320 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26252:164.754 Data: 1F 03 00 00 +T3F74 26252:164.778 - 0.485ms returns 4 (0x4) +T3F74 26252:164.799 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26252:164.817 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26252:165.281 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26252:165.304 - 0.513ms returns 12 (0xC) +T3F74 26252:165.324 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26252:165.343 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26252:165.756 Data: 00 00 00 00 +T3F74 26252:165.779 - 0.463ms returns 4 (0x4) +T3F74 26252:165.800 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26252:165.819 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26252:166.252 Data: 00 00 00 00 +T3F74 26252:166.276 - 0.484ms returns 4 (0x4) +T3F74 26252:166.297 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26252:166.316 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26252:166.754 Data: 00 00 00 00 +T3F74 26252:166.774 - 0.483ms returns 4 (0x4) +T062C 26252:185.299 JLINK_IsHalted() +T062C 26252:186.386 - 1.105ms returns FALSE +T062C 26252:286.571 JLINK_HasError() +T062C 26252:286.661 JLINK_IsHalted() +T062C 26252:287.923 - 1.287ms returns FALSE +T062C 26252:388.141 JLINK_HasError() +T062C 26252:388.214 JLINK_IsHalted() +T062C 26252:389.428 - 1.241ms returns FALSE +T062C 26252:490.074 JLINK_HasError() +T062C 26252:490.147 JLINK_IsHalted() +T062C 26252:491.326 - 1.197ms returns FALSE +T062C 26252:592.366 JLINK_HasError() +T062C 26252:592.412 JLINK_IsHalted() +T062C 26252:593.476 - 1.111ms returns FALSE +T062C 26252:694.659 JLINK_HasError() +T062C 26252:694.734 JLINK_HasError() +T062C 26252:694.779 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26252:694.817 Data: 8D 12 74 01 +T062C 26252:694.842 Debug reg: DWT_CYCCNT +T062C 26252:694.864 - 0.093ms returns 1 (0x1) +T3F74 26252:697.492 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26252:697.530 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26252:698.601 Data: 00 00 80 00 +T3F74 26252:698.648 - 1.164ms returns 4 (0x4) +T3F74 26252:698.696 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26252:698.720 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26252:699.188 Data: 00 00 F0 01 +T3F74 26252:699.212 - 0.524ms returns 4 (0x4) +T3F74 26252:702.375 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26252:702.401 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26252:703.602 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26252:703.631 - 1.263ms returns 16 (0x10) +T3F74 26252:703.651 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26252:703.671 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26252:704.049 Data: 1E 00 00 00 +T3F74 26252:704.069 - 0.424ms returns 4 (0x4) +T3F74 26252:704.087 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26252:704.103 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26252:704.549 Data: 00 00 00 00 00 00 00 00 00 00 00 00 4F 00 00 00 ... +T3F74 26252:704.569 - 0.489ms returns 20 (0x14) +T3F74 26252:704.587 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26252:704.603 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26252:705.054 Data: 1F 03 00 00 +T3F74 26252:705.078 - 0.499ms returns 4 (0x4) +T3F74 26252:705.098 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26252:705.117 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26252:705.587 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26252:705.610 - 0.520ms returns 12 (0xC) +T3F74 26252:705.634 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26252:705.653 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26252:706.059 Data: 00 00 00 00 +T3F74 26252:706.082 - 0.456ms returns 4 (0x4) +T3F74 26252:706.105 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26252:706.125 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26252:706.556 Data: 00 00 00 00 +T3F74 26252:706.579 - 0.481ms returns 4 (0x4) +T3F74 26252:706.603 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26252:706.623 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26252:707.057 Data: 00 00 00 00 +T3F74 26252:707.081 - 0.485ms returns 4 (0x4) +T062C 26252:726.458 JLINK_IsHalted() +T062C 26252:727.636 - 1.221ms returns FALSE +T062C 26252:827.872 JLINK_HasError() +T062C 26252:827.956 JLINK_IsHalted() +T062C 26252:829.136 - 1.197ms returns FALSE +T062C 26252:930.184 JLINK_HasError() +T062C 26252:930.261 JLINK_IsHalted() +T062C 26252:931.594 - 1.351ms returns FALSE +T062C 26253:032.345 JLINK_HasError() +T062C 26253:032.417 JLINK_IsHalted() +T062C 26253:033.566 - 1.166ms returns FALSE +T062C 26253:133.797 JLINK_HasError() +T062C 26253:133.874 JLINK_IsHalted() +T062C 26253:135.094 - 1.237ms returns FALSE +T062C 26253:236.099 JLINK_HasError() +T062C 26253:236.171 JLINK_HasError() +T062C 26253:236.219 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26253:236.250 Data: 8D 12 74 01 +T062C 26253:236.274 Debug reg: DWT_CYCCNT +T062C 26253:236.296 - 0.084ms returns 1 (0x1) +T3F74 26253:238.852 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26253:238.890 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26253:240.069 Data: 00 00 80 00 +T3F74 26253:240.172 - 1.340ms returns 4 (0x4) +T3F74 26253:240.290 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26253:240.348 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26253:241.568 Data: 00 00 F0 01 +T3F74 26253:241.646 - 1.375ms returns 4 (0x4) +T3F74 26253:245.070 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26253:245.097 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26253:246.320 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26253:246.382 - 1.331ms returns 16 (0x10) +T3F74 26253:246.436 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26253:246.453 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26253:246.851 Data: 1F 00 00 00 +T3F74 26253:246.871 - 0.442ms returns 4 (0x4) +T3F74 26253:246.889 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26253:246.905 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26253:247.352 Data: 00 00 00 00 00 00 00 00 00 00 00 00 87 01 00 00 ... +T3F74 26253:247.372 - 0.490ms returns 20 (0x14) +T3F74 26253:247.390 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26253:247.405 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26253:247.855 Data: 1F 03 00 00 +T3F74 26253:247.875 - 0.492ms returns 4 (0x4) +T3F74 26253:247.892 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26253:247.908 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26253:248.476 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26253:248.499 - 0.614ms returns 12 (0xC) +T3F74 26253:248.519 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26253:248.538 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26253:248.986 Data: 00 00 00 00 +T3F74 26253:249.010 - 0.498ms returns 4 (0x4) +T3F74 26253:249.030 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26253:249.052 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26253:249.485 Data: 00 00 00 00 +T3F74 26253:249.508 - 0.486ms returns 4 (0x4) +T3F74 26253:249.528 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26253:249.547 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26253:249.983 Data: 00 00 00 00 +T3F74 26253:250.007 - 0.486ms returns 4 (0x4) +T062C 26253:268.929 JLINK_IsHalted() +T062C 26253:270.028 - 1.117ms returns FALSE +T062C 26253:370.775 JLINK_HasError() +T062C 26253:370.850 JLINK_IsHalted() +T062C 26253:372.082 - 1.251ms returns FALSE +T062C 26253:472.278 JLINK_HasError() +T062C 26253:472.349 JLINK_IsHalted() +T062C 26253:473.579 - 1.271ms returns FALSE +T062C 26253:574.194 JLINK_HasError() +T062C 26253:574.265 JLINK_IsHalted() +T062C 26253:575.377 - 1.129ms returns FALSE +T062C 26253:676.152 JLINK_HasError() +T062C 26253:676.193 JLINK_IsHalted() +T062C 26253:677.358 - 1.184ms returns FALSE +T062C 26253:777.710 JLINK_HasError() +T062C 26253:777.755 JLINK_HasError() +T062C 26253:777.774 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26253:777.803 Data: 8D 12 74 01 +T062C 26253:777.828 Debug reg: DWT_CYCCNT +T062C 26253:777.850 - 0.084ms returns 1 (0x1) +T3F74 26253:780.277 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26253:780.310 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26253:781.566 Data: 00 00 80 00 +T3F74 26253:781.644 - 1.387ms returns 4 (0x4) +T3F74 26253:781.702 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26253:781.725 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26253:782.793 Data: 00 00 F0 01 +T3F74 26253:782.826 - 1.132ms returns 4 (0x4) +T3F74 26253:785.979 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26253:786.006 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26253:787.179 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26253:787.211 - 1.239ms returns 16 (0x10) +T3F74 26253:787.235 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26253:787.258 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26253:787.660 Data: 1F 00 00 00 +T3F74 26253:787.684 - 0.457ms returns 4 (0x4) +T3F74 26253:787.709 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26253:787.726 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26253:788.293 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B3 01 00 00 ... +T3F74 26253:788.317 - 0.615ms returns 20 (0x14) +T3F74 26253:788.337 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26253:788.356 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26253:788.785 Data: 1F 03 00 00 +T3F74 26253:788.808 - 0.479ms returns 4 (0x4) +T3F74 26253:788.829 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26253:788.847 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26253:789.285 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26253:789.308 - 0.487ms returns 12 (0xC) +T3F74 26253:789.334 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26253:789.350 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26253:789.797 Data: 00 00 00 00 +T3F74 26253:789.821 - 0.494ms returns 4 (0x4) +T3F74 26253:789.841 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26253:789.860 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26253:790.294 Data: 00 00 00 00 +T3F74 26253:790.318 - 0.484ms returns 4 (0x4) +T3F74 26253:790.338 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26253:790.357 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26253:790.789 Data: 00 00 00 00 +T3F74 26253:790.812 - 0.482ms returns 4 (0x4) +T062C 26253:803.187 JLINK_IsHalted() +T062C 26253:804.353 - 1.184ms returns FALSE +T062C 26253:905.190 JLINK_HasError() +T062C 26253:905.266 JLINK_IsHalted() +T062C 26253:906.507 - 1.261ms returns FALSE +T062C 26254:007.206 JLINK_HasError() +T062C 26254:007.237 JLINK_IsHalted() +T062C 26254:008.391 - 1.203ms returns FALSE +T062C 26254:108.603 JLINK_HasError() +T062C 26254:108.675 JLINK_IsHalted() +T062C 26254:109.867 - 1.240ms returns FALSE +T062C 26254:210.063 JLINK_HasError() +T062C 26254:210.134 JLINK_IsHalted() +T062C 26254:211.371 - 1.279ms returns FALSE +T062C 26254:311.651 JLINK_HasError() +T062C 26254:311.722 JLINK_HasError() +T062C 26254:311.770 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26254:311.795 Data: 8D 12 74 01 +T062C 26254:311.816 Debug reg: DWT_CYCCNT +T062C 26254:311.835 - 0.071ms returns 1 (0x1) +T3F74 26254:314.283 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26254:314.316 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26254:315.500 Data: 00 00 80 00 +T3F74 26254:315.534 - 1.259ms returns 4 (0x4) +T3F74 26254:315.573 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26254:315.596 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26254:316.746 Data: 00 00 F0 01 +T3F74 26254:316.776 - 1.211ms returns 4 (0x4) +T3F74 26254:320.405 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26254:320.436 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26254:321.672 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26254:321.731 - 1.334ms returns 16 (0x10) +T3F74 26254:321.757 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26254:321.780 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26254:322.209 Data: 1E 00 00 00 +T3F74 26254:322.229 - 0.479ms returns 4 (0x4) +T3F74 26254:322.247 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26254:322.263 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26254:322.720 Data: 00 00 00 00 00 00 00 00 00 00 00 00 09 01 00 00 ... +T3F74 26254:322.744 - 0.505ms returns 20 (0x14) +T3F74 26254:322.765 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26254:322.783 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26254:323.220 Data: 1F 03 00 00 +T3F74 26254:323.243 - 0.486ms returns 4 (0x4) +T3F74 26254:323.263 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26254:323.282 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26254:323.718 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26254:323.741 - 0.485ms returns 12 (0xC) +T3F74 26254:323.761 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26254:323.780 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26254:324.213 Data: 00 00 00 00 +T3F74 26254:324.232 - 0.477ms returns 4 (0x4) +T3F74 26254:324.249 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26254:324.275 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26254:324.712 Data: 00 00 00 00 +T3F74 26254:324.732 - 0.489ms returns 4 (0x4) +T3F74 26254:324.750 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26254:324.766 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26254:325.213 Data: 00 00 00 00 +T3F74 26254:325.233 - 0.490ms returns 4 (0x4) +T062C 26254:343.757 JLINK_IsHalted() +T062C 26254:344.904 - 1.165ms returns FALSE +T062C 26254:445.832 JLINK_HasError() +T062C 26254:445.912 JLINK_IsHalted() +T062C 26254:447.163 - 1.267ms returns FALSE +T062C 26254:547.940 JLINK_HasError() +T062C 26254:548.012 JLINK_IsHalted() +T062C 26254:549.183 - 1.189ms returns FALSE +T062C 26254:649.964 JLINK_HasError() +T062C 26254:650.038 JLINK_IsHalted() +T062C 26254:651.161 - 1.142ms returns FALSE +T062C 26254:751.514 JLINK_HasError() +T062C 26254:751.612 JLINK_IsHalted() +T062C 26254:752.815 - 1.256ms returns FALSE +T062C 26254:853.278 JLINK_HasError() +T062C 26254:853.352 JLINK_HasError() +T062C 26254:853.397 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26254:853.458 Data: 8D 12 74 01 +T062C 26254:853.508 Debug reg: DWT_CYCCNT +T062C 26254:853.527 - 0.137ms returns 1 (0x1) +T3F74 26254:855.980 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26254:856.013 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26254:857.165 Data: 00 00 80 00 +T3F74 26254:857.222 - 1.250ms returns 4 (0x4) +T3F74 26254:857.260 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26254:857.284 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26254:858.388 Data: 00 00 F0 01 +T3F74 26254:858.409 - 1.155ms returns 4 (0x4) +T3F74 26254:861.775 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26254:861.805 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26254:863.105 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26254:863.182 - 1.414ms returns 16 (0x10) +T3F74 26254:863.202 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26254:863.220 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26254:863.637 Data: 1E 00 00 00 +T3F74 26254:863.657 - 0.462ms returns 4 (0x4) +T3F74 26254:863.675 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26254:863.691 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26254:864.137 Data: 00 00 00 00 00 00 00 00 00 00 00 00 EF 01 00 00 ... +T3F74 26254:864.157 - 0.489ms returns 20 (0x14) +T3F74 26254:864.174 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26254:864.191 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26254:864.636 Data: 1F 03 00 00 +T3F74 26254:864.656 - 0.488ms returns 4 (0x4) +T3F74 26254:864.674 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26254:864.690 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26254:865.141 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26254:865.161 - 0.494ms returns 12 (0xC) +T3F74 26254:865.178 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26254:865.194 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26254:865.641 Data: 00 00 00 00 +T3F74 26254:865.661 - 0.489ms returns 4 (0x4) +T3F74 26254:865.678 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26254:865.694 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26254:866.140 Data: 00 00 00 00 +T3F74 26254:866.160 - 0.488ms returns 4 (0x4) +T3F74 26254:866.177 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26254:866.193 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26254:866.644 Data: 00 00 00 00 +T3F74 26254:866.668 - 0.499ms returns 4 (0x4) +T062C 26254:879.192 JLINK_IsHalted() +T062C 26254:880.302 - 1.127ms returns FALSE +T062C 26254:980.516 JLINK_HasError() +T062C 26254:980.597 JLINK_IsHalted() +T062C 26254:981.849 - 1.271ms returns FALSE +T062C 26255:082.975 JLINK_HasError() +T062C 26255:083.005 JLINK_IsHalted() +T062C 26255:084.123 - 1.135ms returns FALSE +T062C 26255:184.265 JLINK_HasError() +T062C 26255:184.336 JLINK_IsHalted() +T062C 26255:185.610 - 1.316ms returns FALSE +T062C 26255:285.817 JLINK_HasError() +T062C 26255:285.909 JLINK_IsHalted() +T062C 26255:287.079 - 1.218ms returns FALSE +T062C 26255:387.871 JLINK_HasError() +T062C 26255:387.942 JLINK_HasError() +T062C 26255:387.984 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26255:388.013 Data: 8D 12 74 01 +T062C 26255:388.037 Debug reg: DWT_CYCCNT +T062C 26255:388.059 - 0.082ms returns 1 (0x1) +T3F74 26255:390.392 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26255:390.426 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26255:391.473 Data: 00 00 80 00 +T3F74 26255:391.509 - 1.125ms returns 4 (0x4) +T3F74 26255:391.552 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26255:391.576 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26255:392.066 Data: 00 00 F0 01 +T3F74 26255:392.086 - 0.541ms returns 4 (0x4) +T3F74 26255:395.553 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26255:395.580 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26255:396.752 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26255:396.780 - 1.234ms returns 16 (0x10) +T3F74 26255:396.801 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26255:396.820 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26255:397.191 Data: 1E 00 00 00 +T3F74 26255:397.211 - 0.417ms returns 4 (0x4) +T3F74 26255:397.229 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26255:397.245 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26255:397.709 Data: 00 00 00 00 00 00 00 00 00 00 00 00 4B 00 00 00 ... +T3F74 26255:397.729 - 0.506ms returns 20 (0x14) +T3F74 26255:397.746 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26255:397.762 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26255:398.191 Data: 1F 03 00 00 +T3F74 26255:398.211 - 0.471ms returns 4 (0x4) +T3F74 26255:398.228 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26255:398.244 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26255:398.704 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26255:398.724 - 0.502ms returns 12 (0xC) +T3F74 26255:398.741 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26255:398.757 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26255:399.190 Data: 00 00 00 00 +T3F74 26255:399.210 - 0.475ms returns 4 (0x4) +T3F74 26255:399.227 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26255:399.243 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26255:399.698 Data: 00 00 00 00 +T3F74 26255:399.718 - 0.497ms returns 4 (0x4) +T3F74 26255:399.735 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26255:399.751 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26255:400.195 Data: 00 00 00 00 +T3F74 26255:400.215 - 0.486ms returns 4 (0x4) +T062C 26255:412.094 JLINK_IsHalted() +T062C 26255:413.256 - 1.204ms returns FALSE +T062C 26255:513.842 JLINK_HasError() +T062C 26255:513.922 JLINK_IsHalted() +T062C 26255:515.103 - 1.199ms returns FALSE +T062C 26255:615.776 JLINK_HasError() +T062C 26255:615.803 JLINK_IsHalted() +T062C 26255:616.888 - 1.137ms returns FALSE +T062C 26255:717.806 JLINK_HasError() +T062C 26255:717.835 JLINK_IsHalted() +T062C 26255:718.907 - 1.089ms returns FALSE +T062C 26255:819.138 JLINK_HasError() +T062C 26255:819.179 JLINK_IsHalted() +T062C 26255:820.250 - 1.085ms returns FALSE +T062C 26255:920.777 JLINK_HasError() +T062C 26255:920.826 JLINK_HasError() +T062C 26255:920.844 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26255:920.875 Data: 8D 12 74 01 +T062C 26255:920.899 Debug reg: DWT_CYCCNT +T062C 26255:920.921 - 0.084ms returns 1 (0x1) +T3F74 26255:923.319 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26255:923.353 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26255:924.523 Data: 00 00 80 00 +T3F74 26255:924.571 - 1.259ms returns 4 (0x4) +T3F74 26255:924.610 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26255:924.633 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26255:925.816 Data: 00 00 F0 01 +T3F74 26255:925.879 - 1.287ms returns 4 (0x4) +T3F74 26255:929.252 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26255:929.286 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26255:930.517 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26255:930.543 - 1.299ms returns 16 (0x10) +T3F74 26255:930.565 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26255:930.585 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26255:931.035 Data: 1F 00 00 00 +T3F74 26255:931.059 - 0.502ms returns 4 (0x4) +T3F74 26255:931.080 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26255:931.099 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26255:931.626 Data: 00 00 00 00 00 00 00 00 00 00 00 00 49 01 00 00 ... +T3F74 26255:931.646 - 0.573ms returns 20 (0x14) +T3F74 26255:931.664 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26255:931.680 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26255:932.126 Data: 1F 03 00 00 +T3F74 26255:932.146 - 0.489ms returns 4 (0x4) +T3F74 26255:932.164 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26255:932.180 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26255:932.626 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26255:932.646 - 0.489ms returns 12 (0xC) +T3F74 26255:932.663 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26255:932.679 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26255:933.126 Data: 00 00 00 00 +T3F74 26255:933.146 - 0.489ms returns 4 (0x4) +T3F74 26255:933.163 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26255:933.179 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26255:933.626 Data: 00 00 00 00 +T3F74 26255:933.646 - 0.489ms returns 4 (0x4) +T3F74 26255:933.663 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26255:933.679 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26255:934.209 Data: 00 00 00 00 +T3F74 26255:934.233 - 0.577ms returns 4 (0x4) +T062C 26255:954.200 JLINK_IsHalted() +T062C 26255:955.261 - 1.090ms returns FALSE +T062C 26256:055.913 JLINK_HasError() +T062C 26256:055.992 JLINK_IsHalted() +T062C 26256:057.257 - 1.306ms returns FALSE +T062C 26256:158.032 JLINK_HasError() +T062C 26256:158.117 JLINK_IsHalted() +T062C 26256:159.241 - 1.142ms returns FALSE +T062C 26256:259.442 JLINK_HasError() +T062C 26256:259.512 JLINK_IsHalted() +T062C 26256:260.694 - 1.200ms returns FALSE +T062C 26256:361.476 JLINK_HasError() +T062C 26256:361.549 JLINK_IsHalted() +T062C 26256:362.684 - 1.153ms returns FALSE +T062C 26256:462.972 JLINK_HasError() +T062C 26256:463.044 JLINK_HasError() +T062C 26256:463.088 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26256:463.150 Data: 8D 12 74 01 +T062C 26256:463.171 Debug reg: DWT_CYCCNT +T062C 26256:463.189 - 0.108ms returns 1 (0x1) +T3F74 26256:465.956 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26256:465.988 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26256:467.146 Data: 00 00 80 00 +T3F74 26256:467.213 - 1.264ms returns 4 (0x4) +T3F74 26256:467.247 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26256:467.266 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26256:467.673 Data: 00 00 F0 01 +T3F74 26256:467.694 - 0.453ms returns 4 (0x4) +T3F74 26256:470.898 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26256:470.927 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26256:472.076 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26256:472.105 - 1.215ms returns 16 (0x10) +T3F74 26256:472.128 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26256:472.149 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26256:472.547 Data: 1E 00 00 00 +T3F74 26256:472.567 - 0.446ms returns 4 (0x4) +T3F74 26256:472.585 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26256:472.601 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26256:473.068 Data: 00 00 00 00 00 00 00 00 00 00 00 00 BF 01 00 00 ... +T3F74 26256:473.092 - 0.515ms returns 20 (0x14) +T3F74 26256:473.112 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26256:473.131 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26256:473.558 Data: 1F 03 00 00 +T3F74 26256:473.588 - 0.489ms returns 4 (0x4) +T3F74 26256:473.614 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26256:473.633 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26256:474.073 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26256:474.096 - 0.489ms returns 12 (0xC) +T3F74 26256:474.176 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26256:474.195 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26256:474.676 Data: 00 00 00 00 +T3F74 26256:474.696 - 0.527ms returns 4 (0x4) +T3F74 26256:474.714 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26256:474.730 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26256:475.177 Data: 00 00 00 00 +T3F74 26256:475.197 - 0.490ms returns 4 (0x4) +T3F74 26256:475.214 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26256:475.230 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26256:475.676 Data: 00 00 00 00 +T3F74 26256:475.696 - 0.489ms returns 4 (0x4) +T062C 26256:494.471 JLINK_IsHalted() +T062C 26256:495.619 - 1.177ms returns FALSE +T062C 26256:596.883 JLINK_HasError() +T062C 26256:596.962 JLINK_IsHalted() +T062C 26256:598.104 - 1.160ms returns FALSE +T062C 26256:699.123 JLINK_HasError() +T062C 26256:699.270 JLINK_IsHalted() +T062C 26256:700.377 - 1.118ms returns FALSE +T062C 26256:800.577 JLINK_HasError() +T062C 26256:800.654 JLINK_IsHalted() +T062C 26256:801.894 - 1.272ms returns FALSE +T062C 26256:902.282 JLINK_HasError() +T062C 26256:902.324 JLINK_IsHalted() +T062C 26256:903.346 - 1.036ms returns FALSE +T062C 26257:004.095 JLINK_HasError() +T062C 26257:004.173 JLINK_HasError() +T062C 26257:004.207 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26257:004.237 Data: 8D 12 74 01 +T062C 26257:004.261 Debug reg: DWT_CYCCNT +T062C 26257:004.283 - 0.084ms returns 1 (0x1) +T3F74 26257:006.678 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26257:006.711 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26257:007.886 Data: 00 00 80 00 +T3F74 26257:007.965 - 1.306ms returns 4 (0x4) +T3F74 26257:008.023 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26257:008.047 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26257:009.190 Data: 00 00 F0 01 +T3F74 26257:009.268 - 1.265ms returns 4 (0x4) +T3F74 26257:012.520 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26257:012.554 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26257:013.811 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26257:013.868 - 1.358ms returns 16 (0x10) +T3F74 26257:013.894 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26257:013.916 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26257:014.375 Data: 1F 00 00 00 +T3F74 26257:014.411 - 0.525ms returns 4 (0x4) +T3F74 26257:014.438 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26257:014.461 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26257:015.000 Data: 00 00 00 00 00 00 00 00 00 00 00 00 93 00 00 00 ... +T3F74 26257:015.033 - 0.602ms returns 20 (0x14) +T3F74 26257:015.055 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26257:015.076 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26257:015.488 Data: 1F 03 00 00 +T3F74 26257:015.512 - 0.464ms returns 4 (0x4) +T3F74 26257:015.532 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26257:015.551 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26257:015.980 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26257:016.000 - 0.475ms returns 12 (0xC) +T3F74 26257:016.018 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26257:016.034 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26257:016.479 Data: 00 00 00 00 +T3F74 26257:016.499 - 0.488ms returns 4 (0x4) +T3F74 26257:016.516 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26257:016.532 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26257:016.980 Data: 00 00 00 00 +T3F74 26257:017.000 - 0.490ms returns 4 (0x4) +T3F74 26257:017.017 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26257:017.033 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26257:017.479 Data: 00 00 00 00 +T3F74 26257:017.503 - 0.493ms returns 4 (0x4) +T062C 26257:036.945 JLINK_IsHalted() +T062C 26257:038.000 - 1.073ms returns FALSE +T062C 26257:138.240 JLINK_HasError() +T062C 26257:138.375 JLINK_IsHalted() +T062C 26257:139.515 - 1.165ms returns FALSE +T062C 26257:240.594 JLINK_HasError() +T062C 26257:240.665 JLINK_IsHalted() +T062C 26257:242.037 - 1.414ms returns FALSE +T062C 26257:342.341 JLINK_HasError() +T062C 26257:342.412 JLINK_IsHalted() +T062C 26257:343.558 - 1.194ms returns FALSE +T062C 26257:443.696 JLINK_HasError() +T062C 26257:443.767 JLINK_IsHalted() +T062C 26257:445.012 - 1.287ms returns FALSE +T062C 26257:545.276 JLINK_HasError() +T062C 26257:545.353 JLINK_HasError() +T062C 26257:545.397 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26257:545.457 Data: 8D 12 74 01 +T062C 26257:545.478 Debug reg: DWT_CYCCNT +T062C 26257:545.496 - 0.106ms returns 1 (0x1) +T3F74 26257:548.128 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26257:548.165 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26257:549.301 Data: 00 00 80 00 +T3F74 26257:549.332 - 1.210ms returns 4 (0x4) +T3F74 26257:549.372 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26257:549.392 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26257:549.784 Data: 00 00 F0 01 +T3F74 26257:549.805 - 0.439ms returns 4 (0x4) +T3F74 26257:553.021 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26257:553.053 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26257:554.303 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26257:554.336 - 1.323ms returns 16 (0x10) +T3F74 26257:554.360 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26257:554.383 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26257:554.791 Data: 1E 00 00 00 +T3F74 26257:554.815 - 0.462ms returns 4 (0x4) +T3F74 26257:554.835 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26257:554.855 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26257:555.409 Data: 00 00 00 00 00 00 00 00 00 00 00 00 AB 01 00 00 ... +T3F74 26257:555.429 - 0.600ms returns 20 (0x14) +T3F74 26257:555.447 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26257:555.463 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26257:555.908 Data: 1F 03 00 00 +T3F74 26257:555.928 - 0.488ms returns 4 (0x4) +T3F74 26257:555.945 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26257:555.961 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26257:556.408 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26257:556.428 - 0.489ms returns 12 (0xC) +T3F74 26257:556.445 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26257:556.461 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26257:556.904 Data: 00 00 00 00 +T3F74 26257:556.924 - 0.486ms returns 4 (0x4) +T3F74 26257:556.941 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26257:556.957 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26257:557.539 Data: 00 00 00 00 +T3F74 26257:557.575 - 0.644ms returns 4 (0x4) +T3F74 26257:557.601 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26257:557.627 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26257:558.037 Data: 00 00 00 00 +T3F74 26257:558.062 - 0.468ms returns 4 (0x4) +T062C 26257:576.788 JLINK_IsHalted() +T062C 26257:577.919 - 1.148ms returns FALSE +T062C 26257:678.628 JLINK_HasError() +T062C 26257:678.666 JLINK_IsHalted() +T062C 26257:679.898 - 1.278ms returns FALSE +T062C 26257:780.588 JLINK_HasError() +T062C 26257:780.663 JLINK_IsHalted() +T062C 26257:781.844 - 1.222ms returns FALSE +T062C 26257:882.516 JLINK_HasError() +T062C 26257:882.595 JLINK_IsHalted() +T062C 26257:883.826 - 1.272ms returns FALSE +T062C 26257:984.012 JLINK_HasError() +T062C 26257:984.099 JLINK_IsHalted() +T062C 26257:985.323 - 1.275ms returns FALSE +T062C 26258:086.059 JLINK_HasError() +T062C 26258:086.090 JLINK_HasError() +T062C 26258:086.106 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26258:086.131 Data: 8D 12 74 01 +T062C 26258:086.154 Debug reg: DWT_CYCCNT +T062C 26258:086.173 - 0.079ms returns 1 (0x1) +T3F74 26258:088.680 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26258:088.712 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26258:089.760 Data: 00 00 80 00 +T3F74 26258:089.813 - 1.141ms returns 4 (0x4) +T3F74 26258:089.866 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26258:089.890 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26258:090.430 Data: 00 00 F0 01 +T3F74 26258:090.459 - 0.601ms returns 4 (0x4) +T3F74 26258:093.777 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26258:093.804 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26258:095.023 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26258:095.052 - 1.282ms returns 16 (0x10) +T3F74 26258:095.073 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26258:095.092 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26258:095.587 Data: 1E 00 00 00 +T3F74 26258:095.608 - 0.541ms returns 4 (0x4) +T3F74 26258:095.625 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26258:095.641 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26258:096.087 Data: 00 00 00 00 00 00 00 00 00 00 00 00 89 00 00 00 ... +T3F74 26258:096.107 - 0.488ms returns 20 (0x14) +T3F74 26258:096.124 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26258:096.140 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26258:096.587 Data: 1F 03 00 00 +T3F74 26258:096.607 - 0.489ms returns 4 (0x4) +T3F74 26258:096.624 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26258:096.640 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26258:097.111 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26258:097.131 - 0.513ms returns 12 (0xC) +T3F74 26258:097.148 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26258:097.164 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26258:097.586 Data: 00 00 00 00 +T3F74 26258:097.606 - 0.465ms returns 4 (0x4) +T3F74 26258:097.623 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26258:097.639 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26258:098.085 Data: 00 00 00 00 +T3F74 26258:098.105 - 0.488ms returns 4 (0x4) +T3F74 26258:098.122 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26258:098.138 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26258:098.586 Data: 00 00 00 00 +T3F74 26258:098.606 - 0.490ms returns 4 (0x4) +T062C 26258:110.567 JLINK_IsHalted() +T062C 26258:111.628 - 1.079ms returns FALSE +T062C 26258:212.398 JLINK_HasError() +T062C 26258:212.475 JLINK_IsHalted() +T062C 26258:213.711 - 1.255ms returns FALSE +T062C 26258:314.478 JLINK_HasError() +T062C 26258:314.550 JLINK_IsHalted() +T062C 26258:315.676 - 1.144ms returns FALSE +T062C 26258:415.861 JLINK_HasError() +T062C 26258:415.933 JLINK_IsHalted() +T062C 26258:417.095 - 1.181ms returns FALSE +T062C 26258:517.516 JLINK_HasError() +T062C 26258:517.588 JLINK_IsHalted() +T062C 26258:518.763 - 1.194ms returns FALSE +T062C 26258:618.945 JLINK_HasError() +T062C 26258:619.017 JLINK_HasError() +T062C 26258:619.061 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26258:619.128 Data: 8D 12 74 01 +T062C 26258:619.149 Debug reg: DWT_CYCCNT +T062C 26258:619.167 - 0.113ms returns 1 (0x1) +T3F74 26258:621.648 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26258:621.680 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26258:622.920 Data: 00 00 80 00 +T3F74 26258:623.000 - 1.381ms returns 4 (0x4) +T3F74 26258:623.060 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26258:623.083 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26258:624.236 Data: 00 00 F0 01 +T3F74 26258:624.314 - 1.273ms returns 4 (0x4) +T3F74 26258:627.361 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26258:627.389 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26258:628.570 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26258:628.598 - 1.243ms returns 16 (0x10) +T3F74 26258:628.619 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26258:628.638 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26258:629.137 Data: 1E 00 00 00 +T3F74 26258:629.157 - 0.545ms returns 4 (0x4) +T3F74 26258:629.175 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26258:629.191 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26258:629.637 Data: 00 00 00 00 00 00 00 00 00 00 00 00 F3 01 00 00 ... +T3F74 26258:629.657 - 0.488ms returns 20 (0x14) +T3F74 26258:629.674 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26258:629.690 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26258:630.136 Data: 1F 03 00 00 +T3F74 26258:630.156 - 0.488ms returns 4 (0x4) +T3F74 26258:630.173 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26258:630.189 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26258:630.637 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26258:630.656 - 0.490ms returns 12 (0xC) +T3F74 26258:630.674 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26258:630.690 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26258:631.142 Data: 00 00 00 00 +T3F74 26258:631.166 - 0.500ms returns 4 (0x4) +T3F74 26258:631.186 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26258:631.205 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26258:631.648 Data: 00 00 00 00 +T3F74 26258:631.671 - 0.493ms returns 4 (0x4) +T3F74 26258:631.691 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26258:631.710 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26258:632.147 Data: 00 00 00 00 +T3F74 26258:632.173 - 0.490ms returns 4 (0x4) +T062C 26258:644.039 JLINK_IsHalted() +T062C 26258:645.152 - 1.131ms returns FALSE +T062C 26258:745.906 JLINK_HasError() +T062C 26258:745.988 JLINK_IsHalted() +T062C 26258:747.295 - 1.341ms returns FALSE +T062C 26258:847.993 JLINK_HasError() +T062C 26258:848.027 JLINK_IsHalted() +T062C 26258:849.220 - 1.210ms returns FALSE +T062C 26258:949.998 JLINK_HasError() +T062C 26258:950.072 JLINK_IsHalted() +T062C 26258:951.213 - 1.159ms returns FALSE +T062C 26259:051.912 JLINK_HasError() +T062C 26259:051.955 JLINK_IsHalted() +T062C 26259:052.977 - 1.040ms returns FALSE +T062C 26259:153.158 JLINK_HasError() +T062C 26259:153.236 JLINK_HasError() +T062C 26259:153.280 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26259:153.348 Data: 8D 12 74 01 +T062C 26259:153.368 Debug reg: DWT_CYCCNT +T062C 26259:153.387 - 0.113ms returns 1 (0x1) +T3F74 26259:155.926 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26259:155.963 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26259:157.224 Data: 00 00 80 00 +T3F74 26259:157.304 - 1.406ms returns 4 (0x4) +T3F74 26259:157.363 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26259:157.387 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26259:158.540 Data: 00 00 F0 01 +T3F74 26259:158.618 - 1.274ms returns 4 (0x4) +T3F74 26259:161.674 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26259:161.705 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26259:162.835 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26259:162.863 - 1.195ms returns 16 (0x10) +T3F74 26259:162.884 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26259:162.903 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26259:163.315 Data: 1E 00 00 00 +T3F74 26259:163.349 - 0.477ms returns 4 (0x4) +T3F74 26259:163.404 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26259:163.451 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26259:164.103 Data: 00 00 00 00 00 00 00 00 00 00 00 00 3B 02 00 00 ... +T3F74 26259:164.129 - 0.733ms returns 20 (0x14) +T3F74 26259:164.151 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26259:164.172 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26259:164.572 Data: 1F 03 00 00 +T3F74 26259:164.596 - 0.452ms returns 4 (0x4) +T3F74 26259:164.616 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26259:164.637 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26259:165.065 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26259:165.085 - 0.476ms returns 12 (0xC) +T3F74 26259:165.102 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26259:165.124 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26259:165.571 Data: 00 00 00 00 +T3F74 26259:165.595 - 0.500ms returns 4 (0x4) +T3F74 26259:165.615 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26259:165.634 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26259:166.069 Data: 00 00 00 00 +T3F74 26259:166.093 - 0.485ms returns 4 (0x4) +T3F74 26259:166.113 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26259:166.132 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26259:166.577 Data: 00 00 00 00 +T3F74 26259:166.600 - 0.495ms returns 4 (0x4) +T062C 26259:178.970 JLINK_IsHalted() +T062C 26259:180.090 - 1.149ms returns FALSE +T062C 26259:280.255 JLINK_HasError() +T062C 26259:280.334 JLINK_IsHalted() +T062C 26259:281.561 - 1.275ms returns FALSE +T062C 26259:381.875 JLINK_HasError() +T062C 26259:381.944 JLINK_IsHalted() +T062C 26259:383.181 - 1.278ms returns FALSE +T062C 26259:484.062 JLINK_HasError() +T062C 26259:484.141 JLINK_IsHalted() +T062C 26259:485.375 - 1.252ms returns FALSE +T062C 26259:585.460 JLINK_HasError() +T062C 26259:585.534 JLINK_IsHalted() +T062C 26259:586.621 - 1.106ms returns FALSE +T062C 26259:686.764 JLINK_HasError() +T062C 26259:686.838 JLINK_HasError() +T062C 26259:686.882 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26259:686.942 Data: 8D 12 74 01 +T062C 26259:686.988 Debug reg: DWT_CYCCNT +T062C 26259:687.007 - 0.132ms returns 1 (0x1) +T3F74 26259:689.461 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26259:689.494 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26259:690.533 Data: 00 00 80 00 +T3F74 26259:690.568 - 1.116ms returns 4 (0x4) +T3F74 26259:690.611 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26259:690.635 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26259:691.124 Data: 00 00 F0 01 +T3F74 26259:691.145 - 0.541ms returns 4 (0x4) +T3F74 26259:694.395 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26259:694.428 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26259:695.711 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26259:695.774 - 1.404ms returns 16 (0x10) +T3F74 26259:695.812 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26259:695.829 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26259:696.249 Data: 1E 00 00 00 +T3F74 26259:696.269 - 0.463ms returns 4 (0x4) +T3F74 26259:696.286 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26259:696.303 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26259:696.750 Data: 00 00 00 00 00 00 00 00 00 00 00 00 11 01 00 00 ... +T3F74 26259:696.770 - 0.490ms returns 20 (0x14) +T3F74 26259:696.787 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26259:696.803 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26259:697.243 Data: 1F 03 00 00 +T3F74 26259:697.263 - 0.483ms returns 4 (0x4) +T3F74 26259:697.280 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26259:697.296 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26259:697.750 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26259:697.770 - 0.496ms returns 12 (0xC) +T3F74 26259:697.787 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26259:697.803 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26259:698.273 Data: 00 00 00 00 +T3F74 26259:698.293 - 0.512ms returns 4 (0x4) +T3F74 26259:698.310 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26259:698.326 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26259:698.777 Data: 00 00 00 00 +T3F74 26259:698.801 - 0.498ms returns 4 (0x4) +T3F74 26259:698.821 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26259:698.840 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26259:699.254 Data: 00 00 00 00 +T3F74 26259:699.277 - 0.464ms returns 4 (0x4) +T062C 26259:712.212 JLINK_IsHalted() +T062C 26259:713.277 - 1.085ms returns FALSE +T062C 26259:813.482 JLINK_HasError() +T062C 26259:813.566 JLINK_IsHalted() +T062C 26259:814.770 - 1.222ms returns FALSE +T062C 26259:914.965 JLINK_HasError() +T062C 26259:915.037 JLINK_IsHalted() +T062C 26259:916.323 - 1.303ms returns FALSE +T062C 26260:017.435 JLINK_HasError() +T062C 26260:017.507 JLINK_IsHalted() +T062C 26260:018.683 - 1.218ms returns FALSE +T062C 26260:118.874 JLINK_HasError() +T062C 26260:118.960 JLINK_IsHalted() +T062C 26260:120.200 - 1.281ms returns FALSE +T062C 26260:220.496 JLINK_HasError() +T062C 26260:220.585 JLINK_HasError() +T062C 26260:220.616 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26260:220.641 Data: 8D 12 74 01 +T062C 26260:220.662 Debug reg: DWT_CYCCNT +T062C 26260:220.680 - 0.071ms returns 1 (0x1) +T3F74 26260:223.101 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26260:223.135 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26260:224.330 Data: 00 00 80 00 +T3F74 26260:224.400 - 1.307ms returns 4 (0x4) +T3F74 26260:224.439 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26260:224.462 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26260:225.549 Data: 00 00 F0 01 +T3F74 26260:225.575 - 1.143ms returns 4 (0x4) +T3F74 26260:228.794 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26260:228.821 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26260:230.107 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26260:230.135 - 1.348ms returns 16 (0x10) +T3F74 26260:230.156 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26260:230.175 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26260:230.552 Data: 1E 00 00 00 +T3F74 26260:230.573 - 0.424ms returns 4 (0x4) +T3F74 26260:230.590 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26260:230.607 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26260:231.054 Data: 00 00 00 00 00 00 00 00 00 00 00 00 43 01 00 00 ... +T3F74 26260:231.074 - 0.490ms returns 20 (0x14) +T3F74 26260:231.091 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26260:231.107 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26260:231.553 Data: 1F 03 00 00 +T3F74 26260:231.573 - 0.488ms returns 4 (0x4) +T3F74 26260:231.590 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26260:231.606 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26260:232.048 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26260:232.068 - 0.485ms returns 12 (0xC) +T3F74 26260:232.085 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26260:232.101 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26260:232.564 Data: 00 00 00 00 +T3F74 26260:232.584 - 0.506ms returns 4 (0x4) +T3F74 26260:232.601 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26260:232.617 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26260:233.048 Data: 00 00 00 00 +T3F74 26260:233.068 - 0.473ms returns 4 (0x4) +T3F74 26260:233.085 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26260:233.101 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26260:233.674 Data: 00 00 00 00 +T3F74 26260:233.711 - 0.635ms returns 4 (0x4) +T062C 26260:245.740 JLINK_IsHalted() +T062C 26260:246.876 - 1.155ms returns FALSE +T062C 26260:347.065 JLINK_HasError() +T062C 26260:347.115 JLINK_IsHalted() +T062C 26260:348.305 - 1.208ms returns FALSE +T062C 26260:448.501 JLINK_HasError() +T062C 26260:448.574 JLINK_IsHalted() +T062C 26260:449.735 - 1.204ms returns FALSE +T062C 26260:550.125 JLINK_HasError() +T062C 26260:550.196 JLINK_IsHalted() +T062C 26260:551.351 - 1.196ms returns FALSE +T062C 26260:651.553 JLINK_HasError() +T062C 26260:651.624 JLINK_IsHalted() +T062C 26260:652.840 - 1.234ms returns FALSE +T062C 26260:752.950 JLINK_HasError() +T062C 26260:752.977 JLINK_HasError() +T062C 26260:752.993 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26260:753.018 Data: 8D 12 74 01 +T062C 26260:753.038 Debug reg: DWT_CYCCNT +T062C 26260:753.057 - 0.071ms returns 1 (0x1) +T3F74 26260:755.645 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26260:755.694 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26260:756.824 Data: 00 00 80 00 +T3F74 26260:756.906 - 1.280ms returns 4 (0x4) +T3F74 26260:756.956 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26260:756.988 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26260:758.238 Data: 00 00 F0 01 +T3F74 26260:758.271 - 1.322ms returns 4 (0x4) +T3F74 26260:761.542 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26260:761.574 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26260:762.789 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26260:762.817 - 1.281ms returns 16 (0x10) +T3F74 26260:762.837 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26260:762.857 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26260:763.228 Data: 1E 00 00 00 +T3F74 26260:763.249 - 0.418ms returns 4 (0x4) +T3F74 26260:763.266 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26260:763.282 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26260:763.734 Data: 00 00 00 00 00 00 00 00 00 00 00 00 93 00 00 00 ... +T3F74 26260:763.754 - 0.495ms returns 20 (0x14) +T3F74 26260:763.771 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26260:763.788 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26260:764.227 Data: 1F 03 00 00 +T3F74 26260:764.248 - 0.483ms returns 4 (0x4) +T3F74 26260:764.265 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26260:764.281 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26260:764.911 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26260:764.946 - 0.689ms returns 12 (0xC) +T3F74 26260:764.972 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26260:764.995 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26260:766.148 Data: 00 00 00 00 +T3F74 26260:766.182 - 1.218ms returns 4 (0x4) +T3F74 26260:766.206 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26260:766.228 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26260:766.739 Data: 00 00 00 00 +T3F74 26260:766.763 - 0.565ms returns 4 (0x4) +T3F74 26260:766.784 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26260:766.803 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26260:767.233 Data: 00 00 00 00 +T3F74 26260:767.257 - 0.481ms returns 4 (0x4) +T062C 26260:779.540 JLINK_IsHalted() +T062C 26260:780.673 - 1.154ms returns FALSE +T062C 26260:880.819 JLINK_HasError() +T062C 26260:880.911 JLINK_IsHalted() +T062C 26260:881.983 - 1.087ms returns FALSE +T062C 26260:982.835 JLINK_HasError() +T062C 26260:982.890 JLINK_IsHalted() +T062C 26260:983.965 - 1.086ms returns FALSE +T062C 26261:084.171 JLINK_HasError() +T062C 26261:084.245 JLINK_IsHalted() +T062C 26261:085.475 - 1.247ms returns FALSE +T062C 26261:186.356 JLINK_HasError() +T062C 26261:186.403 JLINK_IsHalted() +T062C 26261:187.504 - 1.123ms returns FALSE +T062C 26261:287.940 JLINK_HasError() +T062C 26261:288.017 JLINK_HasError() +T062C 26261:288.060 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26261:288.086 Data: 8D 12 74 01 +T062C 26261:288.107 Debug reg: DWT_CYCCNT +T062C 26261:288.125 - 0.072ms returns 1 (0x1) +T3F74 26261:290.644 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26261:290.677 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26261:291.818 Data: 00 00 80 00 +T3F74 26261:291.858 - 1.222ms returns 4 (0x4) +T3F74 26261:291.905 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26261:291.928 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26261:292.420 Data: 00 00 F0 01 +T3F74 26261:292.444 - 0.547ms returns 4 (0x4) +T3F74 26261:295.796 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26261:295.827 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26261:297.039 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26261:297.061 - 1.272ms returns 16 (0x10) +T3F74 26261:297.080 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26261:297.096 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26261:297.538 Data: 1E 00 00 00 +T3F74 26261:297.558 - 0.485ms returns 4 (0x4) +T3F74 26261:297.576 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26261:297.592 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26261:298.036 Data: 00 00 00 00 00 00 00 00 00 00 00 00 3B 01 00 00 ... +T3F74 26261:298.056 - 0.487ms returns 20 (0x14) +T3F74 26261:298.079 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26261:298.100 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26261:298.536 Data: 1F 03 00 00 +T3F74 26261:298.556 - 0.484ms returns 4 (0x4) +T3F74 26261:298.574 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26261:298.590 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26261:299.035 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26261:299.055 - 0.488ms returns 12 (0xC) +T3F74 26261:299.072 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26261:299.089 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26261:299.536 Data: 00 00 00 00 +T3F74 26261:299.556 - 0.490ms returns 4 (0x4) +T3F74 26261:299.573 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26261:299.589 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26261:300.035 Data: 00 00 00 00 +T3F74 26261:300.055 - 0.488ms returns 4 (0x4) +T3F74 26261:300.072 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26261:300.088 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26261:300.532 Data: 00 00 00 00 +T3F74 26261:300.552 - 0.486ms returns 4 (0x4) +T062C 26261:313.196 JLINK_IsHalted() +T062C 26261:314.295 - 1.118ms returns FALSE +T062C 26261:414.664 JLINK_HasError() +T062C 26261:414.743 JLINK_IsHalted() +T062C 26261:416.036 - 1.311ms returns FALSE +T062C 26261:516.859 JLINK_HasError() +T062C 26261:516.895 JLINK_IsHalted() +T062C 26261:517.938 - 1.085ms returns FALSE +T062C 26261:618.674 JLINK_HasError() +T062C 26261:618.702 JLINK_IsHalted() +T062C 26261:619.865 - 1.181ms returns FALSE +T062C 26261:720.644 JLINK_HasError() +T062C 26261:720.716 JLINK_IsHalted() +T062C 26261:721.851 - 1.152ms returns FALSE +T062C 26261:822.039 JLINK_HasError() +T062C 26261:822.116 JLINK_HasError() +T062C 26261:822.161 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26261:822.222 Data: 8D 12 74 01 +T062C 26261:822.242 Debug reg: DWT_CYCCNT +T062C 26261:822.261 - 0.106ms returns 1 (0x1) +T3F74 26261:825.106 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26261:825.139 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26261:826.275 Data: 00 00 80 00 +T3F74 26261:826.308 - 1.210ms returns 4 (0x4) +T3F74 26261:826.348 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26261:826.371 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26261:826.842 Data: 00 00 F0 01 +T3F74 26261:826.866 - 0.525ms returns 4 (0x4) +T3F74 26261:830.280 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26261:830.311 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26261:831.570 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26261:831.598 - 1.325ms returns 16 (0x10) +T3F74 26261:831.618 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26261:831.638 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26261:832.093 Data: 1F 00 00 00 +T3F74 26261:832.113 - 0.501ms returns 4 (0x4) +T3F74 26261:832.131 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26261:832.147 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26261:832.590 Data: 00 00 00 00 00 00 00 00 00 00 00 00 39 02 00 00 ... +T3F74 26261:832.610 - 0.486ms returns 20 (0x14) +T3F74 26261:832.628 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26261:832.644 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26261:833.091 Data: 1F 03 00 00 +T3F74 26261:833.111 - 0.489ms returns 4 (0x4) +T3F74 26261:833.128 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26261:833.144 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26261:833.590 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26261:833.610 - 0.488ms returns 12 (0xC) +T3F74 26261:833.627 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26261:833.643 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26261:834.090 Data: 00 00 00 00 +T3F74 26261:834.109 - 0.489ms returns 4 (0x4) +T3F74 26261:834.126 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26261:834.142 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26261:834.589 Data: 00 00 00 00 +T3F74 26261:834.724 - 0.604ms returns 4 (0x4) +T3F74 26261:834.742 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26261:834.759 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26261:835.213 Data: 00 00 00 00 +T3F74 26261:835.233 - 0.497ms returns 4 (0x4) +T062C 26261:854.357 JLINK_IsHalted() +T062C 26261:855.470 - 1.130ms returns FALSE +T062C 26261:956.216 JLINK_HasError() +T062C 26261:956.294 JLINK_IsHalted() +T062C 26261:957.547 - 1.295ms returns FALSE +T062C 26262:058.360 JLINK_HasError() +T062C 26262:058.393 JLINK_IsHalted() +T062C 26262:059.486 - 1.110ms returns FALSE +T062C 26262:160.236 JLINK_HasError() +T062C 26262:160.310 JLINK_IsHalted() +T062C 26262:161.555 - 1.294ms returns FALSE +T062C 26262:262.303 JLINK_HasError() +T062C 26262:262.347 JLINK_IsHalted() +T062C 26262:263.458 - 1.128ms returns FALSE +T062C 26262:364.010 JLINK_HasError() +T062C 26262:364.090 JLINK_HasError() +T062C 26262:364.135 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26262:364.193 Data: 8D 12 74 01 +T062C 26262:364.214 Debug reg: DWT_CYCCNT +T062C 26262:364.233 - 0.104ms returns 1 (0x1) +T3F74 26262:366.779 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26262:366.812 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26262:367.992 Data: 00 00 80 00 +T3F74 26262:368.079 - 1.320ms returns 4 (0x4) +T3F74 26262:368.171 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26262:368.228 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26262:369.284 Data: 00 00 F0 01 +T3F74 26262:369.310 - 1.147ms returns 4 (0x4) +T3F74 26262:372.602 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26262:372.633 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26262:373.783 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26262:373.809 - 1.214ms returns 16 (0x10) +T3F74 26262:373.830 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26262:373.849 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26262:374.272 Data: 1E 00 00 00 +T3F74 26262:374.296 - 0.473ms returns 4 (0x4) +T3F74 26262:374.316 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26262:374.335 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26262:374.903 Data: 00 00 00 00 00 00 00 00 00 00 00 00 83 02 00 00 ... +T3F74 26262:374.928 - 0.620ms returns 20 (0x14) +T3F74 26262:374.948 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26262:374.967 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26262:375.389 Data: 1F 03 00 00 +T3F74 26262:375.409 - 0.468ms returns 4 (0x4) +T3F74 26262:375.427 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26262:375.443 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26262:375.888 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26262:375.908 - 0.488ms returns 12 (0xC) +T3F74 26262:375.925 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26262:375.941 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26262:376.403 Data: 00 00 00 00 +T3F74 26262:376.427 - 0.509ms returns 4 (0x4) +T3F74 26262:376.447 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26262:376.466 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26262:376.893 Data: 00 00 00 00 +T3F74 26262:376.939 - 0.500ms returns 4 (0x4) +T3F74 26262:376.959 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26262:376.978 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26262:377.399 Data: 00 00 00 00 +T3F74 26262:377.430 - 0.478ms returns 4 (0x4) +T062C 26262:397.136 JLINK_IsHalted() +T062C 26262:398.285 - 1.167ms returns FALSE +T062C 26262:498.693 JLINK_HasError() +T062C 26262:498.741 JLINK_IsHalted() +T062C 26262:499.833 - 1.111ms returns FALSE +T062C 26262:601.525 JLINK_HasError() +T062C 26262:601.600 JLINK_IsHalted() +T062C 26262:602.632 - 1.056ms returns FALSE +T062C 26262:703.314 JLINK_HasError() +T062C 26262:703.341 JLINK_IsHalted() +T062C 26262:704.480 - 1.186ms returns FALSE +T062C 26262:805.000 JLINK_HasError() +T062C 26262:805.074 JLINK_IsHalted() +T062C 26262:806.321 - 1.291ms returns FALSE +T062C 26262:906.544 JLINK_HasError() +T062C 26262:906.630 JLINK_HasError() +T062C 26262:906.675 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26262:906.723 Data: 8D 12 74 01 +T062C 26262:906.744 Debug reg: DWT_CYCCNT +T062C 26262:906.763 - 0.094ms returns 1 (0x1) +T3F74 26262:909.220 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26262:909.253 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26262:910.452 Data: 00 00 80 00 +T3F74 26262:910.515 - 1.303ms returns 4 (0x4) +T3F74 26262:910.557 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26262:910.581 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26262:911.845 Data: 00 00 F0 01 +T3F74 26262:911.931 - 1.393ms returns 4 (0x4) +T3F74 26262:915.814 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26262:915.849 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26262:917.171 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26262:917.254 - 1.448ms returns 16 (0x10) +T3F74 26262:917.278 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26262:917.301 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26262:917.702 Data: 1E 00 00 00 +T3F74 26262:917.726 - 0.455ms returns 4 (0x4) +T3F74 26262:917.746 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26262:917.766 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26262:918.322 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1B 00 00 00 ... +T3F74 26262:918.342 - 0.602ms returns 20 (0x14) +T3F74 26262:918.359 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26262:918.375 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26262:918.844 Data: 1F 03 00 00 +T3F74 26262:918.864 - 0.511ms returns 4 (0x4) +T3F74 26262:918.881 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26262:918.897 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26262:919.322 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26262:919.342 - 0.467ms returns 12 (0xC) +T3F74 26262:919.359 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26262:919.375 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26262:919.820 Data: 00 00 00 00 +T3F74 26262:919.840 - 0.488ms returns 4 (0x4) +T3F74 26262:919.857 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26262:919.873 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26262:920.321 Data: 00 00 00 00 +T3F74 26262:920.341 - 0.490ms returns 4 (0x4) +T3F74 26262:920.358 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26262:920.374 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26262:920.816 Data: 00 00 00 00 +T3F74 26262:920.836 - 0.485ms returns 4 (0x4) +T062C 26262:932.961 JLINK_IsHalted() +T062C 26262:934.096 - 1.153ms returns FALSE +T062C 26263:034.880 JLINK_HasError() +T062C 26263:034.961 JLINK_IsHalted() +T062C 26263:036.172 - 1.229ms returns FALSE +T062C 26263:137.203 JLINK_HasError() +T062C 26263:137.286 JLINK_IsHalted() +T062C 26263:138.503 - 1.259ms returns FALSE +T062C 26263:239.166 JLINK_HasError() +T062C 26263:239.199 JLINK_IsHalted() +T062C 26263:240.346 - 1.175ms returns FALSE +T062C 26263:340.871 JLINK_HasError() +T062C 26263:340.945 JLINK_IsHalted() +T062C 26263:342.181 - 1.339ms returns FALSE +T062C 26263:442.800 JLINK_HasError() +T062C 26263:442.842 JLINK_HasError() +T062C 26263:442.860 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26263:442.890 Data: 8D 12 74 01 +T062C 26263:442.914 Debug reg: DWT_CYCCNT +T062C 26263:442.936 - 0.083ms returns 1 (0x1) +T3F74 26263:446.356 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26263:446.396 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26263:447.556 Data: 00 00 80 00 +T3F74 26263:447.611 - 1.263ms returns 4 (0x4) +T3F74 26263:447.649 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26263:447.672 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26263:448.126 Data: 00 00 F0 01 +T3F74 26263:448.150 - 0.508ms returns 4 (0x4) +T3F74 26263:451.657 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26263:451.688 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26263:452.888 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26263:452.928 - 1.279ms returns 16 (0x10) +T3F74 26263:452.951 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26263:452.974 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26263:453.403 Data: 1E 00 00 00 +T3F74 26263:453.427 - 0.483ms returns 4 (0x4) +T3F74 26263:453.448 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26263:453.467 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26263:454.003 Data: 00 00 00 00 00 00 00 00 00 00 00 00 A5 00 00 00 ... +T3F74 26263:454.026 - 0.586ms returns 20 (0x14) +T3F74 26263:454.047 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26263:454.066 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26263:454.500 Data: 1F 03 00 00 +T3F74 26263:454.524 - 0.485ms returns 4 (0x4) +T3F74 26263:454.544 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26263:454.563 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26263:455.001 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26263:455.025 - 0.489ms returns 12 (0xC) +T3F74 26263:455.045 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26263:455.064 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26263:455.500 Data: 00 00 00 00 +T3F74 26263:455.524 - 0.486ms returns 4 (0x4) +T3F74 26263:455.544 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26263:455.563 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26263:456.001 Data: 00 00 00 00 +T3F74 26263:456.025 - 0.488ms returns 4 (0x4) +T3F74 26263:456.045 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26263:456.064 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26263:456.500 Data: 00 00 00 00 +T3F74 26263:456.523 - 0.486ms returns 4 (0x4) +T062C 26263:469.010 JLINK_IsHalted() +T062C 26263:470.130 - 1.139ms returns FALSE +T062C 26263:570.991 JLINK_HasError() +T062C 26263:571.055 JLINK_IsHalted() +T062C 26263:572.127 - 1.088ms returns FALSE +T062C 26263:672.846 JLINK_HasError() +T062C 26263:672.894 JLINK_IsHalted() +T062C 26263:673.989 - 1.103ms returns FALSE +T062C 26263:774.080 JLINK_HasError() +T062C 26263:774.158 JLINK_IsHalted() +T062C 26263:775.464 - 1.354ms returns FALSE +T062C 26263:875.846 JLINK_HasError() +T062C 26263:875.927 JLINK_IsHalted() +T062C 26263:876.988 - 1.079ms returns FALSE +T062C 26263:977.962 JLINK_HasError() +T062C 26263:978.003 JLINK_HasError() +T062C 26263:978.023 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26263:978.054 Data: 8D 12 74 01 +T062C 26263:978.079 Debug reg: DWT_CYCCNT +T062C 26263:978.101 - 0.087ms returns 1 (0x1) +T3F74 26263:980.660 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26263:980.697 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26263:981.851 Data: 00 00 80 00 +T3F74 26263:981.941 - 1.297ms returns 4 (0x4) +T3F74 26263:982.016 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26263:982.043 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26263:982.580 Data: 00 00 F0 01 +T3F74 26263:982.605 - 0.597ms returns 4 (0x4) +T3F74 26263:986.060 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26263:986.092 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26263:987.321 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26263:987.354 - 1.301ms returns 16 (0x10) +T3F74 26263:987.378 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26263:987.400 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26263:987.805 Data: 1E 00 00 00 +T3F74 26263:987.829 - 0.459ms returns 4 (0x4) +T3F74 26263:987.849 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26263:987.869 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26263:988.432 Data: 00 00 00 00 00 00 00 00 00 00 00 00 8F 02 00 00 ... +T3F74 26263:988.455 - 0.614ms returns 20 (0x14) +T3F74 26263:988.476 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26263:988.495 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26263:988.937 Data: 1F 03 00 00 +T3F74 26263:988.960 - 0.493ms returns 4 (0x4) +T3F74 26263:988.981 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26263:989.000 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26263:989.430 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26263:989.453 - 0.480ms returns 12 (0xC) +T3F74 26263:989.474 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26263:989.492 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26263:989.953 Data: 00 00 00 00 +T3F74 26263:989.977 - 0.511ms returns 4 (0x4) +T3F74 26263:989.997 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26263:990.016 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26263:990.431 Data: 00 00 00 00 +T3F74 26263:990.454 - 0.465ms returns 4 (0x4) +T3F74 26263:990.474 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26263:990.493 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26263:990.935 Data: 00 00 00 00 +T3F74 26263:990.959 - 0.492ms returns 4 (0x4) +T062C 26264:003.632 JLINK_IsHalted() +T062C 26264:004.688 - 1.070ms returns FALSE +T062C 26264:104.955 JLINK_HasError() +T062C 26264:104.997 JLINK_IsHalted() +T062C 26264:106.074 - 1.104ms returns FALSE +T062C 26264:207.002 JLINK_HasError() +T062C 26264:207.043 JLINK_IsHalted() +T062C 26264:208.210 - 1.184ms returns FALSE +T062C 26264:308.971 JLINK_HasError() +T062C 26264:309.010 JLINK_IsHalted() +T062C 26264:310.042 - 1.046ms returns FALSE +T062C 26264:410.972 JLINK_HasError() +T062C 26264:411.014 JLINK_IsHalted() +T062C 26264:412.315 - 1.318ms returns FALSE +T062C 26264:513.088 JLINK_HasError() +T062C 26264:513.125 JLINK_HasError() +T062C 26264:513.144 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26264:513.175 Data: 8D 12 74 01 +T062C 26264:513.199 Debug reg: DWT_CYCCNT +T062C 26264:513.222 - 0.085ms returns 1 (0x1) +T3F74 26264:516.230 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26264:516.302 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26264:517.387 Data: 00 00 80 00 +T3F74 26264:517.425 - 1.203ms returns 4 (0x4) +T3F74 26264:517.477 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26264:517.503 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26264:517.997 Data: 00 00 F0 01 +T3F74 26264:518.028 - 0.559ms returns 4 (0x4) +T3F74 26264:521.685 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26264:521.718 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26264:522.909 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26264:522.945 - 1.268ms returns 16 (0x10) +T3F74 26264:522.971 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26264:522.994 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26264:523.499 Data: 1E 00 00 00 +T3F74 26264:523.526 - 0.564ms returns 4 (0x4) +T3F74 26264:523.548 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26264:523.569 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26264:524.175 Data: 00 00 00 00 00 00 00 00 00 00 00 00 27 00 00 00 ... +T3F74 26264:524.207 - 0.669ms returns 20 (0x14) +T3F74 26264:524.235 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26264:524.259 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26264:524.749 Data: 1F 03 00 00 +T3F74 26264:524.775 - 0.548ms returns 4 (0x4) +T3F74 26264:524.797 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26264:524.817 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26264:525.371 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26264:525.406 - 0.617ms returns 12 (0xC) +T3F74 26264:525.431 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26264:525.455 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26264:525.863 Data: 00 00 00 00 +T3F74 26264:525.888 - 0.464ms returns 4 (0x4) +T3F74 26264:525.909 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26264:525.928 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26264:526.363 Data: 00 00 00 00 +T3F74 26264:526.387 - 0.486ms returns 4 (0x4) +T3F74 26264:526.408 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26264:526.427 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26264:526.876 Data: 00 00 00 00 +T3F74 26264:526.902 - 0.502ms returns 4 (0x4) +T062C 26264:541.736 JLINK_IsHalted() +T062C 26264:542.953 - 1.247ms returns FALSE +T062C 26264:643.899 JLINK_HasError() +T062C 26264:643.942 JLINK_IsHalted() +T062C 26264:644.985 - 1.063ms returns FALSE +T062C 26264:746.057 JLINK_HasError() +T062C 26264:746.145 JLINK_IsHalted() +T062C 26264:747.333 - 1.238ms returns FALSE +T062C 26264:847.591 JLINK_HasError() +T062C 26264:847.672 JLINK_IsHalted() +T062C 26264:848.982 - 1.354ms returns FALSE +T062C 26264:949.220 JLINK_HasError() +T062C 26264:949.299 JLINK_IsHalted() +T062C 26264:950.531 - 1.249ms returns FALSE +T062C 26265:050.766 JLINK_HasError() +T062C 26265:050.843 JLINK_HasError() +T062C 26265:050.892 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26265:050.919 Data: 8D 12 74 01 +T062C 26265:050.939 Debug reg: DWT_CYCCNT +T062C 26265:050.958 - 0.074ms returns 1 (0x1) +T3F74 26265:053.593 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26265:053.638 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26265:055.088 Data: 00 00 80 00 +T3F74 26265:055.196 - 1.614ms returns 4 (0x4) +T3F74 26265:055.245 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26265:055.273 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26265:056.297 Data: 00 00 F0 01 +T3F74 26265:056.333 - 1.096ms returns 4 (0x4) +T3F74 26265:059.664 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26265:059.699 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26265:060.929 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26265:060.965 - 1.309ms returns 16 (0x10) +T3F74 26265:060.991 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26265:061.014 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26265:061.553 Data: 1E 00 00 00 +T3F74 26265:061.577 - 0.593ms returns 4 (0x4) +T3F74 26265:061.598 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26265:061.617 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26265:062.164 Data: 00 00 00 00 00 00 00 00 00 00 00 00 51 02 00 00 ... +T3F74 26265:062.187 - 0.597ms returns 20 (0x14) +T3F74 26265:062.220 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26265:062.239 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26265:062.672 Data: 1F 03 00 00 +T3F74 26265:062.696 - 0.483ms returns 4 (0x4) +T3F74 26265:062.718 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26265:062.737 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26265:063.167 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26265:063.191 - 0.480ms returns 12 (0xC) +T3F74 26265:063.222 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26265:063.241 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26265:063.662 Data: 00 00 00 00 +T3F74 26265:063.686 - 0.471ms returns 4 (0x4) +T3F74 26265:063.708 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26265:063.727 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26265:064.176 Data: 00 00 00 00 +T3F74 26265:064.200 - 0.499ms returns 4 (0x4) +T3F74 26265:064.231 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26265:064.250 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26265:064.670 Data: 00 00 00 00 +T3F74 26265:064.694 - 0.471ms returns 4 (0x4) +T062C 26265:076.772 JLINK_IsHalted() +T062C 26265:077.817 - 1.062ms returns FALSE +T062C 26265:178.335 JLINK_HasError() +T062C 26265:178.391 JLINK_IsHalted() +T062C 26265:179.443 - 1.085ms returns FALSE +T062C 26265:279.665 JLINK_HasError() +T062C 26265:279.736 JLINK_IsHalted() +T062C 26265:281.004 - 1.310ms returns FALSE +T062C 26265:382.129 JLINK_HasError() +T062C 26265:382.201 JLINK_IsHalted() +T062C 26265:383.467 - 1.307ms returns FALSE +T062C 26265:483.725 JLINK_HasError() +T062C 26265:483.773 JLINK_IsHalted() +T062C 26265:484.881 - 1.131ms returns FALSE +T062C 26265:585.704 JLINK_HasError() +T062C 26265:585.744 JLINK_HasError() +T062C 26265:585.766 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26265:585.797 Data: 8D 12 74 01 +T062C 26265:585.821 Debug reg: DWT_CYCCNT +T062C 26265:585.843 - 0.084ms returns 1 (0x1) +T3F74 26265:592.230 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26265:592.269 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26265:593.406 Data: 00 00 80 00 +T3F74 26265:593.441 - 1.219ms returns 4 (0x4) +T3F74 26265:593.481 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26265:593.504 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26265:593.968 Data: 00 00 F0 01 +T3F74 26265:593.992 - 0.519ms returns 4 (0x4) +T3F74 26265:597.575 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26265:597.602 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26265:598.938 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26265:598.971 - 1.404ms returns 16 (0x10) +T3F74 26265:598.994 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26265:599.017 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26265:599.467 Data: 1E 00 00 00 +T3F74 26265:599.491 - 0.505ms returns 4 (0x4) +T3F74 26265:599.512 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26265:599.531 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26265:600.105 Data: 00 00 00 00 00 00 00 00 00 00 00 00 25 01 00 00 ... +T3F74 26265:600.137 - 0.633ms returns 20 (0x14) +T3F74 26265:600.161 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26265:600.184 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26265:600.732 Data: 1F 03 00 00 +T3F74 26265:600.803 - 0.650ms returns 4 (0x4) +T3F74 26265:600.898 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26265:600.934 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26265:601.478 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26265:601.508 - 0.618ms returns 12 (0xC) +T3F74 26265:601.530 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26265:601.551 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26265:601.967 Data: 00 00 00 00 +T3F74 26265:601.991 - 0.468ms returns 4 (0x4) +T3F74 26265:602.011 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26265:602.030 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26265:602.471 Data: 00 00 00 00 +T3F74 26265:602.495 - 0.492ms returns 4 (0x4) +T3F74 26265:602.515 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26265:602.535 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26265:602.976 Data: 00 00 00 00 +T3F74 26265:603.011 - 0.503ms returns 4 (0x4) +T062C 26265:616.303 JLINK_IsHalted() +T062C 26265:617.354 - 1.069ms returns FALSE +T062C 26265:718.000 JLINK_HasError() +T062C 26265:718.049 JLINK_IsHalted() +T062C 26265:719.194 - 1.163ms returns FALSE +T062C 26265:819.985 JLINK_HasError() +T062C 26265:820.062 JLINK_IsHalted() +T062C 26265:821.191 - 1.178ms returns FALSE +T062C 26265:922.348 JLINK_HasError() +T062C 26265:922.419 JLINK_IsHalted() +T062C 26265:923.439 - 1.038ms returns FALSE +T062C 26266:023.638 JLINK_HasError() +T062C 26266:023.712 JLINK_IsHalted() +T062C 26266:024.797 - 1.104ms returns FALSE +T062C 26266:125.503 JLINK_HasError() +T062C 26266:125.530 JLINK_HasError() +T062C 26266:125.545 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26266:125.571 Data: 8D 12 74 01 +T062C 26266:125.591 Debug reg: DWT_CYCCNT +T062C 26266:125.610 - 0.071ms returns 1 (0x1) +T3F74 26266:128.199 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26266:128.233 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26266:129.366 Data: 00 00 80 00 +T3F74 26266:129.401 - 1.210ms returns 4 (0x4) +T3F74 26266:129.440 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26266:129.463 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26266:129.964 Data: 00 00 F0 01 +T3F74 26266:130.003 - 0.571ms returns 4 (0x4) +T3F74 26266:133.291 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26266:133.323 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26266:134.576 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26266:134.605 - 1.321ms returns 16 (0x10) +T3F74 26266:134.626 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26266:134.645 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26266:135.019 Data: 1E 00 00 00 +T3F74 26266:135.039 - 0.420ms returns 4 (0x4) +T3F74 26266:135.057 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26266:135.080 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26266:135.514 Data: 00 00 00 00 00 00 00 00 00 00 00 00 CD 00 00 00 ... +T3F74 26266:135.535 - 0.485ms returns 20 (0x14) +T3F74 26266:135.552 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26266:135.568 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26266:136.014 Data: 1F 03 00 00 +T3F74 26266:136.034 - 0.488ms returns 4 (0x4) +T3F74 26266:136.051 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26266:136.067 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26266:136.515 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26266:136.535 - 0.491ms returns 12 (0xC) +T3F74 26266:136.567 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26266:136.583 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26266:137.047 Data: 00 00 00 00 +T3F74 26266:137.071 - 0.512ms returns 4 (0x4) +T3F74 26266:137.093 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26266:137.113 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26266:137.523 Data: 00 00 00 00 +T3F74 26266:137.547 - 0.461ms returns 4 (0x4) +T3F74 26266:137.570 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26266:137.589 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26266:138.029 Data: 00 00 00 00 +T3F74 26266:138.052 - 0.489ms returns 4 (0x4) +T062C 26266:149.992 JLINK_IsHalted() +T062C 26266:151.064 - 1.091ms returns FALSE +T062C 26266:251.718 JLINK_HasError() +T062C 26266:251.793 JLINK_IsHalted() +T062C 26266:252.999 - 1.224ms returns FALSE +T062C 26266:353.766 JLINK_HasError() +T062C 26266:353.839 JLINK_IsHalted() +T062C 26266:354.967 - 1.147ms returns FALSE +T062C 26266:455.601 JLINK_HasError() +T062C 26266:455.628 JLINK_IsHalted() +T062C 26266:456.743 - 1.126ms returns FALSE +T062C 26266:557.789 JLINK_HasError() +T062C 26266:557.845 JLINK_IsHalted() +T062C 26266:559.007 - 1.192ms returns FALSE +T062C 26266:659.739 JLINK_HasError() +T062C 26266:659.842 JLINK_HasError() +T062C 26266:659.864 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26266:659.900 Data: 8D 12 74 01 +T062C 26266:659.934 Debug reg: DWT_CYCCNT +T062C 26266:659.962 - 0.105ms returns 1 (0x1) +T3F74 26266:662.333 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26266:662.364 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26266:663.542 Data: 00 00 80 00 +T3F74 26266:663.593 - 1.268ms returns 4 (0x4) +T3F74 26266:663.632 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26266:663.655 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26266:664.082 Data: 00 00 F0 01 +T3F74 26266:664.106 - 0.482ms returns 4 (0x4) +T3F74 26266:667.125 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26266:667.152 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26266:668.338 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26266:668.362 - 1.245ms returns 16 (0x10) +T3F74 26266:668.383 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26266:668.402 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26266:668.829 Data: 1E 00 00 00 +T3F74 26266:668.853 - 0.477ms returns 4 (0x4) +T3F74 26266:668.875 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26266:668.894 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26266:669.449 Data: 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 ... +T3F74 26266:669.469 - 0.601ms returns 20 (0x14) +T3F74 26266:669.487 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26266:669.503 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26266:669.947 Data: 1F 03 00 00 +T3F74 26266:669.967 - 0.487ms returns 4 (0x4) +T3F74 26266:669.984 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26266:670.000 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26266:670.448 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26266:670.468 - 0.490ms returns 12 (0xC) +T3F74 26266:670.485 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26266:670.501 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26266:670.948 Data: 00 00 00 00 +T3F74 26266:670.968 - 0.496ms returns 4 (0x4) +T3F74 26266:670.992 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26266:671.008 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26266:671.448 Data: 00 00 00 00 +T3F74 26266:671.468 - 0.482ms returns 4 (0x4) +T3F74 26266:671.485 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26266:671.501 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26266:671.947 Data: 00 00 00 00 +T3F74 26266:671.967 - 0.488ms returns 4 (0x4) +T062C 26266:683.795 JLINK_IsHalted() +T062C 26266:684.888 - 1.113ms returns FALSE +T062C 26266:785.524 JLINK_HasError() +T062C 26266:785.574 JLINK_IsHalted() +T062C 26266:786.771 - 1.216ms returns FALSE +T062C 26266:887.343 JLINK_HasError() +T062C 26266:887.416 JLINK_IsHalted() +T062C 26266:888.620 - 1.246ms returns FALSE +T062C 26266:988.849 JLINK_HasError() +T062C 26266:988.920 JLINK_IsHalted() +T062C 26266:990.127 - 1.225ms returns FALSE +T062C 26267:090.801 JLINK_HasError() +T062C 26267:090.828 JLINK_IsHalted() +T062C 26267:092.017 - 1.237ms returns FALSE +T062C 26267:192.214 JLINK_HasError() +T062C 26267:192.245 JLINK_HasError() +T062C 26267:192.264 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26267:192.292 Data: 8D 12 74 01 +T062C 26267:192.316 Debug reg: DWT_CYCCNT +T062C 26267:192.338 - 0.081ms returns 1 (0x1) +T3F74 26267:195.510 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26267:195.543 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26267:196.733 Data: 00 00 80 00 +T3F74 26267:196.768 - 1.266ms returns 4 (0x4) +T3F74 26267:196.806 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26267:196.830 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26267:197.254 Data: 00 00 F0 01 +T3F74 26267:197.275 - 0.475ms returns 4 (0x4) +T3F74 26267:200.453 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26267:200.484 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26267:201.660 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26267:201.688 - 1.243ms returns 16 (0x10) +T3F74 26267:201.711 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26267:201.732 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26267:202.134 Data: 1E 00 00 00 +T3F74 26267:202.158 - 0.455ms returns 4 (0x4) +T3F74 26267:202.178 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26267:202.197 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26267:202.747 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E1 01 00 00 ... +T3F74 26267:202.767 - 0.595ms returns 20 (0x14) +T3F74 26267:202.785 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26267:202.801 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26267:203.247 Data: 1F 03 00 00 +T3F74 26267:203.267 - 0.489ms returns 4 (0x4) +T3F74 26267:203.284 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26267:203.300 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26267:203.747 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26267:203.767 - 0.488ms returns 12 (0xC) +T3F74 26267:203.784 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26267:203.800 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26267:204.308 Data: 00 00 00 00 +T3F74 26267:204.371 - 0.601ms returns 4 (0x4) +T3F74 26267:204.403 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26267:204.430 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26267:204.913 Data: 00 00 00 00 +T3F74 26267:204.948 - 0.553ms returns 4 (0x4) +T3F74 26267:204.973 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26267:204.996 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26267:205.503 Data: 00 00 00 00 +T3F74 26267:205.527 - 0.561ms returns 4 (0x4) +T062C 26267:217.312 JLINK_IsHalted() +T062C 26267:218.392 - 1.098ms returns FALSE +T062C 26267:319.168 JLINK_HasError() +T062C 26267:319.243 JLINK_IsHalted() +T062C 26267:320.317 - 1.102ms returns FALSE +T062C 26267:420.718 JLINK_HasError() +T062C 26267:420.791 JLINK_IsHalted() +T062C 26267:421.961 - 1.211ms returns FALSE +T062C 26267:523.033 JLINK_HasError() +T062C 26267:523.104 JLINK_IsHalted() +T062C 26267:524.333 - 1.286ms returns FALSE +T062C 26267:624.653 JLINK_HasError() +T062C 26267:624.698 JLINK_IsHalted() +T062C 26267:625.854 - 1.178ms returns FALSE +T062C 26267:726.002 JLINK_HasError() +T062C 26267:726.084 JLINK_HasError() +T062C 26267:726.128 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26267:726.189 Data: 8D 12 74 01 +T062C 26267:726.279 Debug reg: DWT_CYCCNT +T062C 26267:726.298 - 0.176ms returns 1 (0x1) +T3F74 26267:728.895 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26267:728.933 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26267:730.209 Data: 00 00 80 00 +T3F74 26267:730.296 - 1.421ms returns 4 (0x4) +T3F74 26267:730.372 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26267:730.395 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26267:731.438 Data: 00 00 F0 01 +T3F74 26267:731.472 - 1.107ms returns 4 (0x4) +T3F74 26267:734.705 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26267:734.733 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26267:735.996 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26267:736.067 - 1.374ms returns 16 (0x10) +T3F74 26267:736.143 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26267:736.199 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26267:737.462 Data: 1E 00 00 00 +T3F74 26267:737.495 - 1.360ms returns 4 (0x4) +T3F74 26267:737.519 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26267:737.542 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26267:738.063 Data: 00 00 00 00 00 00 00 00 00 00 00 00 21 01 00 00 ... +T3F74 26267:738.087 - 0.575ms returns 20 (0x14) +T3F74 26267:738.107 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26267:738.127 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26267:738.562 Data: 1F 03 00 00 +T3F74 26267:738.585 - 0.485ms returns 4 (0x4) +T3F74 26267:738.605 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26267:738.624 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26267:739.056 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26267:739.076 - 0.477ms returns 12 (0xC) +T3F74 26267:739.093 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26267:739.109 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26267:739.556 Data: 00 00 00 00 +T3F74 26267:739.576 - 0.490ms returns 4 (0x4) +T3F74 26267:739.594 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26267:739.610 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26267:740.056 Data: 00 00 00 00 +T3F74 26267:740.076 - 0.488ms returns 4 (0x4) +T3F74 26267:740.093 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26267:740.109 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26267:740.554 Data: 00 00 00 00 +T3F74 26267:740.574 - 0.488ms returns 4 (0x4) +T062C 26267:752.832 JLINK_IsHalted() +T062C 26267:753.944 - 1.130ms returns FALSE +T062C 26267:854.145 JLINK_HasError() +T062C 26267:854.229 JLINK_IsHalted() +T062C 26267:855.439 - 1.253ms returns FALSE +T062C 26267:955.912 JLINK_HasError() +T062C 26267:955.951 JLINK_IsHalted() +T062C 26267:957.103 - 1.171ms returns FALSE +T062C 26268:057.887 JLINK_HasError() +T062C 26268:057.962 JLINK_IsHalted() +T062C 26268:059.143 - 1.200ms returns FALSE +T062C 26268:159.924 JLINK_HasError() +T062C 26268:159.997 JLINK_IsHalted() +T062C 26268:161.150 - 1.171ms returns FALSE +T062C 26268:261.995 JLINK_HasError() +T062C 26268:262.068 JLINK_HasError() +T062C 26268:262.113 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26268:262.177 Data: 8D 12 74 01 +T062C 26268:262.198 Debug reg: DWT_CYCCNT +T062C 26268:262.216 - 0.110ms returns 1 (0x1) +T3F74 26268:264.695 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26268:264.728 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26268:265.800 Data: 00 00 80 00 +T3F74 26268:265.837 - 1.150ms returns 4 (0x4) +T3F74 26268:265.880 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26268:265.903 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26268:266.365 Data: 00 00 F0 01 +T3F74 26268:266.385 - 0.512ms returns 4 (0x4) +T3F74 26268:269.451 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26268:269.484 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26268:270.620 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26268:270.645 - 1.202ms returns 16 (0x10) +T3F74 26268:270.666 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26268:270.686 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26268:271.111 Data: 1E 00 00 00 +T3F74 26268:271.135 - 0.477ms returns 4 (0x4) +T3F74 26268:271.158 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26268:271.178 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26268:271.742 Data: 00 00 00 00 00 00 00 00 00 00 00 00 BD 00 00 00 ... +T3F74 26268:271.766 - 0.616ms returns 20 (0x14) +T3F74 26268:271.787 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26268:271.806 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26268:272.241 Data: 1F 03 00 00 +T3F74 26268:272.265 - 0.486ms returns 4 (0x4) +T3F74 26268:272.286 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26268:272.305 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26268:272.770 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26268:272.791 - 0.512ms returns 12 (0xC) +T3F74 26268:272.809 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26268:272.825 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26268:273.235 Data: 00 00 00 00 +T3F74 26268:273.255 - 0.453ms returns 4 (0x4) +T3F74 26268:273.273 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26268:273.289 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26268:273.734 Data: 00 00 00 00 +T3F74 26268:273.755 - 0.489ms returns 4 (0x4) +T3F74 26268:273.772 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26268:273.789 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26268:274.234 Data: 00 00 00 00 +T3F74 26268:274.255 - 0.489ms returns 4 (0x4) +T062C 26268:285.970 JLINK_IsHalted() +T062C 26268:287.021 - 1.070ms returns FALSE +T062C 26268:387.788 JLINK_HasError() +T062C 26268:387.874 JLINK_IsHalted() +T062C 26268:389.118 - 1.267ms returns FALSE +T062C 26268:489.379 JLINK_HasError() +T062C 26268:489.451 JLINK_IsHalted() +T062C 26268:490.742 - 1.337ms returns FALSE +T062C 26268:590.983 JLINK_HasError() +T062C 26268:591.014 JLINK_IsHalted() +T062C 26268:592.131 - 1.136ms returns FALSE +T062C 26268:692.324 JLINK_HasError() +T062C 26268:692.370 JLINK_IsHalted() +T062C 26268:693.503 - 1.156ms returns FALSE +T062C 26268:793.953 JLINK_HasError() +T062C 26268:794.051 JLINK_HasError() +T062C 26268:794.085 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26268:794.125 Data: 8D 12 74 01 +T062C 26268:794.152 Debug reg: DWT_CYCCNT +T062C 26268:794.180 - 0.103ms returns 1 (0x1) +T3F74 26268:796.780 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26268:796.823 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26268:798.017 Data: 00 00 80 00 +T3F74 26268:798.077 - 1.304ms returns 4 (0x4) +T3F74 26268:798.112 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26268:798.132 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26268:798.541 Data: 00 00 F0 01 +T3F74 26268:798.562 - 0.456ms returns 4 (0x4) +T3F74 26268:801.535 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26268:801.583 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26268:802.810 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26268:802.843 - 1.316ms returns 16 (0x10) +T3F74 26268:802.867 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26268:802.890 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26268:803.289 Data: 1E 00 00 00 +T3F74 26268:803.310 - 0.450ms returns 4 (0x4) +T3F74 26268:803.327 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26268:803.344 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26268:803.789 Data: 00 00 00 00 00 00 00 00 00 00 00 00 41 00 00 00 ... +T3F74 26268:803.809 - 0.488ms returns 20 (0x14) +T3F74 26268:803.826 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26268:803.842 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26268:804.289 Data: 1F 03 00 00 +T3F74 26268:804.309 - 0.490ms returns 4 (0x4) +T3F74 26268:804.327 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26268:804.343 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26268:804.788 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26268:804.808 - 0.488ms returns 12 (0xC) +T3F74 26268:804.825 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26268:804.841 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26268:805.289 Data: 00 00 00 00 +T3F74 26268:805.309 - 0.490ms returns 4 (0x4) +T3F74 26268:805.326 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26268:805.342 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26268:805.788 Data: 00 00 00 00 +T3F74 26268:805.808 - 0.488ms returns 4 (0x4) +T3F74 26268:805.825 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26268:805.841 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26268:806.288 Data: 00 00 00 00 +T3F74 26268:806.308 - 0.490ms returns 4 (0x4) +T062C 26268:818.452 JLINK_IsHalted() +T062C 26268:819.551 - 1.118ms returns FALSE +T062C 26268:919.770 JLINK_HasError() +T062C 26268:919.850 JLINK_IsHalted() +T062C 26268:921.048 - 1.240ms returns FALSE +T062C 26269:021.638 JLINK_HasError() +T062C 26269:021.721 JLINK_IsHalted() +T062C 26269:022.778 - 1.074ms returns FALSE +T062C 26269:123.472 JLINK_HasError() +T062C 26269:123.507 JLINK_IsHalted() +T062C 26269:124.641 - 1.175ms returns FALSE +T062C 26269:225.686 JLINK_HasError() +T062C 26269:225.761 JLINK_IsHalted() +T062C 26269:226.932 - 1.203ms returns FALSE +T062C 26269:327.333 JLINK_HasError() +T062C 26269:327.405 JLINK_HasError() +T062C 26269:327.450 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26269:327.511 Data: 8D 12 74 01 +T062C 26269:327.575 Debug reg: DWT_CYCCNT +T062C 26269:327.628 - 0.202ms returns 1 (0x1) +T3F74 26269:330.122 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26269:330.159 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26269:331.373 Data: 00 00 80 00 +T3F74 26269:331.453 - 1.360ms returns 4 (0x4) +T3F74 26269:331.512 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26269:331.535 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26269:332.679 Data: 00 00 F0 01 +T3F74 26269:332.758 - 1.265ms returns 4 (0x4) +T3F74 26269:336.097 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26269:336.127 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26269:337.355 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26269:337.388 - 1.299ms returns 16 (0x10) +T3F74 26269:337.412 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26269:337.435 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26269:337.849 Data: 1E 00 00 00 +T3F74 26269:337.873 - 0.469ms returns 4 (0x4) +T3F74 26269:337.894 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26269:337.913 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26269:338.484 Data: 00 00 00 00 00 00 00 00 00 00 00 00 07 01 00 00 ... +T3F74 26269:338.505 - 0.618ms returns 20 (0x14) +T3F74 26269:338.522 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26269:338.538 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26269:338.967 Data: 1F 03 00 00 +T3F74 26269:338.988 - 0.472ms returns 4 (0x4) +T3F74 26269:339.005 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26269:339.021 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26269:339.468 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26269:339.488 - 0.490ms returns 12 (0xC) +T3F74 26269:339.506 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26269:339.528 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26269:339.973 Data: 00 00 00 00 +T3F74 26269:339.997 - 0.499ms returns 4 (0x4) +T3F74 26269:340.017 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26269:340.036 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26269:340.474 Data: 00 00 00 00 +T3F74 26269:340.498 - 0.489ms returns 4 (0x4) +T3F74 26269:340.518 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26269:340.545 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26269:340.973 Data: 00 00 00 00 +T3F74 26269:340.993 - 0.481ms returns 4 (0x4) +T062C 26269:352.859 JLINK_IsHalted() +T062C 26269:354.042 - 1.202ms returns FALSE +T062C 26269:454.228 JLINK_HasError() +T062C 26269:454.311 JLINK_IsHalted() +T062C 26269:455.548 - 1.280ms returns FALSE +T062C 26269:556.773 JLINK_HasError() +T062C 26269:556.845 JLINK_IsHalted() +T062C 26269:558.016 - 1.213ms returns FALSE +T062C 26269:658.240 JLINK_HasError() +T062C 26269:658.314 JLINK_IsHalted() +T062C 26269:659.525 - 1.229ms returns FALSE +T062C 26269:759.943 JLINK_HasError() +T062C 26269:759.990 JLINK_IsHalted() +T062C 26269:761.134 - 1.167ms returns FALSE +T062C 26269:861.355 JLINK_HasError() +T062C 26269:861.442 JLINK_HasError() +T062C 26269:861.487 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26269:861.535 Data: 8D 12 74 01 +T062C 26269:861.556 Debug reg: DWT_CYCCNT +T062C 26269:861.574 - 0.094ms returns 1 (0x1) +T3F74 26269:864.260 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26269:864.298 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26269:865.556 Data: 00 00 80 00 +T3F74 26269:865.636 - 1.396ms returns 4 (0x4) +T3F74 26269:865.733 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26269:865.794 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26269:866.969 Data: 00 00 F0 01 +T3F74 26269:867.047 - 1.334ms returns 4 (0x4) +T3F74 26269:870.428 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26269:870.460 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26269:871.681 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26269:871.713 - 1.292ms returns 16 (0x10) +T3F74 26269:871.745 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26269:871.764 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26269:872.147 Data: 1F 00 00 00 +T3F74 26269:872.167 - 0.429ms returns 4 (0x4) +T3F74 26269:872.184 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26269:872.201 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26269:872.649 Data: 00 00 00 00 00 00 00 00 00 00 00 00 29 01 00 00 ... +T3F74 26269:872.669 - 0.491ms returns 20 (0x14) +T3F74 26269:872.686 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26269:872.703 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26269:873.147 Data: 1F 03 00 00 +T3F74 26269:873.167 - 0.488ms returns 4 (0x4) +T3F74 26269:873.184 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26269:873.200 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26269:873.647 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26269:873.667 - 0.489ms returns 12 (0xC) +T3F74 26269:873.684 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26269:873.700 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26269:874.141 Data: 00 00 00 00 +T3F74 26269:874.161 - 0.484ms returns 4 (0x4) +T3F74 26269:874.178 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26269:874.194 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26269:874.660 Data: 00 00 00 00 +T3F74 26269:874.680 - 0.508ms returns 4 (0x4) +T3F74 26269:874.697 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26269:874.713 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26269:875.158 Data: 00 00 00 00 +T3F74 26269:875.178 - 0.487ms returns 4 (0x4) +T062C 26269:894.617 JLINK_IsHalted() +T062C 26269:895.696 - 1.096ms returns FALSE +T062C 26269:996.230 JLINK_HasError() +T062C 26269:996.311 JLINK_IsHalted() +T062C 26269:997.529 - 1.261ms returns FALSE +T062C 26270:097.767 JLINK_HasError() +T062C 26270:097.839 JLINK_IsHalted() +T062C 26270:099.038 - 1.217ms returns FALSE +T062C 26270:199.701 JLINK_HasError() +T062C 26270:199.772 JLINK_IsHalted() +T062C 26270:200.940 - 1.210ms returns FALSE +T062C 26270:301.179 JLINK_HasError() +T062C 26270:301.218 JLINK_IsHalted() +T062C 26270:302.332 - 1.132ms returns FALSE +T062C 26270:402.538 JLINK_HasError() +T062C 26270:402.610 JLINK_HasError() +T062C 26270:402.655 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26270:402.716 Data: 8D 12 74 01 +T062C 26270:402.747 Debug reg: DWT_CYCCNT +T062C 26270:402.766 - 0.118ms returns 1 (0x1) +T3F74 26270:405.127 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26270:405.159 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26270:406.345 Data: 00 00 80 00 +T3F74 26270:406.424 - 1.317ms returns 4 (0x4) +T3F74 26270:406.505 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26270:406.540 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26270:407.674 Data: 00 00 F0 01 +T3F74 26270:407.739 - 1.241ms returns 4 (0x4) +T3F74 26270:410.885 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26270:410.918 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26270:412.078 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26270:412.099 - 1.220ms returns 16 (0x10) +T3F74 26270:412.131 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26270:412.147 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26270:412.578 Data: 1F 00 00 00 +T3F74 26270:412.602 - 0.479ms returns 4 (0x4) +T3F74 26270:412.625 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26270:412.644 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26270:413.202 Data: 00 00 00 00 00 00 00 00 00 00 00 00 5F 01 00 00 ... +T3F74 26270:413.226 - 0.608ms returns 20 (0x14) +T3F74 26270:413.258 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26270:413.277 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26270:413.703 Data: 1F 03 00 00 +T3F74 26270:413.726 - 0.476ms returns 4 (0x4) +T3F74 26270:413.749 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26270:413.768 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26270:414.337 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26270:414.363 - 0.621ms returns 12 (0xC) +T3F74 26270:414.387 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26270:414.408 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26270:414.951 Data: 00 00 00 00 +T3F74 26270:414.975 - 0.595ms returns 4 (0x4) +T3F74 26270:414.997 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26270:415.017 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26270:415.455 Data: 00 00 00 00 +T3F74 26270:415.478 - 0.489ms returns 4 (0x4) +T3F74 26270:415.501 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26270:415.520 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26270:415.953 Data: 00 00 00 00 +T3F74 26270:415.977 - 0.485ms returns 4 (0x4) +T062C 26270:427.465 JLINK_IsHalted() +T062C 26270:428.600 - 1.153ms returns FALSE +T062C 26270:528.760 JLINK_HasError() +T062C 26270:528.841 JLINK_IsHalted() +T062C 26270:529.977 - 1.154ms returns FALSE +T062C 26270:630.671 JLINK_HasError() +T062C 26270:630.702 JLINK_IsHalted() +T062C 26270:631.975 - 1.292ms returns FALSE +T062C 26270:732.254 JLINK_HasError() +T062C 26270:732.325 JLINK_IsHalted() +T062C 26270:733.498 - 1.215ms returns FALSE +T062C 26270:833.860 JLINK_HasError() +T062C 26270:833.907 JLINK_IsHalted() +T062C 26270:835.118 - 1.236ms returns FALSE +T062C 26270:935.319 JLINK_HasError() +T062C 26270:935.405 JLINK_HasError() +T062C 26270:935.450 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26270:935.510 Data: 8D 12 74 01 +T062C 26270:935.530 Debug reg: DWT_CYCCNT +T062C 26270:935.549 - 0.106ms returns 1 (0x1) +T3F74 26270:938.056 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26270:938.090 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26270:939.223 Data: 00 00 80 00 +T3F74 26270:939.290 - 1.241ms returns 4 (0x4) +T3F74 26270:939.325 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26270:939.345 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26270:939.758 Data: 00 00 F0 01 +T3F74 26270:939.783 - 0.465ms returns 4 (0x4) +T3F74 26270:942.942 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26270:942.978 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26270:944.230 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26270:944.286 - 1.352ms returns 16 (0x10) +T3F74 26270:944.310 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26270:944.339 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26270:944.762 Data: 1E 00 00 00 +T3F74 26270:944.785 - 0.483ms returns 4 (0x4) +T3F74 26270:944.806 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26270:944.825 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26270:945.392 Data: 00 00 00 00 00 00 00 00 00 00 00 00 ED 01 00 00 ... +T3F74 26270:945.412 - 0.612ms returns 20 (0x14) +T3F74 26270:945.429 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26270:945.445 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26270:945.874 Data: 1F 03 00 00 +T3F74 26270:945.894 - 0.472ms returns 4 (0x4) +T3F74 26270:945.911 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26270:945.927 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26270:946.396 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26270:946.420 - 0.516ms returns 12 (0xC) +T3F74 26270:946.440 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26270:946.459 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26270:946.887 Data: 00 00 00 00 +T3F74 26270:946.911 - 0.479ms returns 4 (0x4) +T3F74 26270:946.931 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26270:946.950 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26270:947.494 Data: 00 00 00 00 +T3F74 26270:947.518 - 0.595ms returns 4 (0x4) +T3F74 26270:947.538 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26270:947.557 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26270:948.005 Data: 00 00 00 00 +T3F74 26270:948.029 - 0.499ms returns 4 (0x4) +T062C 26270:967.724 JLINK_IsHalted() +T062C 26270:968.823 - 1.116ms returns FALSE +T062C 26271:069.135 JLINK_HasError() +T062C 26271:069.179 JLINK_IsHalted() +T062C 26271:070.303 - 1.166ms returns FALSE +T062C 26271:170.559 JLINK_HasError() +T062C 26271:170.641 JLINK_IsHalted() +T062C 26271:171.822 - 1.199ms returns FALSE +T062C 26271:272.553 JLINK_HasError() +T062C 26271:272.633 JLINK_IsHalted() +T062C 26271:273.808 - 1.193ms returns FALSE +T062C 26271:374.614 JLINK_HasError() +T062C 26271:374.665 JLINK_IsHalted() +T062C 26271:375.791 - 1.145ms returns FALSE +T062C 26271:476.335 JLINK_HasError() +T062C 26271:476.408 JLINK_HasError() +T062C 26271:476.452 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26271:476.516 Data: 8D 12 74 01 +T062C 26271:476.537 Debug reg: DWT_CYCCNT +T062C 26271:476.556 - 0.110ms returns 1 (0x1) +T3F74 26271:479.105 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26271:479.143 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26271:480.288 Data: 00 00 80 00 +T3F74 26271:480.335 - 1.239ms returns 4 (0x4) +T3F74 26271:480.380 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26271:480.403 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26271:480.821 Data: 00 00 F0 01 +T3F74 26271:480.845 - 0.473ms returns 4 (0x4) +T3F74 26271:484.239 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26271:484.270 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26271:485.436 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26271:485.456 - 1.223ms returns 16 (0x10) +T3F74 26271:485.489 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26271:485.505 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26271:485.944 Data: 1E 00 00 00 +T3F74 26271:485.981 - 0.500ms returns 4 (0x4) +T3F74 26271:486.053 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26271:486.081 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26271:486.566 Data: 00 00 00 00 00 00 00 00 00 00 00 00 35 00 00 00 ... +T3F74 26271:486.590 - 0.545ms returns 20 (0x14) +T3F74 26271:486.611 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26271:486.630 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26271:487.057 Data: 1F 03 00 00 +T3F74 26271:487.077 - 0.473ms returns 4 (0x4) +T3F74 26271:487.095 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26271:487.111 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26271:487.558 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26271:487.578 - 0.490ms returns 12 (0xC) +T3F74 26271:487.602 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26271:487.623 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26271:488.052 Data: 00 00 00 00 +T3F74 26271:488.072 - 0.477ms returns 4 (0x4) +T3F74 26271:488.089 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26271:488.105 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26271:488.560 Data: 00 00 00 00 +T3F74 26271:488.583 - 0.502ms returns 4 (0x4) +T3F74 26271:488.604 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26271:488.623 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26271:489.062 Data: 00 00 00 00 +T3F74 26271:489.086 - 0.489ms returns 4 (0x4) +T062C 26271:500.576 JLINK_IsHalted() +T062C 26271:501.697 - 1.133ms returns FALSE +T062C 26271:601.858 JLINK_HasError() +T062C 26271:601.937 JLINK_IsHalted() +T062C 26271:603.150 - 1.255ms returns FALSE +T062C 26271:703.768 JLINK_HasError() +T062C 26271:703.855 JLINK_IsHalted() +T062C 26271:705.064 - 1.227ms returns FALSE +T062C 26271:805.659 JLINK_HasError() +T062C 26271:805.749 JLINK_IsHalted() +T062C 26271:806.994 - 1.263ms returns FALSE +T062C 26271:907.726 JLINK_HasError() +T062C 26271:907.821 JLINK_IsHalted() +T062C 26271:908.912 - 1.110ms returns FALSE +T062C 26272:009.426 JLINK_HasError() +T062C 26272:009.512 JLINK_HasError() +T062C 26272:009.559 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26272:009.590 Data: 8D 12 74 01 +T062C 26272:009.614 Debug reg: DWT_CYCCNT +T062C 26272:009.636 - 0.084ms returns 1 (0x1) +T3F74 26272:012.197 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26272:012.229 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26272:013.362 Data: 00 00 80 00 +T3F74 26272:013.410 - 1.220ms returns 4 (0x4) +T3F74 26272:013.444 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26272:013.464 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26272:013.858 Data: 00 00 F0 01 +T3F74 26272:013.879 - 0.441ms returns 4 (0x4) +T3F74 26272:017.819 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26272:017.852 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26272:019.069 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26272:019.106 - 1.295ms returns 16 (0x10) +T3F74 26272:019.130 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26272:019.153 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26272:019.615 Data: 1E 00 00 00 +T3F74 26272:019.638 - 0.516ms returns 4 (0x4) +T3F74 26272:019.659 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26272:019.678 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26272:020.238 Data: 00 00 00 00 00 00 00 00 00 00 00 00 7F 02 00 00 ... +T3F74 26272:020.262 - 0.610ms returns 20 (0x14) +T3F74 26272:020.282 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26272:020.300 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26272:020.732 Data: 1F 03 00 00 +T3F74 26272:020.753 - 0.477ms returns 4 (0x4) +T3F74 26272:020.769 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26272:020.786 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26272:021.231 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26272:021.251 - 0.488ms returns 12 (0xC) +T3F74 26272:021.268 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26272:021.284 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26272:021.742 Data: 00 00 00 00 +T3F74 26272:021.765 - 0.504ms returns 4 (0x4) +T3F74 26272:021.785 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26272:021.804 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26272:022.242 Data: 00 00 00 00 +T3F74 26272:022.265 - 0.488ms returns 4 (0x4) +T3F74 26272:022.285 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26272:022.304 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26272:022.744 Data: 00 00 00 00 +T3F74 26272:022.767 - 0.490ms returns 4 (0x4) +T062C 26272:035.320 JLINK_IsHalted() +T062C 26272:036.443 - 1.167ms returns FALSE +T062C 26272:137.417 JLINK_HasError() +T062C 26272:137.498 JLINK_IsHalted() +T062C 26272:138.696 - 1.216ms returns FALSE +T062C 26272:239.248 JLINK_HasError() +T062C 26272:239.348 JLINK_IsHalted() +T062C 26272:240.507 - 1.178ms returns FALSE +T062C 26272:341.428 JLINK_HasError() +T062C 26272:341.503 JLINK_IsHalted() +T062C 26272:342.727 - 1.267ms returns FALSE +T062C 26272:443.602 JLINK_HasError() +T062C 26272:443.662 JLINK_IsHalted() +T062C 26272:444.820 - 1.176ms returns FALSE +T062C 26272:545.010 JLINK_HasError() +T062C 26272:545.095 JLINK_HasError() +T062C 26272:545.140 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26272:545.209 Data: 8D 12 74 01 +T062C 26272:545.267 Debug reg: DWT_CYCCNT +T062C 26272:545.313 - 0.180ms returns 1 (0x1) +T3F74 26272:547.613 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26272:547.646 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26272:548.759 Data: 00 00 80 00 +T3F74 26272:548.826 - 1.220ms returns 4 (0x4) +T3F74 26272:548.881 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26272:548.903 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26272:550.110 Data: 00 00 F0 01 +T3F74 26272:550.139 - 1.266ms returns 4 (0x4) +T3F74 26272:553.844 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26272:553.876 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26272:555.077 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26272:555.110 - 1.274ms returns 16 (0x10) +T3F74 26272:555.148 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26272:555.171 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26272:555.677 Data: 1E 00 00 00 +T3F74 26272:555.700 - 0.560ms returns 4 (0x4) +T3F74 26272:555.732 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26272:555.751 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26272:556.356 Data: 00 00 00 00 00 00 00 00 00 00 00 00 C3 01 00 00 ... +T3F74 26272:556.380 - 0.656ms returns 20 (0x14) +T3F74 26272:556.412 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26272:556.431 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26272:556.926 Data: 1F 03 00 00 +T3F74 26272:556.950 - 0.546ms returns 4 (0x4) +T3F74 26272:556.981 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26272:557.000 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26272:557.421 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26272:557.444 - 0.473ms returns 12 (0xC) +T3F74 26272:557.469 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26272:557.488 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26272:557.921 Data: 00 00 00 00 +T3F74 26272:557.946 - 0.485ms returns 4 (0x4) +T3F74 26272:557.977 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26272:557.996 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26272:558.416 Data: 00 00 00 00 +T3F74 26272:558.439 - 0.470ms returns 4 (0x4) +T3F74 26272:558.461 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26272:558.480 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26272:558.941 Data: 00 00 00 00 +T3F74 26272:558.964 - 0.510ms returns 4 (0x4) +T062C 26272:570.732 JLINK_IsHalted() +T062C 26272:571.802 - 1.088ms returns FALSE +T062C 26272:672.001 JLINK_HasError() +T062C 26272:672.081 JLINK_IsHalted() +T062C 26272:673.233 - 1.171ms returns FALSE +T062C 26272:774.358 JLINK_HasError() +T062C 26272:774.431 JLINK_IsHalted() +T062C 26272:775.643 - 1.241ms returns FALSE +T062C 26272:876.364 JLINK_HasError() +T062C 26272:876.438 JLINK_IsHalted() +T062C 26272:877.582 - 1.185ms returns FALSE +T062C 26272:978.509 JLINK_HasError() +T062C 26272:978.576 JLINK_IsHalted() +T062C 26272:979.653 - 1.099ms returns FALSE +T062C 26273:079.966 JLINK_HasError() +T062C 26273:080.054 JLINK_HasError() +T062C 26273:080.098 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26273:080.146 Data: 8D 12 74 01 +T062C 26273:080.167 Debug reg: DWT_CYCCNT +T062C 26273:080.186 - 0.094ms returns 1 (0x1) +T3F74 26273:083.093 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26273:083.137 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26273:084.257 Data: 00 00 80 00 +T3F74 26273:084.289 - 1.204ms returns 4 (0x4) +T3F74 26273:084.331 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26273:084.423 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26273:084.861 Data: 00 00 F0 01 +T3F74 26273:084.905 - 0.583ms returns 4 (0x4) +T3F74 26273:088.569 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26273:088.599 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26273:089.853 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26273:089.951 - 1.390ms returns 16 (0x10) +T3F74 26273:089.975 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26273:089.998 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26273:091.239 Data: 1E 00 00 00 +T3F74 26273:091.318 - 1.362ms returns 4 (0x4) +T3F74 26273:091.367 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26273:091.390 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26273:092.686 Data: 00 00 00 00 00 00 00 00 00 00 00 00 53 02 00 00 ... +T3F74 26273:092.714 - 1.353ms returns 20 (0x14) +T3F74 26273:092.734 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26273:092.753 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26273:093.220 Data: 1F 03 00 00 +T3F74 26273:093.240 - 0.513ms returns 4 (0x4) +T3F74 26273:093.257 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26273:093.274 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26273:093.720 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26273:093.740 - 0.489ms returns 12 (0xC) +T3F74 26273:093.757 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26273:093.773 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26273:094.214 Data: 00 00 00 00 +T3F74 26273:094.234 - 0.484ms returns 4 (0x4) +T3F74 26273:094.251 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26273:094.267 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26273:094.714 Data: 00 00 00 00 +T3F74 26273:094.734 - 0.489ms returns 4 (0x4) +T3F74 26273:094.751 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26273:094.767 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26273:095.216 Data: 00 00 00 00 +T3F74 26273:095.236 - 0.491ms returns 4 (0x4) +T062C 26273:107.355 JLINK_IsHalted() +T062C 26273:108.481 - 1.144ms returns FALSE +T062C 26273:209.190 JLINK_HasError() +T062C 26273:209.268 JLINK_IsHalted() +T062C 26273:210.420 - 1.193ms returns FALSE +T062C 26273:311.212 JLINK_HasError() +T062C 26273:311.249 JLINK_IsHalted() +T062C 26273:312.405 - 1.173ms returns FALSE +T062C 26273:412.607 JLINK_HasError() +T062C 26273:412.691 JLINK_IsHalted() +T062C 26273:413.900 - 1.227ms returns FALSE +T062C 26273:514.589 JLINK_HasError() +T062C 26273:514.620 JLINK_IsHalted() +T062C 26273:515.795 - 1.223ms returns FALSE +T062C 26273:616.038 JLINK_HasError() +T062C 26273:616.114 JLINK_HasError() +T062C 26273:616.159 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26273:616.223 Data: 8D 12 74 01 +T062C 26273:616.244 Debug reg: DWT_CYCCNT +T062C 26273:616.263 - 0.110ms returns 1 (0x1) +T3F74 26273:618.732 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26273:618.765 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26273:619.871 Data: 00 00 80 00 +T3F74 26273:619.958 - 1.234ms returns 4 (0x4) +T3F74 26273:619.997 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26273:620.021 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26273:621.157 Data: 00 00 F0 01 +T3F74 26273:621.186 - 1.197ms returns 4 (0x4) +T3F74 26273:624.332 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26273:624.359 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26273:625.559 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26273:625.591 - 1.267ms returns 16 (0x10) +T3F74 26273:625.614 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26273:625.637 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26273:626.144 Data: 1E 00 00 00 +T3F74 26273:626.165 - 0.557ms returns 4 (0x4) +T3F74 26273:626.182 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26273:626.199 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26273:626.644 Data: 00 00 00 00 00 00 00 00 00 00 00 00 EF 01 00 00 ... +T3F74 26273:626.736 - 0.561ms returns 20 (0x14) +T3F74 26273:626.754 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26273:626.771 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26273:627.144 Data: 1F 03 00 00 +T3F74 26273:627.164 - 0.416ms returns 4 (0x4) +T3F74 26273:627.182 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26273:627.198 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26273:627.650 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26273:627.673 - 0.499ms returns 12 (0xC) +T3F74 26273:627.694 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26273:627.713 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26273:628.265 Data: 00 00 00 00 +T3F74 26273:628.291 - 0.605ms returns 4 (0x4) +T3F74 26273:628.312 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26273:628.333 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26273:628.777 Data: 00 00 00 00 +T3F74 26273:628.803 - 0.498ms returns 4 (0x4) +T3F74 26273:628.824 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26273:628.844 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26273:629.269 Data: 00 00 00 00 +T3F74 26273:629.289 - 0.472ms returns 4 (0x4) +T062C 26273:641.155 JLINK_IsHalted() +T062C 26273:642.298 - 1.160ms returns FALSE +T062C 26273:743.019 JLINK_HasError() +T062C 26273:743.097 JLINK_IsHalted() +T062C 26273:744.349 - 1.293ms returns FALSE +T062C 26273:844.543 JLINK_HasError() +T062C 26273:844.624 JLINK_IsHalted() +T062C 26273:845.875 - 1.293ms returns FALSE +T062C 26273:946.695 JLINK_HasError() +T062C 26273:946.769 JLINK_IsHalted() +T062C 26273:947.980 - 1.230ms returns FALSE +T062C 26274:048.799 JLINK_HasError() +T062C 26274:048.849 JLINK_IsHalted() +T062C 26274:050.052 - 1.220ms returns FALSE +T062C 26274:150.612 JLINK_HasError() +T062C 26274:150.701 JLINK_HasError() +T062C 26274:150.721 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26274:150.750 Data: 8D 12 74 01 +T062C 26274:150.774 Debug reg: DWT_CYCCNT +T062C 26274:150.796 - 0.083ms returns 1 (0x1) +T3F74 26274:153.373 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26274:153.414 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26274:154.503 Data: 00 00 80 00 +T3F74 26274:154.535 - 1.169ms returns 4 (0x4) +T3F74 26274:154.576 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26274:154.599 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26274:155.099 Data: 00 00 F0 01 +T3F74 26274:155.123 - 0.555ms returns 4 (0x4) +T3F74 26274:158.660 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26274:158.691 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26274:159.847 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26274:159.889 - 1.240ms returns 16 (0x10) +T3F74 26274:159.920 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26274:159.947 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26274:160.474 Data: 1F 00 00 00 +T3F74 26274:160.498 - 0.586ms returns 4 (0x4) +T3F74 26274:160.519 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26274:160.538 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26274:161.101 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E5 02 00 00 ... +T3F74 26274:161.127 - 0.616ms returns 20 (0x14) +T3F74 26274:161.148 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26274:161.168 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26274:161.583 Data: 1F 03 00 00 +T3F74 26274:161.607 - 0.467ms returns 4 (0x4) +T3F74 26274:161.628 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26274:161.647 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26274:162.083 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26274:162.107 - 0.486ms returns 12 (0xC) +T3F74 26274:162.127 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26274:162.146 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26274:162.580 Data: 00 00 00 00 +T3F74 26274:162.604 - 0.485ms returns 4 (0x4) +T3F74 26274:162.625 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26274:162.644 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26274:163.205 Data: 00 00 00 00 +T3F74 26274:163.230 - 0.613ms returns 4 (0x4) +T3F74 26274:163.251 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26274:163.270 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26274:163.708 Data: 00 00 00 00 +T3F74 26274:163.732 - 0.489ms returns 4 (0x4) +T062C 26274:184.829 JLINK_IsHalted() +T062C 26274:185.977 - 1.168ms returns FALSE +T062C 26274:286.591 JLINK_HasError() +T062C 26274:286.631 JLINK_IsHalted() +T062C 26274:287.700 - 1.078ms returns FALSE +T062C 26274:387.892 JLINK_HasError() +T062C 26274:387.968 JLINK_IsHalted() +T062C 26274:389.144 - 1.195ms returns FALSE +T062C 26274:489.945 JLINK_HasError() +T062C 26274:490.020 JLINK_IsHalted() +T062C 26274:491.262 - 1.284ms returns FALSE +T062C 26274:591.443 JLINK_HasError() +T062C 26274:591.514 JLINK_IsHalted() +T062C 26274:592.764 - 1.292ms returns FALSE +T062C 26274:693.572 JLINK_HasError() +T062C 26274:693.646 JLINK_HasError() +T062C 26274:693.664 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26274:693.693 Data: 8D 12 74 01 +T062C 26274:693.717 Debug reg: DWT_CYCCNT +T062C 26274:693.738 - 0.082ms returns 1 (0x1) +T3F74 26274:696.091 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26274:696.124 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26274:697.225 Data: 00 00 80 00 +T3F74 26274:697.312 - 1.241ms returns 4 (0x4) +T3F74 26274:697.398 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26274:697.422 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26274:698.590 Data: 00 00 F0 01 +T3F74 26274:698.660 - 1.281ms returns 4 (0x4) +T3F74 26274:702.276 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26274:702.307 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26274:703.541 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26274:703.573 - 1.305ms returns 16 (0x10) +T3F74 26274:703.600 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26274:703.623 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26274:704.005 Data: 1E 00 00 00 +T3F74 26274:704.029 - 0.437ms returns 4 (0x4) +T3F74 26274:704.053 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26274:704.088 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26274:704.632 Data: 00 00 00 00 00 00 00 00 00 00 00 00 BB 02 00 00 ... +T3F74 26274:704.656 - 0.610ms returns 20 (0x14) +T3F74 26274:704.679 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26274:704.698 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26274:705.198 Data: 1F 03 00 00 +T3F74 26274:705.234 - 0.563ms returns 4 (0x4) +T3F74 26274:705.304 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26274:705.327 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26274:705.767 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26274:705.799 - 0.503ms returns 12 (0xC) +T3F74 26274:705.821 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26274:705.842 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26274:706.254 Data: 00 00 00 00 +T3F74 26274:706.274 - 0.460ms returns 4 (0x4) +T3F74 26274:706.292 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26274:706.308 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26274:706.755 Data: 00 00 00 00 +T3F74 26274:706.775 - 0.490ms returns 4 (0x4) +T3F74 26274:706.792 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26274:706.808 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26274:707.253 Data: 00 00 00 00 +T3F74 26274:707.273 - 0.487ms returns 4 (0x4) +T062C 26274:725.873 JLINK_IsHalted() +T062C 26274:727.043 - 1.188ms returns FALSE +T062C 26274:827.206 JLINK_HasError() +T062C 26274:827.288 JLINK_IsHalted() +T062C 26274:828.471 - 1.202ms returns FALSE +T062C 26274:929.169 JLINK_HasError() +T062C 26274:929.199 JLINK_IsHalted() +T062C 26274:930.378 - 1.221ms returns FALSE +T062C 26275:030.576 JLINK_HasError() +T062C 26275:030.647 JLINK_IsHalted() +T062C 26275:031.963 - 1.336ms returns FALSE +T062C 26275:132.304 JLINK_HasError() +T062C 26275:132.348 JLINK_IsHalted() +T062C 26275:133.537 - 1.220ms returns FALSE +T062C 26275:234.443 JLINK_HasError() +T062C 26275:234.531 JLINK_HasError() +T062C 26275:234.576 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26275:234.651 Data: 8D 12 74 01 +T062C 26275:234.675 Debug reg: DWT_CYCCNT +T062C 26275:234.698 - 0.130ms returns 1 (0x1) +T3F74 26275:237.075 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26275:237.110 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26275:238.206 Data: 00 00 80 00 +T3F74 26275:238.233 - 1.165ms returns 4 (0x4) +T3F74 26275:238.267 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26275:238.288 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26275:238.722 Data: 00 00 F0 01 +T3F74 26275:238.746 - 0.487ms returns 4 (0x4) +T3F74 26275:242.090 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26275:242.122 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26275:243.365 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26275:243.393 - 1.309ms returns 16 (0x10) +T3F74 26275:243.413 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26275:243.433 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26275:243.804 Data: 1F 00 00 00 +T3F74 26275:243.825 - 0.418ms returns 4 (0x4) +T3F74 26275:243.842 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26275:243.858 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26275:244.322 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1B 02 00 00 ... +T3F74 26275:244.342 - 0.506ms returns 20 (0x14) +T3F74 26275:244.359 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26275:244.375 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26275:244.813 Data: 1F 03 00 00 +T3F74 26275:244.833 - 0.481ms returns 4 (0x4) +T3F74 26275:244.850 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26275:244.866 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26275:245.312 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26275:245.332 - 0.488ms returns 12 (0xC) +T3F74 26275:245.349 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26275:245.365 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26275:245.803 Data: 00 00 00 00 +T3F74 26275:245.823 - 0.481ms returns 4 (0x4) +T3F74 26275:245.840 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26275:245.856 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26275:246.310 Data: 00 00 00 00 +T3F74 26275:246.330 - 0.496ms returns 4 (0x4) +T3F74 26275:246.347 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26275:246.362 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26275:246.807 Data: 00 00 00 00 +T3F74 26275:246.827 - 0.487ms returns 4 (0x4) +T062C 26275:266.232 JLINK_IsHalted() +T062C 26275:267.314 - 1.092ms returns FALSE +T062C 26275:368.039 JLINK_HasError() +T062C 26275:368.121 JLINK_IsHalted() +T062C 26275:369.298 - 1.226ms returns FALSE +T062C 26275:470.337 JLINK_HasError() +T062C 26275:470.478 JLINK_IsHalted() +T062C 26275:471.665 - 1.236ms returns FALSE +T062C 26275:572.381 JLINK_HasError() +T062C 26275:572.454 JLINK_IsHalted() +T062C 26275:573.641 - 1.236ms returns FALSE +T062C 26275:674.006 JLINK_HasError() +T062C 26275:674.077 JLINK_IsHalted() +T062C 26275:675.214 - 1.178ms returns FALSE +T062C 26275:775.938 JLINK_HasError() +T062C 26275:775.967 JLINK_HasError() +T062C 26275:775.993 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26275:776.022 Data: 8D 12 74 01 +T062C 26275:776.046 Debug reg: DWT_CYCCNT +T062C 26275:776.067 - 0.082ms returns 1 (0x1) +T3F74 26275:778.445 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26275:778.477 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26275:779.544 Data: 00 00 80 00 +T3F74 26275:779.580 - 1.143ms returns 4 (0x4) +T3F74 26275:779.624 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26275:779.647 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26275:780.123 Data: 00 00 F0 01 +T3F74 26275:780.149 - 0.533ms returns 4 (0x4) +T3F74 26275:783.308 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26275:783.336 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26275:784.542 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26275:784.582 - 1.281ms returns 16 (0x10) +T3F74 26275:784.602 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26275:784.622 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26275:785.133 Data: 1E 00 00 00 +T3F74 26275:785.157 - 0.563ms returns 4 (0x4) +T3F74 26275:785.178 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26275:785.198 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26275:785.742 Data: 00 00 00 00 00 00 00 00 00 00 00 00 11 02 00 00 ... +T3F74 26275:785.766 - 0.596ms returns 20 (0x14) +T3F74 26275:785.786 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26275:785.805 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26275:786.239 Data: 1F 03 00 00 +T3F74 26275:786.263 - 0.484ms returns 4 (0x4) +T3F74 26275:786.283 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26275:786.302 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26275:786.743 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26275:786.766 - 0.491ms returns 12 (0xC) +T3F74 26275:786.787 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26275:786.806 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26275:787.236 Data: 00 00 00 00 +T3F74 26275:787.256 - 0.476ms returns 4 (0x4) +T3F74 26275:787.273 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26275:787.289 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26275:787.734 Data: 00 00 00 00 +T3F74 26275:787.754 - 0.488ms returns 4 (0x4) +T3F74 26275:787.772 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26275:787.787 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26275:788.235 Data: 00 00 00 00 +T3F74 26275:788.255 - 0.490ms returns 4 (0x4) +T062C 26275:806.897 JLINK_IsHalted() +T062C 26275:808.043 - 1.188ms returns FALSE +T062C 26275:908.432 JLINK_HasError() +T062C 26275:908.513 JLINK_IsHalted() +T062C 26275:909.689 - 1.218ms returns FALSE +T062C 26276:010.422 JLINK_HasError() +T062C 26276:010.449 JLINK_IsHalted() +T062C 26276:011.606 - 1.199ms returns FALSE +T062C 26276:112.464 JLINK_HasError() +T062C 26276:112.506 JLINK_IsHalted() +T062C 26276:113.688 - 1.200ms returns FALSE +T062C 26276:214.271 JLINK_HasError() +T062C 26276:214.327 JLINK_IsHalted() +T062C 26276:215.493 - 1.185ms returns FALSE +T062C 26276:316.187 JLINK_HasError() +T062C 26276:316.228 JLINK_HasError() +T062C 26276:316.244 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26276:316.270 Data: 8D 12 74 01 +T062C 26276:316.294 Debug reg: DWT_CYCCNT +T062C 26276:316.312 - 0.075ms returns 1 (0x1) +T3F74 26276:318.908 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26276:318.949 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26276:320.110 Data: 00 00 80 00 +T3F74 26276:320.144 - 1.244ms returns 4 (0x4) +T3F74 26276:320.184 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26276:320.208 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26276:320.671 Data: 00 00 F0 01 +T3F74 26276:320.694 - 0.517ms returns 4 (0x4) +T3F74 26276:323.756 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26276:323.787 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26276:324.923 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26276:324.948 - 1.200ms returns 16 (0x10) +T3F74 26276:324.970 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26276:324.990 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26276:325.409 Data: 1E 00 00 00 +T3F74 26276:325.430 - 0.467ms returns 4 (0x4) +T3F74 26276:325.448 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26276:325.464 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26276:325.940 Data: 00 00 00 00 00 00 00 00 00 00 00 00 83 02 00 00 ... +T3F74 26276:325.984 - 0.547ms returns 20 (0x14) +T3F74 26276:326.017 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26276:326.046 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26276:326.551 Data: 1F 03 00 00 +T3F74 26276:326.584 - 0.576ms returns 4 (0x4) +T3F74 26276:326.608 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26276:326.636 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26276:327.164 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26276:327.185 - 0.584ms returns 12 (0xC) +T3F74 26276:327.202 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26276:327.219 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26276:327.658 Data: 00 00 00 00 +T3F74 26276:327.679 - 0.483ms returns 4 (0x4) +T3F74 26276:327.696 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26276:327.712 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26276:328.166 Data: 00 00 00 00 +T3F74 26276:328.186 - 0.496ms returns 4 (0x4) +T3F74 26276:328.203 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26276:328.220 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26276:328.659 Data: 00 00 00 00 +T3F74 26276:328.679 - 0.482ms returns 4 (0x4) +T062C 26276:340.946 JLINK_IsHalted() +T062C 26276:342.051 - 1.119ms returns FALSE +T062C 26276:442.452 JLINK_HasError() +T062C 26276:442.531 JLINK_IsHalted() +T062C 26276:443.687 - 1.176ms returns FALSE +T062C 26276:543.902 JLINK_HasError() +T062C 26276:543.974 JLINK_IsHalted() +T062C 26276:545.181 - 1.226ms returns FALSE +T062C 26276:645.945 JLINK_HasError() +T062C 26276:646.018 JLINK_IsHalted() +T062C 26276:647.199 - 1.199ms returns FALSE +T062C 26276:748.451 JLINK_HasError() +T062C 26276:748.523 JLINK_IsHalted() +T062C 26276:749.660 - 1.149ms returns FALSE +T062C 26276:849.839 JLINK_HasError() +T062C 26276:849.912 JLINK_HasError() +T062C 26276:849.957 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26276:850.024 Data: 8D 12 74 01 +T062C 26276:850.082 Debug reg: DWT_CYCCNT +T062C 26276:850.135 - 0.185ms returns 1 (0x1) +T3F74 26276:852.454 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26276:852.487 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26276:853.681 Data: 00 00 80 00 +T3F74 26276:853.753 - 1.309ms returns 4 (0x4) +T3F74 26276:853.820 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26276:853.850 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26276:855.066 Data: 00 00 F0 01 +T3F74 26276:855.103 - 1.290ms returns 4 (0x4) +T3F74 26276:858.400 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26276:858.428 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26276:859.648 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26276:859.676 - 1.283ms returns 16 (0x10) +T3F74 26276:859.697 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26276:859.716 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26276:860.094 Data: 1E 00 00 00 +T3F74 26276:860.114 - 0.424ms returns 4 (0x4) +T3F74 26276:860.132 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26276:860.148 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26276:860.593 Data: 00 00 00 00 00 00 00 00 00 00 00 00 ED 01 00 00 ... +T3F74 26276:860.613 - 0.488ms returns 20 (0x14) +T3F74 26276:860.630 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26276:860.646 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26276:861.093 Data: 1F 03 00 00 +T3F74 26276:861.113 - 0.489ms returns 4 (0x4) +T3F74 26276:861.130 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26276:861.146 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26276:861.593 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26276:861.613 - 0.490ms returns 12 (0xC) +T3F74 26276:861.630 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26276:861.646 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26276:862.093 Data: 00 00 00 00 +T3F74 26276:862.113 - 0.490ms returns 4 (0x4) +T3F74 26276:862.130 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26276:862.146 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26276:862.592 Data: 00 00 00 00 +T3F74 26276:862.612 - 0.488ms returns 4 (0x4) +T3F74 26276:862.629 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26276:862.645 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26276:863.088 Data: 00 00 00 00 +T3F74 26276:863.108 - 0.486ms returns 4 (0x4) +T062C 26276:875.248 JLINK_IsHalted() +T062C 26276:876.443 - 1.214ms returns FALSE +T062C 26276:977.202 JLINK_HasError() +T062C 26276:977.276 JLINK_IsHalted() +T062C 26276:978.464 - 1.206ms returns FALSE +T062C 26277:079.244 JLINK_HasError() +T062C 26277:079.318 JLINK_IsHalted() +T062C 26277:080.440 - 1.140ms returns FALSE +T062C 26277:181.501 JLINK_HasError() +T062C 26277:181.572 JLINK_IsHalted() +T062C 26277:182.764 - 1.234ms returns FALSE +T062C 26277:283.648 JLINK_HasError() +T062C 26277:283.689 JLINK_IsHalted() +T062C 26277:284.782 - 1.112ms returns FALSE +T062C 26277:385.095 JLINK_HasError() +T062C 26277:385.202 JLINK_HasError() +T062C 26277:385.268 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26277:385.300 Data: 8D 12 74 01 +T062C 26277:385.325 Debug reg: DWT_CYCCNT +T062C 26277:385.348 - 0.088ms returns 1 (0x1) +T3F74 26277:388.019 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26277:388.053 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26277:389.272 Data: 00 00 80 00 +T3F74 26277:389.307 - 1.296ms returns 4 (0x4) +T3F74 26277:389.347 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26277:389.369 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26277:389.790 Data: 00 00 F0 01 +T3F74 26277:389.813 - 0.475ms returns 4 (0x4) +T3F74 26277:393.008 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26277:393.039 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26277:394.363 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26277:394.391 - 1.390ms returns 16 (0x10) +T3F74 26277:394.411 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26277:394.431 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26277:394.897 Data: 1E 00 00 00 +T3F74 26277:394.918 - 0.513ms returns 4 (0x4) +T3F74 26277:394.935 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26277:394.952 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26277:395.398 Data: 00 00 00 00 00 00 00 00 00 00 00 00 6D 01 00 00 ... +T3F74 26277:395.418 - 0.489ms returns 20 (0x14) +T3F74 26277:395.435 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26277:395.452 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26277:395.897 Data: 1F 03 00 00 +T3F74 26277:395.917 - 0.488ms returns 4 (0x4) +T3F74 26277:395.934 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26277:395.950 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26277:396.397 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26277:396.417 - 0.489ms returns 12 (0xC) +T3F74 26277:396.434 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26277:396.450 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26277:396.896 Data: 00 00 00 00 +T3F74 26277:396.916 - 0.488ms returns 4 (0x4) +T3F74 26277:396.933 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26277:396.949 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26277:397.397 Data: 00 00 00 00 +T3F74 26277:397.416 - 0.490ms returns 4 (0x4) +T3F74 26277:397.433 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26277:397.449 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26277:397.896 Data: 00 00 00 00 +T3F74 26277:397.916 - 0.489ms returns 4 (0x4) +T062C 26277:410.110 JLINK_IsHalted() +T062C 26277:411.158 - 1.067ms returns FALSE +T062C 26277:512.206 JLINK_HasError() +T062C 26277:512.284 JLINK_IsHalted() +T062C 26277:513.472 - 1.229ms returns FALSE +T062C 26277:613.725 JLINK_HasError() +T062C 26277:613.804 JLINK_IsHalted() +T062C 26277:614.990 - 1.234ms returns FALSE +T062C 26277:715.548 JLINK_HasError() +T062C 26277:715.634 JLINK_IsHalted() +T062C 26277:716.744 - 1.134ms returns FALSE +T062C 26277:817.429 JLINK_HasError() +T062C 26277:817.459 JLINK_IsHalted() +T062C 26277:818.573 - 1.133ms returns FALSE +T062C 26277:919.355 JLINK_HasError() +T062C 26277:919.388 JLINK_HasError() +T062C 26277:919.406 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26277:919.436 Data: 8D 12 74 01 +T062C 26277:919.469 Debug reg: DWT_CYCCNT +T062C 26277:919.492 - 0.093ms returns 1 (0x1) +T3F74 26277:921.956 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26277:922.002 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26277:923.171 Data: 00 00 80 00 +T3F74 26277:923.252 - 1.329ms returns 4 (0x4) +T3F74 26277:923.327 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26277:923.350 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26277:924.457 Data: 00 00 F0 01 +T3F74 26277:924.486 - 1.165ms returns 4 (0x4) +T3F74 26277:927.505 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26277:927.544 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26277:928.733 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26277:928.767 - 1.270ms returns 16 (0x10) +T3F74 26277:928.790 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26277:928.813 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26277:929.200 Data: 1E 00 00 00 +T3F74 26277:929.221 - 0.437ms returns 4 (0x4) +T3F74 26277:929.238 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26277:929.255 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26277:929.702 Data: 00 00 00 00 00 00 00 00 00 00 00 00 15 01 00 00 ... +T3F74 26277:929.722 - 0.490ms returns 20 (0x14) +T3F74 26277:929.739 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26277:929.755 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26277:930.200 Data: 1F 03 00 00 +T3F74 26277:930.220 - 0.487ms returns 4 (0x4) +T3F74 26277:930.237 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26277:930.254 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26277:930.701 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26277:930.721 - 0.490ms returns 12 (0xC) +T3F74 26277:930.738 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26277:930.753 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26277:931.200 Data: 00 00 00 00 +T3F74 26277:931.220 - 0.489ms returns 4 (0x4) +T3F74 26277:931.237 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26277:931.253 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26277:931.696 Data: 00 00 00 00 +T3F74 26277:931.716 - 0.485ms returns 4 (0x4) +T3F74 26277:931.733 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26277:931.749 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26277:932.216 Data: 00 00 00 00 +T3F74 26277:932.236 - 0.510ms returns 4 (0x4) +T062C 26277:944.133 JLINK_IsHalted() +T062C 26277:945.207 - 1.092ms returns FALSE +T062C 26278:045.531 JLINK_HasError() +T062C 26278:045.574 JLINK_IsHalted() +T062C 26278:046.772 - 1.218ms returns FALSE +T062C 26278:147.554 JLINK_HasError() +T062C 26278:147.627 JLINK_IsHalted() +T062C 26278:148.791 - 1.183ms returns FALSE +T062C 26278:249.440 JLINK_HasError() +T062C 26278:249.512 JLINK_IsHalted() +T062C 26278:250.762 - 1.299ms returns FALSE +T062C 26278:351.881 JLINK_HasError() +T062C 26278:351.923 JLINK_IsHalted() +T062C 26278:353.064 - 1.160ms returns FALSE +T062C 26278:453.884 JLINK_HasError() +T062C 26278:453.968 JLINK_HasError() +T062C 26278:454.013 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26278:454.078 Data: 8D 12 74 01 +T062C 26278:454.098 Debug reg: DWT_CYCCNT +T062C 26278:454.117 - 0.110ms returns 1 (0x1) +T3F74 26278:456.696 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26278:456.729 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26278:457.864 Data: 00 00 80 00 +T3F74 26278:457.898 - 1.210ms returns 4 (0x4) +T3F74 26278:457.938 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26278:457.961 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26278:458.384 Data: 00 00 F0 01 +T3F74 26278:458.405 - 0.473ms returns 4 (0x4) +T3F74 26278:461.376 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26278:461.404 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26278:462.684 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26278:462.713 - 1.343ms returns 16 (0x10) +T3F74 26278:462.733 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26278:462.753 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26278:463.131 Data: 1F 00 00 00 +T3F74 26278:463.151 - 0.425ms returns 4 (0x4) +T3F74 26278:463.175 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26278:463.195 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26278:463.631 Data: 00 00 00 00 00 00 00 00 00 00 00 00 35 01 00 00 ... +T3F74 26278:463.651 - 0.482ms returns 20 (0x14) +T3F74 26278:463.668 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26278:463.684 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26278:464.157 Data: 1F 03 00 00 +T3F74 26278:464.177 - 0.516ms returns 4 (0x4) +T3F74 26278:464.194 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26278:464.211 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26278:464.630 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26278:464.649 - 0.461ms returns 12 (0xC) +T3F74 26278:464.666 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26278:464.683 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26278:465.126 Data: 00 00 00 00 +T3F74 26278:465.146 - 0.486ms returns 4 (0x4) +T3F74 26278:465.163 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26278:465.179 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26278:465.630 Data: 00 00 00 00 +T3F74 26278:465.650 - 0.493ms returns 4 (0x4) +T3F74 26278:465.667 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26278:465.683 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26278:466.125 Data: 00 00 00 00 +T3F74 26278:466.145 - 0.485ms returns 4 (0x4) +T062C 26278:485.851 JLINK_IsHalted() +T062C 26278:486.890 - 1.057ms returns FALSE +T062C 26278:587.719 JLINK_HasError() +T062C 26278:587.757 JLINK_IsHalted() +T062C 26278:589.008 - 1.293ms returns FALSE +T062C 26278:689.726 JLINK_HasError() +T062C 26278:689.759 JLINK_IsHalted() +T062C 26278:690.998 - 1.281ms returns FALSE +T062C 26278:791.574 JLINK_HasError() +T062C 26278:791.605 JLINK_IsHalted() +T062C 26278:792.672 - 1.108ms returns FALSE +T062C 26278:892.905 JLINK_HasError() +T062C 26278:892.980 JLINK_IsHalted() +T062C 26278:894.233 - 1.295ms returns FALSE +T062C 26278:994.496 JLINK_HasError() +T062C 26278:994.571 JLINK_HasError() +T062C 26278:994.615 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26278:994.672 Data: 8D 12 74 01 +T062C 26278:994.693 Debug reg: DWT_CYCCNT +T062C 26278:994.711 - 0.103ms returns 1 (0x1) +T3F74 26278:997.162 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26278:997.194 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26278:998.415 Data: 00 00 80 00 +T3F74 26278:998.475 - 1.319ms returns 4 (0x4) +T3F74 26278:998.509 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26278:998.529 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26278:998.930 Data: 00 00 F0 01 +T3F74 26278:998.951 - 0.448ms returns 4 (0x4) +T3F74 26279:002.136 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26279:002.166 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26279:003.343 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26279:003.376 - 1.248ms returns 16 (0x10) +T3F74 26279:003.400 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26279:003.423 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26279:003.934 Data: 1E 00 00 00 +T3F74 26279:003.954 - 0.561ms returns 4 (0x4) +T3F74 26279:003.972 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26279:003.988 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26279:004.433 Data: 00 00 00 00 00 00 00 00 00 00 00 00 F1 00 00 00 ... +T3F74 26279:004.453 - 0.488ms returns 20 (0x14) +T3F74 26279:004.470 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26279:004.486 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26279:004.940 Data: 1F 03 00 00 +T3F74 26279:004.963 - 0.501ms returns 4 (0x4) +T3F74 26279:004.983 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26279:005.002 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26279:005.439 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26279:005.462 - 0.486ms returns 12 (0xC) +T3F74 26279:005.482 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26279:005.505 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26279:005.934 Data: 00 00 00 00 +T3F74 26279:005.958 - 0.484ms returns 4 (0x4) +T3F74 26279:005.978 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26279:005.997 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26279:006.434 Data: 00 00 00 00 +T3F74 26279:006.454 - 0.482ms returns 4 (0x4) +T3F74 26279:006.471 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26279:006.487 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26279:006.929 Data: 00 00 00 00 +T3F74 26279:006.949 - 0.484ms returns 4 (0x4) +T062C 26279:026.328 JLINK_IsHalted() +T062C 26279:027.480 - 1.171ms returns FALSE +T062C 26279:128.079 JLINK_HasError() +T062C 26279:128.159 JLINK_IsHalted() +T062C 26279:129.385 - 1.270ms returns FALSE +T062C 26279:229.982 JLINK_HasError() +T062C 26279:230.055 JLINK_IsHalted() +T062C 26279:231.163 - 1.116ms returns FALSE +T062C 26279:331.579 JLINK_HasError() +T062C 26279:331.650 JLINK_IsHalted() +T062C 26279:332.797 - 1.155ms returns FALSE +T062C 26279:432.933 JLINK_HasError() +T062C 26279:432.978 JLINK_IsHalted() +T062C 26279:434.037 - 1.080ms returns FALSE +T062C 26279:534.822 JLINK_HasError() +T062C 26279:534.910 JLINK_HasError() +T062C 26279:534.945 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26279:534.977 Data: 8D 12 74 01 +T062C 26279:535.001 Debug reg: DWT_CYCCNT +T062C 26279:535.023 - 0.085ms returns 1 (0x1) +T3F74 26279:537.507 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26279:537.540 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26279:538.792 Data: 00 00 80 00 +T3F74 26279:538.827 - 1.328ms returns 4 (0x4) +T3F74 26279:538.866 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26279:538.889 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26279:539.996 Data: 00 00 F0 01 +T3F74 26279:540.023 - 1.164ms returns 4 (0x4) +T3F74 26279:543.455 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26279:543.484 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26279:544.614 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26279:544.635 - 1.186ms returns 16 (0x10) +T3F74 26279:544.653 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26279:544.670 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26279:545.117 Data: 1F 00 00 00 +T3F74 26279:545.137 - 0.490ms returns 4 (0x4) +T3F74 26279:545.169 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26279:545.185 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26279:545.745 Data: 00 00 00 00 00 00 00 00 00 00 00 00 91 01 00 00 ... +T3F74 26279:545.769 - 0.607ms returns 20 (0x14) +T3F74 26279:545.801 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26279:545.820 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26279:546.242 Data: 1F 03 00 00 +T3F74 26279:546.265 - 0.476ms returns 4 (0x4) +T3F74 26279:546.292 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26279:546.311 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26279:546.745 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26279:546.771 - 0.486ms returns 12 (0xC) +T3F74 26279:546.801 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26279:546.820 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26279:547.242 Data: 00 00 00 00 +T3F74 26279:547.265 - 0.471ms returns 4 (0x4) +T3F74 26279:547.288 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26279:547.307 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26279:547.744 Data: 00 00 00 00 +T3F74 26279:547.767 - 0.487ms returns 4 (0x4) +T3F74 26279:547.790 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26279:547.810 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26279:548.241 Data: 00 00 00 00 +T3F74 26279:548.265 - 0.482ms returns 4 (0x4) +T062C 26279:567.384 JLINK_IsHalted() +T062C 26279:568.498 - 1.132ms returns FALSE +T062C 26279:669.438 JLINK_HasError() +T062C 26279:669.522 JLINK_IsHalted() +T062C 26279:670.698 - 1.195ms returns FALSE +T062C 26279:771.228 JLINK_HasError() +T062C 26279:771.302 JLINK_IsHalted() +T062C 26279:772.477 - 1.200ms returns FALSE +T062C 26279:872.685 JLINK_HasError() +T062C 26279:872.782 JLINK_IsHalted() +T062C 26279:873.940 - 1.206ms returns FALSE +T062C 26279:974.458 JLINK_HasError() +T062C 26279:974.490 JLINK_IsHalted() +T062C 26279:975.698 - 1.249ms returns FALSE +T062C 26280:076.436 JLINK_HasError() +T062C 26280:076.463 JLINK_HasError() +T062C 26280:076.478 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26280:076.504 Data: 8D 12 74 01 +T062C 26280:076.524 Debug reg: DWT_CYCCNT +T062C 26280:076.543 - 0.071ms returns 1 (0x1) +T3F74 26280:079.018 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26280:079.050 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26280:080.197 Data: 00 00 80 00 +T3F74 26280:080.233 - 1.222ms returns 4 (0x4) +T3F74 26280:080.276 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26280:080.299 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26280:080.793 Data: 00 00 F0 01 +T3F74 26280:080.817 - 0.549ms returns 4 (0x4) +T3F74 26280:084.168 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26280:084.195 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26280:085.470 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26280:085.498 - 1.337ms returns 16 (0x10) +T3F74 26280:085.518 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26280:085.538 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26280:085.915 Data: 1F 00 00 00 +T3F74 26280:085.935 - 0.424ms returns 4 (0x4) +T3F74 26280:085.953 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26280:085.969 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26280:086.415 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E7 02 00 00 ... +T3F74 26280:086.435 - 0.488ms returns 20 (0x14) +T3F74 26280:086.452 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26280:086.468 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26280:086.914 Data: 1F 03 00 00 +T3F74 26280:086.933 - 0.488ms returns 4 (0x4) +T3F74 26280:086.950 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26280:086.967 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26280:087.414 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26280:087.433 - 0.489ms returns 12 (0xC) +T3F74 26280:087.451 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26280:087.467 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26280:087.914 Data: 00 00 00 00 +T3F74 26280:087.934 - 0.490ms returns 4 (0x4) +T3F74 26280:087.951 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26280:087.967 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26280:088.439 Data: 00 00 00 00 +T3F74 26280:088.459 - 0.514ms returns 4 (0x4) +T3F74 26280:088.476 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26280:088.492 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26280:088.942 Data: 00 00 00 00 +T3F74 26280:088.966 - 0.497ms returns 4 (0x4) +T062C 26280:100.830 JLINK_IsHalted() +T062C 26280:101.964 - 1.176ms returns FALSE +T062C 26280:202.219 JLINK_HasError() +T062C 26280:202.304 JLINK_IsHalted() +T062C 26280:203.484 - 1.222ms returns FALSE +T062C 26280:303.781 JLINK_HasError() +T062C 26280:303.855 JLINK_IsHalted() +T062C 26280:305.013 - 1.206ms returns FALSE +T062C 26280:406.144 JLINK_HasError() +T062C 26280:406.219 JLINK_IsHalted() +T062C 26280:407.475 - 1.274ms returns FALSE +T062C 26280:507.587 JLINK_HasError() +T062C 26280:507.628 JLINK_IsHalted() +T062C 26280:508.797 - 1.192ms returns FALSE +T062C 26280:609.678 JLINK_HasError() +T062C 26280:609.767 JLINK_HasError() +T062C 26280:609.814 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26280:609.843 Data: 8D 12 74 01 +T062C 26280:609.867 Debug reg: DWT_CYCCNT +T062C 26280:609.889 - 0.083ms returns 1 (0x1) +T3F74 26280:612.455 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26280:612.489 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26280:613.641 Data: 00 00 80 00 +T3F74 26280:613.678 - 1.230ms returns 4 (0x4) +T3F74 26280:613.719 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26280:613.743 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26280:614.222 Data: 00 00 F0 01 +T3F74 26280:614.257 - 0.546ms returns 4 (0x4) +T3F74 26280:617.881 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26280:617.912 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26280:619.113 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26280:619.146 - 1.273ms returns 16 (0x10) +T3F74 26280:619.170 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26280:619.193 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26280:619.724 Data: 1F 00 00 00 +T3F74 26280:619.748 - 0.586ms returns 4 (0x4) +T3F74 26280:619.769 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26280:619.788 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26280:620.343 Data: 00 00 00 00 00 00 00 00 00 00 00 00 BF 01 00 00 ... +T3F74 26280:620.364 - 0.601ms returns 20 (0x14) +T3F74 26280:620.381 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26280:620.397 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26280:620.843 Data: 1F 03 00 00 +T3F74 26280:620.863 - 0.489ms returns 4 (0x4) +T3F74 26280:620.880 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26280:620.896 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26280:621.343 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26280:621.363 - 0.489ms returns 12 (0xC) +T3F74 26280:621.380 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26280:621.396 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26280:621.842 Data: 00 00 00 00 +T3F74 26280:621.863 - 0.489ms returns 4 (0x4) +T3F74 26280:621.880 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26280:621.896 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26280:622.340 Data: 00 00 00 00 +T3F74 26280:622.360 - 0.486ms returns 4 (0x4) +T3F74 26280:622.376 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26280:622.392 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26280:622.847 Data: 00 00 00 00 +T3F74 26280:622.871 - 0.502ms returns 4 (0x4) +T062C 26280:635.591 JLINK_IsHalted() +T062C 26280:636.729 - 1.156ms returns FALSE +T062C 26280:736.934 JLINK_HasError() +T062C 26280:737.015 JLINK_IsHalted() +T062C 26280:738.153 - 1.179ms returns FALSE +T062C 26280:838.978 JLINK_HasError() +T062C 26280:839.053 JLINK_IsHalted() +T062C 26280:840.089 - 1.047ms returns FALSE +T062C 26280:940.652 JLINK_HasError() +T062C 26280:940.733 JLINK_IsHalted() +T062C 26280:941.930 - 1.246ms returns FALSE +T062C 26281:042.184 JLINK_HasError() +T062C 26281:042.256 JLINK_IsHalted() +T062C 26281:043.537 - 1.329ms returns FALSE +T062C 26281:143.856 JLINK_HasError() +T062C 26281:143.916 JLINK_HasError() +T062C 26281:143.943 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26281:143.973 Data: 8D 12 74 01 +T062C 26281:144.006 Debug reg: DWT_CYCCNT +T062C 26281:144.029 - 0.093ms returns 1 (0x1) +T3F74 26281:146.393 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26281:146.424 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26281:147.614 Data: 00 00 80 00 +T3F74 26281:147.681 - 1.295ms returns 4 (0x4) +T3F74 26281:147.716 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26281:147.736 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26281:148.149 Data: 00 00 F0 01 +T3F74 26281:148.169 - 0.460ms returns 4 (0x4) +T3F74 26281:151.337 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26281:151.367 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26281:152.582 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26281:152.604 - 1.274ms returns 16 (0x10) +T3F74 26281:152.623 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26281:152.640 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26281:153.023 Data: 1E 00 00 00 +T3F74 26281:153.043 - 0.426ms returns 4 (0x4) +T3F74 26281:153.060 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26281:153.076 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26281:153.523 Data: 00 00 00 00 00 00 00 00 00 00 00 00 09 02 00 00 ... +T3F74 26281:153.543 - 0.490ms returns 20 (0x14) +T3F74 26281:153.560 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26281:153.583 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26281:154.018 Data: 1F 03 00 00 +T3F74 26281:154.038 - 0.484ms returns 4 (0x4) +T3F74 26281:154.055 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26281:154.072 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26281:154.518 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26281:154.538 - 0.489ms returns 12 (0xC) +T3F74 26281:154.555 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26281:154.571 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26281:155.026 Data: 00 00 00 00 +T3F74 26281:155.049 - 0.503ms returns 4 (0x4) +T3F74 26281:155.071 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26281:155.090 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26281:155.531 Data: 00 00 00 00 +T3F74 26281:155.554 - 0.491ms returns 4 (0x4) +T3F74 26281:155.574 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26281:155.593 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26281:156.027 Data: 00 00 00 00 +T3F74 26281:156.050 - 0.483ms returns 4 (0x4) +T062C 26281:175.881 JLINK_IsHalted() +T062C 26281:176.931 - 1.066ms returns FALSE +T062C 26281:277.695 JLINK_HasError() +T062C 26281:277.781 JLINK_IsHalted() +T062C 26281:278.902 - 1.139ms returns FALSE +T062C 26281:379.106 JLINK_HasError() +T062C 26281:379.181 JLINK_IsHalted() +T062C 26281:380.328 - 1.195ms returns FALSE +T062C 26281:481.130 JLINK_HasError() +T062C 26281:481.205 JLINK_IsHalted() +T062C 26281:482.344 - 1.157ms returns FALSE +T062C 26281:583.362 JLINK_HasError() +T062C 26281:583.406 JLINK_IsHalted() +T062C 26281:584.511 - 1.127ms returns FALSE +T062C 26281:684.754 JLINK_HasError() +T062C 26281:684.841 JLINK_HasError() +T062C 26281:684.882 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26281:684.908 Data: 8D 12 74 01 +T062C 26281:684.928 Debug reg: DWT_CYCCNT +T062C 26281:684.947 - 0.072ms returns 1 (0x1) +T3F74 26281:687.672 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26281:687.709 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26281:688.938 Data: 00 00 80 00 +T3F74 26281:688.995 - 1.330ms returns 4 (0x4) +T3F74 26281:689.029 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26281:689.049 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26281:689.447 Data: 00 00 F0 01 +T3F74 26281:689.468 - 0.445ms returns 4 (0x4) +T3F74 26281:692.669 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26281:692.696 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26281:693.881 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26281:693.909 - 1.247ms returns 16 (0x10) +T3F74 26281:693.929 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26281:693.949 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26281:694.326 Data: 1E 00 00 00 +T3F74 26281:694.347 - 0.424ms returns 4 (0x4) +T3F74 26281:694.364 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26281:694.380 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26281:694.821 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1B 02 00 00 ... +T3F74 26281:694.841 - 0.484ms returns 20 (0x14) +T3F74 26281:694.858 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26281:694.874 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26281:695.321 Data: 1F 03 00 00 +T3F74 26281:695.341 - 0.489ms returns 4 (0x4) +T3F74 26281:695.358 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26281:695.374 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26281:695.832 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26281:695.856 - 0.505ms returns 12 (0xC) +T3F74 26281:695.876 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26281:695.895 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26281:696.332 Data: 00 00 00 00 +T3F74 26281:696.355 - 0.487ms returns 4 (0x4) +T3F74 26281:696.375 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26281:696.394 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26281:696.831 Data: 00 00 00 00 +T3F74 26281:696.854 - 0.487ms returns 4 (0x4) +T3F74 26281:696.874 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26281:696.899 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26281:697.326 Data: 00 00 00 00 +T3F74 26281:697.346 - 0.478ms returns 4 (0x4) +T062C 26281:709.487 JLINK_IsHalted() +T062C 26281:710.587 - 1.118ms returns FALSE +T062C 26281:810.830 JLINK_HasError() +T062C 26281:810.915 JLINK_IsHalted() +T062C 26281:812.274 - 1.377ms returns FALSE +T062C 26281:913.023 JLINK_HasError() +T062C 26281:913.097 JLINK_IsHalted() +T062C 26281:914.235 - 1.155ms returns FALSE +T062C 26282:014.546 JLINK_HasError() +T062C 26282:014.617 JLINK_IsHalted() +T062C 26282:015.893 - 1.296ms returns FALSE +T062C 26282:116.087 JLINK_HasError() +T062C 26282:116.160 JLINK_IsHalted() +T062C 26282:117.322 - 1.180ms returns FALSE +T062C 26282:218.050 JLINK_HasError() +T062C 26282:218.150 JLINK_HasError() +T062C 26282:218.216 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26282:218.306 Data: 8D 12 74 01 +T062C 26282:218.340 Debug reg: DWT_CYCCNT +T062C 26282:218.371 - 0.166ms returns 1 (0x1) +T3F74 26282:221.288 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26282:221.341 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26282:222.468 Data: 00 00 80 00 +T3F74 26282:222.501 - 1.222ms returns 4 (0x4) +T3F74 26282:222.549 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26282:222.576 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26282:223.015 Data: 00 00 F0 01 +T3F74 26282:223.039 - 0.497ms returns 4 (0x4) +T3F74 26282:226.613 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26282:226.639 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26282:227.980 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26282:228.014 - 1.409ms returns 16 (0x10) +T3F74 26282:228.038 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26282:228.061 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26282:228.506 Data: 1F 00 00 00 +T3F74 26282:228.526 - 0.494ms returns 4 (0x4) +T3F74 26282:228.543 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26282:228.560 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26282:229.007 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D7 01 00 00 ... +T3F74 26282:229.027 - 0.490ms returns 20 (0x14) +T3F74 26282:229.044 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26282:229.060 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26282:229.500 Data: 1F 03 00 00 +T3F74 26282:229.520 - 0.482ms returns 4 (0x4) +T3F74 26282:229.537 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26282:229.554 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26282:230.020 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26282:230.044 - 0.514ms returns 12 (0xC) +T3F74 26282:230.064 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26282:230.082 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26282:230.512 Data: 00 00 00 00 +T3F74 26282:230.536 - 0.480ms returns 4 (0x4) +T3F74 26282:230.556 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26282:230.574 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26282:231.010 Data: 00 00 00 00 +T3F74 26282:231.033 - 0.485ms returns 4 (0x4) +T3F74 26282:231.053 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26282:231.072 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26282:231.504 Data: 00 00 00 00 +T3F74 26282:231.524 - 0.477ms returns 4 (0x4) +T062C 26282:250.254 JLINK_IsHalted() +T062C 26282:251.390 - 1.148ms returns FALSE +T062C 26282:352.246 JLINK_HasError() +T062C 26282:352.336 JLINK_IsHalted() +T062C 26282:353.597 - 1.304ms returns FALSE +T062C 26282:454.105 JLINK_HasError() +T062C 26282:454.143 JLINK_IsHalted() +T062C 26282:455.234 - 1.112ms returns FALSE +T062C 26282:556.185 JLINK_HasError() +T062C 26282:556.274 JLINK_IsHalted() +T062C 26282:557.468 - 1.242ms returns FALSE +T062C 26282:657.689 JLINK_HasError() +T062C 26282:657.732 JLINK_IsHalted() +T062C 26282:658.917 - 1.210ms returns FALSE +T062C 26282:759.136 JLINK_HasError() +T062C 26282:759.222 JLINK_HasError() +T062C 26282:759.267 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26282:759.321 Data: 8D 12 74 01 +T062C 26282:759.345 Debug reg: DWT_CYCCNT +T062C 26282:759.363 - 0.103ms returns 1 (0x1) +T3F74 26282:761.897 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26282:761.935 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26282:763.167 Data: 00 00 80 00 +T3F74 26282:763.255 - 1.377ms returns 4 (0x4) +T3F74 26282:763.339 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26282:763.362 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26282:764.484 Data: 00 00 F0 01 +T3F74 26282:764.518 - 1.186ms returns 4 (0x4) +T3F74 26282:767.635 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26282:767.663 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26282:768.828 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26282:768.853 - 1.225ms returns 16 (0x10) +T3F74 26282:768.874 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26282:768.894 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26282:769.308 Data: 1F 00 00 00 +T3F74 26282:769.328 - 0.460ms returns 4 (0x4) +T3F74 26282:769.346 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26282:769.362 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26282:769.808 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B3 00 00 00 ... +T3F74 26282:769.828 - 0.489ms returns 20 (0x14) +T3F74 26282:769.846 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26282:769.862 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26282:770.304 Data: 1F 03 00 00 +T3F74 26282:770.324 - 0.485ms returns 4 (0x4) +T3F74 26282:770.341 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26282:770.357 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26282:770.831 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26282:770.851 - 0.516ms returns 12 (0xC) +T3F74 26282:770.868 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26282:770.885 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26282:771.311 Data: 00 00 00 00 +T3F74 26282:771.334 - 0.474ms returns 4 (0x4) +T3F74 26282:771.356 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26282:771.375 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26282:771.809 Data: 00 00 00 00 +T3F74 26282:771.833 - 0.485ms returns 4 (0x4) +T3F74 26282:771.853 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26282:771.872 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26282:772.321 Data: 00 00 00 00 +T3F74 26282:772.345 - 0.499ms returns 4 (0x4) +T062C 26282:784.958 JLINK_IsHalted() +T062C 26282:786.097 - 1.158ms returns FALSE +T062C 26282:886.295 JLINK_HasError() +T062C 26282:886.378 JLINK_IsHalted() +T062C 26282:887.577 - 1.217ms returns FALSE +T062C 26282:987.761 JLINK_HasError() +T062C 26282:987.841 JLINK_IsHalted() +T062C 26282:988.992 - 1.169ms returns FALSE +T062C 26283:089.552 JLINK_HasError() +T062C 26283:089.706 JLINK_IsHalted() +T062C 26283:090.814 - 1.132ms returns FALSE +T062C 26283:191.511 JLINK_HasError() +T062C 26283:191.537 JLINK_IsHalted() +T062C 26283:192.714 - 1.218ms returns FALSE +T062C 26283:293.505 JLINK_HasError() +T062C 26283:293.577 JLINK_HasError() +T062C 26283:293.621 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26283:293.681 Data: 8D 12 74 01 +T062C 26283:293.738 Debug reg: DWT_CYCCNT +T062C 26283:293.792 - 0.190ms returns 1 (0x1) +T3F74 26283:296.251 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26283:296.284 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26283:297.382 Data: 00 00 80 00 +T3F74 26283:297.419 - 1.175ms returns 4 (0x4) +T3F74 26283:297.466 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26283:297.490 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26283:297.984 Data: 00 00 F0 01 +T3F74 26283:298.004 - 0.545ms returns 4 (0x4) +T3F74 26283:301.088 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26283:301.115 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26283:302.291 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26283:302.319 - 1.238ms returns 16 (0x10) +T3F74 26283:302.339 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26283:302.368 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26283:302.737 Data: 1E 00 00 00 +T3F74 26283:302.758 - 0.425ms returns 4 (0x4) +T3F74 26283:302.775 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26283:302.792 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26283:303.237 Data: 00 00 00 00 00 00 00 00 00 00 00 00 71 00 00 00 ... +T3F74 26283:303.257 - 0.488ms returns 20 (0x14) +T3F74 26283:303.274 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26283:303.290 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26283:303.739 Data: 1F 03 00 00 +T3F74 26283:303.759 - 0.491ms returns 4 (0x4) +T3F74 26283:303.776 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26283:303.792 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26283:304.237 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26283:304.257 - 0.487ms returns 12 (0xC) +T3F74 26283:304.274 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26283:304.290 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26283:304.737 Data: 00 00 00 00 +T3F74 26283:304.757 - 0.489ms returns 4 (0x4) +T3F74 26283:304.774 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26283:304.790 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26283:305.236 Data: 00 00 00 00 +T3F74 26283:305.256 - 0.489ms returns 4 (0x4) +T3F74 26283:305.273 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26283:305.289 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26283:305.736 Data: 00 00 00 00 +T3F74 26283:305.756 - 0.490ms returns 4 (0x4) +T062C 26283:325.223 JLINK_IsHalted() +T062C 26283:326.252 - 1.049ms returns FALSE +T062C 26283:427.419 JLINK_HasError() +T062C 26283:427.501 JLINK_IsHalted() +T062C 26283:428.687 - 1.228ms returns FALSE +T062C 26283:529.006 JLINK_HasError() +T062C 26283:529.047 JLINK_IsHalted() +T062C 26283:530.181 - 1.158ms returns FALSE +T062C 26283:630.874 JLINK_HasError() +T062C 26283:630.900 JLINK_IsHalted() +T062C 26283:632.056 - 1.173ms returns FALSE +T062C 26283:732.486 JLINK_HasError() +T062C 26283:732.573 JLINK_IsHalted() +T062C 26283:733.698 - 1.146ms returns FALSE +T062C 26283:833.970 JLINK_HasError() +T062C 26283:834.057 JLINK_HasError() +T062C 26283:834.090 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26283:834.117 Data: 8D 12 74 01 +T062C 26283:834.138 Debug reg: DWT_CYCCNT +T062C 26283:834.156 - 0.073ms returns 1 (0x1) +T3F74 26283:836.719 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26283:836.754 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26283:837.841 Data: 00 00 80 00 +T3F74 26283:837.900 - 1.189ms returns 4 (0x4) +T3F74 26283:837.953 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26283:837.976 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26283:838.456 Data: 00 00 F0 01 +T3F74 26283:838.487 - 0.542ms returns 4 (0x4) +T3F74 26283:842.031 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26283:842.058 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26283:843.379 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26283:843.411 - 1.388ms returns 16 (0x10) +T3F74 26283:843.435 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26283:843.458 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26283:843.923 Data: 1E 00 00 00 +T3F74 26283:843.947 - 0.519ms returns 4 (0x4) +T3F74 26283:843.967 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26283:843.993 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26283:844.541 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B5 00 00 00 ... +T3F74 26283:844.561 - 0.600ms returns 20 (0x14) +T3F74 26283:844.578 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26283:844.594 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26283:845.040 Data: 1F 03 00 00 +T3F74 26283:845.060 - 0.487ms returns 4 (0x4) +T3F74 26283:845.077 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26283:845.093 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26283:845.541 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26283:845.571 - 0.501ms returns 12 (0xC) +T3F74 26283:845.588 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26283:845.605 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26283:846.039 Data: 00 00 00 00 +T3F74 26283:846.059 - 0.477ms returns 4 (0x4) +T3F74 26283:846.076 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26283:846.093 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26283:846.536 Data: 00 00 00 00 +T3F74 26283:846.556 - 0.485ms returns 4 (0x4) +T3F74 26283:846.572 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26283:846.589 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26283:847.035 Data: 00 00 00 00 +T3F74 26283:847.055 - 0.489ms returns 4 (0x4) +T062C 26283:859.120 JLINK_IsHalted() +T062C 26283:860.298 - 1.190ms returns FALSE +T062C 26283:961.617 JLINK_HasError() +T062C 26283:961.695 JLINK_IsHalted() +T062C 26283:962.966 - 1.314ms returns FALSE +T062C 26284:063.213 JLINK_HasError() +T062C 26284:063.290 JLINK_IsHalted() +T062C 26284:064.479 - 1.207ms returns FALSE +T062C 26284:165.375 JLINK_HasError() +T062C 26284:165.446 JLINK_IsHalted() +T062C 26284:166.609 - 1.205ms returns FALSE +T062C 26284:267.145 JLINK_HasError() +T062C 26284:267.216 JLINK_IsHalted() +T062C 26284:268.428 - 1.261ms returns FALSE +T062C 26284:369.125 JLINK_HasError() +T062C 26284:369.199 JLINK_HasError() +T062C 26284:369.243 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26284:369.313 Data: 8D 12 74 01 +T062C 26284:369.333 Debug reg: DWT_CYCCNT +T062C 26284:369.352 - 0.115ms returns 1 (0x1) +T3F74 26284:371.844 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26284:371.876 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26284:373.061 Data: 00 00 80 00 +T3F74 26284:373.129 - 1.292ms returns 4 (0x4) +T3F74 26284:373.163 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26284:373.182 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26284:373.596 Data: 00 00 F0 01 +T3F74 26284:373.616 - 0.460ms returns 4 (0x4) +T3F74 26284:376.728 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26284:376.758 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26284:377.982 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26284:378.014 - 1.295ms returns 16 (0x10) +T3F74 26284:378.038 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26284:378.061 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26284:378.470 Data: 1E 00 00 00 +T3F74 26284:378.493 - 0.463ms returns 4 (0x4) +T3F74 26284:378.514 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26284:378.533 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26284:379.110 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D9 02 00 00 ... +T3F74 26284:379.136 - 0.630ms returns 20 (0x14) +T3F74 26284:379.157 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26284:379.178 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26284:379.599 Data: 1F 03 00 00 +T3F74 26284:379.622 - 0.472ms returns 4 (0x4) +T3F74 26284:379.642 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26284:379.661 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26284:380.095 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26284:380.123 - 0.487ms returns 12 (0xC) +T3F74 26284:380.141 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26284:380.156 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26284:380.590 Data: 00 00 00 00 +T3F74 26284:380.609 - 0.475ms returns 4 (0x4) +T3F74 26284:380.627 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26284:380.643 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26284:381.104 Data: 00 00 00 00 +T3F74 26284:381.128 - 0.509ms returns 4 (0x4) +T3F74 26284:381.151 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26284:381.171 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26284:381.603 Data: 00 00 00 00 +T3F74 26284:381.627 - 0.483ms returns 4 (0x4) +T062C 26284:392.482 JLINK_IsHalted() +T062C 26284:393.681 - 1.219ms returns FALSE +T062C 26284:493.891 JLINK_HasError() +T062C 26284:493.970 JLINK_IsHalted() +T062C 26284:495.205 - 1.292ms returns FALSE +T062C 26284:596.197 JLINK_HasError() +T062C 26284:596.267 JLINK_IsHalted() +T062C 26284:597.580 - 1.356ms returns FALSE +T062C 26284:697.821 JLINK_HasError() +T062C 26284:697.893 JLINK_IsHalted() +T062C 26284:699.138 - 1.283ms returns FALSE +T062C 26284:800.141 JLINK_HasError() +T062C 26284:800.184 JLINK_IsHalted() +T062C 26284:801.325 - 1.162ms returns FALSE +T062C 26284:901.493 JLINK_HasError() +T062C 26284:901.581 JLINK_HasError() +T062C 26284:901.625 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26284:901.694 Data: 8D 12 74 01 +T062C 26284:901.751 Debug reg: DWT_CYCCNT +T062C 26284:901.805 - 0.190ms returns 1 (0x1) +T3F74 26284:904.256 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26284:904.289 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26284:905.544 Data: 00 00 80 00 +T3F74 26284:905.596 - 1.348ms returns 4 (0x4) +T3F74 26284:905.635 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26284:905.658 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26284:906.786 Data: 00 00 F0 01 +T3F74 26284:906.813 - 1.191ms returns 4 (0x4) +T3F74 26284:909.814 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26284:909.853 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26284:911.090 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26284:911.123 - 1.316ms returns 16 (0x10) +T3F74 26284:911.146 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26284:911.169 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26284:911.650 Data: 1E 00 00 00 +T3F74 26284:911.679 - 0.539ms returns 4 (0x4) +T3F74 26284:911.697 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26284:911.713 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26284:912.163 Data: 00 00 00 00 00 00 00 00 00 00 00 00 F5 01 00 00 ... +T3F74 26284:912.186 - 0.497ms returns 20 (0x14) +T3F74 26284:912.207 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26284:912.226 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26284:912.652 Data: 1F 03 00 00 +T3F74 26284:912.675 - 0.476ms returns 4 (0x4) +T3F74 26284:912.695 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26284:912.714 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26284:913.158 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26284:913.181 - 0.493ms returns 12 (0xC) +T3F74 26284:913.201 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26284:913.220 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26284:913.665 Data: 00 00 00 00 +T3F74 26284:913.689 - 0.496ms returns 4 (0x4) +T3F74 26284:913.709 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26284:913.728 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26284:914.147 Data: 00 00 00 00 +T3F74 26284:914.171 - 0.469ms returns 4 (0x4) +T3F74 26284:914.193 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26284:914.212 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26284:914.650 Data: 00 00 00 00 +T3F74 26284:914.674 - 0.488ms returns 4 (0x4) +T062C 26284:926.424 JLINK_IsHalted() +T062C 26284:927.545 - 1.137ms returns FALSE +T062C 26285:027.748 JLINK_HasError() +T062C 26285:027.833 JLINK_IsHalted() +T062C 26285:028.967 - 1.176ms returns FALSE +T062C 26285:129.447 JLINK_HasError() +T062C 26285:129.520 JLINK_IsHalted() +T062C 26285:130.628 - 1.116ms returns FALSE +T062C 26285:231.391 JLINK_HasError() +T062C 26285:231.465 JLINK_IsHalted() +T062C 26285:232.604 - 1.157ms returns FALSE +T062C 26285:332.861 JLINK_HasError() +T062C 26285:332.931 JLINK_IsHalted() +T062C 26285:334.098 - 1.185ms returns FALSE +T062C 26285:434.290 JLINK_HasError() +T062C 26285:434.369 JLINK_HasError() +T062C 26285:434.413 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26285:434.472 Data: 8D 12 74 01 +T062C 26285:434.493 Debug reg: DWT_CYCCNT +T062C 26285:434.511 - 0.104ms returns 1 (0x1) +T3F74 26285:436.975 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26285:437.008 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26285:438.177 Data: 00 00 80 00 +T3F74 26285:438.212 - 1.252ms returns 4 (0x4) +T3F74 26285:438.265 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26285:438.289 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26285:438.700 Data: 00 00 F0 01 +T3F74 26285:438.720 - 0.461ms returns 4 (0x4) +T3F74 26285:442.086 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26285:442.117 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26285:443.383 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26285:443.411 - 1.332ms returns 16 (0x10) +T3F74 26285:443.432 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26285:443.451 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26285:443.960 Data: 1F 00 00 00 +T3F74 26285:443.984 - 0.560ms returns 4 (0x4) +T3F74 26285:444.005 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26285:444.024 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26285:444.597 Data: 00 00 00 00 00 00 00 00 00 00 00 00 51 02 00 00 ... +T3F74 26285:444.623 - 0.626ms returns 20 (0x14) +T3F74 26285:444.643 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26285:444.663 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26285:445.089 Data: 1F 03 00 00 +T3F74 26285:445.113 - 0.478ms returns 4 (0x4) +T3F74 26285:445.134 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26285:445.154 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26285:445.577 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26285:445.596 - 0.469ms returns 12 (0xC) +T3F74 26285:445.614 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26285:445.630 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26285:446.078 Data: 00 00 00 00 +T3F74 26285:446.097 - 0.490ms returns 4 (0x4) +T3F74 26285:446.114 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26285:446.130 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26285:446.573 Data: 00 00 00 00 +T3F74 26285:446.593 - 0.485ms returns 4 (0x4) +T3F74 26285:446.610 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26285:446.625 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26285:447.072 Data: 00 00 00 00 +T3F74 26285:447.092 - 0.489ms returns 4 (0x4) +T062C 26285:465.737 JLINK_IsHalted() +T062C 26285:466.838 - 1.120ms returns FALSE +T062C 26285:567.314 JLINK_HasError() +T062C 26285:567.360 JLINK_IsHalted() +T062C 26285:568.528 - 1.210ms returns FALSE +T062C 26285:669.336 JLINK_HasError() +T062C 26285:669.408 JLINK_IsHalted() +T062C 26285:670.540 - 1.149ms returns FALSE +T062C 26285:770.725 JLINK_HasError() +T062C 26285:770.797 JLINK_IsHalted() +T062C 26285:771.920 - 1.141ms returns FALSE +T062C 26285:872.593 JLINK_HasError() +T062C 26285:872.637 JLINK_IsHalted() +T062C 26285:873.683 - 1.078ms returns FALSE +T062C 26285:974.258 JLINK_HasError() +T062C 26285:974.345 JLINK_HasError() +T062C 26285:974.380 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26285:974.406 Data: 8D 12 74 01 +T062C 26285:974.426 Debug reg: DWT_CYCCNT +T062C 26285:974.445 - 0.072ms returns 1 (0x1) +T3F74 26285:976.890 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26285:976.922 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26285:978.101 Data: 00 00 80 00 +T3F74 26285:978.140 - 1.259ms returns 4 (0x4) +T3F74 26285:978.184 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26285:978.208 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26285:978.637 Data: 00 00 F0 01 +T3F74 26285:978.662 - 0.485ms returns 4 (0x4) +T3F74 26285:981.963 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26285:981.989 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26285:983.211 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26285:983.272 - 1.329ms returns 16 (0x10) +T3F74 26285:983.345 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26285:983.396 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26285:984.519 Data: 1E 00 00 00 +T3F74 26285:984.545 - 1.208ms returns 4 (0x4) +T3F74 26285:984.570 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26285:984.591 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26285:985.136 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B5 02 00 00 ... +T3F74 26285:985.160 - 0.598ms returns 20 (0x14) +T3F74 26285:985.198 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26285:985.215 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26285:985.637 Data: 1F 03 00 00 +T3F74 26285:985.660 - 0.469ms returns 4 (0x4) +T3F74 26285:985.683 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26285:985.702 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26285:986.141 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26285:986.164 - 0.489ms returns 12 (0xC) +T3F74 26285:986.186 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26285:986.211 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26285:986.636 Data: 00 00 00 00 +T3F74 26285:986.660 - 0.481ms returns 4 (0x4) +T3F74 26285:986.683 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26285:986.702 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26285:987.137 Data: 00 00 00 00 +T3F74 26285:987.162 - 0.486ms returns 4 (0x4) +T3F74 26285:987.184 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26285:987.207 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26285:987.636 Data: 00 00 00 00 +T3F74 26285:987.659 - 0.482ms returns 4 (0x4) +T062C 26286:006.642 JLINK_IsHalted() +T062C 26286:007.791 - 1.167ms returns FALSE +T062C 26286:108.867 JLINK_HasError() +T062C 26286:108.960 JLINK_IsHalted() +T062C 26286:110.206 - 1.289ms returns FALSE +T062C 26286:210.983 JLINK_HasError() +T062C 26286:211.047 JLINK_IsHalted() +T062C 26286:212.215 - 1.186ms returns FALSE +T062C 26286:312.430 JLINK_HasError() +T062C 26286:312.503 JLINK_IsHalted() +T062C 26286:313.684 - 1.199ms returns FALSE +T062C 26286:414.453 JLINK_HasError() +T062C 26286:414.525 JLINK_IsHalted() +T062C 26286:415.701 - 1.224ms returns FALSE +T062C 26286:516.514 JLINK_HasError() +T062C 26286:516.588 JLINK_HasError() +T062C 26286:516.606 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26286:516.634 Data: 8D 12 74 01 +T062C 26286:516.657 Debug reg: DWT_CYCCNT +T062C 26286:516.679 - 0.081ms returns 1 (0x1) +T3F74 26286:519.102 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26286:519.143 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26286:520.289 Data: 00 00 80 00 +T3F74 26286:520.349 - 1.254ms returns 4 (0x4) +T3F74 26286:520.383 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26286:520.403 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26286:520.810 Data: 00 00 F0 01 +T3F74 26286:520.831 - 0.454ms returns 4 (0x4) +T3F74 26286:523.915 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26286:523.946 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26286:525.154 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26286:525.214 - 1.307ms returns 16 (0x10) +T3F74 26286:525.238 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26286:525.261 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26286:525.686 Data: 1E 00 00 00 +T3F74 26286:525.710 - 0.480ms returns 4 (0x4) +T3F74 26286:525.731 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26286:525.750 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26286:526.315 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B5 00 00 00 ... +T3F74 26286:526.335 - 0.611ms returns 20 (0x14) +T3F74 26286:526.353 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26286:526.369 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26286:526.810 Data: 1F 03 00 00 +T3F74 26286:526.833 - 0.488ms returns 4 (0x4) +T3F74 26286:526.857 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26286:526.876 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26286:527.314 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26286:527.337 - 0.488ms returns 12 (0xC) +T3F74 26286:527.360 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26286:527.382 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26286:527.986 Data: 00 00 00 00 +T3F74 26286:528.013 - 0.660ms returns 4 (0x4) +T3F74 26286:528.037 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26286:528.063 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26286:528.566 Data: 00 00 00 00 +T3F74 26286:528.589 - 0.560ms returns 4 (0x4) +T3F74 26286:528.612 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26286:528.632 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26286:529.060 Data: 00 00 00 00 +T3F74 26286:529.083 - 0.479ms returns 4 (0x4) +T062C 26286:540.527 JLINK_IsHalted() +T062C 26286:541.617 - 1.131ms returns FALSE +T062C 26286:641.804 JLINK_HasError() +T062C 26286:641.887 JLINK_IsHalted() +T062C 26286:643.130 - 1.284ms returns FALSE +T062C 26286:743.938 JLINK_HasError() +T062C 26286:744.022 JLINK_IsHalted() +T062C 26286:745.224 - 1.223ms returns FALSE +T062C 26286:845.936 JLINK_HasError() +T062C 26286:845.966 JLINK_IsHalted() +T062C 26286:847.113 - 1.164ms returns FALSE +T062C 26286:947.819 JLINK_HasError() +T062C 26286:947.859 JLINK_IsHalted() +T062C 26286:948.978 - 1.144ms returns FALSE +T062C 26287:049.148 JLINK_HasError() +T062C 26287:049.234 JLINK_HasError() +T062C 26287:049.282 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26287:049.344 Data: 8D 12 74 01 +T062C 26287:049.396 Debug reg: DWT_CYCCNT +T062C 26287:049.414 - 0.139ms returns 1 (0x1) +T3F74 26287:051.899 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26287:051.933 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26287:053.144 Data: 00 00 80 00 +T3F74 26287:053.225 - 1.352ms returns 4 (0x4) +T3F74 26287:053.285 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26287:053.308 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26287:054.398 Data: 00 00 F0 01 +T3F74 26287:054.431 - 1.153ms returns 4 (0x4) +T3F74 26287:057.652 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26287:057.679 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26287:058.936 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26287:058.966 - 1.321ms returns 16 (0x10) +T3F74 26287:058.997 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26287:059.020 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26287:059.490 Data: 1E 00 00 00 +T3F74 26287:059.520 - 0.531ms returns 4 (0x4) +T3F74 26287:059.541 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26287:059.560 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26287:060.136 Data: 00 00 00 00 00 00 00 00 00 00 00 00 FD 00 00 00 ... +T3F74 26287:060.171 - 0.638ms returns 20 (0x14) +T3F74 26287:060.197 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26287:060.220 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26287:060.623 Data: 1F 03 00 00 +T3F74 26287:060.652 - 0.463ms returns 4 (0x4) +T3F74 26287:060.675 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26287:060.695 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26287:061.113 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26287:061.133 - 0.465ms returns 12 (0xC) +T3F74 26287:061.150 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26287:061.166 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26287:061.607 Data: 00 00 00 00 +T3F74 26287:061.627 - 0.483ms returns 4 (0x4) +T3F74 26287:061.644 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26287:061.660 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26287:062.120 Data: 00 00 00 00 +T3F74 26287:062.144 - 0.507ms returns 4 (0x4) +T3F74 26287:062.163 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26287:062.182 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26287:062.633 Data: 00 00 00 00 +T3F74 26287:062.656 - 0.500ms returns 4 (0x4) +T062C 26287:074.540 JLINK_IsHalted() +T062C 26287:075.623 - 1.095ms returns FALSE +T062C 26287:176.728 JLINK_HasError() +T062C 26287:176.807 JLINK_IsHalted() +T062C 26287:177.990 - 1.225ms returns FALSE +T062C 26287:278.182 JLINK_HasError() +T062C 26287:278.259 JLINK_IsHalted() +T062C 26287:279.418 - 1.200ms returns FALSE +T062C 26287:380.144 JLINK_HasError() +T062C 26287:380.172 JLINK_IsHalted() +T062C 26287:381.350 - 1.220ms returns FALSE +T062C 26287:482.141 JLINK_HasError() +T062C 26287:482.211 JLINK_IsHalted() +T062C 26287:483.411 - 1.218ms returns FALSE +T062C 26287:584.179 JLINK_HasError() +T062C 26287:584.252 JLINK_HasError() +T062C 26287:584.270 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26287:584.298 Data: 8D 12 74 01 +T062C 26287:584.322 Debug reg: DWT_CYCCNT +T062C 26287:584.343 - 0.081ms returns 1 (0x1) +T3F74 26287:586.910 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26287:586.947 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26287:588.187 Data: 00 00 80 00 +T3F74 26287:588.222 - 1.320ms returns 4 (0x4) +T3F74 26287:588.261 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26287:588.284 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26287:588.663 Data: 00 00 F0 01 +T3F74 26287:588.683 - 0.429ms returns 4 (0x4) +T3F74 26287:592.207 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26287:592.240 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26287:593.424 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26287:593.452 - 1.251ms returns 16 (0x10) +T3F74 26287:593.472 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26287:593.492 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26287:593.912 Data: 1F 00 00 00 +T3F74 26287:593.946 - 0.480ms returns 4 (0x4) +T3F74 26287:593.963 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26287:593.988 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26287:594.554 Data: 00 00 00 00 00 00 00 00 00 00 00 00 8B 02 00 00 ... +T3F74 26287:594.577 - 0.622ms returns 20 (0x14) +T3F74 26287:594.598 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26287:594.617 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26287:595.048 Data: 1F 03 00 00 +T3F74 26287:595.071 - 0.481ms returns 4 (0x4) +T3F74 26287:595.091 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26287:595.110 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26287:595.596 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26287:595.619 - 0.535ms returns 12 (0xC) +T3F74 26287:595.639 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26287:595.658 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26287:596.042 Data: 00 00 00 00 +T3F74 26287:596.065 - 0.434ms returns 4 (0x4) +T3F74 26287:596.085 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26287:596.103 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26287:596.544 Data: 00 00 00 00 +T3F74 26287:596.568 - 0.490ms returns 4 (0x4) +T3F74 26287:596.587 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26287:596.606 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26287:597.042 Data: 00 00 00 00 +T3F74 26287:597.065 - 0.492ms returns 4 (0x4) +T062C 26287:616.762 JLINK_IsHalted() +T062C 26287:617.933 - 1.189ms returns FALSE +T062C 26287:718.672 JLINK_HasError() +T062C 26287:718.757 JLINK_IsHalted() +T062C 26287:719.873 - 1.134ms returns FALSE +T062C 26287:820.628 JLINK_HasError() +T062C 26287:820.712 JLINK_IsHalted() +T062C 26287:821.875 - 1.181ms returns FALSE +T062C 26287:923.122 JLINK_HasError() +T062C 26287:923.174 JLINK_IsHalted() +T062C 26287:924.275 - 1.119ms returns FALSE +T062C 26288:024.700 JLINK_HasError() +T062C 26288:024.746 JLINK_IsHalted() +T062C 26288:025.929 - 1.207ms returns FALSE +T062C 26288:126.963 JLINK_HasError() +T062C 26288:127.050 JLINK_HasError() +T062C 26288:127.094 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26288:127.163 Data: 8D 12 74 01 +T062C 26288:127.220 Debug reg: DWT_CYCCNT +T062C 26288:127.254 - 0.168ms returns 1 (0x1) +T3F74 26288:129.744 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26288:129.781 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26288:131.005 Data: 00 00 80 00 +T3F74 26288:131.085 - 1.365ms returns 4 (0x4) +T3F74 26288:131.176 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26288:131.199 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26288:132.308 Data: 00 00 F0 01 +T3F74 26288:132.385 - 1.229ms returns 4 (0x4) +T3F74 26288:135.667 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26288:135.694 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26288:136.995 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26288:137.028 - 1.369ms returns 16 (0x10) +T3F74 26288:137.053 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26288:137.075 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26288:137.483 Data: 1E 00 00 00 +T3F74 26288:137.523 - 0.479ms returns 4 (0x4) +T3F74 26288:137.548 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26288:137.574 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26288:138.100 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D3 02 00 00 ... +T3F74 26288:138.124 - 0.590ms returns 20 (0x14) +T3F74 26288:138.148 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26288:138.164 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26288:138.595 Data: 1F 03 00 00 +T3F74 26288:138.615 - 0.474ms returns 4 (0x4) +T3F74 26288:138.633 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26288:138.649 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26288:139.090 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26288:139.110 - 0.483ms returns 12 (0xC) +T3F74 26288:139.127 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26288:139.143 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26288:139.590 Data: 00 00 00 00 +T3F74 26288:139.610 - 0.490ms returns 4 (0x4) +T3F74 26288:139.627 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26288:139.643 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26288:140.094 Data: 00 00 00 00 +T3F74 26288:140.114 - 0.493ms returns 4 (0x4) +T3F74 26288:140.131 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26288:140.147 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26288:140.594 Data: 00 00 00 00 +T3F74 26288:140.614 - 0.490ms returns 4 (0x4) +T062C 26288:160.136 JLINK_IsHalted() +T062C 26288:161.230 - 1.112ms returns FALSE +T062C 26288:261.836 JLINK_HasError() +T062C 26288:261.916 JLINK_IsHalted() +T062C 26288:263.241 - 1.346ms returns FALSE +T062C 26288:363.933 JLINK_HasError() +T062C 26288:364.009 JLINK_IsHalted() +T062C 26288:365.160 - 1.193ms returns FALSE +T062C 26288:465.981 JLINK_HasError() +T062C 26288:466.051 JLINK_IsHalted() +T062C 26288:467.268 - 1.243ms returns FALSE +T062C 26288:567.426 JLINK_HasError() +T062C 26288:567.497 JLINK_IsHalted() +T062C 26288:568.726 - 1.245ms returns FALSE +T062C 26288:669.126 JLINK_HasError() +T062C 26288:669.159 JLINK_HasError() +T062C 26288:669.177 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26288:669.207 Data: 8D 12 74 01 +T062C 26288:669.231 Debug reg: DWT_CYCCNT +T062C 26288:669.254 - 0.084ms returns 1 (0x1) +T3F74 26288:675.396 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26288:675.428 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26288:676.629 Data: 00 00 80 00 +T3F74 26288:676.662 - 1.274ms returns 4 (0x4) +T3F74 26288:676.700 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26288:676.723 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26288:677.148 Data: 00 00 F0 01 +T3F74 26288:677.168 - 0.475ms returns 4 (0x4) +T3F74 26288:680.299 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26288:680.329 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26288:681.532 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26288:681.557 - 1.266ms returns 16 (0x10) +T3F74 26288:681.578 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26288:681.598 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26288:682.028 Data: 1E 00 00 00 +T3F74 26288:682.048 - 0.477ms returns 4 (0x4) +T3F74 26288:682.066 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26288:682.082 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26288:682.649 Data: 00 00 00 00 00 00 00 00 00 00 00 00 53 01 00 00 ... +T3F74 26288:682.672 - 0.614ms returns 20 (0x14) +T3F74 26288:682.692 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26288:682.711 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26288:683.305 Data: 1F 03 00 00 +T3F74 26288:683.343 - 0.658ms returns 4 (0x4) +T3F74 26288:683.377 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26288:683.404 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26288:684.651 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26288:684.680 - 1.309ms returns 12 (0xC) +T3F74 26288:684.700 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26288:684.719 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26288:685.178 Data: 00 00 00 00 +T3F74 26288:685.203 - 0.510ms returns 4 (0x4) +T3F74 26288:685.223 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26288:685.242 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26288:685.648 Data: 00 00 00 00 +T3F74 26288:685.672 - 0.456ms returns 4 (0x4) +T3F74 26288:685.692 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26288:685.711 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26288:686.153 Data: 00 00 00 00 +T3F74 26288:686.176 - 0.492ms returns 4 (0x4) +T062C 26288:697.438 JLINK_IsHalted() +T062C 26288:698.550 - 1.132ms returns FALSE +T062C 26288:799.880 JLINK_HasError() +T062C 26288:799.970 JLINK_IsHalted() +T062C 26288:801.241 - 1.313ms returns FALSE +T062C 26288:901.839 JLINK_HasError() +T062C 26288:901.866 JLINK_IsHalted() +T062C 26288:902.904 - 1.056ms returns FALSE +T062C 26289:003.761 JLINK_HasError() +T062C 26289:003.838 JLINK_IsHalted() +T062C 26289:005.077 - 1.257ms returns FALSE +T062C 26289:105.809 JLINK_HasError() +T062C 26289:105.854 JLINK_IsHalted() +T062C 26289:106.984 - 1.151ms returns FALSE +T062C 26289:207.694 JLINK_HasError() +T062C 26289:207.737 JLINK_HasError() +T062C 26289:207.752 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26289:207.778 Data: 8D 12 74 01 +T062C 26289:207.799 Debug reg: DWT_CYCCNT +T062C 26289:207.817 - 0.072ms returns 1 (0x1) +T3F74 26289:210.422 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26289:210.457 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26289:211.670 Data: 00 00 80 00 +T3F74 26289:211.737 - 1.322ms returns 4 (0x4) +T3F74 26289:211.773 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26289:211.792 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26289:212.214 Data: 00 00 F0 01 +T3F74 26289:212.250 - 0.485ms returns 4 (0x4) +T3F74 26289:215.763 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26289:215.791 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26289:217.010 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26289:217.040 - 1.283ms returns 16 (0x10) +T3F74 26289:217.060 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26289:217.080 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26289:217.577 Data: 1E 00 00 00 +T3F74 26289:217.598 - 0.544ms returns 4 (0x4) +T3F74 26289:217.615 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26289:217.631 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26289:218.077 Data: 00 00 00 00 00 00 00 00 00 00 00 00 9F 00 00 00 ... +T3F74 26289:218.097 - 0.488ms returns 20 (0x14) +T3F74 26289:218.114 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26289:218.130 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26289:218.576 Data: 1F 03 00 00 +T3F74 26289:218.596 - 0.488ms returns 4 (0x4) +T3F74 26289:218.613 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26289:218.629 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26289:219.071 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26289:219.091 - 0.484ms returns 12 (0xC) +T3F74 26289:219.108 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26289:219.124 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26289:219.571 Data: 00 00 00 00 +T3F74 26289:219.591 - 0.490ms returns 4 (0x4) +T3F74 26289:219.608 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26289:219.624 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26289:220.071 Data: 00 00 00 00 +T3F74 26289:220.091 - 0.489ms returns 4 (0x4) +T3F74 26289:220.108 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26289:220.124 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26289:220.583 Data: 00 00 00 00 +T3F74 26289:220.620 - 0.519ms returns 4 (0x4) +T062C 26289:233.178 JLINK_IsHalted() +T062C 26289:234.210 - 1.050ms returns FALSE +T062C 26289:335.611 JLINK_HasError() +T062C 26289:335.649 JLINK_IsHalted() +T062C 26289:336.767 - 1.160ms returns FALSE +T062C 26289:437.481 JLINK_HasError() +T062C 26289:437.508 JLINK_IsHalted() +T062C 26289:438.640 - 1.150ms returns FALSE +T062C 26289:539.538 JLINK_HasError() +T062C 26289:539.612 JLINK_IsHalted() +T062C 26289:540.933 - 1.335ms returns FALSE +T062C 26289:641.086 JLINK_HasError() +T062C 26289:641.175 JLINK_IsHalted() +T062C 26289:642.401 - 1.272ms returns FALSE +T062C 26289:742.680 JLINK_HasError() +T062C 26289:742.770 JLINK_HasError() +T062C 26289:742.829 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26289:742.906 Data: 8D 12 74 01 +T062C 26289:742.943 Debug reg: DWT_CYCCNT +T062C 26289:742.969 - 0.147ms returns 1 (0x1) +T3F74 26289:745.346 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26289:745.377 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26289:746.477 Data: 00 00 80 00 +T3F74 26289:746.554 - 1.216ms returns 4 (0x4) +T3F74 26289:746.591 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26289:746.619 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26289:747.012 Data: 00 00 F0 01 +T3F74 26289:747.036 - 0.453ms returns 4 (0x4) +T3F74 26289:750.533 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26289:750.561 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26289:751.838 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26289:751.898 - 1.385ms returns 16 (0x10) +T3F74 26289:751.952 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26289:751.977 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26289:752.380 Data: 1E 00 00 00 +T3F74 26289:752.401 - 0.456ms returns 4 (0x4) +T3F74 26289:752.418 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26289:752.434 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26289:752.880 Data: 00 00 00 00 00 00 00 00 00 00 00 00 41 00 00 00 ... +T3F74 26289:752.900 - 0.488ms returns 20 (0x14) +T3F74 26289:752.917 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26289:752.933 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26289:753.380 Data: 1F 03 00 00 +T3F74 26289:753.400 - 0.489ms returns 4 (0x4) +T3F74 26289:753.417 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26289:753.433 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26289:753.879 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26289:753.899 - 0.488ms returns 12 (0xC) +T3F74 26289:753.916 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26289:753.932 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26289:754.380 Data: 00 00 00 00 +T3F74 26289:754.400 - 0.490ms returns 4 (0x4) +T3F74 26289:754.417 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26289:754.433 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26289:754.880 Data: 00 00 00 00 +T3F74 26289:754.900 - 0.489ms returns 4 (0x4) +T3F74 26289:754.917 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26289:754.933 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26289:755.379 Data: 00 00 00 00 +T3F74 26289:755.399 - 0.489ms returns 4 (0x4) +T062C 26289:767.525 JLINK_IsHalted() +T062C 26289:768.641 - 1.135ms returns FALSE +T062C 26289:869.558 JLINK_HasError() +T062C 26289:869.599 JLINK_IsHalted() +T062C 26289:870.679 - 1.116ms returns FALSE +T062C 26289:970.889 JLINK_HasError() +T062C 26289:970.961 JLINK_IsHalted() +T062C 26289:972.195 - 1.252ms returns FALSE +T062C 26290:072.456 JLINK_HasError() +T062C 26290:072.530 JLINK_IsHalted() +T062C 26290:073.662 - 1.164ms returns FALSE +T062C 26290:173.802 JLINK_HasError() +T062C 26290:173.843 JLINK_IsHalted() +T062C 26290:175.026 - 1.203ms returns FALSE +T062C 26290:276.092 JLINK_HasError() +T062C 26290:276.137 JLINK_HasError() +T062C 26290:276.155 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26290:276.185 Data: 8D 12 74 01 +T062C 26290:276.209 Debug reg: DWT_CYCCNT +T062C 26290:276.231 - 0.083ms returns 1 (0x1) +T3F74 26290:278.816 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26290:278.853 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26290:280.029 Data: 00 00 80 00 +T3F74 26290:280.113 - 1.316ms returns 4 (0x4) +T3F74 26290:280.205 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26290:280.261 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26290:281.603 Data: 00 00 F0 01 +T3F74 26290:281.678 - 1.481ms returns 4 (0x4) +T3F74 26290:284.927 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26290:284.954 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26290:286.214 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26290:286.247 - 1.327ms returns 16 (0x10) +T3F74 26290:286.270 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26290:286.293 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26290:286.686 Data: 1E 00 00 00 +T3F74 26290:286.709 - 0.447ms returns 4 (0x4) +T3F74 26290:286.735 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26290:286.751 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26290:287.348 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1F 03 00 00 ... +T3F74 26290:287.384 - 0.657ms returns 20 (0x14) +T3F74 26290:287.411 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26290:287.433 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26290:287.954 Data: 1F 03 00 00 +T3F74 26290:287.985 - 0.582ms returns 4 (0x4) +T3F74 26290:288.007 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26290:288.028 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26290:288.564 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26290:288.584 - 0.583ms returns 12 (0xC) +T3F74 26290:288.601 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26290:288.617 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26290:289.058 Data: 00 00 00 00 +T3F74 26290:289.078 - 0.484ms returns 4 (0x4) +T3F74 26290:289.095 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26290:289.111 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26290:289.561 Data: 00 00 00 00 +T3F74 26290:289.581 - 0.492ms returns 4 (0x4) +T3F74 26290:289.598 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26290:289.614 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26290:290.054 Data: 00 00 00 00 +T3F74 26290:290.074 - 0.482ms returns 4 (0x4) +T062C 26290:302.288 JLINK_IsHalted() +T062C 26290:303.326 - 1.067ms returns FALSE +T062C 26290:404.004 JLINK_HasError() +T062C 26290:404.039 JLINK_IsHalted() +T062C 26290:405.204 - 1.207ms returns FALSE +T062C 26290:505.384 JLINK_HasError() +T062C 26290:505.455 JLINK_IsHalted() +T062C 26290:506.673 - 1.260ms returns FALSE +T062C 26290:607.213 JLINK_HasError() +T062C 26290:607.285 JLINK_IsHalted() +T062C 26290:608.536 - 1.293ms returns FALSE +T062C 26290:709.270 JLINK_HasError() +T062C 26290:709.341 JLINK_IsHalted() +T062C 26290:710.411 - 1.089ms returns FALSE +T062C 26290:811.102 JLINK_HasError() +T062C 26290:811.149 JLINK_HasError() +T062C 26290:811.169 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26290:811.198 Data: 8D 12 74 01 +T062C 26290:811.222 Debug reg: DWT_CYCCNT +T062C 26290:811.244 - 0.083ms returns 1 (0x1) +T3F74 26290:813.809 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26290:813.853 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26290:815.025 Data: 00 00 80 00 +T3F74 26290:815.074 - 1.273ms returns 4 (0x4) +T3F74 26290:815.114 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26290:815.138 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26290:816.255 Data: 00 00 F0 01 +T3F74 26290:816.288 - 1.182ms returns 4 (0x4) +T3F74 26290:819.392 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26290:819.419 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26290:820.664 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26290:820.692 - 1.307ms returns 16 (0x10) +T3F74 26290:820.713 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26290:820.732 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26290:821.130 Data: 1E 00 00 00 +T3F74 26290:821.166 - 0.461ms returns 4 (0x4) +T3F74 26290:821.187 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26290:821.207 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26290:821.745 Data: 00 00 00 00 00 00 00 00 00 00 00 00 75 01 00 00 ... +T3F74 26290:821.769 - 0.589ms returns 20 (0x14) +T3F74 26290:821.789 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26290:821.808 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26290:822.256 Data: 1F 03 00 00 +T3F74 26290:822.280 - 0.498ms returns 4 (0x4) +T3F74 26290:822.300 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26290:822.319 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26290:822.748 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26290:822.771 - 0.479ms returns 12 (0xC) +T3F74 26290:822.793 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26290:822.811 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26290:823.233 Data: 00 00 00 00 +T3F74 26290:823.253 - 0.466ms returns 4 (0x4) +T3F74 26290:823.269 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26290:823.285 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26290:823.733 Data: 00 00 00 00 +T3F74 26290:823.753 - 0.489ms returns 4 (0x4) +T3F74 26290:823.769 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26290:823.785 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26290:824.233 Data: 00 00 00 00 +T3F74 26290:824.253 - 0.490ms returns 4 (0x4) +T062C 26290:835.941 JLINK_IsHalted() +T062C 26290:837.044 - 1.150ms returns FALSE +T062C 26290:937.996 JLINK_HasError() +T062C 26290:938.212 JLINK_IsHalted() +T062C 26290:939.477 - 1.309ms returns FALSE +T062C 26291:040.493 JLINK_HasError() +T062C 26291:040.566 JLINK_IsHalted() +T062C 26291:041.833 - 1.309ms returns FALSE +T062C 26291:142.495 JLINK_HasError() +T062C 26291:142.565 JLINK_IsHalted() +T062C 26291:143.806 - 1.282ms returns FALSE +T062C 26291:244.533 JLINK_HasError() +T062C 26291:244.574 JLINK_IsHalted() +T062C 26291:245.782 - 1.231ms returns FALSE +T062C 26291:346.208 JLINK_HasError() +T062C 26291:346.294 JLINK_HasError() +T062C 26291:346.339 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26291:346.391 Data: 8D 12 74 01 +T062C 26291:346.412 Debug reg: DWT_CYCCNT +T062C 26291:346.430 - 0.098ms returns 1 (0x1) +T3F74 26291:348.931 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26291:348.973 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26291:350.139 Data: 00 00 80 00 +T3F74 26291:350.177 - 1.255ms returns 4 (0x4) +T3F74 26291:350.231 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26291:350.257 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26291:350.669 Data: 00 00 F0 01 +T3F74 26291:350.690 - 0.465ms returns 4 (0x4) +T3F74 26291:353.777 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26291:353.803 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26291:354.966 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26291:354.995 - 1.225ms returns 16 (0x10) +T3F74 26291:355.015 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26291:355.035 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26291:355.542 Data: 1F 00 00 00 +T3F74 26291:355.566 - 0.558ms returns 4 (0x4) +T3F74 26291:355.586 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26291:355.606 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26291:356.168 Data: 00 00 00 00 00 00 00 00 00 00 00 00 31 02 00 00 ... +T3F74 26291:356.194 - 0.619ms returns 20 (0x14) +T3F74 26291:356.227 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26291:356.249 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26291:356.667 Data: 1F 03 00 00 +T3F74 26291:356.694 - 0.479ms returns 4 (0x4) +T3F74 26291:356.720 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26291:356.739 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26291:357.167 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26291:357.187 - 0.473ms returns 12 (0xC) +T3F74 26291:357.204 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26291:357.226 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26291:357.666 Data: 00 00 00 00 +T3F74 26291:357.686 - 0.488ms returns 4 (0x4) +T3F74 26291:357.703 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26291:357.719 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26291:358.167 Data: 00 00 00 00 +T3F74 26291:358.186 - 0.490ms returns 4 (0x4) +T3F74 26291:358.203 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26291:358.219 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26291:358.690 Data: 00 00 00 00 +T3F74 26291:358.710 - 0.513ms returns 4 (0x4) +T062C 26291:377.770 JLINK_IsHalted() +T062C 26291:378.804 - 1.051ms returns FALSE +T062C 26291:478.996 JLINK_HasError() +T062C 26291:479.073 JLINK_IsHalted() +T062C 26291:480.222 - 1.197ms returns FALSE +T062C 26291:581.006 JLINK_HasError() +T062C 26291:581.038 JLINK_IsHalted() +T062C 26291:582.191 - 1.194ms returns FALSE +T062C 26291:683.012 JLINK_HasError() +T062C 26291:683.086 JLINK_IsHalted() +T062C 26291:684.243 - 1.175ms returns FALSE +T062C 26291:784.439 JLINK_HasError() +T062C 26291:784.517 JLINK_IsHalted() +T062C 26291:785.736 - 1.267ms returns FALSE +T062C 26291:885.987 JLINK_HasError() +T062C 26291:886.059 JLINK_HasError() +T062C 26291:886.104 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26291:886.163 Data: 8D 12 74 01 +T062C 26291:886.183 Debug reg: DWT_CYCCNT +T062C 26291:886.202 - 0.105ms returns 1 (0x1) +T3F74 26291:888.639 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26291:888.671 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26291:889.745 Data: 00 00 80 00 +T3F74 26291:889.780 - 1.149ms returns 4 (0x4) +T3F74 26291:889.830 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26291:889.853 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26291:890.352 Data: 00 00 F0 01 +T3F74 26291:890.381 - 0.558ms returns 4 (0x4) +T3F74 26291:893.362 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26291:893.389 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26291:894.654 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26291:894.682 - 1.328ms returns 16 (0x10) +T3F74 26291:894.703 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26291:894.722 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26291:895.095 Data: 1E 00 00 00 +T3F74 26291:895.116 - 0.419ms returns 4 (0x4) +T3F74 26291:895.133 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26291:895.149 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26291:895.595 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E3 02 00 00 ... +T3F74 26291:895.615 - 0.488ms returns 20 (0x14) +T3F74 26291:895.632 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26291:895.648 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26291:896.094 Data: 1F 03 00 00 +T3F74 26291:896.114 - 0.488ms returns 4 (0x4) +T3F74 26291:896.131 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26291:896.148 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26291:896.595 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26291:896.615 - 0.490ms returns 12 (0xC) +T3F74 26291:896.632 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26291:896.648 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26291:897.094 Data: 00 00 00 00 +T3F74 26291:897.114 - 0.489ms returns 4 (0x4) +T3F74 26291:897.131 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26291:897.147 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26291:897.594 Data: 00 00 00 00 +T3F74 26291:897.614 - 0.490ms returns 4 (0x4) +T3F74 26291:897.631 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26291:897.647 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26291:898.100 Data: 00 00 00 00 +T3F74 26291:898.120 - 0.496ms returns 4 (0x4) +T062C 26291:916.365 JLINK_IsHalted() +T062C 26291:917.547 - 1.201ms returns FALSE +T062C 26292:017.698 JLINK_HasError() +T062C 26292:017.779 JLINK_IsHalted() +T062C 26292:018.850 - 1.088ms returns FALSE +T062C 26292:119.972 JLINK_HasError() +T062C 26292:120.044 JLINK_IsHalted() +T062C 26292:121.306 - 1.288ms returns FALSE +T062C 26292:221.518 JLINK_HasError() +T062C 26292:221.595 JLINK_IsHalted() +T062C 26292:222.805 - 1.252ms returns FALSE +T062C 26292:323.358 JLINK_HasError() +T062C 26292:323.440 JLINK_IsHalted() +T062C 26292:324.583 - 1.162ms returns FALSE +T062C 26292:424.797 JLINK_HasError() +T062C 26292:424.884 JLINK_HasError() +T062C 26292:424.929 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26292:424.979 Data: 8D 12 74 01 +T062C 26292:424.999 Debug reg: DWT_CYCCNT +T062C 26292:425.018 - 0.095ms returns 1 (0x1) +T3F74 26292:427.407 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26292:427.440 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26292:428.657 Data: 00 00 80 00 +T3F74 26292:428.692 - 1.292ms returns 4 (0x4) +T3F74 26292:428.731 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26292:428.754 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26292:429.159 Data: 00 00 F0 01 +T3F74 26292:429.182 - 0.459ms returns 4 (0x4) +T3F74 26292:432.160 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26292:432.187 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26292:433.409 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26292:433.435 - 1.282ms returns 16 (0x10) +T3F74 26292:433.457 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26292:433.476 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26292:433.906 Data: 1E 00 00 00 +T3F74 26292:433.930 - 0.481ms returns 4 (0x4) +T3F74 26292:433.950 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26292:433.969 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26292:434.534 Data: 00 00 00 00 00 00 00 00 00 00 00 00 5B 02 00 00 ... +T3F74 26292:434.558 - 0.615ms returns 20 (0x14) +T3F74 26292:434.578 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26292:434.597 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26292:435.044 Data: 1F 03 00 00 +T3F74 26292:435.065 - 0.493ms returns 4 (0x4) +T3F74 26292:435.082 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26292:435.098 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26292:435.545 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26292:435.582 - 0.508ms returns 12 (0xC) +T3F74 26292:435.662 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26292:435.682 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26292:436.149 Data: 00 00 00 00 +T3F74 26292:436.173 - 0.519ms returns 4 (0x4) +T3F74 26292:436.193 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26292:436.212 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26292:436.667 Data: 00 00 00 00 +T3F74 26292:436.702 - 0.517ms returns 4 (0x4) +T3F74 26292:436.729 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26292:436.752 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26292:437.162 Data: 00 00 00 00 +T3F74 26292:437.191 - 0.469ms returns 4 (0x4) +T062C 26292:448.987 JLINK_IsHalted() +T062C 26292:450.069 - 1.100ms returns FALSE +T062C 26292:550.550 JLINK_HasError() +T062C 26292:550.626 JLINK_IsHalted() +T062C 26292:551.755 - 1.146ms returns FALSE +T062C 26292:652.109 JLINK_HasError() +T062C 26292:652.181 JLINK_IsHalted() +T062C 26292:653.386 - 1.246ms returns FALSE +T062C 26292:753.591 JLINK_HasError() +T062C 26292:753.670 JLINK_IsHalted() +T062C 26292:754.830 - 1.202ms returns FALSE +T062C 26292:855.371 JLINK_HasError() +T062C 26292:855.410 JLINK_IsHalted() +T062C 26292:856.527 - 1.135ms returns FALSE +T062C 26292:957.212 JLINK_HasError() +T062C 26292:957.242 JLINK_HasError() +T062C 26292:957.257 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26292:957.284 Data: 8D 12 74 01 +T062C 26292:957.304 Debug reg: DWT_CYCCNT +T062C 26292:957.323 - 0.072ms returns 1 (0x1) +T3F74 26292:959.693 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26292:959.725 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26292:960.854 Data: 00 00 80 00 +T3F74 26292:960.892 - 1.207ms returns 4 (0x4) +T3F74 26292:960.933 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26292:960.956 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26292:961.455 Data: 00 00 F0 01 +T3F74 26292:961.479 - 0.553ms returns 4 (0x4) +T3F74 26292:964.771 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26292:964.798 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26292:966.010 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26292:966.038 - 1.274ms returns 16 (0x10) +T3F74 26292:966.059 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26292:966.078 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26292:966.453 Data: 1E 00 00 00 +T3F74 26292:966.473 - 0.421ms returns 4 (0x4) +T3F74 26292:966.491 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26292:966.507 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26292:967.030 Data: 00 00 00 00 00 00 00 00 00 00 00 00 27 00 00 00 ... +T3F74 26292:967.053 - 0.570ms returns 20 (0x14) +T3F74 26292:967.073 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26292:967.092 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26292:967.580 Data: 1F 03 00 00 +T3F74 26292:967.604 - 0.539ms returns 4 (0x4) +T3F74 26292:967.624 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26292:967.643 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26292:968.078 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26292:968.101 - 0.484ms returns 12 (0xC) +T3F74 26292:968.121 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26292:968.140 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26292:968.584 Data: 00 00 00 00 +T3F74 26292:968.607 - 0.494ms returns 4 (0x4) +T3F74 26292:968.647 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26292:968.664 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26292:969.082 Data: 00 00 00 00 +T3F74 26292:969.105 - 0.465ms returns 4 (0x4) +T3F74 26292:969.128 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26292:969.147 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26292:969.606 Data: 00 00 00 00 +T3F74 26292:969.629 - 0.509ms returns 4 (0x4) +T062C 26292:981.722 JLINK_IsHalted() +T062C 26292:982.850 - 1.145ms returns FALSE +T062C 26293:083.603 JLINK_HasError() +T062C 26293:083.696 JLINK_IsHalted() +T062C 26293:084.871 - 1.194ms returns FALSE +T062C 26293:186.016 JLINK_HasError() +T062C 26293:186.048 JLINK_IsHalted() +T062C 26293:187.101 - 1.071ms returns FALSE +T062C 26293:287.922 JLINK_HasError() +T062C 26293:287.995 JLINK_IsHalted() +T062C 26293:289.122 - 1.170ms returns FALSE +T062C 26293:390.132 JLINK_HasError() +T062C 26293:390.215 JLINK_IsHalted() +T062C 26293:391.293 - 1.097ms returns FALSE +T062C 26293:491.472 JLINK_HasError() +T062C 26293:491.679 JLINK_HasError() +T062C 26293:491.729 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26293:491.791 Data: 8D 12 74 01 +T062C 26293:491.853 Debug reg: DWT_CYCCNT +T062C 26293:491.877 - 0.155ms returns 1 (0x1) +T3F74 26293:494.283 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26293:494.316 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26293:495.482 Data: 00 00 80 00 +T3F74 26293:495.517 - 1.242ms returns 4 (0x4) +T3F74 26293:495.556 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26293:495.579 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26293:496.004 Data: 00 00 F0 01 +T3F74 26293:496.024 - 0.474ms returns 4 (0x4) +T3F74 26293:499.267 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26293:499.294 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26293:500.608 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26293:500.663 - 1.404ms returns 16 (0x10) +T3F74 26293:500.687 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26293:500.709 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26293:501.139 Data: 1E 00 00 00 +T3F74 26293:501.163 - 0.484ms returns 4 (0x4) +T3F74 26293:501.183 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26293:501.203 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26293:501.758 Data: 00 00 00 00 00 00 00 00 00 00 00 00 49 01 00 00 ... +T3F74 26293:501.782 - 0.606ms returns 20 (0x14) +T3F74 26293:501.802 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26293:501.832 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26293:502.262 Data: 1F 03 00 00 +T3F74 26293:502.285 - 0.491ms returns 4 (0x4) +T3F74 26293:502.305 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26293:502.324 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26293:502.751 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26293:502.771 - 0.472ms returns 12 (0xC) +T3F74 26293:502.788 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26293:502.805 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26293:503.266 Data: 00 00 00 00 +T3F74 26293:503.289 - 0.508ms returns 4 (0x4) +T3F74 26293:503.313 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26293:503.332 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26293:503.766 Data: 00 00 00 00 +T3F74 26293:503.789 - 0.484ms returns 4 (0x4) +T3F74 26293:503.811 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26293:503.830 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26293:504.262 Data: 00 00 00 00 +T3F74 26293:504.285 - 0.481ms returns 4 (0x4) +T062C 26293:515.893 JLINK_IsHalted() +T062C 26293:517.042 - 1.168ms returns FALSE +T062C 26293:618.094 JLINK_HasError() +T062C 26293:618.138 JLINK_IsHalted() +T062C 26293:619.268 - 1.148ms returns FALSE +T062C 26293:719.475 JLINK_HasError() +T062C 26293:719.546 JLINK_IsHalted() +T062C 26293:720.722 - 1.218ms returns FALSE +T062C 26293:821.003 JLINK_HasError() +T062C 26293:821.078 JLINK_IsHalted() +T062C 26293:822.343 - 1.314ms returns FALSE +T062C 26293:923.096 JLINK_HasError() +T062C 26293:923.135 JLINK_IsHalted() +T062C 26293:924.318 - 1.201ms returns FALSE +T062C 26294:024.470 JLINK_HasError() +T062C 26294:024.544 JLINK_HasError() +T062C 26294:024.572 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26294:024.601 Data: 8D 12 74 01 +T062C 26294:024.625 Debug reg: DWT_CYCCNT +T062C 26294:024.647 - 0.083ms returns 1 (0x1) +T3F74 26294:028.519 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26294:028.552 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26294:029.662 Data: 00 00 80 00 +T3F74 26294:029.724 - 1.211ms returns 4 (0x4) +T3F74 26294:029.758 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26294:029.777 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26294:030.187 Data: 00 00 F0 01 +T3F74 26294:030.208 - 0.457ms returns 4 (0x4) +T3F74 26294:033.193 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26294:033.220 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26294:034.561 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26294:034.591 - 1.411ms returns 16 (0x10) +T3F74 26294:034.620 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26294:034.643 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26294:035.066 Data: 1E 00 00 00 +T3F74 26294:035.090 - 0.477ms returns 4 (0x4) +T3F74 26294:035.110 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26294:035.129 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26294:035.688 Data: 00 00 00 00 00 00 00 00 00 00 00 00 AF 02 00 00 ... +T3F74 26294:035.712 - 0.609ms returns 20 (0x14) +T3F74 26294:035.732 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26294:035.751 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26294:036.188 Data: 1F 03 00 00 +T3F74 26294:036.212 - 0.487ms returns 4 (0x4) +T3F74 26294:036.232 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26294:036.260 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26294:036.681 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26294:036.701 - 0.475ms returns 12 (0xC) +T3F74 26294:036.733 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26294:036.749 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26294:037.185 Data: 00 00 00 00 +T3F74 26294:037.209 - 0.484ms returns 4 (0x4) +T3F74 26294:037.232 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26294:037.251 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26294:037.701 Data: 00 00 00 00 +T3F74 26294:037.737 - 0.519ms returns 4 (0x4) +T3F74 26294:037.812 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26294:037.836 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26294:038.321 Data: 00 00 00 00 +T3F74 26294:038.352 - 0.548ms returns 4 (0x4) +T062C 26294:049.466 JLINK_IsHalted() +T062C 26294:050.586 - 1.138ms returns FALSE +T062C 26294:150.773 JLINK_HasError() +T062C 26294:150.857 JLINK_IsHalted() +T062C 26294:151.946 - 1.107ms returns FALSE +T062C 26294:252.608 JLINK_HasError() +T062C 26294:252.679 JLINK_IsHalted() +T062C 26294:253.868 - 1.231ms returns FALSE +T062C 26294:354.519 JLINK_HasError() +T062C 26294:354.590 JLINK_IsHalted() +T062C 26294:355.725 - 1.163ms returns FALSE +T062C 26294:455.876 JLINK_HasError() +T062C 26294:455.947 JLINK_IsHalted() +T062C 26294:457.123 - 1.224ms returns FALSE +T062C 26294:558.421 JLINK_HasError() +T062C 26294:558.508 JLINK_HasError() +T062C 26294:558.553 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26294:558.614 Data: 8D 12 74 01 +T062C 26294:558.671 Debug reg: DWT_CYCCNT +T062C 26294:558.725 - 0.187ms returns 1 (0x1) +T3F74 26294:561.297 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26294:561.330 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26294:562.520 Data: 00 00 80 00 +T3F74 26294:562.601 - 1.331ms returns 4 (0x4) +T3F74 26294:562.662 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26294:562.685 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26294:563.835 Data: 00 00 F0 01 +T3F74 26294:563.913 - 1.271ms returns 4 (0x4) +T3F74 26294:566.983 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26294:567.014 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26294:568.391 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26294:568.419 - 1.444ms returns 16 (0x10) +T3F74 26294:568.449 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26294:568.471 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26294:569.097 Data: 1F 00 00 00 +T3F74 26294:569.133 - 0.692ms returns 4 (0x4) +T3F74 26294:569.159 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26294:569.181 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26294:570.414 Data: 00 00 00 00 00 00 00 00 00 00 00 00 63 00 00 00 ... +T3F74 26294:570.443 - 1.291ms returns 20 (0x14) +T3F74 26294:570.463 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26294:570.482 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26294:570.860 Data: 1F 03 00 00 +T3F74 26294:570.881 - 0.424ms returns 4 (0x4) +T3F74 26294:570.898 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26294:570.914 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26294:571.364 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26294:571.384 - 0.492ms returns 12 (0xC) +T3F74 26294:571.414 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26294:571.430 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26294:571.870 Data: 00 00 00 00 +T3F74 26294:571.893 - 0.487ms returns 4 (0x4) +T3F74 26294:571.916 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26294:571.935 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26294:572.373 Data: 00 00 00 00 +T3F74 26294:572.397 - 0.488ms returns 4 (0x4) +T3F74 26294:572.419 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26294:572.438 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26294:572.870 Data: 00 00 00 00 +T3F74 26294:572.893 - 0.483ms returns 4 (0x4) +T062C 26294:592.000 JLINK_IsHalted() +T062C 26294:593.125 - 1.153ms returns FALSE +T062C 26294:693.642 JLINK_HasError() +T062C 26294:693.722 JLINK_IsHalted() +T062C 26294:694.977 - 1.303ms returns FALSE +T062C 26294:795.219 JLINK_HasError() +T062C 26294:795.293 JLINK_IsHalted() +T062C 26294:796.497 - 1.222ms returns FALSE +T062C 26294:897.204 JLINK_HasError() +T062C 26294:897.233 JLINK_IsHalted() +T062C 26294:898.287 - 1.071ms returns FALSE +T062C 26294:999.313 JLINK_HasError() +T062C 26294:999.399 JLINK_IsHalted() +T062C 26295:000.633 - 1.250ms returns FALSE +T062C 26295:100.824 JLINK_HasError() +T062C 26295:100.901 JLINK_HasError() +T062C 26295:101.038 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26295:101.068 Data: 8D 12 74 01 +T062C 26295:101.089 Debug reg: DWT_CYCCNT +T062C 26295:101.107 - 0.076ms returns 1 (0x1) +T3F74 26295:103.621 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26295:103.655 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26295:104.691 Data: 00 00 80 00 +T3F74 26295:104.729 - 1.116ms returns 4 (0x4) +T3F74 26295:104.797 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26295:104.879 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26295:105.326 Data: 00 00 F0 01 +T3F74 26295:105.350 - 0.561ms returns 4 (0x4) +T3F74 26295:108.498 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26295:108.525 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26295:109.719 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26295:109.747 - 1.256ms returns 16 (0x10) +T3F74 26295:109.767 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26295:109.787 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26295:110.170 Data: 1E 00 00 00 +T3F74 26295:110.190 - 0.429ms returns 4 (0x4) +T3F74 26295:110.207 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26295:110.224 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26295:110.679 Data: 00 00 00 00 00 00 00 00 00 00 00 00 A5 02 00 00 ... +T3F74 26295:110.713 - 0.514ms returns 20 (0x14) +T3F74 26295:110.739 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26295:110.762 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26295:111.176 Data: 1F 03 00 00 +T3F74 26295:111.205 - 0.473ms returns 4 (0x4) +T3F74 26295:111.227 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26295:111.247 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26295:111.792 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26295:111.812 - 0.591ms returns 12 (0xC) +T3F74 26295:111.829 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26295:111.845 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26295:112.292 Data: 00 00 00 00 +T3F74 26295:112.312 - 0.489ms returns 4 (0x4) +T3F74 26295:112.329 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26295:112.345 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26295:112.792 Data: 00 00 00 00 +T3F74 26295:112.812 - 0.490ms returns 4 (0x4) +T3F74 26295:112.830 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26295:112.846 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26295:113.291 Data: 00 00 00 00 +T3F74 26295:113.311 - 0.487ms returns 4 (0x4) +T062C 26295:131.962 JLINK_IsHalted() +T062C 26295:133.083 - 1.139ms returns FALSE +T062C 26295:233.297 JLINK_HasError() +T062C 26295:233.375 JLINK_IsHalted() +T062C 26295:234.659 - 1.328ms returns FALSE +T062C 26295:335.270 JLINK_HasError() +T062C 26295:335.296 JLINK_IsHalted() +T062C 26295:336.504 - 1.243ms returns FALSE +T062C 26295:437.122 JLINK_HasError() +T062C 26295:437.161 JLINK_IsHalted() +T062C 26295:438.398 - 1.259ms returns FALSE +T062C 26295:538.611 JLINK_HasError() +T062C 26295:538.664 JLINK_IsHalted() +T062C 26295:539.763 - 1.118ms returns FALSE +T062C 26295:640.411 JLINK_HasError() +T062C 26295:640.501 JLINK_HasError() +T062C 26295:640.523 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26295:640.552 Data: 8D 12 74 01 +T062C 26295:640.576 Debug reg: DWT_CYCCNT +T062C 26295:640.598 - 0.082ms returns 1 (0x1) +T3F74 26295:643.106 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26295:643.139 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26295:644.355 Data: 00 00 80 00 +T3F74 26295:644.390 - 1.292ms returns 4 (0x4) +T3F74 26295:644.431 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26295:644.454 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26295:644.847 Data: 00 00 F0 01 +T3F74 26295:644.868 - 0.443ms returns 4 (0x4) +T3F74 26295:648.092 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26295:648.123 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26295:649.404 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26295:649.432 - 1.353ms returns 16 (0x10) +T3F74 26295:649.463 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26295:649.483 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26295:649.971 Data: 1E 00 00 00 +T3F74 26295:649.991 - 0.535ms returns 4 (0x4) +T3F74 26295:650.008 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26295:650.025 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26295:650.472 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B7 02 00 00 ... +T3F74 26295:650.492 - 0.490ms returns 20 (0x14) +T3F74 26295:650.509 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26295:650.525 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26295:650.970 Data: 1F 03 00 00 +T3F74 26295:650.990 - 0.487ms returns 4 (0x4) +T3F74 26295:651.007 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26295:651.023 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26295:651.471 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26295:651.491 - 0.490ms returns 12 (0xC) +T3F74 26295:651.508 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26295:651.524 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26295:651.998 Data: 00 00 00 00 +T3F74 26295:652.018 - 0.517ms returns 4 (0x4) +T3F74 26295:652.035 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26295:652.051 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26295:652.466 Data: 00 00 00 00 +T3F74 26295:652.486 - 0.457ms returns 4 (0x4) +T3F74 26295:652.503 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26295:652.519 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26295:653.096 Data: 00 00 00 00 +T3F74 26295:653.120 - 0.624ms returns 4 (0x4) +T062C 26295:665.295 JLINK_IsHalted() +T062C 26295:666.396 - 1.142ms returns FALSE +T062C 26295:767.250 JLINK_HasError() +T062C 26295:767.295 JLINK_IsHalted() +T062C 26295:768.416 - 1.163ms returns FALSE +T062C 26295:868.637 JLINK_HasError() +T062C 26295:868.684 JLINK_IsHalted() +T062C 26295:869.722 - 1.056ms returns FALSE +T062C 26295:970.068 JLINK_HasError() +T062C 26295:970.115 JLINK_IsHalted() +T062C 26295:971.242 - 1.144ms returns FALSE +T062C 26296:071.527 JLINK_HasError() +T062C 26296:071.600 JLINK_IsHalted() +T062C 26296:072.797 - 1.246ms returns FALSE +T062C 26296:173.671 JLINK_HasError() +T062C 26296:173.743 JLINK_HasError() +T062C 26296:173.788 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26296:173.848 Data: 8D 12 74 01 +T062C 26296:173.911 Debug reg: DWT_CYCCNT +T062C 26296:173.930 - 0.149ms returns 1 (0x1) +T3F74 26296:176.400 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26296:176.433 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26296:177.674 Data: 00 00 80 00 +T3F74 26296:177.754 - 1.374ms returns 4 (0x4) +T3F74 26296:177.817 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26296:177.840 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26296:178.972 Data: 00 00 F0 01 +T3F74 26296:179.005 - 1.195ms returns 4 (0x4) +T3F74 26296:182.111 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26296:182.139 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26296:183.296 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26296:183.320 - 1.217ms returns 16 (0x10) +T3F74 26296:183.342 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26296:183.361 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26296:183.783 Data: 1E 00 00 00 +T3F74 26296:183.806 - 0.473ms returns 4 (0x4) +T3F74 26296:183.827 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26296:183.846 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26296:184.399 Data: 00 00 00 00 00 00 00 00 00 00 00 00 13 03 00 00 ... +T3F74 26296:184.419 - 0.599ms returns 20 (0x14) +T3F74 26296:184.437 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26296:184.453 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26296:184.900 Data: 1F 03 00 00 +T3F74 26296:184.920 - 0.490ms returns 4 (0x4) +T3F74 26296:184.937 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26296:184.953 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26296:185.400 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26296:185.420 - 0.489ms returns 12 (0xC) +T3F74 26296:185.437 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26296:185.453 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26296:185.899 Data: 00 00 00 00 +T3F74 26296:185.919 - 0.489ms returns 4 (0x4) +T3F74 26296:185.937 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26296:185.953 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26296:186.550 Data: 00 00 00 00 +T3F74 26296:186.574 - 0.645ms returns 4 (0x4) +T3F74 26296:186.594 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26296:186.614 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26296:187.025 Data: 00 00 00 00 +T3F74 26296:187.049 - 0.463ms returns 4 (0x4) +T062C 26296:199.051 JLINK_IsHalted() +T062C 26296:200.185 - 1.153ms returns FALSE +T062C 26296:301.027 JLINK_HasError() +T062C 26296:301.108 JLINK_IsHalted() +T062C 26296:302.279 - 1.196ms returns FALSE +T062C 26296:402.463 JLINK_HasError() +T062C 26296:402.536 JLINK_IsHalted() +T062C 26296:403.696 - 1.202ms returns FALSE +T062C 26296:504.540 JLINK_HasError() +T062C 26296:504.577 JLINK_IsHalted() +T062C 26296:505.637 - 1.078ms returns FALSE +T062C 26296:606.643 JLINK_HasError() +T062C 26296:606.779 JLINK_IsHalted() +T062C 26296:607.866 - 1.110ms returns FALSE +T062C 26296:708.085 JLINK_HasError() +T062C 26296:708.172 JLINK_HasError() +T062C 26296:708.216 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26296:708.260 Data: 8D 12 74 01 +T062C 26296:708.281 Debug reg: DWT_CYCCNT +T062C 26296:708.299 - 0.090ms returns 1 (0x1) +T3F74 26296:710.849 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26296:710.882 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26296:711.989 Data: 00 00 80 00 +T3F74 26296:712.029 - 1.188ms returns 4 (0x4) +T3F74 26296:712.078 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26296:712.101 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26296:712.587 Data: 00 00 F0 01 +T3F74 26296:712.611 - 0.541ms returns 4 (0x4) +T3F74 26296:715.627 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26296:715.654 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26296:716.878 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26296:716.906 - 1.286ms returns 16 (0x10) +T3F74 26296:716.927 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26296:716.946 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26296:717.326 Data: 1E 00 00 00 +T3F74 26296:717.346 - 0.426ms returns 4 (0x4) +T3F74 26296:717.363 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26296:717.380 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26296:717.825 Data: 00 00 00 00 00 00 00 00 00 00 00 00 29 00 00 00 ... +T3F74 26296:717.845 - 0.488ms returns 20 (0x14) +T3F74 26296:717.862 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26296:717.878 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26296:718.324 Data: 1F 03 00 00 +T3F74 26296:718.345 - 0.489ms returns 4 (0x4) +T3F74 26296:718.362 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26296:718.378 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26296:718.829 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26296:718.852 - 0.498ms returns 12 (0xC) +T3F74 26296:718.872 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26296:718.891 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26296:719.330 Data: 00 00 00 00 +T3F74 26296:719.353 - 0.489ms returns 4 (0x4) +T3F74 26296:719.373 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26296:719.392 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26296:719.862 Data: 00 00 00 00 +T3F74 26296:719.888 - 0.522ms returns 4 (0x4) +T3F74 26296:719.909 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26296:719.929 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26296:720.354 Data: 00 00 00 00 +T3F74 26296:720.378 - 0.477ms returns 4 (0x4) +T062C 26296:732.133 JLINK_IsHalted() +T062C 26296:733.234 - 1.124ms returns FALSE +T062C 26296:833.430 JLINK_HasError() +T062C 26296:833.537 JLINK_IsHalted() +T062C 26296:834.786 - 1.269ms returns FALSE +T062C 26296:935.555 JLINK_HasError() +T062C 26296:935.627 JLINK_IsHalted() +T062C 26296:936.750 - 1.141ms returns FALSE +T062C 26297:037.646 JLINK_HasError() +T062C 26297:037.679 JLINK_IsHalted() +T062C 26297:038.911 - 1.250ms returns FALSE +T062C 26297:140.090 JLINK_HasError() +T062C 26297:140.162 JLINK_IsHalted() +T062C 26297:141.418 - 1.275ms returns FALSE +T062C 26297:242.379 JLINK_HasError() +T062C 26297:242.451 JLINK_HasError() +T062C 26297:242.495 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26297:242.555 Data: 8D 12 74 01 +T062C 26297:242.610 Debug reg: DWT_CYCCNT +T062C 26297:242.629 - 0.140ms returns 1 (0x1) +T3F74 26297:245.056 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26297:245.088 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26297:246.284 Data: 00 00 80 00 +T3F74 26297:246.365 - 1.328ms returns 4 (0x4) +T3F74 26297:246.426 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26297:246.449 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26297:247.595 Data: 00 00 F0 01 +T3F74 26297:247.673 - 1.267ms returns 4 (0x4) +T3F74 26297:251.239 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26297:251.269 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26297:252.565 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26297:252.594 - 1.362ms returns 16 (0x10) +T3F74 26297:252.615 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26297:252.634 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26297:253.161 Data: 1E 00 00 00 +T3F74 26297:253.181 - 0.573ms returns 4 (0x4) +T3F74 26297:253.199 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26297:253.215 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26297:253.758 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E7 00 00 00 ... +T3F74 26297:253.778 - 0.586ms returns 20 (0x14) +T3F74 26297:253.796 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26297:253.812 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26297:254.264 Data: 1F 03 00 00 +T3F74 26297:254.288 - 0.500ms returns 4 (0x4) +T3F74 26297:254.309 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26297:254.327 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26297:254.763 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26297:254.787 - 0.486ms returns 12 (0xC) +T3F74 26297:254.807 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26297:254.826 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26297:255.269 Data: 00 00 00 00 +T3F74 26297:255.293 - 0.493ms returns 4 (0x4) +T3F74 26297:255.313 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26297:255.332 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26297:255.769 Data: 00 00 00 00 +T3F74 26297:255.789 - 0.482ms returns 4 (0x4) +T3F74 26297:255.806 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26297:255.822 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26297:256.256 Data: 00 00 00 00 +T3F74 26297:256.276 - 0.477ms returns 4 (0x4) +T062C 26297:267.856 JLINK_IsHalted() +T062C 26297:268.906 - 1.068ms returns FALSE +T062C 26297:369.621 JLINK_HasError() +T062C 26297:369.758 JLINK_IsHalted() +T062C 26297:371.167 - 1.452ms returns FALSE +T062C 26297:471.915 JLINK_HasError() +T062C 26297:471.986 JLINK_IsHalted() +T062C 26297:473.116 - 1.137ms returns FALSE +T062C 26297:574.470 JLINK_HasError() +T062C 26297:574.504 JLINK_IsHalted() +T062C 26297:575.599 - 1.115ms returns FALSE +T062C 26297:675.878 JLINK_HasError() +T062C 26297:675.916 JLINK_IsHalted() +T062C 26297:676.993 - 1.101ms returns FALSE +T062C 26297:777.627 JLINK_HasError() +T062C 26297:777.672 JLINK_HasError() +T062C 26297:777.691 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26297:777.721 Data: 8D 12 74 01 +T062C 26297:777.744 Debug reg: DWT_CYCCNT +T062C 26297:777.766 - 0.083ms returns 1 (0x1) +T3F74 26297:780.168 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26297:780.202 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26297:781.334 Data: 00 00 80 00 +T3F74 26297:781.376 - 1.216ms returns 4 (0x4) +T3F74 26297:781.416 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26297:781.439 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26297:781.943 Data: 00 00 F0 01 +T3F74 26297:781.967 - 0.559ms returns 4 (0x4) +T3F74 26297:785.321 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26297:785.349 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26297:786.617 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26297:786.646 - 1.331ms returns 16 (0x10) +T3F74 26297:786.666 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26297:786.686 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26297:787.062 Data: 1E 00 00 00 +T3F74 26297:787.082 - 0.423ms returns 4 (0x4) +T3F74 26297:787.100 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26297:787.116 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26297:787.562 Data: 00 00 00 00 00 00 00 00 00 00 00 00 0B 01 00 00 ... +T3F74 26297:787.582 - 0.489ms returns 20 (0x14) +T3F74 26297:787.599 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26297:787.615 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26297:788.068 Data: 1F 03 00 00 +T3F74 26297:788.092 - 0.500ms returns 4 (0x4) +T3F74 26297:788.112 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26297:788.131 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26297:788.562 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26297:788.585 - 0.481ms returns 12 (0xC) +T3F74 26297:788.606 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26297:788.624 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26297:789.064 Data: 00 00 00 00 +T3F74 26297:789.088 - 0.490ms returns 4 (0x4) +T3F74 26297:789.108 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26297:789.127 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26297:789.562 Data: 00 00 00 00 +T3F74 26297:789.585 - 0.485ms returns 4 (0x4) +T3F74 26297:789.606 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26297:789.624 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26297:790.071 Data: 00 00 00 00 +T3F74 26297:790.095 - 0.497ms returns 4 (0x4) +T062C 26297:801.841 JLINK_IsHalted() +T062C 26297:802.946 - 1.123ms returns FALSE +T062C 26297:903.172 JLINK_HasError() +T062C 26297:903.253 JLINK_IsHalted() +T062C 26297:904.336 - 1.102ms returns FALSE +T062C 26298:004.535 JLINK_HasError() +T062C 26298:004.620 JLINK_IsHalted() +T062C 26298:005.869 - 1.297ms returns FALSE +T062C 26298:106.624 JLINK_HasError() +T062C 26298:106.763 JLINK_IsHalted() +T062C 26298:107.853 - 1.108ms returns FALSE +T062C 26298:208.666 JLINK_HasError() +T062C 26298:208.739 JLINK_IsHalted() +T062C 26298:209.969 - 1.272ms returns FALSE +T062C 26298:310.467 JLINK_HasError() +T062C 26298:310.538 JLINK_HasError() +T062C 26298:310.582 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26298:310.623 Data: 8D 12 74 01 +T062C 26298:310.644 Debug reg: DWT_CYCCNT +T062C 26298:310.662 - 0.086ms returns 1 (0x1) +T3F74 26298:313.618 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26298:313.651 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26298:314.892 Data: 00 00 80 00 +T3F74 26298:314.970 - 1.371ms returns 4 (0x4) +T3F74 26298:315.032 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26298:315.055 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26298:316.224 Data: 00 00 F0 01 +T3F74 26298:316.302 - 1.289ms returns 4 (0x4) +T3F74 26298:319.333 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26298:319.360 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26298:320.545 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26298:320.574 - 1.248ms returns 16 (0x10) +T3F74 26298:320.594 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26298:320.613 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26298:321.019 Data: 1E 00 00 00 +T3F74 26298:321.040 - 0.452ms returns 4 (0x4) +T3F74 26298:321.057 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26298:321.079 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26298:321.700 Data: 00 00 00 00 00 00 00 00 00 00 00 00 6D 02 00 00 ... +T3F74 26298:321.721 - 0.672ms returns 20 (0x14) +T3F74 26298:321.747 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26298:321.767 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26298:322.249 Data: 1F 03 00 00 +T3F74 26298:322.273 - 0.533ms returns 4 (0x4) +T3F74 26298:322.293 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26298:322.312 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26298:322.741 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26298:322.765 - 0.479ms returns 12 (0xC) +T3F74 26298:322.785 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26298:322.804 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26298:323.245 Data: 00 00 00 00 +T3F74 26298:323.269 - 0.492ms returns 4 (0x4) +T3F74 26298:323.294 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26298:323.311 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26298:323.740 Data: 00 00 00 00 +T3F74 26298:323.760 - 0.472ms returns 4 (0x4) +T3F74 26298:323.777 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26298:323.793 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26298:324.239 Data: 00 00 00 00 +T3F74 26298:324.259 - 0.488ms returns 4 (0x4) +T062C 26298:335.538 JLINK_IsHalted() +T062C 26298:336.624 - 1.104ms returns FALSE +T062C 26298:437.471 JLINK_HasError() +T062C 26298:437.561 JLINK_IsHalted() +T062C 26298:438.737 - 1.185ms returns FALSE +T062C 26298:538.896 JLINK_HasError() +T062C 26298:538.967 JLINK_IsHalted() +T062C 26298:540.170 - 1.243ms returns FALSE +T062C 26298:640.911 JLINK_HasError() +T062C 26298:640.942 JLINK_IsHalted() +T062C 26298:641.964 - 1.040ms returns FALSE +T062C 26298:742.049 JLINK_HasError() +T062C 26298:742.089 JLINK_IsHalted() +T062C 26298:743.198 - 1.123ms returns FALSE +T062C 26298:843.394 JLINK_HasError() +T062C 26298:843.481 JLINK_HasError() +T062C 26298:843.525 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26298:843.576 Data: 8D 12 74 01 +T062C 26298:843.597 Debug reg: DWT_CYCCNT +T062C 26298:843.616 - 0.097ms returns 1 (0x1) +T3F74 26298:846.177 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26298:846.209 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26298:847.426 Data: 00 00 80 00 +T3F74 26298:847.461 - 1.292ms returns 4 (0x4) +T3F74 26298:847.530 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26298:847.554 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26298:848.671 Data: 00 00 F0 01 +T3F74 26298:848.692 - 1.168ms returns 4 (0x4) +T3F74 26298:851.668 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26298:851.696 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26298:852.976 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26298:853.004 - 1.343ms returns 16 (0x10) +T3F74 26298:853.025 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26298:853.044 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26298:853.420 Data: 1E 00 00 00 +T3F74 26298:853.440 - 0.422ms returns 4 (0x4) +T3F74 26298:853.457 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26298:853.474 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26298:853.916 Data: 00 00 00 00 00 00 00 00 00 00 00 00 A9 00 00 00 ... +T3F74 26298:853.936 - 0.485ms returns 20 (0x14) +T3F74 26298:853.953 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26298:853.969 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26298:854.435 Data: 1F 03 00 00 +T3F74 26298:854.455 - 0.509ms returns 4 (0x4) +T3F74 26298:854.473 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26298:854.489 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26298:854.918 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26298:854.938 - 0.471ms returns 12 (0xC) +T3F74 26298:854.955 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26298:854.971 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26298:855.490 Data: 00 00 00 00 +T3F74 26298:855.510 - 0.562ms returns 4 (0x4) +T3F74 26298:855.544 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26298:855.578 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26298:856.046 Data: 00 00 00 00 +T3F74 26298:856.069 - 0.533ms returns 4 (0x4) +T3F74 26298:856.090 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26298:856.109 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26298:856.564 Data: 00 00 00 00 +T3F74 26298:856.600 - 0.518ms returns 4 (0x4) +T062C 26298:872.012 JLINK_IsHalted() +T062C 26298:873.198 - 1.210ms returns FALSE +T062C 26298:973.397 JLINK_HasError() +T062C 26298:973.477 JLINK_IsHalted() +T062C 26298:974.688 - 1.253ms returns FALSE +T062C 26299:075.496 JLINK_HasError() +T062C 26299:075.570 JLINK_IsHalted() +T062C 26299:076.764 - 1.214ms returns FALSE +T062C 26299:177.545 JLINK_HasError() +T062C 26299:177.618 JLINK_IsHalted() +T062C 26299:178.760 - 1.160ms returns FALSE +T062C 26299:278.898 JLINK_HasError() +T062C 26299:278.942 JLINK_IsHalted() +T062C 26299:280.112 - 1.211ms returns FALSE +T062C 26299:380.683 JLINK_HasError() +T062C 26299:380.755 JLINK_HasError() +T062C 26299:380.803 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26299:380.832 Data: 8D 12 74 01 +T062C 26299:380.856 Debug reg: DWT_CYCCNT +T062C 26299:380.879 - 0.083ms returns 1 (0x1) +T3F74 26299:383.368 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26299:383.401 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26299:384.572 Data: 00 00 80 00 +T3F74 26299:384.637 - 1.275ms returns 4 (0x4) +T3F74 26299:384.671 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26299:384.691 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26299:385.099 Data: 00 00 F0 01 +T3F74 26299:385.120 - 0.455ms returns 4 (0x4) +T3F74 26299:388.630 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26299:388.658 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26299:389.858 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26299:389.882 - 1.261ms returns 16 (0x10) +T3F74 26299:389.903 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26299:389.923 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26299:390.355 Data: 1E 00 00 00 +T3F74 26299:390.379 - 0.483ms returns 4 (0x4) +T3F74 26299:390.400 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26299:390.419 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26299:390.985 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D3 00 00 00 ... +T3F74 26299:391.009 - 0.616ms returns 20 (0x14) +T3F74 26299:391.029 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26299:391.048 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26299:391.473 Data: 1F 03 00 00 +T3F74 26299:391.494 - 0.471ms returns 4 (0x4) +T3F74 26299:391.511 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26299:391.527 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26299:391.973 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26299:391.992 - 0.488ms returns 12 (0xC) +T3F74 26299:392.009 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26299:392.025 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26299:392.473 Data: 00 00 00 00 +T3F74 26299:392.494 - 0.491ms returns 4 (0x4) +T3F74 26299:392.511 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26299:392.527 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26299:392.972 Data: 00 00 00 00 +T3F74 26299:392.992 - 0.488ms returns 4 (0x4) +T3F74 26299:393.009 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26299:393.025 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26299:393.474 Data: 00 00 00 00 +T3F74 26299:393.494 - 0.491ms returns 4 (0x4) +T062C 26299:404.913 JLINK_IsHalted() +T062C 26299:406.064 - 1.169ms returns FALSE +T062C 26299:506.259 JLINK_HasError() +T062C 26299:506.345 JLINK_IsHalted() +T062C 26299:507.583 - 1.256ms returns FALSE +T062C 26299:608.169 JLINK_HasError() +T062C 26299:608.209 JLINK_IsHalted() +T062C 26299:609.436 - 1.246ms returns FALSE +T062C 26299:710.267 JLINK_HasError() +T062C 26299:710.333 JLINK_IsHalted() +T062C 26299:711.487 - 1.174ms returns FALSE +T062C 26299:811.704 JLINK_HasError() +T062C 26299:811.749 JLINK_IsHalted() +T062C 26299:812.806 - 1.076ms returns FALSE +T062C 26299:913.010 JLINK_HasError() +T062C 26299:913.094 JLINK_HasError() +T062C 26299:913.139 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26299:913.200 Data: 8D 12 74 01 +T062C 26299:913.221 Debug reg: DWT_CYCCNT +T062C 26299:913.240 - 0.107ms returns 1 (0x1) +T3F74 26299:916.048 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26299:916.086 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26299:917.167 Data: 00 00 80 00 +T3F74 26299:917.188 - 1.147ms returns 4 (0x4) +T3F74 26299:917.216 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26299:917.233 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26299:917.654 Data: 00 00 F0 01 +T3F74 26299:917.674 - 0.465ms returns 4 (0x4) +T3F74 26299:920.618 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26299:920.645 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26299:921.835 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26299:921.863 - 1.252ms returns 16 (0x10) +T3F74 26299:921.884 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26299:921.903 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26299:922.280 Data: 1E 00 00 00 +T3F74 26299:922.300 - 0.423ms returns 4 (0x4) +T3F74 26299:922.318 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26299:922.334 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26299:922.778 Data: 00 00 00 00 00 00 00 00 00 00 00 00 2B 02 00 00 ... +T3F74 26299:922.798 - 0.486ms returns 20 (0x14) +T3F74 26299:922.815 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26299:922.831 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26299:923.282 Data: 1F 03 00 00 +T3F74 26299:923.305 - 0.498ms returns 4 (0x4) +T3F74 26299:923.325 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26299:923.345 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26299:923.784 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26299:923.807 - 0.489ms returns 12 (0xC) +T3F74 26299:923.828 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26299:923.846 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26299:924.285 Data: 00 00 00 00 +T3F74 26299:924.308 - 0.488ms returns 4 (0x4) +T3F74 26299:924.329 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26299:924.348 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26299:924.790 Data: 00 00 00 00 +T3F74 26299:924.810 - 0.487ms returns 4 (0x4) +T3F74 26299:924.827 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26299:924.843 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26299:925.272 Data: 00 00 00 00 +T3F74 26299:925.292 - 0.472ms returns 4 (0x4) +T062C 26299:937.318 JLINK_IsHalted() +T062C 26299:938.427 - 1.127ms returns FALSE +T062C 26300:039.208 JLINK_HasError() +T062C 26300:039.284 JLINK_IsHalted() +T062C 26300:040.404 - 1.135ms returns FALSE +T062C 26300:140.548 JLINK_HasError() +T062C 26300:140.621 JLINK_IsHalted() +T062C 26300:141.818 - 1.245ms returns FALSE +T062C 26300:242.123 JLINK_HasError() +T062C 26300:242.195 JLINK_IsHalted() +T062C 26300:243.359 - 1.182ms returns FALSE +T062C 26300:343.569 JLINK_HasError() +T062C 26300:343.642 JLINK_IsHalted() +T062C 26300:344.864 - 1.264ms returns FALSE +T062C 26300:446.220 JLINK_HasError() +T062C 26300:446.305 JLINK_HasError() +T062C 26300:446.350 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26300:446.410 Data: 8D 12 74 01 +T062C 26300:446.468 Debug reg: DWT_CYCCNT +T062C 26300:446.511 - 0.169ms returns 1 (0x1) +T3F74 26300:448.825 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26300:448.857 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26300:449.992 Data: 00 00 80 00 +T3F74 26300:450.029 - 1.212ms returns 4 (0x4) +T3F74 26300:450.075 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26300:450.098 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26300:450.593 Data: 00 00 F0 01 +T3F74 26300:450.613 - 0.545ms returns 4 (0x4) +T3F74 26300:453.615 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26300:453.649 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26300:454.887 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26300:454.915 - 1.307ms returns 16 (0x10) +T3F74 26300:454.936 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26300:454.955 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26300:455.327 Data: 1F 00 00 00 +T3F74 26300:455.348 - 0.418ms returns 4 (0x4) +T3F74 26300:455.365 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26300:455.430 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26300:455.953 Data: 00 00 00 00 00 00 00 00 00 00 00 00 7B 01 00 00 ... +T3F74 26300:455.973 - 0.614ms returns 20 (0x14) +T3F74 26300:455.990 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26300:456.006 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26300:456.458 Data: 1F 03 00 00 +T3F74 26300:456.481 - 0.499ms returns 4 (0x4) +T3F74 26300:456.501 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26300:456.520 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26300:456.984 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26300:457.007 - 0.514ms returns 12 (0xC) +T3F74 26300:457.028 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26300:457.046 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26300:457.464 Data: 00 00 00 00 +T3F74 26300:457.488 - 0.468ms returns 4 (0x4) +T3F74 26300:457.508 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26300:457.527 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26300:457.962 Data: 00 00 00 00 +T3F74 26300:457.986 - 0.485ms returns 4 (0x4) +T3F74 26300:458.006 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26300:458.024 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26300:458.464 Data: 00 00 00 00 +T3F74 26300:458.487 - 0.489ms returns 4 (0x4) +T062C 26300:476.943 JLINK_IsHalted() +T062C 26300:477.968 - 1.044ms returns FALSE +T062C 26300:578.113 JLINK_HasError() +T062C 26300:578.188 JLINK_IsHalted() +T062C 26300:579.446 - 1.306ms returns FALSE +T062C 26300:679.580 JLINK_HasError() +T062C 26300:679.652 JLINK_IsHalted() +T062C 26300:680.886 - 1.276ms returns FALSE +T062C 26300:781.386 JLINK_HasError() +T062C 26300:781.438 JLINK_IsHalted() +T062C 26300:782.669 - 1.248ms returns FALSE +T062C 26300:883.245 JLINK_HasError() +T062C 26300:883.287 JLINK_IsHalted() +T062C 26300:884.499 - 1.231ms returns FALSE +T062C 26300:985.568 JLINK_HasError() +T062C 26300:985.656 JLINK_HasError() +T062C 26300:985.701 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26300:985.769 Data: 8D 12 74 01 +T062C 26300:985.827 Debug reg: DWT_CYCCNT +T062C 26300:985.871 - 0.178ms returns 1 (0x1) +T3F74 26300:988.261 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26300:988.295 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26300:989.540 Data: 00 00 80 00 +T3F74 26300:989.618 - 1.386ms returns 4 (0x4) +T3F74 26300:989.679 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26300:989.702 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26300:991.088 Data: 00 00 F0 01 +T3F74 26300:991.163 - 1.491ms returns 4 (0x4) +T3F74 26300:994.323 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26300:994.350 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26300:995.594 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26300:995.652 - 1.346ms returns 16 (0x10) +T3F74 26300:995.686 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26300:995.721 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26300:996.897 Data: 1E 00 00 00 +T3F74 26300:996.931 - 1.252ms returns 4 (0x4) +T3F74 26300:996.955 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26300:996.977 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26300:997.511 Data: 00 00 00 00 00 00 00 00 00 00 00 00 5F 01 00 00 ... +T3F74 26300:997.535 - 0.588ms returns 20 (0x14) +T3F74 26300:997.555 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26300:997.574 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26300:998.012 Data: 1F 03 00 00 +T3F74 26300:998.046 - 0.499ms returns 4 (0x4) +T3F74 26300:998.067 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26300:998.086 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26300:998.511 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26300:998.535 - 0.476ms returns 12 (0xC) +T3F74 26300:998.555 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26300:998.574 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26300:999.011 Data: 00 00 00 00 +T3F74 26300:999.035 - 0.487ms returns 4 (0x4) +T3F74 26300:999.055 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26300:999.074 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26300:999.510 Data: 00 00 00 00 +T3F74 26300:999.534 - 0.486ms returns 4 (0x4) +T3F74 26300:999.554 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26300:999.573 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26301:000.011 Data: 00 00 00 00 +T3F74 26301:000.034 - 0.488ms returns 4 (0x4) +T062C 26301:020.807 JLINK_IsHalted() +T062C 26301:021.894 - 1.105ms returns FALSE +T062C 26301:122.358 JLINK_HasError() +T062C 26301:122.438 JLINK_IsHalted() +T062C 26301:123.648 - 1.252ms returns FALSE +T062C 26301:223.933 JLINK_HasError() +T062C 26301:224.004 JLINK_IsHalted() +T062C 26301:225.225 - 1.269ms returns FALSE +T062C 26301:325.456 JLINK_HasError() +T062C 26301:325.536 JLINK_IsHalted() +T062C 26301:326.841 - 1.322ms returns FALSE +T062C 26301:427.127 JLINK_HasError() +T062C 26301:427.201 JLINK_IsHalted() +T062C 26301:428.417 - 1.258ms returns FALSE +T062C 26301:529.539 JLINK_HasError() +T062C 26301:529.613 JLINK_HasError() +T062C 26301:529.658 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26301:529.725 Data: 8D 12 74 01 +T062C 26301:529.783 Debug reg: DWT_CYCCNT +T062C 26301:529.833 - 0.183ms returns 1 (0x1) +T3F74 26301:532.178 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26301:532.212 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26301:533.335 Data: 00 00 80 00 +T3F74 26301:533.370 - 1.200ms returns 4 (0x4) +T3F74 26301:533.414 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26301:533.437 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26301:533.944 Data: 00 00 F0 01 +T3F74 26301:533.968 - 0.562ms returns 4 (0x4) +T3F74 26301:536.978 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26301:537.005 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26301:538.238 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26301:538.267 - 1.295ms returns 16 (0x10) +T3F74 26301:538.287 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26301:538.306 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26301:538.689 Data: 1E 00 00 00 +T3F74 26301:538.713 - 0.434ms returns 4 (0x4) +T3F74 26301:538.733 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26301:538.752 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26301:539.315 Data: 00 00 00 00 00 00 00 00 00 00 00 00 4F 00 00 00 ... +T3F74 26301:539.338 - 0.612ms returns 20 (0x14) +T3F74 26301:539.358 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26301:539.377 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26301:539.814 Data: 1F 03 00 00 +T3F74 26301:539.837 - 0.486ms returns 4 (0x4) +T3F74 26301:539.857 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26301:539.876 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26301:540.308 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26301:540.328 - 0.477ms returns 12 (0xC) +T3F74 26301:540.345 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26301:540.361 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26301:540.826 Data: 00 00 00 00 +T3F74 26301:540.861 - 0.524ms returns 4 (0x4) +T3F74 26301:540.887 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26301:540.910 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26301:541.306 Data: 00 00 00 00 +T3F74 26301:541.335 - 0.456ms returns 4 (0x4) +T3F74 26301:541.358 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26301:541.378 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26301:541.955 Data: 00 00 00 00 +T3F74 26301:541.979 - 0.629ms returns 4 (0x4) +T062C 26301:553.320 JLINK_IsHalted() +T062C 26301:554.447 - 1.145ms returns FALSE +T062C 26301:654.597 JLINK_HasError() +T062C 26301:654.682 JLINK_IsHalted() +T062C 26301:655.891 - 1.225ms returns FALSE +T062C 26301:756.087 JLINK_HasError() +T062C 26301:756.163 JLINK_IsHalted() +T062C 26301:757.433 - 1.292ms returns FALSE +T062C 26301:857.572 JLINK_HasError() +T062C 26301:857.645 JLINK_IsHalted() +T062C 26301:858.917 - 1.314ms returns FALSE +T062C 26301:959.910 JLINK_HasError() +T062C 26301:959.978 JLINK_IsHalted() +T062C 26301:961.036 - 1.077ms returns FALSE +T062C 26302:061.851 JLINK_HasError() +T062C 26302:061.937 JLINK_HasError() +T062C 26302:061.956 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26302:061.986 Data: 8D 12 74 01 +T062C 26302:062.010 Debug reg: DWT_CYCCNT +T062C 26302:062.032 - 0.083ms returns 1 (0x1) +T3F74 26302:064.629 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26302:064.668 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26302:065.850 Data: 00 00 80 00 +T3F74 26302:065.931 - 1.322ms returns 4 (0x4) +T3F74 26302:066.021 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26302:066.069 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26302:067.265 Data: 00 00 F0 01 +T3F74 26302:067.344 - 1.342ms returns 4 (0x4) +T3F74 26302:070.962 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26302:071.000 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26302:072.339 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26302:072.411 - 1.456ms returns 16 (0x10) +T3F74 26302:072.435 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26302:072.458 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26302:072.868 Data: 1F 00 00 00 +T3F74 26302:072.892 - 0.465ms returns 4 (0x4) +T3F74 26302:072.912 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26302:072.931 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26302:073.488 Data: 00 00 00 00 00 00 00 00 00 00 00 00 EF 00 00 00 ... +T3F74 26302:073.508 - 0.602ms returns 20 (0x14) +T3F74 26302:073.525 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26302:073.541 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26302:074.001 Data: 1F 03 00 00 +T3F74 26302:074.025 - 0.508ms returns 4 (0x4) +T3F74 26302:074.045 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26302:074.064 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26302:074.499 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26302:074.522 - 0.485ms returns 12 (0xC) +T3F74 26302:074.543 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26302:074.561 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26302:075.150 Data: 00 00 00 00 +T3F74 26302:075.187 - 0.652ms returns 4 (0x4) +T3F74 26302:075.212 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26302:075.234 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26302:076.379 Data: 00 00 00 00 +T3F74 26302:076.413 - 1.209ms returns 4 (0x4) +T3F74 26302:076.437 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26302:076.459 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26302:076.874 Data: 00 00 00 00 +T3F74 26302:076.898 - 0.469ms returns 4 (0x4) +T062C 26302:096.740 JLINK_IsHalted() +T062C 26302:097.906 - 1.185ms returns FALSE +T062C 26302:198.092 JLINK_HasError() +T062C 26302:198.170 JLINK_IsHalted() +T062C 26302:199.346 - 1.219ms returns FALSE +T062C 26302:300.078 JLINK_HasError() +T062C 26302:300.105 JLINK_IsHalted() +T062C 26302:301.217 - 1.162ms returns FALSE +T062C 26302:401.465 JLINK_HasError() +T062C 26302:401.537 JLINK_IsHalted() +T062C 26302:402.816 - 1.297ms returns FALSE +T062C 26302:502.936 JLINK_HasError() +T062C 26302:502.977 JLINK_IsHalted() +T062C 26302:504.182 - 1.223ms returns FALSE +T062C 26302:604.963 JLINK_HasError() +T062C 26302:605.039 JLINK_HasError() +T062C 26302:605.057 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26302:605.086 Data: 8D 12 74 01 +T062C 26302:605.109 Debug reg: DWT_CYCCNT +T062C 26302:605.142 - 0.093ms returns 1 (0x1) +T3F74 26302:607.502 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26302:607.534 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26302:608.571 Data: 00 00 80 00 +T3F74 26302:608.609 - 1.115ms returns 4 (0x4) +T3F74 26302:608.653 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26302:608.677 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26302:609.185 Data: 00 00 F0 01 +T3F74 26302:609.212 - 0.566ms returns 4 (0x4) +T3F74 26302:612.823 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26302:612.851 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26302:614.079 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26302:614.111 - 1.297ms returns 16 (0x10) +T3F74 26302:614.135 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26302:614.158 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26302:614.546 Data: 1E 00 00 00 +T3F74 26302:614.566 - 0.437ms returns 4 (0x4) +T3F74 26302:614.583 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26302:614.600 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26302:615.044 Data: 00 00 00 00 00 00 00 00 00 00 00 00 2F 02 00 00 ... +T3F74 26302:615.064 - 0.487ms returns 20 (0x14) +T3F74 26302:615.081 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26302:615.097 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26302:615.545 Data: 1F 03 00 00 +T3F74 26302:615.565 - 0.490ms returns 4 (0x4) +T3F74 26302:615.582 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26302:615.598 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26302:616.044 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26302:616.063 - 0.488ms returns 12 (0xC) +T3F74 26302:616.080 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26302:616.096 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26302:616.544 Data: 00 00 00 00 +T3F74 26302:616.564 - 0.490ms returns 4 (0x4) +T3F74 26302:616.581 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26302:616.597 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26302:617.043 Data: 00 00 00 00 +T3F74 26302:617.063 - 0.489ms returns 4 (0x4) +T3F74 26302:617.080 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26302:617.096 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26302:617.544 Data: 00 00 00 00 +T3F74 26302:617.564 - 0.490ms returns 4 (0x4) +T062C 26302:636.408 JLINK_IsHalted() +T062C 26302:637.459 - 1.070ms returns FALSE +T062C 26302:737.646 JLINK_HasError() +T062C 26302:737.728 JLINK_IsHalted() +T062C 26302:738.920 - 1.235ms returns FALSE +T062C 26302:839.761 JLINK_HasError() +T062C 26302:839.835 JLINK_IsHalted() +T062C 26302:841.006 - 1.189ms returns FALSE +T062C 26302:942.025 JLINK_HasError() +T062C 26302:942.070 JLINK_IsHalted() +T062C 26302:943.189 - 1.141ms returns FALSE +T062C 26303:044.006 JLINK_HasError() +T062C 26303:044.056 JLINK_IsHalted() +T062C 26303:045.132 - 1.095ms returns FALSE +T062C 26303:146.075 JLINK_HasError() +T062C 26303:146.163 JLINK_HasError() +T062C 26303:146.181 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26303:146.212 Data: 8D 12 74 01 +T062C 26303:146.236 Debug reg: DWT_CYCCNT +T062C 26303:146.258 - 0.084ms returns 1 (0x1) +T3F74 26303:148.940 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26303:148.983 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26303:150.143 Data: 00 00 80 00 +T3F74 26303:150.186 - 1.254ms returns 4 (0x4) +T3F74 26303:150.227 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26303:150.250 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26303:150.735 Data: 00 00 F0 01 +T3F74 26303:150.759 - 0.539ms returns 4 (0x4) +T3F74 26303:154.326 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26303:154.357 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26303:155.645 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26303:155.677 - 1.359ms returns 16 (0x10) +T3F74 26303:155.702 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26303:155.725 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26303:156.235 Data: 1E 00 00 00 +T3F74 26303:156.260 - 0.565ms returns 4 (0x4) +T3F74 26303:156.280 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26303:156.300 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26303:156.884 Data: 00 00 00 00 00 00 00 00 00 00 00 00 2F 01 00 00 ... +T3F74 26303:156.910 - 0.637ms returns 20 (0x14) +T3F74 26303:156.931 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26303:156.951 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26303:157.495 Data: 1F 03 00 00 +T3F74 26303:157.518 - 0.595ms returns 4 (0x4) +T3F74 26303:157.539 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26303:157.557 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26303:157.992 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26303:158.023 - 0.519ms returns 12 (0xC) +T3F74 26303:158.074 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26303:158.101 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26303:158.608 Data: 00 00 00 00 +T3F74 26303:158.643 - 0.577ms returns 4 (0x4) +T3F74 26303:158.669 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26303:158.690 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26303:159.099 Data: 00 00 00 00 +T3F74 26303:159.122 - 0.461ms returns 4 (0x4) +T3F74 26303:159.143 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26303:159.161 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26303:159.725 Data: 00 00 00 00 +T3F74 26303:159.748 - 0.613ms returns 4 (0x4) +T062C 26303:172.821 JLINK_IsHalted() +T062C 26303:173.870 - 1.067ms returns FALSE +T062C 26303:274.158 JLINK_HasError() +T062C 26303:274.207 JLINK_IsHalted() +T062C 26303:275.249 - 1.053ms returns FALSE +T062C 26303:376.073 JLINK_HasError() +T062C 26303:376.120 JLINK_IsHalted() +T062C 26303:377.267 - 1.165ms returns FALSE +T062C 26303:478.008 JLINK_HasError() +T062C 26303:478.065 JLINK_IsHalted() +T062C 26303:479.243 - 1.219ms returns FALSE +T062C 26303:580.014 JLINK_HasError() +T062C 26303:580.060 JLINK_IsHalted() +T062C 26303:581.186 - 1.140ms returns FALSE +T062C 26303:681.888 JLINK_HasError() +T062C 26303:681.950 JLINK_HasError() +T062C 26303:681.968 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26303:681.998 Data: 8D 12 74 01 +T062C 26303:682.021 Debug reg: DWT_CYCCNT +T062C 26303:682.043 - 0.083ms returns 1 (0x1) +T3F74 26303:684.598 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26303:684.637 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26303:685.734 Data: 00 00 80 00 +T3F74 26303:685.770 - 1.179ms returns 4 (0x4) +T3F74 26303:685.809 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26303:685.832 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26303:686.281 Data: 00 00 F0 01 +T3F74 26303:686.305 - 0.504ms returns 4 (0x4) +T3F74 26303:689.775 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26303:689.806 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26303:691.042 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26303:691.074 - 1.307ms returns 16 (0x10) +T3F74 26303:691.098 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26303:691.121 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26303:691.528 Data: 1E 00 00 00 +T3F74 26303:691.552 - 0.462ms returns 4 (0x4) +T3F74 26303:691.573 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26303:691.592 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26303:692.153 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1D 02 00 00 ... +T3F74 26303:692.177 - 0.611ms returns 20 (0x14) +T3F74 26303:692.197 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26303:692.216 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26303:692.653 Data: 1F 03 00 00 +T3F74 26303:692.676 - 0.489ms returns 4 (0x4) +T3F74 26303:692.699 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26303:692.718 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26303:693.278 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26303:693.314 - 0.623ms returns 12 (0xC) +T3F74 26303:693.340 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26303:693.374 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26303:693.781 Data: 00 00 00 00 +T3F74 26303:693.809 - 0.476ms returns 4 (0x4) +T3F74 26303:693.831 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26303:693.851 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26303:694.279 Data: 00 00 00 00 +T3F74 26303:694.303 - 0.480ms returns 4 (0x4) +T3F74 26303:694.323 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26303:694.342 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26303:694.778 Data: 00 00 00 00 +T3F74 26303:694.801 - 0.486ms returns 4 (0x4) +T062C 26303:707.277 JLINK_IsHalted() +T062C 26303:708.422 - 1.164ms returns FALSE +T062C 26303:808.618 JLINK_HasError() +T062C 26303:808.664 JLINK_IsHalted() +T062C 26303:809.840 - 1.204ms returns FALSE +T062C 26303:910.590 JLINK_HasError() +T062C 26303:910.639 JLINK_IsHalted() +T062C 26303:911.794 - 1.173ms returns FALSE +T062C 26304:012.646 JLINK_HasError() +T062C 26304:012.693 JLINK_IsHalted() +T062C 26304:013.767 - 1.092ms returns FALSE +T062C 26304:114.517 JLINK_HasError() +T062C 26304:114.566 JLINK_IsHalted() +T062C 26304:115.685 - 1.153ms returns FALSE +T062C 26304:216.545 JLINK_HasError() +T062C 26304:216.614 JLINK_HasError() +T062C 26304:216.640 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26304:216.686 Data: 8D 12 74 01 +T062C 26304:216.718 Debug reg: DWT_CYCCNT +T062C 26304:216.748 - 0.118ms returns 1 (0x1) +T3F74 26304:221.501 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26304:221.642 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26304:222.964 Data: 00 00 80 00 +T3F74 26304:223.035 - 1.548ms returns 4 (0x4) +T3F74 26304:223.169 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26304:223.229 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26304:224.382 Data: 00 00 F0 01 +T3F74 26304:224.428 - 1.268ms returns 4 (0x4) +T3F74 26304:228.919 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26304:228.966 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26304:230.303 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26304:230.382 - 1.470ms returns 16 (0x10) +T3F74 26304:230.406 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26304:230.429 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26304:230.832 Data: 1E 00 00 00 +T3F74 26304:230.856 - 0.458ms returns 4 (0x4) +T3F74 26304:230.877 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26304:230.896 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26304:231.457 Data: 00 00 00 00 00 00 00 00 00 00 00 00 13 00 00 00 ... +T3F74 26304:231.480 - 0.613ms returns 20 (0x14) +T3F74 26304:231.510 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26304:231.530 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26304:231.956 Data: 1F 03 00 00 +T3F74 26304:231.980 - 0.477ms returns 4 (0x4) +T3F74 26304:232.000 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26304:232.019 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26304:232.457 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26304:232.481 - 0.490ms returns 12 (0xC) +T3F74 26304:232.502 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26304:232.521 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26304:232.956 Data: 00 00 00 00 +T3F74 26304:232.979 - 0.485ms returns 4 (0x4) +T3F74 26304:232.999 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26304:233.018 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26304:233.455 Data: 00 00 00 00 +T3F74 26304:233.478 - 0.486ms returns 4 (0x4) +T3F74 26304:233.500 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26304:233.519 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26304:233.956 Data: 00 00 00 00 +T3F74 26304:233.979 - 0.487ms returns 4 (0x4) +T062C 26304:247.343 JLINK_IsHalted() +T062C 26304:248.464 - 1.143ms returns FALSE +T062C 26304:348.618 JLINK_HasError() +T062C 26304:348.659 JLINK_IsHalted() +T062C 26304:349.727 - 1.102ms returns FALSE +T062C 26304:450.698 JLINK_HasError() +T062C 26304:450.781 JLINK_IsHalted() +T062C 26304:451.818 - 1.057ms returns FALSE +T062C 26304:552.581 JLINK_HasError() +T062C 26304:552.629 JLINK_IsHalted() +T062C 26304:553.710 - 1.095ms returns FALSE +T062C 26304:654.329 JLINK_HasError() +T062C 26304:654.416 JLINK_IsHalted() +T062C 26304:655.542 - 1.144ms returns FALSE +T062C 26304:756.310 JLINK_HasError() +T062C 26304:756.360 JLINK_HasError() +T062C 26304:756.379 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26304:756.409 Data: 8D 12 74 01 +T062C 26304:756.433 Debug reg: DWT_CYCCNT +T062C 26304:756.455 - 0.084ms returns 1 (0x1) +T3F74 26304:760.978 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26304:761.017 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26304:762.201 Data: 00 00 80 00 +T3F74 26304:762.234 - 1.264ms returns 4 (0x4) +T3F74 26304:762.289 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26304:762.315 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26304:762.766 Data: 00 00 F0 01 +T3F74 26304:762.789 - 0.508ms returns 4 (0x4) +T3F74 26304:766.289 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26304:766.320 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26304:767.525 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26304:767.558 - 1.277ms returns 16 (0x10) +T3F74 26304:767.581 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26304:767.604 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26304:768.009 Data: 1F 00 00 00 +T3F74 26304:768.033 - 0.460ms returns 4 (0x4) +T3F74 26304:768.054 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26304:768.073 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26304:768.637 Data: 00 00 00 00 00 00 00 00 00 00 00 00 9F 01 00 00 ... +T3F74 26304:768.661 - 0.615ms returns 20 (0x14) +T3F74 26304:768.681 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26304:768.700 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26304:769.134 Data: 1F 03 00 00 +T3F74 26304:769.158 - 0.484ms returns 4 (0x4) +T3F74 26304:769.178 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26304:769.206 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26304:769.771 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26304:769.808 - 0.638ms returns 12 (0xC) +T3F74 26304:769.835 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26304:769.858 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26304:770.263 Data: 00 00 00 00 +T3F74 26304:770.292 - 0.465ms returns 4 (0x4) +T3F74 26304:770.314 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26304:770.335 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26304:770.760 Data: 00 00 00 00 +T3F74 26304:770.784 - 0.478ms returns 4 (0x4) +T3F74 26304:770.804 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26304:770.823 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26304:771.258 Data: 00 00 00 00 +T3F74 26304:771.282 - 0.485ms returns 4 (0x4) +T062C 26304:792.488 JLINK_IsHalted() +T062C 26304:793.580 - 1.113ms returns FALSE +T062C 26304:893.870 JLINK_HasError() +T062C 26304:893.924 JLINK_IsHalted() +T062C 26304:895.038 - 1.135ms returns FALSE +T062C 26304:995.916 JLINK_HasError() +T062C 26304:996.002 JLINK_IsHalted() +T062C 26304:997.176 - 1.193ms returns FALSE +T062C 26305:097.966 JLINK_HasError() +T062C 26305:098.050 JLINK_IsHalted() +T062C 26305:099.107 - 1.076ms returns FALSE +T062C 26305:199.958 JLINK_HasError() +T062C 26305:200.059 JLINK_IsHalted() +T062C 26305:201.265 - 1.246ms returns FALSE +T062C 26305:301.859 JLINK_HasError() +T062C 26305:301.911 JLINK_HasError() +T062C 26305:301.930 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26305:301.959 Data: 8D 12 74 01 +T062C 26305:301.983 Debug reg: DWT_CYCCNT +T062C 26305:302.004 - 0.082ms returns 1 (0x1) +T3F74 26305:304.555 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26305:304.593 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26305:305.712 Data: 00 00 80 00 +T3F74 26305:305.744 - 1.196ms returns 4 (0x4) +T3F74 26305:305.782 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26305:305.813 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26305:306.321 Data: 00 00 F0 01 +T3F74 26305:306.345 - 0.571ms returns 4 (0x4) +T3F74 26305:309.380 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26305:309.407 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26305:310.589 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26305:310.619 - 1.247ms returns 16 (0x10) +T3F74 26305:310.642 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26305:310.663 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26305:311.068 Data: 1E 00 00 00 +T3F74 26305:311.092 - 0.458ms returns 4 (0x4) +T3F74 26305:311.112 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26305:311.132 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26305:311.695 Data: 00 00 00 00 00 00 00 00 00 00 00 00 87 02 00 00 ... +T3F74 26305:311.719 - 0.614ms returns 20 (0x14) +T3F74 26305:311.739 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26305:311.758 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26305:312.191 Data: 1F 03 00 00 +T3F74 26305:312.217 - 0.486ms returns 4 (0x4) +T3F74 26305:312.238 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26305:312.259 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26305:312.689 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26305:312.713 - 0.482ms returns 12 (0xC) +T3F74 26305:312.733 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26305:312.752 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26305:313.187 Data: 00 00 00 00 +T3F74 26305:313.210 - 0.484ms returns 4 (0x4) +T3F74 26305:313.230 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26305:313.249 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26305:313.714 Data: 00 00 00 00 +T3F74 26305:313.738 - 0.515ms returns 4 (0x4) +T3F74 26305:313.758 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26305:313.776 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26305:314.186 Data: 00 00 00 00 +T3F74 26305:314.209 - 0.459ms returns 4 (0x4) +T062C 26305:335.124 JLINK_IsHalted() +T062C 26305:336.202 - 1.101ms returns FALSE +T062C 26305:436.890 JLINK_HasError() +T062C 26305:436.933 JLINK_IsHalted() +T062C 26305:438.078 - 1.163ms returns FALSE +T062C 26305:538.848 JLINK_HasError() +T062C 26305:538.902 JLINK_IsHalted() +T062C 26305:539.945 - 1.059ms returns FALSE +T062C 26305:640.671 JLINK_HasError() +T062C 26305:640.757 JLINK_IsHalted() +T062C 26305:641.786 - 1.046ms returns FALSE +T062C 26305:742.731 JLINK_HasError() +T062C 26305:742.832 JLINK_IsHalted() +T062C 26305:743.897 - 1.076ms returns FALSE +T062C 26305:844.036 JLINK_HasError() +T062C 26305:844.123 JLINK_HasError() +T062C 26305:844.142 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26305:844.171 Data: 8D 12 74 01 +T062C 26305:844.195 Debug reg: DWT_CYCCNT +T062C 26305:844.217 - 0.083ms returns 1 (0x1) +T3F74 26305:846.860 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26305:846.902 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26305:848.062 Data: 00 00 80 00 +T3F74 26305:848.098 - 1.246ms returns 4 (0x4) +T3F74 26305:848.137 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26305:848.160 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26305:848.617 Data: 00 00 F0 01 +T3F74 26305:848.641 - 0.512ms returns 4 (0x4) +T3F74 26305:852.084 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26305:852.116 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26305:853.253 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26305:853.286 - 1.209ms returns 16 (0x10) +T3F74 26305:853.310 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26305:853.333 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26305:853.741 Data: 1E 00 00 00 +T3F74 26305:853.765 - 0.463ms returns 4 (0x4) +T3F74 26305:853.785 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26305:853.805 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26305:854.378 Data: 00 00 00 00 00 00 00 00 00 00 00 00 69 01 00 00 ... +T3F74 26305:854.413 - 0.776ms returns 20 (0x14) +T3F74 26305:854.581 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26305:854.604 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26305:855.778 Data: 1F 03 00 00 +T3F74 26305:855.834 - 1.261ms returns 4 (0x4) +T3F74 26305:855.857 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26305:855.880 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26305:856.366 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26305:856.389 - 0.540ms returns 12 (0xC) +T3F74 26305:856.469 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26305:856.488 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26305:856.866 Data: 00 00 00 00 +T3F74 26305:856.891 - 0.429ms returns 4 (0x4) +T3F74 26305:856.911 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26305:856.930 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26305:857.365 Data: 00 00 00 00 +T3F74 26305:857.388 - 0.484ms returns 4 (0x4) +T3F74 26305:857.408 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26305:857.427 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26305:857.865 Data: 00 00 00 00 +T3F74 26305:857.900 - 0.500ms returns 4 (0x4) +T062C 26305:870.768 JLINK_IsHalted() +T062C 26305:871.931 - 1.183ms returns FALSE +T062C 26305:972.908 JLINK_HasError() +T062C 26305:972.954 JLINK_IsHalted() +T062C 26305:974.001 - 1.059ms returns FALSE +T062C 26306:074.908 JLINK_HasError() +T062C 26306:074.957 JLINK_IsHalted() +T062C 26306:075.980 - 1.035ms returns FALSE +T062C 26306:176.929 JLINK_HasError() +T062C 26306:176.981 JLINK_IsHalted() +T062C 26306:178.106 - 1.157ms returns FALSE +T062C 26306:279.025 JLINK_HasError() +T062C 26306:279.072 JLINK_IsHalted() +T062C 26306:280.173 - 1.135ms returns FALSE +T062C 26306:381.894 JLINK_HasError() +T062C 26306:381.974 JLINK_HasError() +T062C 26306:381.993 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26306:382.023 Data: 8D 12 74 01 +T062C 26306:382.050 Debug reg: DWT_CYCCNT +T062C 26306:382.072 - 0.086ms returns 1 (0x1) +T3F74 26306:384.546 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26306:384.578 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26306:385.760 Data: 00 00 80 00 +T3F74 26306:385.795 - 1.257ms returns 4 (0x4) +T3F74 26306:385.837 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26306:385.861 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26306:386.298 Data: 00 00 F0 01 +T3F74 26306:386.318 - 0.488ms returns 4 (0x4) +T3F74 26306:389.369 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26306:389.396 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26306:390.600 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26306:390.628 - 1.266ms returns 16 (0x10) +T3F74 26306:390.649 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26306:390.668 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26306:391.045 Data: 1E 00 00 00 +T3F74 26306:391.065 - 0.423ms returns 4 (0x4) +T3F74 26306:391.083 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26306:391.099 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26306:391.546 Data: 00 00 00 00 00 00 00 00 00 00 00 00 89 00 00 00 ... +T3F74 26306:391.566 - 0.489ms returns 20 (0x14) +T3F74 26306:391.583 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26306:391.599 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26306:392.046 Data: 1F 03 00 00 +T3F74 26306:392.066 - 0.489ms returns 4 (0x4) +T3F74 26306:392.083 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26306:392.099 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26306:392.573 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26306:392.593 - 0.516ms returns 12 (0xC) +T3F74 26306:392.610 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26306:392.626 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26306:393.044 Data: 00 00 00 00 +T3F74 26306:393.064 - 0.461ms returns 4 (0x4) +T3F74 26306:393.081 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26306:393.097 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26306:393.538 Data: 00 00 00 00 +T3F74 26306:393.636 - 0.561ms returns 4 (0x4) +T3F74 26306:393.654 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26306:393.670 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26306:394.038 Data: 00 00 00 00 +T3F74 26306:394.058 - 0.411ms returns 4 (0x4) +T062C 26306:405.870 JLINK_IsHalted() +T062C 26306:406.925 - 1.069ms returns FALSE +T062C 26306:507.398 JLINK_HasError() +T062C 26306:507.443 JLINK_IsHalted() +T062C 26306:508.619 - 1.195ms returns FALSE +T062C 26306:609.228 JLINK_HasError() +T062C 26306:609.265 JLINK_IsHalted() +T062C 26306:610.466 - 1.226ms returns FALSE +T062C 26306:711.440 JLINK_HasError() +T062C 26306:711.513 JLINK_IsHalted() +T062C 26306:712.750 - 1.286ms returns FALSE +T062C 26306:813.497 JLINK_HasError() +T062C 26306:813.542 JLINK_IsHalted() +T062C 26306:814.731 - 1.207ms returns FALSE +T062C 26306:915.017 JLINK_HasError() +T062C 26306:915.093 JLINK_HasError() +T062C 26306:915.118 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26306:915.143 Data: 8D 12 74 01 +T062C 26306:915.164 Debug reg: DWT_CYCCNT +T062C 26306:915.183 - 0.071ms returns 1 (0x1) +T3F74 26306:917.644 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26306:917.676 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26306:918.827 Data: 00 00 80 00 +T3F74 26306:918.910 - 1.286ms returns 4 (0x4) +T3F74 26306:918.976 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26306:918.999 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26306:920.299 Data: 00 00 F0 01 +T3F74 26306:920.377 - 1.418ms returns 4 (0x4) +T3F74 26306:923.667 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26306:923.698 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26306:924.903 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26306:924.931 - 1.271ms returns 16 (0x10) +T3F74 26306:924.952 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26306:924.971 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26306:925.342 Data: 1E 00 00 00 +T3F74 26306:925.362 - 0.417ms returns 4 (0x4) +T3F74 26306:925.380 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26306:925.396 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26306:925.842 Data: 00 00 00 00 00 00 00 00 00 00 00 00 DD 01 00 00 ... +T3F74 26306:925.862 - 0.489ms returns 20 (0x14) +T3F74 26306:925.879 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26306:925.895 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26306:926.343 Data: 1F 03 00 00 +T3F74 26306:926.363 - 0.490ms returns 4 (0x4) +T3F74 26306:926.380 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26306:926.396 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26306:926.842 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26306:926.861 - 0.488ms returns 12 (0xC) +T3F74 26306:926.878 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26306:926.894 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26306:927.364 Data: 00 00 00 00 +T3F74 26306:927.400 - 0.530ms returns 4 (0x4) +T3F74 26306:927.426 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26306:927.448 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26306:927.856 Data: 00 00 00 00 +T3F74 26306:927.885 - 0.467ms returns 4 (0x4) +T3F74 26306:927.907 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26306:927.930 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26306:928.354 Data: 00 00 00 00 +T3F74 26306:928.378 - 0.478ms returns 4 (0x4) +T062C 26306:939.884 JLINK_IsHalted() +T062C 26306:940.980 - 1.111ms returns FALSE +T062C 26307:041.519 JLINK_HasError() +T062C 26307:041.606 JLINK_IsHalted() +T062C 26307:042.722 - 1.134ms returns FALSE +T062C 26307:143.484 JLINK_HasError() +T062C 26307:143.574 JLINK_IsHalted() +T062C 26307:144.791 - 1.259ms returns FALSE +T062C 26307:245.521 JLINK_HasError() +T062C 26307:245.610 JLINK_IsHalted() +T062C 26307:246.696 - 1.107ms returns FALSE +T062C 26307:347.431 JLINK_HasError() +T062C 26307:347.509 JLINK_IsHalted() +T062C 26307:348.743 - 1.258ms returns FALSE +T062C 26307:449.441 JLINK_HasError() +T062C 26307:449.690 JLINK_HasError() +T062C 26307:449.716 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26307:449.763 Data: 8D 12 74 01 +T062C 26307:449.794 Debug reg: DWT_CYCCNT +T062C 26307:449.825 - 0.119ms returns 1 (0x1) +T3F74 26307:453.982 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26307:454.063 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26307:455.185 Data: 00 00 80 00 +T3F74 26307:455.242 - 1.270ms returns 4 (0x4) +T3F74 26307:455.306 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26307:455.339 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26307:455.783 Data: 00 00 F0 01 +T3F74 26307:455.810 - 0.512ms returns 4 (0x4) +T3F74 26307:459.718 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26307:459.751 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26307:460.907 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26307:460.935 - 1.225ms returns 16 (0x10) +T3F74 26307:460.959 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26307:460.980 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26307:461.412 Data: 1F 00 00 00 +T3F74 26307:461.437 - 0.486ms returns 4 (0x4) +T3F74 26307:461.458 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26307:461.478 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26307:462.029 Data: 00 00 00 00 00 00 00 00 00 00 00 00 CF 01 00 00 ... +T3F74 26307:462.054 - 0.604ms returns 20 (0x14) +T3F74 26307:462.075 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26307:462.095 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26307:462.529 Data: 1F 03 00 00 +T3F74 26307:462.554 - 0.487ms returns 4 (0x4) +T3F74 26307:462.575 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26307:462.594 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26307:463.029 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26307:463.053 - 0.486ms returns 12 (0xC) +T3F74 26307:463.074 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26307:463.094 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26307:463.530 Data: 00 00 00 00 +T3F74 26307:463.556 - 0.489ms returns 4 (0x4) +T3F74 26307:463.577 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26307:463.596 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26307:464.080 Data: 00 00 00 00 +T3F74 26307:464.104 - 0.536ms returns 4 (0x4) +T3F74 26307:464.125 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26307:464.145 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26307:464.528 Data: 00 00 00 00 +T3F74 26307:464.553 - 0.436ms returns 4 (0x4) +T062C 26307:488.924 JLINK_IsHalted() +T062C 26307:490.038 - 1.129ms returns FALSE +T062C 26307:590.476 JLINK_HasError() +T062C 26307:590.529 JLINK_IsHalted() +T062C 26307:591.752 - 1.242ms returns FALSE +T062C 26307:692.355 JLINK_HasError() +T062C 26307:692.404 JLINK_IsHalted() +T062C 26307:693.533 - 1.157ms returns FALSE +T062C 26307:794.107 JLINK_HasError() +T062C 26307:794.193 JLINK_IsHalted() +T062C 26307:795.253 - 1.078ms returns FALSE +T062C 26307:896.069 JLINK_HasError() +T062C 26307:896.210 JLINK_IsHalted() +T062C 26307:897.364 - 1.172ms returns FALSE +T062C 26307:998.005 JLINK_HasError() +T062C 26307:998.082 JLINK_HasError() +T062C 26307:998.105 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26307:998.185 Data: 8D 12 74 01 +T062C 26307:998.218 Debug reg: DWT_CYCCNT +T062C 26307:998.269 - 0.175ms returns 1 (0x1) +T3F74 26308:001.631 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26308:001.691 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26308:002.898 Data: 00 00 80 00 +T3F74 26308:002.957 - 1.337ms returns 4 (0x4) +T3F74 26308:003.019 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26308:003.051 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26308:004.246 Data: 00 00 F0 01 +T3F74 26308:004.284 - 1.275ms returns 4 (0x4) +T3F74 26308:009.286 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26308:009.349 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26308:010.632 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26308:010.677 - 1.401ms returns 16 (0x10) +T3F74 26308:010.706 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26308:010.733 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26308:011.239 Data: 1F 00 00 00 +T3F74 26308:011.273 - 0.577ms returns 4 (0x4) +T3F74 26308:011.301 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26308:011.327 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26308:011.859 Data: 00 00 00 00 00 00 00 00 00 00 00 00 8F 01 00 00 ... +T3F74 26308:011.891 - 0.599ms returns 20 (0x14) +T3F74 26308:011.916 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26308:011.941 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26308:012.481 Data: 1F 03 00 00 +T3F74 26308:012.511 - 0.605ms returns 4 (0x4) +T3F74 26308:012.537 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26308:012.562 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26308:013.112 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26308:013.146 - 0.618ms returns 12 (0xC) +T3F74 26308:013.172 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26308:013.194 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26308:013.755 Data: 00 00 00 00 +T3F74 26308:013.820 - 0.656ms returns 4 (0x4) +T3F74 26308:013.853 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26308:013.882 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26308:014.364 Data: 00 00 00 00 +T3F74 26308:014.400 - 0.557ms returns 4 (0x4) +T3F74 26308:014.427 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26308:014.453 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26308:014.998 Data: 00 00 00 00 +T3F74 26308:015.035 - 0.618ms returns 4 (0x4) +T062C 26308:033.838 JLINK_IsHalted() +T062C 26308:034.972 - 1.149ms returns FALSE +T062C 26308:135.043 JLINK_HasError() +T062C 26308:135.092 JLINK_IsHalted() +T062C 26308:136.294 - 1.222ms returns FALSE +T062C 26308:236.976 JLINK_HasError() +T062C 26308:237.009 JLINK_IsHalted() +T062C 26308:238.192 - 1.203ms returns FALSE +T062C 26308:338.346 JLINK_HasError() +T062C 26308:338.418 JLINK_IsHalted() +T062C 26308:339.820 - 1.421ms returns FALSE +T062C 26308:440.619 JLINK_HasError() +T062C 26308:440.663 JLINK_IsHalted() +T062C 26308:441.869 - 1.237ms returns FALSE +T062C 26308:542.025 JLINK_HasError() +T062C 26308:542.123 JLINK_HasError() +T062C 26308:542.150 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26308:542.184 Data: 8D 12 74 01 +T062C 26308:542.208 Debug reg: DWT_CYCCNT +T062C 26308:542.230 - 0.088ms returns 1 (0x1) +T3F74 26308:544.893 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26308:544.940 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26308:546.111 Data: 00 00 80 00 +T3F74 26308:546.172 - 1.286ms returns 4 (0x4) +T3F74 26308:546.207 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26308:546.227 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26308:546.631 Data: 00 00 F0 01 +T3F74 26308:546.651 - 0.451ms returns 4 (0x4) +T3F74 26308:549.897 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26308:549.924 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26308:551.187 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26308:551.216 - 1.325ms returns 16 (0x10) +T3F74 26308:551.236 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26308:551.255 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26308:551.757 Data: 1F 00 00 00 +T3F74 26308:551.781 - 0.553ms returns 4 (0x4) +T3F74 26308:551.802 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26308:551.821 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26308:552.386 Data: 00 00 00 00 00 00 00 00 00 00 00 00 49 01 00 00 ... +T3F74 26308:552.409 - 0.615ms returns 20 (0x14) +T3F74 26308:552.430 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26308:552.449 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26308:552.880 Data: 1F 03 00 00 +T3F74 26308:552.904 - 0.482ms returns 4 (0x4) +T3F74 26308:552.928 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26308:552.961 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26308:553.507 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26308:553.530 - 0.610ms returns 12 (0xC) +T3F74 26308:553.550 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26308:553.569 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26308:554.007 Data: 00 00 00 00 +T3F74 26308:554.032 - 0.491ms returns 4 (0x4) +T3F74 26308:554.054 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26308:554.073 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26308:554.516 Data: 00 00 00 00 +T3F74 26308:554.540 - 0.494ms returns 4 (0x4) +T3F74 26308:554.560 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26308:554.579 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26308:555.034 Data: 00 00 00 00 +T3F74 26308:555.054 - 0.500ms returns 4 (0x4) +T062C 26308:567.432 JLINK_IsHalted() +T062C 26308:568.517 - 1.103ms returns FALSE +T062C 26308:669.475 JLINK_HasError() +T062C 26308:669.554 JLINK_IsHalted() +T062C 26308:670.705 - 1.193ms returns FALSE +T062C 26308:771.397 JLINK_HasError() +T062C 26308:771.435 JLINK_IsHalted() +T062C 26308:772.619 - 1.202ms returns FALSE +T062C 26308:872.802 JLINK_HasError() +T062C 26308:872.877 JLINK_IsHalted() +T062C 26308:874.051 - 1.215ms returns FALSE +T062C 26308:974.780 JLINK_HasError() +T062C 26308:974.849 JLINK_IsHalted() +T062C 26308:976.046 - 1.216ms returns FALSE +T062C 26309:076.498 JLINK_HasError() +T062C 26309:076.572 JLINK_HasError() +T062C 26309:076.616 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26309:076.676 Data: 8D 12 74 01 +T062C 26309:076.739 Debug reg: DWT_CYCCNT +T062C 26309:076.758 - 0.148ms returns 1 (0x1) +T3F74 26309:079.195 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26309:079.228 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26309:080.394 Data: 00 00 80 00 +T3F74 26309:080.474 - 1.295ms returns 4 (0x4) +T3F74 26309:080.522 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26309:080.545 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26309:081.071 Data: 00 00 F0 01 +T3F74 26309:081.096 - 0.582ms returns 4 (0x4) +T3F74 26309:084.666 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26309:084.698 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26309:086.017 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26309:086.053 - 1.394ms returns 16 (0x10) +T3F74 26309:086.083 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26309:086.106 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26309:086.565 Data: 1E 00 00 00 +T3F74 26309:086.589 - 0.513ms returns 4 (0x4) +T3F74 26309:086.609 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26309:086.628 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26309:087.192 Data: 00 00 00 00 00 00 00 00 00 00 00 00 DB 02 00 00 ... +T3F74 26309:087.215 - 0.613ms returns 20 (0x14) +T3F74 26309:087.235 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26309:087.254 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26309:087.683 Data: 1F 03 00 00 +T3F74 26309:087.703 - 0.475ms returns 4 (0x4) +T3F74 26309:087.720 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26309:087.736 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26309:088.185 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26309:088.204 - 0.490ms returns 12 (0xC) +T3F74 26309:088.221 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26309:088.237 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26309:088.683 Data: 00 00 00 00 +T3F74 26309:088.703 - 0.488ms returns 4 (0x4) +T3F74 26309:088.721 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26309:088.736 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26309:089.180 Data: 00 00 00 00 +T3F74 26309:089.200 - 0.485ms returns 4 (0x4) +T3F74 26309:089.216 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26309:089.232 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26309:089.678 Data: 00 00 00 00 +T3F74 26309:089.698 - 0.488ms returns 4 (0x4) +T062C 26309:108.972 JLINK_IsHalted() +T062C 26309:110.096 - 1.143ms returns FALSE +T062C 26309:210.313 JLINK_HasError() +T062C 26309:210.394 JLINK_IsHalted() +T062C 26309:211.618 - 1.251ms returns FALSE +T062C 26309:312.078 JLINK_HasError() +T062C 26309:312.150 JLINK_IsHalted() +T062C 26309:313.318 - 1.186ms returns FALSE +T062C 26309:413.781 JLINK_HasError() +T062C 26309:413.855 JLINK_IsHalted() +T062C 26309:415.112 - 1.276ms returns FALSE +T062C 26309:515.821 JLINK_HasError() +T062C 26309:515.866 JLINK_IsHalted() +T062C 26309:516.895 - 1.050ms returns FALSE +T062C 26309:618.085 JLINK_HasError() +T062C 26309:618.172 JLINK_HasError() +T062C 26309:618.216 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26309:618.277 Data: 8D 12 74 01 +T062C 26309:618.334 Debug reg: DWT_CYCCNT +T062C 26309:618.388 - 0.197ms returns 1 (0x1) +T3F74 26309:620.858 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26309:620.892 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26309:622.041 Data: 00 00 80 00 +T3F74 26309:622.077 - 1.227ms returns 4 (0x4) +T3F74 26309:622.121 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26309:622.145 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26309:622.620 Data: 00 00 F0 01 +T3F74 26309:622.644 - 0.531ms returns 4 (0x4) +T3F74 26309:625.686 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26309:625.722 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26309:626.896 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26309:626.929 - 1.250ms returns 16 (0x10) +T3F74 26309:626.952 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26309:626.975 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26309:627.357 Data: 1E 00 00 00 +T3F74 26309:627.378 - 0.432ms returns 4 (0x4) +T3F74 26309:627.405 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26309:627.422 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26309:628.003 Data: 00 00 00 00 00 00 00 00 00 00 00 00 3B 02 00 00 ... +T3F74 26309:628.038 - 0.641ms returns 20 (0x14) +T3F74 26309:628.064 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26309:628.087 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26309:628.498 Data: 1F 03 00 00 +T3F74 26309:628.527 - 0.470ms returns 4 (0x4) +T3F74 26309:628.549 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26309:628.569 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26309:628.995 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26309:629.018 - 0.477ms returns 12 (0xC) +T3F74 26309:629.039 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26309:629.058 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26309:629.492 Data: 00 00 00 00 +T3F74 26309:629.516 - 0.484ms returns 4 (0x4) +T3F74 26309:629.536 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26309:629.554 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26309:629.993 Data: 00 00 00 00 +T3F74 26309:630.016 - 0.488ms returns 4 (0x4) +T3F74 26309:630.036 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26309:630.055 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26309:630.487 Data: 00 00 00 00 +T3F74 26309:630.506 - 0.477ms returns 4 (0x4) +T062C 26309:642.343 JLINK_IsHalted() +T062C 26309:643.398 - 1.076ms returns FALSE +T062C 26309:744.374 JLINK_HasError() +T062C 26309:744.452 JLINK_IsHalted() +T062C 26309:745.689 - 1.286ms returns FALSE +T062C 26309:846.622 JLINK_HasError() +T062C 26309:846.694 JLINK_IsHalted() +T062C 26309:847.940 - 1.288ms returns FALSE +T062C 26309:948.655 JLINK_HasError() +T062C 26309:948.684 JLINK_IsHalted() +T062C 26309:949.792 - 1.156ms returns FALSE +T062C 26310:050.528 JLINK_HasError() +T062C 26310:050.555 JLINK_IsHalted() +T062C 26310:051.651 - 1.114ms returns FALSE +T062C 26310:151.743 JLINK_HasError() +T062C 26310:151.785 JLINK_HasError() +T062C 26310:151.804 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26310:151.833 Data: 8D 12 74 01 +T062C 26310:151.857 Debug reg: DWT_CYCCNT +T062C 26310:151.880 - 0.084ms returns 1 (0x1) +T3F74 26310:154.212 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26310:154.250 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26310:155.311 Data: 00 00 80 00 +T3F74 26310:155.338 - 1.134ms returns 4 (0x4) +T3F74 26310:155.376 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26310:155.397 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26310:155.809 Data: 00 00 F0 01 +T3F74 26310:155.830 - 0.461ms returns 4 (0x4) +T3F74 26310:158.793 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26310:158.821 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26310:160.079 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26310:160.111 - 1.326ms returns 16 (0x10) +T3F74 26310:160.135 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26310:160.159 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26310:160.666 Data: 1E 00 00 00 +T3F74 26310:160.686 - 0.558ms returns 4 (0x4) +T3F74 26310:160.704 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26310:160.720 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26310:161.163 Data: 00 00 00 00 00 00 00 00 00 00 00 00 43 01 00 00 ... +T3F74 26310:161.183 - 0.485ms returns 20 (0x14) +T3F74 26310:161.200 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26310:161.216 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26310:161.667 Data: 1F 03 00 00 +T3F74 26310:161.687 - 0.494ms returns 4 (0x4) +T3F74 26310:161.705 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26310:161.721 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26310:162.163 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26310:162.183 - 0.484ms returns 12 (0xC) +T3F74 26310:162.200 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26310:162.216 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26310:162.696 Data: 00 00 00 00 +T3F74 26310:162.720 - 0.528ms returns 4 (0x4) +T3F74 26310:162.741 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26310:162.760 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26310:163.172 Data: 00 00 00 00 +T3F74 26310:163.196 - 0.463ms returns 4 (0x4) +T3F74 26310:163.216 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26310:163.235 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26310:163.671 Data: 00 00 00 00 +T3F74 26310:163.694 - 0.486ms returns 4 (0x4) +T062C 26310:175.592 JLINK_IsHalted() +T062C 26310:176.710 - 1.137ms returns FALSE +T062C 26310:276.913 JLINK_HasError() +T062C 26310:276.997 JLINK_IsHalted() +T062C 26310:278.243 - 1.283ms returns FALSE +T062C 26310:378.413 JLINK_HasError() +T062C 26310:378.486 JLINK_IsHalted() +T062C 26310:379.787 - 1.343ms returns FALSE +T062C 26310:480.559 JLINK_HasError() +T062C 26310:480.629 JLINK_IsHalted() +T062C 26310:481.840 - 1.229ms returns FALSE +T062C 26310:582.514 JLINK_HasError() +T062C 26310:582.558 JLINK_IsHalted() +T062C 26310:583.676 - 1.141ms returns FALSE +T062C 26310:683.856 JLINK_HasError() +T062C 26310:683.937 JLINK_HasError() +T062C 26310:683.981 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26310:684.043 Data: 8D 12 74 01 +T062C 26310:684.082 Debug reg: DWT_CYCCNT +T062C 26310:684.100 - 0.126ms returns 1 (0x1) +T3F74 26310:687.108 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26310:687.147 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26310:688.375 Data: 00 00 80 00 +T3F74 26310:688.455 - 1.367ms returns 4 (0x4) +T3F74 26310:688.517 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26310:688.540 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26310:689.708 Data: 00 00 F0 01 +T3F74 26310:689.786 - 1.287ms returns 4 (0x4) +T3F74 26310:692.860 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26310:692.891 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26310:694.146 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26310:694.174 - 1.321ms returns 16 (0x10) +T3F74 26310:694.195 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26310:694.215 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26310:694.591 Data: 1E 00 00 00 +T3F74 26310:694.612 - 0.423ms returns 4 (0x4) +T3F74 26310:694.629 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26310:694.652 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26310:695.103 Data: 00 00 00 00 00 00 00 00 00 00 00 00 35 01 00 00 ... +T3F74 26310:695.126 - 0.505ms returns 20 (0x14) +T3F74 26310:695.147 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26310:695.166 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26310:695.616 Data: 1F 03 00 00 +T3F74 26310:695.639 - 0.500ms returns 4 (0x4) +T3F74 26310:695.660 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26310:695.679 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26310:696.100 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26310:696.124 - 0.474ms returns 12 (0xC) +T3F74 26310:696.146 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26310:696.165 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26310:696.595 Data: 00 00 00 00 +T3F74 26310:696.615 - 0.476ms returns 4 (0x4) +T3F74 26310:696.632 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26310:696.648 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26310:697.094 Data: 00 00 00 00 +T3F74 26310:697.115 - 0.489ms returns 4 (0x4) +T3F74 26310:697.132 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26310:697.148 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26310:697.595 Data: 00 00 00 00 +T3F74 26310:697.614 - 0.489ms returns 4 (0x4) +T062C 26310:709.840 JLINK_IsHalted() +T062C 26310:710.980 - 1.158ms returns FALSE +T062C 26310:811.479 JLINK_HasError() +T062C 26310:811.563 JLINK_IsHalted() +T062C 26310:812.803 - 1.259ms returns FALSE +T062C 26310:913.496 JLINK_HasError() +T062C 26310:913.523 JLINK_IsHalted() +T062C 26310:914.687 - 1.181ms returns FALSE +T062C 26311:014.952 JLINK_HasError() +T062C 26311:015.026 JLINK_IsHalted() +T062C 26311:016.274 - 1.267ms returns FALSE +T062C 26311:116.412 JLINK_HasError() +T062C 26311:116.483 JLINK_IsHalted() +T062C 26311:117.639 - 1.173ms returns FALSE +T062C 26311:217.822 JLINK_HasError() +T062C 26311:217.894 JLINK_HasError() +T062C 26311:217.938 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26311:218.007 Data: 8D 12 74 01 +T062C 26311:218.027 Debug reg: DWT_CYCCNT +T062C 26311:218.046 - 0.114ms returns 1 (0x1) +T3F74 26311:220.837 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26311:220.874 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26311:222.007 Data: 00 00 80 00 +T3F74 26311:222.064 - 1.234ms returns 4 (0x4) +T3F74 26311:222.098 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26311:222.118 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26311:222.522 Data: 00 00 F0 01 +T3F74 26311:222.542 - 0.451ms returns 4 (0x4) +T3F74 26311:225.790 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26311:225.817 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26311:227.168 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26311:227.217 - 1.435ms returns 16 (0x10) +T3F74 26311:227.242 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26311:227.265 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26311:227.664 Data: 1E 00 00 00 +T3F74 26311:227.698 - 0.464ms returns 4 (0x4) +T3F74 26311:227.722 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26311:227.745 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26311:228.280 Data: 00 00 00 00 00 00 00 00 00 00 00 00 A1 01 00 00 ... +T3F74 26311:228.301 - 0.585ms returns 20 (0x14) +T3F74 26311:228.318 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26311:228.334 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26311:228.777 Data: 1F 03 00 00 +T3F74 26311:228.801 - 0.490ms returns 4 (0x4) +T3F74 26311:228.821 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26311:228.840 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26311:229.275 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26311:229.298 - 0.485ms returns 12 (0xC) +T3F74 26311:229.319 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26311:229.337 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26311:229.781 Data: 00 00 00 00 +T3F74 26311:229.815 - 0.504ms returns 4 (0x4) +T3F74 26311:229.835 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26311:229.854 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26311:230.289 Data: 00 00 00 00 +T3F74 26311:230.309 - 0.480ms returns 4 (0x4) +T3F74 26311:230.326 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26311:230.342 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26311:230.776 Data: 00 00 00 00 +T3F74 26311:230.796 - 0.476ms returns 4 (0x4) +T062C 26311:242.228 JLINK_IsHalted() +T062C 26311:243.409 - 1.195ms returns FALSE +T062C 26311:343.531 JLINK_HasError() +T062C 26311:343.608 JLINK_IsHalted() +T062C 26311:344.783 - 1.193ms returns FALSE +T062C 26311:445.015 JLINK_HasError() +T062C 26311:445.109 JLINK_IsHalted() +T062C 26311:446.259 - 1.172ms returns FALSE +T062C 26311:547.079 JLINK_HasError() +T062C 26311:547.129 JLINK_IsHalted() +T062C 26311:548.264 - 1.152ms returns FALSE +T062C 26311:648.830 JLINK_HasError() +T062C 26311:648.894 JLINK_IsHalted() +T062C 26311:650.114 - 1.237ms returns FALSE +T062C 26311:750.269 JLINK_HasError() +T062C 26311:750.364 JLINK_HasError() +T062C 26311:750.408 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26311:750.470 Data: 8D 12 74 01 +T062C 26311:750.534 Debug reg: DWT_CYCCNT +T062C 26311:750.588 - 0.201ms returns 1 (0x1) +T3F74 26311:753.151 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26311:753.183 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26311:754.437 Data: 00 00 80 00 +T3F74 26311:754.470 - 1.327ms returns 4 (0x4) +T3F74 26311:754.509 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26311:754.534 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26311:754.963 Data: 00 00 F0 01 +T3F74 26311:754.983 - 0.480ms returns 4 (0x4) +T3F74 26311:757.969 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26311:758.006 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26311:759.230 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26311:759.267 - 1.306ms returns 16 (0x10) +T3F74 26311:759.295 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26311:759.320 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26311:759.713 Data: 1E 00 00 00 +T3F74 26311:759.744 - 0.457ms returns 4 (0x4) +T3F74 26311:759.767 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26311:759.788 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26311:760.334 Data: 00 00 00 00 00 00 00 00 00 00 00 00 AF 02 00 00 ... +T3F74 26311:760.357 - 0.598ms returns 20 (0x14) +T3F74 26311:760.378 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26311:760.397 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26311:760.824 Data: 1F 03 00 00 +T3F74 26311:760.844 - 0.472ms returns 4 (0x4) +T3F74 26311:760.861 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26311:760.877 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26311:761.330 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26311:761.349 - 0.495ms returns 12 (0xC) +T3F74 26311:761.367 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26311:761.383 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26311:761.828 Data: 00 00 00 00 +T3F74 26311:761.848 - 0.488ms returns 4 (0x4) +T3F74 26311:761.865 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26311:761.881 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26311:762.325 Data: 00 00 00 00 +T3F74 26311:762.345 - 0.486ms returns 4 (0x4) +T3F74 26311:762.362 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26311:762.378 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26311:762.823 Data: 00 00 00 00 +T3F74 26311:762.843 - 0.488ms returns 4 (0x4) +T062C 26311:775.644 JLINK_IsHalted() +T062C 26311:776.737 - 1.132ms returns FALSE +T062C 26311:877.594 JLINK_HasError() +T062C 26311:877.678 JLINK_IsHalted() +T062C 26311:878.925 - 1.295ms returns FALSE +T062C 26311:979.660 JLINK_HasError() +T062C 26311:979.748 JLINK_IsHalted() +T062C 26311:980.841 - 1.111ms returns FALSE +T062C 26312:080.998 JLINK_HasError() +T062C 26312:081.071 JLINK_IsHalted() +T062C 26312:082.173 - 1.120ms returns FALSE +T062C 26312:183.188 JLINK_HasError() +T062C 26312:183.271 JLINK_IsHalted() +T062C 26312:184.288 - 1.036ms returns FALSE +T062C 26312:284.774 JLINK_HasError() +T062C 26312:284.848 JLINK_HasError() +T062C 26312:284.877 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26312:284.906 Data: 8D 12 74 01 +T062C 26312:284.930 Debug reg: DWT_CYCCNT +T062C 26312:284.953 - 0.083ms returns 1 (0x1) +T3F74 26312:287.463 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26312:287.504 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26312:288.597 Data: 00 00 80 00 +T3F74 26312:288.676 - 1.233ms returns 4 (0x4) +T3F74 26312:288.799 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26312:288.853 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26312:289.978 Data: 00 00 F0 01 +T3F74 26312:290.012 - 1.222ms returns 4 (0x4) +T3F74 26312:293.129 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26312:293.156 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26312:294.434 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26312:294.462 - 1.340ms returns 16 (0x10) +T3F74 26312:294.483 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26312:294.502 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26312:294.889 Data: 1F 00 00 00 +T3F74 26312:294.913 - 0.438ms returns 4 (0x4) +T3F74 26312:294.934 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26312:294.953 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26312:295.510 Data: 00 00 00 00 00 00 00 00 00 00 00 00 7D 01 00 00 ... +T3F74 26312:295.533 - 0.607ms returns 20 (0x14) +T3F74 26312:295.554 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26312:295.572 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26312:296.013 Data: 1F 03 00 00 +T3F74 26312:296.036 - 0.490ms returns 4 (0x4) +T3F74 26312:296.056 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26312:296.076 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26312:296.508 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26312:296.528 - 0.478ms returns 12 (0xC) +T3F74 26312:296.545 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26312:296.561 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26312:297.006 Data: 00 00 00 00 +T3F74 26312:297.026 - 0.488ms returns 4 (0x4) +T3F74 26312:297.043 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26312:297.059 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26312:297.508 Data: 00 00 00 00 +T3F74 26312:297.528 - 0.491ms returns 4 (0x4) +T3F74 26312:297.545 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26312:297.561 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26312:298.007 Data: 00 00 00 00 +T3F74 26312:298.027 - 0.488ms returns 4 (0x4) +T062C 26312:317.292 JLINK_IsHalted() +T062C 26312:318.394 - 1.117ms returns FALSE +T062C 26312:419.029 JLINK_HasError() +T062C 26312:419.065 JLINK_IsHalted() +T062C 26312:420.162 - 1.115ms returns FALSE +T062C 26312:520.715 JLINK_HasError() +T062C 26312:520.790 JLINK_IsHalted() +T062C 26312:521.978 - 1.236ms returns FALSE +T062C 26312:622.162 JLINK_HasError() +T062C 26312:622.233 JLINK_IsHalted() +T062C 26312:623.349 - 1.133ms returns FALSE +T062C 26312:723.891 JLINK_HasError() +T062C 26312:723.935 JLINK_IsHalted() +T062C 26312:724.972 - 1.048ms returns FALSE +T062C 26312:825.734 JLINK_HasError() +T062C 26312:825.819 JLINK_HasError() +T062C 26312:825.838 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26312:825.867 Data: 8D 12 74 01 +T062C 26312:825.891 Debug reg: DWT_CYCCNT +T062C 26312:825.913 - 0.083ms returns 1 (0x1) +T3F74 26312:828.462 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26312:828.499 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26312:829.614 Data: 00 00 80 00 +T3F74 26312:829.668 - 1.215ms returns 4 (0x4) +T3F74 26312:829.721 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26312:829.745 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26312:830.195 Data: 00 00 F0 01 +T3F74 26312:830.219 - 0.513ms returns 4 (0x4) +T3F74 26312:833.301 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26312:833.328 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26312:834.608 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26312:834.641 - 1.348ms returns 16 (0x10) +T3F74 26312:834.664 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26312:834.687 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26312:835.820 Data: 1E 00 00 00 +T3F74 26312:835.855 - 1.199ms returns 4 (0x4) +T3F74 26312:835.881 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26312:835.903 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26312:836.449 Data: 00 00 00 00 00 00 00 00 00 00 00 00 EF 02 00 00 ... +T3F74 26312:836.479 - 0.605ms returns 20 (0x14) +T3F74 26312:836.501 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26312:836.522 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26312:836.931 Data: 1F 03 00 00 +T3F74 26312:836.951 - 0.457ms returns 4 (0x4) +T3F74 26312:836.968 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26312:836.985 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26312:837.432 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26312:837.452 - 0.490ms returns 12 (0xC) +T3F74 26312:837.469 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26312:837.485 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26312:837.930 Data: 00 00 00 00 +T3F74 26312:837.950 - 0.488ms returns 4 (0x4) +T3F74 26312:837.967 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26312:837.983 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26312:838.435 Data: 00 00 00 00 +T3F74 26312:838.455 - 0.495ms returns 4 (0x4) +T3F74 26312:838.473 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26312:838.489 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26312:838.935 Data: 00 00 00 00 +T3F74 26312:838.955 - 0.489ms returns 4 (0x4) +T062C 26312:858.457 JLINK_IsHalted() +T062C 26312:859.572 - 1.129ms returns FALSE +T062C 26312:959.753 JLINK_HasError() +T062C 26312:959.834 JLINK_IsHalted() +T062C 26312:961.170 - 1.356ms returns FALSE +T062C 26313:061.953 JLINK_HasError() +T062C 26313:062.027 JLINK_IsHalted() +T062C 26313:063.147 - 1.139ms returns FALSE +T062C 26313:163.357 JLINK_HasError() +T062C 26313:163.428 JLINK_IsHalted() +T062C 26313:164.611 - 1.201ms returns FALSE +T062C 26313:264.696 JLINK_HasError() +T062C 26313:264.732 JLINK_IsHalted() +T062C 26313:265.761 - 1.046ms returns FALSE +T062C 26313:366.653 JLINK_HasError() +T062C 26313:366.734 JLINK_HasError() +T062C 26313:366.779 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26313:366.825 Data: 8D 12 74 01 +T062C 26313:366.849 Debug reg: DWT_CYCCNT +T062C 26313:366.872 - 0.100ms returns 1 (0x1) +T3F74 26313:369.315 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26313:369.356 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26313:370.586 Data: 00 00 80 00 +T3F74 26313:370.650 - 1.341ms returns 4 (0x4) +T3F74 26313:370.685 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26313:370.705 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26313:371.120 Data: 00 00 F0 01 +T3F74 26313:371.144 - 0.466ms returns 4 (0x4) +T3F74 26313:374.291 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26313:374.318 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26313:375.505 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26313:375.538 - 1.255ms returns 16 (0x10) +T3F74 26313:375.562 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26313:375.584 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26313:375.991 Data: 1E 00 00 00 +T3F74 26313:376.016 - 0.462ms returns 4 (0x4) +T3F74 26313:376.037 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26313:376.057 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26313:376.616 Data: 00 00 00 00 00 00 00 00 00 00 00 00 07 00 00 00 ... +T3F74 26313:376.640 - 0.610ms returns 20 (0x14) +T3F74 26313:376.660 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26313:376.679 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26313:377.114 Data: 1F 03 00 00 +T3F74 26313:377.138 - 0.486ms returns 4 (0x4) +T3F74 26313:377.158 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26313:377.190 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26313:377.623 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26313:377.646 - 0.495ms returns 12 (0xC) +T3F74 26313:377.666 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26313:377.685 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26313:378.123 Data: 00 00 00 00 +T3F74 26313:378.146 - 0.488ms returns 4 (0x4) +T3F74 26313:378.166 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26313:378.185 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26313:378.609 Data: 00 00 00 00 +T3F74 26313:378.629 - 0.469ms returns 4 (0x4) +T3F74 26313:378.646 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26313:378.662 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26313:379.221 Data: 00 00 00 00 +T3F74 26313:379.248 - 0.610ms returns 4 (0x4) +T062C 26313:390.946 JLINK_IsHalted() +T062C 26313:392.026 - 1.098ms returns FALSE +T062C 26313:493.031 JLINK_HasError() +T062C 26313:493.107 JLINK_IsHalted() +T062C 26313:494.327 - 1.239ms returns FALSE +T062C 26313:595.027 JLINK_HasError() +T062C 26313:595.056 JLINK_IsHalted() +T062C 26313:596.203 - 1.165ms returns FALSE +T062C 26313:696.405 JLINK_HasError() +T062C 26313:696.480 JLINK_IsHalted() +T062C 26313:697.680 - 1.220ms returns FALSE +T062C 26313:798.013 JLINK_HasError() +T062C 26313:798.059 JLINK_IsHalted() +T062C 26313:799.097 - 1.067ms returns FALSE +T062C 26313:900.065 JLINK_HasError() +T062C 26313:900.139 JLINK_HasError() +T062C 26313:900.185 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26313:900.246 Data: 8D 12 74 01 +T062C 26313:900.304 Debug reg: DWT_CYCCNT +T062C 26313:900.358 - 0.192ms returns 1 (0x1) +T3F74 26313:902.959 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26313:902.996 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26313:904.055 Data: 00 00 80 00 +T3F74 26313:904.075 - 1.123ms returns 4 (0x4) +T3F74 26313:904.103 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26313:904.120 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26313:904.544 Data: 00 00 F0 01 +T3F74 26313:904.565 - 0.468ms returns 4 (0x4) +T3F74 26313:907.476 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26313:907.513 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26313:908.705 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26313:908.738 - 1.270ms returns 16 (0x10) +T3F74 26313:908.762 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26313:908.785 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26313:909.294 Data: 1E 00 00 00 +T3F74 26313:909.314 - 0.559ms returns 4 (0x4) +T3F74 26313:909.332 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26313:909.348 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26313:909.793 Data: 00 00 00 00 00 00 00 00 00 00 00 00 8B 00 00 00 ... +T3F74 26313:909.813 - 0.488ms returns 20 (0x14) +T3F74 26313:909.830 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26313:909.846 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26313:910.289 Data: 1F 03 00 00 +T3F74 26313:910.309 - 0.485ms returns 4 (0x4) +T3F74 26313:910.326 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26313:910.342 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26313:910.788 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26313:910.808 - 0.489ms returns 12 (0xC) +T3F74 26313:910.825 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26313:910.841 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26313:911.328 Data: 00 00 00 00 +T3F74 26313:911.351 - 0.534ms returns 4 (0x4) +T3F74 26313:911.371 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26313:911.390 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26313:911.798 Data: 00 00 00 00 +T3F74 26313:911.821 - 0.457ms returns 4 (0x4) +T3F74 26313:911.841 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26313:911.866 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26313:912.301 Data: 00 00 00 00 +T3F74 26313:912.325 - 0.491ms returns 4 (0x4) +T062C 26313:924.827 JLINK_IsHalted() +T062C 26313:925.942 - 1.133ms returns FALSE +T062C 26314:026.416 JLINK_HasError() +T062C 26314:026.478 JLINK_IsHalted() +T062C 26314:027.542 - 1.072ms returns FALSE +T062C 26314:128.702 JLINK_HasError() +T062C 26314:128.736 JLINK_IsHalted() +T062C 26314:129.897 - 1.208ms returns FALSE +T062C 26314:230.360 JLINK_HasError() +T062C 26314:230.449 JLINK_IsHalted() +T062C 26314:231.595 - 1.164ms returns FALSE +T062C 26314:331.792 JLINK_HasError() +T062C 26314:331.863 JLINK_IsHalted() +T062C 26314:333.062 - 1.240ms returns FALSE +T062C 26314:433.866 JLINK_HasError() +T062C 26314:433.940 JLINK_HasError() +T062C 26314:433.958 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26314:433.987 Data: 8D 12 74 01 +T062C 26314:434.011 Debug reg: DWT_CYCCNT +T062C 26314:434.033 - 0.082ms returns 1 (0x1) +T3F74 26314:436.657 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26314:436.698 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26314:437.876 Data: 00 00 80 00 +T3F74 26314:437.956 - 1.318ms returns 4 (0x4) +T3F74 26314:438.044 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26314:438.068 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26314:439.186 Data: 00 00 F0 01 +T3F74 26314:439.264 - 1.240ms returns 4 (0x4) +T3F74 26314:442.557 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26314:442.590 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26314:443.725 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26314:443.746 - 1.195ms returns 16 (0x10) +T3F74 26314:443.764 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26314:443.780 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26314:444.258 Data: 1E 00 00 00 +T3F74 26314:444.294 - 0.537ms returns 4 (0x4) +T3F74 26314:444.320 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26314:444.342 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26314:444.863 Data: 00 00 00 00 00 00 00 00 00 00 00 00 F9 02 00 00 ... +T3F74 26314:444.893 - 0.580ms returns 20 (0x14) +T3F74 26314:444.915 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26314:444.936 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26314:445.350 Data: 1F 03 00 00 +T3F74 26314:445.374 - 0.467ms returns 4 (0x4) +T3F74 26314:445.394 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26314:445.413 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26314:445.865 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26314:445.885 - 0.497ms returns 12 (0xC) +T3F74 26314:445.902 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26314:445.918 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26314:446.343 Data: 00 00 00 00 +T3F74 26314:446.363 - 0.467ms returns 4 (0x4) +T3F74 26314:446.380 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26314:446.396 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26314:446.871 Data: 00 00 00 00 +T3F74 26314:446.895 - 0.523ms returns 4 (0x4) +T3F74 26314:446.915 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26314:446.934 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26314:447.352 Data: 00 00 00 00 +T3F74 26314:447.375 - 0.467ms returns 4 (0x4) +T062C 26314:458.888 JLINK_IsHalted() +T062C 26314:459.983 - 1.106ms returns FALSE +T062C 26314:560.669 JLINK_HasError() +T062C 26314:560.707 JLINK_IsHalted() +T062C 26314:561.835 - 1.146ms returns FALSE +T062C 26314:662.453 JLINK_HasError() +T062C 26314:662.635 JLINK_IsHalted() +T062C 26314:663.833 - 1.241ms returns FALSE +T062C 26314:764.062 JLINK_HasError() +T062C 26314:764.132 JLINK_IsHalted() +T062C 26314:765.359 - 1.245ms returns FALSE +T062C 26314:865.856 JLINK_HasError() +T062C 26314:865.918 JLINK_IsHalted() +T062C 26314:867.093 - 1.210ms returns FALSE +T062C 26314:967.265 JLINK_HasError() +T062C 26314:967.339 JLINK_HasError() +T062C 26314:967.383 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26314:967.444 Data: 8D 12 74 01 +T062C 26314:967.501 Debug reg: DWT_CYCCNT +T062C 26314:967.520 - 0.143ms returns 1 (0x1) +T3F74 26314:970.173 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26314:970.210 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26314:971.373 Data: 00 00 80 00 +T3F74 26314:971.456 - 1.303ms returns 4 (0x4) +T3F74 26314:971.567 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26314:971.631 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26314:972.863 Data: 00 00 F0 01 +T3F74 26314:972.941 - 1.394ms returns 4 (0x4) +T3F74 26314:976.727 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26314:976.758 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26314:977.969 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26314:977.998 - 1.277ms returns 16 (0x10) +T3F74 26314:978.018 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26314:978.038 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26314:978.527 Data: 1F 00 00 00 +T3F74 26314:978.547 - 0.535ms returns 4 (0x4) +T3F74 26314:978.564 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26314:978.580 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26314:979.027 Data: 00 00 00 00 00 00 00 00 00 00 00 00 15 01 00 00 ... +T3F74 26314:979.047 - 0.490ms returns 20 (0x14) +T3F74 26314:979.065 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26314:979.081 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26314:979.525 Data: 1F 03 00 00 +T3F74 26314:979.546 - 0.487ms returns 4 (0x4) +T3F74 26314:979.563 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26314:979.579 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26314:980.026 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26314:980.046 - 0.490ms returns 12 (0xC) +T3F74 26314:980.063 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26314:980.079 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26314:980.525 Data: 00 00 00 00 +T3F74 26314:980.545 - 0.488ms returns 4 (0x4) +T3F74 26314:980.562 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26314:980.578 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26314:981.026 Data: 00 00 00 00 +T3F74 26314:981.046 - 0.491ms returns 4 (0x4) +T3F74 26314:981.063 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26314:981.079 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26314:981.525 Data: 00 00 00 00 +T3F74 26314:981.545 - 0.489ms returns 4 (0x4) +T062C 26315:001.079 JLINK_IsHalted() +T062C 26315:002.163 - 1.102ms returns FALSE +T062C 26315:102.929 JLINK_HasError() +T062C 26315:103.005 JLINK_IsHalted() +T062C 26315:104.128 - 1.141ms returns FALSE +T062C 26315:205.282 JLINK_HasError() +T062C 26315:205.356 JLINK_IsHalted() +T062C 26315:206.640 - 1.302ms returns FALSE +T062C 26315:307.313 JLINK_HasError() +T062C 26315:307.339 JLINK_IsHalted() +T062C 26315:308.486 - 1.194ms returns FALSE +T062C 26315:409.389 JLINK_HasError() +T062C 26315:409.459 JLINK_IsHalted() +T062C 26315:410.692 - 1.252ms returns FALSE +T062C 26315:511.620 JLINK_HasError() +T062C 26315:511.648 JLINK_HasError() +T062C 26315:511.663 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26315:511.689 Data: 8D 12 74 01 +T062C 26315:511.710 Debug reg: DWT_CYCCNT +T062C 26315:511.728 - 0.071ms returns 1 (0x1) +T3F74 26315:514.290 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26315:514.326 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26315:515.487 Data: 00 00 80 00 +T3F74 26315:515.567 - 1.306ms returns 4 (0x4) +T3F74 26315:515.627 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26315:515.650 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26315:516.792 Data: 00 00 F0 01 +T3F74 26315:516.870 - 1.263ms returns 4 (0x4) +T3F74 26315:520.072 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26315:520.105 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26315:521.455 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26315:521.487 - 1.423ms returns 16 (0x10) +T3F74 26315:521.511 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26315:521.541 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26315:521.955 Data: 1E 00 00 00 +T3F74 26315:521.979 - 0.475ms returns 4 (0x4) +T3F74 26315:521.999 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26315:522.018 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26315:522.580 Data: 00 00 00 00 00 00 00 00 00 00 00 00 03 02 00 00 ... +T3F74 26315:522.610 - 0.617ms returns 20 (0x14) +T3F74 26315:522.627 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26315:522.643 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26315:523.090 Data: 1F 03 00 00 +T3F74 26315:523.120 - 0.502ms returns 4 (0x4) +T3F74 26315:523.139 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26315:523.165 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26315:523.585 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26315:523.608 - 0.477ms returns 12 (0xC) +T3F74 26315:523.628 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26315:523.647 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26315:524.083 Data: 00 00 00 00 +T3F74 26315:524.107 - 0.486ms returns 4 (0x4) +T3F74 26315:524.127 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26315:524.146 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26315:524.579 Data: 00 00 00 00 +T3F74 26315:524.599 - 0.478ms returns 4 (0x4) +T3F74 26315:524.616 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26315:524.632 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26315:525.078 Data: 00 00 00 00 +T3F74 26315:525.098 - 0.488ms returns 4 (0x4) +T062C 26315:543.354 JLINK_IsHalted() +T062C 26315:544.465 - 1.129ms returns FALSE +T062C 26315:645.861 JLINK_HasError() +T062C 26315:646.017 JLINK_IsHalted() +T062C 26315:647.322 - 1.355ms returns FALSE +T062C 26315:747.562 JLINK_HasError() +T062C 26315:747.637 JLINK_IsHalted() +T062C 26315:748.925 - 1.330ms returns FALSE +T062C 26315:849.142 JLINK_HasError() +T062C 26315:849.215 JLINK_IsHalted() +T062C 26315:850.451 - 1.278ms returns FALSE +T062C 26315:950.808 JLINK_HasError() +T062C 26315:950.895 JLINK_IsHalted() +T062C 26315:952.117 - 1.263ms returns FALSE +T062C 26316:052.707 JLINK_HasError() +T062C 26316:052.782 JLINK_HasError() +T062C 26316:052.827 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26316:052.891 Data: 8D 12 74 01 +T062C 26316:052.953 Debug reg: DWT_CYCCNT +T062C 26316:052.972 - 0.151ms returns 1 (0x1) +T3F74 26316:055.629 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26316:055.662 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26316:056.931 Data: 00 00 80 00 +T3F74 26316:057.010 - 1.400ms returns 4 (0x4) +T3F74 26316:057.061 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26316:057.084 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26316:058.139 Data: 00 00 F0 01 +T3F74 26316:058.172 - 1.119ms returns 4 (0x4) +T3F74 26316:061.399 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26316:061.426 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26316:062.719 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26316:062.751 - 1.360ms returns 16 (0x10) +T3F74 26316:062.775 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26316:062.798 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26316:063.273 Data: 1E 00 00 00 +T3F74 26316:063.294 - 0.525ms returns 4 (0x4) +T3F74 26316:063.311 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26316:063.328 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26316:063.754 Data: 00 00 00 00 00 00 00 00 00 00 00 00 7D 00 00 00 ... +T3F74 26316:063.774 - 0.470ms returns 20 (0x14) +T3F74 26316:063.791 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26316:063.807 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26316:064.252 Data: 1F 03 00 00 +T3F74 26316:064.272 - 0.487ms returns 4 (0x4) +T3F74 26316:064.289 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26316:064.305 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26316:064.767 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26316:064.790 - 0.515ms returns 12 (0xC) +T3F74 26316:064.821 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26316:064.841 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26316:065.264 Data: 00 00 00 00 +T3F74 26316:065.290 - 0.476ms returns 4 (0x4) +T3F74 26316:065.316 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26316:065.367 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26316:065.764 Data: 00 00 00 00 +T3F74 26316:065.789 - 0.480ms returns 4 (0x4) +T3F74 26316:065.810 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26316:065.830 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26316:066.262 Data: 00 00 00 00 +T3F74 26316:066.282 - 0.479ms returns 4 (0x4) +T062C 26316:077.951 JLINK_IsHalted() +T062C 26316:079.018 - 1.086ms returns FALSE +T062C 26316:179.222 JLINK_HasError() +T062C 26316:179.306 JLINK_IsHalted() +T062C 26316:180.494 - 1.237ms returns FALSE +T062C 26316:281.315 JLINK_HasError() +T062C 26316:281.388 JLINK_IsHalted() +T062C 26316:282.611 - 1.241ms returns FALSE +T062C 26316:382.808 JLINK_HasError() +T062C 26316:382.882 JLINK_IsHalted() +T062C 26316:384.102 - 1.239ms returns FALSE +T062C 26316:484.685 JLINK_HasError() +T062C 26316:484.756 JLINK_IsHalted() +T062C 26316:485.948 - 1.241ms returns FALSE +T062C 26316:586.131 JLINK_HasError() +T062C 26316:586.203 JLINK_HasError() +T062C 26316:586.247 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26316:586.308 Data: 8D 12 74 01 +T062C 26316:586.359 Debug reg: DWT_CYCCNT +T062C 26316:586.378 - 0.137ms returns 1 (0x1) +T3F74 26316:588.889 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26316:588.925 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26316:590.093 Data: 00 00 80 00 +T3F74 26316:590.129 - 1.248ms returns 4 (0x4) +T3F74 26316:590.168 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26316:590.191 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26316:591.372 Data: 00 00 F0 01 +T3F74 26316:591.435 - 1.287ms returns 4 (0x4) +T3F74 26316:594.592 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26316:594.619 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26316:595.824 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26316:595.851 - 1.268ms returns 16 (0x10) +T3F74 26316:595.874 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26316:595.895 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26316:596.316 Data: 1E 00 00 00 +T3F74 26316:596.342 - 0.476ms returns 4 (0x4) +T3F74 26316:596.363 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26316:596.383 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26316:596.932 Data: 00 00 00 00 00 00 00 00 00 00 00 00 19 01 00 00 ... +T3F74 26316:596.952 - 0.596ms returns 20 (0x14) +T3F74 26316:596.970 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26316:596.986 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26316:597.448 Data: 1F 03 00 00 +T3F74 26316:597.471 - 0.509ms returns 4 (0x4) +T3F74 26316:597.492 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26316:597.511 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26316:597.942 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26316:597.965 - 0.481ms returns 12 (0xC) +T3F74 26316:597.986 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26316:598.005 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26316:598.442 Data: 00 00 00 00 +T3F74 26316:598.466 - 0.488ms returns 4 (0x4) +T3F74 26316:598.486 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26316:598.513 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26316:598.935 Data: 00 00 00 00 +T3F74 26316:598.955 - 0.476ms returns 4 (0x4) +T3F74 26316:598.972 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26316:598.988 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26316:599.435 Data: 00 00 00 00 +T3F74 26316:599.455 - 0.489ms returns 4 (0x4) +T062C 26316:611.150 JLINK_IsHalted() +T062C 26316:612.225 - 1.117ms returns FALSE +T062C 26316:712.942 JLINK_HasError() +T062C 26316:712.978 JLINK_IsHalted() +T062C 26316:714.153 - 1.200ms returns FALSE +T062C 26316:814.814 JLINK_HasError() +T062C 26316:814.891 JLINK_IsHalted() +T062C 26316:816.155 - 1.306ms returns FALSE +T062C 26316:916.395 JLINK_HasError() +T062C 26316:916.466 JLINK_IsHalted() +T062C 26316:917.529 - 1.081ms returns FALSE +T062C 26317:018.126 JLINK_HasError() +T062C 26317:018.172 JLINK_IsHalted() +T062C 26317:019.292 - 1.138ms returns FALSE +T062C 26317:119.487 JLINK_HasError() +T062C 26317:119.562 JLINK_HasError() +T062C 26317:119.606 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26317:119.666 Data: 8D 12 74 01 +T062C 26317:119.735 Debug reg: DWT_CYCCNT +T062C 26317:119.754 - 0.154ms returns 1 (0x1) +T3F74 26317:122.576 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26317:122.613 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26317:123.708 Data: 00 00 80 00 +T3F74 26317:123.789 - 1.222ms returns 4 (0x4) +T3F74 26317:123.833 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26317:123.870 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26317:125.069 Data: 00 00 F0 01 +T3F74 26317:125.146 - 1.334ms returns 4 (0x4) +T3F74 26317:128.450 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26317:128.477 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26317:129.669 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26317:129.698 - 1.254ms returns 16 (0x10) +T3F74 26317:129.718 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26317:129.738 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26317:130.115 Data: 1E 00 00 00 +T3F74 26317:130.135 - 0.424ms returns 4 (0x4) +T3F74 26317:130.153 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26317:130.169 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26317:130.615 Data: 00 00 00 00 00 00 00 00 00 00 00 00 A1 00 00 00 ... +T3F74 26317:130.635 - 0.489ms returns 20 (0x14) +T3F74 26317:130.652 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26317:130.669 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26317:131.116 Data: 1F 03 00 00 +T3F74 26317:131.136 - 0.490ms returns 4 (0x4) +T3F74 26317:131.153 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26317:131.169 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26317:131.614 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26317:131.634 - 0.487ms returns 12 (0xC) +T3F74 26317:131.651 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26317:131.667 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26317:132.115 Data: 00 00 00 00 +T3F74 26317:132.135 - 0.490ms returns 4 (0x4) +T3F74 26317:132.152 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26317:132.168 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26317:132.614 Data: 00 00 00 00 +T3F74 26317:132.634 - 0.489ms returns 4 (0x4) +T3F74 26317:132.651 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26317:132.667 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26317:133.120 Data: 00 00 00 00 +T3F74 26317:133.140 - 0.496ms returns 4 (0x4) +T062C 26317:145.162 JLINK_IsHalted() +T062C 26317:146.297 - 1.152ms returns FALSE +T062C 26317:247.080 JLINK_HasError() +T062C 26317:247.159 JLINK_IsHalted() +T062C 26317:248.356 - 1.217ms returns FALSE +T062C 26317:348.558 JLINK_HasError() +T062C 26317:348.639 JLINK_IsHalted() +T062C 26317:349.860 - 1.265ms returns FALSE +T062C 26317:450.872 JLINK_HasError() +T062C 26317:450.910 JLINK_IsHalted() +T062C 26317:452.005 - 1.128ms returns FALSE +T062C 26317:553.066 JLINK_HasError() +T062C 26317:553.141 JLINK_IsHalted() +T062C 26317:554.218 - 1.101ms returns FALSE +T062C 26317:654.378 JLINK_HasError() +T062C 26317:654.457 JLINK_HasError() +T062C 26317:654.502 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26317:654.564 Data: 8D 12 74 01 +T062C 26317:654.608 Debug reg: DWT_CYCCNT +T062C 26317:654.627 - 0.131ms returns 1 (0x1) +T3F74 26317:657.144 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26317:657.176 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26317:658.424 Data: 00 00 80 00 +T3F74 26317:658.459 - 1.322ms returns 4 (0x4) +T3F74 26317:658.504 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26317:658.532 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26317:658.929 Data: 00 00 F0 01 +T3F74 26317:658.953 - 0.456ms returns 4 (0x4) +T3F74 26317:661.963 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26317:661.990 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26317:663.272 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26317:663.331 - 1.375ms returns 16 (0x10) +T3F74 26317:663.355 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26317:663.377 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26317:663.805 Data: 1F 00 00 00 +T3F74 26317:663.829 - 0.482ms returns 4 (0x4) +T3F74 26317:663.849 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26317:663.869 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26317:664.426 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E7 00 00 00 ... +T3F74 26317:664.446 - 0.604ms returns 20 (0x14) +T3F74 26317:664.464 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26317:664.480 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26317:664.940 Data: 1F 03 00 00 +T3F74 26317:665.006 - 0.552ms returns 4 (0x4) +T3F74 26317:665.036 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26317:665.063 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26317:665.548 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26317:665.576 - 0.548ms returns 12 (0xC) +T3F74 26317:665.598 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26317:665.619 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26317:666.046 Data: 00 00 00 00 +T3F74 26317:666.072 - 0.481ms returns 4 (0x4) +T3F74 26317:666.092 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26317:666.111 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26317:666.553 Data: 00 00 00 00 +T3F74 26317:666.577 - 0.493ms returns 4 (0x4) +T3F74 26317:666.597 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26317:666.616 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26317:667.052 Data: 00 00 00 00 +T3F74 26317:667.076 - 0.486ms returns 4 (0x4) +T062C 26317:685.315 JLINK_IsHalted() +T062C 26317:686.430 - 1.133ms returns FALSE +T062C 26317:787.211 JLINK_HasError() +T062C 26317:787.287 JLINK_IsHalted() +T062C 26317:788.401 - 1.132ms returns FALSE +T062C 26317:888.614 JLINK_HasError() +T062C 26317:888.692 JLINK_IsHalted() +T062C 26317:889.854 - 1.206ms returns FALSE +T062C 26317:990.590 JLINK_HasError() +T062C 26317:990.740 JLINK_IsHalted() +T062C 26317:991.795 - 1.076ms returns FALSE +T062C 26318:092.831 JLINK_HasError() +T062C 26318:092.875 JLINK_IsHalted() +T062C 26318:093.997 - 1.138ms returns FALSE +T062C 26318:194.732 JLINK_HasError() +T062C 26318:194.810 JLINK_HasError() +T062C 26318:194.856 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26318:194.924 Data: 8D 12 74 01 +T062C 26318:194.982 Debug reg: DWT_CYCCNT +T062C 26318:195.035 - 0.198ms returns 1 (0x1) +T3F74 26318:197.470 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26318:197.503 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26318:198.737 Data: 00 00 80 00 +T3F74 26318:198.772 - 1.309ms returns 4 (0x4) +T3F74 26318:198.811 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26318:198.834 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26318:199.233 Data: 00 00 F0 01 +T3F74 26318:199.257 - 0.454ms returns 4 (0x4) +T3F74 26318:202.256 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26318:202.283 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26318:203.527 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26318:203.555 - 1.305ms returns 16 (0x10) +T3F74 26318:203.575 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26318:203.595 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26318:203.967 Data: 1E 00 00 00 +T3F74 26318:203.988 - 0.419ms returns 4 (0x4) +T3F74 26318:204.005 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26318:204.022 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26318:204.487 Data: 00 00 00 00 00 00 00 00 00 00 00 00 05 03 00 00 ... +T3F74 26318:204.517 - 0.518ms returns 20 (0x14) +T3F74 26318:204.535 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26318:204.551 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26318:204.968 Data: 1F 03 00 00 +T3F74 26318:204.988 - 0.459ms returns 4 (0x4) +T3F74 26318:205.005 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26318:205.021 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26318:205.517 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26318:205.541 - 0.543ms returns 12 (0xC) +T3F74 26318:205.561 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26318:205.580 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26318:206.055 Data: 00 00 00 00 +T3F74 26318:206.078 - 0.525ms returns 4 (0x4) +T3F74 26318:206.098 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26318:206.117 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26318:206.599 Data: 00 00 00 00 +T3F74 26318:206.623 - 0.532ms returns 4 (0x4) +T3F74 26318:206.643 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26318:206.662 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26318:207.098 Data: 00 00 00 00 +T3F74 26318:207.121 - 0.486ms returns 4 (0x4) +T062C 26318:226.778 JLINK_IsHalted() +T062C 26318:227.871 - 1.111ms returns FALSE +T062C 26318:328.023 JLINK_HasError() +T062C 26318:328.103 JLINK_IsHalted() +T062C 26318:329.335 - 1.280ms returns FALSE +T062C 26318:429.904 JLINK_HasError() +T062C 26318:429.978 JLINK_IsHalted() +T062C 26318:431.080 - 1.119ms returns FALSE +T062C 26318:531.401 JLINK_HasError() +T062C 26318:531.475 JLINK_IsHalted() +T062C 26318:532.700 - 1.266ms returns FALSE +T062C 26318:632.921 JLINK_HasError() +T062C 26318:632.994 JLINK_IsHalted() +T062C 26318:634.185 - 1.209ms returns FALSE +T062C 26318:734.885 JLINK_HasError() +T062C 26318:734.912 JLINK_HasError() +T062C 26318:734.928 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26318:734.953 Data: 8D 12 74 01 +T062C 26318:734.973 Debug reg: DWT_CYCCNT +T062C 26318:734.992 - 0.070ms returns 1 (0x1) +T3F74 26318:737.334 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26318:737.366 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26318:738.418 Data: 00 00 80 00 +T3F74 26318:738.455 - 1.129ms returns 4 (0x4) +T3F74 26318:738.503 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26318:738.527 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26318:739.039 Data: 00 00 F0 01 +T3F74 26318:739.063 - 0.568ms returns 4 (0x4) +T3F74 26318:742.818 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26318:742.853 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26318:744.082 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26318:744.111 - 1.299ms returns 16 (0x10) +T3F74 26318:744.146 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26318:744.166 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26318:744.658 Data: 1F 00 00 00 +T3F74 26318:744.681 - 0.543ms returns 4 (0x4) +T3F74 26318:744.705 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26318:744.724 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26318:745.281 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E1 01 00 00 ... +T3F74 26318:745.304 - 0.607ms returns 20 (0x14) +T3F74 26318:745.336 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26318:745.355 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26318:745.781 Data: 1F 03 00 00 +T3F74 26318:745.805 - 0.476ms returns 4 (0x4) +T3F74 26318:745.828 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26318:745.847 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26318:746.285 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26318:746.308 - 0.488ms returns 12 (0xC) +T3F74 26318:746.332 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26318:746.355 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26318:746.781 Data: 00 00 00 00 +T3F74 26318:746.804 - 0.479ms returns 4 (0x4) +T3F74 26318:746.827 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26318:746.845 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26318:747.280 Data: 00 00 00 00 +T3F74 26318:747.304 - 0.485ms returns 4 (0x4) +T3F74 26318:747.326 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26318:747.346 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26318:747.795 Data: 00 00 00 00 +T3F74 26318:747.821 - 0.503ms returns 4 (0x4) +T062C 26318:766.563 JLINK_IsHalted() +T062C 26318:767.706 - 1.189ms returns FALSE +T062C 26318:868.803 JLINK_HasError() +T062C 26318:868.843 JLINK_IsHalted() +T062C 26318:869.956 - 1.131ms returns FALSE +T062C 26318:970.662 JLINK_HasError() +T062C 26318:970.701 JLINK_IsHalted() +T062C 26318:971.879 - 1.226ms returns FALSE +T062C 26319:072.621 JLINK_HasError() +T062C 26319:072.659 JLINK_IsHalted() +T062C 26319:073.780 - 1.137ms returns FALSE +T062C 26319:173.889 JLINK_HasError() +T062C 26319:173.931 JLINK_IsHalted() +T062C 26319:175.114 - 1.225ms returns FALSE +T062C 26319:275.352 JLINK_HasError() +T062C 26319:275.430 JLINK_HasError() +T062C 26319:275.474 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26319:275.530 Data: 8D 12 74 01 +T062C 26319:275.551 Debug reg: DWT_CYCCNT +T062C 26319:275.570 - 0.102ms returns 1 (0x1) +T3F74 26319:278.213 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26319:278.250 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26319:279.427 Data: 00 00 80 00 +T3F74 26319:279.492 - 1.286ms returns 4 (0x4) +T3F74 26319:279.526 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26319:279.546 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26319:279.961 Data: 00 00 F0 01 +T3F74 26319:279.985 - 0.466ms returns 4 (0x4) +T3F74 26319:283.125 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26319:283.152 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26319:284.384 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26319:284.412 - 1.293ms returns 16 (0x10) +T3F74 26319:284.432 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26319:284.452 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26319:284.829 Data: 1E 00 00 00 +T3F74 26319:284.849 - 0.423ms returns 4 (0x4) +T3F74 26319:284.867 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26319:284.884 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26319:285.329 Data: 00 00 00 00 00 00 00 00 00 00 00 00 17 02 00 00 ... +T3F74 26319:285.350 - 0.489ms returns 20 (0x14) +T3F74 26319:285.367 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26319:285.383 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26319:285.841 Data: 1F 03 00 00 +T3F74 26319:285.861 - 0.500ms returns 4 (0x4) +T3F74 26319:285.878 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26319:285.894 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26319:286.329 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26319:286.349 - 0.477ms returns 12 (0xC) +T3F74 26319:286.366 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26319:286.382 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26319:286.823 Data: 00 00 00 00 +T3F74 26319:286.843 - 0.484ms returns 4 (0x4) +T3F74 26319:286.860 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26319:286.876 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26319:287.324 Data: 00 00 00 00 +T3F74 26319:287.344 - 0.490ms returns 4 (0x4) +T3F74 26319:287.361 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26319:287.377 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26319:287.841 Data: 00 00 00 00 +T3F74 26319:287.877 - 0.524ms returns 4 (0x4) +T062C 26319:307.242 JLINK_IsHalted() +T062C 26319:308.334 - 1.103ms returns FALSE +T062C 26319:408.806 JLINK_HasError() +T062C 26319:408.885 JLINK_IsHalted() +T062C 26319:410.080 - 1.238ms returns FALSE +T062C 26319:510.423 JLINK_HasError() +T062C 26319:510.494 JLINK_IsHalted() +T062C 26319:511.637 - 1.184ms returns FALSE +T062C 26319:612.218 JLINK_HasError() +T062C 26319:612.245 JLINK_IsHalted() +T062C 26319:613.453 - 1.227ms returns FALSE +T062C 26319:714.307 JLINK_HasError() +T062C 26319:714.339 JLINK_IsHalted() +T062C 26319:715.521 - 1.206ms returns FALSE +T062C 26319:816.525 JLINK_HasError() +T062C 26319:816.682 JLINK_HasError() +T062C 26319:816.737 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26319:816.800 Data: 8D 12 74 01 +T062C 26319:816.825 Debug reg: DWT_CYCCNT +T062C 26319:816.848 - 0.118ms returns 1 (0x1) +T3F74 26319:819.198 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26319:819.231 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26319:820.363 Data: 00 00 80 00 +T3F74 26319:820.423 - 1.232ms returns 4 (0x4) +T3F74 26319:820.458 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26319:820.478 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26319:820.883 Data: 00 00 F0 01 +T3F74 26319:820.903 - 0.452ms returns 4 (0x4) +T3F74 26319:823.878 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26319:823.918 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26319:825.208 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26319:825.241 - 1.371ms returns 16 (0x10) +T3F74 26319:825.265 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26319:825.288 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26319:825.764 Data: 1E 00 00 00 +T3F74 26319:825.788 - 0.531ms returns 4 (0x4) +T3F74 26319:825.808 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26319:825.831 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26319:826.382 Data: 00 00 00 00 00 00 00 00 00 00 00 00 83 02 00 00 ... +T3F74 26319:826.402 - 0.600ms returns 20 (0x14) +T3F74 26319:826.419 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26319:826.435 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26319:826.881 Data: 1F 03 00 00 +T3F74 26319:826.901 - 0.488ms returns 4 (0x4) +T3F74 26319:826.918 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26319:826.934 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26319:827.382 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26319:827.402 - 0.490ms returns 12 (0xC) +T3F74 26319:827.419 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26319:827.435 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26319:827.882 Data: 00 00 00 00 +T3F74 26319:827.902 - 0.490ms returns 4 (0x4) +T3F74 26319:827.919 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26319:827.935 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26319:828.382 Data: 00 00 00 00 +T3F74 26319:828.402 - 0.489ms returns 4 (0x4) +T3F74 26319:828.419 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26319:828.435 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26319:828.881 Data: 00 00 00 00 +T3F74 26319:828.900 - 0.488ms returns 4 (0x4) +T062C 26319:840.059 JLINK_IsHalted() +T062C 26319:841.139 - 1.096ms returns FALSE +T062C 26319:941.423 JLINK_HasError() +T062C 26319:941.494 JLINK_IsHalted() +T062C 26319:942.733 - 1.282ms returns FALSE +T062C 26320:042.942 JLINK_HasError() +T062C 26320:042.981 JLINK_IsHalted() +T062C 26320:044.127 - 1.164ms returns FALSE +T062C 26320:144.341 JLINK_HasError() +T062C 26320:144.503 JLINK_IsHalted() +T062C 26320:145.726 - 1.235ms returns FALSE +T062C 26320:246.411 JLINK_HasError() +T062C 26320:246.497 JLINK_IsHalted() +T062C 26320:247.593 - 1.114ms returns FALSE +T062C 26320:348.271 JLINK_HasError() +T062C 26320:348.303 JLINK_HasError() +T062C 26320:348.319 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26320:348.345 Data: 8D 12 74 01 +T062C 26320:348.366 Debug reg: DWT_CYCCNT +T062C 26320:348.384 - 0.072ms returns 1 (0x1) +T3F74 26320:351.107 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26320:351.140 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26320:352.343 Data: 00 00 80 00 +T3F74 26320:352.422 - 1.342ms returns 4 (0x4) +T3F74 26320:352.480 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26320:352.503 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26320:353.645 Data: 00 00 F0 01 +T3F74 26320:353.724 - 1.263ms returns 4 (0x4) +T3F74 26320:356.777 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26320:356.808 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26320:358.133 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26320:358.166 - 1.397ms returns 16 (0x10) +T3F74 26320:358.191 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26320:358.214 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26320:359.321 Data: 1E 00 00 00 +T3F74 26320:359.354 - 1.171ms returns 4 (0x4) +T3F74 26320:359.378 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26320:359.400 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26320:359.936 Data: 00 00 00 00 00 00 00 00 00 00 00 00 DD 02 00 00 ... +T3F74 26320:359.956 - 0.585ms returns 20 (0x14) +T3F74 26320:359.974 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26320:359.990 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26320:360.439 Data: 1F 03 00 00 +T3F74 26320:360.459 - 0.491ms returns 4 (0x4) +T3F74 26320:360.476 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26320:360.492 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26320:360.965 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26320:360.985 - 0.515ms returns 12 (0xC) +T3F74 26320:361.002 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26320:361.018 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26320:361.439 Data: 00 00 00 00 +T3F74 26320:361.459 - 0.463ms returns 4 (0x4) +T3F74 26320:361.477 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26320:361.492 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26320:361.935 Data: 00 00 00 00 +T3F74 26320:361.955 - 0.484ms returns 4 (0x4) +T3F74 26320:361.972 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26320:361.988 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26320:362.438 Data: 00 00 00 00 +T3F74 26320:362.458 - 0.492ms returns 4 (0x4) +T062C 26320:374.115 JLINK_IsHalted() +T062C 26320:375.254 - 1.158ms returns FALSE +T062C 26320:475.459 JLINK_HasError() +T062C 26320:475.537 JLINK_IsHalted() +T062C 26320:476.695 - 1.176ms returns FALSE +T062C 26320:576.904 JLINK_HasError() +T062C 26320:576.977 JLINK_IsHalted() +T062C 26320:578.176 - 1.241ms returns FALSE +T062C 26320:678.873 JLINK_HasError() +T062C 26320:678.901 JLINK_IsHalted() +T062C 26320:679.912 - 1.029ms returns FALSE +T062C 26320:780.582 JLINK_HasError() +T062C 26320:780.629 JLINK_IsHalted() +T062C 26320:781.689 - 1.083ms returns FALSE +T062C 26320:882.767 JLINK_HasError() +T062C 26320:882.812 JLINK_HasError() +T062C 26320:882.830 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26320:882.860 Data: 8D 12 74 01 +T062C 26320:882.884 Debug reg: DWT_CYCCNT +T062C 26320:882.906 - 0.083ms returns 1 (0x1) +T3F74 26320:885.269 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26320:885.305 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26320:886.461 Data: 00 00 80 00 +T3F74 26320:886.549 - 1.288ms returns 4 (0x4) +T3F74 26320:886.589 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26320:886.612 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26320:887.890 Data: 00 00 F0 01 +T3F74 26320:887.969 - 1.399ms returns 4 (0x4) +T3F74 26320:891.210 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26320:891.237 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26320:892.386 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26320:892.410 - 1.208ms returns 16 (0x10) +T3F74 26320:892.431 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26320:892.451 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26320:892.868 Data: 1F 00 00 00 +T3F74 26320:892.891 - 0.468ms returns 4 (0x4) +T3F74 26320:892.912 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26320:892.931 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26320:893.486 Data: 00 00 00 00 00 00 00 00 00 00 00 00 21 02 00 00 ... +T3F74 26320:893.506 - 0.601ms returns 20 (0x14) +T3F74 26320:893.524 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26320:893.540 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26320:893.985 Data: 1F 03 00 00 +T3F74 26320:894.005 - 0.488ms returns 4 (0x4) +T3F74 26320:894.023 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26320:894.050 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26320:894.492 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26320:894.516 - 0.501ms returns 12 (0xC) +T3F74 26320:894.536 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26320:894.555 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26320:895.044 Data: 00 00 00 00 +T3F74 26320:895.082 - 0.554ms returns 4 (0x4) +T3F74 26320:895.109 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26320:895.132 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26320:895.625 Data: 00 00 00 00 +T3F74 26320:895.658 - 0.557ms returns 4 (0x4) +T3F74 26320:895.680 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26320:895.701 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26320:896.110 Data: 00 00 00 00 +T3F74 26320:896.130 - 0.456ms returns 4 (0x4) +T062C 26320:914.763 JLINK_IsHalted() +T062C 26320:915.878 - 1.133ms returns FALSE +T062C 26321:016.567 JLINK_HasError() +T062C 26321:016.603 JLINK_IsHalted() +T062C 26321:017.732 - 1.177ms returns FALSE +T062C 26321:117.919 JLINK_HasError() +T062C 26321:117.994 JLINK_IsHalted() +T062C 26321:119.250 - 1.298ms returns FALSE +T062C 26321:219.878 JLINK_HasError() +T062C 26321:219.918 JLINK_IsHalted() +T062C 26321:221.049 - 1.148ms returns FALSE +T062C 26321:321.815 JLINK_HasError() +T062C 26321:321.901 JLINK_IsHalted() +T062C 26321:323.022 - 1.139ms returns FALSE +T062C 26321:423.203 JLINK_HasError() +T062C 26321:423.294 JLINK_HasError() +T062C 26321:423.421 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26321:423.554 Data: 8D 12 74 01 +T062C 26321:423.585 Debug reg: DWT_CYCCNT +T062C 26321:423.606 - 0.193ms returns 1 (0x1) +T3F74 26321:426.195 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26321:426.237 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26321:427.449 Data: 00 00 80 00 +T3F74 26321:427.529 - 1.361ms returns 4 (0x4) +T3F74 26321:427.586 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26321:427.610 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26321:428.753 Data: 00 00 F0 01 +T3F74 26321:428.831 - 1.264ms returns 4 (0x4) +T3F74 26321:432.259 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26321:432.291 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26321:433.483 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26321:433.511 - 1.259ms returns 16 (0x10) +T3F74 26321:433.532 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26321:433.551 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26321:434.043 Data: 1E 00 00 00 +T3F74 26321:434.064 - 0.538ms returns 4 (0x4) +T3F74 26321:434.081 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26321:434.098 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26321:434.544 Data: 00 00 00 00 00 00 00 00 00 00 00 00 5F 01 00 00 ... +T3F74 26321:434.564 - 0.490ms returns 20 (0x14) +T3F74 26321:434.582 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26321:434.597 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26321:435.043 Data: 1F 03 00 00 +T3F74 26321:435.063 - 0.488ms returns 4 (0x4) +T3F74 26321:435.080 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26321:435.096 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26321:435.546 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26321:435.569 - 0.497ms returns 12 (0xC) +T3F74 26321:435.589 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26321:435.608 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26321:436.050 Data: 00 00 00 00 +T3F74 26321:436.074 - 0.492ms returns 4 (0x4) +T3F74 26321:436.094 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26321:436.113 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26321:436.551 Data: 00 00 00 00 +T3F74 26321:436.571 - 0.484ms returns 4 (0x4) +T3F74 26321:436.588 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26321:436.604 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26321:437.071 Data: 00 00 00 00 +T3F74 26321:437.095 - 0.514ms returns 4 (0x4) +T062C 26321:456.881 JLINK_IsHalted() +T062C 26321:457.958 - 1.095ms returns FALSE +T062C 26321:558.737 JLINK_HasError() +T062C 26321:558.814 JLINK_IsHalted() +T062C 26321:560.043 - 1.249ms returns FALSE +T062C 26321:661.344 JLINK_HasError() +T062C 26321:661.419 JLINK_IsHalted() +T062C 26321:662.603 - 1.226ms returns FALSE +T062C 26321:763.735 JLINK_HasError() +T062C 26321:763.806 JLINK_IsHalted() +T062C 26321:765.016 - 1.252ms returns FALSE +T062C 26321:865.807 JLINK_HasError() +T062C 26321:865.881 JLINK_IsHalted() +T062C 26321:867.035 - 1.172ms returns FALSE +T062C 26321:967.396 JLINK_HasError() +T062C 26321:967.430 JLINK_HasError() +T062C 26321:967.448 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26321:967.476 Data: 8D 12 74 01 +T062C 26321:967.500 Debug reg: DWT_CYCCNT +T062C 26321:967.522 - 0.082ms returns 1 (0x1) +T3F74 26321:969.761 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26321:969.794 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26321:970.935 Data: 00 00 80 00 +T3F74 26321:971.016 - 1.275ms returns 4 (0x4) +T3F74 26321:971.105 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26321:971.162 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26321:972.318 Data: 00 00 F0 01 +T3F74 26321:972.384 - 1.286ms returns 4 (0x4) +T3F74 26321:975.649 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26321:975.680 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26321:976.855 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26321:976.881 - 1.247ms returns 16 (0x10) +T3F74 26321:976.909 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26321:976.929 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26321:977.353 Data: 1F 00 00 00 +T3F74 26321:977.377 - 0.476ms returns 4 (0x4) +T3F74 26321:977.398 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26321:977.417 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26321:977.971 Data: 00 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00 ... +T3F74 26321:977.991 - 0.600ms returns 20 (0x14) +T3F74 26321:978.008 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26321:978.024 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26321:978.466 Data: 1F 03 00 00 +T3F74 26321:978.486 - 0.484ms returns 4 (0x4) +T3F74 26321:978.503 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26321:978.519 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26321:978.967 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26321:978.987 - 0.490ms returns 12 (0xC) +T3F74 26321:979.004 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26321:979.020 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26321:979.467 Data: 00 00 00 00 +T3F74 26321:979.487 - 0.489ms returns 4 (0x4) +T3F74 26321:979.518 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26321:979.534 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26321:979.971 Data: 00 00 00 00 +T3F74 26321:979.995 - 0.484ms returns 4 (0x4) +T3F74 26321:980.018 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26321:980.037 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26321:980.477 Data: 00 00 00 00 +T3F74 26321:980.501 - 0.491ms returns 4 (0x4) +T062C 26321:999.603 JLINK_IsHalted() +T062C 26322:000.748 - 1.162ms returns FALSE +T062C 26322:100.956 JLINK_HasError() +T062C 26322:101.034 JLINK_IsHalted() +T062C 26322:102.095 - 1.075ms returns FALSE +T062C 26322:202.865 JLINK_HasError() +T062C 26322:202.941 JLINK_IsHalted() +T062C 26322:204.169 - 1.246ms returns FALSE +T062C 26322:304.372 JLINK_HasError() +T062C 26322:304.445 JLINK_IsHalted() +T062C 26322:305.632 - 1.227ms returns FALSE +T062C 26322:406.070 JLINK_HasError() +T062C 26322:406.115 JLINK_IsHalted() +T062C 26322:407.174 - 1.075ms returns FALSE +T062C 26322:507.940 JLINK_HasError() +T062C 26322:508.025 JLINK_HasError() +T062C 26322:508.043 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26322:508.073 Data: 8D 12 74 01 +T062C 26322:508.096 Debug reg: DWT_CYCCNT +T062C 26322:508.118 - 0.083ms returns 1 (0x1) +T3F74 26322:510.663 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26322:510.708 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26322:511.932 Data: 00 00 80 00 +T3F74 26322:512.012 - 1.375ms returns 4 (0x4) +T3F74 26322:512.072 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26322:512.095 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26322:513.155 Data: 00 00 F0 01 +T3F74 26322:513.192 - 1.128ms returns 4 (0x4) +T3F74 26322:516.615 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26322:516.645 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26322:517.779 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26322:517.856 - 1.249ms returns 16 (0x10) +T3F74 26322:517.875 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26322:517.893 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26322:518.269 Data: 1E 00 00 00 +T3F74 26322:518.289 - 0.421ms returns 4 (0x4) +T3F74 26322:518.307 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26322:518.323 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26322:518.789 Data: 00 00 00 00 00 00 00 00 00 00 00 00 4F 02 00 00 ... +T3F74 26322:518.812 - 0.513ms returns 20 (0x14) +T3F74 26322:518.833 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26322:518.852 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26322:519.280 Data: 1F 03 00 00 +T3F74 26322:519.303 - 0.478ms returns 4 (0x4) +T3F74 26322:519.324 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26322:519.343 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26322:519.789 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26322:519.812 - 0.496ms returns 12 (0xC) +T3F74 26322:519.832 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26322:519.851 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26322:520.273 Data: 00 00 00 00 +T3F74 26322:520.293 - 0.467ms returns 4 (0x4) +T3F74 26322:520.310 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26322:520.326 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26322:520.774 Data: 00 00 00 00 +T3F74 26322:520.794 - 0.491ms returns 4 (0x4) +T3F74 26322:520.811 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26322:520.827 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26322:521.273 Data: 00 00 00 00 +T3F74 26322:521.293 - 0.488ms returns 4 (0x4) +T062C 26322:540.542 JLINK_IsHalted() +T062C 26322:541.677 - 1.154ms returns FALSE +T062C 26322:642.780 JLINK_HasError() +T062C 26322:642.861 JLINK_IsHalted() +T062C 26322:644.039 - 1.196ms returns FALSE +T062C 26322:744.160 JLINK_HasError() +T062C 26322:744.196 JLINK_IsHalted() +T062C 26322:745.250 - 1.071ms returns FALSE +T062C 26322:846.060 JLINK_HasError() +T062C 26322:846.141 JLINK_IsHalted() +T062C 26322:847.328 - 1.229ms returns FALSE +T062C 26322:947.575 JLINK_HasError() +T062C 26322:947.650 JLINK_IsHalted() +T062C 26322:948.809 - 1.201ms returns FALSE +T062C 26323:049.723 JLINK_HasError() +T062C 26323:049.797 JLINK_HasError() +T062C 26323:049.842 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26323:049.903 Data: 8D 12 74 01 +T062C 26323:049.960 Debug reg: DWT_CYCCNT +T062C 26323:050.013 - 0.177ms returns 1 (0x1) +T3F74 26323:052.424 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26323:052.456 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26323:053.597 Data: 00 00 80 00 +T3F74 26323:053.632 - 1.216ms returns 4 (0x4) +T3F74 26323:053.696 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26323:053.721 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26323:054.204 Data: 00 00 F0 01 +T3F74 26323:054.228 - 0.540ms returns 4 (0x4) +T3F74 26323:057.603 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26323:057.630 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26323:058.922 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26323:059.000 - 1.405ms returns 16 (0x10) +T3F74 26323:059.024 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26323:059.046 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26323:059.452 Data: 1E 00 00 00 +T3F74 26323:059.472 - 0.461ms returns 4 (0x4) +T3F74 26323:059.501 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26323:059.517 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26323:059.953 Data: 00 00 00 00 00 00 00 00 00 00 00 00 69 01 00 00 ... +T3F74 26323:059.973 - 0.479ms returns 20 (0x14) +T3F74 26323:059.990 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26323:060.006 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26323:060.458 Data: 1F 03 00 00 +T3F74 26323:060.482 - 0.499ms returns 4 (0x4) +T3F74 26323:060.502 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26323:060.521 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26323:060.961 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26323:060.984 - 0.489ms returns 12 (0xC) +T3F74 26323:061.004 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26323:061.023 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26323:061.453 Data: 00 00 00 00 +T3F74 26323:061.476 - 0.480ms returns 4 (0x4) +T3F74 26323:061.496 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26323:061.515 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26323:061.953 Data: 00 00 00 00 +T3F74 26323:061.976 - 0.492ms returns 4 (0x4) +T3F74 26323:061.999 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26323:062.015 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26323:062.447 Data: 00 00 00 00 +T3F74 26323:062.467 - 0.474ms returns 4 (0x4) +T062C 26323:073.977 JLINK_IsHalted() +T062C 26323:075.088 - 1.128ms returns FALSE +T062C 26323:175.288 JLINK_HasError() +T062C 26323:175.368 JLINK_IsHalted() +T062C 26323:176.624 - 1.299ms returns FALSE +T062C 26323:276.905 JLINK_HasError() +T062C 26323:276.977 JLINK_IsHalted() +T062C 26323:278.128 - 1.201ms returns FALSE +T062C 26323:378.301 JLINK_HasError() +T062C 26323:378.335 JLINK_IsHalted() +T062C 26323:379.425 - 1.107ms returns FALSE +T062C 26323:479.899 JLINK_HasError() +T062C 26323:479.986 JLINK_IsHalted() +T062C 26323:481.153 - 1.216ms returns FALSE +T062C 26323:581.381 JLINK_HasError() +T062C 26323:581.462 JLINK_HasError() +T062C 26323:581.482 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26323:581.512 Data: 8D 12 74 01 +T062C 26323:581.536 Debug reg: DWT_CYCCNT +T062C 26323:581.558 - 0.083ms returns 1 (0x1) +T3F74 26323:587.317 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26323:587.364 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26323:588.505 Data: 00 00 80 00 +T3F74 26323:588.540 - 1.231ms returns 4 (0x4) +T3F74 26323:588.607 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26323:588.631 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26323:589.754 Data: 00 00 F0 01 +T3F74 26323:589.774 - 1.174ms returns 4 (0x4) +T3F74 26323:592.998 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26323:593.025 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26323:594.435 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26323:594.507 - 1.517ms returns 16 (0x10) +T3F74 26323:594.531 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26323:594.554 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26323:595.638 Data: 1E 00 00 00 +T3F74 26323:595.673 - 1.149ms returns 4 (0x4) +T3F74 26323:595.696 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26323:595.718 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26323:596.252 Data: 00 00 00 00 00 00 00 00 00 00 00 00 85 01 00 00 ... +T3F74 26323:596.272 - 0.583ms returns 20 (0x14) +T3F74 26323:596.290 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26323:596.326 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26323:596.883 Data: 1F 03 00 00 +T3F74 26323:596.909 - 0.627ms returns 4 (0x4) +T3F74 26323:596.930 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26323:596.951 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26323:597.387 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26323:597.410 - 0.487ms returns 12 (0xC) +T3F74 26323:597.430 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26323:597.450 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26323:597.881 Data: 00 00 00 00 +T3F74 26323:597.901 - 0.477ms returns 4 (0x4) +T3F74 26323:597.919 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26323:597.935 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26323:598.380 Data: 00 00 00 00 +T3F74 26323:598.400 - 0.488ms returns 4 (0x4) +T3F74 26323:598.417 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26323:598.433 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26323:598.880 Data: 00 00 00 00 +T3F74 26323:598.900 - 0.490ms returns 4 (0x4) +T062C 26323:610.449 JLINK_IsHalted() +T062C 26323:611.516 - 1.077ms returns FALSE +T062C 26323:711.721 JLINK_HasError() +T062C 26323:711.807 JLINK_IsHalted() +T062C 26323:713.090 - 1.302ms returns FALSE +T062C 26323:813.658 JLINK_HasError() +T062C 26323:813.742 JLINK_IsHalted() +T062C 26323:814.987 - 1.264ms returns FALSE +T062C 26323:915.175 JLINK_HasError() +T062C 26323:915.248 JLINK_IsHalted() +T062C 26323:916.407 - 1.178ms returns FALSE +T062C 26324:016.564 JLINK_HasError() +T062C 26324:016.645 JLINK_IsHalted() +T062C 26324:017.716 - 1.085ms returns FALSE +T062C 26324:117.899 JLINK_HasError() +T062C 26324:117.974 JLINK_HasError() +T062C 26324:118.018 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26324:118.083 Data: 8D 12 74 01 +T062C 26324:118.104 Debug reg: DWT_CYCCNT +T062C 26324:118.122 - 0.111ms returns 1 (0x1) +T3F74 26324:120.582 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26324:120.614 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26324:121.823 Data: 00 00 80 00 +T3F74 26324:121.857 - 1.283ms returns 4 (0x4) +T3F74 26324:121.896 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26324:121.919 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26324:122.448 Data: 00 00 F0 01 +T3F74 26324:122.469 - 0.579ms returns 4 (0x4) +T3F74 26324:125.656 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26324:125.687 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26324:126.938 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26324:126.962 - 1.313ms returns 16 (0x10) +T3F74 26324:126.982 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26324:127.000 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26324:127.631 Data: 1F 00 00 00 +T3F74 26324:127.663 - 0.688ms returns 4 (0x4) +T3F74 26324:127.684 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26324:127.705 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26324:128.943 Data: 00 00 00 00 00 00 00 00 00 00 00 00 A7 01 00 00 ... +T3F74 26324:128.976 - 1.299ms returns 20 (0x14) +T3F74 26324:129.000 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26324:129.023 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26324:129.479 Data: 1F 03 00 00 +T3F74 26324:129.503 - 0.511ms returns 4 (0x4) +T3F74 26324:129.524 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26324:129.543 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26324:130.066 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26324:130.089 - 0.573ms returns 12 (0xC) +T3F74 26324:130.114 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26324:130.131 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26324:130.559 Data: 00 00 00 00 +T3F74 26324:130.579 - 0.471ms returns 4 (0x4) +T3F74 26324:130.596 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26324:130.613 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26324:131.059 Data: 00 00 00 00 +T3F74 26324:131.079 - 0.489ms returns 4 (0x4) +T3F74 26324:131.096 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26324:131.112 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26324:131.559 Data: 00 00 00 00 +T3F74 26324:131.579 - 0.489ms returns 4 (0x4) +T062C 26324:150.568 JLINK_IsHalted() +T062C 26324:151.743 - 1.219ms returns FALSE +T062C 26324:252.104 JLINK_HasError() +T062C 26324:252.278 JLINK_IsHalted() +T062C 26324:253.424 - 1.194ms returns FALSE +T062C 26324:353.732 JLINK_HasError() +T062C 26324:353.805 JLINK_IsHalted() +T062C 26324:354.981 - 1.218ms returns FALSE +T062C 26324:455.662 JLINK_HasError() +T062C 26324:455.718 JLINK_IsHalted() +T062C 26324:456.807 - 1.109ms returns FALSE +T062C 26324:557.554 JLINK_HasError() +T062C 26324:557.640 JLINK_IsHalted() +T062C 26324:558.861 - 1.239ms returns FALSE +T062C 26324:659.881 JLINK_HasError() +T062C 26324:659.922 JLINK_HasError() +T062C 26324:659.941 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26324:659.970 Data: 8D 12 74 01 +T062C 26324:659.994 Debug reg: DWT_CYCCNT +T062C 26324:660.016 - 0.083ms returns 1 (0x1) +T3F74 26324:666.518 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26324:666.555 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26324:667.798 Data: 00 00 80 00 +T3F74 26324:667.881 - 1.372ms returns 4 (0x4) +T3F74 26324:667.921 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26324:667.944 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26324:669.076 Data: 00 00 F0 01 +T3F74 26324:669.154 - 1.253ms returns 4 (0x4) +T3F74 26324:672.253 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26324:672.284 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26324:673.536 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26324:673.564 - 1.318ms returns 16 (0x10) +T3F74 26324:673.585 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26324:673.604 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26324:673.983 Data: 1E 00 00 00 +T3F74 26324:674.004 - 0.425ms returns 4 (0x4) +T3F74 26324:674.021 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26324:674.037 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26324:674.496 Data: 00 00 00 00 00 00 00 00 00 00 00 00 4B 01 00 00 ... +T3F74 26324:674.523 - 0.509ms returns 20 (0x14) +T3F74 26324:674.544 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26324:674.564 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26324:674.996 Data: 1F 03 00 00 +T3F74 26324:675.020 - 0.484ms returns 4 (0x4) +T3F74 26324:675.040 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26324:675.059 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26324:675.488 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26324:675.512 - 0.479ms returns 12 (0xC) +T3F74 26324:675.532 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26324:675.552 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26324:676.000 Data: 00 00 00 00 +T3F74 26324:676.024 - 0.500ms returns 4 (0x4) +T3F74 26324:676.045 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26324:676.064 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26324:676.492 Data: 00 00 00 00 +T3F74 26324:676.516 - 0.479ms returns 4 (0x4) +T3F74 26324:676.536 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26324:676.555 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26324:676.992 Data: 00 00 00 00 +T3F74 26324:677.016 - 0.487ms returns 4 (0x4) +T062C 26324:696.479 JLINK_IsHalted() +T062C 26324:697.500 - 1.029ms returns FALSE +T062C 26324:797.980 JLINK_HasError() +T062C 26324:798.012 JLINK_IsHalted() +T062C 26324:799.138 - 1.148ms returns FALSE +T062C 26324:899.349 JLINK_HasError() +T062C 26324:899.421 JLINK_IsHalted() +T062C 26324:900.658 - 1.255ms returns FALSE +T062C 26325:001.622 JLINK_HasError() +T062C 26325:001.665 JLINK_IsHalted() +T062C 26325:002.780 - 1.146ms returns FALSE +T062C 26325:103.219 JLINK_HasError() +T062C 26325:103.263 JLINK_IsHalted() +T062C 26325:104.365 - 1.122ms returns FALSE +T062C 26325:205.197 JLINK_HasError() +T062C 26325:205.283 JLINK_HasError() +T062C 26325:205.302 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26325:205.332 Data: 8D 12 74 01 +T062C 26325:205.357 Debug reg: DWT_CYCCNT +T062C 26325:205.379 - 0.085ms returns 1 (0x1) +T3F74 26325:213.025 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26325:213.074 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26325:214.213 Data: 00 00 80 00 +T3F74 26325:214.265 - 1.248ms returns 4 (0x4) +T3F74 26325:214.306 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26325:214.329 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26325:214.827 Data: 00 00 F0 01 +T3F74 26325:214.877 - 0.580ms returns 4 (0x4) +T3F74 26325:218.935 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26325:218.972 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26325:220.171 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26325:220.191 - 1.263ms returns 16 (0x10) +T3F74 26325:220.209 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26325:220.226 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26325:220.662 Data: 1E 00 00 00 +T3F74 26325:220.695 - 0.492ms returns 4 (0x4) +T3F74 26325:220.712 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26325:220.730 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26325:221.300 Data: 00 00 00 00 00 00 00 00 00 00 00 00 93 00 00 00 ... +T3F74 26325:221.324 - 0.619ms returns 20 (0x14) +T3F74 26325:221.345 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26325:221.364 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26325:221.792 Data: 1F 03 00 00 +T3F74 26325:221.815 - 0.478ms returns 4 (0x4) +T3F74 26325:221.835 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26325:221.854 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26325:222.285 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26325:222.304 - 0.476ms returns 12 (0xC) +T3F74 26325:222.322 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26325:222.338 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26325:222.835 Data: 00 00 00 00 +T3F74 26325:222.872 - 0.558ms returns 4 (0x4) +T3F74 26325:222.900 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26325:222.924 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26325:223.418 Data: 00 00 00 00 +T3F74 26325:223.444 - 0.552ms returns 4 (0x4) +T3F74 26325:223.465 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26325:223.485 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26325:223.916 Data: 00 00 00 00 +T3F74 26325:223.940 - 0.483ms returns 4 (0x4) +T062C 26325:237.238 JLINK_IsHalted() +T062C 26325:238.358 - 1.139ms returns FALSE +T062C 26325:339.241 JLINK_HasError() +T062C 26325:339.289 JLINK_IsHalted() +T062C 26325:340.428 - 1.153ms returns FALSE +T062C 26325:440.563 JLINK_HasError() +T062C 26325:440.606 JLINK_IsHalted() +T062C 26325:441.764 - 1.206ms returns FALSE +T062C 26325:542.696 JLINK_HasError() +T062C 26325:542.752 JLINK_IsHalted() +T062C 26325:543.900 - 1.159ms returns FALSE +T062C 26325:644.576 JLINK_HasError() +T062C 26325:644.661 JLINK_IsHalted() +T062C 26325:645.808 - 1.167ms returns FALSE +T062C 26325:746.740 JLINK_HasError() +T062C 26325:746.786 JLINK_HasError() +T062C 26325:746.814 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26325:746.848 Data: 8D 12 74 01 +T062C 26325:746.872 Debug reg: DWT_CYCCNT +T062C 26325:746.894 - 0.087ms returns 1 (0x1) +T3F74 26325:749.367 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26325:749.404 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26325:750.573 Data: 00 00 80 00 +T3F74 26325:750.634 - 1.274ms returns 4 (0x4) +T3F74 26325:750.670 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26325:750.690 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26325:751.226 Data: 00 00 F0 01 +T3F74 26325:751.252 - 0.590ms returns 4 (0x4) +T3F74 26325:755.292 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26325:755.328 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26325:756.488 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26325:756.521 - 1.238ms returns 16 (0x10) +T3F74 26325:756.547 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26325:756.570 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26325:756.971 Data: 1E 00 00 00 +T3F74 26325:756.995 - 0.456ms returns 4 (0x4) +T3F74 26325:757.016 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26325:757.035 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26325:757.609 Data: 00 00 00 00 00 00 00 00 00 00 00 00 2D 01 00 00 ... +T3F74 26325:757.632 - 0.624ms returns 20 (0x14) +T3F74 26325:757.653 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26325:757.679 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26325:758.094 Data: 1F 03 00 00 +T3F74 26325:758.114 - 0.468ms returns 4 (0x4) +T3F74 26325:758.131 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26325:758.147 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26325:758.610 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26325:758.630 - 0.505ms returns 12 (0xC) +T3F74 26325:758.648 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26325:758.665 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26325:759.107 Data: 00 00 00 00 +T3F74 26325:759.134 - 0.493ms returns 4 (0x4) +T3F74 26325:759.155 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26325:759.176 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26325:759.605 Data: 00 00 00 00 +T3F74 26325:759.641 - 0.494ms returns 4 (0x4) +T3F74 26325:759.666 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26325:759.688 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26325:760.107 Data: 00 00 00 00 +T3F74 26325:760.136 - 0.477ms returns 4 (0x4) +T062C 26325:773.119 JLINK_IsHalted() +T062C 26325:774.298 - 1.197ms returns FALSE +T062C 26325:874.487 JLINK_HasError() +T062C 26325:874.582 JLINK_IsHalted() +T062C 26325:875.826 - 1.263ms returns FALSE +T062C 26325:976.774 JLINK_HasError() +T062C 26325:976.832 JLINK_IsHalted() +T062C 26325:977.955 - 1.141ms returns FALSE +T062C 26326:079.041 JLINK_HasError() +T062C 26326:079.101 JLINK_IsHalted() +T062C 26326:080.219 - 1.150ms returns FALSE +T062C 26326:180.743 JLINK_HasError() +T062C 26326:180.789 JLINK_IsHalted() +T062C 26326:181.946 - 1.174ms returns FALSE +T062C 26326:282.199 JLINK_HasError() +T062C 26326:282.283 JLINK_HasError() +T062C 26326:282.319 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26326:282.345 Data: 8D 12 74 01 +T062C 26326:282.365 Debug reg: DWT_CYCCNT +T062C 26326:282.384 - 0.072ms returns 1 (0x1) +T3F74 26326:284.890 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26326:284.924 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26326:286.185 Data: 00 00 80 00 +T3F74 26326:286.220 - 1.337ms returns 4 (0x4) +T3F74 26326:286.260 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26326:286.283 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26326:287.411 Data: 00 00 F0 01 +T3F74 26326:287.446 - 1.194ms returns 4 (0x4) +T3F74 26326:290.915 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26326:290.948 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26326:292.166 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26326:292.195 - 1.286ms returns 16 (0x10) +T3F74 26326:292.216 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26326:292.235 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26326:292.648 Data: 1E 00 00 00 +T3F74 26326:292.668 - 0.459ms returns 4 (0x4) +T3F74 26326:292.685 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26326:292.702 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26326:293.148 Data: 00 00 00 00 00 00 00 00 00 00 00 00 71 00 00 00 ... +T3F74 26326:293.168 - 0.489ms returns 20 (0x14) +T3F74 26326:293.185 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26326:293.201 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26326:293.646 Data: 1F 03 00 00 +T3F74 26326:293.666 - 0.487ms returns 4 (0x4) +T3F74 26326:293.683 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26326:293.699 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26326:294.148 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26326:294.167 - 0.491ms returns 12 (0xC) +T3F74 26326:294.184 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26326:294.200 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26326:294.677 Data: 00 00 00 00 +T3F74 26326:294.697 - 0.519ms returns 4 (0x4) +T3F74 26326:294.723 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26326:294.748 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26326:295.286 Data: 00 00 00 00 +T3F74 26326:295.321 - 0.607ms returns 4 (0x4) +T3F74 26326:295.353 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26326:295.380 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26326:295.781 Data: 00 00 00 00 +T3F74 26326:295.810 - 0.466ms returns 4 (0x4) +T062C 26326:308.488 JLINK_IsHalted() +T062C 26326:309.535 - 1.065ms returns FALSE +T062C 26326:410.084 JLINK_HasError() +T062C 26326:410.171 JLINK_IsHalted() +T062C 26326:411.342 - 1.213ms returns FALSE +T062C 26326:511.824 JLINK_HasError() +T062C 26326:511.873 JLINK_IsHalted() +T062C 26326:512.962 - 1.130ms returns FALSE +T062C 26326:613.225 JLINK_HasError() +T062C 26326:613.309 JLINK_IsHalted() +T062C 26326:614.405 - 1.121ms returns FALSE +T062C 26326:715.132 JLINK_HasError() +T062C 26326:715.224 JLINK_IsHalted() +T062C 26326:716.442 - 1.260ms returns FALSE +T062C 26326:816.683 JLINK_HasError() +T062C 26326:816.770 JLINK_HasError() +T062C 26326:816.815 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26326:816.858 Data: 8D 12 74 01 +T062C 26326:816.879 Debug reg: DWT_CYCCNT +T062C 26326:816.897 - 0.089ms returns 1 (0x1) +T3F74 26326:819.452 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26326:819.485 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26326:820.620 Data: 00 00 80 00 +T3F74 26326:820.658 - 1.214ms returns 4 (0x4) +T3F74 26326:820.706 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26326:820.729 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26326:821.203 Data: 00 00 F0 01 +T3F74 26326:821.227 - 0.530ms returns 4 (0x4) +T3F74 26326:825.340 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26326:825.375 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26326:826.599 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26326:826.629 - 1.296ms returns 16 (0x10) +T3F74 26326:826.652 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26326:826.671 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26326:827.077 Data: 1E 00 00 00 +T3F74 26326:827.098 - 0.453ms returns 4 (0x4) +T3F74 26326:827.115 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26326:827.132 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26326:827.577 Data: 00 00 00 00 00 00 00 00 00 00 00 00 89 00 00 00 ... +T3F74 26326:827.597 - 0.488ms returns 20 (0x14) +T3F74 26326:827.614 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26326:827.630 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26326:828.077 Data: 1F 03 00 00 +T3F74 26326:828.097 - 0.490ms returns 4 (0x4) +T3F74 26326:828.114 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26326:828.130 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26326:828.577 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26326:828.597 - 0.489ms returns 12 (0xC) +T3F74 26326:828.614 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26326:828.630 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26326:829.076 Data: 00 00 00 00 +T3F74 26326:829.096 - 0.489ms returns 4 (0x4) +T3F74 26326:829.113 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26326:829.129 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26326:829.571 Data: 00 00 00 00 +T3F74 26326:829.591 - 0.484ms returns 4 (0x4) +T3F74 26326:829.608 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26326:829.624 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26326:830.089 Data: 00 00 00 00 +T3F74 26326:830.109 - 0.507ms returns 4 (0x4) +T062C 26326:843.933 JLINK_IsHalted() +T062C 26326:845.009 - 1.123ms returns FALSE +T062C 26326:946.102 JLINK_HasError() +T062C 26326:946.143 JLINK_IsHalted() +T062C 26326:947.196 - 1.079ms returns FALSE +T062C 26327:047.286 JLINK_HasError() +T062C 26327:047.330 JLINK_IsHalted() +T062C 26327:048.444 - 1.127ms returns FALSE +T062C 26327:149.900 JLINK_HasError() +T062C 26327:149.945 JLINK_IsHalted() +T062C 26327:151.059 - 1.125ms returns FALSE +T062C 26327:251.392 JLINK_HasError() +T062C 26327:251.479 JLINK_IsHalted() +T062C 26327:252.639 - 1.178ms returns FALSE +T062C 26327:353.503 JLINK_HasError() +T062C 26327:353.550 JLINK_HasError() +T062C 26327:353.569 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26327:353.611 Data: 8D 12 74 01 +T062C 26327:353.635 Debug reg: DWT_CYCCNT +T062C 26327:353.656 - 0.095ms returns 1 (0x1) +T3F74 26327:356.112 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26327:356.147 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26327:357.352 Data: 00 00 80 00 +T3F74 26327:357.417 - 1.312ms returns 4 (0x4) +T3F74 26327:357.452 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26327:357.472 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26327:357.878 Data: 00 00 F0 01 +T3F74 26327:357.898 - 0.452ms returns 4 (0x4) +T3F74 26327:361.309 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26327:361.340 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26327:362.554 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26327:362.582 - 1.280ms returns 16 (0x10) +T3F74 26327:362.603 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26327:362.622 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26327:363.001 Data: 1F 00 00 00 +T3F74 26327:363.021 - 0.425ms returns 4 (0x4) +T3F74 26327:363.039 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26327:363.055 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26327:363.501 Data: 00 00 00 00 00 00 00 00 00 00 00 00 63 00 00 00 ... +T3F74 26327:363.521 - 0.488ms returns 20 (0x14) +T3F74 26327:363.538 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26327:363.554 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26327:364.006 Data: 1F 03 00 00 +T3F74 26327:364.030 - 0.499ms returns 4 (0x4) +T3F74 26327:364.050 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26327:364.068 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26327:364.514 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26327:364.538 - 0.496ms returns 12 (0xC) +T3F74 26327:364.558 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26327:364.578 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26327:365.029 Data: 00 00 00 00 +T3F74 26327:365.059 - 0.508ms returns 4 (0x4) +T3F74 26327:365.079 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26327:365.098 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26327:365.513 Data: 00 00 00 00 +T3F74 26327:365.537 - 0.466ms returns 4 (0x4) +T3F74 26327:365.557 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26327:365.576 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26327:366.005 Data: 00 00 00 00 +T3F74 26327:366.025 - 0.474ms returns 4 (0x4) +T062C 26327:387.013 JLINK_IsHalted() +T062C 26327:388.167 - 1.173ms returns FALSE +T062C 26327:488.687 JLINK_HasError() +T062C 26327:488.778 JLINK_IsHalted() +T062C 26327:490.075 - 1.339ms returns FALSE +T062C 26327:590.909 JLINK_HasError() +T062C 26327:590.959 JLINK_IsHalted() +T062C 26327:592.014 - 1.069ms returns FALSE +T062C 26327:692.498 JLINK_HasError() +T062C 26327:692.559 JLINK_IsHalted() +T062C 26327:693.610 - 1.070ms returns FALSE +T062C 26327:793.906 JLINK_HasError() +T062C 26327:793.960 JLINK_IsHalted() +T062C 26327:795.077 - 1.136ms returns FALSE +T062C 26327:895.608 JLINK_HasError() +T062C 26327:895.655 JLINK_HasError() +T062C 26327:895.674 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26327:895.706 Data: 8D 12 74 01 +T062C 26327:895.730 Debug reg: DWT_CYCCNT +T062C 26327:895.753 - 0.086ms returns 1 (0x1) +T3F74 26327:898.427 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26327:898.467 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26327:899.609 Data: 00 00 80 00 +T3F74 26327:899.639 - 1.220ms returns 4 (0x4) +T3F74 26327:899.677 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26327:899.699 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26327:900.187 Data: 00 00 F0 01 +T3F74 26327:900.210 - 0.541ms returns 4 (0x4) +T3F74 26327:903.801 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26327:903.832 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26327:905.075 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26327:905.108 - 1.316ms returns 16 (0x10) +T3F74 26327:905.211 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26327:905.239 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26327:905.684 Data: 1E 00 00 00 +T3F74 26327:905.708 - 0.505ms returns 4 (0x4) +T3F74 26327:905.729 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26327:905.748 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26327:906.310 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 00 ... +T3F74 26327:906.334 - 0.613ms returns 20 (0x14) +T3F74 26327:906.354 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26327:906.373 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26327:906.808 Data: 1F 03 00 00 +T3F74 26327:906.832 - 0.485ms returns 4 (0x4) +T3F74 26327:906.852 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26327:906.871 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26327:907.309 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26327:907.333 - 0.488ms returns 12 (0xC) +T3F74 26327:907.353 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26327:907.372 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26327:907.836 Data: 00 00 00 00 +T3F74 26327:907.860 - 0.514ms returns 4 (0x4) +T3F74 26327:907.880 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26327:907.899 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26327:908.309 Data: 00 00 00 00 +T3F74 26327:908.333 - 0.460ms returns 4 (0x4) +T3F74 26327:908.353 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26327:908.372 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26327:908.809 Data: 00 00 00 00 +T3F74 26327:908.832 - 0.487ms returns 4 (0x4) +T062C 26327:928.980 JLINK_IsHalted() +T062C 26327:930.076 - 1.110ms returns FALSE +T062C 26328:030.449 JLINK_HasError() +T062C 26328:030.536 JLINK_IsHalted() +T062C 26328:031.684 - 1.159ms returns FALSE +T062C 26328:132.710 JLINK_HasError() +T062C 26328:132.753 JLINK_IsHalted() +T062C 26328:133.810 - 1.075ms returns FALSE +T062C 26328:234.736 JLINK_HasError() +T062C 26328:234.781 JLINK_IsHalted() +T062C 26328:235.943 - 1.180ms returns FALSE +T062C 26328:336.834 JLINK_HasError() +T062C 26328:336.920 JLINK_IsHalted() +T062C 26328:338.113 - 1.212ms returns FALSE +T062C 26328:438.642 JLINK_HasError() +T062C 26328:438.689 JLINK_HasError() +T062C 26328:438.708 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26328:438.739 Data: 8D 12 74 01 +T062C 26328:438.764 Debug reg: DWT_CYCCNT +T062C 26328:438.787 - 0.087ms returns 1 (0x1) +T3F74 26328:441.552 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26328:441.585 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26328:442.643 Data: 00 00 80 00 +T3F74 26328:442.678 - 1.134ms returns 4 (0x4) +T3F74 26328:442.718 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26328:442.741 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26328:443.251 Data: 00 00 F0 01 +T3F74 26328:443.275 - 0.565ms returns 4 (0x4) +T3F74 26328:446.752 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26328:446.784 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26328:448.035 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26328:448.063 - 1.319ms returns 16 (0x10) +T3F74 26328:448.086 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26328:448.107 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26328:448.558 Data: 1F 00 00 00 +T3F74 26328:448.587 - 0.509ms returns 4 (0x4) +T3F74 26328:448.608 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26328:448.628 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26328:449.139 Data: 00 00 00 00 00 00 00 00 00 00 00 00 DB 02 00 00 ... +T3F74 26328:449.163 - 0.563ms returns 20 (0x14) +T3F74 26328:449.183 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26328:449.203 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26328:449.624 Data: 1F 03 00 00 +T3F74 26328:449.651 - 0.476ms returns 4 (0x4) +T3F74 26328:449.673 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26328:449.693 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26328:450.121 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26328:450.157 - 0.492ms returns 12 (0xC) +T3F74 26328:450.178 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26328:450.197 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26328:450.627 Data: 00 00 00 00 +T3F74 26328:450.650 - 0.480ms returns 4 (0x4) +T3F74 26328:450.670 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26328:450.689 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26328:451.122 Data: 00 00 00 00 +T3F74 26328:451.146 - 0.483ms returns 4 (0x4) +T3F74 26328:451.166 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26328:451.185 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26328:451.627 Data: 00 00 00 00 +T3F74 26328:451.651 - 0.492ms returns 4 (0x4) +T062C 26328:473.215 JLINK_IsHalted() +T062C 26328:474.437 - 1.240ms returns FALSE +T062C 26328:574.680 JLINK_HasError() +T062C 26328:574.766 JLINK_IsHalted() +T062C 26328:575.905 - 1.155ms returns FALSE +T062C 26328:676.100 JLINK_HasError() +T062C 26328:676.184 JLINK_IsHalted() +T062C 26328:677.475 - 1.337ms returns FALSE +T062C 26328:777.823 JLINK_HasError() +T062C 26328:777.868 JLINK_IsHalted() +T062C 26328:778.981 - 1.134ms returns FALSE +T062C 26328:879.452 JLINK_HasError() +T062C 26328:879.489 JLINK_IsHalted() +T062C 26328:880.596 - 1.134ms returns FALSE +T062C 26328:980.791 JLINK_HasError() +T062C 26328:980.829 JLINK_HasError() +T062C 26328:980.845 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26328:980.871 Data: 8D 12 74 01 +T062C 26328:980.892 Debug reg: DWT_CYCCNT +T062C 26328:980.910 - 0.072ms returns 1 (0x1) +T3F74 26328:983.744 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26328:983.778 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26328:984.823 Data: 00 00 80 00 +T3F74 26328:984.860 - 1.124ms returns 4 (0x4) +T3F74 26328:984.908 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26328:984.932 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26328:985.417 Data: 00 00 F0 01 +T3F74 26328:985.441 - 0.541ms returns 4 (0x4) +T3F74 26328:989.296 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26328:989.330 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26328:990.612 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26328:990.645 - 1.357ms returns 16 (0x10) +T3F74 26328:990.669 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26328:990.692 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26328:991.165 Data: 1E 00 00 00 +T3F74 26328:991.189 - 0.528ms returns 4 (0x4) +T3F74 26328:991.210 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26328:991.230 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26328:991.790 Data: 00 00 00 00 00 00 00 00 00 00 00 00 CF 02 00 00 ... +T3F74 26328:991.813 - 0.611ms returns 20 (0x14) +T3F74 26328:991.834 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26328:991.853 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26328:992.290 Data: 1F 03 00 00 +T3F74 26328:992.313 - 0.487ms returns 4 (0x4) +T3F74 26328:992.333 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26328:992.352 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26328:992.792 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26328:992.815 - 0.489ms returns 12 (0xC) +T3F74 26328:992.835 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26328:992.854 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26328:993.290 Data: 00 00 00 00 +T3F74 26328:993.313 - 0.486ms returns 4 (0x4) +T3F74 26328:993.333 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26328:993.352 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26328:993.789 Data: 00 00 00 00 +T3F74 26328:993.812 - 0.487ms returns 4 (0x4) +T3F74 26328:993.832 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26328:993.851 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26328:994.301 Data: 00 00 00 00 +T3F74 26328:994.324 - 0.500ms returns 4 (0x4) +T062C 26329:014.481 JLINK_IsHalted() +T062C 26329:015.657 - 1.200ms returns FALSE +T062C 26329:115.828 JLINK_HasError() +T062C 26329:115.930 JLINK_IsHalted() +T062C 26329:117.165 - 1.253ms returns FALSE +T062C 26329:218.490 JLINK_HasError() +T062C 26329:218.562 JLINK_IsHalted() +T062C 26329:219.721 - 1.201ms returns FALSE +T062C 26329:319.950 JLINK_HasError() +T062C 26329:319.986 JLINK_IsHalted() +T062C 26329:321.015 - 1.051ms returns FALSE +T062C 26329:422.159 JLINK_HasError() +T062C 26329:422.245 JLINK_IsHalted() +T062C 26329:423.464 - 1.238ms returns FALSE +T062C 26329:524.504 JLINK_HasError() +T062C 26329:524.588 JLINK_HasError() +T062C 26329:524.633 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26329:524.695 Data: 8D 12 74 01 +T062C 26329:524.741 Debug reg: DWT_CYCCNT +T062C 26329:524.763 - 0.137ms returns 1 (0x1) +T3F74 26329:527.087 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26329:527.122 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26329:528.319 Data: 00 00 80 00 +T3F74 26329:528.379 - 1.299ms returns 4 (0x4) +T3F74 26329:528.413 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26329:528.433 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26329:528.844 Data: 00 00 F0 01 +T3F74 26329:528.868 - 0.462ms returns 4 (0x4) +T3F74 26329:532.267 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26329:532.306 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26329:533.510 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26329:533.535 - 1.276ms returns 16 (0x10) +T3F74 26329:533.556 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26329:533.575 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26329:533.967 Data: 1E 00 00 00 +T3F74 26329:533.991 - 0.442ms returns 4 (0x4) +T3F74 26329:534.013 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26329:534.032 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26329:534.588 Data: 00 00 00 00 00 00 00 00 00 00 00 00 29 00 00 00 ... +T3F74 26329:534.608 - 0.602ms returns 20 (0x14) +T3F74 26329:534.626 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26329:534.642 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26329:535.221 Data: 1F 03 00 00 +T3F74 26329:535.247 - 0.629ms returns 4 (0x4) +T3F74 26329:535.268 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26329:535.289 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26329:535.723 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26329:535.746 - 0.486ms returns 12 (0xC) +T3F74 26329:535.767 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26329:535.786 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26329:536.223 Data: 00 00 00 00 +T3F74 26329:536.243 - 0.483ms returns 4 (0x4) +T3F74 26329:536.260 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26329:536.276 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26329:536.716 Data: 00 00 00 00 +T3F74 26329:536.736 - 0.483ms returns 4 (0x4) +T3F74 26329:536.753 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26329:536.770 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26329:537.215 Data: 00 00 00 00 +T3F74 26329:537.235 - 0.488ms returns 4 (0x4) +T062C 26329:548.920 JLINK_IsHalted() +T062C 26329:549.977 - 1.068ms returns FALSE +T062C 26329:650.398 JLINK_HasError() +T062C 26329:650.448 JLINK_IsHalted() +T062C 26329:651.516 - 1.110ms returns FALSE +T062C 26329:752.324 JLINK_HasError() +T062C 26329:752.370 JLINK_IsHalted() +T062C 26329:753.469 - 1.113ms returns FALSE +T062C 26329:854.227 JLINK_HasError() +T062C 26329:854.302 JLINK_IsHalted() +T062C 26329:855.344 - 1.076ms returns FALSE +T062C 26329:955.588 JLINK_HasError() +T062C 26329:955.675 JLINK_IsHalted() +T062C 26329:956.881 - 1.249ms returns FALSE +T062C 26330:057.816 JLINK_HasError() +T062C 26330:057.903 JLINK_HasError() +T062C 26330:057.938 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26330:057.968 Data: 8D 12 74 01 +T062C 26330:057.992 Debug reg: DWT_CYCCNT +T062C 26330:058.015 - 0.085ms returns 1 (0x1) +T3F74 26330:060.519 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26330:060.554 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26330:061.776 Data: 00 00 80 00 +T3F74 26330:061.821 - 1.310ms returns 4 (0x4) +T3F74 26330:061.861 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26330:061.884 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26330:062.276 Data: 00 00 F0 01 +T3F74 26330:062.300 - 0.447ms returns 4 (0x4) +T3F74 26330:066.488 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26330:066.518 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26330:067.792 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26330:067.824 - 1.344ms returns 16 (0x10) +T3F74 26330:067.851 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26330:067.873 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26330:068.274 Data: 1E 00 00 00 +T3F74 26330:068.297 - 0.454ms returns 4 (0x4) +T3F74 26330:068.318 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26330:068.337 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26330:068.905 Data: 00 00 00 00 00 00 00 00 00 00 00 00 81 01 00 00 ... +T3F74 26330:068.928 - 0.618ms returns 20 (0x14) +T3F74 26330:068.948 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26330:068.967 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26330:069.403 Data: 1F 03 00 00 +T3F74 26330:069.426 - 0.486ms returns 4 (0x4) +T3F74 26330:069.447 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26330:069.465 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26330:069.903 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26330:069.928 - 0.489ms returns 12 (0xC) +T3F74 26330:069.949 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26330:069.968 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26330:070.394 Data: 00 00 00 00 +T3F74 26330:070.414 - 0.471ms returns 4 (0x4) +T3F74 26330:070.431 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26330:070.447 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26330:070.897 Data: 00 00 00 00 +T3F74 26330:070.929 - 0.506ms returns 4 (0x4) +T3F74 26330:070.949 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26330:070.968 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26330:071.398 Data: 00 00 00 00 +T3F74 26330:071.422 - 0.481ms returns 4 (0x4) +T062C 26330:084.917 JLINK_IsHalted() +T062C 26330:086.105 - 1.208ms returns FALSE +T062C 26330:186.774 JLINK_HasError() +T062C 26330:186.860 JLINK_IsHalted() +T062C 26330:187.900 - 1.060ms returns FALSE +T062C 26330:288.984 JLINK_HasError() +T062C 26330:289.041 JLINK_IsHalted() +T062C 26330:290.149 - 1.127ms returns FALSE +T062C 26330:390.774 JLINK_HasError() +T062C 26330:390.865 JLINK_IsHalted() +T062C 26330:392.002 - 1.168ms returns FALSE +T062C 26330:492.715 JLINK_HasError() +T062C 26330:492.756 JLINK_IsHalted() +T062C 26330:493.982 - 1.268ms returns FALSE +T062C 26330:595.360 JLINK_HasError() +T062C 26330:595.530 JLINK_HasError() +T062C 26330:595.576 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26330:595.631 Data: 8D 12 74 01 +T062C 26330:595.655 Debug reg: DWT_CYCCNT +T062C 26330:595.677 - 0.108ms returns 1 (0x1) +T3F74 26330:598.289 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26330:598.327 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26330:599.455 Data: 00 00 80 00 +T3F74 26330:599.482 - 1.201ms returns 4 (0x4) +T3F74 26330:599.517 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26330:599.539 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26330:599.958 Data: 00 00 F0 01 +T3F74 26330:599.982 - 0.473ms returns 4 (0x4) +T3F74 26330:603.329 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26330:603.362 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26330:604.591 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26330:604.616 - 1.295ms returns 16 (0x10) +T3F74 26330:604.638 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26330:604.658 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26330:605.080 Data: 1E 00 00 00 +T3F74 26330:605.104 - 0.474ms returns 4 (0x4) +T3F74 26330:605.125 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26330:605.144 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26330:605.700 Data: 00 00 00 00 00 00 00 00 00 00 00 00 5B 00 00 00 ... +T3F74 26330:605.721 - 0.602ms returns 20 (0x14) +T3F74 26330:605.738 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26330:605.754 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26330:606.198 Data: 1F 03 00 00 +T3F74 26330:606.218 - 0.487ms returns 4 (0x4) +T3F74 26330:606.236 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26330:606.252 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26330:606.717 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26330:606.741 - 0.513ms returns 12 (0xC) +T3F74 26330:606.761 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26330:606.780 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26330:607.203 Data: 00 00 00 00 +T3F74 26330:607.227 - 0.474ms returns 4 (0x4) +T3F74 26330:607.248 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26330:607.267 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26330:607.702 Data: 00 00 00 00 +T3F74 26330:607.726 - 0.486ms returns 4 (0x4) +T3F74 26330:607.746 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26330:607.765 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26330:608.201 Data: 00 00 00 00 +T3F74 26330:608.224 - 0.485ms returns 4 (0x4) +T062C 26330:620.459 JLINK_IsHalted() +T062C 26330:621.640 - 1.226ms returns FALSE +T062C 26330:721.925 JLINK_HasError() +T062C 26330:721.971 JLINK_IsHalted() +T062C 26330:723.074 - 1.111ms returns FALSE +T062C 26330:823.179 JLINK_HasError() +T062C 26330:823.226 JLINK_IsHalted() +T062C 26330:824.348 - 1.150ms returns FALSE +T062C 26330:924.916 JLINK_HasError() +T062C 26330:924.964 JLINK_IsHalted() +T062C 26330:926.072 - 1.119ms returns FALSE +T062C 26331:026.271 JLINK_HasError() +T062C 26331:026.355 JLINK_IsHalted() +T062C 26331:027.624 - 1.287ms returns FALSE +T062C 26331:128.306 JLINK_HasError() +T062C 26331:128.352 JLINK_HasError() +T062C 26331:128.370 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26331:128.400 Data: 8D 12 74 01 +T062C 26331:128.424 Debug reg: DWT_CYCCNT +T062C 26331:128.447 - 0.085ms returns 1 (0x1) +T3F74 26331:133.829 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26331:133.869 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26331:134.931 Data: 00 00 80 00 +T3F74 26331:134.968 - 1.147ms returns 4 (0x4) +T3F74 26331:135.010 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26331:135.033 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26331:135.517 Data: 00 00 F0 01 +T3F74 26331:135.552 - 0.550ms returns 4 (0x4) +T3F74 26331:139.026 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26331:139.055 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26331:140.289 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26331:140.321 - 1.303ms returns 16 (0x10) +T3F74 26331:140.345 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26331:140.368 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26331:140.748 Data: 1E 00 00 00 +T3F74 26331:140.768 - 0.430ms returns 4 (0x4) +T3F74 26331:140.785 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26331:140.802 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26331:141.257 Data: 00 00 00 00 00 00 00 00 00 00 00 00 69 02 00 00 ... +T3F74 26331:141.277 - 0.498ms returns 20 (0x14) +T3F74 26331:141.294 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26331:141.310 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26331:141.748 Data: 1F 03 00 00 +T3F74 26331:141.768 - 0.481ms returns 4 (0x4) +T3F74 26331:141.785 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26331:141.801 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26331:142.408 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26331:142.452 - 0.674ms returns 12 (0xC) +T3F74 26331:142.477 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26331:142.500 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26331:143.029 Data: 00 00 00 00 +T3F74 26331:143.064 - 0.595ms returns 4 (0x4) +T3F74 26331:143.090 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26331:143.118 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26331:143.635 Data: 00 00 00 00 +T3F74 26331:143.664 - 0.583ms returns 4 (0x4) +T3F74 26331:143.687 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26331:143.708 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26331:144.130 Data: 00 00 00 00 +T3F74 26331:144.153 - 0.474ms returns 4 (0x4) +T062C 26331:157.120 JLINK_IsHalted() +T062C 26331:158.336 - 1.235ms returns FALSE +T062C 26331:258.536 JLINK_HasError() +T062C 26331:258.622 JLINK_IsHalted() +T062C 26331:259.846 - 1.265ms returns FALSE +T062C 26331:360.657 JLINK_HasError() +T062C 26331:360.733 JLINK_IsHalted() +T062C 26331:361.976 - 1.261ms returns FALSE +T062C 26331:462.599 JLINK_HasError() +T062C 26331:462.683 JLINK_IsHalted() +T062C 26331:463.908 - 1.241ms returns FALSE +T062C 26331:564.121 JLINK_HasError() +T062C 26331:564.218 JLINK_IsHalted() +T062C 26331:565.394 - 1.195ms returns FALSE +T062C 26331:666.227 JLINK_HasError() +T062C 26331:666.310 JLINK_HasError() +T062C 26331:666.328 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26331:666.357 Data: 8D 12 74 01 +T062C 26331:666.381 Debug reg: DWT_CYCCNT +T062C 26331:666.403 - 0.082ms returns 1 (0x1) +T3F74 26331:668.935 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26331:668.976 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26331:670.217 Data: 00 00 80 00 +T3F74 26331:670.271 - 1.344ms returns 4 (0x4) +T3F74 26331:670.322 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26331:670.346 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26331:671.495 Data: 00 00 F0 01 +T3F74 26331:671.529 - 1.214ms returns 4 (0x4) +T3F74 26331:675.316 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26331:675.350 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26331:676.600 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26331:676.630 - 1.321ms returns 16 (0x10) +T3F74 26331:676.654 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26331:676.676 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26331:677.205 Data: 1E 00 00 00 +T3F74 26331:677.230 - 0.584ms returns 4 (0x4) +T3F74 26331:677.251 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26331:677.271 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26331:677.808 Data: 00 00 00 00 00 00 00 00 00 00 00 00 A5 01 00 00 ... +T3F74 26331:677.831 - 0.588ms returns 20 (0x14) +T3F74 26331:677.852 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26331:677.871 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26331:678.321 Data: 1F 03 00 00 +T3F74 26331:678.363 - 0.519ms returns 4 (0x4) +T3F74 26331:678.391 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26331:678.416 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26331:678.940 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26331:678.969 - 0.586ms returns 12 (0xC) +T3F74 26331:678.991 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26331:679.012 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26331:679.436 Data: 00 00 00 00 +T3F74 26331:679.462 - 0.479ms returns 4 (0x4) +T3F74 26331:679.483 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26331:679.504 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26331:679.933 Data: 00 00 00 00 +T3F74 26331:679.957 - 0.481ms returns 4 (0x4) +T3F74 26331:679.977 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26331:679.997 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26331:680.458 Data: 00 00 00 00 +T3F74 26331:680.481 - 0.512ms returns 4 (0x4) +T062C 26331:695.425 JLINK_IsHalted() +T062C 26331:696.605 - 1.206ms returns FALSE +T062C 26331:797.678 JLINK_HasError() +T062C 26331:797.722 JLINK_IsHalted() +T062C 26331:798.807 - 1.102ms returns FALSE +T062C 26331:899.722 JLINK_HasError() +T062C 26331:899.766 JLINK_IsHalted() +T062C 26331:900.851 - 1.104ms returns FALSE +T062C 26332:001.690 JLINK_HasError() +T062C 26332:001.732 JLINK_IsHalted() +T062C 26332:002.804 - 1.107ms returns FALSE +T062C 26332:103.616 JLINK_HasError() +T062C 26332:103.672 JLINK_IsHalted() +T062C 26332:104.784 - 1.124ms returns FALSE +T062C 26332:205.748 JLINK_HasError() +T062C 26332:205.831 JLINK_HasError() +T062C 26332:205.875 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26332:205.937 Data: 8D 12 74 01 +T062C 26332:205.967 Debug reg: DWT_CYCCNT +T062C 26332:205.986 - 0.117ms returns 1 (0x1) +T3F74 26332:208.595 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26332:208.628 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26332:209.831 Data: 00 00 80 00 +T3F74 26332:209.941 - 1.367ms returns 4 (0x4) +T3F74 26332:210.026 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26332:210.052 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26332:211.196 Data: 00 00 F0 01 +T3F74 26332:211.274 - 1.268ms returns 4 (0x4) +T3F74 26332:215.158 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26332:215.192 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26332:216.417 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26332:216.446 - 1.295ms returns 16 (0x10) +T3F74 26332:216.467 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26332:216.487 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26332:216.860 Data: 1E 00 00 00 +T3F74 26332:216.880 - 0.420ms returns 4 (0x4) +T3F74 26332:216.898 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26332:216.915 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26332:217.359 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D5 02 00 00 ... +T3F74 26332:217.379 - 0.488ms returns 20 (0x14) +T3F74 26332:217.397 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26332:217.414 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26332:217.859 Data: 1F 03 00 00 +T3F74 26332:217.880 - 0.489ms returns 4 (0x4) +T3F74 26332:217.897 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26332:217.914 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26332:218.368 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26332:218.388 - 0.498ms returns 12 (0xC) +T3F74 26332:218.421 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26332:218.437 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26332:218.873 Data: 00 00 00 00 +T3F74 26332:218.898 - 0.484ms returns 4 (0x4) +T3F74 26332:218.918 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26332:218.937 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26332:219.361 Data: 00 00 00 00 +T3F74 26332:219.385 - 0.475ms returns 4 (0x4) +T3F74 26332:219.406 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26332:219.425 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26332:219.871 Data: 00 00 00 00 +T3F74 26332:219.891 - 0.492ms returns 4 (0x4) +T062C 26332:232.643 JLINK_IsHalted() +T062C 26332:233.883 - 1.282ms returns FALSE +T062C 26332:334.906 JLINK_HasError() +T062C 26332:334.946 JLINK_IsHalted() +T062C 26332:335.990 - 1.060ms returns FALSE +T062C 26332:436.127 JLINK_HasError() +T062C 26332:436.174 JLINK_IsHalted() +T062C 26332:437.219 - 1.052ms returns FALSE +T062C 26332:537.352 JLINK_HasError() +T062C 26332:537.398 JLINK_IsHalted() +T062C 26332:538.640 - 1.264ms returns FALSE +T062C 26332:638.842 JLINK_HasError() +T062C 26332:638.937 JLINK_IsHalted() +T062C 26332:640.074 - 1.148ms returns FALSE +T062C 26332:740.847 JLINK_HasError() +T062C 26332:740.890 JLINK_HasError() +T062C 26332:740.905 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26332:740.932 Data: 8D 12 74 01 +T062C 26332:740.952 Debug reg: DWT_CYCCNT +T062C 26332:740.971 - 0.072ms returns 1 (0x1) +T3F74 26332:743.930 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26332:743.974 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26332:745.061 Data: 00 00 80 00 +T3F74 26332:745.096 - 1.174ms returns 4 (0x4) +T3F74 26332:745.137 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26332:745.161 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26332:745.665 Data: 00 00 F0 01 +T3F74 26332:745.690 - 0.560ms returns 4 (0x4) +T3F74 26332:748.854 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26332:748.888 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26332:750.073 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26332:750.106 - 1.260ms returns 16 (0x10) +T3F74 26332:750.130 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26332:750.152 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26332:750.539 Data: 1E 00 00 00 +T3F74 26332:750.559 - 0.436ms returns 4 (0x4) +T3F74 26332:750.577 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26332:750.593 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26332:751.168 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1D 03 00 00 ... +T3F74 26332:751.193 - 0.624ms returns 20 (0x14) +T3F74 26332:751.214 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26332:751.234 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26332:751.665 Data: 1F 03 00 00 +T3F74 26332:751.688 - 0.482ms returns 4 (0x4) +T3F74 26332:751.709 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26332:751.728 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26332:752.300 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26332:752.324 - 0.623ms returns 12 (0xC) +T3F74 26332:752.344 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26332:752.363 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26332:752.794 Data: 00 00 00 00 +T3F74 26332:752.820 - 0.483ms returns 4 (0x4) +T3F74 26332:752.841 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26332:752.861 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26332:753.305 Data: 00 00 00 00 +T3F74 26332:753.348 - 0.515ms returns 4 (0x4) +T3F74 26332:753.375 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26332:753.399 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26332:754.042 Data: 00 00 00 00 +T3F74 26332:754.071 - 0.703ms returns 4 (0x4) +T062C 26332:766.096 JLINK_IsHalted() +T062C 26332:767.177 - 1.090ms returns FALSE +T062C 26332:867.916 JLINK_HasError() +T062C 26332:868.004 JLINK_IsHalted() +T062C 26332:869.213 - 1.227ms returns FALSE +T062C 26332:969.915 JLINK_HasError() +T062C 26332:969.962 JLINK_IsHalted() +T062C 26332:971.035 - 1.104ms returns FALSE +T062C 26333:071.610 JLINK_HasError() +T062C 26333:071.658 JLINK_IsHalted() +T062C 26333:072.783 - 1.137ms returns FALSE +T062C 26333:173.617 JLINK_HasError() +T062C 26333:173.664 JLINK_IsHalted() +T062C 26333:174.776 - 1.126ms returns FALSE +T062C 26333:275.670 JLINK_HasError() +T062C 26333:275.757 JLINK_HasError() +T062C 26333:275.776 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26333:275.806 Data: 8D 12 74 01 +T062C 26333:275.831 Debug reg: DWT_CYCCNT +T062C 26333:275.853 - 0.085ms returns 1 (0x1) +T3F74 26333:281.043 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26333:281.091 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26333:282.232 Data: 00 00 80 00 +T3F74 26333:282.258 - 1.223ms returns 4 (0x4) +T3F74 26333:282.291 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26333:282.312 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26333:282.881 Data: 00 00 F0 01 +T3F74 26333:282.933 - 0.650ms returns 4 (0x4) +T3F74 26333:286.780 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26333:286.816 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26333:287.992 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26333:288.022 - 1.250ms returns 16 (0x10) +T3F74 26333:288.045 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26333:288.067 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26333:288.470 Data: 1E 00 00 00 +T3F74 26333:288.493 - 0.456ms returns 4 (0x4) +T3F74 26333:288.514 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26333:288.533 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26333:289.095 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1F 03 00 00 ... +T3F74 26333:289.118 - 0.612ms returns 20 (0x14) +T3F74 26333:289.139 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26333:289.158 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26333:289.595 Data: 1F 03 00 00 +T3F74 26333:289.618 - 0.495ms returns 4 (0x4) +T3F74 26333:289.651 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26333:289.671 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26333:290.093 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26333:290.117 - 0.473ms returns 12 (0xC) +T3F74 26333:290.137 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26333:290.156 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26333:290.594 Data: 00 00 00 00 +T3F74 26333:290.617 - 0.488ms returns 4 (0x4) +T3F74 26333:290.637 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26333:290.656 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26333:291.218 Data: 00 00 00 00 +T3F74 26333:291.242 - 0.612ms returns 4 (0x4) +T3F74 26333:291.262 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26333:291.281 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26333:291.718 Data: 00 00 00 00 +T3F74 26333:291.741 - 0.487ms returns 4 (0x4) +T062C 26333:305.217 JLINK_IsHalted() +T062C 26333:306.366 - 1.180ms returns FALSE +T062C 26333:406.597 JLINK_HasError() +T062C 26333:406.652 JLINK_IsHalted() +T062C 26333:407.739 - 1.103ms returns FALSE +T062C 26333:507.942 JLINK_HasError() +T062C 26333:508.030 JLINK_IsHalted() +T062C 26333:509.191 - 1.209ms returns FALSE +T062C 26333:609.427 JLINK_HasError() +T062C 26333:609.513 JLINK_IsHalted() +T062C 26333:610.769 - 1.274ms returns FALSE +T062C 26333:711.553 JLINK_HasError() +T062C 26333:711.658 JLINK_IsHalted() +T062C 26333:712.653 - 1.038ms returns FALSE +T062C 26333:813.551 JLINK_HasError() +T062C 26333:813.600 JLINK_HasError() +T062C 26333:813.618 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26333:813.649 Data: 8D 12 74 01 +T062C 26333:813.672 Debug reg: DWT_CYCCNT +T062C 26333:813.694 - 0.084ms returns 1 (0x1) +T3F74 26333:816.218 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26333:816.258 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26333:817.375 Data: 00 00 80 00 +T3F74 26333:817.436 - 1.225ms returns 4 (0x4) +T3F74 26333:817.471 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26333:817.491 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26333:817.894 Data: 00 00 F0 01 +T3F74 26333:817.914 - 0.450ms returns 4 (0x4) +T3F74 26333:821.920 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26333:821.959 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26333:823.174 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26333:823.208 - 1.296ms returns 16 (0x10) +T3F74 26333:823.233 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26333:823.257 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26333:823.805 Data: 1E 00 00 00 +T3F74 26333:823.830 - 0.605ms returns 4 (0x4) +T3F74 26333:823.851 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26333:823.871 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26333:824.398 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B9 01 00 00 ... +T3F74 26333:824.419 - 0.575ms returns 20 (0x14) +T3F74 26333:824.437 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26333:824.454 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26333:824.896 Data: 1F 03 00 00 +T3F74 26333:824.916 - 0.486ms returns 4 (0x4) +T3F74 26333:824.934 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26333:824.951 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26333:825.396 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26333:825.417 - 0.489ms returns 12 (0xC) +T3F74 26333:825.434 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26333:825.451 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26333:825.906 Data: 00 00 00 00 +T3F74 26333:825.926 - 0.498ms returns 4 (0x4) +T3F74 26333:825.944 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26333:825.961 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26333:826.397 Data: 00 00 00 00 +T3F74 26333:826.417 - 0.480ms returns 4 (0x4) +T3F74 26333:826.435 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26333:826.451 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26333:826.896 Data: 00 00 00 00 +T3F74 26333:826.927 - 0.499ms returns 4 (0x4) +T062C 26333:838.923 JLINK_IsHalted() +T062C 26333:840.048 - 1.142ms returns FALSE +T062C 26333:940.343 JLINK_HasError() +T062C 26333:940.395 JLINK_IsHalted() +T062C 26333:941.541 - 1.178ms returns FALSE +T062C 26334:042.369 JLINK_HasError() +T062C 26334:042.411 JLINK_IsHalted() +T062C 26334:043.528 - 1.147ms returns FALSE +T062C 26334:144.350 JLINK_HasError() +T062C 26334:144.394 JLINK_IsHalted() +T062C 26334:145.497 - 1.119ms returns FALSE +T062C 26334:246.838 JLINK_HasError() +T062C 26334:246.882 JLINK_IsHalted() +T062C 26334:248.033 - 1.172ms returns FALSE +T062C 26334:349.069 JLINK_HasError() +T062C 26334:349.114 JLINK_HasError() +T062C 26334:349.133 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26334:349.162 Data: 8D 12 74 01 +T062C 26334:349.186 Debug reg: DWT_CYCCNT +T062C 26334:349.209 - 0.083ms returns 1 (0x1) +T3F74 26334:356.507 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26334:356.557 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26334:357.596 Data: 00 00 80 00 +T3F74 26334:357.623 - 1.124ms returns 4 (0x4) +T3F74 26334:357.659 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26334:357.680 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26334:358.099 Data: 00 00 F0 01 +T3F74 26334:358.144 - 0.493ms returns 4 (0x4) +T3F74 26334:366.169 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26334:366.209 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26334:367.468 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26334:367.495 - 1.334ms returns 16 (0x10) +T3F74 26334:367.517 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26334:367.538 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26334:367.960 Data: 1E 00 00 00 +T3F74 26334:367.996 - 0.487ms returns 4 (0x4) +T3F74 26334:368.023 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26334:368.064 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26334:368.585 Data: 00 00 00 00 00 00 00 00 00 00 00 00 31 01 00 00 ... +T3F74 26334:368.619 - 0.604ms returns 20 (0x14) +T3F74 26334:368.646 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26334:368.670 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26334:369.088 Data: 1F 03 00 00 +T3F74 26334:369.125 - 0.487ms returns 4 (0x4) +T3F74 26334:369.152 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26334:369.176 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26334:369.722 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26334:369.748 - 0.604ms returns 12 (0xC) +T3F74 26334:369.769 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26334:369.790 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26334:370.197 Data: 00 00 00 00 +T3F74 26334:370.334 - 0.573ms returns 4 (0x4) +T3F74 26334:370.355 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26334:370.375 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26334:370.831 Data: 00 00 00 00 +T3F74 26334:370.864 - 0.516ms returns 4 (0x4) +T3F74 26334:370.888 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26334:370.910 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26334:371.364 Data: 00 00 00 00 +T3F74 26334:371.399 - 0.519ms returns 4 (0x4) +T062C 26334:421.113 JLINK_IsHalted() +T062C 26334:422.208 - 1.108ms returns FALSE +T062C 26334:523.076 JLINK_HasError() +T062C 26334:523.128 JLINK_IsHalted() +T062C 26334:524.213 - 1.119ms returns FALSE +T062C 26334:624.840 JLINK_HasError() +T062C 26334:624.886 JLINK_IsHalted() +T062C 26334:625.934 - 1.060ms returns FALSE +T062C 26334:726.931 JLINK_HasError() +T062C 26334:727.033 JLINK_IsHalted() +T062C 26334:728.186 - 1.170ms returns FALSE +T062C 26334:828.462 JLINK_HasError() +T062C 26334:828.548 JLINK_IsHalted() +T062C 26334:829.765 - 1.265ms returns FALSE +T062C 26334:930.361 JLINK_HasError() +T062C 26334:930.447 JLINK_HasError() +T062C 26334:930.492 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26334:930.553 Data: 8D 12 74 01 +T062C 26334:930.599 Debug reg: DWT_CYCCNT +T062C 26334:930.621 - 0.144ms returns 1 (0x1) +T3F74 26334:933.293 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26334:933.330 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26334:934.527 Data: 00 00 80 00 +T3F74 26334:934.608 - 1.343ms returns 4 (0x4) +T3F74 26334:934.670 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26334:934.693 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26334:935.837 Data: 00 00 F0 01 +T3F74 26334:935.903 - 1.241ms returns 4 (0x4) +T3F74 26334:939.490 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26334:939.522 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26334:940.804 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26334:940.832 - 1.349ms returns 16 (0x10) +T3F74 26334:940.853 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26334:940.872 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26334:941.249 Data: 1F 00 00 00 +T3F74 26334:941.269 - 0.423ms returns 4 (0x4) +T3F74 26334:941.287 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26334:941.303 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26334:941.750 Data: 00 00 00 00 00 00 00 00 00 00 00 00 DB 02 00 00 ... +T3F74 26334:941.770 - 0.490ms returns 20 (0x14) +T3F74 26334:941.788 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26334:941.804 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26334:942.247 Data: 1F 03 00 00 +T3F74 26334:942.267 - 0.486ms returns 4 (0x4) +T3F74 26334:942.284 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26334:942.300 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26334:942.742 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26334:942.762 - 0.484ms returns 12 (0xC) +T3F74 26334:942.779 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26334:942.795 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26334:943.472 Data: 00 00 00 00 +T3F74 26334:943.511 - 0.740ms returns 4 (0x4) +T3F74 26334:943.536 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26334:943.559 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26334:944.707 Data: 00 00 00 00 +T3F74 26334:944.785 - 1.268ms returns 4 (0x4) +T3F74 26334:944.834 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26334:944.853 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26334:945.248 Data: 00 00 00 00 +T3F74 26334:945.268 - 0.440ms returns 4 (0x4) +T062C 26334:964.785 JLINK_IsHalted() +T062C 26334:965.885 - 1.117ms returns FALSE +T062C 26335:066.774 JLINK_HasError() +T062C 26335:066.818 JLINK_IsHalted() +T062C 26335:067.908 - 1.118ms returns FALSE +T062C 26335:168.737 JLINK_HasError() +T062C 26335:168.823 JLINK_IsHalted() +T062C 26335:169.914 - 1.109ms returns FALSE +T062C 26335:270.674 JLINK_HasError() +T062C 26335:270.721 JLINK_IsHalted() +T062C 26335:271.845 - 1.134ms returns FALSE +T062C 26335:372.636 JLINK_HasError() +T062C 26335:372.681 JLINK_IsHalted() +T062C 26335:373.700 - 1.027ms returns FALSE +T062C 26335:474.743 JLINK_HasError() +T062C 26335:474.829 JLINK_HasError() +T062C 26335:474.847 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26335:474.878 Data: 8D 12 74 01 +T062C 26335:474.902 Debug reg: DWT_CYCCNT +T062C 26335:474.924 - 0.085ms returns 1 (0x1) +T3F74 26335:478.781 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26335:478.828 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26335:479.946 Data: 00 00 80 00 +T3F74 26335:479.976 - 1.203ms returns 4 (0x4) +T3F74 26335:480.013 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26335:480.034 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26335:480.437 Data: 00 00 F0 01 +T3F74 26335:480.457 - 0.451ms returns 4 (0x4) +T3F74 26335:483.694 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26335:483.721 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26335:484.933 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26335:484.958 - 1.270ms returns 16 (0x10) +T3F74 26335:484.978 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26335:484.995 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26335:485.422 Data: 1E 00 00 00 +T3F74 26335:485.453 - 0.482ms returns 4 (0x4) +T3F74 26335:485.470 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26335:485.486 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26335:485.921 Data: 00 00 00 00 00 00 00 00 00 00 00 00 6D 01 00 00 ... +T3F74 26335:485.941 - 0.477ms returns 20 (0x14) +T3F74 26335:485.959 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26335:485.975 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26335:486.420 Data: 1F 03 00 00 +T3F74 26335:486.440 - 0.488ms returns 4 (0x4) +T3F74 26335:486.457 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26335:486.473 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26335:486.931 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26335:486.955 - 0.506ms returns 12 (0xC) +T3F74 26335:486.976 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26335:486.996 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26335:487.431 Data: 00 00 00 00 +T3F74 26335:487.454 - 0.486ms returns 4 (0x4) +T3F74 26335:487.475 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26335:487.494 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26335:488.057 Data: 00 00 00 00 +T3F74 26335:488.080 - 0.615ms returns 4 (0x4) +T3F74 26335:488.102 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26335:488.121 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26335:488.552 Data: 00 00 00 00 +T3F74 26335:488.576 - 0.481ms returns 4 (0x4) +T062C 26335:508.536 JLINK_IsHalted() +T062C 26335:509.711 - 1.186ms returns FALSE +T062C 26335:609.923 JLINK_HasError() +T062C 26335:610.011 JLINK_IsHalted() +T062C 26335:611.264 - 1.271ms returns FALSE +T062C 26335:712.041 JLINK_HasError() +T062C 26335:712.185 JLINK_IsHalted() +T062C 26335:713.295 - 1.128ms returns FALSE +T062C 26335:813.551 JLINK_HasError() +T062C 26335:813.635 JLINK_IsHalted() +T062C 26335:814.971 - 1.383ms returns FALSE +T062C 26335:915.238 JLINK_HasError() +T062C 26335:915.323 JLINK_IsHalted() +T062C 26335:916.598 - 1.293ms returns FALSE +T062C 26336:016.697 JLINK_HasError() +T062C 26336:016.738 JLINK_HasError() +T062C 26336:016.753 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26336:016.779 Data: 8D 12 74 01 +T062C 26336:016.799 Debug reg: DWT_CYCCNT +T062C 26336:016.818 - 0.071ms returns 1 (0x1) +T3F74 26336:019.259 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26336:019.293 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26336:020.508 Data: 00 00 80 00 +T3F74 26336:020.589 - 1.357ms returns 4 (0x4) +T3F74 26336:020.649 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26336:020.672 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26336:021.816 Data: 00 00 F0 01 +T3F74 26336:021.847 - 1.206ms returns 4 (0x4) +T3F74 26336:025.828 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26336:025.862 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26336:027.002 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26336:027.036 - 1.216ms returns 16 (0x10) +T3F74 26336:027.060 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26336:027.083 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26336:027.609 Data: 1E 00 00 00 +T3F74 26336:027.641 - 0.588ms returns 4 (0x4) +T3F74 26336:027.659 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26336:027.675 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26336:028.229 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B7 02 00 00 ... +T3F74 26336:028.249 - 0.597ms returns 20 (0x14) +T3F74 26336:028.267 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26336:028.283 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26336:028.727 Data: 1F 03 00 00 +T3F74 26336:028.747 - 0.487ms returns 4 (0x4) +T3F74 26336:028.764 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26336:028.780 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26336:029.229 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26336:029.249 - 0.491ms returns 12 (0xC) +T3F74 26336:029.265 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26336:029.288 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26336:029.727 Data: 00 00 00 00 +T3F74 26336:029.747 - 0.488ms returns 4 (0x4) +T3F74 26336:029.765 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26336:029.781 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26336:030.228 Data: 00 00 00 00 +T3F74 26336:030.248 - 0.490ms returns 4 (0x4) +T3F74 26336:030.266 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26336:030.281 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26336:030.746 Data: 00 00 00 00 +T3F74 26336:030.769 - 0.511ms returns 4 (0x4) +T062C 26336:044.345 JLINK_IsHalted() +T062C 26336:045.548 - 1.222ms returns FALSE +T062C 26336:145.797 JLINK_HasError() +T062C 26336:145.884 JLINK_IsHalted() +T062C 26336:147.114 - 1.256ms returns FALSE +T062C 26336:247.824 JLINK_HasError() +T062C 26336:247.866 JLINK_IsHalted() +T062C 26336:249.047 - 1.200ms returns FALSE +T062C 26336:349.854 JLINK_HasError() +T062C 26336:349.925 JLINK_IsHalted() +T062C 26336:350.976 - 1.086ms returns FALSE +T062C 26336:452.030 JLINK_HasError() +T062C 26336:452.115 JLINK_IsHalted() +T062C 26336:453.335 - 1.270ms returns FALSE +T062C 26336:554.427 JLINK_HasError() +T062C 26336:554.513 JLINK_HasError() +T062C 26336:554.557 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26336:554.618 Data: 8D 12 74 01 +T062C 26336:554.682 Debug reg: DWT_CYCCNT +T062C 26336:554.736 - 0.197ms returns 1 (0x1) +T3F74 26336:557.619 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26336:557.658 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26336:558.812 Data: 00 00 80 00 +T3F74 26336:558.892 - 1.300ms returns 4 (0x4) +T3F74 26336:558.951 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26336:558.975 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26336:560.118 Data: 00 00 F0 01 +T3F74 26336:560.195 - 1.264ms returns 4 (0x4) +T3F74 26336:563.460 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26336:563.487 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26336:564.732 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26336:564.762 - 1.318ms returns 16 (0x10) +T3F74 26336:564.794 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26336:564.817 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26336:565.283 Data: 1F 00 00 00 +T3F74 26336:565.306 - 0.523ms returns 4 (0x4) +T3F74 26336:565.329 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26336:565.349 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26336:565.915 Data: 00 00 00 00 00 00 00 00 00 00 00 00 17 02 00 00 ... +T3F74 26336:565.939 - 0.617ms returns 20 (0x14) +T3F74 26336:565.959 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26336:565.978 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26336:566.412 Data: 1F 03 00 00 +T3F74 26336:566.432 - 0.480ms returns 4 (0x4) +T3F74 26336:566.449 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26336:566.465 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26336:567.112 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26336:567.148 - 0.706ms returns 12 (0xC) +T3F74 26336:567.173 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26336:567.196 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26336:568.365 Data: 00 00 00 00 +T3F74 26336:568.445 - 1.291ms returns 4 (0x4) +T3F74 26336:568.494 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26336:568.513 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26336:568.902 Data: 00 00 00 00 +T3F74 26336:568.923 - 0.435ms returns 4 (0x4) +T3F74 26336:568.940 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26336:568.956 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26336:569.401 Data: 00 00 00 00 +T3F74 26336:569.421 - 0.488ms returns 4 (0x4) +T062C 26336:588.780 JLINK_IsHalted() +T062C 26336:589.919 - 1.157ms returns FALSE +T062C 26336:690.034 JLINK_HasError() +T062C 26336:690.078 JLINK_IsHalted() +T062C 26336:691.293 - 1.257ms returns FALSE +T062C 26336:791.927 JLINK_HasError() +T062C 26336:791.971 JLINK_IsHalted() +T062C 26336:793.160 - 1.230ms returns FALSE +T062C 26336:893.394 JLINK_HasError() +T062C 26336:893.480 JLINK_IsHalted() +T062C 26336:894.775 - 1.338ms returns FALSE +T062C 26336:995.533 JLINK_HasError() +T062C 26336:995.618 JLINK_IsHalted() +T062C 26336:996.846 - 1.270ms returns FALSE +T062C 26337:097.653 JLINK_HasError() +T062C 26337:097.734 JLINK_HasError() +T062C 26337:097.779 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26337:097.840 Data: 8D 12 74 01 +T062C 26337:097.876 Debug reg: DWT_CYCCNT +T062C 26337:097.898 - 0.127ms returns 1 (0x1) +T3F74 26337:100.190 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26337:100.223 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26337:101.465 Data: 00 00 80 00 +T3F74 26337:101.500 - 1.318ms returns 4 (0x4) +T3F74 26337:101.539 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26337:101.562 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26337:101.970 Data: 00 00 F0 01 +T3F74 26337:101.994 - 0.463ms returns 4 (0x4) +T3F74 26337:105.206 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26337:105.237 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26337:106.481 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26337:106.514 - 1.316ms returns 16 (0x10) +T3F74 26337:106.538 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26337:106.561 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26337:107.087 Data: 1E 00 00 00 +T3F74 26337:107.111 - 0.581ms returns 4 (0x4) +T3F74 26337:107.132 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26337:107.151 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26337:107.706 Data: 00 00 00 00 00 00 00 00 00 00 00 00 C9 01 00 00 ... +T3F74 26337:107.726 - 0.600ms returns 20 (0x14) +T3F74 26337:107.743 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26337:107.760 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26337:108.216 Data: 1F 03 00 00 +T3F74 26337:108.240 - 0.504ms returns 4 (0x4) +T3F74 26337:108.260 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26337:108.279 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26337:108.719 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26337:108.742 - 0.490ms returns 12 (0xC) +T3F74 26337:108.762 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26337:108.781 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26337:109.215 Data: 00 00 00 00 +T3F74 26337:109.238 - 0.484ms returns 4 (0x4) +T3F74 26337:109.258 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26337:109.277 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26337:109.712 Data: 00 00 00 00 +T3F74 26337:109.732 - 0.480ms returns 4 (0x4) +T3F74 26337:109.749 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26337:109.765 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26337:110.204 Data: 00 00 00 00 +T3F74 26337:110.225 - 0.482ms returns 4 (0x4) +T062C 26337:132.568 JLINK_IsHalted() +T062C 26337:133.625 - 1.075ms returns FALSE +T062C 26337:233.828 JLINK_HasError() +T062C 26337:233.916 JLINK_IsHalted() +T062C 26337:235.137 - 1.240ms returns FALSE +T062C 26337:335.661 JLINK_HasError() +T062C 26337:335.706 JLINK_IsHalted() +T062C 26337:336.865 - 1.176ms returns FALSE +T062C 26337:437.059 JLINK_HasError() +T062C 26337:437.145 JLINK_IsHalted() +T062C 26337:438.380 - 1.276ms returns FALSE +T062C 26337:538.601 JLINK_HasError() +T062C 26337:538.685 JLINK_IsHalted() +T062C 26337:540.059 - 1.416ms returns FALSE +T062C 26337:640.798 JLINK_HasError() +T062C 26337:640.858 JLINK_HasError() +T062C 26337:640.876 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26337:640.905 Data: 8D 12 74 01 +T062C 26337:640.929 Debug reg: DWT_CYCCNT +T062C 26337:640.951 - 0.082ms returns 1 (0x1) +T3F74 26337:643.455 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26337:643.488 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26337:644.548 Data: 00 00 80 00 +T3F74 26337:644.584 - 1.138ms returns 4 (0x4) +T3F74 26337:644.633 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26337:644.669 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26337:645.146 Data: 00 00 F0 01 +T3F74 26337:645.171 - 0.546ms returns 4 (0x4) +T3F74 26337:648.887 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26337:648.920 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26337:650.146 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26337:650.167 - 1.286ms returns 16 (0x10) +T3F74 26337:650.186 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26337:650.203 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26337:650.638 Data: 1F 00 00 00 +T3F74 26337:650.659 - 0.480ms returns 4 (0x4) +T3F74 26337:650.676 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26337:650.693 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26337:651.135 Data: 00 00 00 00 00 00 00 00 00 00 00 00 6B 00 00 00 ... +T3F74 26337:651.155 - 0.486ms returns 20 (0x14) +T3F74 26337:651.173 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26337:651.190 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26337:651.639 Data: 1F 03 00 00 +T3F74 26337:651.659 - 0.493ms returns 4 (0x4) +T3F74 26337:651.677 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26337:651.694 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26337:652.133 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26337:652.153 - 0.483ms returns 12 (0xC) +T3F74 26337:652.171 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26337:652.187 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26337:652.697 Data: 00 00 00 00 +T3F74 26337:652.721 - 0.558ms returns 4 (0x4) +T3F74 26337:652.742 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26337:652.762 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26337:653.143 Data: 00 00 00 00 +T3F74 26337:653.168 - 0.434ms returns 4 (0x4) +T3F74 26337:653.189 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26337:653.208 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26337:653.642 Data: 00 00 00 00 +T3F74 26337:653.666 - 0.485ms returns 4 (0x4) +T062C 26337:674.232 JLINK_IsHalted() +T062C 26337:675.278 - 1.064ms returns FALSE +T062C 26337:775.442 JLINK_HasError() +T062C 26337:775.523 JLINK_IsHalted() +T062C 26337:776.639 - 1.133ms returns FALSE +T062C 26337:876.831 JLINK_HasError() +T062C 26337:876.914 JLINK_IsHalted() +T062C 26337:878.123 - 1.226ms returns FALSE +T062C 26337:978.814 JLINK_HasError() +T062C 26337:978.897 JLINK_IsHalted() +T062C 26337:980.115 - 1.260ms returns FALSE +T062C 26338:080.668 JLINK_HasError() +T062C 26338:080.710 JLINK_IsHalted() +T062C 26338:081.905 - 1.213ms returns FALSE +T062C 26338:182.048 JLINK_HasError() +T062C 26338:182.133 JLINK_HasError() +T062C 26338:182.178 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26338:182.239 Data: 8D 12 74 01 +T062C 26338:182.277 Debug reg: DWT_CYCCNT +T062C 26338:182.295 - 0.123ms returns 1 (0x1) +T3F74 26338:184.766 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26338:184.802 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26338:185.913 Data: 00 00 80 00 +T3F74 26338:186.022 - 1.264ms returns 4 (0x4) +T3F74 26338:186.064 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26338:186.087 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26338:187.221 Data: 00 00 F0 01 +T3F74 26338:187.241 - 1.184ms returns 4 (0x4) +T3F74 26338:190.736 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26338:190.771 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26338:192.038 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26338:192.072 - 1.344ms returns 16 (0x10) +T3F74 26338:192.096 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26338:192.119 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26338:192.568 Data: 1E 00 00 00 +T3F74 26338:192.592 - 0.504ms returns 4 (0x4) +T3F74 26338:192.613 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26338:192.632 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26338:193.197 Data: 00 00 00 00 00 00 00 00 00 00 00 00 39 02 00 00 ... +T3F74 26338:193.217 - 0.611ms returns 20 (0x14) +T3F74 26338:193.240 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26338:193.261 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26338:193.692 Data: 1F 03 00 00 +T3F74 26338:193.715 - 0.482ms returns 4 (0x4) +T3F74 26338:193.736 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26338:193.755 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26338:194.192 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26338:194.216 - 0.488ms returns 12 (0xC) +T3F74 26338:194.236 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26338:194.255 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26338:194.693 Data: 00 00 00 00 +T3F74 26338:194.717 - 0.488ms returns 4 (0x4) +T3F74 26338:194.737 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26338:194.756 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26338:195.185 Data: 00 00 00 00 +T3F74 26338:195.205 - 0.474ms returns 4 (0x4) +T3F74 26338:195.222 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26338:195.238 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26338:195.714 Data: 00 00 00 00 +T3F74 26338:195.734 - 0.518ms returns 4 (0x4) +T062C 26338:214.063 JLINK_IsHalted() +T062C 26338:215.201 - 1.156ms returns FALSE +T062C 26338:315.410 JLINK_HasError() +T062C 26338:315.498 JLINK_IsHalted() +T062C 26338:316.669 - 1.189ms returns FALSE +T062C 26338:417.407 JLINK_HasError() +T062C 26338:417.473 JLINK_IsHalted() +T062C 26338:418.553 - 1.100ms returns FALSE +T062C 26338:519.153 JLINK_HasError() +T062C 26338:519.200 JLINK_IsHalted() +T062C 26338:520.431 - 1.272ms returns FALSE +T062C 26338:620.845 JLINK_HasError() +T062C 26338:620.925 JLINK_IsHalted() +T062C 26338:622.104 - 1.192ms returns FALSE +T062C 26338:722.351 JLINK_HasError() +T062C 26338:722.430 JLINK_HasError() +T062C 26338:722.474 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26338:722.533 Data: 8D 12 74 01 +T062C 26338:722.558 Debug reg: DWT_CYCCNT +T062C 26338:722.580 - 0.114ms returns 1 (0x1) +T3F74 26338:725.169 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26338:725.206 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26338:726.403 Data: 00 00 80 00 +T3F74 26338:726.438 - 1.276ms returns 4 (0x4) +T3F74 26338:726.477 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26338:726.500 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26338:727.713 Data: 00 00 F0 01 +T3F74 26338:727.779 - 1.309ms returns 4 (0x4) +T3F74 26338:730.811 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26338:730.843 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26338:732.015 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26338:732.048 - 1.246ms returns 16 (0x10) +T3F74 26338:732.073 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26338:732.096 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26338:732.500 Data: 1F 00 00 00 +T3F74 26338:732.520 - 0.454ms returns 4 (0x4) +T3F74 26338:732.538 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26338:732.555 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26338:732.990 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1B 02 00 00 ... +T3F74 26338:733.011 - 0.480ms returns 20 (0x14) +T3F74 26338:733.029 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26338:733.045 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26338:733.642 Data: 1F 03 00 00 +T3F74 26338:733.669 - 0.648ms returns 4 (0x4) +T3F74 26338:733.691 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26338:733.714 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26338:734.246 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26338:734.270 - 0.588ms returns 12 (0xC) +T3F74 26338:734.291 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26338:734.311 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26338:734.751 Data: 00 00 00 00 +T3F74 26338:734.775 - 0.492ms returns 4 (0x4) +T3F74 26338:734.796 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26338:734.816 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26338:735.251 Data: 00 00 00 00 +T3F74 26338:735.340 - 0.551ms returns 4 (0x4) +T3F74 26338:735.359 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26338:735.376 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26338:735.743 Data: 00 00 00 00 +T3F74 26338:735.764 - 0.412ms returns 4 (0x4) +T062C 26338:754.894 JLINK_IsHalted() +T062C 26338:756.004 - 1.128ms returns FALSE +T062C 26338:856.872 JLINK_HasError() +T062C 26338:856.958 JLINK_IsHalted() +T062C 26338:858.016 - 1.083ms returns FALSE +T062C 26338:958.136 JLINK_HasError() +T062C 26338:958.174 JLINK_IsHalted() +T062C 26338:959.311 - 1.178ms returns FALSE +T062C 26339:060.872 JLINK_HasError() +T062C 26339:060.948 JLINK_IsHalted() +T062C 26339:062.161 - 1.234ms returns FALSE +T062C 26339:163.123 JLINK_HasError() +T062C 26339:163.205 JLINK_IsHalted() +T062C 26339:164.325 - 1.127ms returns FALSE +T062C 26339:264.567 JLINK_HasError() +T062C 26339:264.607 JLINK_HasError() +T062C 26339:264.626 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26339:264.657 Data: 8D 12 74 01 +T062C 26339:264.681 Debug reg: DWT_CYCCNT +T062C 26339:264.703 - 0.085ms returns 1 (0x1) +T3F74 26339:267.219 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26339:267.258 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26339:268.345 Data: 00 00 80 00 +T3F74 26339:268.400 - 1.190ms returns 4 (0x4) +T3F74 26339:268.440 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26339:268.464 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26339:268.923 Data: 00 00 F0 01 +T3F74 26339:268.948 - 0.516ms returns 4 (0x4) +T3F74 26339:272.436 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26339:272.467 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26339:273.692 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26339:273.725 - 1.296ms returns 16 (0x10) +T3F74 26339:273.748 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26339:273.771 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26339:274.174 Data: 1E 00 00 00 +T3F74 26339:274.199 - 0.458ms returns 4 (0x4) +T3F74 26339:274.219 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26339:274.239 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26339:274.799 Data: 00 00 00 00 00 00 00 00 00 00 00 00 8D 02 00 00 ... +T3F74 26339:274.824 - 0.613ms returns 20 (0x14) +T3F74 26339:274.845 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26339:274.865 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26339:275.308 Data: 1F 03 00 00 +T3F74 26339:275.332 - 0.494ms returns 4 (0x4) +T3F74 26339:275.353 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26339:275.372 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26339:275.800 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26339:275.824 - 0.479ms returns 12 (0xC) +T3F74 26339:275.845 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26339:275.864 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26339:276.299 Data: 00 00 00 00 +T3F74 26339:276.323 - 0.487ms returns 4 (0x4) +T3F74 26339:276.345 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26339:276.364 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26339:276.798 Data: 00 00 00 00 +T3F74 26339:276.822 - 0.485ms returns 4 (0x4) +T3F74 26339:276.842 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26339:276.861 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26339:277.297 Data: 00 00 00 00 +T3F74 26339:277.321 - 0.487ms returns 4 (0x4) +T062C 26339:298.328 JLINK_IsHalted() +T062C 26339:299.506 - 1.225ms returns FALSE +T062C 26339:400.484 JLINK_HasError() +T062C 26339:400.566 JLINK_IsHalted() +T062C 26339:401.754 - 1.237ms returns FALSE +T062C 26339:502.663 JLINK_HasError() +T062C 26339:502.758 JLINK_IsHalted() +T062C 26339:503.785 - 1.046ms returns FALSE +T062C 26339:604.543 JLINK_HasError() +T062C 26339:604.630 JLINK_IsHalted() +T062C 26339:605.818 - 1.208ms returns FALSE +T062C 26339:706.848 JLINK_HasError() +T062C 26339:706.929 JLINK_IsHalted() +T062C 26339:708.083 - 1.197ms returns FALSE +T062C 26339:808.277 JLINK_HasError() +T062C 26339:808.353 JLINK_HasError() +T062C 26339:808.392 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26339:808.426 Data: 8D 12 74 01 +T062C 26339:808.450 Debug reg: DWT_CYCCNT +T062C 26339:808.472 - 0.087ms returns 1 (0x1) +T3F74 26339:810.951 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26339:810.984 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26339:812.206 Data: 00 00 80 00 +T3F74 26339:812.266 - 1.322ms returns 4 (0x4) +T3F74 26339:812.300 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26339:812.319 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26339:812.725 Data: 00 00 F0 01 +T3F74 26339:812.745 - 0.452ms returns 4 (0x4) +T3F74 26339:815.724 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26339:815.753 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26339:817.024 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26339:817.053 - 1.335ms returns 16 (0x10) +T3F74 26339:817.073 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26339:817.093 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26339:817.481 Data: 1F 00 00 00 +T3F74 26339:817.506 - 0.440ms returns 4 (0x4) +T3F74 26339:817.527 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26339:817.546 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26339:818.109 Data: 00 00 00 00 00 00 00 00 00 00 00 00 69 01 00 00 ... +T3F74 26339:818.134 - 0.615ms returns 20 (0x14) +T3F74 26339:818.154 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26339:818.174 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26339:818.608 Data: 1F 03 00 00 +T3F74 26339:818.632 - 0.490ms returns 4 (0x4) +T3F74 26339:818.656 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26339:818.672 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26339:819.102 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26339:819.123 - 0.473ms returns 12 (0xC) +T3F74 26339:819.140 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26339:819.157 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26339:819.601 Data: 00 00 00 00 +T3F74 26339:819.622 - 0.488ms returns 4 (0x4) +T3F74 26339:819.639 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26339:819.656 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26339:820.102 Data: 00 00 00 00 +T3F74 26339:820.122 - 0.489ms returns 4 (0x4) +T3F74 26339:820.140 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26339:820.157 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26339:820.595 Data: 00 00 00 00 +T3F74 26339:820.616 - 0.483ms returns 4 (0x4) +T062C 26339:840.169 JLINK_IsHalted() +T062C 26339:841.291 - 1.141ms returns FALSE +T062C 26339:941.545 JLINK_HasError() +T062C 26339:941.630 JLINK_IsHalted() +T062C 26339:942.832 - 1.243ms returns FALSE +T062C 26340:043.557 JLINK_HasError() +T062C 26340:043.587 JLINK_IsHalted() +T062C 26340:044.903 - 1.360ms returns FALSE +T062C 26340:145.161 JLINK_HasError() +T062C 26340:145.233 JLINK_IsHalted() +T062C 26340:146.310 - 1.085ms returns FALSE +T062C 26340:247.112 JLINK_HasError() +T062C 26340:247.166 JLINK_IsHalted() +T062C 26340:248.287 - 1.139ms returns FALSE +T062C 26340:349.041 JLINK_HasError() +T062C 26340:349.112 JLINK_HasError() +T062C 26340:349.131 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26340:349.159 Data: 8D 12 74 01 +T062C 26340:349.184 Debug reg: DWT_CYCCNT +T062C 26340:349.206 - 0.082ms returns 1 (0x1) +T3F74 26340:351.669 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26340:351.706 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26340:352.871 Data: 00 00 80 00 +T3F74 26340:352.940 - 1.278ms returns 4 (0x4) +T3F74 26340:352.983 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26340:353.003 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26340:353.403 Data: 00 00 F0 01 +T3F74 26340:353.424 - 0.447ms returns 4 (0x4) +T3F74 26340:356.401 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26340:356.440 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26340:357.685 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26340:357.731 - 1.339ms returns 16 (0x10) +T3F74 26340:357.769 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26340:357.792 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26340:358.284 Data: 1E 00 00 00 +T3F74 26340:358.308 - 0.547ms returns 4 (0x4) +T3F74 26340:358.331 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26340:358.351 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26340:359.051 Data: 00 00 00 00 00 00 00 00 00 00 00 00 53 00 00 00 ... +T3F74 26340:359.078 - 0.755ms returns 20 (0x14) +T3F74 26340:359.113 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26340:359.133 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26340:359.533 Data: 1F 03 00 00 +T3F74 26340:359.559 - 0.454ms returns 4 (0x4) +T3F74 26340:359.584 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26340:359.603 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26340:360.030 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26340:360.053 - 0.477ms returns 12 (0xC) +T3F74 26340:360.076 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26340:360.095 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26340:360.533 Data: 00 00 00 00 +T3F74 26340:360.556 - 0.487ms returns 4 (0x4) +T3F74 26340:360.578 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26340:360.598 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26340:361.033 Data: 00 00 00 00 +T3F74 26340:361.057 - 0.486ms returns 4 (0x4) +T3F74 26340:361.079 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26340:361.098 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26340:361.528 Data: 00 00 00 00 +T3F74 26340:361.551 - 0.482ms returns 4 (0x4) +T062C 26340:380.834 JLINK_IsHalted() +T062C 26340:381.997 - 1.205ms returns FALSE +T062C 26340:482.744 JLINK_HasError() +T062C 26340:482.782 JLINK_IsHalted() +T062C 26340:483.908 - 1.168ms returns FALSE +T062C 26340:584.303 JLINK_HasError() +T062C 26340:584.348 JLINK_IsHalted() +T062C 26340:585.401 - 1.072ms returns FALSE +T062C 26340:686.094 JLINK_HasError() +T062C 26340:686.136 JLINK_IsHalted() +T062C 26340:687.349 - 1.231ms returns FALSE +T062C 26340:787.658 JLINK_HasError() +T062C 26340:787.710 JLINK_IsHalted() +T062C 26340:788.864 - 1.200ms returns FALSE +T062C 26340:889.527 JLINK_HasError() +T062C 26340:889.618 JLINK_HasError() +T062C 26340:889.636 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26340:889.667 Data: 8D 12 74 01 +T062C 26340:889.691 Debug reg: DWT_CYCCNT +T062C 26340:889.713 - 0.085ms returns 1 (0x1) +T3F74 26340:892.088 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26340:892.128 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26340:893.223 Data: 00 00 80 00 +T3F74 26340:893.249 - 1.168ms returns 4 (0x4) +T3F74 26340:893.281 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26340:893.301 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26340:893.709 Data: 00 00 F0 01 +T3F74 26340:893.733 - 0.460ms returns 4 (0x4) +T3F74 26340:896.920 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26340:896.952 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26340:898.110 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26340:898.134 - 1.221ms returns 16 (0x10) +T3F74 26340:898.154 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26340:898.174 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26340:898.595 Data: 1E 00 00 00 +T3F74 26340:898.615 - 0.467ms returns 4 (0x4) +T3F74 26340:898.633 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26340:898.649 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26340:899.204 Data: 00 00 00 00 00 00 00 00 00 00 00 00 F1 02 00 00 ... +T3F74 26340:899.224 - 0.598ms returns 20 (0x14) +T3F74 26340:899.241 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26340:899.258 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26340:899.714 Data: 1F 03 00 00 +T3F74 26340:899.738 - 0.504ms returns 4 (0x4) +T3F74 26340:899.758 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26340:899.778 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26340:900.338 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26340:900.361 - 0.611ms returns 12 (0xC) +T3F74 26340:900.382 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26340:900.401 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26340:900.839 Data: 00 00 00 00 +T3F74 26340:900.859 - 0.484ms returns 4 (0x4) +T3F74 26340:900.876 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26340:900.893 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26340:901.326 Data: 00 00 00 00 +T3F74 26340:901.346 - 0.476ms returns 4 (0x4) +T3F74 26340:901.363 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26340:901.379 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26340:901.825 Data: 00 00 00 00 +T3F74 26340:901.845 - 0.488ms returns 4 (0x4) +T062C 26340:913.904 JLINK_IsHalted() +T062C 26340:915.026 - 1.140ms returns FALSE +T062C 26341:015.295 JLINK_HasError() +T062C 26341:015.379 JLINK_IsHalted() +T062C 26341:016.538 - 1.177ms returns FALSE +T062C 26341:117.331 JLINK_HasError() +T062C 26341:117.416 JLINK_IsHalted() +T062C 26341:118.793 - 1.397ms returns FALSE +T062C 26341:219.053 JLINK_HasError() +T062C 26341:219.134 JLINK_IsHalted() +T062C 26341:220.254 - 1.150ms returns FALSE +T062C 26341:321.102 JLINK_HasError() +T062C 26341:321.188 JLINK_IsHalted() +T062C 26341:322.381 - 1.238ms returns FALSE +T062C 26341:423.244 JLINK_HasError() +T062C 26341:423.327 JLINK_HasError() +T062C 26341:423.371 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26341:423.433 Data: 8D 12 74 01 +T062C 26341:423.491 Debug reg: DWT_CYCCNT +T062C 26341:423.526 - 0.163ms returns 1 (0x1) +T3F74 26341:426.155 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26341:426.188 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26341:427.346 Data: 00 00 80 00 +T3F74 26341:427.380 - 1.232ms returns 4 (0x4) +T3F74 26341:427.419 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26341:427.442 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26341:427.897 Data: 00 00 F0 01 +T3F74 26341:427.921 - 0.510ms returns 4 (0x4) +T3F74 26341:431.123 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26341:431.149 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26341:432.268 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26341:432.293 - 1.177ms returns 16 (0x10) +T3F74 26341:432.328 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26341:432.346 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26341:432.762 Data: 1E 00 00 00 +T3F74 26341:432.786 - 0.466ms returns 4 (0x4) +T3F74 26341:432.809 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26341:432.829 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26341:433.391 Data: 00 00 00 00 00 00 00 00 00 00 00 00 3F 02 00 00 ... +T3F74 26341:433.415 - 0.613ms returns 20 (0x14) +T3F74 26341:433.447 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26341:433.466 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26341:433.890 Data: 1F 03 00 00 +T3F74 26341:433.914 - 0.475ms returns 4 (0x4) +T3F74 26341:433.938 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26341:433.957 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26341:434.395 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26341:434.420 - 0.490ms returns 12 (0xC) +T3F74 26341:434.442 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26341:434.461 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26341:434.890 Data: 00 00 00 00 +T3F74 26341:434.914 - 0.480ms returns 4 (0x4) +T3F74 26341:434.937 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26341:434.956 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26341:435.394 Data: 00 00 00 00 +T3F74 26341:435.417 - 0.488ms returns 4 (0x4) +T3F74 26341:435.440 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26341:435.459 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26341:435.890 Data: 00 00 00 00 +T3F74 26341:435.914 - 0.482ms returns 4 (0x4) +T062C 26341:448.109 JLINK_IsHalted() +T062C 26341:449.150 - 1.060ms returns FALSE +T062C 26341:550.336 JLINK_HasError() +T062C 26341:550.506 JLINK_IsHalted() +T062C 26341:551.651 - 1.156ms returns FALSE +T062C 26341:652.709 JLINK_HasError() +T062C 26341:652.782 JLINK_IsHalted() +T062C 26341:653.850 - 1.090ms returns FALSE +T062C 26341:754.047 JLINK_HasError() +T062C 26341:754.093 JLINK_IsHalted() +T062C 26341:755.157 - 1.107ms returns FALSE +T062C 26341:856.326 JLINK_HasError() +T062C 26341:856.404 JLINK_IsHalted() +T062C 26341:857.677 - 1.290ms returns FALSE +T062C 26341:958.571 JLINK_HasError() +T062C 26341:958.655 JLINK_HasError() +T062C 26341:958.699 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26341:958.762 Data: 8D 12 74 01 +T062C 26341:958.797 Debug reg: DWT_CYCCNT +T062C 26341:958.819 - 0.128ms returns 1 (0x1) +T3F74 26341:961.475 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26341:961.512 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26341:962.638 Data: 00 00 80 00 +T3F74 26341:962.673 - 1.206ms returns 4 (0x4) +T3F74 26341:962.715 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26341:962.738 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26341:963.196 Data: 00 00 F0 01 +T3F74 26341:963.220 - 0.513ms returns 4 (0x4) +T3F74 26341:966.312 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26341:966.339 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26341:967.574 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26341:967.599 - 1.295ms returns 16 (0x10) +T3F74 26341:967.621 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26341:967.641 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26341:968.065 Data: 1F 00 00 00 +T3F74 26341:968.088 - 0.481ms returns 4 (0x4) +T3F74 26341:968.112 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26341:968.129 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26341:968.695 Data: 00 00 00 00 00 00 00 00 00 00 00 00 15 00 00 00 ... +T3F74 26341:968.718 - 0.614ms returns 20 (0x14) +T3F74 26341:968.740 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26341:968.761 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26341:969.189 Data: 1F 03 00 00 +T3F74 26341:969.213 - 0.480ms returns 4 (0x4) +T3F74 26341:969.233 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26341:969.252 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26341:969.689 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26341:969.709 - 0.482ms returns 12 (0xC) +T3F74 26341:969.726 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26341:969.742 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26341:970.184 Data: 00 00 00 00 +T3F74 26341:970.204 - 0.484ms returns 4 (0x4) +T3F74 26341:970.221 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26341:970.237 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26341:970.827 Data: 00 00 00 00 +T3F74 26341:970.860 - 0.647ms returns 4 (0x4) +T3F74 26341:970.882 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26341:970.902 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26341:971.316 Data: 00 00 00 00 +T3F74 26341:971.340 - 0.466ms returns 4 (0x4) +T062C 26341:991.210 JLINK_IsHalted() +T062C 26341:992.325 - 1.133ms returns FALSE +T062C 26342:092.807 JLINK_HasError() +T062C 26342:092.891 JLINK_IsHalted() +T062C 26342:094.189 - 1.340ms returns FALSE +T062C 26342:194.430 JLINK_HasError() +T062C 26342:194.483 JLINK_IsHalted() +T062C 26342:195.550 - 1.086ms returns FALSE +T062C 26342:296.265 JLINK_HasError() +T062C 26342:296.306 JLINK_IsHalted() +T062C 26342:297.427 - 1.141ms returns FALSE +T062C 26342:397.627 JLINK_HasError() +T062C 26342:397.705 JLINK_IsHalted() +T062C 26342:398.893 - 1.230ms returns FALSE +T062C 26342:499.700 JLINK_HasError() +T062C 26342:499.795 JLINK_HasError() +T062C 26342:499.833 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26342:499.863 Data: 8D 12 74 01 +T062C 26342:499.887 Debug reg: DWT_CYCCNT +T062C 26342:499.909 - 0.083ms returns 1 (0x1) +T3F74 26342:502.191 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26342:502.223 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26342:503.392 Data: 00 00 80 00 +T3F74 26342:503.448 - 1.265ms returns 4 (0x4) +T3F74 26342:503.487 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26342:503.510 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26342:504.613 Data: 00 00 F0 01 +T3F74 26342:504.634 - 1.153ms returns 4 (0x4) +T3F74 26342:507.955 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26342:507.982 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26342:509.169 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26342:509.197 - 1.249ms returns 16 (0x10) +T3F74 26342:509.218 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26342:509.237 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26342:509.617 Data: 1E 00 00 00 +T3F74 26342:509.638 - 0.426ms returns 4 (0x4) +T3F74 26342:509.655 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26342:509.672 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26342:510.118 Data: 00 00 00 00 00 00 00 00 00 00 00 00 F9 01 00 00 ... +T3F74 26342:510.138 - 0.490ms returns 20 (0x14) +T3F74 26342:510.155 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26342:510.172 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26342:510.617 Data: 1F 03 00 00 +T3F74 26342:510.637 - 0.487ms returns 4 (0x4) +T3F74 26342:510.654 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26342:510.670 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26342:511.119 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26342:511.143 - 0.497ms returns 12 (0xC) +T3F74 26342:511.163 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26342:511.182 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26342:511.626 Data: 00 00 00 00 +T3F74 26342:511.650 - 0.494ms returns 4 (0x4) +T3F74 26342:511.670 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26342:511.689 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26342:512.123 Data: 00 00 00 00 +T3F74 26342:512.146 - 0.484ms returns 4 (0x4) +T3F74 26342:512.166 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26342:512.185 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26342:512.622 Data: 00 00 00 00 +T3F74 26342:512.649 - 0.489ms returns 4 (0x4) +T062C 26342:531.889 JLINK_IsHalted() +T062C 26342:532.365 - 0.485ms returns FALSE +T062C 26342:632.490 JLINK_HasError() +T062C 26342:632.581 JLINK_IsHalted() +T062C 26342:633.751 - 1.189ms returns FALSE +T062C 26342:734.778 JLINK_HasError() +T062C 26342:734.864 JLINK_IsHalted() +T062C 26342:735.982 - 1.142ms returns FALSE +T062C 26342:836.157 JLINK_HasError() +T062C 26342:836.242 JLINK_IsHalted() +T062C 26342:837.454 - 1.260ms returns FALSE +T062C 26342:937.876 JLINK_HasError() +T062C 26342:937.921 JLINK_IsHalted() +T062C 26342:939.068 - 1.197ms returns FALSE +T062C 26343:040.060 JLINK_HasError() +T062C 26343:040.142 JLINK_HasError() +T062C 26343:040.187 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26343:040.242 Data: 8D 12 74 01 +T062C 26343:040.268 Debug reg: DWT_CYCCNT +T062C 26343:040.290 - 0.111ms returns 1 (0x1) +T3F74 26343:042.822 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26343:042.854 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26343:044.028 Data: 00 00 80 00 +T3F74 26343:044.063 - 1.249ms returns 4 (0x4) +T3F74 26343:044.103 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26343:044.126 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26343:044.715 Data: 00 00 F0 01 +T3F74 26343:044.739 - 0.644ms returns 4 (0x4) +T3F74 26343:048.255 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26343:048.282 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26343:049.425 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26343:049.453 - 1.205ms returns 16 (0x10) +T3F74 26343:049.474 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26343:049.493 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26343:049.934 Data: 1E 00 00 00 +T3F74 26343:049.957 - 0.491ms returns 4 (0x4) +T3F74 26343:049.979 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26343:050.005 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26343:050.555 Data: 00 00 00 00 00 00 00 00 00 00 00 00 71 00 00 00 ... +T3F74 26343:050.579 - 0.607ms returns 20 (0x14) +T3F74 26343:050.599 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26343:050.618 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26343:051.051 Data: 1F 03 00 00 +T3F74 26343:051.074 - 0.483ms returns 4 (0x4) +T3F74 26343:051.096 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26343:051.115 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26343:051.574 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26343:051.594 - 0.504ms returns 12 (0xC) +T3F74 26343:051.611 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26343:051.627 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26343:052.044 Data: 00 00 00 00 +T3F74 26343:052.064 - 0.459ms returns 4 (0x4) +T3F74 26343:052.081 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26343:052.097 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26343:052.544 Data: 00 00 00 00 +T3F74 26343:052.564 - 0.490ms returns 4 (0x4) +T3F74 26343:052.581 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26343:052.598 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26343:053.044 Data: 00 00 00 00 +T3F74 26343:053.064 - 0.490ms returns 4 (0x4) +T062C 26343:065.404 JLINK_IsHalted() +T062C 26343:066.430 - 1.044ms returns FALSE +T062C 26343:166.883 JLINK_HasError() +T062C 26343:166.923 JLINK_IsHalted() +T062C 26343:168.069 - 1.164ms returns FALSE +T062C 26343:268.973 JLINK_HasError() +T062C 26343:269.029 JLINK_IsHalted() +T062C 26343:270.260 - 1.249ms returns FALSE +T062C 26343:370.511 JLINK_HasError() +T062C 26343:370.593 JLINK_IsHalted() +T062C 26343:371.705 - 1.130ms returns FALSE +T062C 26343:472.432 JLINK_HasError() +T062C 26343:472.518 JLINK_IsHalted() +T062C 26343:473.706 - 1.231ms returns FALSE +T062C 26343:574.502 JLINK_HasError() +T062C 26343:574.586 JLINK_HasError() +T062C 26343:574.605 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26343:574.633 Data: 8D 12 74 01 +T062C 26343:574.658 Debug reg: DWT_CYCCNT +T062C 26343:574.680 - 0.083ms returns 1 (0x1) +T3F74 26343:577.085 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26343:577.118 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26343:578.247 Data: 00 00 80 00 +T3F74 26343:578.283 - 1.208ms returns 4 (0x4) +T3F74 26343:578.630 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26343:578.659 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26343:579.107 Data: 00 00 F0 01 +T3F74 26343:579.134 - 0.514ms returns 4 (0x4) +T3F74 26343:582.541 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26343:582.574 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26343:583.780 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26343:583.808 - 1.273ms returns 16 (0x10) +T3F74 26343:583.829 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26343:583.848 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26343:584.225 Data: 1E 00 00 00 +T3F74 26343:584.246 - 0.424ms returns 4 (0x4) +T3F74 26343:584.263 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26343:584.279 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26343:584.720 Data: 00 00 00 00 00 00 00 00 00 00 00 00 9F 01 00 00 ... +T3F74 26343:584.740 - 0.483ms returns 20 (0x14) +T3F74 26343:584.757 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26343:584.774 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26343:585.219 Data: 1F 03 00 00 +T3F74 26343:585.239 - 0.488ms returns 4 (0x4) +T3F74 26343:585.256 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26343:585.272 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26343:585.732 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26343:585.755 - 0.507ms returns 12 (0xC) +T3F74 26343:585.776 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26343:585.795 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26343:586.229 Data: 00 00 00 00 +T3F74 26343:586.253 - 0.491ms returns 4 (0x4) +T3F74 26343:586.285 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26343:586.304 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26343:586.728 Data: 00 00 00 00 +T3F74 26343:586.752 - 0.474ms returns 4 (0x4) +T3F74 26343:586.773 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26343:586.792 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26343:587.223 Data: 00 00 00 00 +T3F74 26343:587.243 - 0.476ms returns 4 (0x4) +T062C 26343:599.106 JLINK_IsHalted() +T062C 26343:600.236 - 1.148ms returns FALSE +T062C 26343:700.483 JLINK_HasError() +T062C 26343:700.563 JLINK_IsHalted() +T062C 26343:701.805 - 1.283ms returns FALSE +T062C 26343:802.465 JLINK_HasError() +T062C 26343:802.513 JLINK_IsHalted() +T062C 26343:803.610 - 1.108ms returns FALSE +T062C 26343:904.356 JLINK_HasError() +T062C 26343:904.443 JLINK_IsHalted() +T062C 26343:905.647 - 1.223ms returns FALSE +T062C 26344:006.709 JLINK_HasError() +T062C 26344:006.795 JLINK_IsHalted() +T062C 26344:007.995 - 1.230ms returns FALSE +T062C 26344:108.129 JLINK_HasError() +T062C 26344:108.175 JLINK_HasError() +T062C 26344:108.194 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26344:108.225 Data: 8D 12 74 01 +T062C 26344:108.248 Debug reg: DWT_CYCCNT +T062C 26344:108.270 - 0.083ms returns 1 (0x1) +T3F74 26344:114.815 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26344:114.864 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26344:116.065 Data: 00 00 80 00 +T3F74 26344:116.145 - 1.354ms returns 4 (0x4) +T3F74 26344:116.201 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26344:116.224 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26344:117.376 Data: 00 00 F0 01 +T3F74 26344:117.455 - 1.279ms returns 4 (0x4) +T3F74 26344:120.488 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26344:120.515 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26344:121.702 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26344:121.730 - 1.249ms returns 16 (0x10) +T3F74 26344:121.751 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26344:121.770 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26344:122.147 Data: 1F 00 00 00 +T3F74 26344:122.168 - 0.423ms returns 4 (0x4) +T3F74 26344:122.185 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26344:122.202 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26344:122.670 Data: 00 00 00 00 00 00 00 00 00 00 00 00 4B 00 00 00 ... +T3F74 26344:122.705 - 0.528ms returns 20 (0x14) +T3F74 26344:122.731 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26344:122.754 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26344:123.173 Data: 1F 03 00 00 +T3F74 26344:123.203 - 0.479ms returns 4 (0x4) +T3F74 26344:123.225 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26344:123.246 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26344:123.795 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26344:123.819 - 0.601ms returns 12 (0xC) +T3F74 26344:123.839 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26344:123.859 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26344:124.278 Data: 00 00 00 00 +T3F74 26344:124.302 - 0.470ms returns 4 (0x4) +T3F74 26344:124.322 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26344:124.341 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26344:124.779 Data: 00 00 00 00 +T3F74 26344:124.806 - 0.491ms returns 4 (0x4) +T3F74 26344:124.826 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26344:124.845 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26344:125.278 Data: 00 00 00 00 +T3F74 26344:125.301 - 0.483ms returns 4 (0x4) +T062C 26344:146.259 JLINK_IsHalted() +T062C 26344:147.293 - 1.059ms returns FALSE +T062C 26344:248.470 JLINK_HasError() +T062C 26344:248.553 JLINK_IsHalted() +T062C 26344:249.726 - 1.214ms returns FALSE +T062C 26344:350.481 JLINK_HasError() +T062C 26344:350.524 JLINK_IsHalted() +T062C 26344:351.649 - 1.142ms returns FALSE +T062C 26344:452.464 JLINK_HasError() +T062C 26344:452.496 JLINK_IsHalted() +T062C 26344:453.614 - 1.142ms returns FALSE +T062C 26344:553.895 JLINK_HasError() +T062C 26344:553.982 JLINK_IsHalted() +T062C 26344:555.223 - 1.259ms returns FALSE +T062C 26344:655.919 JLINK_HasError() +T062C 26344:655.960 JLINK_HasError() +T062C 26344:655.976 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26344:656.006 Data: 8D 12 74 01 +T062C 26344:656.026 Debug reg: DWT_CYCCNT +T062C 26344:656.045 - 0.075ms returns 1 (0x1) +T3F74 26344:658.271 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26344:658.305 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26344:659.485 Data: 00 00 80 00 +T3F74 26344:659.565 - 1.322ms returns 4 (0x4) +T3F74 26344:659.626 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26344:659.706 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26344:660.791 Data: 00 00 F0 01 +T3F74 26344:660.869 - 1.262ms returns 4 (0x4) +T3F74 26344:664.406 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26344:664.433 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26344:665.596 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26344:665.623 - 1.225ms returns 16 (0x10) +T3F74 26344:665.649 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26344:665.670 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26344:666.087 Data: 1E 00 00 00 +T3F74 26344:666.111 - 0.470ms returns 4 (0x4) +T3F74 26344:666.131 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26344:666.150 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26344:666.705 Data: 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 ... +T3F74 26344:666.725 - 0.600ms returns 20 (0x14) +T3F74 26344:666.742 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26344:666.759 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26344:667.204 Data: 1F 03 00 00 +T3F74 26344:667.224 - 0.488ms returns 4 (0x4) +T3F74 26344:667.242 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26344:667.258 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26344:667.705 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26344:667.725 - 0.490ms returns 12 (0xC) +T3F74 26344:667.742 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26344:667.758 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26344:668.205 Data: 00 00 00 00 +T3F74 26344:668.225 - 0.489ms returns 4 (0x4) +T3F74 26344:668.242 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26344:668.258 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26344:668.705 Data: 00 00 00 00 +T3F74 26344:668.725 - 0.489ms returns 4 (0x4) +T3F74 26344:668.742 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26344:668.758 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26344:669.203 Data: 00 00 00 00 +T3F74 26344:669.223 - 0.488ms returns 4 (0x4) +T062C 26344:688.022 JLINK_IsHalted() +T062C 26344:689.120 - 1.116ms returns FALSE +T062C 26344:789.856 JLINK_HasError() +T062C 26344:789.895 JLINK_IsHalted() +T062C 26344:790.967 - 1.097ms returns FALSE +T062C 26344:891.336 JLINK_HasError() +T062C 26344:891.419 JLINK_IsHalted() +T062C 26344:892.477 - 1.076ms returns FALSE +T062C 26344:993.452 JLINK_HasError() +T062C 26344:993.525 JLINK_IsHalted() +T062C 26344:994.794 - 1.318ms returns FALSE +T062C 26345:095.620 JLINK_HasError() +T062C 26345:095.694 JLINK_IsHalted() +T062C 26345:096.807 - 1.131ms returns FALSE +T062C 26345:196.925 JLINK_HasError() +T062C 26345:196.963 JLINK_HasError() +T062C 26345:196.979 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26345:197.005 Data: 8D 12 74 01 +T062C 26345:197.025 Debug reg: DWT_CYCCNT +T062C 26345:197.044 - 0.072ms returns 1 (0x1) +T3F74 26345:199.540 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26345:199.573 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26345:200.790 Data: 00 00 80 00 +T3F74 26345:200.870 - 1.356ms returns 4 (0x4) +T3F74 26345:200.927 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26345:200.950 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26345:202.148 Data: 00 00 F0 01 +T3F74 26345:202.181 - 1.262ms returns 4 (0x4) +T3F74 26345:205.496 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26345:205.540 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26345:206.856 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26345:206.885 - 1.395ms returns 16 (0x10) +T3F74 26345:206.905 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26345:206.924 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26345:207.379 Data: 1E 00 00 00 +T3F74 26345:207.399 - 0.501ms returns 4 (0x4) +T3F74 26345:207.417 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26345:207.433 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26345:207.879 Data: 00 00 00 00 00 00 00 00 00 00 00 00 9D 01 00 00 ... +T3F74 26345:207.899 - 0.489ms returns 20 (0x14) +T3F74 26345:207.917 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26345:207.933 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26345:208.383 Data: 1F 03 00 00 +T3F74 26345:208.403 - 0.493ms returns 4 (0x4) +T3F74 26345:208.434 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26345:208.451 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26345:208.883 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26345:208.906 - 0.479ms returns 12 (0xC) +T3F74 26345:208.929 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26345:208.948 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26345:209.394 Data: 00 00 00 00 +T3F74 26345:209.418 - 0.496ms returns 4 (0x4) +T3F74 26345:209.448 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26345:209.467 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26345:209.883 Data: 00 00 00 00 +T3F74 26345:209.906 - 0.466ms returns 4 (0x4) +T3F74 26345:209.930 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26345:209.949 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26345:210.501 Data: 00 00 00 00 +T3F74 26345:210.545 - 0.626ms returns 4 (0x4) +T062C 26345:224.577 JLINK_IsHalted() +T062C 26345:225.731 - 1.181ms returns FALSE +T062C 26345:326.380 JLINK_HasError() +T062C 26345:326.420 JLINK_IsHalted() +T062C 26345:327.543 - 1.147ms returns FALSE +T062C 26345:428.178 JLINK_HasError() +T062C 26345:428.222 JLINK_IsHalted() +T062C 26345:429.262 - 1.051ms returns FALSE +T062C 26345:529.527 JLINK_HasError() +T062C 26345:529.576 JLINK_IsHalted() +T062C 26345:530.611 - 1.068ms returns FALSE +T062C 26345:631.353 JLINK_HasError() +T062C 26345:631.399 JLINK_IsHalted() +T062C 26345:632.486 - 1.106ms returns FALSE +T062C 26345:733.247 JLINK_HasError() +T062C 26345:733.333 JLINK_HasError() +T062C 26345:733.377 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26345:733.439 Data: 8D 12 74 01 +T062C 26345:733.505 Debug reg: DWT_CYCCNT +T062C 26345:733.524 - 0.153ms returns 1 (0x1) +T3F74 26345:735.660 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26345:735.696 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26345:736.941 Data: 00 00 80 00 +T3F74 26345:736.975 - 1.324ms returns 4 (0x4) +T3F74 26345:737.015 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26345:737.038 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26345:737.445 Data: 00 00 F0 01 +T3F74 26345:737.469 - 0.462ms returns 4 (0x4) +T3F74 26345:740.465 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26345:740.491 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26345:741.702 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26345:741.727 - 1.270ms returns 16 (0x10) +T3F74 26345:741.748 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26345:741.768 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26345:742.196 Data: 1E 00 00 00 +T3F74 26345:742.216 - 0.474ms returns 4 (0x4) +T3F74 26345:742.233 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26345:742.249 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26345:742.687 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1D 00 00 00 ... +T3F74 26345:742.707 - 0.481ms returns 20 (0x14) +T3F74 26345:742.739 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26345:742.755 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26345:743.191 Data: 1F 03 00 00 +T3F74 26345:743.215 - 0.484ms returns 4 (0x4) +T3F74 26345:743.238 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26345:743.257 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26345:743.698 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26345:743.722 - 0.491ms returns 12 (0xC) +T3F74 26345:743.752 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26345:743.771 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26345:744.193 Data: 00 00 00 00 +T3F74 26345:744.216 - 0.471ms returns 4 (0x4) +T3F74 26345:744.239 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26345:744.258 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26345:744.693 Data: 00 00 00 00 +T3F74 26345:744.717 - 0.486ms returns 4 (0x4) +T3F74 26345:744.740 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26345:744.759 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26345:745.195 Data: 00 00 00 00 +T3F74 26345:745.220 - 0.488ms returns 4 (0x4) +T062C 26345:756.808 JLINK_IsHalted() +T062C 26345:757.972 - 1.183ms returns FALSE +T062C 26345:858.177 JLINK_HasError() +T062C 26345:858.264 JLINK_IsHalted() +T062C 26345:859.553 - 1.336ms returns FALSE +T062C 26345:960.502 JLINK_HasError() +T062C 26345:960.549 JLINK_IsHalted() +T062C 26345:961.685 - 1.168ms returns FALSE +T062C 26346:061.887 JLINK_HasError() +T062C 26346:061.969 JLINK_IsHalted() +T062C 26346:063.308 - 1.381ms returns FALSE +T062C 26346:163.978 JLINK_HasError() +T062C 26346:164.051 JLINK_IsHalted() +T062C 26346:165.250 - 1.222ms returns FALSE +T062C 26346:265.412 JLINK_HasError() +T062C 26346:265.490 JLINK_HasError() +T062C 26346:265.535 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26346:265.596 Data: 8D 12 74 01 +T062C 26346:265.640 Debug reg: DWT_CYCCNT +T062C 26346:265.658 - 0.130ms returns 1 (0x1) +T3F74 26346:268.270 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26346:268.308 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26346:269.540 Data: 00 00 80 00 +T3F74 26346:269.620 - 1.374ms returns 4 (0x4) +T3F74 26346:269.675 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26346:269.698 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26346:270.831 Data: 00 00 F0 01 +T3F74 26346:270.909 - 1.254ms returns 4 (0x4) +T3F74 26346:274.084 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26346:274.117 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26346:275.344 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26346:275.399 - 1.322ms returns 16 (0x10) +T3F74 26346:275.423 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26346:275.446 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26346:275.893 Data: 1F 00 00 00 +T3F74 26346:275.917 - 0.502ms returns 4 (0x4) +T3F74 26346:275.937 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26346:275.957 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26346:276.497 Data: 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 ... +T3F74 26346:276.521 - 0.593ms returns 20 (0x14) +T3F74 26346:276.543 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26346:276.562 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26346:276.986 Data: 1F 03 00 00 +T3F74 26346:277.006 - 0.469ms returns 4 (0x4) +T3F74 26346:277.023 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26346:277.039 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26346:277.491 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26346:277.514 - 0.499ms returns 12 (0xC) +T3F74 26346:277.534 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26346:277.553 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26346:277.992 Data: 00 00 00 00 +T3F74 26346:278.015 - 0.489ms returns 4 (0x4) +T3F74 26346:278.036 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26346:278.054 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26346:278.499 Data: 00 00 00 00 +T3F74 26346:278.523 - 0.495ms returns 4 (0x4) +T3F74 26346:278.543 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26346:278.562 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26346:278.986 Data: 00 00 00 00 +T3F74 26346:279.007 - 0.470ms returns 4 (0x4) +T062C 26346:298.517 JLINK_IsHalted() +T062C 26346:299.676 - 1.178ms returns FALSE +T062C 26346:400.678 JLINK_HasError() +T062C 26346:400.718 JLINK_IsHalted() +T062C 26346:401.768 - 1.072ms returns FALSE +T062C 26346:501.978 JLINK_HasError() +T062C 26346:502.058 JLINK_IsHalted() +T062C 26346:503.357 - 1.342ms returns FALSE +T062C 26346:603.576 JLINK_HasError() +T062C 26346:603.615 JLINK_IsHalted() +T062C 26346:604.845 - 1.274ms returns FALSE +T062C 26346:705.100 JLINK_HasError() +T062C 26346:705.179 JLINK_IsHalted() +T062C 26346:706.438 - 1.301ms returns FALSE +T062C 26346:806.680 JLINK_HasError() +T062C 26346:806.762 JLINK_HasError() +T062C 26346:806.807 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26346:806.868 Data: 8D 12 74 01 +T062C 26346:806.889 Debug reg: DWT_CYCCNT +T062C 26346:806.907 - 0.107ms returns 1 (0x1) +T3F74 26346:809.081 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26346:809.115 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26346:810.266 Data: 00 00 80 00 +T3F74 26346:810.332 - 1.257ms returns 4 (0x4) +T3F74 26346:810.366 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26346:810.386 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26346:810.791 Data: 00 00 F0 01 +T3F74 26346:810.811 - 0.451ms returns 4 (0x4) +T3F74 26346:814.004 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26346:814.031 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26346:815.182 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26346:815.214 - 1.218ms returns 16 (0x10) +T3F74 26346:815.242 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26346:815.265 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26346:815.672 Data: 1E 00 00 00 +T3F74 26346:815.696 - 0.461ms returns 4 (0x4) +T3F74 26346:815.719 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26346:815.738 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26346:816.298 Data: 00 00 00 00 00 00 00 00 00 00 00 00 07 03 00 00 ... +T3F74 26346:816.324 - 0.613ms returns 20 (0x14) +T3F74 26346:816.348 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26346:816.369 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26346:816.800 Data: 1F 03 00 00 +T3F74 26346:816.824 - 0.483ms returns 4 (0x4) +T3F74 26346:816.847 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26346:816.866 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26346:817.295 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26346:817.318 - 0.479ms returns 12 (0xC) +T3F74 26346:817.341 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26346:817.360 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26346:817.795 Data: 00 00 00 00 +T3F74 26346:817.818 - 0.485ms returns 4 (0x4) +T3F74 26346:817.841 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26346:817.860 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26346:818.304 Data: 00 00 00 00 +T3F74 26346:818.327 - 0.494ms returns 4 (0x4) +T3F74 26346:818.350 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26346:818.369 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26346:818.804 Data: 00 00 00 00 +T3F74 26346:818.827 - 0.485ms returns 4 (0x4) +T062C 26346:837.386 JLINK_IsHalted() +T062C 26346:838.429 - 1.069ms returns FALSE +T062C 26346:939.182 JLINK_HasError() +T062C 26346:939.246 JLINK_IsHalted() +T062C 26346:940.398 - 1.171ms returns FALSE +T062C 26347:040.573 JLINK_HasError() +T062C 26347:040.636 JLINK_IsHalted() +T062C 26347:041.693 - 1.073ms returns FALSE +T062C 26347:142.396 JLINK_HasError() +T062C 26347:142.448 JLINK_IsHalted() +T062C 26347:143.619 - 1.188ms returns FALSE +T062C 26347:243.816 JLINK_HasError() +T062C 26347:243.889 JLINK_IsHalted() +T062C 26347:245.070 - 1.199ms returns FALSE +T062C 26347:346.189 JLINK_HasError() +T062C 26347:346.275 JLINK_HasError() +T062C 26347:346.310 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26347:346.341 Data: 8D 12 74 01 +T062C 26347:346.366 Debug reg: DWT_CYCCNT +T062C 26347:346.398 - 0.096ms returns 1 (0x1) +T3F74 26347:348.937 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26347:348.974 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26347:350.002 Data: 00 00 80 00 +T3F74 26347:350.040 - 1.111ms returns 4 (0x4) +T3F74 26347:350.083 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26347:350.106 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26347:350.600 Data: 00 00 F0 01 +T3F74 26347:350.624 - 0.549ms returns 4 (0x4) +T3F74 26347:354.040 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26347:354.068 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26347:355.293 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26347:355.340 - 1.307ms returns 16 (0x10) +T3F74 26347:355.363 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26347:355.392 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26347:355.876 Data: 1E 00 00 00 +T3F74 26347:355.900 - 0.545ms returns 4 (0x4) +T3F74 26347:355.921 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26347:355.940 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26347:356.483 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D5 01 00 00 ... +T3F74 26347:356.507 - 0.594ms returns 20 (0x14) +T3F74 26347:356.527 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26347:356.546 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26347:356.990 Data: 1F 03 00 00 +T3F74 26347:357.010 - 0.489ms returns 4 (0x4) +T3F74 26347:357.027 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26347:357.043 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26347:357.475 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26347:357.495 - 0.474ms returns 12 (0xC) +T3F74 26347:357.512 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26347:357.528 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26347:357.973 Data: 00 00 00 00 +T3F74 26347:357.993 - 0.488ms returns 4 (0x4) +T3F74 26347:358.010 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26347:358.026 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26347:358.474 Data: 00 00 00 00 +T3F74 26347:358.495 - 0.490ms returns 4 (0x4) +T3F74 26347:358.512 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26347:358.528 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26347:358.973 Data: 00 00 00 00 +T3F74 26347:358.993 - 0.488ms returns 4 (0x4) +T062C 26347:370.804 JLINK_IsHalted() +T062C 26347:371.887 - 1.102ms returns FALSE +T062C 26347:472.077 JLINK_HasError() +T062C 26347:472.157 JLINK_IsHalted() +T062C 26347:473.367 - 1.228ms returns FALSE +T062C 26347:573.558 JLINK_HasError() +T062C 26347:573.600 JLINK_IsHalted() +T062C 26347:574.742 - 1.160ms returns FALSE +T062C 26347:674.930 JLINK_HasError() +T062C 26347:675.011 JLINK_IsHalted() +T062C 26347:676.250 - 1.258ms returns FALSE +T062C 26347:776.399 JLINK_HasError() +T062C 26347:776.484 JLINK_IsHalted() +T062C 26347:777.670 - 1.234ms returns FALSE +T062C 26347:878.233 JLINK_HasError() +T062C 26347:878.338 JLINK_HasError() +T062C 26347:878.360 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26347:878.396 Data: 8D 12 74 01 +T062C 26347:878.421 Debug reg: DWT_CYCCNT +T062C 26347:878.443 - 0.091ms returns 1 (0x1) +T3F74 26347:881.391 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26347:881.427 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26347:882.603 Data: 00 00 80 00 +T3F74 26347:882.636 - 1.253ms returns 4 (0x4) +T3F74 26347:882.676 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26347:882.699 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26347:883.195 Data: 00 00 F0 01 +T3F74 26347:883.219 - 0.550ms returns 4 (0x4) +T3F74 26347:886.322 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26347:886.355 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26347:887.629 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26347:887.657 - 1.341ms returns 16 (0x10) +T3F74 26347:887.678 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26347:887.697 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26347:888.151 Data: 1E 00 00 00 +T3F74 26347:888.172 - 0.500ms returns 4 (0x4) +T3F74 26347:888.189 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26347:888.206 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26347:888.648 Data: 00 00 00 00 00 00 00 00 00 00 00 00 3F 02 00 00 ... +T3F74 26347:888.668 - 0.485ms returns 20 (0x14) +T3F74 26347:888.685 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26347:888.701 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26347:889.192 Data: 1F 03 00 00 +T3F74 26347:889.212 - 0.533ms returns 4 (0x4) +T3F74 26347:889.229 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26347:889.245 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26347:889.682 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26347:889.705 - 0.484ms returns 12 (0xC) +T3F74 26347:889.725 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26347:889.744 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26347:890.183 Data: 00 00 00 00 +T3F74 26347:890.206 - 0.489ms returns 4 (0x4) +T3F74 26347:890.227 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26347:890.245 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26347:890.658 Data: 00 00 00 00 +T3F74 26347:890.681 - 0.462ms returns 4 (0x4) +T3F74 26347:890.701 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26347:890.720 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26347:891.154 Data: 00 00 00 00 +T3F74 26347:891.174 - 0.479ms returns 4 (0x4) +T062C 26347:902.845 JLINK_IsHalted() +T062C 26347:903.912 - 1.086ms returns FALSE +T062C 26348:004.269 JLINK_HasError() +T062C 26348:004.355 JLINK_IsHalted() +T062C 26348:005.369 - 1.034ms returns FALSE +T062C 26348:105.506 JLINK_HasError() +T062C 26348:105.556 JLINK_IsHalted() +T062C 26348:106.729 - 1.191ms returns FALSE +T062C 26348:206.916 JLINK_HasError() +T062C 26348:207.204 JLINK_IsHalted() +T062C 26348:208.435 - 1.250ms returns FALSE +T062C 26348:309.652 JLINK_HasError() +T062C 26348:309.725 JLINK_IsHalted() +T062C 26348:310.916 - 1.219ms returns FALSE +T062C 26348:411.067 JLINK_HasError() +T062C 26348:411.144 JLINK_HasError() +T062C 26348:411.189 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26348:411.251 Data: 8D 12 74 01 +T062C 26348:411.293 Debug reg: DWT_CYCCNT +T062C 26348:411.311 - 0.129ms returns 1 (0x1) +T3F74 26348:414.005 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26348:414.050 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26348:415.238 Data: 00 00 80 00 +T3F74 26348:415.319 - 1.340ms returns 4 (0x4) +T3F74 26348:415.380 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26348:415.403 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26348:416.477 Data: 00 00 F0 01 +T3F74 26348:416.510 - 1.139ms returns 4 (0x4) +T3F74 26348:419.930 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26348:419.962 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26348:421.289 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26348:421.350 - 1.440ms returns 16 (0x10) +T3F74 26348:421.404 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26348:421.453 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26348:421.831 Data: 1E 00 00 00 +T3F74 26348:421.851 - 0.454ms returns 4 (0x4) +T3F74 26348:421.868 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26348:421.884 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26348:422.327 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1B 00 00 00 ... +T3F74 26348:422.347 - 0.485ms returns 20 (0x14) +T3F74 26348:422.364 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26348:422.380 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26348:422.832 Data: 1F 03 00 00 +T3F74 26348:422.852 - 0.494ms returns 4 (0x4) +T3F74 26348:422.869 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26348:422.885 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26348:423.326 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26348:423.345 - 0.482ms returns 12 (0xC) +T3F74 26348:423.368 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26348:423.388 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26348:424.102 Data: 00 00 00 00 +T3F74 26348:424.137 - 0.777ms returns 4 (0x4) +T3F74 26348:424.163 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26348:424.186 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26348:425.274 Data: 00 00 00 00 +T3F74 26348:425.304 - 1.147ms returns 4 (0x4) +T3F74 26348:425.324 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26348:425.343 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26348:425.842 Data: 00 00 00 00 +T3F74 26348:425.866 - 0.550ms returns 4 (0x4) +T062C 26348:437.756 JLINK_IsHalted() +T062C 26348:438.877 - 1.140ms returns FALSE +T062C 26348:539.079 JLINK_HasError() +T062C 26348:539.164 JLINK_IsHalted() +T062C 26348:540.422 - 1.276ms returns FALSE +T062C 26348:641.185 JLINK_HasError() +T062C 26348:641.227 JLINK_IsHalted() +T062C 26348:642.340 - 1.152ms returns FALSE +T062C 26348:742.510 JLINK_HasError() +T062C 26348:742.583 JLINK_IsHalted() +T062C 26348:743.756 - 1.221ms returns FALSE +T062C 26348:844.021 JLINK_HasError() +T062C 26348:844.102 JLINK_IsHalted() +T062C 26348:845.168 - 1.075ms returns FALSE +T062C 26348:945.306 JLINK_HasError() +T062C 26348:945.382 JLINK_HasError() +T062C 26348:945.401 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26348:945.429 Data: 8D 12 74 01 +T062C 26348:945.453 Debug reg: DWT_CYCCNT +T062C 26348:945.474 - 0.081ms returns 1 (0x1) +T3F74 26348:947.795 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26348:947.829 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26348:948.980 Data: 00 00 80 00 +T3F74 26348:949.060 - 1.285ms returns 4 (0x4) +T3F74 26348:949.147 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26348:949.171 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26348:950.270 Data: 00 00 F0 01 +T3F74 26348:950.297 - 1.157ms returns 4 (0x4) +T3F74 26348:953.459 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26348:953.490 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26348:954.698 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26348:954.731 - 1.284ms returns 16 (0x10) +T3F74 26348:954.843 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26348:954.870 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26348:955.266 Data: 1E 00 00 00 +T3F74 26348:955.290 - 0.454ms returns 4 (0x4) +T3F74 26348:955.310 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26348:955.330 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26348:955.891 Data: 00 00 00 00 00 00 00 00 00 00 00 00 43 02 00 00 ... +T3F74 26348:955.915 - 0.612ms returns 20 (0x14) +T3F74 26348:955.935 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26348:955.954 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26348:956.385 Data: 1F 03 00 00 +T3F74 26348:956.405 - 0.477ms returns 4 (0x4) +T3F74 26348:956.422 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26348:956.438 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26348:956.884 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26348:956.904 - 0.488ms returns 12 (0xC) +T3F74 26348:956.921 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26348:956.937 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26348:957.384 Data: 00 00 00 00 +T3F74 26348:957.404 - 0.489ms returns 4 (0x4) +T3F74 26348:957.421 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26348:957.437 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26348:957.884 Data: 00 00 00 00 +T3F74 26348:957.904 - 0.490ms returns 4 (0x4) +T3F74 26348:957.922 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26348:957.937 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26348:958.384 Data: 00 00 00 00 +T3F74 26348:958.404 - 0.489ms returns 4 (0x4) +T062C 26348:969.888 JLINK_IsHalted() +T062C 26348:971.021 - 1.152ms returns FALSE +T062C 26349:071.252 JLINK_HasError() +T062C 26349:071.334 JLINK_IsHalted() +T062C 26349:072.517 - 1.225ms returns FALSE +T062C 26349:172.863 JLINK_HasError() +T062C 26349:172.958 JLINK_IsHalted() +T062C 26349:174.003 - 1.064ms returns FALSE +T062C 26349:274.272 JLINK_HasError() +T062C 26349:274.359 JLINK_IsHalted() +T062C 26349:275.529 - 1.188ms returns FALSE +T062C 26349:375.703 JLINK_HasError() +T062C 26349:375.786 JLINK_IsHalted() +T062C 26349:377.087 - 1.350ms returns FALSE +T062C 26349:478.192 JLINK_HasError() +T062C 26349:478.270 JLINK_HasError() +T062C 26349:478.315 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26349:478.376 Data: 8D 12 74 01 +T062C 26349:478.433 Debug reg: DWT_CYCCNT +T062C 26349:478.487 - 0.191ms returns 1 (0x1) +T3F74 26349:481.432 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26349:481.464 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26349:482.716 Data: 00 00 80 00 +T3F74 26349:482.794 - 1.382ms returns 4 (0x4) +T3F74 26349:482.857 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26349:482.880 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26349:484.058 Data: 00 00 F0 01 +T3F74 26349:484.133 - 1.284ms returns 4 (0x4) +T3F74 26349:487.401 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26349:487.432 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26349:488.566 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26349:488.587 - 1.192ms returns 16 (0x10) +T3F74 26349:488.629 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26349:488.646 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26349:489.076 Data: 1E 00 00 00 +T3F74 26349:489.099 - 0.478ms returns 4 (0x4) +T3F74 26349:489.123 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26349:489.142 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26349:489.696 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E3 02 00 00 ... +T3F74 26349:489.719 - 0.603ms returns 20 (0x14) +T3F74 26349:489.751 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26349:489.770 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26349:490.194 Data: 1F 03 00 00 +T3F74 26349:490.218 - 0.476ms returns 4 (0x4) +T3F74 26349:490.243 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26349:490.264 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26349:490.819 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26349:490.846 - 0.610ms returns 12 (0xC) +T3F74 26349:490.875 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26349:490.892 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26349:491.319 Data: 00 00 00 00 +T3F74 26349:491.343 - 0.475ms returns 4 (0x4) +T3F74 26349:491.366 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26349:491.385 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26349:491.822 Data: 00 00 00 00 +T3F74 26349:491.846 - 0.487ms returns 4 (0x4) +T3F74 26349:491.868 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26349:491.887 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26349:492.319 Data: 00 00 00 00 +T3F74 26349:492.343 - 0.484ms returns 4 (0x4) +T062C 26349:504.946 JLINK_IsHalted() +T062C 26349:506.082 - 1.154ms returns FALSE +T062C 26349:606.864 JLINK_HasError() +T062C 26349:606.905 JLINK_IsHalted() +T062C 26349:607.996 - 1.110ms returns FALSE +T062C 26349:708.205 JLINK_HasError() +T062C 26349:708.291 JLINK_IsHalted() +T062C 26349:709.536 - 1.263ms returns FALSE +T062C 26349:809.775 JLINK_HasError() +T062C 26349:809.857 JLINK_IsHalted() +T062C 26349:810.989 - 1.173ms returns FALSE +T062C 26349:911.214 JLINK_HasError() +T062C 26349:911.293 JLINK_IsHalted() +T062C 26349:912.511 - 1.236ms returns FALSE +T062C 26350:012.649 JLINK_HasError() +T062C 26350:012.726 JLINK_HasError() +T062C 26350:012.771 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26350:012.830 Data: 8D 12 74 01 +T062C 26350:012.878 Debug reg: DWT_CYCCNT +T062C 26350:012.896 - 0.132ms returns 1 (0x1) +T3F74 26350:015.292 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26350:015.325 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26350:016.428 Data: 00 00 80 00 +T3F74 26350:016.464 - 1.179ms returns 4 (0x4) +T3F74 26350:016.508 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26350:016.674 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26350:017.889 Data: 00 00 F0 01 +T3F74 26350:017.968 - 1.485ms returns 4 (0x4) +T3F74 26350:021.181 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26350:021.209 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26350:022.396 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26350:022.430 - 1.257ms returns 16 (0x10) +T3F74 26350:022.456 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26350:022.479 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26350:022.998 Data: 1F 00 00 00 +T3F74 26350:023.022 - 0.574ms returns 4 (0x4) +T3F74 26350:023.043 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26350:023.123 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26350:023.617 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E7 02 00 00 ... +T3F74 26350:023.637 - 0.601ms returns 20 (0x14) +T3F74 26350:023.655 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26350:023.671 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26350:024.118 Data: 1F 03 00 00 +T3F74 26350:024.138 - 0.490ms returns 4 (0x4) +T3F74 26350:024.156 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26350:024.172 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26350:024.617 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26350:024.637 - 0.488ms returns 12 (0xC) +T3F74 26350:024.654 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26350:024.671 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26350:025.118 Data: 00 00 00 00 +T3F74 26350:025.138 - 0.490ms returns 4 (0x4) +T3F74 26350:025.155 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26350:025.171 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26350:025.613 Data: 00 00 00 00 +T3F74 26350:025.633 - 0.484ms returns 4 (0x4) +T3F74 26350:025.650 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26350:025.666 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26350:026.146 Data: 00 00 00 00 +T3F74 26350:026.166 - 0.522ms returns 4 (0x4) +T062C 26350:044.892 JLINK_IsHalted() +T062C 26350:046.031 - 1.157ms returns FALSE +T062C 26350:146.743 JLINK_HasError() +T062C 26350:146.796 JLINK_IsHalted() +T062C 26350:147.947 - 1.187ms returns FALSE +T062C 26350:248.774 JLINK_HasError() +T062C 26350:248.860 JLINK_IsHalted() +T062C 26350:249.992 - 1.153ms returns FALSE +T062C 26350:350.923 JLINK_HasError() +T062C 26350:351.001 JLINK_IsHalted() +T062C 26350:352.163 - 1.207ms returns FALSE +T062C 26350:453.407 JLINK_HasError() +T062C 26350:453.483 JLINK_IsHalted() +T062C 26350:454.655 - 1.213ms returns FALSE +T062C 26350:554.895 JLINK_HasError() +T062C 26350:554.975 JLINK_HasError() +T062C 26350:555.019 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26350:555.074 Data: 8D 12 74 01 +T062C 26350:555.094 Debug reg: DWT_CYCCNT +T062C 26350:555.113 - 0.100ms returns 1 (0x1) +T3F74 26350:557.640 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26350:557.674 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26350:558.840 Data: 00 00 80 00 +T3F74 26350:558.877 - 1.244ms returns 4 (0x4) +T3F74 26350:558.919 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26350:558.942 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26350:559.449 Data: 00 00 F0 01 +T3F74 26350:559.473 - 0.562ms returns 4 (0x4) +T3F74 26350:562.793 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26350:562.820 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26350:564.077 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26350:564.109 - 1.324ms returns 16 (0x10) +T3F74 26350:564.146 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26350:564.169 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26350:564.683 Data: 1E 00 00 00 +T3F74 26350:564.707 - 0.568ms returns 4 (0x4) +T3F74 26350:564.739 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26350:564.758 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26350:565.304 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D3 01 00 00 ... +T3F74 26350:565.335 - 0.604ms returns 20 (0x14) +T3F74 26350:565.357 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26350:565.379 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26350:565.800 Data: 1F 03 00 00 +T3F74 26350:565.824 - 0.474ms returns 4 (0x4) +T3F74 26350:565.846 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26350:565.865 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26350:566.307 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26350:566.331 - 0.493ms returns 12 (0xC) +T3F74 26350:566.353 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26350:566.373 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26350:566.800 Data: 00 00 00 00 +T3F74 26350:566.825 - 0.480ms returns 4 (0x4) +T3F74 26350:566.856 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26350:566.875 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26350:567.297 Data: 00 00 00 00 +T3F74 26350:567.320 - 0.471ms returns 4 (0x4) +T3F74 26350:567.342 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26350:567.361 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26350:567.809 Data: 00 00 00 00 +T3F74 26350:567.844 - 0.510ms returns 4 (0x4) +T062C 26350:587.637 JLINK_IsHalted() +T062C 26350:588.693 - 1.074ms returns FALSE +T062C 26350:689.835 JLINK_HasError() +T062C 26350:689.884 JLINK_IsHalted() +T062C 26350:691.025 - 1.159ms returns FALSE +T062C 26350:791.138 JLINK_HasError() +T062C 26350:791.178 JLINK_IsHalted() +T062C 26350:792.285 - 1.120ms returns FALSE +T062C 26350:892.960 JLINK_HasError() +T062C 26350:893.058 JLINK_IsHalted() +T062C 26350:894.217 - 1.219ms returns FALSE +T062C 26350:994.964 JLINK_HasError() +T062C 26350:994.996 JLINK_IsHalted() +T062C 26350:996.114 - 1.166ms returns FALSE +T062C 26351:096.817 JLINK_HasError() +T062C 26351:096.847 JLINK_HasError() +T062C 26351:096.862 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26351:096.889 Data: 8D 12 74 01 +T062C 26351:096.909 Debug reg: DWT_CYCCNT +T062C 26351:096.928 - 0.071ms returns 1 (0x1) +T3F74 26351:100.523 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26351:100.557 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26351:101.691 Data: 00 00 80 00 +T3F74 26351:101.762 - 1.246ms returns 4 (0x4) +T3F74 26351:101.817 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26351:101.843 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26351:103.043 Data: 00 00 F0 01 +T3F74 26351:103.072 - 1.263ms returns 4 (0x4) +T3F74 26351:106.199 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26351:106.226 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26351:107.390 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26351:107.422 - 1.232ms returns 16 (0x10) +T3F74 26351:107.446 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26351:107.469 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26351:107.851 Data: 1F 00 00 00 +T3F74 26351:107.872 - 0.432ms returns 4 (0x4) +T3F74 26351:107.889 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26351:107.905 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26351:108.345 Data: 00 00 00 00 00 00 00 00 00 00 00 00 0D 02 00 00 ... +T3F74 26351:108.365 - 0.482ms returns 20 (0x14) +T3F74 26351:108.382 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26351:108.398 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26351:108.852 Data: 1F 03 00 00 +T3F74 26351:108.873 - 0.497ms returns 4 (0x4) +T3F74 26351:108.890 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26351:108.906 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26351:109.366 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26351:109.390 - 0.507ms returns 12 (0xC) +T3F74 26351:109.409 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26351:109.428 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26351:109.849 Data: 00 00 00 00 +T3F74 26351:109.872 - 0.480ms returns 4 (0x4) +T3F74 26351:109.902 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26351:109.921 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26351:110.353 Data: 00 00 00 00 +T3F74 26351:110.377 - 0.482ms returns 4 (0x4) +T3F74 26351:110.397 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26351:110.415 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26351:111.014 Data: 00 00 00 00 +T3F74 26351:111.040 - 0.651ms returns 4 (0x4) +T062C 26351:130.305 JLINK_IsHalted() +T062C 26351:131.361 - 1.074ms returns FALSE +T062C 26351:232.097 JLINK_HasError() +T062C 26351:232.132 JLINK_IsHalted() +T062C 26351:233.395 - 1.282ms returns FALSE +T062C 26351:333.489 JLINK_HasError() +T062C 26351:333.534 JLINK_IsHalted() +T062C 26351:334.589 - 1.067ms returns FALSE +T062C 26351:434.833 JLINK_HasError() +T062C 26351:434.919 JLINK_IsHalted() +T062C 26351:435.940 - 1.028ms returns FALSE +T062C 26351:536.575 JLINK_HasError() +T062C 26351:536.659 JLINK_IsHalted() +T062C 26351:537.885 - 1.268ms returns FALSE +T062C 26351:638.627 JLINK_HasError() +T062C 26351:638.665 JLINK_HasError() +T062C 26351:638.681 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26351:638.706 Data: 8D 12 74 01 +T062C 26351:638.729 Debug reg: DWT_CYCCNT +T062C 26351:638.748 - 0.074ms returns 1 (0x1) +T3F74 26351:641.480 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26351:641.514 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26351:642.635 Data: 00 00 80 00 +T3F74 26351:642.694 - 1.220ms returns 4 (0x4) +T3F74 26351:642.728 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26351:642.749 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26351:643.153 Data: 00 00 F0 01 +T3F74 26351:643.173 - 0.452ms returns 4 (0x4) +T3F74 26351:646.426 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26351:646.456 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26351:647.740 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26351:647.769 - 1.349ms returns 16 (0x10) +T3F74 26351:647.789 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26351:647.809 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26351:648.277 Data: 1E 00 00 00 +T3F74 26351:648.298 - 0.515ms returns 4 (0x4) +T3F74 26351:648.315 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26351:648.332 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26351:648.778 Data: 00 00 00 00 00 00 00 00 00 00 00 00 0D 02 00 00 ... +T3F74 26351:648.798 - 0.489ms returns 20 (0x14) +T3F74 26351:648.815 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26351:648.831 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26351:649.277 Data: 1F 03 00 00 +T3F74 26351:649.297 - 0.489ms returns 4 (0x4) +T3F74 26351:649.314 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26351:649.330 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26351:649.776 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26351:649.796 - 0.488ms returns 12 (0xC) +T3F74 26351:649.813 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26351:649.829 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26351:650.277 Data: 00 00 00 00 +T3F74 26351:650.297 - 0.490ms returns 4 (0x4) +T3F74 26351:650.314 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26351:650.330 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26351:650.775 Data: 00 00 00 00 +T3F74 26351:650.795 - 0.488ms returns 4 (0x4) +T3F74 26351:650.812 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26351:650.828 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26351:651.276 Data: 00 00 00 00 +T3F74 26351:651.296 - 0.490ms returns 4 (0x4) +T062C 26351:664.091 JLINK_IsHalted() +T062C 26351:665.187 - 1.115ms returns FALSE +T062C 26351:765.780 JLINK_HasError() +T062C 26351:765.858 JLINK_IsHalted() +T062C 26351:767.137 - 1.315ms returns FALSE +T062C 26351:867.338 JLINK_HasError() +T062C 26351:867.419 JLINK_IsHalted() +T062C 26351:868.570 - 1.169ms returns FALSE +T062C 26351:968.774 JLINK_HasError() +T062C 26351:968.854 JLINK_IsHalted() +T062C 26351:970.073 - 1.260ms returns FALSE +T062C 26352:070.844 JLINK_HasError() +T062C 26352:070.922 JLINK_IsHalted() +T062C 26352:072.095 - 1.215ms returns FALSE +T062C 26352:172.845 JLINK_HasError() +T062C 26352:172.880 JLINK_HasError() +T062C 26352:172.896 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26352:172.922 Data: 8D 12 74 01 +T062C 26352:172.943 Debug reg: DWT_CYCCNT +T062C 26352:172.961 - 0.071ms returns 1 (0x1) +T3F74 26352:175.448 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26352:175.481 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26352:176.610 Data: 00 00 80 00 +T3F74 26352:176.645 - 1.205ms returns 4 (0x4) +T3F74 26352:176.684 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26352:176.707 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26352:177.215 Data: 00 00 F0 01 +T3F74 26352:177.245 - 0.567ms returns 4 (0x4) +T3F74 26352:180.256 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26352:180.284 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26352:181.484 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26352:181.568 - 1.320ms returns 16 (0x10) +T3F74 26352:181.593 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26352:181.616 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26352:182.089 Data: 1F 00 00 00 +T3F74 26352:182.116 - 0.531ms returns 4 (0x4) +T3F74 26352:182.137 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26352:182.156 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26352:182.707 Data: 00 00 00 00 00 00 00 00 00 00 00 00 C9 02 00 00 ... +T3F74 26352:182.727 - 0.597ms returns 20 (0x14) +T3F74 26352:182.745 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26352:182.761 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26352:183.200 Data: 1F 03 00 00 +T3F74 26352:183.220 - 0.482ms returns 4 (0x4) +T3F74 26352:183.237 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26352:183.253 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26352:183.720 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26352:183.740 - 0.509ms returns 12 (0xC) +T3F74 26352:183.757 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26352:183.773 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26352:184.211 Data: 00 00 00 00 +T3F74 26352:184.234 - 0.485ms returns 4 (0x4) +T3F74 26352:184.255 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26352:184.273 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26352:184.712 Data: 00 00 00 00 +T3F74 26352:184.735 - 0.488ms returns 4 (0x4) +T3F74 26352:184.755 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26352:184.774 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26352:185.208 Data: 00 00 00 00 +T3F74 26352:185.231 - 0.484ms returns 4 (0x4) +T062C 26352:204.780 JLINK_IsHalted() +T062C 26352:205.850 - 1.089ms returns FALSE +T062C 26352:307.039 JLINK_HasError() +T062C 26352:307.181 JLINK_IsHalted() +T062C 26352:308.373 - 1.210ms returns FALSE +T062C 26352:409.129 JLINK_HasError() +T062C 26352:409.176 JLINK_IsHalted() +T062C 26352:410.225 - 1.061ms returns FALSE +T062C 26352:510.980 JLINK_HasError() +T062C 26352:511.056 JLINK_IsHalted() +T062C 26352:512.264 - 1.228ms returns FALSE +T062C 26352:612.740 JLINK_HasError() +T062C 26352:612.815 JLINK_IsHalted() +T062C 26352:614.038 - 1.264ms returns FALSE +T062C 26352:714.300 JLINK_HasError() +T062C 26352:714.345 JLINK_HasError() +T062C 26352:714.364 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26352:714.394 Data: 8D 12 74 01 +T062C 26352:714.418 Debug reg: DWT_CYCCNT +T062C 26352:714.440 - 0.084ms returns 1 (0x1) +T3F74 26352:717.702 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26352:717.741 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26352:718.776 Data: 00 00 80 00 +T3F74 26352:718.813 - 1.119ms returns 4 (0x4) +T3F74 26352:718.856 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26352:718.880 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26352:719.387 Data: 00 00 F0 01 +T3F74 26352:719.411 - 0.563ms returns 4 (0x4) +T3F74 26352:723.001 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26352:723.032 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26352:724.278 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26352:724.318 - 1.325ms returns 16 (0x10) +T3F74 26352:724.342 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26352:724.365 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26352:724.760 Data: 1F 00 00 00 +T3F74 26352:724.785 - 0.450ms returns 4 (0x4) +T3F74 26352:724.805 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26352:724.825 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26352:725.386 Data: 00 00 00 00 00 00 00 00 00 00 00 00 83 01 00 00 ... +T3F74 26352:725.409 - 0.612ms returns 20 (0x14) +T3F74 26352:725.430 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26352:725.449 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26352:725.885 Data: 1F 03 00 00 +T3F74 26352:725.908 - 0.486ms returns 4 (0x4) +T3F74 26352:725.929 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26352:725.948 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26352:726.417 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26352:726.452 - 0.534ms returns 12 (0xC) +T3F74 26352:726.481 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26352:726.504 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26352:726.898 Data: 00 00 00 00 +T3F74 26352:726.922 - 0.449ms returns 4 (0x4) +T3F74 26352:726.943 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26352:726.962 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26352:727.392 Data: 00 00 00 00 +T3F74 26352:727.416 - 0.481ms returns 4 (0x4) +T3F74 26352:727.437 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26352:727.455 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26352:727.893 Data: 00 00 00 00 +T3F74 26352:727.916 - 0.487ms returns 4 (0x4) +T062C 26352:741.963 JLINK_IsHalted() +T062C 26352:743.018 - 1.066ms returns FALSE +T062C 26352:843.586 JLINK_HasError() +T062C 26352:843.641 JLINK_IsHalted() +T062C 26352:844.878 - 1.255ms returns FALSE +T062C 26352:945.093 JLINK_HasError() +T062C 26352:945.183 JLINK_IsHalted() +T062C 26352:946.365 - 1.200ms returns FALSE +T062C 26353:047.125 JLINK_HasError() +T062C 26353:047.204 JLINK_IsHalted() +T062C 26353:048.337 - 1.176ms returns FALSE +T062C 26353:148.594 JLINK_HasError() +T062C 26353:148.677 JLINK_IsHalted() +T062C 26353:149.933 - 1.274ms returns FALSE +T062C 26353:250.138 JLINK_HasError() +T062C 26353:250.220 JLINK_HasError() +T062C 26353:250.264 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26353:250.312 Data: 8D 12 74 01 +T062C 26353:250.333 Debug reg: DWT_CYCCNT +T062C 26353:250.352 - 0.094ms returns 1 (0x1) +T3F74 26353:252.797 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26353:252.829 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26353:254.027 Data: 00 00 80 00 +T3F74 26353:254.084 - 1.295ms returns 4 (0x4) +T3F74 26353:254.134 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26353:254.171 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26353:255.396 Data: 00 00 F0 01 +T3F74 26353:255.484 - 1.369ms returns 4 (0x4) +T3F74 26353:258.889 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26353:258.916 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26353:260.125 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26353:260.154 - 1.271ms returns 16 (0x10) +T3F74 26353:260.174 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26353:260.193 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26353:260.563 Data: 1E 00 00 00 +T3F74 26353:260.584 - 0.416ms returns 4 (0x4) +T3F74 26353:260.601 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26353:260.618 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26353:261.065 Data: 00 00 00 00 00 00 00 00 00 00 00 00 7B 02 00 00 ... +T3F74 26353:261.085 - 0.490ms returns 20 (0x14) +T3F74 26353:261.102 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26353:261.118 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26353:261.563 Data: 1F 03 00 00 +T3F74 26353:261.583 - 0.487ms returns 4 (0x4) +T3F74 26353:261.600 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26353:261.623 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26353:262.062 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26353:262.082 - 0.488ms returns 12 (0xC) +T3F74 26353:262.099 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26353:262.115 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26353:262.562 Data: 00 00 00 00 +T3F74 26353:262.582 - 0.490ms returns 4 (0x4) +T3F74 26353:262.599 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26353:262.615 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26353:263.063 Data: 00 00 00 00 +T3F74 26353:263.083 - 0.490ms returns 4 (0x4) +T3F74 26353:263.100 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26353:263.116 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26353:263.562 Data: 00 00 00 00 +T3F74 26353:263.582 - 0.489ms returns 4 (0x4) +T062C 26353:282.862 JLINK_IsHalted() +T062C 26353:284.004 - 1.160ms returns FALSE +T062C 26353:384.155 JLINK_HasError() +T062C 26353:384.238 JLINK_IsHalted() +T062C 26353:385.426 - 1.235ms returns FALSE +T062C 26353:485.815 JLINK_HasError() +T062C 26353:485.862 JLINK_IsHalted() +T062C 26353:486.946 - 1.104ms returns FALSE +T062C 26353:587.387 JLINK_HasError() +T062C 26353:587.439 JLINK_IsHalted() +T062C 26353:588.642 - 1.220ms returns FALSE +T062C 26353:689.129 JLINK_HasError() +T062C 26353:689.207 JLINK_IsHalted() +T062C 26353:690.337 - 1.148ms returns FALSE +T062C 26353:790.481 JLINK_HasError() +T062C 26353:790.566 JLINK_HasError() +T062C 26353:790.610 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26353:790.672 Data: 8D 12 74 01 +T062C 26353:790.711 Debug reg: DWT_CYCCNT +T062C 26353:790.729 - 0.125ms returns 1 (0x1) +T3F74 26353:793.210 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26353:793.243 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26353:794.524 Data: 00 00 80 00 +T3F74 26353:794.604 - 1.420ms returns 4 (0x4) +T3F74 26353:794.663 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26353:794.686 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26353:795.833 Data: 00 00 F0 01 +T3F74 26353:795.911 - 1.268ms returns 4 (0x4) +T3F74 26353:799.632 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26353:799.669 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26353:800.956 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26353:801.016 - 1.390ms returns 16 (0x10) +T3F74 26353:801.035 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26353:801.053 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26353:801.490 Data: 1E 00 00 00 +T3F74 26353:801.511 - 0.482ms returns 4 (0x4) +T3F74 26353:801.528 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26353:801.544 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26353:801.992 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B7 02 00 00 ... +T3F74 26353:802.012 - 0.490ms returns 20 (0x14) +T3F74 26353:802.029 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26353:802.045 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26353:802.486 Data: 1F 03 00 00 +T3F74 26353:802.506 - 0.484ms returns 4 (0x4) +T3F74 26353:802.523 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26353:802.539 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26353:802.986 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26353:803.005 - 0.489ms returns 12 (0xC) +T3F74 26353:803.023 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26353:803.039 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26353:803.486 Data: 00 00 00 00 +T3F74 26353:803.506 - 0.490ms returns 4 (0x4) +T3F74 26353:803.539 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26353:803.555 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26353:803.997 Data: 00 00 00 00 +T3F74 26353:804.020 - 0.489ms returns 4 (0x4) +T3F74 26353:804.043 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26353:804.062 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26353:804.621 Data: 00 00 00 00 +T3F74 26353:804.645 - 0.609ms returns 4 (0x4) +T062C 26353:817.635 JLINK_IsHalted() +T062C 26353:818.772 - 1.155ms returns FALSE +T062C 26353:919.544 JLINK_HasError() +T062C 26353:919.620 JLINK_IsHalted() +T062C 26353:920.861 - 1.260ms returns FALSE +T062C 26354:021.571 JLINK_HasError() +T062C 26354:021.608 JLINK_IsHalted() +T062C 26354:022.832 - 1.242ms returns FALSE +T062C 26354:123.531 JLINK_HasError() +T062C 26354:123.608 JLINK_IsHalted() +T062C 26354:124.717 - 1.120ms returns FALSE +T062C 26354:225.492 JLINK_HasError() +T062C 26354:225.568 JLINK_IsHalted() +T062C 26354:226.679 - 1.129ms returns FALSE +T062C 26354:327.796 JLINK_HasError() +T062C 26354:327.868 JLINK_HasError() +T062C 26354:327.912 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26354:327.972 Data: 8D 12 74 01 +T062C 26354:328.036 Debug reg: DWT_CYCCNT +T062C 26354:328.055 - 0.149ms returns 1 (0x1) +T3F74 26354:330.441 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26354:330.474 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26354:331.708 Data: 00 00 80 00 +T3F74 26354:331.742 - 1.309ms returns 4 (0x4) +T3F74 26354:331.782 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26354:331.805 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26354:332.984 Data: 00 00 F0 01 +T3F74 26354:333.046 - 1.283ms returns 4 (0x4) +T3F74 26354:336.195 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26354:336.238 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26354:337.452 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26354:337.484 - 1.297ms returns 16 (0x10) +T3F74 26354:337.509 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26354:337.532 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26354:338.070 Data: 1E 00 00 00 +T3F74 26354:338.094 - 0.592ms returns 4 (0x4) +T3F74 26354:338.114 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26354:338.135 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26354:338.679 Data: 00 00 00 00 00 00 00 00 00 00 00 00 C1 02 00 00 ... +T3F74 26354:338.703 - 0.596ms returns 20 (0x14) +T3F74 26354:338.723 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26354:338.742 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26354:339.169 Data: 1F 03 00 00 +T3F74 26354:339.193 - 0.477ms returns 4 (0x4) +T3F74 26354:339.213 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26354:339.232 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26354:339.677 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26354:339.700 - 0.495ms returns 12 (0xC) +T3F74 26354:339.724 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26354:339.743 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26354:340.179 Data: 00 00 00 00 +T3F74 26354:340.204 - 0.488ms returns 4 (0x4) +T3F74 26354:340.235 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26354:340.254 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26354:340.675 Data: 00 00 00 00 +T3F74 26354:340.698 - 0.471ms returns 4 (0x4) +T3F74 26354:340.720 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26354:340.739 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26354:341.174 Data: 00 00 00 00 +T3F74 26354:341.197 - 0.485ms returns 4 (0x4) +T062C 26354:352.799 JLINK_IsHalted() +T062C 26354:353.985 - 1.205ms returns FALSE +T062C 26354:454.921 JLINK_HasError() +T062C 26354:454.960 JLINK_IsHalted() +T062C 26354:456.094 - 1.176ms returns FALSE +T062C 26354:556.771 JLINK_HasError() +T062C 26354:556.818 JLINK_IsHalted() +T062C 26354:557.914 - 1.127ms returns FALSE +T062C 26354:658.114 JLINK_HasError() +T062C 26354:658.201 JLINK_IsHalted() +T062C 26354:659.470 - 1.287ms returns FALSE +T062C 26354:759.679 JLINK_HasError() +T062C 26354:759.752 JLINK_IsHalted() +T062C 26354:760.981 - 1.271ms returns FALSE +T062C 26354:861.311 JLINK_HasError() +T062C 26354:861.397 JLINK_HasError() +T062C 26354:861.416 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26354:861.445 Data: 8D 12 74 01 +T062C 26354:861.470 Debug reg: DWT_CYCCNT +T062C 26354:861.492 - 0.084ms returns 1 (0x1) +T3F74 26354:865.536 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26354:865.577 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26354:866.707 Data: 00 00 80 00 +T3F74 26354:866.763 - 1.233ms returns 4 (0x4) +T3F74 26354:866.797 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26354:866.817 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26354:867.224 Data: 00 00 F0 01 +T3F74 26354:867.245 - 0.454ms returns 4 (0x4) +T3F74 26354:870.218 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26354:870.264 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26354:871.504 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26354:871.538 - 1.331ms returns 16 (0x10) +T3F74 26354:871.562 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26354:871.585 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26354:871.979 Data: 1E 00 00 00 +T3F74 26354:872.002 - 0.448ms returns 4 (0x4) +T3F74 26354:872.023 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26354:872.042 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26354:872.605 Data: 00 00 00 00 00 00 00 00 00 00 00 00 53 01 00 00 ... +T3F74 26354:872.629 - 0.613ms returns 20 (0x14) +T3F74 26354:872.649 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26354:872.667 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26354:873.100 Data: 1F 03 00 00 +T3F74 26354:873.123 - 0.482ms returns 4 (0x4) +T3F74 26354:873.143 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26354:873.162 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26354:873.809 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26354:874.140 - 1.011ms returns 12 (0xC) +T3F74 26354:874.208 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26354:874.235 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26354:875.357 Data: 00 00 00 00 +T3F74 26354:875.382 - 1.182ms returns 4 (0x4) +T3F74 26354:875.416 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26354:875.435 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26354:875.854 Data: 00 00 00 00 +T3F74 26354:875.878 - 0.473ms returns 4 (0x4) +T3F74 26354:875.904 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26354:875.924 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26354:876.355 Data: 00 00 00 00 +T3F74 26354:876.380 - 0.484ms returns 4 (0x4) +T062C 26354:888.199 JLINK_IsHalted() +T062C 26354:889.231 - 1.042ms returns FALSE +T062C 26354:989.437 JLINK_HasError() +T062C 26354:989.482 JLINK_IsHalted() +T062C 26354:990.710 - 1.248ms returns FALSE +T062C 26355:091.895 JLINK_HasError() +T062C 26355:091.970 JLINK_IsHalted() +T062C 26355:093.237 - 1.286ms returns FALSE +T062C 26355:193.399 JLINK_HasError() +T062C 26355:193.480 JLINK_IsHalted() +T062C 26355:194.570 - 1.104ms returns FALSE +T062C 26355:294.710 JLINK_HasError() +T062C 26355:294.792 JLINK_IsHalted() +T062C 26355:296.176 - 1.416ms returns FALSE +T062C 26355:396.887 JLINK_HasError() +T062C 26355:396.919 JLINK_HasError() +T062C 26355:396.935 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26355:396.960 Data: 8D 12 74 01 +T062C 26355:396.981 Debug reg: DWT_CYCCNT +T062C 26355:397.000 - 0.071ms returns 1 (0x1) +T3F74 26355:399.435 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26355:399.469 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26355:400.686 Data: 00 00 80 00 +T3F74 26355:400.766 - 1.356ms returns 4 (0x4) +T3F74 26355:400.826 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26355:400.849 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26355:401.918 Data: 00 00 F0 01 +T3F74 26355:401.951 - 1.133ms returns 4 (0x4) +T3F74 26355:405.363 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26355:405.394 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26355:406.647 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26355:406.731 - 1.389ms returns 16 (0x10) +T3F74 26355:406.789 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26355:406.830 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26355:408.014 Data: 1E 00 00 00 +T3F74 26355:408.093 - 1.322ms returns 4 (0x4) +T3F74 26355:408.130 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26355:408.154 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26355:408.653 Data: 00 00 00 00 00 00 00 00 00 00 00 00 81 01 00 00 ... +T3F74 26355:408.673 - 0.549ms returns 20 (0x14) +T3F74 26355:408.690 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26355:408.707 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26355:409.161 Data: 1F 03 00 00 +T3F74 26355:409.181 - 0.497ms returns 4 (0x4) +T3F74 26355:409.198 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26355:409.215 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26355:409.647 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26355:409.667 - 0.475ms returns 12 (0xC) +T3F74 26355:409.734 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26355:409.750 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26355:410.154 Data: 00 00 00 00 +T3F74 26355:410.174 - 0.446ms returns 4 (0x4) +T3F74 26355:410.191 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26355:410.207 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26355:410.647 Data: 00 00 00 00 +T3F74 26355:410.667 - 0.482ms returns 4 (0x4) +T3F74 26355:410.684 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26355:410.700 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26355:411.155 Data: 00 00 00 00 +T3F74 26355:411.175 - 0.497ms returns 4 (0x4) +T062C 26355:423.093 JLINK_IsHalted() +T062C 26355:424.183 - 1.108ms returns FALSE +T062C 26355:524.396 JLINK_HasError() +T062C 26355:524.478 JLINK_IsHalted() +T062C 26355:525.787 - 1.351ms returns FALSE +T062C 26355:626.294 JLINK_HasError() +T062C 26355:626.345 JLINK_IsHalted() +T062C 26355:627.424 - 1.113ms returns FALSE +T062C 26355:727.654 JLINK_HasError() +T062C 26355:727.739 JLINK_IsHalted() +T062C 26355:728.964 - 1.243ms returns FALSE +T062C 26355:829.711 JLINK_HasError() +T062C 26355:829.799 JLINK_IsHalted() +T062C 26355:830.864 - 1.083ms returns FALSE +T062C 26355:931.077 JLINK_HasError() +T062C 26355:931.161 JLINK_HasError() +T062C 26355:931.206 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26355:931.260 Data: 8D 12 74 01 +T062C 26355:931.280 Debug reg: DWT_CYCCNT +T062C 26355:931.298 - 0.099ms returns 1 (0x1) +T3F74 26355:933.910 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26355:933.948 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26355:934.987 Data: 00 00 80 00 +T3F74 26355:935.023 - 1.122ms returns 4 (0x4) +T3F74 26355:935.081 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26355:935.105 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26355:935.583 Data: 00 00 F0 01 +T3F74 26355:935.604 - 0.529ms returns 4 (0x4) +T3F74 26355:938.604 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26355:938.632 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26355:939.872 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26355:939.904 - 1.308ms returns 16 (0x10) +T3F74 26355:939.928 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26355:939.951 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26355:940.459 Data: 1E 00 00 00 +T3F74 26355:940.483 - 0.562ms returns 4 (0x4) +T3F74 26355:940.503 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26355:940.523 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26355:941.093 Data: 00 00 00 00 00 00 00 00 00 00 00 00 95 01 00 00 ... +T3F74 26355:941.116 - 0.620ms returns 20 (0x14) +T3F74 26355:941.136 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26355:941.155 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26355:941.581 Data: 1F 03 00 00 +T3F74 26355:941.601 - 0.471ms returns 4 (0x4) +T3F74 26355:941.618 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26355:941.634 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26355:942.081 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26355:942.101 - 0.490ms returns 12 (0xC) +T3F74 26355:942.118 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26355:942.134 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26355:942.577 Data: 00 00 00 00 +T3F74 26355:942.607 - 0.496ms returns 4 (0x4) +T3F74 26355:942.625 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26355:942.641 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26355:943.076 Data: 00 00 00 00 +T3F74 26355:943.096 - 0.477ms returns 4 (0x4) +T3F74 26355:943.113 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26355:943.129 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26355:943.584 Data: 00 00 00 00 +T3F74 26355:943.610 - 0.505ms returns 4 (0x4) +T062C 26355:955.833 JLINK_IsHalted() +T062C 26355:956.967 - 1.144ms returns FALSE +T062C 26356:057.153 JLINK_HasError() +T062C 26356:057.236 JLINK_IsHalted() +T062C 26356:058.409 - 1.216ms returns FALSE +T062C 26356:158.636 JLINK_HasError() +T062C 26356:158.708 JLINK_IsHalted() +T062C 26356:159.884 - 1.217ms returns FALSE +T062C 26356:260.669 JLINK_HasError() +T062C 26356:260.703 JLINK_IsHalted() +T062C 26356:261.794 - 1.099ms returns FALSE +T062C 26356:362.474 JLINK_HasError() +T062C 26356:362.500 JLINK_IsHalted() +T062C 26356:363.668 - 1.210ms returns FALSE +T062C 26356:463.905 JLINK_HasError() +T062C 26356:463.977 JLINK_HasError() +T062C 26356:464.021 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26356:464.081 Data: 8D 12 74 01 +T062C 26356:464.102 Debug reg: DWT_CYCCNT +T062C 26356:464.120 - 0.106ms returns 1 (0x1) +T3F74 26356:466.584 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26356:466.617 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26356:467.789 Data: 00 00 80 00 +T3F74 26356:467.869 - 1.304ms returns 4 (0x4) +T3F74 26356:467.930 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26356:467.953 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26356:469.099 Data: 00 00 F0 01 +T3F74 26356:469.177 - 1.266ms returns 4 (0x4) +T3F74 26356:472.610 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26356:472.642 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26356:473.770 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26356:473.794 - 1.191ms returns 16 (0x10) +T3F74 26356:473.814 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26356:473.834 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26356:474.276 Data: 1E 00 00 00 +T3F74 26356:474.300 - 0.493ms returns 4 (0x4) +T3F74 26356:474.320 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26356:474.339 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26356:474.888 Data: 00 00 00 00 00 00 00 00 00 00 00 00 9F 00 00 00 ... +T3F74 26356:474.911 - 0.604ms returns 20 (0x14) +T3F74 26356:474.935 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26356:474.951 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26356:475.398 Data: 1F 03 00 00 +T3F74 26356:475.433 - 0.506ms returns 4 (0x4) +T3F74 26356:475.460 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26356:475.482 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26356:476.024 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26356:476.053 - 0.601ms returns 12 (0xC) +T3F74 26356:476.075 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26356:476.096 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26356:476.653 Data: 00 00 00 00 +T3F74 26356:476.677 - 0.610ms returns 4 (0x4) +T3F74 26356:476.698 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26356:476.717 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26356:477.142 Data: 00 00 00 00 +T3F74 26356:477.165 - 0.475ms returns 4 (0x4) +T3F74 26356:477.185 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26356:477.204 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26356:477.636 Data: 00 00 00 00 +T3F74 26356:477.656 - 0.477ms returns 4 (0x4) +T062C 26356:488.640 JLINK_IsHalted() +T062C 26356:489.793 - 1.178ms returns FALSE +T062C 26356:590.570 JLINK_HasError() +T062C 26356:590.612 JLINK_IsHalted() +T062C 26356:591.744 - 1.152ms returns FALSE +T062C 26356:692.209 JLINK_HasError() +T062C 26356:692.299 JLINK_IsHalted() +T062C 26356:693.374 - 1.093ms returns FALSE +T062C 26356:793.586 JLINK_HasError() +T062C 26356:793.684 JLINK_IsHalted() +T062C 26356:794.942 - 1.276ms returns FALSE +T062C 26356:895.726 JLINK_HasError() +T062C 26356:895.804 JLINK_IsHalted() +T062C 26356:896.948 - 1.163ms returns FALSE +T062C 26356:997.538 JLINK_HasError() +T062C 26356:997.582 JLINK_HasError() +T062C 26356:997.602 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26356:997.631 Data: 8D 12 74 01 +T062C 26356:997.655 Debug reg: DWT_CYCCNT +T062C 26356:997.677 - 0.083ms returns 1 (0x1) +T3F74 26357:001.797 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26357:001.830 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26357:003.044 Data: 00 00 80 00 +T3F74 26357:003.104 - 1.313ms returns 4 (0x4) +T3F74 26357:003.138 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26357:003.158 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26357:003.566 Data: 00 00 F0 01 +T3F74 26357:003.586 - 0.455ms returns 4 (0x4) +T3F74 26357:006.567 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26357:006.606 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26357:007.846 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26357:007.879 - 1.320ms returns 16 (0x10) +T3F74 26357:007.903 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26357:007.926 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26357:008.325 Data: 1F 00 00 00 +T3F74 26357:008.348 - 0.453ms returns 4 (0x4) +T3F74 26357:008.369 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26357:008.388 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26357:008.946 Data: 00 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 ... +T3F74 26357:008.972 - 0.610ms returns 20 (0x14) +T3F74 26357:008.993 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26357:009.014 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26357:009.440 Data: 1F 03 00 00 +T3F74 26357:009.464 - 0.478ms returns 4 (0x4) +T3F74 26357:009.484 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26357:009.503 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26357:009.941 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26357:009.964 - 0.488ms returns 12 (0xC) +T3F74 26357:009.985 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26357:010.003 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26357:010.440 Data: 00 00 00 00 +T3F74 26357:010.463 - 0.486ms returns 4 (0x4) +T3F74 26357:010.483 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26357:010.502 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26357:010.945 Data: 00 00 00 00 +T3F74 26357:010.968 - 0.492ms returns 4 (0x4) +T3F74 26357:010.988 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26357:011.007 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26357:011.451 Data: 00 00 00 00 +T3F74 26357:011.474 - 0.493ms returns 4 (0x4) +T062C 26357:031.317 JLINK_IsHalted() +T062C 26357:032.475 - 1.177ms returns FALSE +T062C 26357:133.540 JLINK_HasError() +T062C 26357:133.620 JLINK_IsHalted() +T062C 26357:134.803 - 1.232ms returns FALSE +T062C 26357:235.553 JLINK_HasError() +T062C 26357:235.587 JLINK_IsHalted() +T062C 26357:236.780 - 1.211ms returns FALSE +T062C 26357:336.992 JLINK_HasError() +T062C 26357:337.063 JLINK_IsHalted() +T062C 26357:338.200 - 1.175ms returns FALSE +T062C 26357:438.416 JLINK_HasError() +T062C 26357:438.487 JLINK_IsHalted() +T062C 26357:439.771 - 1.329ms returns FALSE +T062C 26357:539.981 JLINK_HasError() +T062C 26357:540.059 JLINK_HasError() +T062C 26357:540.105 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26357:540.171 Data: 8D 12 74 01 +T062C 26357:540.191 Debug reg: DWT_CYCCNT +T062C 26357:540.210 - 0.112ms returns 1 (0x1) +T3F74 26357:542.734 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26357:542.770 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26357:543.968 Data: 00 00 80 00 +T3F74 26357:544.030 - 1.303ms returns 4 (0x4) +T3F74 26357:544.065 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26357:544.084 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26357:544.493 Data: 00 00 F0 01 +T3F74 26357:544.524 - 0.467ms returns 4 (0x4) +T3F74 26357:547.807 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26357:547.838 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26357:548.999 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26357:549.027 - 1.227ms returns 16 (0x10) +T3F74 26357:549.048 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26357:549.067 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26357:549.633 Data: 1E 00 00 00 +T3F74 26357:549.662 - 0.622ms returns 4 (0x4) +T3F74 26357:549.683 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26357:549.704 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26357:550.272 Data: 00 00 00 00 00 00 00 00 00 00 00 00 07 00 00 00 ... +T3F74 26357:550.296 - 0.621ms returns 20 (0x14) +T3F74 26357:550.317 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26357:550.337 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26357:550.744 Data: 1F 03 00 00 +T3F74 26357:550.769 - 0.459ms returns 4 (0x4) +T3F74 26357:550.789 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26357:550.808 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26357:551.244 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26357:551.267 - 0.486ms returns 12 (0xC) +T3F74 26357:551.287 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26357:551.306 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26357:551.742 Data: 00 00 00 00 +T3F74 26357:551.766 - 0.486ms returns 4 (0x4) +T3F74 26357:551.786 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26357:551.805 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26357:552.249 Data: 00 00 00 00 +T3F74 26357:552.273 - 0.494ms returns 4 (0x4) +T3F74 26357:552.296 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26357:552.315 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26357:552.751 Data: 00 00 00 00 +T3F74 26357:552.775 - 0.486ms returns 4 (0x4) +T062C 26357:571.675 JLINK_IsHalted() +T062C 26357:572.792 - 1.135ms returns FALSE +T062C 26357:673.073 JLINK_HasError() +T062C 26357:673.179 JLINK_IsHalted() +T062C 26357:674.495 - 1.335ms returns FALSE +T062C 26357:774.640 JLINK_HasError() +T062C 26357:774.687 JLINK_IsHalted() +T062C 26357:775.774 - 1.119ms returns FALSE +T062C 26357:876.826 JLINK_HasError() +T062C 26357:876.913 JLINK_IsHalted() +T062C 26357:878.129 - 1.236ms returns FALSE +T062C 26357:978.314 JLINK_HasError() +T062C 26357:978.394 JLINK_IsHalted() +T062C 26357:979.612 - 1.236ms returns FALSE +T062C 26358:080.328 JLINK_HasError() +T062C 26358:080.405 JLINK_HasError() +T062C 26358:080.432 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26358:080.461 Data: 8D 12 74 01 +T062C 26358:080.485 Debug reg: DWT_CYCCNT +T062C 26358:080.508 - 0.084ms returns 1 (0x1) +T3F74 26358:085.493 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26358:085.526 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26358:086.641 Data: 00 00 80 00 +T3F74 26358:086.706 - 1.220ms returns 4 (0x4) +T3F74 26358:086.739 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26358:086.759 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26358:087.166 Data: 00 00 F0 01 +T3F74 26358:087.186 - 0.454ms returns 4 (0x4) +T3F74 26358:090.657 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26358:090.688 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26358:091.931 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26358:091.957 - 1.308ms returns 16 (0x10) +T3F74 26358:091.978 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26358:091.997 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26358:092.429 Data: 1E 00 00 00 +T3F74 26358:092.453 - 0.483ms returns 4 (0x4) +T3F74 26358:092.474 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26358:092.493 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26358:093.042 Data: 00 00 00 00 00 00 00 00 00 00 00 00 55 02 00 00 ... +T3F74 26358:093.062 - 0.595ms returns 20 (0x14) +T3F74 26358:093.079 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26358:093.102 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26358:093.541 Data: 1F 03 00 00 +T3F74 26358:093.561 - 0.488ms returns 4 (0x4) +T3F74 26358:093.578 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26358:093.594 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26358:094.042 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26358:094.061 - 0.490ms returns 12 (0xC) +T3F74 26358:094.079 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26358:094.095 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26358:094.591 Data: 00 00 00 00 +T3F74 26358:094.627 - 0.557ms returns 4 (0x4) +T3F74 26358:094.654 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26358:094.677 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26358:095.203 Data: 00 00 00 00 +T3F74 26358:095.234 - 0.587ms returns 4 (0x4) +T3F74 26358:095.256 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26358:095.277 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26358:095.672 Data: 00 00 00 00 +T3F74 26358:095.696 - 0.448ms returns 4 (0x4) +T062C 26358:107.343 JLINK_IsHalted() +T062C 26358:108.442 - 1.116ms returns FALSE +T062C 26358:209.626 JLINK_HasError() +T062C 26358:209.710 JLINK_IsHalted() +T062C 26358:210.913 - 1.253ms returns FALSE +T062C 26358:311.165 JLINK_HasError() +T062C 26358:311.239 JLINK_IsHalted() +T062C 26358:312.412 - 1.193ms returns FALSE +T062C 26358:413.345 JLINK_HasError() +T062C 26358:413.419 JLINK_IsHalted() +T062C 26358:414.543 - 1.142ms returns FALSE +T062C 26358:515.307 JLINK_HasError() +T062C 26358:515.383 JLINK_IsHalted() +T062C 26358:516.572 - 1.207ms returns FALSE +T062C 26358:617.250 JLINK_HasError() +T062C 26358:617.323 JLINK_HasError() +T062C 26358:617.368 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26358:617.431 Data: 8D 12 74 01 +T062C 26358:617.451 Debug reg: DWT_CYCCNT +T062C 26358:617.470 - 0.109ms returns 1 (0x1) +T3F74 26358:619.884 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26358:619.917 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26358:621.070 Data: 00 00 80 00 +T3F74 26358:621.136 - 1.259ms returns 4 (0x4) +T3F74 26358:621.171 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26358:621.191 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26358:621.595 Data: 00 00 F0 01 +T3F74 26358:621.616 - 0.451ms returns 4 (0x4) +T3F74 26358:624.828 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26358:624.855 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26358:625.986 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26358:626.026 - 1.206ms returns 16 (0x10) +T3F74 26358:626.048 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26358:626.069 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26358:626.475 Data: 1F 00 00 00 +T3F74 26358:626.499 - 0.458ms returns 4 (0x4) +T3F74 26358:626.520 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26358:626.539 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26358:627.139 Data: 00 00 00 00 00 00 00 00 00 00 00 00 87 01 00 00 ... +T3F74 26358:627.167 - 0.655ms returns 20 (0x14) +T3F74 26358:627.188 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26358:627.209 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26358:627.734 Data: 1F 03 00 00 +T3F74 26358:627.758 - 0.577ms returns 4 (0x4) +T3F74 26358:627.778 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26358:627.798 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26358:628.225 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26358:628.245 - 0.473ms returns 12 (0xC) +T3F74 26358:628.262 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26358:628.278 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26358:628.725 Data: 00 00 00 00 +T3F74 26358:628.745 - 0.489ms returns 4 (0x4) +T3F74 26358:628.762 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26358:628.778 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26358:629.220 Data: 00 00 00 00 +T3F74 26358:629.240 - 0.485ms returns 4 (0x4) +T3F74 26358:629.257 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26358:629.279 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26358:629.745 Data: 00 00 00 00 +T3F74 26358:629.765 - 0.515ms returns 4 (0x4) +T062C 26358:649.065 JLINK_IsHalted() +T062C 26358:650.261 - 1.215ms returns FALSE +T062C 26358:750.467 JLINK_HasError() +T062C 26358:750.549 JLINK_IsHalted() +T062C 26358:751.782 - 1.253ms returns FALSE +T062C 26358:851.888 JLINK_HasError() +T062C 26358:851.935 JLINK_IsHalted() +T062C 26358:853.119 - 1.217ms returns FALSE +T062C 26358:953.893 JLINK_HasError() +T062C 26358:953.988 JLINK_IsHalted() +T062C 26358:955.162 - 1.219ms returns FALSE +T062C 26359:055.340 JLINK_HasError() +T062C 26359:055.417 JLINK_IsHalted() +T062C 26359:056.677 - 1.306ms returns FALSE +T062C 26359:157.444 JLINK_HasError() +T062C 26359:157.485 JLINK_HasError() +T062C 26359:157.500 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26359:157.527 Data: 8D 12 74 01 +T062C 26359:157.547 Debug reg: DWT_CYCCNT +T062C 26359:157.566 - 0.072ms returns 1 (0x1) +T3F74 26359:160.446 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26359:160.484 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26359:161.673 Data: 00 00 80 00 +T3F74 26359:161.753 - 1.326ms returns 4 (0x4) +T3F74 26359:161.820 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26359:161.843 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26359:162.990 Data: 00 00 F0 01 +T3F74 26359:163.088 - 1.287ms returns 4 (0x4) +T3F74 26359:166.327 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26359:166.354 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26359:167.581 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26359:167.609 - 1.289ms returns 16 (0x10) +T3F74 26359:167.630 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26359:167.649 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26359:168.028 Data: 1E 00 00 00 +T3F74 26359:168.049 - 0.425ms returns 4 (0x4) +T3F74 26359:168.066 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26359:168.082 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26359:168.528 Data: 00 00 00 00 00 00 00 00 00 00 00 00 9F 00 00 00 ... +T3F74 26359:168.548 - 0.489ms returns 20 (0x14) +T3F74 26359:168.565 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26359:168.581 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26359:169.027 Data: 1F 03 00 00 +T3F74 26359:169.048 - 0.489ms returns 4 (0x4) +T3F74 26359:169.065 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26359:169.081 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26359:169.526 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26359:169.546 - 0.488ms returns 12 (0xC) +T3F74 26359:169.563 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26359:169.579 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26359:170.027 Data: 00 00 00 00 +T3F74 26359:170.047 - 0.490ms returns 4 (0x4) +T3F74 26359:170.064 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26359:170.080 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26359:170.522 Data: 00 00 00 00 +T3F74 26359:170.542 - 0.484ms returns 4 (0x4) +T3F74 26359:170.559 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26359:170.575 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26359:171.022 Data: 00 00 00 00 +T3F74 26359:171.042 - 0.489ms returns 4 (0x4) +T062C 26359:190.375 JLINK_IsHalted() +T062C 26359:191.572 - 1.215ms returns FALSE +T062C 26359:291.760 JLINK_HasError() +T062C 26359:291.843 JLINK_IsHalted() +T062C 26359:293.023 - 1.200ms returns FALSE +T062C 26359:393.135 JLINK_HasError() +T062C 26359:393.171 JLINK_IsHalted() +T062C 26359:394.320 - 1.190ms returns FALSE +T062C 26359:495.561 JLINK_HasError() +T062C 26359:495.638 JLINK_IsHalted() +T062C 26359:496.880 - 1.284ms returns FALSE +T062C 26359:597.508 JLINK_HasError() +T062C 26359:597.592 JLINK_IsHalted() +T062C 26359:598.616 - 1.041ms returns FALSE +T062C 26359:699.305 JLINK_HasError() +T062C 26359:699.343 JLINK_HasError() +T062C 26359:699.358 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26359:699.391 Data: 8D 12 74 01 +T062C 26359:699.418 Debug reg: DWT_CYCCNT +T062C 26359:699.436 - 0.084ms returns 1 (0x1) +T3F74 26359:701.878 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26359:701.912 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26359:702.988 Data: 00 00 80 00 +T3F74 26359:703.028 - 1.157ms returns 4 (0x4) +T3F74 26359:703.074 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26359:703.098 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26359:703.585 Data: 00 00 F0 01 +T3F74 26359:703.608 - 0.542ms returns 4 (0x4) +T3F74 26359:706.793 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26359:706.820 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26359:708.012 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26359:708.040 - 1.254ms returns 16 (0x10) +T3F74 26359:708.061 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26359:708.080 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26359:708.456 Data: 1E 00 00 00 +T3F74 26359:708.476 - 0.422ms returns 4 (0x4) +T3F74 26359:708.494 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26359:708.510 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26359:708.955 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B9 01 00 00 ... +T3F74 26359:708.975 - 0.488ms returns 20 (0x14) +T3F74 26359:708.993 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26359:709.009 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26359:709.524 Data: 1F 03 00 00 +T3F74 26359:709.548 - 0.563ms returns 4 (0x4) +T3F74 26359:709.568 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26359:709.587 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26359:710.082 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26359:710.105 - 0.545ms returns 12 (0xC) +T3F74 26359:710.126 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26359:710.144 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26359:710.678 Data: 00 00 00 00 +T3F74 26359:710.701 - 0.583ms returns 4 (0x4) +T3F74 26359:710.722 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26359:710.740 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26359:711.219 Data: 00 00 00 00 +T3F74 26359:711.239 - 0.524ms returns 4 (0x4) +T3F74 26359:711.256 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26359:711.272 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26359:711.705 Data: 00 00 00 00 +T3F74 26359:711.725 - 0.476ms returns 4 (0x4) +T062C 26359:723.114 JLINK_IsHalted() +T062C 26359:724.234 - 1.138ms returns FALSE +T062C 26359:824.861 JLINK_HasError() +T062C 26359:824.941 JLINK_IsHalted() +T062C 26359:826.125 - 1.203ms returns FALSE +T062C 26359:926.812 JLINK_HasError() +T062C 26359:926.864 JLINK_IsHalted() +T062C 26359:927.950 - 1.116ms returns FALSE +T062C 26360:028.701 JLINK_HasError() +T062C 26360:028.786 JLINK_IsHalted() +T062C 26360:029.924 - 1.146ms returns FALSE +T062C 26360:130.545 JLINK_HasError() +T062C 26360:130.622 JLINK_IsHalted() +T062C 26360:131.826 - 1.222ms returns FALSE +T062C 26360:232.368 JLINK_HasError() +T062C 26360:232.443 JLINK_HasError() +T062C 26360:232.480 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26360:232.509 Data: 8D 12 74 01 +T062C 26360:232.533 Debug reg: DWT_CYCCNT +T062C 26360:232.555 - 0.083ms returns 1 (0x1) +T3F74 26360:235.254 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26360:235.296 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26360:236.491 Data: 00 00 80 00 +T3F74 26360:236.526 - 1.280ms returns 4 (0x4) +T3F74 26360:236.565 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26360:236.588 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26360:237.023 Data: 00 00 F0 01 +T3F74 26360:237.043 - 0.485ms returns 4 (0x4) +T3F74 26360:240.021 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26360:240.048 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26360:241.283 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26360:241.315 - 1.302ms returns 16 (0x10) +T3F74 26360:241.339 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26360:241.368 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26360:241.769 Data: 1E 00 00 00 +T3F74 26360:241.793 - 0.462ms returns 4 (0x4) +T3F74 26360:241.813 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26360:241.833 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26360:242.387 Data: 00 00 00 00 00 00 00 00 00 00 00 00 2B 02 00 00 ... +T3F74 26360:242.410 - 0.605ms returns 20 (0x14) +T3F74 26360:242.431 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26360:242.449 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26360:242.893 Data: 1F 03 00 00 +T3F74 26360:242.912 - 0.488ms returns 4 (0x4) +T3F74 26360:242.929 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26360:242.946 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26360:243.398 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26360:243.423 - 0.501ms returns 12 (0xC) +T3F74 26360:243.443 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26360:243.466 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26360:243.892 Data: 00 00 00 00 +T3F74 26360:243.916 - 0.481ms returns 4 (0x4) +T3F74 26360:243.936 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26360:243.955 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26360:244.392 Data: 00 00 00 00 +T3F74 26360:244.415 - 0.487ms returns 4 (0x4) +T3F74 26360:244.435 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26360:244.454 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26360:244.883 Data: 00 00 00 00 +T3F74 26360:244.903 - 0.474ms returns 4 (0x4) +T062C 26360:257.835 JLINK_IsHalted() +T062C 26360:258.948 - 1.155ms returns FALSE +T062C 26360:359.162 JLINK_HasError() +T062C 26360:359.248 JLINK_IsHalted() +T062C 26360:360.448 - 1.218ms returns FALSE +T062C 26360:461.383 JLINK_HasError() +T062C 26360:461.427 JLINK_IsHalted() +T062C 26360:462.471 - 1.062ms returns FALSE +T062C 26360:563.504 JLINK_HasError() +T062C 26360:563.553 JLINK_IsHalted() +T062C 26360:564.576 - 1.049ms returns FALSE +T062C 26360:665.089 JLINK_HasError() +T062C 26360:665.183 JLINK_IsHalted() +T062C 26360:666.230 - 1.067ms returns FALSE +T062C 26360:767.009 JLINK_HasError() +T062C 26360:767.051 JLINK_HasError() +T062C 26360:767.067 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26360:767.095 Data: 8D 12 74 01 +T062C 26360:767.115 Debug reg: DWT_CYCCNT +T062C 26360:767.133 - 0.072ms returns 1 (0x1) +T3F74 26360:769.796 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26360:769.839 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26360:771.082 Data: 00 00 80 00 +T3F74 26360:771.118 - 1.329ms returns 4 (0x4) +T3F74 26360:771.162 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26360:771.186 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26360:772.333 Data: 00 00 F0 01 +T3F74 26360:772.370 - 1.216ms returns 4 (0x4) +T3F74 26360:775.861 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26360:775.894 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26360:777.191 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26360:777.225 - 1.372ms returns 16 (0x10) +T3F74 26360:777.251 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26360:777.274 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26360:777.701 Data: 1F 00 00 00 +T3F74 26360:777.737 - 0.494ms returns 4 (0x4) +T3F74 26360:777.763 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26360:777.788 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26360:778.317 Data: 00 00 00 00 00 00 00 00 00 00 00 00 85 01 00 00 ... +T3F74 26360:778.344 - 0.588ms returns 20 (0x14) +T3F74 26360:778.365 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26360:778.386 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26360:778.843 Data: 1F 03 00 00 +T3F74 26360:778.867 - 0.510ms returns 4 (0x4) +T3F74 26360:778.887 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26360:778.906 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26360:779.440 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26360:779.550 - 0.671ms returns 12 (0xC) +T3F74 26360:779.571 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26360:779.591 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26360:780.065 Data: 00 00 00 00 +T3F74 26360:780.089 - 0.526ms returns 4 (0x4) +T3F74 26360:780.110 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26360:780.129 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26360:780.565 Data: 00 00 00 00 +T3F74 26360:780.588 - 0.486ms returns 4 (0x4) +T3F74 26360:780.608 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26360:780.627 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26360:781.065 Data: 00 00 00 00 +T3F74 26360:781.088 - 0.488ms returns 4 (0x4) +T062C 26360:801.235 JLINK_IsHalted() +T062C 26360:802.452 - 1.227ms returns FALSE +T062C 26360:903.015 JLINK_HasError() +T062C 26360:903.079 JLINK_IsHalted() +T062C 26360:904.301 - 1.241ms returns FALSE +T062C 26361:005.090 JLINK_HasError() +T062C 26361:005.136 JLINK_IsHalted() +T062C 26361:006.181 - 1.062ms returns FALSE +T062C 26361:107.015 JLINK_HasError() +T062C 26361:107.100 JLINK_IsHalted() +T062C 26361:108.279 - 1.227ms returns FALSE +T062C 26361:209.049 JLINK_HasError() +T062C 26361:209.125 JLINK_IsHalted() +T062C 26361:210.348 - 1.241ms returns FALSE +T062C 26361:310.956 JLINK_HasError() +T062C 26361:311.044 JLINK_HasError() +T062C 26361:311.074 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26361:311.103 Data: 8D 12 74 01 +T062C 26361:311.127 Debug reg: DWT_CYCCNT +T062C 26361:311.149 - 0.082ms returns 1 (0x1) +T3F74 26361:313.550 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26361:313.583 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26361:314.643 Data: 00 00 80 00 +T3F74 26361:314.679 - 1.137ms returns 4 (0x4) +T3F74 26361:314.729 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26361:314.754 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26361:315.248 Data: 00 00 F0 01 +T3F74 26361:315.272 - 0.550ms returns 4 (0x4) +T3F74 26361:318.522 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26361:318.549 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26361:319.795 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26361:319.824 - 1.308ms returns 16 (0x10) +T3F74 26361:319.844 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26361:319.863 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26361:320.241 Data: 1E 00 00 00 +T3F74 26361:320.261 - 0.424ms returns 4 (0x4) +T3F74 26361:320.279 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26361:320.295 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26361:320.742 Data: 00 00 00 00 00 00 00 00 00 00 00 00 3B 01 00 00 ... +T3F74 26361:320.762 - 0.490ms returns 20 (0x14) +T3F74 26361:320.779 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26361:320.795 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26361:321.236 Data: 1F 03 00 00 +T3F74 26361:321.256 - 0.484ms returns 4 (0x4) +T3F74 26361:321.274 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26361:321.290 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26361:321.738 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26361:321.758 - 0.490ms returns 12 (0xC) +T3F74 26361:321.775 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26361:321.791 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26361:322.247 Data: 00 00 00 00 +T3F74 26361:322.270 - 0.503ms returns 4 (0x4) +T3F74 26361:322.291 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26361:322.310 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26361:322.747 Data: 00 00 00 00 +T3F74 26361:322.770 - 0.487ms returns 4 (0x4) +T3F74 26361:322.790 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26361:322.809 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26361:323.242 Data: 00 00 00 00 +T3F74 26361:323.265 - 0.483ms returns 4 (0x4) +T062C 26361:342.541 JLINK_IsHalted() +T062C 26361:343.624 - 1.092ms returns FALSE +T062C 26361:443.771 JLINK_HasError() +T062C 26361:443.851 JLINK_IsHalted() +T062C 26361:444.990 - 1.162ms returns FALSE +T062C 26361:546.121 JLINK_HasError() +T062C 26361:546.199 JLINK_IsHalted() +T062C 26361:547.366 - 1.187ms returns FALSE +T062C 26361:647.628 JLINK_HasError() +T062C 26361:647.706 JLINK_IsHalted() +T062C 26361:648.945 - 1.271ms returns FALSE +T062C 26361:749.492 JLINK_HasError() +T062C 26361:749.568 JLINK_IsHalted() +T062C 26361:750.722 - 1.165ms returns FALSE +T062C 26361:851.404 JLINK_HasError() +T062C 26361:851.450 JLINK_HasError() +T062C 26361:851.469 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26361:851.498 Data: 8D 12 74 01 +T062C 26361:851.522 Debug reg: DWT_CYCCNT +T062C 26361:851.544 - 0.083ms returns 1 (0x1) +T3F74 26361:853.938 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26361:853.979 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26361:855.198 Data: 00 00 80 00 +T3F74 26361:855.278 - 1.369ms returns 4 (0x4) +T3F74 26361:855.338 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26361:855.362 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26361:856.513 Data: 00 00 F0 01 +T3F74 26361:856.590 - 1.271ms returns 4 (0x4) +T3F74 26361:860.185 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26361:860.216 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26361:861.610 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26361:861.643 - 1.465ms returns 16 (0x10) +T3F74 26361:861.667 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26361:861.690 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26361:862.801 Data: 1E 00 00 00 +T3F74 26361:862.833 - 1.174ms returns 4 (0x4) +T3F74 26361:862.857 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26361:862.879 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26361:863.421 Data: 00 00 00 00 00 00 00 00 00 00 00 00 91 01 00 00 ... +T3F74 26361:863.447 - 0.598ms returns 20 (0x14) +T3F74 26361:863.468 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26361:863.487 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26361:863.927 Data: 1F 03 00 00 +T3F74 26361:863.950 - 0.490ms returns 4 (0x4) +T3F74 26361:863.970 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26361:863.989 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26361:864.422 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26361:864.442 - 0.478ms returns 12 (0xC) +T3F74 26361:864.459 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26361:864.475 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26361:864.926 Data: 00 00 00 00 +T3F74 26361:864.946 - 0.493ms returns 4 (0x4) +T3F74 26361:864.963 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26361:864.979 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26361:865.421 Data: 00 00 00 00 +T3F74 26361:865.441 - 0.485ms returns 4 (0x4) +T3F74 26361:865.458 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26361:865.474 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26361:865.920 Data: 00 00 00 00 +T3F74 26361:865.940 - 0.488ms returns 4 (0x4) +T062C 26361:878.136 JLINK_IsHalted() +T062C 26361:879.349 - 1.231ms returns FALSE +T062C 26361:979.611 JLINK_HasError() +T062C 26361:979.690 JLINK_IsHalted() +T062C 26361:980.911 - 1.262ms returns FALSE +T062C 26362:081.383 JLINK_HasError() +T062C 26362:081.437 JLINK_IsHalted() +T062C 26362:082.537 - 1.111ms returns FALSE +T062C 26362:182.733 JLINK_HasError() +T062C 26362:182.819 JLINK_IsHalted() +T062C 26362:183.998 - 1.222ms returns FALSE +T062C 26362:284.238 JLINK_HasError() +T062C 26362:284.316 JLINK_IsHalted() +T062C 26362:285.587 - 1.289ms returns FALSE +T062C 26362:385.840 JLINK_HasError() +T062C 26362:385.921 JLINK_HasError() +T062C 26362:385.959 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26362:385.984 Data: 8D 12 74 01 +T062C 26362:386.005 Debug reg: DWT_CYCCNT +T062C 26362:386.023 - 0.071ms returns 1 (0x1) +T3F74 26362:388.652 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26362:388.691 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26362:389.756 Data: 00 00 80 00 +T3F74 26362:389.788 - 1.143ms returns 4 (0x4) +T3F74 26362:389.836 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26362:389.861 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26362:390.351 Data: 00 00 F0 01 +T3F74 26362:390.372 - 0.542ms returns 4 (0x4) +T3F74 26362:393.655 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26362:393.687 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26362:394.902 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26362:394.930 - 1.281ms returns 16 (0x10) +T3F74 26362:394.950 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26362:394.970 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26362:395.484 Data: 1F 00 00 00 +T3F74 26362:395.508 - 0.565ms returns 4 (0x4) +T3F74 26362:395.529 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26362:395.548 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26362:396.114 Data: 00 00 00 00 00 00 00 00 00 00 00 00 7B 00 00 00 ... +T3F74 26362:396.137 - 0.616ms returns 20 (0x14) +T3F74 26362:396.158 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26362:396.177 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26362:396.607 Data: 1F 03 00 00 +T3F74 26362:396.630 - 0.480ms returns 4 (0x4) +T3F74 26362:396.650 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26362:396.669 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26362:397.097 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26362:397.117 - 0.474ms returns 12 (0xC) +T3F74 26362:397.134 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26362:397.150 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26362:397.594 Data: 00 00 00 00 +T3F74 26362:397.614 - 0.487ms returns 4 (0x4) +T3F74 26362:397.631 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26362:397.647 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26362:398.094 Data: 00 00 00 00 +T3F74 26362:398.113 - 0.488ms returns 4 (0x4) +T3F74 26362:398.130 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26362:398.146 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26362:398.594 Data: 00 00 00 00 +T3F74 26362:398.614 - 0.490ms returns 4 (0x4) +T062C 26362:420.761 JLINK_IsHalted() +T062C 26362:421.876 - 1.134ms returns FALSE +T062C 26362:522.553 JLINK_HasError() +T062C 26362:522.591 JLINK_IsHalted() +T062C 26362:523.729 - 1.180ms returns FALSE +T062C 26362:624.304 JLINK_HasError() +T062C 26362:624.384 JLINK_IsHalted() +T062C 26362:625.476 - 1.102ms returns FALSE +T062C 26362:725.722 JLINK_HasError() +T062C 26362:725.807 JLINK_IsHalted() +T062C 26362:727.059 - 1.300ms returns FALSE +T062C 26362:827.290 JLINK_HasError() +T062C 26362:827.370 JLINK_IsHalted() +T062C 26362:828.499 - 1.172ms returns FALSE +T062C 26362:928.894 JLINK_HasError() +T062C 26362:928.941 JLINK_HasError() +T062C 26362:928.963 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26362:929.002 Data: 8D 12 74 01 +T062C 26362:929.034 Debug reg: DWT_CYCCNT +T062C 26362:929.063 - 0.110ms returns 1 (0x1) +T3F74 26362:932.790 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26362:932.862 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26362:933.987 Data: 00 00 80 00 +T3F74 26362:934.057 - 1.283ms returns 4 (0x4) +T3F74 26362:934.144 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26362:934.185 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26362:935.314 Data: 00 00 F0 01 +T3F74 26362:935.357 - 1.224ms returns 4 (0x4) +T3F74 26362:941.644 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26362:941.719 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26362:942.955 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26362:942.994 - 1.360ms returns 16 (0x10) +T3F74 26362:943.022 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26362:943.046 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26362:943.575 Data: 1F 00 00 00 +T3F74 26362:943.666 - 0.656ms returns 4 (0x4) +T3F74 26362:943.703 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26362:943.736 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26362:944.294 Data: 00 00 00 00 00 00 00 00 00 00 00 00 9F 01 00 00 ... +T3F74 26362:944.329 - 0.635ms returns 20 (0x14) +T3F74 26362:944.351 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26362:944.371 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26362:944.813 Data: 1F 03 00 00 +T3F74 26362:944.849 - 0.505ms returns 4 (0x4) +T3F74 26362:944.870 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26362:944.890 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26362:945.439 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26362:945.473 - 0.614ms returns 12 (0xC) +T3F74 26362:945.503 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26362:945.531 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26362:946.079 Data: 00 00 00 00 +T3F74 26362:946.120 - 0.627ms returns 4 (0x4) +T3F74 26362:946.148 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26362:946.175 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26362:946.816 Data: 00 00 00 00 +T3F74 26362:946.861 - 0.724ms returns 4 (0x4) +T3F74 26362:946.892 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26362:946.926 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26362:948.087 Data: 00 00 00 00 +T3F74 26362:948.118 - 1.234ms returns 4 (0x4) +T062C 26362:967.735 JLINK_IsHalted() +T062C 26362:969.028 - 1.327ms returns FALSE +T062C 26363:069.984 JLINK_HasError() +T062C 26363:070.066 JLINK_IsHalted() +T062C 26363:071.165 - 1.117ms returns FALSE +T062C 26363:171.738 JLINK_HasError() +T062C 26363:171.787 JLINK_IsHalted() +T062C 26363:172.920 - 1.152ms returns FALSE +T062C 26363:273.690 JLINK_HasError() +T062C 26363:273.764 JLINK_IsHalted() +T062C 26363:274.997 - 1.251ms returns FALSE +T062C 26363:375.145 JLINK_HasError() +T062C 26363:375.219 JLINK_IsHalted() +T062C 26363:376.317 - 1.140ms returns FALSE +T062C 26363:477.424 JLINK_HasError() +T062C 26363:477.498 JLINK_HasError() +T062C 26363:477.542 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26363:477.603 Data: 8D 12 74 01 +T062C 26363:477.664 Debug reg: DWT_CYCCNT +T062C 26363:477.717 - 0.193ms returns 1 (0x1) +T3F74 26363:480.414 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26363:480.451 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26363:481.493 Data: 00 00 80 00 +T3F74 26363:481.529 - 1.123ms returns 4 (0x4) +T3F74 26363:481.570 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26363:481.594 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26363:482.081 Data: 00 00 F0 01 +T3F74 26363:482.105 - 0.542ms returns 4 (0x4) +T3F74 26363:485.942 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26363:485.974 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26363:487.304 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26363:487.367 - 1.433ms returns 16 (0x10) +T3F74 26363:487.391 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26363:487.414 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26363:487.839 Data: 1F 00 00 00 +T3F74 26363:487.863 - 0.479ms returns 4 (0x4) +T3F74 26363:487.883 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26363:487.903 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26363:488.454 Data: 00 00 00 00 00 00 00 00 00 00 00 00 91 00 00 00 ... +T3F74 26363:488.474 - 0.597ms returns 20 (0x14) +T3F74 26363:488.491 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26363:488.507 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26363:488.953 Data: 1F 03 00 00 +T3F74 26363:488.973 - 0.488ms returns 4 (0x4) +T3F74 26363:488.990 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26363:489.006 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26363:489.452 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26363:489.472 - 0.488ms returns 12 (0xC) +T3F74 26363:489.489 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26363:489.505 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26363:489.952 Data: 00 00 00 00 +T3F74 26363:489.972 - 0.490ms returns 4 (0x4) +T3F74 26363:489.990 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26363:490.012 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26363:490.452 Data: 00 00 00 00 +T3F74 26363:490.472 - 0.488ms returns 4 (0x4) +T3F74 26363:490.489 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26363:490.505 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26363:490.949 Data: 00 00 00 00 +T3F74 26363:490.968 - 0.486ms returns 4 (0x4) +T062C 26363:503.153 JLINK_IsHalted() +T062C 26363:504.215 - 1.080ms returns FALSE +T062C 26363:604.432 JLINK_HasError() +T062C 26363:604.513 JLINK_IsHalted() +T062C 26363:605.689 - 1.225ms returns FALSE +T062C 26363:706.069 JLINK_HasError() +T062C 26363:706.149 JLINK_IsHalted() +T062C 26363:707.301 - 1.202ms returns FALSE +T062C 26363:808.143 JLINK_HasError() +T062C 26363:808.188 JLINK_IsHalted() +T062C 26363:809.315 - 1.146ms returns FALSE +T062C 26363:909.998 JLINK_HasError() +T062C 26363:910.041 JLINK_IsHalted() +T062C 26363:911.278 - 1.271ms returns FALSE +T062C 26364:012.060 JLINK_HasError() +T062C 26364:012.145 JLINK_HasError() +T062C 26364:012.164 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26364:012.193 Data: 8D 12 74 01 +T062C 26364:012.217 Debug reg: DWT_CYCCNT +T062C 26364:012.239 - 0.083ms returns 1 (0x1) +T3F74 26364:015.195 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26364:015.228 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26364:016.339 Data: 00 00 80 00 +T3F74 26364:016.373 - 1.185ms returns 4 (0x4) +T3F74 26364:016.409 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26364:016.432 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26364:016.880 Data: 00 00 F0 01 +T3F74 26364:016.900 - 0.498ms returns 4 (0x4) +T3F74 26364:020.127 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26364:020.154 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26364:021.436 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26364:021.465 - 1.346ms returns 16 (0x10) +T3F74 26364:021.488 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26364:021.509 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26364:022.014 Data: 1E 00 00 00 +T3F74 26364:022.037 - 0.557ms returns 4 (0x4) +T3F74 26364:022.058 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26364:022.077 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26364:022.633 Data: 00 00 00 00 00 00 00 00 00 00 00 00 23 01 00 00 ... +T3F74 26364:022.653 - 0.601ms returns 20 (0x14) +T3F74 26364:022.670 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26364:022.686 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26364:023.132 Data: 1F 03 00 00 +T3F74 26364:023.153 - 0.489ms returns 4 (0x4) +T3F74 26364:023.170 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26364:023.186 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26364:023.631 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26364:023.651 - 0.488ms returns 12 (0xC) +T3F74 26364:023.668 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26364:023.685 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26364:024.131 Data: 00 00 00 00 +T3F74 26364:024.151 - 0.489ms returns 4 (0x4) +T3F74 26364:024.168 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26364:024.185 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26364:024.631 Data: 00 00 00 00 +T3F74 26364:024.651 - 0.489ms returns 4 (0x4) +T3F74 26364:024.668 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26364:024.684 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26364:025.132 Data: 00 00 00 00 +T3F74 26364:025.152 - 0.491ms returns 4 (0x4) +T062C 26364:046.713 JLINK_IsHalted() +T062C 26364:047.827 - 1.133ms returns FALSE +T062C 26364:149.517 JLINK_HasError() +T062C 26364:149.601 JLINK_IsHalted() +T062C 26364:150.848 - 1.293ms returns FALSE +T062C 26364:251.146 JLINK_HasError() +T062C 26364:251.195 JLINK_IsHalted() +T062C 26364:252.250 - 1.087ms returns FALSE +T062C 26364:352.962 JLINK_HasError() +T062C 26364:353.000 JLINK_IsHalted() +T062C 26364:354.241 - 1.282ms returns FALSE +T062C 26364:454.433 JLINK_HasError() +T062C 26364:454.510 JLINK_IsHalted() +T062C 26364:455.783 - 1.314ms returns FALSE +T062C 26364:555.982 JLINK_HasError() +T062C 26364:556.062 JLINK_HasError() +T062C 26364:556.106 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26364:556.167 Data: 8D 12 74 01 +T062C 26364:556.207 Debug reg: DWT_CYCCNT +T062C 26364:556.226 - 0.126ms returns 1 (0x1) +T3F74 26364:558.684 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26364:558.716 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26364:559.904 Data: 00 00 80 00 +T3F74 26364:559.971 - 1.294ms returns 4 (0x4) +T3F74 26364:560.005 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26364:560.025 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26364:560.442 Data: 00 00 F0 01 +T3F74 26364:560.466 - 0.471ms returns 4 (0x4) +T3F74 26364:564.105 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26364:564.138 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26364:565.321 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26364:565.357 - 1.260ms returns 16 (0x10) +T3F74 26364:565.379 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26364:565.402 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26364:565.817 Data: 1E 00 00 00 +T3F74 26364:565.841 - 0.470ms returns 4 (0x4) +T3F74 26364:565.861 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26364:565.880 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26364:566.435 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D1 02 00 00 ... +T3F74 26364:566.455 - 0.601ms returns 20 (0x14) +T3F74 26364:566.472 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26364:566.489 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26364:566.934 Data: 1F 03 00 00 +T3F74 26364:566.954 - 0.488ms returns 4 (0x4) +T3F74 26364:566.971 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26364:566.987 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26364:567.435 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26364:567.455 - 0.490ms returns 12 (0xC) +T3F74 26364:567.472 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26364:567.488 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26364:567.964 Data: 00 00 00 00 +T3F74 26364:567.984 - 0.519ms returns 4 (0x4) +T3F74 26364:568.001 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26364:568.017 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26364:568.434 Data: 00 00 00 00 +T3F74 26364:568.454 - 0.460ms returns 4 (0x4) +T3F74 26364:568.471 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26364:568.488 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26364:568.934 Data: 00 00 00 00 +T3F74 26364:568.954 - 0.489ms returns 4 (0x4) +T062C 26364:582.567 JLINK_IsHalted() +T062C 26364:583.705 - 1.156ms returns FALSE +T062C 26364:684.389 JLINK_HasError() +T062C 26364:684.477 JLINK_IsHalted() +T062C 26364:685.683 - 1.224ms returns FALSE +T062C 26364:785.886 JLINK_HasError() +T062C 26364:785.961 JLINK_IsHalted() +T062C 26364:787.162 - 1.250ms returns FALSE +T062C 26364:887.960 JLINK_HasError() +T062C 26364:888.045 JLINK_IsHalted() +T062C 26364:889.232 - 1.228ms returns FALSE +T062C 26364:990.027 JLINK_HasError() +T062C 26364:990.112 JLINK_IsHalted() +T062C 26364:991.228 - 1.134ms returns FALSE +T062C 26365:091.612 JLINK_HasError() +T062C 26365:091.686 JLINK_HasError() +T062C 26365:091.730 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26365:091.791 Data: 8D 12 74 01 +T062C 26365:091.849 Debug reg: DWT_CYCCNT +T062C 26365:091.902 - 0.194ms returns 1 (0x1) +T3F74 26365:094.540 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26365:094.572 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26365:095.706 Data: 00 00 80 00 +T3F74 26365:095.789 - 1.269ms returns 4 (0x4) +T3F74 26365:095.870 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26365:095.893 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26365:097.016 Data: 00 00 F0 01 +T3F74 26365:097.045 - 1.182ms returns 4 (0x4) +T3F74 26365:100.336 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26365:100.364 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26365:101.660 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26365:101.692 - 1.364ms returns 16 (0x10) +T3F74 26365:101.729 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26365:101.752 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26365:102.246 Data: 1E 00 00 00 +T3F74 26365:102.271 - 0.549ms returns 4 (0x4) +T3F74 26365:102.303 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26365:102.323 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26365:102.870 Data: 00 00 00 00 00 00 00 00 00 00 00 00 6F 02 00 00 ... +T3F74 26365:102.893 - 0.601ms returns 20 (0x14) +T3F74 26365:102.919 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26365:102.938 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26365:103.373 Data: 1F 03 00 00 +T3F74 26365:103.396 - 0.484ms returns 4 (0x4) +T3F74 26365:103.427 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26365:103.445 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26365:103.869 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26365:103.893 - 0.474ms returns 12 (0xC) +T3F74 26365:103.915 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26365:103.934 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26365:104.372 Data: 00 00 00 00 +T3F74 26365:104.396 - 0.490ms returns 4 (0x4) +T3F74 26365:104.428 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26365:104.447 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26365:104.863 Data: 00 00 00 00 +T3F74 26365:104.887 - 0.466ms returns 4 (0x4) +T3F74 26365:104.909 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26365:104.928 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26365:105.374 Data: 00 00 00 00 +T3F74 26365:105.398 - 0.496ms returns 4 (0x4) +T062C 26365:117.566 JLINK_IsHalted() +T062C 26365:118.688 - 1.141ms returns FALSE +T062C 26365:219.228 JLINK_HasError() +T062C 26365:219.309 JLINK_IsHalted() +T062C 26365:220.582 - 1.318ms returns FALSE +T062C 26365:321.477 JLINK_HasError() +T062C 26365:321.526 JLINK_IsHalted() +T062C 26365:322.608 - 1.115ms returns FALSE +T062C 26365:423.157 JLINK_HasError() +T062C 26365:423.243 JLINK_IsHalted() +T062C 26365:424.403 - 1.176ms returns FALSE +T062C 26365:524.596 JLINK_HasError() +T062C 26365:524.681 JLINK_IsHalted() +T062C 26365:525.871 - 1.205ms returns FALSE +T062C 26365:626.955 JLINK_HasError() +T062C 26365:627.112 JLINK_HasError() +T062C 26365:627.166 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26365:627.228 Data: 8D 12 74 01 +T062C 26365:627.293 Debug reg: DWT_CYCCNT +T062C 26365:627.315 - 0.157ms returns 1 (0x1) +T3F74 26365:629.888 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26365:629.925 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26365:631.199 Data: 00 00 80 00 +T3F74 26365:631.278 - 1.417ms returns 4 (0x4) +T3F74 26365:631.336 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26365:631.369 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26365:632.495 Data: 00 00 F0 01 +T3F74 26365:632.528 - 1.199ms returns 4 (0x4) +T3F74 26365:635.695 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26365:635.723 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26365:636.971 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26365:637.000 - 1.311ms returns 16 (0x10) +T3F74 26365:637.020 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26365:637.039 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26365:637.417 Data: 1E 00 00 00 +T3F74 26365:637.437 - 0.423ms returns 4 (0x4) +T3F74 26365:637.455 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26365:637.471 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26365:637.915 Data: 00 00 00 00 00 00 00 00 00 00 00 00 07 02 00 00 ... +T3F74 26365:637.935 - 0.487ms returns 20 (0x14) +T3F74 26365:637.952 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26365:637.968 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26365:638.412 Data: 1F 03 00 00 +T3F74 26365:638.432 - 0.486ms returns 4 (0x4) +T3F74 26365:638.455 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26365:638.476 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26365:638.917 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26365:638.937 - 0.489ms returns 12 (0xC) +T3F74 26365:638.954 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26365:638.971 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26365:639.418 Data: 00 00 00 00 +T3F74 26365:639.438 - 0.490ms returns 4 (0x4) +T3F74 26365:639.455 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26365:639.471 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26365:639.917 Data: 00 00 00 00 +T3F74 26365:639.937 - 0.489ms returns 4 (0x4) +T3F74 26365:639.954 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26365:639.970 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26365:640.416 Data: 00 00 00 00 +T3F74 26365:640.436 - 0.488ms returns 4 (0x4) +T062C 26365:652.571 JLINK_IsHalted() +T062C 26365:653.681 - 1.128ms returns FALSE +T062C 26365:753.864 JLINK_HasError() +T062C 26365:753.949 JLINK_IsHalted() +T062C 26365:755.041 - 1.099ms returns FALSE +T062C 26365:855.720 JLINK_HasError() +T062C 26365:855.759 JLINK_IsHalted() +T062C 26365:856.861 - 1.121ms returns FALSE +T062C 26365:957.394 JLINK_HasError() +T062C 26365:957.446 JLINK_IsHalted() +T062C 26365:958.520 - 1.091ms returns FALSE +T062C 26366:059.352 JLINK_HasError() +T062C 26366:059.396 JLINK_IsHalted() +T062C 26366:060.615 - 1.236ms returns FALSE +T062C 26366:161.190 JLINK_HasError() +T062C 26366:161.225 JLINK_HasError() +T062C 26366:161.240 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26366:161.267 Data: 8D 12 74 01 +T062C 26366:161.287 Debug reg: DWT_CYCCNT +T062C 26366:161.306 - 0.072ms returns 1 (0x1) +T3F74 26366:163.757 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26366:163.790 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26366:164.865 Data: 00 00 80 00 +T3F74 26366:164.899 - 1.150ms returns 4 (0x4) +T3F74 26366:164.938 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26366:164.961 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26366:165.514 Data: 00 00 F0 01 +T3F74 26366:165.539 - 0.608ms returns 4 (0x4) +T3F74 26366:168.899 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26366:168.926 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26366:170.112 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26366:170.139 - 1.248ms returns 16 (0x10) +T3F74 26366:170.162 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26366:170.183 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26366:170.597 Data: 1E 00 00 00 +T3F74 26366:170.617 - 0.462ms returns 4 (0x4) +T3F74 26366:170.635 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26366:170.651 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26366:171.096 Data: 00 00 00 00 00 00 00 00 00 00 00 00 19 01 00 00 ... +T3F74 26366:171.116 - 0.488ms returns 20 (0x14) +T3F74 26366:171.133 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26366:171.149 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26366:171.597 Data: 1F 03 00 00 +T3F74 26366:171.617 - 0.490ms returns 4 (0x4) +T3F74 26366:171.634 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26366:171.650 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26366:172.096 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26366:172.116 - 0.489ms returns 12 (0xC) +T3F74 26366:172.134 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26366:172.150 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26366:172.596 Data: 00 00 00 00 +T3F74 26366:172.616 - 0.489ms returns 4 (0x4) +T3F74 26366:172.633 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26366:172.649 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26366:173.095 Data: 00 00 00 00 +T3F74 26366:173.115 - 0.488ms returns 4 (0x4) +T3F74 26366:173.132 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26366:173.148 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26366:173.592 Data: 00 00 00 00 +T3F74 26366:173.622 - 0.497ms returns 4 (0x4) +T062C 26366:185.148 JLINK_IsHalted() +T062C 26366:186.234 - 1.104ms returns FALSE +T062C 26366:287.003 JLINK_HasError() +T062C 26366:287.079 JLINK_IsHalted() +T062C 26366:288.199 - 1.138ms returns FALSE +T062C 26366:389.079 JLINK_HasError() +T062C 26366:389.167 JLINK_IsHalted() +T062C 26366:390.246 - 1.091ms returns FALSE +T062C 26366:490.919 JLINK_HasError() +T062C 26366:490.959 JLINK_IsHalted() +T062C 26366:492.159 - 1.217ms returns FALSE +T062C 26366:592.343 JLINK_HasError() +T062C 26366:592.501 JLINK_IsHalted() +T062C 26366:593.739 - 1.284ms returns FALSE +T062C 26366:694.477 JLINK_HasError() +T062C 26366:694.517 JLINK_HasError() +T062C 26366:694.533 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26366:694.558 Data: 8D 12 74 01 +T062C 26366:694.627 Debug reg: DWT_CYCCNT +T062C 26366:694.646 - 0.120ms returns 1 (0x1) +T3F74 26366:697.160 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26366:697.193 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26366:698.381 Data: 00 00 80 00 +T3F74 26366:698.417 - 1.265ms returns 4 (0x4) +T3F74 26366:698.463 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26366:698.488 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26366:699.004 Data: 00 00 F0 01 +T3F74 26366:699.028 - 0.573ms returns 4 (0x4) +T3F74 26366:702.281 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26366:702.308 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26366:703.536 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26366:703.565 - 1.292ms returns 16 (0x10) +T3F74 26366:703.588 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26366:703.609 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26366:704.032 Data: 1F 00 00 00 +T3F74 26366:704.056 - 0.477ms returns 4 (0x4) +T3F74 26366:704.077 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26366:704.097 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26366:704.650 Data: 00 00 00 00 00 00 00 00 00 00 00 00 53 00 00 00 ... +T3F74 26366:704.670 - 0.599ms returns 20 (0x14) +T3F74 26366:704.687 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26366:704.703 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26366:705.151 Data: 1F 03 00 00 +T3F74 26366:705.171 - 0.490ms returns 4 (0x4) +T3F74 26366:705.188 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26366:705.204 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26366:705.651 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26366:705.671 - 0.489ms returns 12 (0xC) +T3F74 26366:705.688 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26366:705.704 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26366:706.145 Data: 00 00 00 00 +T3F74 26366:706.165 - 0.484ms returns 4 (0x4) +T3F74 26366:706.182 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26366:706.198 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26366:706.651 Data: 00 00 00 00 +T3F74 26366:706.671 - 0.495ms returns 4 (0x4) +T3F74 26366:706.688 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26366:706.704 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26366:707.145 Data: 00 00 00 00 +T3F74 26366:707.165 - 0.483ms returns 4 (0x4) +T062C 26366:726.846 JLINK_IsHalted() +T062C 26366:727.913 - 1.085ms returns FALSE +T062C 26366:828.694 JLINK_HasError() +T062C 26366:828.779 JLINK_IsHalted() +T062C 26366:830.064 - 1.303ms returns FALSE +T062C 26366:930.321 JLINK_HasError() +T062C 26366:930.407 JLINK_IsHalted() +T062C 26366:931.594 - 1.205ms returns FALSE +T062C 26367:033.516 JLINK_HasError() +T062C 26367:033.605 JLINK_IsHalted() +T062C 26367:034.842 - 1.279ms returns FALSE +T062C 26367:135.775 JLINK_HasError() +T062C 26367:135.817 JLINK_IsHalted() +T062C 26367:136.930 - 1.154ms returns FALSE +T062C 26367:237.165 JLINK_HasError() +T062C 26367:237.247 JLINK_HasError() +T062C 26367:237.292 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26367:237.359 Data: 8D 12 74 01 +T062C 26367:237.380 Debug reg: DWT_CYCCNT +T062C 26367:237.399 - 0.114ms returns 1 (0x1) +T3F74 26367:239.881 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26367:239.918 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26367:241.066 Data: 00 00 80 00 +T3F74 26367:241.148 - 1.288ms returns 4 (0x4) +T3F74 26367:241.203 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26367:241.227 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26367:242.412 Data: 00 00 F0 01 +T3F74 26367:242.490 - 1.306ms returns 4 (0x4) +T3F74 26367:245.864 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26367:245.903 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26367:247.099 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26367:247.132 - 1.276ms returns 16 (0x10) +T3F74 26367:247.156 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26367:247.179 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26367:247.579 Data: 1E 00 00 00 +T3F74 26367:247.600 - 0.450ms returns 4 (0x4) +T3F74 26367:247.617 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26367:247.634 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26367:248.078 Data: 00 00 00 00 00 00 00 00 00 00 00 00 DB 00 00 00 ... +T3F74 26367:248.098 - 0.487ms returns 20 (0x14) +T3F74 26367:248.116 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26367:248.132 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26367:248.578 Data: 1F 03 00 00 +T3F74 26367:248.598 - 0.489ms returns 4 (0x4) +T3F74 26367:248.615 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26367:248.631 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26367:249.078 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26367:249.098 - 0.490ms returns 12 (0xC) +T3F74 26367:249.115 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26367:249.131 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26367:249.587 Data: 00 00 00 00 +T3F74 26367:249.610 - 0.503ms returns 4 (0x4) +T3F74 26367:249.630 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26367:249.649 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26367:250.083 Data: 00 00 00 00 +T3F74 26367:250.107 - 0.484ms returns 4 (0x4) +T3F74 26367:250.127 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26367:250.146 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26367:250.580 Data: 00 00 00 00 +T3F74 26367:250.603 - 0.484ms returns 4 (0x4) +T062C 26367:269.337 JLINK_IsHalted() +T062C 26367:270.520 - 1.201ms returns FALSE +T062C 26367:371.345 JLINK_HasError() +T062C 26367:371.399 JLINK_IsHalted() +T062C 26367:372.503 - 1.121ms returns FALSE +T062C 26367:472.777 JLINK_HasError() +T062C 26367:472.824 JLINK_IsHalted() +T062C 26367:473.953 - 1.146ms returns FALSE +T062C 26367:574.790 JLINK_HasError() +T062C 26367:574.874 JLINK_IsHalted() +T062C 26367:576.128 - 1.296ms returns FALSE +T062C 26367:676.450 JLINK_HasError() +T062C 26367:676.553 JLINK_IsHalted() +T062C 26367:677.661 - 1.156ms returns FALSE +T062C 26367:777.919 JLINK_HasError() +T062C 26367:777.995 JLINK_HasError() +T062C 26367:778.039 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26367:778.099 Data: 8D 12 74 01 +T062C 26367:778.120 Debug reg: DWT_CYCCNT +T062C 26367:778.138 - 0.106ms returns 1 (0x1) +T3F74 26367:780.667 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26367:780.701 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26367:781.851 Data: 00 00 80 00 +T3F74 26367:781.923 - 1.263ms returns 4 (0x4) +T3F74 26367:781.968 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26367:781.993 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26367:783.330 Data: 00 00 F0 01 +T3F74 26367:783.412 - 1.464ms returns 4 (0x4) +T3F74 26367:787.191 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26367:787.222 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26367:788.437 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26367:788.465 - 1.281ms returns 16 (0x10) +T3F74 26367:788.485 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26367:788.505 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26367:788.884 Data: 1E 00 00 00 +T3F74 26367:788.915 - 0.437ms returns 4 (0x4) +T3F74 26367:788.948 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26367:788.965 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26367:789.514 Data: 00 00 00 00 00 00 00 00 00 00 00 00 03 03 00 00 ... +T3F74 26367:789.538 - 0.597ms returns 20 (0x14) +T3F74 26367:789.561 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26367:789.580 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26367:790.014 Data: 1F 03 00 00 +T3F74 26367:790.038 - 0.485ms returns 4 (0x4) +T3F74 26367:790.069 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26367:790.088 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26367:790.512 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26367:790.535 - 0.474ms returns 12 (0xC) +T3F74 26367:790.558 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26367:790.577 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26367:791.013 Data: 00 00 00 00 +T3F74 26367:791.038 - 0.488ms returns 4 (0x4) +T3F74 26367:791.069 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26367:791.088 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26367:791.506 Data: 00 00 00 00 +T3F74 26367:791.530 - 0.469ms returns 4 (0x4) +T3F74 26367:791.552 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26367:791.571 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26367:792.019 Data: 00 00 00 00 +T3F74 26367:792.043 - 0.498ms returns 4 (0x4) +T062C 26367:804.314 JLINK_IsHalted() +T062C 26367:805.487 - 1.215ms returns FALSE +T062C 26367:906.851 JLINK_HasError() +T062C 26367:906.934 JLINK_IsHalted() +T062C 26367:908.089 - 1.197ms returns FALSE +T062C 26368:008.828 JLINK_HasError() +T062C 26368:008.865 JLINK_IsHalted() +T062C 26368:010.073 - 1.226ms returns FALSE +T062C 26368:110.275 JLINK_HasError() +T062C 26368:110.428 JLINK_IsHalted() +T062C 26368:111.683 - 1.296ms returns FALSE +T062C 26368:212.592 JLINK_HasError() +T062C 26368:212.670 JLINK_IsHalted() +T062C 26368:213.742 - 1.090ms returns FALSE +T062C 26368:313.954 JLINK_HasError() +T062C 26368:314.038 JLINK_HasError() +T062C 26368:314.083 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26368:314.133 Data: 8D 12 74 01 +T062C 26368:314.153 Debug reg: DWT_CYCCNT +T062C 26368:314.172 - 0.095ms returns 1 (0x1) +T3F74 26368:316.342 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26368:316.376 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26368:317.464 Data: 00 00 80 00 +T3F74 26368:317.499 - 1.165ms returns 4 (0x4) +T3F74 26368:317.541 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26368:317.565 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26368:318.063 Data: 00 00 F0 01 +T3F74 26368:318.087 - 0.553ms returns 4 (0x4) +T3F74 26368:321.529 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26368:321.556 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26368:322.719 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26368:322.751 - 1.230ms returns 16 (0x10) +T3F74 26368:322.775 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26368:322.798 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26368:323.188 Data: 1E 00 00 00 +T3F74 26368:323.208 - 0.440ms returns 4 (0x4) +T3F74 26368:323.225 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26368:323.242 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26368:323.688 Data: 00 00 00 00 00 00 00 00 00 00 00 00 6D 02 00 00 ... +T3F74 26368:323.708 - 0.489ms returns 20 (0x14) +T3F74 26368:323.725 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26368:323.741 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26368:324.187 Data: 1F 03 00 00 +T3F74 26368:324.207 - 0.488ms returns 4 (0x4) +T3F74 26368:324.224 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26368:324.240 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26368:324.688 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26368:324.708 - 0.490ms returns 12 (0xC) +T3F74 26368:324.725 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26368:324.741 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26368:325.187 Data: 00 00 00 00 +T3F74 26368:325.207 - 0.488ms returns 4 (0x4) +T3F74 26368:325.224 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26368:325.240 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26368:325.687 Data: 00 00 00 00 +T3F74 26368:325.708 - 0.490ms returns 4 (0x4) +T3F74 26368:325.725 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26368:325.741 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26368:326.180 Data: 00 00 00 00 +T3F74 26368:326.200 - 0.481ms returns 4 (0x4) +T062C 26368:337.905 JLINK_IsHalted() +T062C 26368:338.947 - 1.060ms returns FALSE +T062C 26368:439.841 JLINK_HasError() +T062C 26368:439.923 JLINK_IsHalted() +T062C 26368:441.180 - 1.305ms returns FALSE +T062C 26368:541.990 JLINK_HasError() +T062C 26368:542.068 JLINK_IsHalted() +T062C 26368:543.180 - 1.131ms returns FALSE +T062C 26368:643.399 JLINK_HasError() +T062C 26368:643.485 JLINK_IsHalted() +T062C 26368:644.648 - 1.211ms returns FALSE +T062C 26368:745.487 JLINK_HasError() +T062C 26368:745.566 JLINK_IsHalted() +T062C 26368:746.794 - 1.273ms returns FALSE +T062C 26368:847.034 JLINK_HasError() +T062C 26368:847.113 JLINK_HasError() +T062C 26368:847.161 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26368:847.223 Data: 8D 12 74 01 +T062C 26368:847.264 Debug reg: DWT_CYCCNT +T062C 26368:847.283 - 0.129ms returns 1 (0x1) +T3F74 26368:849.922 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26368:849.959 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26368:851.283 Data: 00 00 80 00 +T3F74 26368:851.318 - 1.404ms returns 4 (0x4) +T3F74 26368:851.357 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26368:851.380 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26368:852.573 Data: 00 00 F0 01 +T3F74 26368:852.651 - 1.314ms returns 4 (0x4) +T3F74 26368:855.758 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26368:855.785 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26368:857.024 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26368:857.049 - 1.299ms returns 16 (0x10) +T3F74 26368:857.071 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26368:857.224 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26368:857.635 Data: 1E 00 00 00 +T3F74 26368:857.661 - 0.598ms returns 4 (0x4) +T3F74 26368:857.683 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26368:857.703 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26368:858.240 Data: 00 00 00 00 00 00 00 00 00 00 00 00 DB 00 00 00 ... +T3F74 26368:858.260 - 0.584ms returns 20 (0x14) +T3F74 26368:858.277 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26368:858.294 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26368:858.734 Data: 1F 03 00 00 +T3F74 26368:858.754 - 0.483ms returns 4 (0x4) +T3F74 26368:858.771 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26368:858.787 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26368:859.236 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26368:859.256 - 0.491ms returns 12 (0xC) +T3F74 26368:859.273 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26368:859.289 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26368:859.744 Data: 00 00 00 00 +T3F74 26368:859.768 - 0.503ms returns 4 (0x4) +T3F74 26368:859.788 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26368:859.807 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26368:860.245 Data: 00 00 00 00 +T3F74 26368:860.268 - 0.487ms returns 4 (0x4) +T3F74 26368:860.288 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26368:860.307 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26368:860.745 Data: 00 00 00 00 +T3F74 26368:860.768 - 0.488ms returns 4 (0x4) +T062C 26368:872.568 JLINK_IsHalted() +T062C 26368:873.625 - 1.068ms returns FALSE +T062C 26368:973.828 JLINK_HasError() +T062C 26368:973.909 JLINK_IsHalted() +T062C 26368:975.071 - 1.180ms returns FALSE +T062C 26369:075.544 JLINK_HasError() +T062C 26369:075.760 JLINK_IsHalted() +T062C 26369:076.850 - 1.107ms returns FALSE +T062C 26369:177.516 JLINK_HasError() +T062C 26369:177.595 JLINK_IsHalted() +T062C 26369:178.795 - 1.217ms returns FALSE +T062C 26369:279.064 JLINK_HasError() +T062C 26369:279.093 JLINK_IsHalted() +T062C 26369:280.199 - 1.124ms returns FALSE +T062C 26369:380.393 JLINK_HasError() +T062C 26369:380.466 JLINK_HasError() +T062C 26369:380.511 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26369:380.569 Data: 8D 12 74 01 +T062C 26369:380.589 Debug reg: DWT_CYCCNT +T062C 26369:380.608 - 0.103ms returns 1 (0x1) +T3F74 26369:383.026 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26369:383.059 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26369:384.203 Data: 00 00 80 00 +T3F74 26369:384.249 - 1.235ms returns 4 (0x4) +T3F74 26369:384.337 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26369:384.371 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26369:384.797 Data: 00 00 F0 01 +T3F74 26369:384.822 - 0.493ms returns 4 (0x4) +T3F74 26369:388.290 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26369:388.317 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26369:389.598 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26369:389.626 - 1.343ms returns 16 (0x10) +T3F74 26369:389.647 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26369:389.666 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26369:390.045 Data: 1E 00 00 00 +T3F74 26369:390.065 - 0.425ms returns 4 (0x4) +T3F74 26369:390.082 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26369:390.099 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26369:390.544 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E7 00 00 00 ... +T3F74 26369:390.564 - 0.488ms returns 20 (0x14) +T3F74 26369:390.581 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26369:390.597 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26369:391.043 Data: 1F 03 00 00 +T3F74 26369:391.063 - 0.489ms returns 4 (0x4) +T3F74 26369:391.080 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26369:391.096 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26369:391.542 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26369:391.562 - 0.488ms returns 12 (0xC) +T3F74 26369:391.579 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26369:391.595 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26369:392.043 Data: 00 00 00 00 +T3F74 26369:392.063 - 0.491ms returns 4 (0x4) +T3F74 26369:392.080 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26369:392.096 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26369:392.542 Data: 00 00 00 00 +T3F74 26369:392.562 - 0.488ms returns 4 (0x4) +T3F74 26369:392.579 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26369:392.595 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26369:393.043 Data: 00 00 00 00 +T3F74 26369:393.063 - 0.490ms returns 4 (0x4) +T062C 26369:404.766 JLINK_IsHalted() +T062C 26369:405.833 - 1.085ms returns FALSE +T062C 26369:506.036 JLINK_HasError() +T062C 26369:506.119 JLINK_IsHalted() +T062C 26369:507.411 - 1.342ms returns FALSE +T062C 26369:608.314 JLINK_HasError() +T062C 26369:608.359 JLINK_IsHalted() +T062C 26369:609.448 - 1.109ms returns FALSE +T062C 26369:710.026 JLINK_HasError() +T062C 26369:710.081 JLINK_IsHalted() +T062C 26369:711.243 - 1.181ms returns FALSE +T062C 26369:812.549 JLINK_HasError() +T062C 26369:812.631 JLINK_IsHalted() +T062C 26369:813.854 - 1.264ms returns FALSE +T062C 26369:914.723 JLINK_HasError() +T062C 26369:914.763 JLINK_HasError() +T062C 26369:914.782 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26369:914.812 Data: 8D 12 74 01 +T062C 26369:914.836 Debug reg: DWT_CYCCNT +T062C 26369:914.858 - 0.084ms returns 1 (0x1) +T3F74 26369:917.545 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26369:917.584 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26369:918.882 Data: 00 00 80 00 +T3F74 26369:918.917 - 1.379ms returns 4 (0x4) +T3F74 26369:918.957 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26369:918.980 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26369:920.180 Data: 00 00 F0 01 +T3F74 26369:920.213 - 1.265ms returns 4 (0x4) +T3F74 26369:923.280 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26369:923.307 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26369:924.528 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26369:924.557 - 1.284ms returns 16 (0x10) +T3F74 26369:924.577 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26369:924.596 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26369:924.975 Data: 1E 00 00 00 +T3F74 26369:924.995 - 0.425ms returns 4 (0x4) +T3F74 26369:925.013 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26369:925.029 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26369:925.482 Data: 00 00 00 00 00 00 00 00 00 00 00 00 A3 00 00 00 ... +T3F74 26369:925.502 - 0.496ms returns 20 (0x14) +T3F74 26369:925.520 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26369:925.536 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26369:925.975 Data: 1F 03 00 00 +T3F74 26369:925.995 - 0.482ms returns 4 (0x4) +T3F74 26369:926.012 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26369:926.028 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26369:926.468 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26369:926.488 - 0.482ms returns 12 (0xC) +T3F74 26369:926.505 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26369:926.521 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26369:926.987 Data: 00 00 00 00 +T3F74 26369:927.007 - 0.509ms returns 4 (0x4) +T3F74 26369:927.024 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26369:927.040 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26369:927.487 Data: 00 00 00 00 +T3F74 26369:927.510 - 0.494ms returns 4 (0x4) +T3F74 26369:927.530 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26369:927.549 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26369:927.973 Data: 00 00 00 00 +T3F74 26369:927.996 - 0.480ms returns 4 (0x4) +T062C 26369:941.196 JLINK_IsHalted() +T062C 26369:942.235 - 1.068ms returns FALSE +T062C 26370:042.774 JLINK_HasError() +T062C 26370:042.859 JLINK_IsHalted() +T062C 26370:043.972 - 1.130ms returns FALSE +T062C 26370:144.199 JLINK_HasError() +T062C 26370:144.277 JLINK_IsHalted() +T062C 26370:145.438 - 1.179ms returns FALSE +T062C 26370:245.646 JLINK_HasError() +T062C 26370:245.719 JLINK_IsHalted() +T062C 26370:246.928 - 1.257ms returns FALSE +T062C 26370:347.177 JLINK_HasError() +T062C 26370:347.257 JLINK_IsHalted() +T062C 26370:348.407 - 1.191ms returns FALSE +T062C 26370:448.638 JLINK_HasError() +T062C 26370:448.715 JLINK_HasError() +T062C 26370:448.760 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26370:448.824 Data: 8D 12 74 01 +T062C 26370:448.844 Debug reg: DWT_CYCCNT +T062C 26370:448.863 - 0.109ms returns 1 (0x1) +T3F74 26370:451.360 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26370:451.392 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26370:452.681 Data: 00 00 80 00 +T3F74 26370:452.754 - 1.402ms returns 4 (0x4) +T3F74 26370:452.793 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26370:452.817 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26370:454.000 Data: 00 00 F0 01 +T3F74 26370:454.081 - 1.307ms returns 4 (0x4) +T3F74 26370:457.384 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26370:457.410 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26370:458.582 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26370:458.610 - 1.234ms returns 16 (0x10) +T3F74 26370:458.631 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26370:458.650 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26370:459.022 Data: 1E 00 00 00 +T3F74 26370:459.042 - 0.418ms returns 4 (0x4) +T3F74 26370:459.060 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26370:459.076 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26370:459.529 Data: 00 00 00 00 00 00 00 00 00 00 00 00 9F 02 00 00 ... +T3F74 26370:459.549 - 0.496ms returns 20 (0x14) +T3F74 26370:459.566 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26370:459.593 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26370:460.022 Data: 1F 03 00 00 +T3F74 26370:460.042 - 0.482ms returns 4 (0x4) +T3F74 26370:460.059 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26370:460.075 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26370:460.531 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26370:460.551 - 0.498ms returns 12 (0xC) +T3F74 26370:460.568 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26370:460.584 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26370:461.022 Data: 00 00 00 00 +T3F74 26370:461.042 - 0.480ms returns 4 (0x4) +T3F74 26370:461.059 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26370:461.075 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26370:461.679 Data: 00 00 00 00 +T3F74 26370:461.708 - 0.657ms returns 4 (0x4) +T3F74 26370:461.729 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26370:461.750 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26370:462.154 Data: 00 00 00 00 +T3F74 26370:462.178 - 0.456ms returns 4 (0x4) +T062C 26370:473.972 JLINK_IsHalted() +T062C 26370:475.050 - 1.104ms returns FALSE +T062C 26370:576.246 JLINK_HasError() +T062C 26370:576.332 JLINK_IsHalted() +T062C 26370:577.616 - 1.303ms returns FALSE +T062C 26370:678.343 JLINK_HasError() +T062C 26370:678.426 JLINK_IsHalted() +T062C 26370:679.528 - 1.122ms returns FALSE +T062C 26370:780.337 JLINK_HasError() +T062C 26370:780.404 JLINK_IsHalted() +T062C 26370:781.584 - 1.221ms returns FALSE +T062C 26370:882.324 JLINK_HasError() +T062C 26370:882.380 JLINK_IsHalted() +T062C 26370:883.568 - 1.207ms returns FALSE +T062C 26370:984.379 JLINK_HasError() +T062C 26370:984.464 JLINK_HasError() +T062C 26370:984.509 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26370:984.560 Data: 8D 12 74 01 +T062C 26370:984.581 Debug reg: DWT_CYCCNT +T062C 26370:984.600 - 0.097ms returns 1 (0x1) +T3F74 26370:987.326 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26370:987.363 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26370:988.696 Data: 00 00 80 00 +T3F74 26370:988.775 - 1.469ms returns 4 (0x4) +T3F74 26370:988.840 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26370:988.863 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26370:990.053 Data: 00 00 F0 01 +T3F74 26370:990.131 - 1.311ms returns 4 (0x4) +T3F74 26370:993.166 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26370:993.193 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26370:994.343 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26370:994.370 - 1.212ms returns 16 (0x10) +T3F74 26370:994.393 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26370:994.414 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26370:994.840 Data: 1E 00 00 00 +T3F74 26370:994.864 - 0.479ms returns 4 (0x4) +T3F74 26370:994.885 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26370:994.904 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26370:995.455 Data: 00 00 00 00 00 00 00 00 00 00 00 00 9F 01 00 00 ... +T3F74 26370:995.475 - 0.597ms returns 20 (0x14) +T3F74 26370:995.492 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26370:995.508 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26370:995.951 Data: 1F 03 00 00 +T3F74 26370:995.971 - 0.485ms returns 4 (0x4) +T3F74 26370:995.988 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26370:996.004 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26370:996.450 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26370:996.470 - 0.489ms returns 12 (0xC) +T3F74 26370:996.488 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26370:996.504 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26370:996.976 Data: 00 00 00 00 +T3F74 26370:996.996 - 0.515ms returns 4 (0x4) +T3F74 26370:997.013 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26370:997.029 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26370:997.449 Data: 00 00 00 00 +T3F74 26370:997.469 - 0.462ms returns 4 (0x4) +T3F74 26370:997.492 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26370:997.513 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26370:997.955 Data: 00 00 00 00 +T3F74 26370:997.975 - 0.489ms returns 4 (0x4) +T062C 26371:010.680 JLINK_IsHalted() +T062C 26371:011.737 - 1.092ms returns FALSE +T062C 26371:112.507 JLINK_HasError() +T062C 26371:112.591 JLINK_IsHalted() +T062C 26371:113.828 - 1.254ms returns FALSE +T062C 26371:214.953 JLINK_HasError() +T062C 26371:215.057 JLINK_IsHalted() +T062C 26371:216.137 - 1.122ms returns FALSE +T062C 26371:316.664 JLINK_HasError() +T062C 26371:316.704 JLINK_IsHalted() +T062C 26371:317.818 - 1.147ms returns FALSE +T062C 26371:418.358 JLINK_HasError() +T062C 26371:418.393 JLINK_IsHalted() +T062C 26371:419.429 - 1.045ms returns FALSE +T062C 26371:519.618 JLINK_HasError() +T062C 26371:519.698 JLINK_HasError() +T062C 26371:519.743 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26371:519.818 Data: 8D 12 74 01 +T062C 26371:519.840 Debug reg: DWT_CYCCNT +T062C 26371:519.870 - 0.135ms returns 1 (0x1) +T3F74 26371:522.229 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26371:522.262 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26371:523.355 Data: 00 00 80 00 +T3F74 26371:523.420 - 1.198ms returns 4 (0x4) +T3F74 26371:523.455 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26371:523.475 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26371:523.887 Data: 00 00 F0 01 +T3F74 26371:523.911 - 0.463ms returns 4 (0x4) +T3F74 26371:527.288 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26371:527.316 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26371:528.565 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26371:528.593 - 1.312ms returns 16 (0x10) +T3F74 26371:528.613 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26371:528.633 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26371:529.009 Data: 1E 00 00 00 +T3F74 26371:529.029 - 0.422ms returns 4 (0x4) +T3F74 26371:529.047 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26371:529.063 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26371:529.510 Data: 00 00 00 00 00 00 00 00 00 00 00 00 3B 01 00 00 ... +T3F74 26371:529.530 - 0.490ms returns 20 (0x14) +T3F74 26371:529.547 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26371:529.563 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26371:530.005 Data: 1F 03 00 00 +T3F74 26371:530.025 - 0.484ms returns 4 (0x4) +T3F74 26371:530.042 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26371:530.058 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26371:530.522 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26371:530.542 - 0.507ms returns 12 (0xC) +T3F74 26371:530.559 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26371:530.575 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26371:531.004 Data: 00 00 00 00 +T3F74 26371:531.024 - 0.471ms returns 4 (0x4) +T3F74 26371:531.041 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26371:531.057 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26371:531.544 Data: 00 00 00 00 +T3F74 26371:531.567 - 0.534ms returns 4 (0x4) +T3F74 26371:531.588 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26371:531.606 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26371:532.009 Data: 00 00 00 00 +T3F74 26371:532.033 - 0.453ms returns 4 (0x4) +T062C 26371:544.488 JLINK_IsHalted() +T062C 26371:545.552 - 1.082ms returns FALSE +T062C 26371:645.761 JLINK_HasError() +T062C 26371:645.847 JLINK_IsHalted() +T062C 26371:647.034 - 1.205ms returns FALSE +T062C 26371:747.662 JLINK_HasError() +T062C 26371:747.708 JLINK_IsHalted() +T062C 26371:748.718 - 1.031ms returns FALSE +T062C 26371:848.918 JLINK_HasError() +T062C 26371:849.003 JLINK_IsHalted() +T062C 26371:850.219 - 1.259ms returns FALSE +T062C 26371:950.486 JLINK_HasError() +T062C 26371:950.570 JLINK_IsHalted() +T062C 26371:951.808 - 1.256ms returns FALSE +T062C 26372:051.951 JLINK_HasError() +T062C 26372:052.029 JLINK_HasError() +T062C 26372:052.238 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26372:052.291 Data: 8D 12 74 01 +T062C 26372:052.315 Debug reg: DWT_CYCCNT +T062C 26372:052.337 - 0.107ms returns 1 (0x1) +T3F74 26372:055.101 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26372:055.138 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26372:056.207 Data: 00 00 80 00 +T3F74 26372:056.237 - 1.143ms returns 4 (0x4) +T3F74 26372:056.272 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26372:056.291 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26372:056.690 Data: 00 00 F0 01 +T3F74 26372:056.710 - 0.445ms returns 4 (0x4) +T3F74 26372:059.704 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26372:059.733 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26372:061.042 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26372:061.157 - 1.461ms returns 16 (0x10) +T3F74 26372:061.181 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26372:061.204 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26372:062.407 Data: 1E 00 00 00 +T3F74 26372:062.475 - 1.301ms returns 4 (0x4) +T3F74 26372:062.495 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26372:062.515 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26372:063.064 Data: 00 00 00 00 00 00 00 00 00 00 00 00 7F 01 00 00 ... +T3F74 26372:063.084 - 0.595ms returns 20 (0x14) +T3F74 26372:063.101 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26372:063.118 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26372:063.563 Data: 1F 03 00 00 +T3F74 26372:063.583 - 0.488ms returns 4 (0x4) +T3F74 26372:063.600 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26372:063.616 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26372:064.059 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26372:064.079 - 0.485ms returns 12 (0xC) +T3F74 26372:064.096 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26372:064.112 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26372:064.558 Data: 00 00 00 00 +T3F74 26372:064.578 - 0.488ms returns 4 (0x4) +T3F74 26372:064.595 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26372:064.611 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26372:065.066 Data: 00 00 00 00 +T3F74 26372:065.089 - 0.502ms returns 4 (0x4) +T3F74 26372:065.109 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26372:065.128 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26372:065.574 Data: 00 00 00 00 +T3F74 26372:065.598 - 0.496ms returns 4 (0x4) +T062C 26372:078.061 JLINK_IsHalted() +T062C 26372:079.213 - 1.170ms returns FALSE +T062C 26372:179.971 JLINK_HasError() +T062C 26372:180.054 JLINK_IsHalted() +T062C 26372:181.207 - 1.171ms returns FALSE +T062C 26372:282.163 JLINK_HasError() +T062C 26372:282.240 JLINK_IsHalted() +T062C 26372:283.389 - 1.168ms returns FALSE +T062C 26372:383.556 JLINK_HasError() +T062C 26372:383.630 JLINK_IsHalted() +T062C 26372:384.892 - 1.304ms returns FALSE +T062C 26372:485.757 JLINK_HasError() +T062C 26372:485.828 JLINK_IsHalted() +T062C 26372:487.007 - 1.228ms returns FALSE +T062C 26372:587.272 JLINK_HasError() +T062C 26372:587.409 JLINK_HasError() +T062C 26372:587.461 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26372:587.523 Data: 8D 12 74 01 +T062C 26372:587.566 Debug reg: DWT_CYCCNT +T062C 26372:587.588 - 0.134ms returns 1 (0x1) +T3F74 26372:589.937 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26372:589.969 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26372:591.142 Data: 00 00 80 00 +T3F74 26372:591.193 - 1.264ms returns 4 (0x4) +T3F74 26372:591.232 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26372:591.255 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26372:592.434 Data: 00 00 F0 01 +T3F74 26372:592.496 - 1.284ms returns 4 (0x4) +T3F74 26372:595.683 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26372:595.714 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26372:596.965 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26372:596.993 - 1.405ms returns 16 (0x10) +T3F74 26372:597.108 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26372:597.128 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26372:598.253 Data: 1E 00 00 00 +T3F74 26372:598.281 - 1.180ms returns 4 (0x4) +T3F74 26372:598.302 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26372:598.321 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26372:598.898 Data: 00 00 00 00 00 00 00 00 00 00 00 00 63 02 00 00 ... +T3F74 26372:598.922 - 0.628ms returns 20 (0x14) +T3F74 26372:598.942 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26372:598.961 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26372:599.378 Data: 1F 03 00 00 +T3F74 26372:599.402 - 0.468ms returns 4 (0x4) +T3F74 26372:599.422 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26372:599.441 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26372:599.873 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26372:599.896 - 0.481ms returns 12 (0xC) +T3F74 26372:599.916 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26372:599.935 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26372:600.367 Data: 00 00 00 00 +T3F74 26372:600.387 - 0.478ms returns 4 (0x4) +T3F74 26372:600.404 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26372:600.420 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26372:600.866 Data: 00 00 00 00 +T3F74 26372:600.886 - 0.488ms returns 4 (0x4) +T3F74 26372:600.903 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26372:600.919 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26372:601.366 Data: 00 00 00 00 +T3F74 26372:601.386 - 0.490ms returns 4 (0x4) +T062C 26372:613.312 JLINK_IsHalted() +T062C 26372:614.375 - 1.082ms returns FALSE +T062C 26372:715.181 JLINK_HasError() +T062C 26372:715.224 JLINK_IsHalted() +T062C 26372:716.338 - 1.155ms returns FALSE +T062C 26372:817.279 JLINK_HasError() +T062C 26372:817.327 JLINK_IsHalted() +T062C 26372:818.398 - 1.094ms returns FALSE +T062C 26372:918.654 JLINK_HasError() +T062C 26372:918.741 JLINK_IsHalted() +T062C 26372:919.966 - 1.242ms returns FALSE +T062C 26373:020.718 JLINK_HasError() +T062C 26373:020.803 JLINK_IsHalted() +T062C 26373:021.836 - 1.052ms returns FALSE +T062C 26373:122.802 JLINK_HasError() +T062C 26373:122.875 JLINK_HasError() +T062C 26373:122.919 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26373:122.980 Data: 8D 12 74 01 +T062C 26373:123.037 Debug reg: DWT_CYCCNT +T062C 26373:123.090 - 0.178ms returns 1 (0x1) +T3F74 26373:125.556 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26373:125.588 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26373:126.835 Data: 00 00 80 00 +T3F74 26373:126.915 - 1.381ms returns 4 (0x4) +T3F74 26373:126.968 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26373:126.991 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26373:128.134 Data: 00 00 F0 01 +T3F74 26373:128.212 - 1.263ms returns 4 (0x4) +T3F74 26373:131.251 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26373:131.279 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26373:132.438 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26373:132.466 - 1.222ms returns 16 (0x10) +T3F74 26373:132.488 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26373:132.510 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26373:132.921 Data: 1E 00 00 00 +T3F74 26373:132.941 - 0.460ms returns 4 (0x4) +T3F74 26373:132.959 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26373:132.975 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26373:133.421 Data: 00 00 00 00 00 00 00 00 00 00 00 00 CD 02 00 00 ... +T3F74 26373:133.441 - 0.489ms returns 20 (0x14) +T3F74 26373:133.458 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26373:133.475 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26373:133.921 Data: 1F 03 00 00 +T3F74 26373:133.941 - 0.489ms returns 4 (0x4) +T3F74 26373:133.958 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26373:133.974 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26373:134.421 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26373:134.441 - 0.490ms returns 12 (0xC) +T3F74 26373:134.458 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26373:134.475 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26373:134.920 Data: 00 00 00 00 +T3F74 26373:134.940 - 0.488ms returns 4 (0x4) +T3F74 26373:134.958 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26373:134.974 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26373:135.421 Data: 00 00 00 00 +T3F74 26373:135.441 - 0.489ms returns 4 (0x4) +T3F74 26373:135.458 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26373:135.474 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26373:135.920 Data: 00 00 00 00 +T3F74 26373:135.940 - 0.489ms returns 4 (0x4) +T062C 26373:148.354 JLINK_IsHalted() +T062C 26373:149.451 - 1.114ms returns FALSE +T062C 26373:249.645 JLINK_HasError() +T062C 26373:249.726 JLINK_IsHalted() +T062C 26373:250.902 - 1.218ms returns FALSE +T062C 26373:351.152 JLINK_HasError() +T062C 26373:351.228 JLINK_IsHalted() +T062C 26373:352.490 - 1.280ms returns FALSE +T062C 26373:453.677 JLINK_HasError() +T062C 26373:453.750 JLINK_IsHalted() +T062C 26373:454.884 - 1.142ms returns FALSE +T062C 26373:555.035 JLINK_HasError() +T062C 26373:555.122 JLINK_IsHalted() +T062C 26373:556.337 - 1.234ms returns FALSE +T062C 26373:657.802 JLINK_HasError() +T062C 26373:657.834 JLINK_HasError() +T062C 26373:657.850 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26373:657.876 Data: 8D 12 74 01 +T062C 26373:657.896 Debug reg: DWT_CYCCNT +T062C 26373:657.915 - 0.071ms returns 1 (0x1) +T3F74 26373:660.576 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26373:660.611 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26373:661.732 Data: 00 00 80 00 +T3F74 26373:661.753 - 1.183ms returns 4 (0x4) +T3F74 26373:661.781 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26373:661.797 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26373:662.229 Data: 00 00 F0 01 +T3F74 26373:662.253 - 0.481ms returns 4 (0x4) +T3F74 26373:665.441 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26373:665.467 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26373:666.770 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26373:666.803 - 1.370ms returns 16 (0x10) +T3F74 26373:666.826 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26373:666.849 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26373:667.357 Data: 1F 00 00 00 +T3F74 26373:667.381 - 0.562ms returns 4 (0x4) +T3F74 26373:667.401 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26373:667.421 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26373:667.981 Data: 00 00 00 00 00 00 00 00 00 00 00 00 79 02 00 00 ... +T3F74 26373:668.008 - 0.613ms returns 20 (0x14) +T3F74 26373:668.025 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26373:668.041 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26373:668.475 Data: 1F 03 00 00 +T3F74 26373:668.495 - 0.477ms returns 4 (0x4) +T3F74 26373:668.512 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26373:668.528 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26373:668.974 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26373:668.994 - 0.488ms returns 12 (0xC) +T3F74 26373:669.011 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26373:669.027 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26373:669.470 Data: 00 00 00 00 +T3F74 26373:669.490 - 0.486ms returns 4 (0x4) +T3F74 26373:669.508 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26373:669.523 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26373:669.970 Data: 00 00 00 00 +T3F74 26373:669.990 - 0.489ms returns 4 (0x4) +T3F74 26373:670.007 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26373:670.023 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26373:670.481 Data: 00 00 00 00 +T3F74 26373:670.504 - 0.505ms returns 4 (0x4) +T062C 26373:689.716 JLINK_IsHalted() +T062C 26373:690.749 - 1.052ms returns FALSE +T062C 26373:790.938 JLINK_HasError() +T062C 26373:791.046 JLINK_IsHalted() +T062C 26373:792.320 - 1.292ms returns FALSE +T062C 26373:892.503 JLINK_HasError() +T062C 26373:892.572 JLINK_IsHalted() +T062C 26373:893.720 - 1.179ms returns FALSE +T062C 26373:993.933 JLINK_HasError() +T062C 26373:994.015 JLINK_IsHalted() +T062C 26373:995.267 - 1.269ms returns FALSE +T062C 26374:095.488 JLINK_HasError() +T062C 26374:095.524 JLINK_IsHalted() +T062C 26374:096.625 - 1.119ms returns FALSE +T062C 26374:196.776 JLINK_HasError() +T062C 26374:196.860 JLINK_HasError() +T062C 26374:196.906 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26374:196.976 Data: 8D 12 74 01 +T062C 26374:197.035 Debug reg: DWT_CYCCNT +T062C 26374:197.087 - 0.189ms returns 1 (0x1) +T3F74 26374:199.463 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26374:199.496 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26374:200.705 Data: 00 00 80 00 +T3F74 26374:200.739 - 1.283ms returns 4 (0x4) +T3F74 26374:200.777 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26374:200.800 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26374:201.982 Data: 00 00 F0 01 +T3F74 26374:202.042 - 1.285ms returns 4 (0x4) +T3F74 26374:205.182 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26374:205.209 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26374:206.460 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26374:206.488 - 1.313ms returns 16 (0x10) +T3F74 26374:206.510 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26374:206.531 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26374:206.921 Data: 1E 00 00 00 +T3F74 26374:206.945 - 0.443ms returns 4 (0x4) +T3F74 26374:206.966 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26374:206.985 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26374:207.534 Data: 00 00 00 00 00 00 00 00 00 00 00 00 41 00 00 00 ... +T3F74 26374:207.557 - 0.604ms returns 20 (0x14) +T3F74 26374:207.581 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26374:207.597 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26374:208.028 Data: 1F 03 00 00 +T3F74 26374:208.048 - 0.473ms returns 4 (0x4) +T3F74 26374:208.065 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26374:208.081 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26374:208.528 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26374:208.548 - 0.489ms returns 12 (0xC) +T3F74 26374:208.565 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26374:208.581 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26374:209.053 Data: 00 00 00 00 +T3F74 26374:209.073 - 0.515ms returns 4 (0x4) +T3F74 26374:209.090 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26374:209.106 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26374:209.527 Data: 00 00 00 00 +T3F74 26374:209.547 - 0.463ms returns 4 (0x4) +T3F74 26374:209.563 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26374:209.579 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26374:210.023 Data: 00 00 00 00 +T3F74 26374:210.043 - 0.486ms returns 4 (0x4) +T062C 26374:229.436 JLINK_IsHalted() +T062C 26374:230.606 - 1.188ms returns FALSE +T062C 26374:331.673 JLINK_HasError() +T062C 26374:331.714 JLINK_IsHalted() +T062C 26374:332.775 - 1.068ms returns FALSE +T062C 26374:432.917 JLINK_HasError() +T062C 26374:432.991 JLINK_IsHalted() +T062C 26374:434.198 - 1.248ms returns FALSE +T062C 26374:534.431 JLINK_HasError() +T062C 26374:534.470 JLINK_IsHalted() +T062C 26374:535.682 - 1.252ms returns FALSE +T062C 26374:636.767 JLINK_HasError() +T062C 26374:636.852 JLINK_IsHalted() +T062C 26374:638.131 - 1.320ms returns FALSE +T062C 26374:738.878 JLINK_HasError() +T062C 26374:738.956 JLINK_HasError() +T062C 26374:738.974 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26374:739.003 Data: 8D 12 74 01 +T062C 26374:739.027 Debug reg: DWT_CYCCNT +T062C 26374:739.049 - 0.082ms returns 1 (0x1) +T3F74 26374:741.397 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26374:741.430 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26374:742.619 Data: 00 00 80 00 +T3F74 26374:742.682 - 1.293ms returns 4 (0x4) +T3F74 26374:742.722 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26374:742.745 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26374:743.827 Data: 00 00 F0 01 +T3F74 26374:743.848 - 1.133ms returns 4 (0x4) +T3F74 26374:746.996 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26374:747.028 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26374:748.210 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26374:748.232 - 1.242ms returns 16 (0x10) +T3F74 26374:748.250 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26374:748.266 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26374:748.724 Data: 1E 00 00 00 +T3F74 26374:748.751 - 0.509ms returns 4 (0x4) +T3F74 26374:748.772 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26374:748.793 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26374:749.346 Data: 00 00 00 00 00 00 00 00 00 00 00 00 53 00 00 00 ... +T3F74 26374:749.372 - 0.607ms returns 20 (0x14) +T3F74 26374:749.393 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26374:749.413 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26374:749.845 Data: 1F 03 00 00 +T3F74 26374:749.865 - 0.478ms returns 4 (0x4) +T3F74 26374:749.882 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26374:749.898 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26374:750.332 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26374:750.352 - 0.476ms returns 12 (0xC) +T3F74 26374:750.369 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26374:750.385 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26374:750.830 Data: 00 00 00 00 +T3F74 26374:750.850 - 0.487ms returns 4 (0x4) +T3F74 26374:750.867 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26374:750.883 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26374:751.331 Data: 00 00 00 00 +T3F74 26374:751.351 - 0.491ms returns 4 (0x4) +T3F74 26374:751.368 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26374:751.384 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26374:751.830 Data: 00 00 00 00 +T3F74 26374:751.850 - 0.488ms returns 4 (0x4) +T062C 26374:763.058 JLINK_IsHalted() +T062C 26374:764.113 - 1.098ms returns FALSE +T062C 26374:864.347 JLINK_HasError() +T062C 26374:864.429 JLINK_IsHalted() +T062C 26374:865.693 - 1.311ms returns FALSE +T062C 26374:965.912 JLINK_HasError() +T062C 26374:965.962 JLINK_IsHalted() +T062C 26374:967.079 - 1.139ms returns FALSE +T062C 26375:067.799 JLINK_HasError() +T062C 26375:067.844 JLINK_IsHalted() +T062C 26375:069.035 - 1.209ms returns FALSE +T062C 26375:169.292 JLINK_HasError() +T062C 26375:169.368 JLINK_IsHalted() +T062C 26375:170.493 - 1.153ms returns FALSE +T062C 26375:270.718 JLINK_HasError() +T062C 26375:270.799 JLINK_HasError() +T062C 26375:270.843 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26375:270.896 Data: 8D 12 74 01 +T062C 26375:270.917 Debug reg: DWT_CYCCNT +T062C 26375:270.936 - 0.099ms returns 1 (0x1) +T3F74 26375:273.513 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26375:273.550 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26375:274.763 Data: 00 00 80 00 +T3F74 26375:274.926 - 1.441ms returns 4 (0x4) +T3F74 26375:275.036 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26375:275.091 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26375:276.151 Data: 00 00 F0 01 +T3F74 26375:276.175 - 1.146ms returns 4 (0x4) +T3F74 26375:279.450 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26375:279.477 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26375:280.692 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26375:280.720 - 1.277ms returns 16 (0x10) +T3F74 26375:280.741 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26375:280.760 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26375:281.136 Data: 1E 00 00 00 +T3F74 26375:281.156 - 0.422ms returns 4 (0x4) +T3F74 26375:281.173 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26375:281.190 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26375:281.823 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1B 00 00 00 ... +T3F74 26375:281.847 - 0.681ms returns 20 (0x14) +T3F74 26375:281.867 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26375:281.886 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26375:282.268 Data: 1F 03 00 00 +T3F74 26375:282.292 - 0.433ms returns 4 (0x4) +T3F74 26375:282.313 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26375:282.331 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26375:282.761 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26375:282.781 - 0.475ms returns 12 (0xC) +T3F74 26375:282.798 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26375:282.814 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26375:283.260 Data: 00 00 00 00 +T3F74 26375:283.280 - 0.488ms returns 4 (0x4) +T3F74 26375:283.297 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26375:283.313 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26375:283.761 Data: 00 00 00 00 +T3F74 26375:283.780 - 0.490ms returns 4 (0x4) +T3F74 26375:283.797 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26375:283.813 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26375:284.259 Data: 00 00 00 00 +T3F74 26375:284.278 - 0.488ms returns 4 (0x4) +T062C 26375:296.465 JLINK_IsHalted() +T062C 26375:297.524 - 1.076ms returns FALSE +T062C 26375:398.235 JLINK_HasError() +T062C 26375:398.276 JLINK_IsHalted() +T062C 26375:399.555 - 1.296ms returns FALSE +T062C 26375:499.756 JLINK_HasError() +T062C 26375:499.836 JLINK_IsHalted() +T062C 26375:501.130 - 1.335ms returns FALSE +T062C 26375:601.612 JLINK_HasError() +T062C 26375:601.684 JLINK_IsHalted() +T062C 26375:602.741 - 1.066ms returns FALSE +T062C 26375:703.527 JLINK_HasError() +T062C 26375:703.613 JLINK_IsHalted() +T062C 26375:704.757 - 1.161ms returns FALSE +T062C 26375:805.384 JLINK_HasError() +T062C 26375:805.503 JLINK_HasError() +T062C 26375:805.526 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26375:805.559 Data: 8D 12 74 01 +T062C 26375:805.591 Debug reg: DWT_CYCCNT +T062C 26375:805.620 - 0.101ms returns 1 (0x1) +T3F74 26375:808.173 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26375:808.215 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26375:809.462 Data: 00 00 80 00 +T3F74 26375:809.496 - 1.332ms returns 4 (0x4) +T3F74 26375:809.537 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26375:809.560 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26375:810.782 Data: 00 00 F0 01 +T3F74 26375:810.849 - 1.318ms returns 4 (0x4) +T3F74 26375:813.850 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26375:813.886 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26375:815.123 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26375:815.155 - 1.313ms returns 16 (0x10) +T3F74 26375:815.192 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26375:815.215 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26375:815.704 Data: 1F 00 00 00 +T3F74 26375:815.728 - 0.543ms returns 4 (0x4) +T3F74 26375:815.759 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26375:815.779 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26375:816.338 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D7 00 00 00 ... +T3F74 26375:816.362 - 0.610ms returns 20 (0x14) +T3F74 26375:816.394 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26375:816.413 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26375:816.815 Data: 1F 03 00 00 +T3F74 26375:816.838 - 0.452ms returns 4 (0x4) +T3F74 26375:816.861 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26375:816.880 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26375:817.326 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26375:817.350 - 0.496ms returns 12 (0xC) +T3F74 26375:817.372 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26375:817.392 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26375:817.825 Data: 00 00 00 00 +T3F74 26375:817.850 - 0.486ms returns 4 (0x4) +T3F74 26375:817.881 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26375:817.912 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26375:818.321 Data: 00 00 00 00 +T3F74 26375:818.344 - 0.471ms returns 4 (0x4) +T3F74 26375:818.367 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26375:818.386 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26375:818.824 Data: 00 00 00 00 +T3F74 26375:818.847 - 0.488ms returns 4 (0x4) +T062C 26375:839.106 JLINK_IsHalted() +T062C 26375:840.217 - 1.128ms returns FALSE +T062C 26375:940.436 JLINK_HasError() +T062C 26375:940.520 JLINK_IsHalted() +T062C 26375:941.771 - 1.292ms returns FALSE +T062C 26376:042.717 JLINK_HasError() +T062C 26376:042.767 JLINK_IsHalted() +T062C 26376:043.821 - 1.076ms returns FALSE +T062C 26376:144.504 JLINK_HasError() +T062C 26376:144.546 JLINK_IsHalted() +T062C 26376:145.790 - 1.285ms returns FALSE +T062C 26376:246.048 JLINK_HasError() +T062C 26376:246.121 JLINK_IsHalted() +T062C 26376:247.383 - 1.310ms returns FALSE +T062C 26376:348.634 JLINK_HasError() +T062C 26376:348.723 JLINK_HasError() +T062C 26376:348.768 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26376:348.829 Data: 8D 12 74 01 +T062C 26376:348.886 Debug reg: DWT_CYCCNT +T062C 26376:348.936 - 0.176ms returns 1 (0x1) +T3F74 26376:351.605 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26376:351.643 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26376:352.929 Data: 00 00 80 00 +T3F74 26376:353.015 - 1.417ms returns 4 (0x4) +T3F74 26376:353.054 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26376:353.077 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26376:354.214 Data: 00 00 F0 01 +T3F74 26376:354.292 - 1.267ms returns 4 (0x4) +T3F74 26376:357.597 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26376:357.628 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26376:358.879 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26376:358.913 - 1.324ms returns 16 (0x10) +T3F74 26376:358.937 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26376:358.959 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26376:359.493 Data: 1E 00 00 00 +T3F74 26376:359.517 - 0.588ms returns 4 (0x4) +T3F74 26376:359.538 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26376:359.557 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26376:360.121 Data: 00 00 00 00 00 00 00 00 00 00 00 00 13 03 00 00 ... +T3F74 26376:360.144 - 0.614ms returns 20 (0x14) +T3F74 26376:360.165 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26376:360.184 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26376:360.625 Data: 1F 03 00 00 +T3F74 26376:360.649 - 0.492ms returns 4 (0x4) +T3F74 26376:360.669 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26376:360.688 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26376:361.117 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26376:361.136 - 0.474ms returns 12 (0xC) +T3F74 26376:361.153 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26376:361.169 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26376:361.619 Data: 00 00 00 00 +T3F74 26376:361.639 - 0.492ms returns 4 (0x4) +T3F74 26376:361.656 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26376:361.672 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26376:362.117 Data: 00 00 00 00 +T3F74 26376:362.137 - 0.487ms returns 4 (0x4) +T3F74 26376:362.154 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26376:362.170 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26376:362.618 Data: 00 00 00 00 +T3F74 26376:362.638 - 0.491ms returns 4 (0x4) +T062C 26376:382.179 JLINK_IsHalted() +T062C 26376:383.261 - 1.110ms returns FALSE +T062C 26376:483.789 JLINK_HasError() +T062C 26376:483.831 JLINK_IsHalted() +T062C 26376:484.888 - 1.092ms returns FALSE +T062C 26376:585.737 JLINK_HasError() +T062C 26376:585.812 JLINK_IsHalted() +T062C 26376:586.999 - 1.204ms returns FALSE +T062C 26376:687.680 JLINK_HasError() +T062C 26376:687.710 JLINK_IsHalted() +T062C 26376:688.930 - 1.238ms returns FALSE +T062C 26376:789.337 JLINK_HasError() +T062C 26376:789.434 JLINK_IsHalted() +T062C 26376:790.761 - 1.369ms returns FALSE +T062C 26376:891.224 JLINK_HasError() +T062C 26376:891.311 JLINK_HasError() +T062C 26376:891.339 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26376:891.368 Data: 8D 12 74 01 +T062C 26376:891.393 Debug reg: DWT_CYCCNT +T062C 26376:891.418 - 0.086ms returns 1 (0x1) +T3F74 26376:893.710 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26376:893.748 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26376:894.943 Data: 00 00 80 00 +T3F74 26376:895.025 - 1.321ms returns 4 (0x4) +T3F74 26376:895.059 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26376:895.079 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26376:896.187 Data: 00 00 F0 01 +T3F74 26376:896.219 - 1.168ms returns 4 (0x4) +T3F74 26376:899.772 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26376:899.814 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26376:901.081 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26376:901.113 - 1.349ms returns 16 (0x10) +T3F74 26376:901.145 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26376:901.165 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26376:901.545 Data: 1E 00 00 00 +T3F74 26376:901.566 - 0.427ms returns 4 (0x4) +T3F74 26376:901.583 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26376:901.600 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26376:902.045 Data: 00 00 00 00 00 00 00 00 00 00 00 00 19 02 00 00 ... +T3F74 26376:902.065 - 0.488ms returns 20 (0x14) +T3F74 26376:902.082 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26376:902.099 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26376:902.541 Data: 1F 03 00 00 +T3F74 26376:902.561 - 0.485ms returns 4 (0x4) +T3F74 26376:902.578 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26376:902.594 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26376:903.040 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26376:903.060 - 0.488ms returns 12 (0xC) +T3F74 26376:903.077 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26376:903.093 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26376:903.570 Data: 00 00 00 00 +T3F74 26376:903.594 - 0.525ms returns 4 (0x4) +T3F74 26376:903.614 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26376:903.632 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26376:904.050 Data: 00 00 00 00 +T3F74 26376:904.073 - 0.467ms returns 4 (0x4) +T3F74 26376:904.093 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26376:904.112 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26376:904.550 Data: 00 00 00 00 +T3F74 26376:904.574 - 0.488ms returns 4 (0x4) +T062C 26376:916.302 JLINK_IsHalted() +T062C 26376:917.457 - 1.174ms returns FALSE +T062C 26377:017.920 JLINK_HasError() +T062C 26377:017.975 JLINK_IsHalted() +T062C 26377:019.165 - 1.208ms returns FALSE +T062C 26377:120.103 JLINK_HasError() +T062C 26377:120.151 JLINK_IsHalted() +T062C 26377:121.355 - 1.227ms returns FALSE +T062C 26377:222.053 JLINK_HasError() +T062C 26377:222.094 JLINK_IsHalted() +T062C 26377:223.225 - 1.149ms returns FALSE +T062C 26377:323.419 JLINK_HasError() +T062C 26377:323.492 JLINK_IsHalted() +T062C 26377:324.709 - 1.235ms returns FALSE +T062C 26377:424.898 JLINK_HasError() +T062C 26377:424.972 JLINK_HasError() +T062C 26377:425.017 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26377:425.079 Data: 8D 12 74 01 +T062C 26377:425.099 Debug reg: DWT_CYCCNT +T062C 26377:425.118 - 0.107ms returns 1 (0x1) +T3F74 26377:427.792 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26377:427.832 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26377:428.957 Data: 00 00 80 00 +T3F74 26377:428.990 - 1.206ms returns 4 (0x4) +T3F74 26377:429.029 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26377:429.052 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26377:429.479 Data: 00 00 F0 01 +T3F74 26377:429.499 - 0.476ms returns 4 (0x4) +T3F74 26377:432.484 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26377:432.520 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26377:433.754 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26377:433.786 - 1.311ms returns 16 (0x10) +T3F74 26377:433.810 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26377:433.833 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26377:434.233 Data: 1E 00 00 00 +T3F74 26377:434.257 - 0.454ms returns 4 (0x4) +T3F74 26377:434.277 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26377:434.296 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26377:434.850 Data: 00 00 00 00 00 00 00 00 00 00 00 00 C7 02 00 00 ... +T3F74 26377:434.870 - 0.599ms returns 20 (0x14) +T3F74 26377:434.887 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26377:434.903 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26377:435.349 Data: 1F 03 00 00 +T3F74 26377:435.370 - 0.489ms returns 4 (0x4) +T3F74 26377:435.387 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26377:435.403 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26377:435.848 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26377:435.868 - 0.488ms returns 12 (0xC) +T3F74 26377:435.885 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26377:435.901 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26377:436.350 Data: 00 00 00 00 +T3F74 26377:436.370 - 0.491ms returns 4 (0x4) +T3F74 26377:436.387 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26377:436.403 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26377:436.848 Data: 00 00 00 00 +T3F74 26377:436.868 - 0.487ms returns 4 (0x4) +T3F74 26377:436.885 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26377:436.901 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26377:437.349 Data: 00 00 00 00 +T3F74 26377:437.369 - 0.490ms returns 4 (0x4) +T062C 26377:449.786 JLINK_IsHalted() +T062C 26377:450.856 - 1.088ms returns FALSE +T062C 26377:551.702 JLINK_HasError() +T062C 26377:551.751 JLINK_IsHalted() +T062C 26377:552.920 - 1.206ms returns FALSE +T062C 26377:653.595 JLINK_HasError() +T062C 26377:653.673 JLINK_IsHalted() +T062C 26377:654.868 - 1.208ms returns FALSE +T062C 26377:755.377 JLINK_HasError() +T062C 26377:755.453 JLINK_IsHalted() +T062C 26377:756.676 - 1.265ms returns FALSE +T062C 26377:857.515 JLINK_HasError() +T062C 26377:857.602 JLINK_IsHalted() +T062C 26377:858.751 - 1.167ms returns FALSE +T062C 26377:958.959 JLINK_HasError() +T062C 26377:959.051 JLINK_HasError() +T062C 26377:959.095 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26377:959.163 Data: 8D 12 74 01 +T062C 26377:959.221 Debug reg: DWT_CYCCNT +T062C 26377:959.266 - 0.178ms returns 1 (0x1) +T3F74 26377:961.843 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26377:961.892 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26377:962.995 Data: 00 00 80 00 +T3F74 26377:963.075 - 1.252ms returns 4 (0x4) +T3F74 26377:963.164 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26377:963.227 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26377:964.294 Data: 00 00 F0 01 +T3F74 26377:964.327 - 1.171ms returns 4 (0x4) +T3F74 26377:967.419 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26377:967.446 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26377:968.709 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26377:968.737 - 1.325ms returns 16 (0x10) +T3F74 26377:968.758 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26377:968.777 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26377:969.153 Data: 1E 00 00 00 +T3F74 26377:969.173 - 0.422ms returns 4 (0x4) +T3F74 26377:969.191 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26377:969.207 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26377:969.656 Data: 00 00 00 00 00 00 00 00 00 00 00 00 23 01 00 00 ... +T3F74 26377:969.676 - 0.492ms returns 20 (0x14) +T3F74 26377:969.693 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26377:969.709 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26377:970.148 Data: 1F 03 00 00 +T3F74 26377:970.179 - 0.493ms returns 4 (0x4) +T3F74 26377:970.197 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26377:970.213 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26377:970.649 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26377:970.668 - 0.478ms returns 12 (0xC) +T3F74 26377:970.686 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26377:970.702 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26377:971.148 Data: 00 00 00 00 +T3F74 26377:971.168 - 0.489ms returns 4 (0x4) +T3F74 26377:971.185 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26377:971.201 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26377:971.654 Data: 00 00 00 00 +T3F74 26377:971.677 - 0.500ms returns 4 (0x4) +T3F74 26377:971.697 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26377:971.716 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26377:972.153 Data: 00 00 00 00 +T3F74 26377:972.177 - 0.487ms returns 4 (0x4) +T062C 26377:984.111 JLINK_IsHalted() +T062C 26377:985.164 - 1.071ms returns FALSE +T062C 26378:085.884 JLINK_HasError() +T062C 26378:086.003 JLINK_IsHalted() +T062C 26378:087.024 - 1.038ms returns FALSE +T062C 26378:188.016 JLINK_HasError() +T062C 26378:188.060 JLINK_IsHalted() +T062C 26378:189.218 - 1.182ms returns FALSE +T062C 26378:289.358 JLINK_HasError() +T062C 26378:289.444 JLINK_IsHalted() +T062C 26378:290.602 - 1.176ms returns FALSE +T062C 26378:390.803 JLINK_HasError() +T062C 26378:390.889 JLINK_IsHalted() +T062C 26378:392.070 - 1.200ms returns FALSE +T062C 26378:492.603 JLINK_HasError() +T062C 26378:492.682 JLINK_HasError() +T062C 26378:492.726 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26378:492.787 Data: 8D 12 74 01 +T062C 26378:492.856 Debug reg: DWT_CYCCNT +T062C 26378:492.911 - 0.203ms returns 1 (0x1) +T3F74 26378:495.384 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26378:495.417 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26378:496.614 Data: 00 00 80 00 +T3F74 26378:496.694 - 1.337ms returns 4 (0x4) +T3F74 26378:496.752 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26378:496.775 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26378:497.919 Data: 00 00 F0 01 +T3F74 26378:497.996 - 1.264ms returns 4 (0x4) +T3F74 26378:501.427 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26378:501.458 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26378:502.633 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26378:502.662 - 1.241ms returns 16 (0x10) +T3F74 26378:502.682 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26378:502.702 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26378:503.079 Data: 1E 00 00 00 +T3F74 26378:503.099 - 0.424ms returns 4 (0x4) +T3F74 26378:503.117 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26378:503.133 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26378:503.587 Data: 00 00 00 00 00 00 00 00 00 00 00 00 59 00 00 00 ... +T3F74 26378:503.607 - 0.497ms returns 20 (0x14) +T3F74 26378:503.624 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26378:503.640 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26378:504.077 Data: 1F 03 00 00 +T3F74 26378:504.097 - 0.479ms returns 4 (0x4) +T3F74 26378:504.114 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26378:504.130 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26378:504.579 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26378:504.599 - 0.492ms returns 12 (0xC) +T3F74 26378:504.616 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26378:504.632 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26378:505.077 Data: 00 00 00 00 +T3F74 26378:505.097 - 0.487ms returns 4 (0x4) +T3F74 26378:505.114 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26378:505.130 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26378:505.583 Data: 00 00 00 00 +T3F74 26378:505.607 - 0.501ms returns 4 (0x4) +T3F74 26378:505.627 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26378:505.646 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26378:506.083 Data: 00 00 00 00 +T3F74 26378:506.107 - 0.487ms returns 4 (0x4) +T062C 26378:518.263 JLINK_IsHalted() +T062C 26378:519.349 - 1.104ms returns FALSE +T062C 26378:620.062 JLINK_HasError() +T062C 26378:620.144 JLINK_IsHalted() +T062C 26378:621.411 - 1.308ms returns FALSE +T062C 26378:722.035 JLINK_HasError() +T062C 26378:722.117 JLINK_IsHalted() +T062C 26378:723.323 - 1.223ms returns FALSE +T062C 26378:824.248 JLINK_HasError() +T062C 26378:824.331 JLINK_IsHalted() +T062C 26378:825.509 - 1.220ms returns FALSE +T062C 26378:925.995 JLINK_HasError() +T062C 26378:926.033 JLINK_IsHalted() +T062C 26378:927.041 - 1.017ms returns FALSE +T062C 26379:027.115 JLINK_HasError() +T062C 26379:027.249 JLINK_HasError() +T062C 26379:027.271 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26379:027.299 Data: 8D 12 74 01 +T062C 26379:027.323 Debug reg: DWT_CYCCNT +T062C 26379:027.345 - 0.082ms returns 1 (0x1) +T3F74 26379:029.706 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26379:029.739 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26379:030.919 Data: 00 00 80 00 +T3F74 26379:030.999 - 1.319ms returns 4 (0x4) +T3F74 26379:031.058 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26379:031.082 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26379:032.143 Data: 00 00 F0 01 +T3F74 26379:032.182 - 1.132ms returns 4 (0x4) +T3F74 26379:035.627 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26379:035.669 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26379:036.986 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26379:037.049 - 1.441ms returns 16 (0x10) +T3F74 26379:037.104 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26379:037.122 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26379:037.516 Data: 1E 00 00 00 +T3F74 26379:037.540 - 0.444ms returns 4 (0x4) +T3F74 26379:037.561 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26379:037.580 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26379:038.143 Data: 00 00 00 00 00 00 00 00 00 00 00 00 59 00 00 00 ... +T3F74 26379:038.166 - 0.613ms returns 20 (0x14) +T3F74 26379:038.186 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26379:038.205 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26379:038.635 Data: 1F 03 00 00 +T3F74 26379:038.656 - 0.476ms returns 4 (0x4) +T3F74 26379:038.673 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26379:038.689 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26379:039.137 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26379:039.156 - 0.490ms returns 12 (0xC) +T3F74 26379:039.173 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26379:039.189 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26379:039.635 Data: 00 00 00 00 +T3F74 26379:039.655 - 0.488ms returns 4 (0x4) +T3F74 26379:039.672 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26379:039.688 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26379:040.136 Data: 00 00 00 00 +T3F74 26379:040.156 - 0.490ms returns 4 (0x4) +T3F74 26379:040.173 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26379:040.189 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26379:040.635 Data: 00 00 00 00 +T3F74 26379:040.655 - 0.489ms returns 4 (0x4) +T062C 26379:045.529 JLINK_IsHalted() +T062C 26379:046.752 - 1.242ms returns FALSE +T062C 26379:146.903 JLINK_HasError() +T062C 26379:146.978 JLINK_IsHalted() +T062C 26379:148.135 - 1.175ms returns FALSE +T062C 26379:249.002 JLINK_HasError() +T062C 26379:249.056 JLINK_IsHalted() +T062C 26379:250.126 - 1.089ms returns FALSE +T062C 26379:350.459 JLINK_HasError() +T062C 26379:350.515 JLINK_IsHalted() +T062C 26379:351.746 - 1.249ms returns FALSE +T062C 26379:452.568 JLINK_HasError() +T062C 26379:452.641 JLINK_IsHalted() +T062C 26379:453.779 - 1.156ms returns FALSE +T062C 26379:553.884 JLINK_HasError() +T062C 26379:553.965 JLINK_HasError() +T062C 26379:554.013 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26379:554.074 Data: 8D 12 74 01 +T062C 26379:554.130 Debug reg: DWT_CYCCNT +T062C 26379:554.159 - 0.153ms returns 1 (0x1) +T3F74 26379:556.614 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26379:556.647 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26379:557.852 Data: 00 00 80 00 +T3F74 26379:557.931 - 1.341ms returns 4 (0x4) +T3F74 26379:557.988 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26379:558.011 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26379:559.073 Data: 00 00 F0 01 +T3F74 26379:559.106 - 1.125ms returns 4 (0x4) +T3F74 26379:562.761 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26379:562.794 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26379:563.957 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26379:563.990 - 1.237ms returns 16 (0x10) +T3F74 26379:564.014 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26379:564.037 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26379:564.442 Data: 1E 00 00 00 +T3F74 26379:564.466 - 0.460ms returns 4 (0x4) +T3F74 26379:564.487 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26379:564.506 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26379:565.068 Data: 00 00 00 00 00 00 00 00 00 00 00 00 9D 02 00 00 ... +T3F74 26379:565.092 - 0.612ms returns 20 (0x14) +T3F74 26379:565.112 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26379:565.131 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26379:565.568 Data: 1F 03 00 00 +T3F74 26379:565.592 - 0.488ms returns 4 (0x4) +T3F74 26379:565.613 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26379:565.632 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26379:566.068 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26379:566.092 - 0.487ms returns 12 (0xC) +T3F74 26379:566.112 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26379:566.131 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26379:566.594 Data: 00 00 00 00 +T3F74 26379:566.618 - 0.514ms returns 4 (0x4) +T3F74 26379:566.638 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26379:566.657 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26379:567.067 Data: 00 00 00 00 +T3F74 26379:567.091 - 0.460ms returns 4 (0x4) +T3F74 26379:567.111 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26379:567.130 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26379:567.566 Data: 00 00 00 00 +T3F74 26379:567.591 - 0.488ms returns 4 (0x4) +T062C 26379:580.600 JLINK_IsHalted() +T062C 26379:581.764 - 1.184ms returns FALSE +T062C 26379:681.986 JLINK_HasError() +T062C 26379:682.069 JLINK_IsHalted() +T062C 26379:683.240 - 1.189ms returns FALSE +T062C 26379:784.303 JLINK_HasError() +T062C 26379:784.383 JLINK_IsHalted() +T062C 26379:785.538 - 1.173ms returns FALSE +T062C 26379:886.695 JLINK_HasError() +T062C 26379:886.780 JLINK_IsHalted() +T062C 26379:887.960 - 1.197ms returns FALSE +T062C 26379:988.376 JLINK_HasError() +T062C 26379:988.455 JLINK_IsHalted() +T062C 26379:989.526 - 1.080ms returns FALSE +T062C 26380:089.765 JLINK_HasError() +T062C 26380:089.857 JLINK_HasError() +T062C 26380:089.908 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26380:089.970 Data: 8D 12 74 01 +T062C 26380:090.016 Debug reg: DWT_CYCCNT +T062C 26380:090.038 - 0.138ms returns 1 (0x1) +T3F74 26380:092.583 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26380:092.627 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26380:093.855 Data: 00 00 80 00 +T3F74 26380:093.911 - 1.335ms returns 4 (0x4) +T3F74 26380:093.946 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26380:093.966 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26380:094.379 Data: 00 00 F0 01 +T3F74 26380:094.403 - 0.464ms returns 4 (0x4) +T3F74 26380:097.746 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26380:097.778 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26380:099.050 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26380:099.078 - 1.338ms returns 16 (0x10) +T3F74 26380:099.099 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26380:099.118 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26380:099.621 Data: 1F 00 00 00 +T3F74 26380:099.641 - 0.549ms returns 4 (0x4) +T3F74 26380:099.659 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26380:099.675 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26380:100.120 Data: 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00 ... +T3F74 26380:100.140 - 0.488ms returns 20 (0x14) +T3F74 26380:100.157 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26380:100.174 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26380:100.620 Data: 1F 03 00 00 +T3F74 26380:100.641 - 0.489ms returns 4 (0x4) +T3F74 26380:100.657 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26380:100.673 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26380:101.118 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26380:101.138 - 0.487ms returns 12 (0xC) +T3F74 26380:101.155 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26380:101.171 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26380:101.621 Data: 00 00 00 00 +T3F74 26380:101.641 - 0.492ms returns 4 (0x4) +T3F74 26380:101.658 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26380:101.674 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26380:102.116 Data: 00 00 00 00 +T3F74 26380:102.136 - 0.484ms returns 4 (0x4) +T3F74 26380:102.153 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26380:102.169 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26380:102.664 Data: 00 00 00 00 +T3F74 26380:102.688 - 0.543ms returns 4 (0x4) +T062C 26380:121.482 JLINK_IsHalted() +T062C 26380:122.507 - 1.045ms returns FALSE +T062C 26380:222.710 JLINK_HasError() +T062C 26380:222.797 JLINK_IsHalted() +T062C 26380:224.097 - 1.318ms returns FALSE +T062C 26380:324.318 JLINK_HasError() +T062C 26380:324.365 JLINK_IsHalted() +T062C 26380:325.489 - 1.170ms returns FALSE +T062C 26380:425.732 JLINK_HasError() +T062C 26380:425.819 JLINK_IsHalted() +T062C 26380:427.049 - 1.249ms returns FALSE +T062C 26380:527.239 JLINK_HasError() +T062C 26380:527.320 JLINK_IsHalted() +T062C 26380:528.456 - 1.153ms returns FALSE +T062C 26380:629.041 JLINK_HasError() +T062C 26380:629.087 JLINK_HasError() +T062C 26380:629.103 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26380:629.128 Data: 8D 12 74 01 +T062C 26380:629.148 Debug reg: DWT_CYCCNT +T062C 26380:629.166 - 0.070ms returns 1 (0x1) +T3F74 26380:631.637 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26380:631.670 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26380:632.768 Data: 00 00 80 00 +T3F74 26380:632.855 - 1.237ms returns 4 (0x4) +T3F74 26380:632.972 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26380:632.996 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26380:634.199 Data: 00 00 F0 01 +T3F74 26380:634.278 - 1.326ms returns 4 (0x4) +T3F74 26380:637.741 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26380:637.776 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26380:639.055 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26380:639.126 - 1.393ms returns 16 (0x10) +T3F74 26380:639.150 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26380:639.173 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26380:640.397 Data: 1E 00 00 00 +T3F74 26380:640.475 - 1.351ms returns 4 (0x4) +T3F74 26380:640.515 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26380:640.534 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26380:641.048 Data: 00 00 00 00 00 00 00 00 00 00 00 00 F9 02 00 00 ... +T3F74 26380:641.068 - 0.560ms returns 20 (0x14) +T3F74 26380:641.086 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26380:641.102 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26380:641.549 Data: 1F 03 00 00 +T3F74 26380:641.570 - 0.490ms returns 4 (0x4) +T3F74 26380:641.587 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26380:641.603 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26380:642.048 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26380:642.068 - 0.487ms returns 12 (0xC) +T3F74 26380:642.085 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26380:642.107 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26380:642.548 Data: 00 00 00 00 +T3F74 26380:642.568 - 0.490ms returns 4 (0x4) +T3F74 26380:642.585 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26380:642.601 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26380:643.047 Data: 00 00 00 00 +T3F74 26380:643.067 - 0.488ms returns 4 (0x4) +T3F74 26380:643.084 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26380:643.100 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26380:643.547 Data: 00 00 00 00 +T3F74 26380:643.567 - 0.489ms returns 4 (0x4) +T062C 26380:663.221 JLINK_IsHalted() +T062C 26380:664.371 - 1.168ms returns FALSE +T062C 26380:765.451 JLINK_HasError() +T062C 26380:765.530 JLINK_IsHalted() +T062C 26380:766.790 - 1.308ms returns FALSE +T062C 26380:868.033 JLINK_HasError() +T062C 26380:868.115 JLINK_IsHalted() +T062C 26380:869.292 - 1.219ms returns FALSE +T062C 26380:969.481 JLINK_HasError() +T062C 26380:969.568 JLINK_IsHalted() +T062C 26380:970.729 - 1.179ms returns FALSE +T062C 26381:070.957 JLINK_HasError() +T062C 26381:071.035 JLINK_IsHalted() +T062C 26381:072.128 - 1.107ms returns FALSE +T062C 26381:172.283 JLINK_HasError() +T062C 26381:172.364 JLINK_HasError() +T062C 26381:172.408 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26381:172.469 Data: 8D 12 74 01 +T062C 26381:172.508 Debug reg: DWT_CYCCNT +T062C 26381:172.527 - 0.125ms returns 1 (0x1) +T3F74 26381:174.729 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26381:174.762 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26381:176.008 Data: 00 00 80 00 +T3F74 26381:176.088 - 1.386ms returns 4 (0x4) +T3F74 26381:176.148 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26381:176.172 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26381:177.319 Data: 00 00 F0 01 +T3F74 26381:177.397 - 1.268ms returns 4 (0x4) +T3F74 26381:180.824 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26381:180.860 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26381:182.031 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26381:182.060 - 1.242ms returns 16 (0x10) +T3F74 26381:182.080 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26381:182.099 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26381:182.476 Data: 1E 00 00 00 +T3F74 26381:182.496 - 0.423ms returns 4 (0x4) +T3F74 26381:182.514 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26381:182.530 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26381:182.977 Data: 00 00 00 00 00 00 00 00 00 00 00 00 7D 00 00 00 ... +T3F74 26381:182.997 - 0.489ms returns 20 (0x14) +T3F74 26381:183.014 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26381:183.030 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26381:183.476 Data: 1F 03 00 00 +T3F74 26381:183.496 - 0.489ms returns 4 (0x4) +T3F74 26381:183.513 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26381:183.530 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26381:183.976 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26381:183.996 - 0.489ms returns 12 (0xC) +T3F74 26381:184.013 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26381:184.029 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26381:184.475 Data: 00 00 00 00 +T3F74 26381:184.495 - 0.489ms returns 4 (0x4) +T3F74 26381:184.512 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26381:184.528 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26381:184.975 Data: 00 00 00 00 +T3F74 26381:184.995 - 0.489ms returns 4 (0x4) +T3F74 26381:185.012 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26381:185.028 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26381:185.475 Data: 00 00 00 00 +T3F74 26381:185.495 - 0.489ms returns 4 (0x4) +T062C 26381:197.016 JLINK_IsHalted() +T062C 26381:198.144 - 1.146ms returns FALSE +T062C 26381:299.159 JLINK_HasError() +T062C 26381:299.240 JLINK_IsHalted() +T062C 26381:300.348 - 1.115ms returns FALSE +T062C 26381:400.689 JLINK_HasError() +T062C 26381:400.743 JLINK_IsHalted() +T062C 26381:401.906 - 1.185ms returns FALSE +T062C 26381:502.679 JLINK_HasError() +T062C 26381:502.764 JLINK_IsHalted() +T062C 26381:503.972 - 1.226ms returns FALSE +T062C 26381:604.106 JLINK_HasError() +T062C 26381:604.193 JLINK_IsHalted() +T062C 26381:605.312 - 1.129ms returns FALSE +T062C 26381:706.616 JLINK_HasError() +T062C 26381:706.706 JLINK_HasError() +T062C 26381:706.750 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26381:706.811 Data: 8D 12 74 01 +T062C 26381:706.869 Debug reg: DWT_CYCCNT +T062C 26381:706.910 - 0.167ms returns 1 (0x1) +T3F74 26381:709.271 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26381:709.303 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26381:710.502 Data: 00 00 80 00 +T3F74 26381:710.546 - 1.284ms returns 4 (0x4) +T3F74 26381:710.591 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26381:710.654 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26381:711.865 Data: 00 00 F0 01 +T3F74 26381:711.939 - 1.355ms returns 4 (0x4) +T3F74 26381:715.279 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26381:715.306 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26381:716.546 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26381:716.579 - 1.308ms returns 16 (0x10) +T3F74 26381:716.603 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26381:716.626 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26381:717.031 Data: 1F 00 00 00 +T3F74 26381:717.055 - 0.460ms returns 4 (0x4) +T3F74 26381:717.075 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26381:717.104 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26381:717.668 Data: 00 00 00 00 00 00 00 00 00 00 00 00 33 00 00 00 ... +T3F74 26381:717.694 - 0.626ms returns 20 (0x14) +T3F74 26381:717.714 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26381:717.733 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26381:718.154 Data: 1F 03 00 00 +T3F74 26381:718.175 - 0.467ms returns 4 (0x4) +T3F74 26381:718.192 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26381:718.208 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26381:718.655 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26381:718.675 - 0.490ms returns 12 (0xC) +T3F74 26381:718.692 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26381:718.709 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26381:719.154 Data: 00 00 00 00 +T3F74 26381:719.173 - 0.488ms returns 4 (0x4) +T3F74 26381:719.190 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26381:719.206 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26381:719.655 Data: 00 00 00 00 +T3F74 26381:719.675 - 0.491ms returns 4 (0x4) +T3F74 26381:719.692 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26381:719.708 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26381:720.154 Data: 00 00 00 00 +T3F74 26381:720.174 - 0.488ms returns 4 (0x4) +T062C 26381:739.385 JLINK_IsHalted() +T062C 26381:740.432 - 1.065ms returns FALSE +T062C 26381:841.127 JLINK_HasError() +T062C 26381:841.167 JLINK_IsHalted() +T062C 26381:842.410 - 1.285ms returns FALSE +T062C 26381:942.896 JLINK_HasError() +T062C 26381:942.980 JLINK_IsHalted() +T062C 26381:944.044 - 1.072ms returns FALSE +T062C 26382:044.518 JLINK_HasError() +T062C 26382:044.595 JLINK_IsHalted() +T062C 26382:045.816 - 1.266ms returns FALSE +T062C 26382:146.135 JLINK_HasError() +T062C 26382:146.216 JLINK_IsHalted() +T062C 26382:147.429 - 1.256ms returns FALSE +T062C 26382:248.171 JLINK_HasError() +T062C 26382:248.250 JLINK_HasError() +T062C 26382:248.268 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26382:248.298 Data: 8D 12 74 01 +T062C 26382:248.322 Debug reg: DWT_CYCCNT +T062C 26382:248.344 - 0.083ms returns 1 (0x1) +T3F74 26382:250.701 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26382:250.734 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26382:251.869 Data: 00 00 80 00 +T3F74 26382:251.905 - 1.212ms returns 4 (0x4) +T3F74 26382:251.949 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26382:251.980 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26382:252.474 Data: 00 00 F0 01 +T3F74 26382:252.494 - 0.551ms returns 4 (0x4) +T3F74 26382:255.675 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26382:255.706 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26382:256.837 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26382:256.858 - 1.189ms returns 16 (0x10) +T3F74 26382:256.876 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26382:256.893 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26382:257.328 Data: 1E 00 00 00 +T3F74 26382:257.349 - 0.479ms returns 4 (0x4) +T3F74 26382:257.366 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26382:257.382 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26382:257.847 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1F 00 00 00 ... +T3F74 26382:257.882 - 0.524ms returns 20 (0x14) +T3F74 26382:257.909 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26382:257.932 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26382:258.343 Data: 1F 03 00 00 +T3F74 26382:258.373 - 0.471ms returns 4 (0x4) +T3F74 26382:258.395 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26382:258.416 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26382:258.844 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26382:258.868 - 0.480ms returns 12 (0xC) +T3F74 26382:258.888 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26382:258.907 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26382:259.345 Data: 00 00 00 00 +T3F74 26382:259.365 - 0.484ms returns 4 (0x4) +T3F74 26382:259.382 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26382:259.399 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26382:259.843 Data: 00 00 00 00 +T3F74 26382:259.867 - 0.492ms returns 4 (0x4) +T3F74 26382:259.887 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26382:259.906 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26382:260.338 Data: 00 00 00 00 +T3F74 26382:260.361 - 0.482ms returns 4 (0x4) +T062C 26382:280.070 JLINK_IsHalted() +T062C 26382:281.095 - 1.045ms returns FALSE +T062C 26382:381.351 JLINK_HasError() +T062C 26382:381.501 JLINK_IsHalted() +T062C 26382:382.761 - 1.302ms returns FALSE +T062C 26382:483.149 JLINK_HasError() +T062C 26382:483.194 JLINK_IsHalted() +T062C 26382:484.399 - 1.227ms returns FALSE +T062C 26382:584.738 JLINK_HasError() +T062C 26382:584.824 JLINK_IsHalted() +T062C 26382:586.103 - 1.321ms returns FALSE +T062C 26382:686.333 JLINK_HasError() +T062C 26382:686.431 JLINK_IsHalted() +T062C 26382:687.584 - 1.188ms returns FALSE +T062C 26382:787.790 JLINK_HasError() +T062C 26382:787.830 JLINK_HasError() +T062C 26382:787.848 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26382:787.880 Data: 8D 12 74 01 +T062C 26382:787.904 Debug reg: DWT_CYCCNT +T062C 26382:787.925 - 0.085ms returns 1 (0x1) +T3F74 26382:790.367 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26382:790.404 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26382:791.638 Data: 00 00 80 00 +T3F74 26382:791.673 - 1.313ms returns 4 (0x4) +T3F74 26382:791.712 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26382:791.735 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26382:792.145 Data: 00 00 F0 01 +T3F74 26382:792.168 - 0.464ms returns 4 (0x4) +T3F74 26382:795.177 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26382:795.204 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26382:796.417 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26382:796.449 - 1.280ms returns 16 (0x10) +T3F74 26382:796.473 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26382:796.496 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26382:797.017 Data: 1E 00 00 00 +T3F74 26382:797.041 - 0.575ms returns 4 (0x4) +T3F74 26382:797.062 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26382:797.081 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26382:797.649 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D7 01 00 00 ... +T3F74 26382:797.672 - 0.624ms returns 20 (0x14) +T3F74 26382:797.704 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26382:797.724 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26382:798.137 Data: 1F 03 00 00 +T3F74 26382:798.160 - 0.464ms returns 4 (0x4) +T3F74 26382:798.181 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26382:798.200 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26382:798.648 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26382:798.673 - 0.500ms returns 12 (0xC) +T3F74 26382:798.693 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26382:798.712 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26382:799.151 Data: 00 00 00 00 +T3F74 26382:799.174 - 0.489ms returns 4 (0x4) +T3F74 26382:799.195 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26382:799.213 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26382:799.765 Data: 00 00 00 00 +T3F74 26382:799.788 - 0.601ms returns 4 (0x4) +T3F74 26382:799.808 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26382:799.827 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26382:800.278 Data: 00 00 00 00 +T3F74 26382:800.301 - 0.501ms returns 4 (0x4) +T062C 26382:812.648 JLINK_IsHalted() +T062C 26382:813.769 - 1.135ms returns FALSE +T062C 26382:913.851 JLINK_HasError() +T062C 26382:913.889 JLINK_IsHalted() +T062C 26382:915.086 - 1.215ms returns FALSE +T062C 26383:015.924 JLINK_HasError() +T062C 26383:016.003 JLINK_IsHalted() +T062C 26383:017.131 - 1.140ms returns FALSE +T062C 26383:117.596 JLINK_HasError() +T062C 26383:117.669 JLINK_IsHalted() +T062C 26383:118.843 - 1.222ms returns FALSE +T062C 26383:219.076 JLINK_HasError() +T062C 26383:219.147 JLINK_IsHalted() +T062C 26383:220.276 - 1.147ms returns FALSE +T062C 26383:320.667 JLINK_HasError() +T062C 26383:320.742 JLINK_HasError() +T062C 26383:320.773 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26383:320.802 Data: 8D 12 74 01 +T062C 26383:320.827 Debug reg: DWT_CYCCNT +T062C 26383:320.849 - 0.083ms returns 1 (0x1) +T3F74 26383:323.194 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26383:323.227 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26383:324.416 Data: 00 00 80 00 +T3F74 26383:324.477 - 1.290ms returns 4 (0x4) +T3F74 26383:324.511 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26383:324.531 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26383:324.941 Data: 00 00 F0 01 +T3F74 26383:324.962 - 0.457ms returns 4 (0x4) +T3F74 26383:327.940 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26383:327.968 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26383:329.283 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26383:329.347 - 1.415ms returns 16 (0x10) +T3F74 26383:329.371 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26383:329.394 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26383:329.818 Data: 1F 00 00 00 +T3F74 26383:329.842 - 0.478ms returns 4 (0x4) +T3F74 26383:329.863 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26383:329.882 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26383:330.446 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E7 00 00 00 ... +T3F74 26383:330.472 - 0.617ms returns 20 (0x14) +T3F74 26383:330.494 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26383:330.515 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26383:330.963 Data: 1F 03 00 00 +T3F74 26383:330.987 - 0.501ms returns 4 (0x4) +T3F74 26383:331.008 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26383:331.027 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26383:331.582 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26383:331.606 - 0.605ms returns 12 (0xC) +T3F74 26383:331.626 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26383:331.645 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26383:332.063 Data: 00 00 00 00 +T3F74 26383:332.083 - 0.463ms returns 4 (0x4) +T3F74 26383:332.100 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26383:332.116 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26383:332.569 Data: 00 00 00 00 +T3F74 26383:332.599 - 0.506ms returns 4 (0x4) +T3F74 26383:332.616 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26383:332.632 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26383:333.061 Data: 00 00 00 00 +T3F74 26383:333.082 - 0.472ms returns 4 (0x4) +T062C 26383:352.700 JLINK_IsHalted() +T062C 26383:353.829 - 1.141ms returns FALSE +T062C 26383:454.132 JLINK_HasError() +T062C 26383:454.287 JLINK_IsHalted() +T062C 26383:455.560 - 1.323ms returns FALSE +T062C 26383:555.837 JLINK_HasError() +T062C 26383:555.884 JLINK_IsHalted() +T062C 26383:557.003 - 1.141ms returns FALSE +T062C 26383:657.398 JLINK_HasError() +T062C 26383:657.439 JLINK_IsHalted() +T062C 26383:658.531 - 1.100ms returns FALSE +T062C 26383:758.713 JLINK_HasError() +T062C 26383:758.789 JLINK_IsHalted() +T062C 26383:760.013 - 1.265ms returns FALSE +T062C 26383:860.671 JLINK_HasError() +T062C 26383:860.716 JLINK_HasError() +T062C 26383:860.734 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26383:860.763 Data: 8D 12 74 01 +T062C 26383:860.787 Debug reg: DWT_CYCCNT +T062C 26383:860.809 - 0.082ms returns 1 (0x1) +T3F74 26383:863.202 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26383:863.236 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26383:864.336 Data: 00 00 80 00 +T3F74 26383:864.371 - 1.176ms returns 4 (0x4) +T3F74 26383:864.417 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26383:864.440 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26383:864.933 Data: 00 00 F0 01 +T3F74 26383:864.957 - 0.547ms returns 4 (0x4) +T3F74 26383:868.117 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26383:868.144 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26383:869.426 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26383:869.454 - 1.344ms returns 16 (0x10) +T3F74 26383:869.475 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26383:869.495 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26383:869.869 Data: 1E 00 00 00 +T3F74 26383:869.889 - 0.421ms returns 4 (0x4) +T3F74 26383:869.907 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26383:869.923 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26383:870.370 Data: 00 00 00 00 00 00 00 00 00 00 00 00 DB 00 00 00 ... +T3F74 26383:870.390 - 0.489ms returns 20 (0x14) +T3F74 26383:870.407 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26383:870.423 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26383:870.869 Data: 1F 03 00 00 +T3F74 26383:870.889 - 0.488ms returns 4 (0x4) +T3F74 26383:870.906 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26383:870.922 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26383:871.369 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26383:871.389 - 0.489ms returns 12 (0xC) +T3F74 26383:871.406 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26383:871.422 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26383:871.869 Data: 00 00 00 00 +T3F74 26383:871.889 - 0.489ms returns 4 (0x4) +T3F74 26383:871.906 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26383:871.922 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26383:872.368 Data: 00 00 00 00 +T3F74 26383:872.387 - 0.488ms returns 4 (0x4) +T3F74 26383:872.404 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26383:872.420 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26383:872.864 Data: 00 00 00 00 +T3F74 26383:872.884 - 0.486ms returns 4 (0x4) +T062C 26383:892.589 JLINK_IsHalted() +T062C 26383:893.686 - 1.139ms returns FALSE +T062C 26383:994.517 JLINK_HasError() +T062C 26383:994.593 JLINK_IsHalted() +T062C 26383:995.866 - 1.291ms returns FALSE +T062C 26384:095.950 JLINK_HasError() +T062C 26384:095.985 JLINK_IsHalted() +T062C 26384:097.108 - 1.142ms returns FALSE +T062C 26384:197.889 JLINK_HasError() +T062C 26384:197.941 JLINK_IsHalted() +T062C 26384:199.099 - 1.177ms returns FALSE +T062C 26384:299.567 JLINK_HasError() +T062C 26384:299.640 JLINK_IsHalted() +T062C 26384:300.810 - 1.187ms returns FALSE +T062C 26384:401.520 JLINK_HasError() +T062C 26384:401.582 JLINK_HasError() +T062C 26384:401.601 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26384:401.629 Data: 8D 12 74 01 +T062C 26384:401.656 Debug reg: DWT_CYCCNT +T062C 26384:401.678 - 0.084ms returns 1 (0x1) +T3F74 26384:404.117 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26384:404.155 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26384:405.184 Data: 00 00 80 00 +T3F74 26384:405.213 - 1.103ms returns 4 (0x4) +T3F74 26384:405.248 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26384:405.268 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26384:405.708 Data: 00 00 F0 01 +T3F74 26384:405.734 - 0.494ms returns 4 (0x4) +T3F74 26384:408.937 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26384:408.964 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26384:410.239 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26384:410.267 - 1.337ms returns 16 (0x10) +T3F74 26384:410.288 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26384:410.307 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26384:410.794 Data: 1E 00 00 00 +T3F74 26384:410.814 - 0.533ms returns 4 (0x4) +T3F74 26384:410.831 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26384:410.848 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26384:411.293 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1B 03 00 00 ... +T3F74 26384:411.312 - 0.487ms returns 20 (0x14) +T3F74 26384:411.330 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26384:411.346 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26384:411.799 Data: 1F 03 00 00 +T3F74 26384:411.822 - 0.500ms returns 4 (0x4) +T3F74 26384:411.843 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26384:411.861 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26384:412.297 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26384:412.321 - 0.486ms returns 12 (0xC) +T3F74 26384:412.341 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26384:412.360 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26384:412.809 Data: 00 00 00 00 +T3F74 26384:412.833 - 0.499ms returns 4 (0x4) +T3F74 26384:412.866 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26384:412.887 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26384:413.302 Data: 00 00 00 00 +T3F74 26384:413.325 - 0.467ms returns 4 (0x4) +T3F74 26384:413.348 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26384:413.367 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26384:413.833 Data: 00 00 00 00 +T3F74 26384:413.858 - 0.517ms returns 4 (0x4) +T062C 26384:425.392 JLINK_IsHalted() +T062C 26384:426.431 - 1.057ms returns FALSE +T062C 26384:526.618 JLINK_HasError() +T062C 26384:526.701 JLINK_IsHalted() +T062C 26384:527.894 - 1.211ms returns FALSE +T062C 26384:628.052 JLINK_HasError() +T062C 26384:628.098 JLINK_IsHalted() +T062C 26384:629.194 - 1.118ms returns FALSE +T062C 26384:729.545 JLINK_HasError() +T062C 26384:729.601 JLINK_IsHalted() +T062C 26384:730.750 - 1.167ms returns FALSE +T062C 26384:830.938 JLINK_HasError() +T062C 26384:831.014 JLINK_IsHalted() +T062C 26384:832.128 - 1.132ms returns FALSE +T062C 26384:933.262 JLINK_HasError() +T062C 26384:933.301 JLINK_HasError() +T062C 26384:933.317 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26384:933.343 Data: 8D 12 74 01 +T062C 26384:933.363 Debug reg: DWT_CYCCNT +T062C 26384:933.382 - 0.071ms returns 1 (0x1) +T3F74 26384:936.853 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26384:936.892 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26384:938.082 Data: 00 00 80 00 +T3F74 26384:938.140 - 1.294ms returns 4 (0x4) +T3F74 26384:938.175 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26384:938.195 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26384:938.604 Data: 00 00 F0 01 +T3F74 26384:938.628 - 0.460ms returns 4 (0x4) +T3F74 26384:941.802 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26384:941.829 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26384:943.010 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26384:943.054 - 1.260ms returns 16 (0x10) +T3F74 26384:943.078 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26384:943.101 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26384:943.601 Data: 1E 00 00 00 +T3F74 26384:943.622 - 0.550ms returns 4 (0x4) +T3F74 26384:943.639 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26384:943.656 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26384:944.102 Data: 00 00 00 00 00 00 00 00 00 00 00 00 1D 03 00 00 ... +T3F74 26384:944.122 - 0.489ms returns 20 (0x14) +T3F74 26384:944.139 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26384:944.155 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26384:944.597 Data: 1F 03 00 00 +T3F74 26384:944.617 - 0.484ms returns 4 (0x4) +T3F74 26384:944.634 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26384:944.650 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26384:945.096 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26384:945.116 - 0.488ms returns 12 (0xC) +T3F74 26384:945.133 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26384:945.149 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26384:945.605 Data: 00 00 00 00 +T3F74 26384:945.628 - 0.503ms returns 4 (0x4) +T3F74 26384:945.648 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26384:945.667 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26384:946.109 Data: 00 00 00 00 +T3F74 26384:946.132 - 0.491ms returns 4 (0x4) +T3F74 26384:946.152 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26384:946.171 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26384:946.603 Data: 00 00 00 00 +T3F74 26384:946.628 - 0.483ms returns 4 (0x4) +T062C 26384:958.654 JLINK_IsHalted() +T062C 26384:959.735 - 1.099ms returns FALSE +T062C 26385:060.702 JLINK_HasError() +T062C 26385:060.778 JLINK_IsHalted() +T062C 26385:061.962 - 1.202ms returns FALSE +T062C 26385:162.152 JLINK_HasError() +T062C 26385:162.227 JLINK_IsHalted() +T062C 26385:163.422 - 1.237ms returns FALSE +T062C 26385:263.608 JLINK_HasError() +T062C 26385:263.679 JLINK_IsHalted() +T062C 26385:264.829 - 1.159ms returns FALSE +T062C 26385:365.017 JLINK_HasError() +T062C 26385:365.089 JLINK_IsHalted() +T062C 26385:366.293 - 1.252ms returns FALSE +T062C 26385:466.537 JLINK_HasError() +T062C 26385:466.589 JLINK_HasError() +T062C 26385:466.607 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26385:466.637 Data: 8D 12 74 01 +T062C 26385:466.661 Debug reg: DWT_CYCCNT +T062C 26385:466.683 - 0.083ms returns 1 (0x1) +T3F74 26385:469.215 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26385:469.256 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26385:470.438 Data: 00 00 80 00 +T3F74 26385:470.519 - 1.329ms returns 4 (0x4) +T3F74 26385:470.580 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26385:470.603 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26385:471.750 Data: 00 00 F0 01 +T3F74 26385:471.828 - 1.267ms returns 4 (0x4) +T3F74 26385:475.044 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26385:475.075 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26385:476.284 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26385:476.305 - 1.268ms returns 16 (0x10) +T3F74 26385:476.323 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26385:476.339 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26385:476.801 Data: 1F 00 00 00 +T3F74 26385:476.837 - 0.522ms returns 4 (0x4) +T3F74 26385:476.864 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26385:476.887 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26385:477.420 Data: 00 00 00 00 00 00 00 00 00 00 00 00 AF 02 00 00 ... +T3F74 26385:477.444 - 0.587ms returns 20 (0x14) +T3F74 26385:477.465 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26385:477.484 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26385:477.907 Data: 1F 03 00 00 +T3F74 26385:477.930 - 0.473ms returns 4 (0x4) +T3F74 26385:477.951 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26385:477.976 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26385:478.412 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26385:478.443 - 0.500ms returns 12 (0xC) +T3F74 26385:478.469 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26385:478.491 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26385:478.901 Data: 00 00 00 00 +T3F74 26385:478.921 - 0.459ms returns 4 (0x4) +T3F74 26385:478.938 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26385:478.954 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26385:479.428 Data: 00 00 00 00 +T3F74 26385:479.452 - 0.521ms returns 4 (0x4) +T3F74 26385:479.475 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26385:479.495 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26385:479.911 Data: 00 00 00 00 +T3F74 26385:479.934 - 0.466ms returns 4 (0x4) +T062C 26385:498.846 JLINK_IsHalted() +T062C 26385:499.987 - 1.156ms returns FALSE +T062C 26385:600.183 JLINK_HasError() +T062C 26385:600.262 JLINK_IsHalted() +T062C 26385:601.474 - 1.252ms returns FALSE +T062C 26385:701.683 JLINK_HasError() +T062C 26385:701.768 JLINK_IsHalted() +T062C 26385:702.861 - 1.113ms returns FALSE +T062C 26385:803.057 JLINK_HasError() +T062C 26385:803.146 JLINK_IsHalted() +T062C 26385:804.358 - 1.232ms returns FALSE +T062C 26385:905.028 JLINK_HasError() +T062C 26385:905.074 JLINK_IsHalted() +T062C 26385:906.151 - 1.110ms returns FALSE +T062C 26386:007.260 JLINK_HasError() +T062C 26386:007.340 JLINK_HasError() +T062C 26386:007.382 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26386:007.411 Data: 8D 12 74 01 +T062C 26386:007.435 Debug reg: DWT_CYCCNT +T062C 26386:007.457 - 0.083ms returns 1 (0x1) +T3F74 26386:009.697 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26386:009.735 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26386:010.987 Data: 00 00 80 00 +T3F74 26386:011.067 - 1.389ms returns 4 (0x4) +T3F74 26386:011.127 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26386:011.150 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26386:012.294 Data: 00 00 F0 01 +T3F74 26386:012.372 - 1.265ms returns 4 (0x4) +T3F74 26386:015.412 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26386:015.439 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26386:016.599 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26386:016.623 - 1.219ms returns 16 (0x10) +T3F74 26386:016.647 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26386:016.667 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26386:017.089 Data: 1F 00 00 00 +T3F74 26386:017.113 - 0.473ms returns 4 (0x4) +T3F74 26386:017.136 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26386:017.155 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26386:017.717 Data: 00 00 00 00 00 00 00 00 00 00 00 00 BB 00 00 00 ... +T3F74 26386:017.741 - 0.612ms returns 20 (0x14) +T3F74 26386:017.775 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26386:017.794 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26386:018.213 Data: 1F 03 00 00 +T3F74 26386:018.236 - 0.469ms returns 4 (0x4) +T3F74 26386:018.259 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26386:018.278 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26386:018.715 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26386:018.738 - 0.487ms returns 12 (0xC) +T3F74 26386:018.769 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26386:018.788 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26386:019.231 Data: 00 00 00 00 +T3F74 26386:019.254 - 0.493ms returns 4 (0x4) +T3F74 26386:019.277 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26386:019.296 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26386:019.711 Data: 00 00 00 00 +T3F74 26386:019.735 - 0.465ms returns 4 (0x4) +T3F74 26386:019.759 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26386:019.779 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26386:020.236 Data: 00 00 00 00 +T3F74 26386:020.260 - 0.508ms returns 4 (0x4) +T062C 26386:032.530 JLINK_IsHalted() +T062C 26386:033.596 - 1.088ms returns FALSE +T062C 26386:134.068 JLINK_HasError() +T062C 26386:134.106 JLINK_IsHalted() +T062C 26386:135.215 - 1.128ms returns FALSE +T062C 26386:235.433 JLINK_HasError() +T062C 26386:235.511 JLINK_IsHalted() +T062C 26386:236.777 - 1.284ms returns FALSE +T062C 26386:336.964 JLINK_HasError() +T062C 26386:337.041 JLINK_IsHalted() +T062C 26386:338.278 - 1.255ms returns FALSE +T062C 26386:438.528 JLINK_HasError() +T062C 26386:438.615 JLINK_IsHalted() +T062C 26386:439.888 - 1.314ms returns FALSE +T062C 26386:540.622 JLINK_HasError() +T062C 26386:540.657 JLINK_HasError() +T062C 26386:540.672 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26386:540.698 Data: 8D 12 74 01 +T062C 26386:540.719 Debug reg: DWT_CYCCNT +T062C 26386:540.737 - 0.071ms returns 1 (0x1) +T3F74 26386:543.164 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26386:543.197 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26386:544.416 Data: 00 00 80 00 +T3F74 26386:544.496 - 1.352ms returns 4 (0x4) +T3F74 26386:544.556 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26386:544.579 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26386:545.644 Data: 00 00 F0 01 +T3F74 26386:545.677 - 1.130ms returns 4 (0x4) +T3F74 26386:549.159 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26386:549.188 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26386:550.406 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26386:550.438 - 1.287ms returns 16 (0x10) +T3F74 26386:550.462 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26386:550.485 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26386:550.912 Data: 1F 00 00 00 +T3F74 26386:550.945 - 0.491ms returns 4 (0x4) +T3F74 26386:550.966 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26386:550.985 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26386:551.523 Data: 00 00 00 00 00 00 00 00 00 00 00 00 6F 02 00 00 ... +T3F74 26386:551.548 - 0.590ms returns 20 (0x14) +T3F74 26386:551.569 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26386:551.587 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26386:552.013 Data: 1F 03 00 00 +T3F74 26386:552.033 - 0.471ms returns 4 (0x4) +T3F74 26386:552.050 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26386:552.066 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26386:552.513 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26386:552.533 - 0.489ms returns 12 (0xC) +T3F74 26386:552.550 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26386:552.566 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26386:553.012 Data: 00 00 00 00 +T3F74 26386:553.032 - 0.489ms returns 4 (0x4) +T3F74 26386:553.049 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26386:553.065 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26386:553.512 Data: 00 00 00 00 +T3F74 26386:553.532 - 0.489ms returns 4 (0x4) +T3F74 26386:553.549 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26386:553.565 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26386:554.007 Data: 00 00 00 00 +T3F74 26386:554.026 - 0.484ms returns 4 (0x4) +T062C 26386:565.754 JLINK_IsHalted() +T062C 26386:566.800 - 1.064ms returns FALSE +T062C 26386:667.390 JLINK_HasError() +T062C 26386:667.436 JLINK_IsHalted() +T062C 26386:668.649 - 1.254ms returns FALSE +T062C 26386:769.692 JLINK_HasError() +T062C 26386:769.775 JLINK_IsHalted() +T062C 26386:770.878 - 1.125ms returns FALSE +T062C 26386:871.070 JLINK_HasError() +T062C 26386:871.156 JLINK_IsHalted() +T062C 26386:872.321 - 1.206ms returns FALSE +T062C 26386:973.144 JLINK_HasError() +T062C 26386:973.231 JLINK_IsHalted() +T062C 26386:974.437 - 1.247ms returns FALSE +T062C 26387:075.153 JLINK_HasError() +T062C 26387:075.199 JLINK_HasError() +T062C 26387:075.225 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26387:075.255 Data: 8D 12 74 01 +T062C 26387:075.278 Debug reg: DWT_CYCCNT +T062C 26387:075.310 - 0.095ms returns 1 (0x1) +T3F74 26387:077.691 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26387:077.723 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26387:078.911 Data: 00 00 80 00 +T3F74 26387:078.977 - 1.293ms returns 4 (0x4) +T3F74 26387:079.011 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26387:079.031 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26387:079.438 Data: 00 00 F0 01 +T3F74 26387:079.459 - 0.454ms returns 4 (0x4) +T3F74 26387:083.203 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26387:083.233 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26387:084.463 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26387:084.495 - 1.300ms returns 16 (0x10) +T3F74 26387:084.519 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26387:084.552 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26387:084.949 Data: 1F 00 00 00 +T3F74 26387:084.973 - 0.461ms returns 4 (0x4) +T3F74 26387:084.993 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26387:085.013 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26387:085.566 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E1 02 00 00 ... +T3F74 26387:085.586 - 0.600ms returns 20 (0x14) +T3F74 26387:085.604 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26387:085.620 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26387:086.067 Data: 1F 03 00 00 +T3F74 26387:086.087 - 0.489ms returns 4 (0x4) +T3F74 26387:086.104 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26387:086.120 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26387:086.568 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26387:086.587 - 0.490ms returns 12 (0xC) +T3F74 26387:086.604 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26387:086.620 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26387:087.066 Data: 00 00 00 00 +T3F74 26387:087.086 - 0.489ms returns 4 (0x4) +T3F74 26387:087.103 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26387:087.119 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26387:087.565 Data: 00 00 00 00 +T3F74 26387:087.585 - 0.488ms returns 4 (0x4) +T3F74 26387:087.602 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26387:087.618 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26387:088.063 Data: 00 00 00 00 +T3F74 26387:088.082 - 0.487ms returns 4 (0x4) +T062C 26387:101.089 JLINK_IsHalted() +T062C 26387:102.198 - 1.120ms returns FALSE +T062C 26387:202.390 JLINK_HasError() +T062C 26387:202.474 JLINK_IsHalted() +T062C 26387:203.672 - 1.240ms returns FALSE +T062C 26387:303.919 JLINK_HasError() +T062C 26387:303.995 JLINK_IsHalted() +T062C 26387:305.061 - 1.084ms returns FALSE +T062C 26387:405.839 JLINK_HasError() +T062C 26387:405.914 JLINK_IsHalted() +T062C 26387:407.154 - 1.258ms returns FALSE +T062C 26387:508.140 JLINK_HasError() +T062C 26387:508.221 JLINK_IsHalted() +T062C 26387:509.488 - 1.286ms returns FALSE +T062C 26387:610.253 JLINK_HasError() +T062C 26387:610.329 JLINK_HasError() +T062C 26387:610.355 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26387:610.384 Data: 8D 12 74 01 +T062C 26387:610.408 Debug reg: DWT_CYCCNT +T062C 26387:610.430 - 0.082ms returns 1 (0x1) +T3F74 26387:613.011 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26387:613.048 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26387:614.233 Data: 00 00 80 00 +T3F74 26387:614.289 - 1.284ms returns 4 (0x4) +T3F74 26387:614.324 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26387:614.344 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26387:614.743 Data: 00 00 F0 01 +T3F74 26387:614.763 - 0.445ms returns 4 (0x4) +T3F74 26387:618.065 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26387:618.096 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26387:619.265 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26387:619.298 - 1.240ms returns 16 (0x10) +T3F74 26387:619.321 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26387:619.344 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26387:619.747 Data: 1E 00 00 00 +T3F74 26387:619.771 - 0.458ms returns 4 (0x4) +T3F74 26387:619.791 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26387:619.817 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26387:620.373 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B5 01 00 00 ... +T3F74 26387:620.397 - 0.618ms returns 20 (0x14) +T3F74 26387:620.420 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26387:620.437 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26387:620.876 Data: 1F 03 00 00 +T3F74 26387:620.900 - 0.487ms returns 4 (0x4) +T3F74 26387:620.920 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26387:620.939 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26387:621.377 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26387:621.400 - 0.488ms returns 12 (0xC) +T3F74 26387:621.420 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26387:621.439 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26387:621.896 Data: 00 00 00 00 +T3F74 26387:621.920 - 0.507ms returns 4 (0x4) +T3F74 26387:621.940 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26387:621.959 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26387:622.384 Data: 00 00 00 00 +T3F74 26387:622.409 - 0.477ms returns 4 (0x4) +T3F74 26387:622.429 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26387:622.448 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26387:622.878 Data: 00 00 00 00 +T3F74 26387:622.901 - 0.480ms returns 4 (0x4) +T062C 26387:642.073 JLINK_IsHalted() +T062C 26387:643.186 - 1.131ms returns FALSE +T062C 26387:743.945 JLINK_HasError() +T062C 26387:744.027 JLINK_IsHalted() +T062C 26387:745.204 - 1.194ms returns FALSE +T062C 26387:845.790 JLINK_HasError() +T062C 26387:845.835 JLINK_IsHalted() +T062C 26387:846.906 - 1.091ms returns FALSE +T062C 26387:947.238 JLINK_HasError() +T062C 26387:947.329 JLINK_IsHalted() +T062C 26387:948.608 - 1.298ms returns FALSE +T062C 26388:048.739 JLINK_HasError() +T062C 26388:048.773 JLINK_IsHalted() +T062C 26388:049.944 - 1.213ms returns FALSE +T062C 26388:150.880 JLINK_HasError() +T062C 26388:150.921 JLINK_HasError() +T062C 26388:150.939 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26388:150.967 Data: 8D 12 74 01 +T062C 26388:150.991 Debug reg: DWT_CYCCNT +T062C 26388:151.013 - 0.081ms returns 1 (0x1) +T3F74 26388:153.370 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26388:153.404 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26388:154.586 Data: 00 00 80 00 +T3F74 26388:154.665 - 1.318ms returns 4 (0x4) +T3F74 26388:154.722 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26388:154.746 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26388:155.886 Data: 00 00 F0 01 +T3F74 26388:155.932 - 1.216ms returns 4 (0x4) +T3F74 26388:158.949 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26388:158.976 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26388:160.176 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26388:160.197 - 1.255ms returns 16 (0x10) +T3F74 26388:160.215 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26388:160.232 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26388:160.669 Data: 1E 00 00 00 +T3F74 26388:160.690 - 0.481ms returns 4 (0x4) +T3F74 26388:160.707 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26388:160.723 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26388:161.174 Data: 00 00 00 00 00 00 00 00 00 00 00 00 51 02 00 00 ... +T3F74 26388:161.194 - 0.493ms returns 20 (0x14) +T3F74 26388:161.211 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26388:161.227 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26388:161.674 Data: 1F 03 00 00 +T3F74 26388:161.694 - 0.489ms returns 4 (0x4) +T3F74 26388:161.711 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26388:161.727 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26388:162.284 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26388:162.320 - 0.617ms returns 12 (0xC) +T3F74 26388:162.350 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26388:162.372 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26388:162.800 Data: 00 00 00 00 +T3F74 26388:162.843 - 0.502ms returns 4 (0x4) +T3F74 26388:162.866 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26388:162.887 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26388:163.304 Data: 00 00 00 00 +T3F74 26388:163.328 - 0.470ms returns 4 (0x4) +T3F74 26388:163.362 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26388:163.381 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26388:163.805 Data: 00 00 00 00 +T3F74 26388:163.828 - 0.474ms returns 4 (0x4) +T062C 26388:176.007 JLINK_IsHalted() +T062C 26388:177.057 - 1.068ms returns FALSE +T062C 26388:277.703 JLINK_HasError() +T062C 26388:277.753 JLINK_IsHalted() +T062C 26388:278.866 - 1.154ms returns FALSE +T062C 26388:379.955 JLINK_HasError() +T062C 26388:379.988 JLINK_IsHalted() +T062C 26388:381.067 - 1.095ms returns FALSE +T062C 26388:481.753 JLINK_HasError() +T062C 26388:481.784 JLINK_IsHalted() +T062C 26388:482.999 - 1.233ms returns FALSE +T062C 26388:583.893 JLINK_HasError() +T062C 26388:583.973 JLINK_IsHalted() +T062C 26388:585.331 - 1.377ms returns FALSE +T062C 26388:685.999 JLINK_HasError() +T062C 26388:686.033 JLINK_HasError() +T062C 26388:686.051 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26388:686.081 Data: 8D 12 74 01 +T062C 26388:686.105 Debug reg: DWT_CYCCNT +T062C 26388:686.127 - 0.083ms returns 1 (0x1) +T3F74 26388:688.395 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26388:688.431 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26388:689.512 Data: 00 00 80 00 +T3F74 26388:689.546 - 1.159ms returns 4 (0x4) +T3F74 26388:689.584 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26388:689.608 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26388:690.129 Data: 00 00 F0 01 +T3F74 26388:690.149 - 0.571ms returns 4 (0x4) +T3F74 26388:693.965 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26388:693.999 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26388:695.282 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26388:695.311 - 1.353ms returns 16 (0x10) +T3F74 26388:695.332 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26388:695.351 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26388:695.728 Data: 1E 00 00 00 +T3F74 26388:695.748 - 0.423ms returns 4 (0x4) +T3F74 26388:695.766 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26388:695.782 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26388:696.227 Data: 00 00 00 00 00 00 00 00 00 00 00 00 E9 02 00 00 ... +T3F74 26388:696.248 - 0.488ms returns 20 (0x14) +T3F74 26388:696.265 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26388:696.281 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26388:696.727 Data: 1F 03 00 00 +T3F74 26388:696.747 - 0.489ms returns 4 (0x4) +T3F74 26388:696.764 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26388:696.781 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26388:697.227 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26388:697.247 - 0.489ms returns 12 (0xC) +T3F74 26388:697.264 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26388:697.280 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26388:697.727 Data: 00 00 00 00 +T3F74 26388:697.747 - 0.489ms returns 4 (0x4) +T3F74 26388:697.764 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26388:697.780 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26388:698.222 Data: 00 00 00 00 +T3F74 26388:698.242 - 0.484ms returns 4 (0x4) +T3F74 26388:698.259 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26388:698.275 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26388:698.723 Data: 00 00 00 00 +T3F74 26388:698.743 - 0.490ms returns 4 (0x4) +T062C 26388:711.162 JLINK_IsHalted() +T062C 26388:712.254 - 1.110ms returns FALSE +T062C 26388:812.427 JLINK_HasError() +T062C 26388:812.510 JLINK_IsHalted() +T062C 26388:813.717 - 1.254ms returns FALSE +T062C 26388:914.012 JLINK_HasError() +T062C 26388:914.059 JLINK_IsHalted() +T062C 26388:915.090 - 1.040ms returns FALSE +T062C 26389:015.741 JLINK_HasError() +T062C 26389:015.783 JLINK_IsHalted() +T062C 26389:016.977 - 1.213ms returns FALSE +T062C 26389:117.580 JLINK_HasError() +T062C 26389:117.652 JLINK_IsHalted() +T062C 26389:118.983 - 1.347ms returns FALSE +T062C 26389:219.155 JLINK_HasError() +T062C 26389:219.196 JLINK_HasError() +T062C 26389:219.215 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26389:219.244 Data: 8D 12 74 01 +T062C 26389:219.268 Debug reg: DWT_CYCCNT +T062C 26389:219.290 - 0.082ms returns 1 (0x1) +T3F74 26389:221.998 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26389:222.035 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26389:223.314 Data: 00 00 80 00 +T3F74 26389:223.395 - 1.424ms returns 4 (0x4) +T3F74 26389:223.455 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26389:223.478 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26389:224.618 Data: 00 00 F0 01 +T3F74 26389:224.696 - 1.261ms returns 4 (0x4) +T3F74 26389:228.115 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26389:228.145 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26389:229.343 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26389:229.373 - 1.266ms returns 16 (0x10) +T3F74 26389:229.395 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26389:229.416 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26389:229.912 Data: 1E 00 00 00 +T3F74 26389:229.936 - 0.548ms returns 4 (0x4) +T3F74 26389:229.956 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26389:229.975 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26389:230.532 Data: 00 00 00 00 00 00 00 00 00 00 00 00 F5 01 00 00 ... +T3F74 26389:230.552 - 0.602ms returns 20 (0x14) +T3F74 26389:230.569 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26389:230.585 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26389:231.031 Data: 1F 03 00 00 +T3F74 26389:231.051 - 0.488ms returns 4 (0x4) +T3F74 26389:231.068 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26389:231.084 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26389:231.531 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26389:231.551 - 0.489ms returns 12 (0xC) +T3F74 26389:231.568 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26389:231.584 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26389:232.030 Data: 00 00 00 00 +T3F74 26389:232.050 - 0.489ms returns 4 (0x4) +T3F74 26389:232.068 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26389:232.084 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26389:232.530 Data: 00 00 00 00 +T3F74 26389:232.550 - 0.489ms returns 4 (0x4) +T3F74 26389:232.567 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26389:232.583 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26389:233.031 Data: 00 00 00 00 +T3F74 26389:233.051 - 0.490ms returns 4 (0x4) +T062C 26389:245.231 JLINK_IsHalted() +T062C 26389:246.291 - 1.078ms returns FALSE +T062C 26389:346.493 JLINK_HasError() +T062C 26389:346.573 JLINK_IsHalted() +T062C 26389:347.715 - 1.160ms returns FALSE +T062C 26389:447.926 JLINK_HasError() +T062C 26389:448.001 JLINK_IsHalted() +T062C 26389:449.220 - 1.237ms returns FALSE +T062C 26389:550.137 JLINK_HasError() +T062C 26389:550.215 JLINK_IsHalted() +T062C 26389:551.254 - 1.058ms returns FALSE +T062C 26389:651.929 JLINK_HasError() +T062C 26389:651.959 JLINK_IsHalted() +T062C 26389:653.043 - 1.102ms returns FALSE +T062C 26389:753.120 JLINK_HasError() +T062C 26389:753.157 JLINK_HasError() +T062C 26389:753.176 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26389:753.205 Data: 8D 12 74 01 +T062C 26389:753.229 Debug reg: DWT_CYCCNT +T062C 26389:753.251 - 0.083ms returns 1 (0x1) +T3F74 26389:755.829 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26389:755.866 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26389:757.115 Data: 00 00 80 00 +T3F74 26389:757.195 - 1.385ms returns 4 (0x4) +T3F74 26389:757.253 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26389:757.276 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26389:758.423 Data: 00 00 F0 01 +T3F74 26389:758.501 - 1.267ms returns 4 (0x4) +T3F74 26389:761.533 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26389:761.566 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26389:762.765 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26389:762.794 - 1.267ms returns 16 (0x10) +T3F74 26389:762.814 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26389:762.833 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26389:763.206 Data: 1E 00 00 00 +T3F74 26389:763.227 - 0.419ms returns 4 (0x4) +T3F74 26389:763.244 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26389:763.261 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26389:763.707 Data: 00 00 00 00 00 00 00 00 00 00 00 00 B7 01 00 00 ... +T3F74 26389:763.727 - 0.489ms returns 20 (0x14) +T3F74 26389:763.744 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26389:763.760 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26389:764.223 Data: 1F 03 00 00 +T3F74 26389:764.247 - 0.511ms returns 4 (0x4) +T3F74 26389:764.267 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26389:764.286 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26389:764.716 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26389:764.739 - 0.479ms returns 12 (0xC) +T3F74 26389:764.759 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26389:764.778 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26389:765.231 Data: 00 00 00 00 +T3F74 26389:765.254 - 0.503ms returns 4 (0x4) +T3F74 26389:765.274 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26389:765.293 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26389:765.713 Data: 00 00 00 00 +T3F74 26389:765.738 - 0.471ms returns 4 (0x4) +T3F74 26389:765.758 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26389:765.777 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26389:766.379 Data: 00 00 00 00 +T3F74 26389:766.414 - 0.664ms returns 4 (0x4) +T062C 26389:777.913 JLINK_IsHalted() +T062C 26389:778.963 - 1.068ms returns FALSE +T062C 26389:879.239 JLINK_HasError() +T062C 26389:879.282 JLINK_IsHalted() +T062C 26389:880.358 - 1.094ms returns FALSE +T062C 26389:980.574 JLINK_HasError() +T062C 26389:980.655 JLINK_IsHalted() +T062C 26389:981.904 - 1.267ms returns FALSE +T062C 26390:082.960 JLINK_HasError() +T062C 26390:083.001 JLINK_IsHalted() +T062C 26390:084.174 - 1.220ms returns FALSE +T062C 26390:185.189 JLINK_HasError() +T062C 26390:185.272 JLINK_IsHalted() +T062C 26390:186.578 - 1.323ms returns FALSE +T062C 26390:286.785 JLINK_HasError() +T062C 26390:286.867 JLINK_HasError() +T062C 26390:286.909 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26390:286.939 Data: 8D 12 74 01 +T062C 26390:286.963 Debug reg: DWT_CYCCNT +T062C 26390:286.985 - 0.083ms returns 1 (0x1) +T3F74 26390:289.428 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26390:289.474 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26390:290.620 Data: 00 00 80 00 +T3F74 26390:290.681 - 1.259ms returns 4 (0x4) +T3F74 26390:290.716 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26390:290.736 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26390:291.141 Data: 00 00 F0 01 +T3F74 26390:291.161 - 0.452ms returns 4 (0x4) +T3F74 26390:294.140 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26390:294.181 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26390:295.440 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26390:295.468 - 1.335ms returns 16 (0x10) +T3F74 26390:295.488 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26390:295.508 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26390:295.886 Data: 1E 00 00 00 +T3F74 26390:295.907 - 0.425ms returns 4 (0x4) +T3F74 26390:295.924 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26390:295.940 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26390:296.441 Data: 00 00 00 00 00 00 00 00 00 00 00 00 A3 00 00 00 ... +T3F74 26390:296.487 - 0.571ms returns 20 (0x14) +T3F74 26390:296.516 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26390:296.539 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26390:297.017 Data: 1F 03 00 00 +T3F74 26390:297.047 - 0.541ms returns 4 (0x4) +T3F74 26390:297.072 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26390:297.093 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26390:297.517 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26390:297.540 - 0.477ms returns 12 (0xC) +T3F74 26390:297.563 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26390:297.582 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26390:298.010 Data: 00 00 00 00 +T3F74 26390:298.031 - 0.474ms returns 4 (0x4) +T3F74 26390:298.048 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26390:298.064 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26390:298.526 Data: 00 00 00 00 +T3F74 26390:298.550 - 0.510ms returns 4 (0x4) +T3F74 26390:298.570 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26390:298.589 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26390:299.025 Data: 00 00 00 00 +T3F74 26390:299.048 - 0.485ms returns 4 (0x4) +T062C 26390:311.302 JLINK_IsHalted() +T062C 26390:312.411 - 1.342ms returns FALSE +T062C 26390:413.438 JLINK_HasError() +T062C 26390:413.514 JLINK_IsHalted() +T062C 26390:414.761 - 1.265ms returns FALSE +T062C 26390:514.962 JLINK_HasError() +T062C 26390:515.045 JLINK_IsHalted() +T062C 26390:516.283 - 1.279ms returns FALSE +T062C 26390:616.534 JLINK_HasError() +T062C 26390:616.608 JLINK_IsHalted() +T062C 26390:617.849 - 1.289ms returns FALSE +T062C 26390:718.098 JLINK_HasError() +T062C 26390:718.177 JLINK_IsHalted() +T062C 26390:719.429 - 1.293ms returns FALSE +T062C 26390:819.700 JLINK_HasError() +T062C 26390:819.780 JLINK_HasError() +T062C 26390:819.824 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26390:819.859 Data: 8D 12 74 01 +T062C 26390:819.880 Debug reg: DWT_CYCCNT +T062C 26390:819.898 - 0.081ms returns 1 (0x1) +T3F74 26390:822.330 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26390:822.362 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26390:823.532 Data: 00 00 80 00 +T3F74 26390:823.602 - 1.279ms returns 4 (0x4) +T3F74 26390:823.637 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26390:823.656 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26390:824.065 Data: 00 00 F0 01 +T3F74 26390:824.085 - 0.456ms returns 4 (0x4) +T3F74 26390:827.588 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26390:827.626 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26390:828.876 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26390:828.904 - 1.323ms returns 16 (0x10) +T3F74 26390:828.925 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26390:828.944 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26390:829.319 Data: 1F 00 00 00 +T3F74 26390:829.339 - 0.421ms returns 4 (0x4) +T3F74 26390:829.357 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26390:829.373 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26390:829.820 Data: 00 00 00 00 00 00 00 00 00 00 00 00 11 03 00 00 ... +T3F74 26390:829.840 - 0.490ms returns 20 (0x14) +T3F74 26390:829.857 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26390:829.873 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26390:830.319 Data: 1F 03 00 00 +T3F74 26390:830.339 - 0.488ms returns 4 (0x4) +T3F74 26390:830.356 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26390:830.372 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26390:830.819 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26390:830.839 - 0.489ms returns 12 (0xC) +T3F74 26390:830.856 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26390:830.872 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26390:831.318 Data: 00 00 00 00 +T3F74 26390:831.338 - 0.489ms returns 4 (0x4) +T3F74 26390:831.355 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26390:831.371 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26390:831.819 Data: 00 00 00 00 +T3F74 26390:831.839 - 0.490ms returns 4 (0x4) +T3F74 26390:831.856 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26390:831.878 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26390:832.317 Data: 00 00 00 00 +T3F74 26390:832.337 - 0.488ms returns 4 (0x4) +T062C 26390:851.635 JLINK_IsHalted() +T062C 26390:852.707 - 1.091ms returns FALSE +T062C 26390:953.494 JLINK_HasError() +T062C 26390:953.570 JLINK_IsHalted() +T062C 26390:954.701 - 1.139ms returns FALSE +T062C 26391:054.870 JLINK_HasError() +T062C 26391:054.953 JLINK_IsHalted() +T062C 26391:056.128 - 1.216ms returns FALSE +T062C 26391:156.880 JLINK_HasError() +T062C 26391:156.922 JLINK_IsHalted() +T062C 26391:158.036 - 1.130ms returns FALSE +T062C 26391:258.740 JLINK_HasError() +T062C 26391:258.770 JLINK_IsHalted() +T062C 26391:259.880 - 1.128ms returns FALSE +T062C 26391:360.081 JLINK_HasError() +T062C 26391:360.168 JLINK_HasError() +T062C 26391:360.214 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26391:360.264 Data: 8D 12 74 01 +T062C 26391:360.285 Debug reg: DWT_CYCCNT +T062C 26391:360.303 - 0.097ms returns 1 (0x1) +T3F74 26391:362.738 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26391:362.770 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26391:363.999 Data: 00 00 80 00 +T3F74 26391:364.032 - 1.302ms returns 4 (0x4) +T3F74 26391:364.071 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26391:364.094 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26391:364.508 Data: 00 00 F0 01 +T3F74 26391:364.532 - 0.468ms returns 4 (0x4) +T3F74 26391:367.546 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26391:367.584 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26391:368.871 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26391:368.905 - 1.367ms returns 16 (0x10) +T3F74 26391:368.929 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26391:368.952 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26391:369.383 Data: 1F 00 00 00 +T3F74 26391:369.418 - 0.496ms returns 4 (0x4) +T3F74 26391:369.442 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26391:369.468 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26391:369.993 Data: 00 00 00 00 00 00 00 00 00 00 00 00 D1 02 00 00 ... +T3F74 26391:370.013 - 0.577ms returns 20 (0x14) +T3F74 26391:370.030 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26391:370.047 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26391:370.501 Data: 1F 03 00 00 +T3F74 26391:370.521 - 0.497ms returns 4 (0x4) +T3F74 26391:370.553 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26391:370.569 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26391:371.004 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26391:371.028 - 0.483ms returns 12 (0xC) +T3F74 26391:371.052 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26391:371.071 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26391:371.508 Data: 00 00 00 00 +T3F74 26391:371.532 - 0.488ms returns 4 (0x4) +T3F74 26391:371.563 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26391:371.582 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26391:372.002 Data: 00 00 00 00 +T3F74 26391:372.026 - 0.471ms returns 4 (0x4) +T3F74 26391:372.049 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26391:372.067 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26391:372.506 Data: 00 00 00 00 +T3F74 26391:372.530 - 0.489ms returns 4 (0x4) +T062C 26391:384.245 JLINK_IsHalted() +T062C 26391:385.379 - 1.146ms returns FALSE +T062C 26391:486.165 JLINK_HasError() +T062C 26391:486.241 JLINK_IsHalted() +T062C 26391:487.352 - 1.130ms returns FALSE +T062C 26391:587.900 JLINK_HasError() +T062C 26391:587.977 JLINK_IsHalted() +T062C 26391:589.129 - 1.177ms returns FALSE +T062C 26391:689.336 JLINK_HasError() +T062C 26391:689.414 JLINK_IsHalted() +T062C 26391:690.702 - 1.330ms returns FALSE +T062C 26391:790.935 JLINK_HasError() +T062C 26391:791.021 JLINK_IsHalted() +T062C 26391:792.162 - 1.183ms returns FALSE +T062C 26391:892.470 JLINK_HasError() +T062C 26391:892.550 JLINK_HasError() +T062C 26391:892.590 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26391:892.615 Data: 8D 12 74 01 +T062C 26391:892.647 Debug reg: DWT_CYCCNT +T062C 26391:892.666 - 0.082ms returns 1 (0x1) +T3F74 26391:895.088 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26391:895.122 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26391:896.245 Data: 00 00 80 00 +T3F74 26391:896.283 - 1.213ms returns 4 (0x4) +T3F74 26391:896.348 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26391:896.401 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26391:896.940 Data: 00 00 F0 01 +T3F74 26391:896.965 - 0.624ms returns 4 (0x4) +T3F74 26391:900.123 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26391:900.151 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26391:901.318 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26391:901.343 - 1.228ms returns 16 (0x10) +T3F74 26391:901.365 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26391:901.385 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26391:901.810 Data: 1F 00 00 00 +T3F74 26391:901.834 - 0.483ms returns 4 (0x4) +T3F74 26391:901.858 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26391:901.874 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26391:902.427 Data: 00 00 00 00 00 00 00 00 00 00 00 00 25 02 00 00 ... +T3F74 26391:902.447 - 0.595ms returns 20 (0x14) +T3F74 26391:902.464 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26391:902.480 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26391:902.926 Data: 1F 03 00 00 +T3F74 26391:902.946 - 0.488ms returns 4 (0x4) +T3F74 26391:902.963 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26391:902.979 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26391:903.449 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26391:903.469 - 0.512ms returns 12 (0xC) +T3F74 26391:903.486 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26391:903.502 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26391:903.926 Data: 00 00 00 00 +T3F74 26391:903.946 - 0.467ms returns 4 (0x4) +T3F74 26391:903.963 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26391:903.979 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26391:904.425 Data: 00 00 00 00 +T3F74 26391:904.445 - 0.488ms returns 4 (0x4) +T3F74 26391:904.462 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26391:904.478 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26391:905.053 Data: 00 00 00 00 +T3F74 26391:905.077 - 0.623ms returns 4 (0x4) +T062C 26391:916.632 JLINK_IsHalted() +T062C 26391:917.686 - 1.072ms returns FALSE +T062C 26392:018.458 JLINK_HasError() +T062C 26392:018.534 JLINK_IsHalted() +T062C 26392:019.656 - 1.140ms returns FALSE +T062C 26392:120.814 JLINK_HasError() +T062C 26392:120.893 JLINK_IsHalted() +T062C 26392:122.063 - 1.198ms returns FALSE +T062C 26392:223.068 JLINK_HasError() +T062C 26392:223.114 JLINK_IsHalted() +T062C 26392:224.182 - 1.082ms returns FALSE +T062C 26392:324.386 JLINK_HasError() +T062C 26392:324.466 JLINK_IsHalted() +T062C 26392:325.748 - 1.324ms returns FALSE +T062C 26392:425.994 JLINK_HasError() +T062C 26392:426.075 JLINK_HasError() +T062C 26392:426.119 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26392:426.174 Data: 8D 12 74 01 +T062C 26392:426.195 Debug reg: DWT_CYCCNT +T062C 26392:426.213 - 0.100ms returns 1 (0x1) +T3F74 26392:429.087 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26392:429.125 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26392:430.246 Data: 00 00 80 00 +T3F74 26392:430.277 - 1.196ms returns 4 (0x4) +T3F74 26392:430.312 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26392:430.332 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26392:430.858 Data: 00 00 F0 01 +T3F74 26392:430.879 - 0.573ms returns 4 (0x4) +T3F74 26392:434.092 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26392:434.130 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26392:435.391 Data: 81 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +T3F74 26392:435.423 - 1.340ms returns 16 (0x10) +T3F74 26392:435.447 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26392:435.476 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26392:435.855 Data: 1E 00 00 00 +T3F74 26392:435.875 - 0.435ms returns 4 (0x4) +T3F74 26392:435.893 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26392:435.909 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26392:436.356 Data: 00 00 00 00 00 00 00 00 00 00 00 00 27 00 00 00 ... +T3F74 26392:436.376 - 0.490ms returns 20 (0x14) +T3F74 26392:436.393 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26392:436.410 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26392:436.854 Data: 1F 03 00 00 +T3F74 26392:436.875 - 0.488ms returns 4 (0x4) +T3F74 26392:436.892 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26392:436.908 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26392:437.355 Data: 00 00 00 00 00 00 00 00 00 00 00 00 +T3F74 26392:437.375 - 0.490ms returns 12 (0xC) +T3F74 26392:437.392 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26392:437.408 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26392:437.854 Data: 00 00 00 00 +T3F74 26392:437.874 - 0.488ms returns 4 (0x4) +T3F74 26392:437.891 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26392:437.907 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26392:438.427 Data: 00 00 00 00 +T3F74 26392:438.447 - 0.562ms returns 4 (0x4) +T3F74 26392:438.466 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26392:438.490 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26392:438.985 Data: 00 00 00 00 +T3F74 26392:439.009 - 0.550ms returns 4 (0x4) +T062C 26392:458.706 JLINK_IsHalted() +T062C 26392:459.800 - 1.112ms returns FALSE +T062C 26392:560.320 JLINK_HasError() +T062C 26392:560.402 JLINK_IsHalted() +T062C 26392:561.643 - 1.283ms returns FALSE +T062C 26392:662.699 JLINK_HasError() +T062C 26392:662.772 JLINK_IsHalted() +T062C 26392:664.096 - 1.342ms returns FALSE +T062C 26392:764.305 JLINK_HasError() +T062C 26392:764.383 JLINK_IsHalted() +T062C 26392:765.565 - 1.224ms returns FALSE +T062C 26392:866.061 JLINK_HasError() +T062C 26392:866.096 JLINK_IsHalted() +T062C 26392:867.243 - 1.165ms returns FALSE +T062C 26392:967.459 JLINK_HasError() +T062C 26392:967.542 JLINK_HasError() +T062C 26392:967.587 JLINK_ReadMemU32(0xE0001004, 0x1 Items) +T062C 26392:967.639 Data: 8D 12 74 01 +T062C 26392:967.659 Debug reg: DWT_CYCCNT +T062C 26392:967.678 - 0.098ms returns 1 (0x1) +T3F74 26392:970.123 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26392:970.156 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26392:979.734 failed +T3F74 26392:979.817 - 9.703ms returns -1 (0xFFFFFFFF) +T3F74 26392:979.855 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26392:979.880 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26392:988.828 failed +T3F74 26392:988.869 - 9.024ms returns -1 (0xFFFFFFFF) +T3F74 26392:988.900 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26392:988.928 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26392:997.858 failed +T3F74 26392:997.943 - 9.051ms returns -1 (0xFFFFFFFF) +T3F74 26392:997.982 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26392:998.009 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26393:006.851 failed +T3F74 26393:006.886 - 8.912ms returns -1 (0xFFFFFFFF) +T3F74 26393:006.911 JLINK_ReadMemEx(0x20000058, 0x2 Bytes, Flags = 0x02000000) +T3F74 26393:006.935 CPU_ReadMem(2 bytes @ 0x20000058) +T3F74 26393:015.646 failed +T3F74 26393:015.675 - 8.771ms returns -1 (0xFFFFFFFF) +T3F74 26393:015.696 JLINK_ReadMemEx(0x20000058, 0x1 Bytes, Flags = 0x02000000) +T3F74 26393:015.723 CPU_ReadMem(1 bytes @ 0x20000058) +T3F74 26393:024.646 failed +T3F74 26393:024.676 - 8.987ms returns -1 (0xFFFFFFFF) +T3F74 26393:025.209 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26393:025.236 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26393:034.901 failed +T3F74 26393:034.935 - 9.734ms returns -1 (0xFFFFFFFF) +T3F74 26393:034.957 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26393:034.980 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26393:043.999 failed +T3F74 26393:044.030 - 9.080ms returns -1 (0xFFFFFFFF) +T3F74 26393:044.050 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26393:044.070 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26393:052.963 failed +T3F74 26393:052.997 - 8.955ms returns -1 (0xFFFFFFFF) +T3F74 26393:053.022 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26393:053.045 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26393:062.099 failed +T3F74 26393:062.135 - 9.120ms returns -1 (0xFFFFFFFF) +T3F74 26393:062.160 JLINK_ReadMemEx(0x2000005C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26393:062.183 CPU_ReadMem(2 bytes @ 0x2000005C) +T3F74 26393:071.181 failed +T3F74 26393:071.257 - 9.106ms returns -1 (0xFFFFFFFF) +T3F74 26393:071.292 JLINK_ReadMemEx(0x2000005C, 0x1 Bytes, Flags = 0x02000000) +T3F74 26393:071.315 CPU_ReadMem(1 bytes @ 0x2000005C) +T3F74 26393:081.951 failed +T3F74 26393:081.984 - 10.702ms returns -1 (0xFFFFFFFF) +T3F74 26393:085.675 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26393:085.703 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26393:095.438 failed +T3F74 26393:095.467 - 9.798ms returns -1 (0xFFFFFFFF) +T3F74 26393:095.488 JLINK_ReadMemEx(0x40000800, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:095.508 CPU_ReadMem(4 bytes @ 0x40000800) +T3F74 26393:104.487 failed +T3F74 26393:104.517 - 9.035ms returns -1 (0xFFFFFFFF) +T3F74 26393:104.537 JLINK_ReadMemEx(0x40000804, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:104.556 CPU_ReadMem(4 bytes @ 0x40000804) +T3F74 26393:113.502 failed +T3F74 26393:113.532 - 9.001ms returns -1 (0xFFFFFFFF) +T3F74 26393:113.566 JLINK_ReadMemEx(0x40000808, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:113.586 CPU_ReadMem(4 bytes @ 0x40000808) +T3F74 26393:122.660 failed +T3F74 26393:122.693 - 9.135ms returns -1 (0xFFFFFFFF) +T3F74 26393:122.720 JLINK_ReadMemEx(0x4000080C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:122.743 CPU_ReadMem(4 bytes @ 0x4000080C) +T3F74 26393:131.513 failed +T3F74 26393:131.546 - 8.834ms returns -1 (0xFFFFFFFF) +T3F74 26393:131.574 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:131.597 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26393:140.437 failed +T3F74 26393:140.470 - 8.904ms returns -1 (0xFFFFFFFF) +T3F74 26393:140.506 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:140.529 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26393:149.485 failed +T3F74 26393:149.514 - 9.015ms returns -1 (0xFFFFFFFF) +T3F74 26393:149.548 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26393:149.568 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26393:158.474 failed +T3F74 26393:158.502 - 8.961ms returns -1 (0xFFFFFFFF) +T3F74 26393:158.536 JLINK_ReadMemEx(0x40000818, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:158.556 CPU_ReadMem(4 bytes @ 0x40000818) +T3F74 26393:167.483 failed +T3F74 26393:167.512 - 8.983ms returns -1 (0xFFFFFFFF) +T3F74 26393:167.546 JLINK_ReadMemEx(0x4000081C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:167.565 CPU_ReadMem(4 bytes @ 0x4000081C) +T3F74 26393:176.486 failed +T3F74 26393:176.515 - 8.976ms returns -1 (0xFFFFFFFF) +T3F74 26393:176.549 JLINK_ReadMemEx(0x40000820, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:176.569 CPU_ReadMem(4 bytes @ 0x40000820) +T3F74 26393:185.479 failed +T3F74 26393:185.508 - 8.965ms returns -1 (0xFFFFFFFF) +T3F74 26393:185.541 JLINK_ReadMemEx(0x40000824, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:185.561 CPU_ReadMem(4 bytes @ 0x40000824) +T3F74 26393:194.315 failed +T3F74 26393:194.345 - 8.810ms returns -1 (0xFFFFFFFF) +T3F74 26393:194.378 JLINK_ReadMemEx(0x40000828, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:194.398 CPU_ReadMem(4 bytes @ 0x40000828) +T3F74 26393:203.124 failed +T3F74 26393:203.157 - 8.787ms returns -1 (0xFFFFFFFF) +T3F74 26393:203.184 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:203.208 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26393:212.202 failed +T3F74 26393:212.240 - 9.064ms returns -1 (0xFFFFFFFF) +T3F74 26393:212.513 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:212.539 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26393:222.183 failed +T3F74 26393:222.223 - 9.718ms returns -1 (0xFFFFFFFF) +T3F74 26393:222.255 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26393:222.281 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26393:231.337 failed +T3F74 26393:231.379 - 9.132ms returns -1 (0xFFFFFFFF) +T3F74 26393:231.409 JLINK_ReadMemEx(0x40000834, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:231.436 CPU_ReadMem(4 bytes @ 0x40000834) +T3F74 26393:240.129 failed +T3F74 26393:240.172 - 8.770ms returns -1 (0xFFFFFFFF) +T3F74 26393:240.202 JLINK_ReadMemEx(0x40000838, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:240.229 CPU_ReadMem(4 bytes @ 0x40000838) +T3F74 26393:249.181 failed +T3F74 26393:249.224 - 9.029ms returns -1 (0xFFFFFFFF) +T3F74 26393:249.254 JLINK_ReadMemEx(0x4000083C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:249.339 CPU_ReadMem(4 bytes @ 0x4000083C) +T3F74 26393:258.271 failed +T3F74 26393:258.312 - 9.066ms returns -1 (0xFFFFFFFF) +T3F74 26393:258.344 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:258.370 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26393:267.269 failed +T3F74 26393:267.304 - 8.967ms returns -1 (0xFFFFFFFF) +T3F74 26393:267.341 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:267.364 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26393:276.244 failed +T3F74 26393:276.283 - 8.950ms returns -1 (0xFFFFFFFF) +T3F74 26393:276.322 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:276.350 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26393:285.238 failed +T3F74 26393:285.271 - 8.956ms returns -1 (0xFFFFFFFF) +T3F74 26393:285.297 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:285.320 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26393:294.111 failed +T3F74 26393:294.141 - 8.852ms returns -1 (0xFFFFFFFF) +T3F74 26393:294.176 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:294.197 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26393:303.177 failed +T3F74 26393:303.207 - 9.037ms returns -1 (0xFFFFFFFF) +T3F74 26393:303.240 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26393:303.260 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26393:312.210 failed +T3F74 26393:312.239 - 9.005ms returns -1 (0xFFFFFFFF) +T062C 26393:446.935 JLINK_IsHalted() +T062C 26393:472.909 - 26.003ms returns ERROR +T062C 26393:472.957 JLINK_HasError() +T062C 26393:472.980 JLINK_Halt() +T062C 26393:486.953 CPU could not be halted +T062C 26393:486.983 - 14.009ms returns 0x01 +T062C 26393:487.015 JLINK_IsHalted() +T062C 26393:513.192 - 26.229ms returns ERROR +T062C 26393:513.271 JLINK_IsHalted() +T062C 26393:539.539 - 26.316ms returns ERROR +T062C 26393:539.627 JLINK_IsHalted() +T062C 26393:565.781 - 26.195ms returns ERROR +T062C 26393:565.872 JLINK_HasError() +T062C 26393:565.890 JLINK_ReadReg(R15 (PC)) +T062C 26393:591.996 CPU is running +T062C 26393:592.069 + ***** Error: +T062C 26393:592.091 Cannot read register 15 (R15) while CPU is running +T062C 26393:592.113 - 26.231ms returns 0x00000000 +T062C 26393:592.279 JLINK_ReadReg(XPSR) +T062C 26393:618.436 CPU is running +T062C 26393:618.498 + ***** Error: +T062C 26393:618.517 Cannot read register 16 (XPSR) while CPU is running +T062C 26393:618.537 - 26.264ms returns 0x00000000 +T062C 26393:618.784 JLINK_HasError() +T062C 26393:618.805 JLINK_HasError() +T062C 26393:618.823 JLINK_ReadMemU32(0xE000ED30, 0x1 Items) +T062C 26393:618.848 CPU_ReadMem(4 bytes @ 0xE000ED30) +T062C 26393:628.571 failed +T062C 26393:628.607 - 9.791ms returns -1 (0xFFFFFFFF) +T062C 26393:628.688 JLINK_HasError() +T062C 26393:628.708 JLINK_ReadReg(R0) +T062C 26393:654.013 CPU is running +T062C 26393:654.045 + ***** Error: +T062C 26393:654.064 Cannot read register 0 (R0) while CPU is running +T062C 26393:654.083 - 25.381ms returns 0x00000000 +T062C 26393:654.325 JLINK_ReadReg(R1) +T062C 26393:680.245 CPU is running +T062C 26393:680.287 + ***** Error: +T062C 26393:680.309 Cannot read register 1 (R1) while CPU is running +T062C 26393:680.331 - 26.014ms returns 0x00000000 +T062C 26393:680.500 JLINK_ReadReg(R2) +T062C 26393:706.508 CPU is running +T062C 26393:706.541 + ***** Error: +T062C 26393:706.563 Cannot read register 2 (R2) while CPU is running +T062C 26393:706.586 - 26.093ms returns 0x00000000 +T062C 26393:706.704 JLINK_ReadReg(R3) +T062C 26393:732.738 CPU is running +T062C 26393:732.774 + ***** Error: +T062C 26393:732.796 Cannot read register 3 (R3) while CPU is running +T062C 26393:732.819 - 26.123ms returns 0x00000000 +T062C 26393:732.989 JLINK_ReadReg(R4) +T062C 26393:758.985 CPU is running +T062C 26393:759.030 + ***** Error: +T062C 26393:759.052 Cannot read register 4 (R4) while CPU is running +T062C 26393:759.074 - 26.093ms returns 0x00000000 +T062C 26393:759.918 JLINK_ReadReg(R5) +T062C 26393:785.908 CPU is running +T062C 26393:785.962 + ***** Error: +T062C 26393:785.992 Cannot read register 5 (R5) while CPU is running +T062C 26393:786.021 - 26.114ms returns 0x00000000 +T062C 26393:788.909 JLINK_ReadReg(R6) +T062C 26393:814.992 CPU is running +T062C 26393:815.043 + ***** Error: +T062C 26393:815.065 Cannot read register 6 (R6) while CPU is running +T062C 26393:815.088 - 26.187ms returns 0x00000000 +T062C 26393:816.012 JLINK_ReadReg(R7) +T062C 26393:841.952 CPU is running +T062C 26393:841.998 + ***** Error: +T062C 26393:842.024 Cannot read register 7 (R7) while CPU is running +T062C 26393:842.047 - 26.043ms returns 0x00000000 +T062C 26393:844.164 JLINK_ReadReg(R8) +T062C 26393:870.263 CPU is running +T062C 26393:870.310 + ***** Error: +T062C 26393:870.336 Cannot read register 8 (R8) while CPU is running +T062C 26393:870.359 - 26.204ms returns 0x00000000 +T062C 26393:870.531 JLINK_ReadReg(R9) +T062C 26393:896.574 CPU is running +T062C 26393:896.624 + ***** Error: +T062C 26393:896.646 Cannot read register 9 (R9) while CPU is running +T062C 26393:896.669 - 26.146ms returns 0x00000000 +T062C 26393:900.445 JLINK_ReadReg(R10) +T062C 26393:926.491 CPU is running +T062C 26393:926.532 + ***** Error: +T062C 26393:926.551 Cannot read register 10 (R10) while CPU is running +T062C 26393:926.570 - 26.132ms returns 0x00000000 +T062C 26393:926.927 JLINK_ReadReg(R11) +T062C 26393:952.995 CPU is running +T062C 26393:953.043 + ***** Error: +T062C 26393:953.066 Cannot read register 11 (R11) while CPU is running +T062C 26393:953.089 - 26.170ms returns 0x00000000 +T062C 26393:956.249 JLINK_ReadReg(R12) +T062C 26393:982.373 CPU is running +T062C 26393:982.416 + ***** Error: +T062C 26393:982.435 Cannot read register 12 (R12) while CPU is running +T062C 26393:982.455 - 26.212ms returns 0x00000000 +T062C 26393:982.699 JLINK_ReadReg(R13 (SP)) +T062C 26394:008.756 CPU is running +T062C 26394:008.839 + ***** Error: +T062C 26394:008.861 Cannot read register 13 (R13) while CPU is running +T062C 26394:008.884 - 26.193ms returns 0x00000000 +T062C 26394:012.580 JLINK_ReadReg(R14) +T062C 26394:038.550 CPU is running +T062C 26394:038.586 + ***** Error: +T062C 26394:038.608 Cannot read register 14 (R14) while CPU is running +T062C 26394:038.632 - 26.067ms returns 0x00000000 +T062C 26394:038.849 JLINK_ReadReg(R15 (PC)) +T062C 26394:064.800 CPU is running +T062C 26394:064.845 + ***** Error: +T062C 26394:064.867 Cannot read register 15 (R15) while CPU is running +T062C 26394:064.890 - 26.048ms returns 0x00000000 +T062C 26394:068.433 JLINK_ReadReg(XPSR) +T062C 26394:094.473 CPU is running +T062C 26394:094.513 + ***** Error: +T062C 26394:094.532 Cannot read register 16 (XPSR) while CPU is running +T062C 26394:094.552 - 26.125ms returns 0x00000000 +T062C 26394:094.770 JLINK_ReadReg(MSP) +T062C 26394:120.797 CPU is running +T062C 26394:120.838 + ***** Error: +T062C 26394:120.860 Cannot read register 17 (MSP) while CPU is running +T062C 26394:120.882 - 26.121ms returns 0x00000000 +T062C 26394:124.292 JLINK_ReadReg(PSP) +T062C 26394:150.363 CPU is running +T062C 26394:150.402 + ***** Error: +T062C 26394:150.420 Cannot read register 18 (PSP) while CPU is running +T062C 26394:150.440 - 26.154ms returns 0x00000000 +T062C 26394:150.707 JLINK_ReadReg(CFBP) +T062C 26394:176.662 CPU is running +T062C 26394:176.708 + ***** Error: +T062C 26394:176.731 Cannot read register 20 (CFBP) while CPU is running +T062C 26394:176.754 - 26.055ms returns 0x00000000 +T062C 26394:180.070 JLINK_ReadReg(FPSCR) +T062C 26394:206.097 CPU is running +T062C 26394:206.139 + ***** Error: +T062C 26394:206.158 Cannot read register 32 (FPSCR) while CPU is running +T062C 26394:206.178 - 26.114ms returns 0x00000000 +T062C 26394:206.423 JLINK_ReadReg(FPS0) +T062C 26394:232.559 CPU is running +T062C 26394:232.609 + ***** Error: +T062C 26394:232.640 Cannot read register 33 (FPS0) while CPU is running +T062C 26394:232.670 - 26.256ms returns 0x00000000 +T062C 26394:237.414 JLINK_ReadReg(FPS1) +T062C 26394:263.415 CPU is running +T062C 26394:263.460 + ***** Error: +T062C 26394:263.483 Cannot read register 34 (FPS1) while CPU is running +T062C 26394:263.507 - 26.101ms returns 0x00000000 +T062C 26394:263.714 JLINK_ReadReg(FPS2) +T062C 26394:289.655 CPU is running +T062C 26394:289.702 + ***** Error: +T062C 26394:289.725 Cannot read register 35 (FPS2) while CPU is running +T062C 26394:289.751 - 26.045ms returns 0x00000000 +T062C 26394:293.252 JLINK_ReadReg(FPS3) +T062C 26394:319.281 CPU is running +T062C 26394:319.332 + ***** Error: +T062C 26394:319.355 Cannot read register 36 (FPS3) while CPU is running +T062C 26394:319.379 - 26.136ms returns 0x00000000 +T062C 26394:320.094 JLINK_ReadReg(FPS4) +T062C 26394:346.162 CPU is running +T062C 26394:346.210 + ***** Error: +T062C 26394:346.233 Cannot read register 37 (FPS4) while CPU is running +T062C 26394:346.257 - 26.171ms returns 0x00000000 +T062C 26394:348.551 JLINK_ReadReg(FPS5) +T062C 26394:374.538 CPU is running +T062C 26394:374.588 + ***** Error: +T062C 26394:374.610 Cannot read register 38 (FPS5) while CPU is running +T062C 26394:374.634 - 26.096ms returns 0x00000000 +T062C 26394:374.815 JLINK_ReadReg(FPS6) +T062C 26394:400.933 CPU is running +T062C 26394:400.983 + ***** Error: +T062C 26394:401.008 Cannot read register 39 (FPS6) while CPU is running +T062C 26394:401.031 - 26.224ms returns 0x00000000 +T062C 26394:401.194 JLINK_ReadReg(FPS7) +T062C 26394:427.324 CPU is running +T062C 26394:427.363 + ***** Error: +T062C 26394:427.385 Cannot read register 40 (FPS7) while CPU is running +T062C 26394:427.408 - 26.221ms returns 0x00000000 +T062C 26394:427.521 JLINK_ReadReg(FPS8) +T062C 26394:453.534 CPU is running +T062C 26394:453.573 + ***** Error: +T062C 26394:453.595 Cannot read register 41 (FPS8) while CPU is running +T062C 26394:453.618 - 26.106ms returns 0x00000000 +T062C 26394:453.791 JLINK_ReadReg(FPS9) +T062C 26394:479.942 CPU is running +T062C 26394:480.029 + ***** Error: +T062C 26394:480.051 Cannot read register 42 (FPS9) while CPU is running +T062C 26394:480.074 - 26.291ms returns 0x00000000 +T062C 26394:480.198 JLINK_ReadReg(FPS10) +T062C 26394:506.115 CPU is running +T062C 26394:506.159 + ***** Error: +T062C 26394:506.182 Cannot read register 43 (FPS10) while CPU is running +T062C 26394:506.205 - 26.015ms returns 0x00000000 +T062C 26394:507.971 JLINK_ReadReg(FPS11) +T062C 26394:534.185 CPU is running +T062C 26394:534.249 + ***** Error: +T062C 26394:534.268 Cannot read register 44 (FPS11) while CPU is running +T062C 26394:534.287 - 26.323ms returns 0x00000000 +T062C 26394:534.531 JLINK_ReadReg(FPS12) +T062C 26394:560.569 CPU is running +T062C 26394:560.617 + ***** Error: +T062C 26394:560.640 Cannot read register 45 (FPS12) while CPU is running +T062C 26394:560.663 - 26.140ms returns 0x00000000 +T062C 26394:564.241 JLINK_ReadReg(FPS13) +T062C 26394:590.581 CPU is running +T062C 26394:590.653 + ***** Error: +T062C 26394:590.675 Cannot read register 46 (FPS13) while CPU is running +T062C 26394:590.697 - 26.473ms returns 0x00000000 +T062C 26394:590.817 JLINK_ReadReg(FPS14) +T062C 26394:616.969 CPU is running +T062C 26394:617.000 + ***** Error: +T062C 26394:617.019 Cannot read register 47 (FPS14) while CPU is running +T062C 26394:617.038 - 26.227ms returns 0x00000000 +T062C 26394:617.216 JLINK_ReadReg(FPS15) +T062C 26394:643.458 CPU is running +T062C 26394:643.500 + ***** Error: +T062C 26394:643.522 Cannot read register 48 (FPS15) while CPU is running +T062C 26394:643.545 - 26.337ms returns 0x00000000 +T062C 26394:643.718 JLINK_ReadReg(FPS16) +T062C 26394:669.947 CPU is running +T062C 26394:669.984 + ***** Error: +T062C 26394:670.006 Cannot read register 49 (FPS16) while CPU is running +T062C 26394:670.028 - 26.318ms returns 0x00000000 +T062C 26394:670.199 JLINK_ReadReg(FPS17) +T062C 26394:696.401 CPU is running +T062C 26394:696.473 + ***** Error: +T062C 26394:696.492 Cannot read register 50 (FPS17) while CPU is running +T062C 26394:696.511 - 26.319ms returns 0x00000000 +T062C 26394:696.757 JLINK_ReadReg(FPS18) +T062C 26394:722.902 CPU is running +T062C 26394:722.967 + ***** Error: +T062C 26394:722.986 Cannot read register 51 (FPS18) while CPU is running +T062C 26394:723.005 - 26.254ms returns 0x00000000 +T062C 26394:723.246 JLINK_ReadReg(FPS19) +T062C 26394:749.289 CPU is running +T062C 26394:749.329 + ***** Error: +T062C 26394:749.351 Cannot read register 52 (FPS19) while CPU is running +T062C 26394:749.376 - 26.137ms returns 0x00000000 +T062C 26394:749.624 JLINK_ReadReg(FPS20) +T062C 26394:775.642 CPU is running +T062C 26394:775.672 + ***** Error: +T062C 26394:775.691 Cannot read register 53 (FPS20) while CPU is running +T062C 26394:775.710 - 26.092ms returns 0x00000000 +T062C 26394:775.948 JLINK_ReadReg(FPS21) +T062C 26394:802.006 CPU is running +T062C 26394:802.046 + ***** Error: +T062C 26394:802.069 Cannot read register 54 (FPS21) while CPU is running +T062C 26394:802.091 - 26.151ms returns 0x00000000 +T062C 26394:803.120 JLINK_ReadReg(FPS22) +T062C 26394:829.266 CPU is running +T062C 26394:829.329 + ***** Error: +T062C 26394:829.349 Cannot read register 55 (FPS22) while CPU is running +T062C 26394:829.368 - 26.255ms returns 0x00000000 +T062C 26394:829.618 JLINK_ReadReg(FPS23) +T062C 26394:855.575 CPU is running +T062C 26394:855.608 + ***** Error: +T062C 26394:855.630 Cannot read register 56 (FPS23) while CPU is running +T062C 26394:855.653 - 26.042ms returns 0x00000000 +T062C 26394:855.769 JLINK_ReadReg(FPS24) +T062C 26394:881.055 CPU is running +T062C 26394:881.093 + ***** Error: +T062C 26394:881.116 Cannot read register 57 (FPS24) while CPU is running +T062C 26394:881.139 - 25.377ms returns 0x00000000 +T062C 26394:884.528 JLINK_ReadReg(FPS25) +T062C 26394:910.701 CPU is running +T062C 26394:910.773 + ***** Error: +T062C 26394:910.795 Cannot read register 58 (FPS25) while CPU is running +T062C 26394:910.818 - 26.298ms returns 0x00000000 +T062C 26394:910.906 JLINK_ReadReg(FPS26) +T062C 26394:937.285 CPU is running +T062C 26394:937.321 + ***** Error: +T062C 26394:937.344 Cannot read register 59 (FPS26) while CPU is running +T062C 26394:937.367 - 26.468ms returns 0x00000000 +T062C 26394:937.473 JLINK_ReadReg(FPS27) +T062C 26394:963.617 CPU is running +T062C 26394:963.682 + ***** Error: +T062C 26394:963.701 Cannot read register 60 (FPS27) while CPU is running +T062C 26394:963.720 - 26.254ms returns 0x00000000 +T062C 26394:963.958 JLINK_ReadReg(FPS28) +T062C 26394:990.099 CPU is running +T062C 26394:990.180 + ***** Error: +T062C 26394:990.233 Cannot read register 61 (FPS28) while CPU is running +T062C 26394:990.299 - 26.348ms returns 0x00000000 +T062C 26394:990.484 JLINK_ReadReg(FPS29) +T062C 26395:016.410 CPU is running +T062C 26395:016.438 + ***** Error: +T062C 26395:016.457 Cannot read register 62 (FPS29) while CPU is running +T062C 26395:016.476 - 25.998ms returns 0x00000000 +T062C 26395:022.126 JLINK_ReadReg(FPS30) +T062C 26395:048.113 CPU is running +T062C 26395:048.150 + ***** Error: +T062C 26395:048.181 Cannot read register 63 (FPS30) while CPU is running +T062C 26395:048.206 - 26.088ms returns 0x00000000 +T062C 26395:048.318 JLINK_ReadReg(FPS31) +T062C 26395:074.278 CPU is running +T062C 26395:074.314 + ***** Error: +T062C 26395:074.336 Cannot read register 64 (FPS31) while CPU is running +T062C 26395:074.358 - 26.048ms returns 0x00000000 +T3F74 26395:076.570 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26395:076.607 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26395:086.230 failed +T3F74 26395:086.260 - 9.697ms returns -1 (0xFFFFFFFF) +T3F74 26395:086.279 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26395:086.299 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26395:095.133 failed +T3F74 26395:095.166 - 8.895ms returns -1 (0xFFFFFFFF) +T3F74 26395:095.188 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26395:095.211 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26395:104.212 failed +T3F74 26395:104.241 - 9.060ms returns -1 (0xFFFFFFFF) +T3F74 26395:104.273 JLINK_ReadMemEx(0x20000058, 0x4 Bytes, Flags = 0x02000000) +T3F74 26395:104.292 CPU_ReadMem(4 bytes @ 0x20000058) +T3F74 26395:113.223 failed +T3F74 26395:113.252 - 8.987ms returns -1 (0xFFFFFFFF) +T3F74 26395:113.285 JLINK_ReadMemEx(0x20000058, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:113.305 CPU_ReadMem(2 bytes @ 0x20000058) +T3F74 26395:122.221 failed +T3F74 26395:122.251 - 8.972ms returns -1 (0xFFFFFFFF) +T3F74 26395:122.272 JLINK_ReadMemEx(0x20000058, 0x1 Bytes, Flags = 0x02000000) +T3F74 26395:122.293 CPU_ReadMem(1 bytes @ 0x20000058) +T3F74 26395:131.222 failed +T3F74 26395:131.251 - 8.986ms returns -1 (0xFFFFFFFF) +T3F74 26395:131.733 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26395:131.762 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26395:141.351 failed +T3F74 26395:141.426 - 9.700ms returns -1 (0xFFFFFFFF) +T3F74 26395:141.448 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26395:141.470 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26395:150.469 failed +T3F74 26395:150.498 - 9.057ms returns -1 (0xFFFFFFFF) +T3F74 26395:150.516 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26395:150.536 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26395:159.310 failed +T3F74 26395:159.344 - 8.835ms returns -1 (0xFFFFFFFF) +T3F74 26395:159.372 JLINK_ReadMemEx(0x2000005C, 0x4 Bytes, Flags = 0x02000000) +T3F74 26395:159.395 CPU_ReadMem(4 bytes @ 0x2000005C) +T3F74 26395:168.249 failed +T3F74 26395:168.282 - 8.919ms returns -1 (0xFFFFFFFF) +T3F74 26395:168.307 JLINK_ReadMemEx(0x2000005C, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:168.335 CPU_ReadMem(2 bytes @ 0x2000005C) +T3F74 26395:177.328 failed +T3F74 26395:177.357 - 9.057ms returns -1 (0xFFFFFFFF) +T3F74 26395:177.389 JLINK_ReadMemEx(0x2000005C, 0x1 Bytes, Flags = 0x02000000) +T3F74 26395:177.409 CPU_ReadMem(1 bytes @ 0x2000005C) +T3F74 26395:186.237 failed +T3F74 26395:186.271 - 8.890ms returns -1 (0xFFFFFFFF) +T3F74 26395:188.191 JLINK_ReadMemEx(0x40000800, 0x10 Bytes, Flags = 0x02000004) +T3F74 26395:188.216 CPU_ReadMem(16 bytes @ 0x40000800) +T3F74 26395:197.826 failed +T3F74 26395:197.855 - 9.671ms returns -1 (0xFFFFFFFF) +T3F74 26395:197.876 JLINK_ReadMemEx(0x40000800, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:197.895 CPU_ReadMem(4 bytes @ 0x40000800) +T3F74 26395:206.849 failed +T3F74 26395:206.878 - 9.009ms returns -1 (0xFFFFFFFF) +T3F74 26395:206.898 JLINK_ReadMemEx(0x40000804, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:206.917 CPU_ReadMem(4 bytes @ 0x40000804) +T3F74 26395:215.823 failed +T3F74 26395:215.853 - 8.961ms returns -1 (0xFFFFFFFF) +T3F74 26395:215.886 JLINK_ReadMemEx(0x40000808, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:215.906 CPU_ReadMem(4 bytes @ 0x40000808) +T3F74 26395:224.800 failed +T3F74 26395:224.833 - 8.955ms returns -1 (0xFFFFFFFF) +T3F74 26395:224.859 JLINK_ReadMemEx(0x4000080C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:224.883 CPU_ReadMem(4 bytes @ 0x4000080C) +T3F74 26395:233.850 failed +T3F74 26395:233.886 - 9.034ms returns -1 (0xFFFFFFFF) +T3F74 26395:233.920 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:233.940 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26395:242.802 failed +T3F74 26395:242.886 - 8.974ms returns -1 (0xFFFFFFFF) +T3F74 26395:242.912 JLINK_ReadMemEx(0x40000810, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:242.936 CPU_ReadMem(4 bytes @ 0x40000810) +T3F74 26395:251.851 failed +T3F74 26395:251.880 - 8.974ms returns -1 (0xFFFFFFFF) +T3F74 26395:251.912 JLINK_ReadMemEx(0x40000818, 0x14 Bytes, Flags = 0x02000004) +T3F74 26395:251.932 CPU_ReadMem(20 bytes @ 0x40000818) +T3F74 26395:260.831 failed +T3F74 26395:260.859 - 8.954ms returns -1 (0xFFFFFFFF) +T3F74 26395:260.882 JLINK_ReadMemEx(0x40000818, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:260.907 CPU_ReadMem(4 bytes @ 0x40000818) +T3F74 26395:269.819 failed +T3F74 26395:269.855 - 8.981ms returns -1 (0xFFFFFFFF) +T3F74 26395:269.891 JLINK_ReadMemEx(0x4000081C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:269.914 CPU_ReadMem(4 bytes @ 0x4000081C) +T3F74 26395:278.904 failed +T3F74 26395:278.937 - 9.054ms returns -1 (0xFFFFFFFF) +T3F74 26395:278.964 JLINK_ReadMemEx(0x40000820, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:278.987 CPU_ReadMem(4 bytes @ 0x40000820) +T3F74 26395:287.948 failed +T3F74 26395:287.978 - 9.021ms returns -1 (0xFFFFFFFF) +T3F74 26395:288.000 JLINK_ReadMemEx(0x40000824, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:288.022 CPU_ReadMem(4 bytes @ 0x40000824) +T3F74 26395:297.037 failed +T3F74 26395:297.066 - 9.072ms returns -1 (0xFFFFFFFF) +T3F74 26395:297.097 JLINK_ReadMemEx(0x40000828, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:297.117 CPU_ReadMem(4 bytes @ 0x40000828) +T3F74 26395:305.852 failed +T3F74 26395:305.885 - 8.795ms returns -1 (0xFFFFFFFF) +T3F74 26395:305.912 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:305.935 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26395:314.943 failed +T3F74 26395:314.972 - 9.067ms returns -1 (0xFFFFFFFF) +T3F74 26395:314.995 JLINK_ReadMemEx(0x4000082C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:315.016 CPU_ReadMem(4 bytes @ 0x4000082C) +T3F74 26395:323.933 failed +T3F74 26395:323.963 - 8.975ms returns -1 (0xFFFFFFFF) +T3F74 26395:323.996 JLINK_ReadMemEx(0x40000834, 0xC Bytes, Flags = 0x02000004) +T3F74 26395:324.016 CPU_ReadMem(12 bytes @ 0x40000834) +T3F74 26395:332.945 failed +T3F74 26395:332.974 - 8.985ms returns -1 (0xFFFFFFFF) +T3F74 26395:333.006 JLINK_ReadMemEx(0x40000834, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:333.026 CPU_ReadMem(4 bytes @ 0x40000834) +T3F74 26395:341.778 failed +T3F74 26395:341.807 - 8.808ms returns -1 (0xFFFFFFFF) +T3F74 26395:341.838 JLINK_ReadMemEx(0x40000838, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:341.858 CPU_ReadMem(4 bytes @ 0x40000838) +T3F74 26395:350.817 failed +T3F74 26395:350.847 - 9.015ms returns -1 (0xFFFFFFFF) +T3F74 26395:350.869 JLINK_ReadMemEx(0x4000083C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:350.891 CPU_ReadMem(4 bytes @ 0x4000083C) +T3F74 26395:359.785 failed +T3F74 26395:359.820 - 8.959ms returns -1 (0xFFFFFFFF) +T3F74 26395:359.859 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:359.883 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26395:368.802 failed +T3F74 26395:368.885 - 9.034ms returns -1 (0xFFFFFFFF) +T3F74 26395:368.924 JLINK_ReadMemEx(0x40000840, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:368.950 CPU_ReadMem(4 bytes @ 0x40000840) +T3F74 26395:377.938 failed +T3F74 26395:378.022 - 9.106ms returns -1 (0xFFFFFFFF) +T3F74 26395:378.064 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:378.090 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26395:387.726 failed +T3F74 26395:387.768 - 9.712ms returns -1 (0xFFFFFFFF) +T3F74 26395:387.799 JLINK_ReadMemEx(0x40000848, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:387.824 CPU_ReadMem(4 bytes @ 0x40000848) +T3F74 26395:396.809 failed +T3F74 26395:396.891 - 9.100ms returns -1 (0xFFFFFFFF) +T3F74 26395:396.932 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:396.970 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26395:406.614 failed +T3F74 26395:406.654 - 9.730ms returns -1 (0xFFFFFFFF) +T3F74 26395:406.694 JLINK_ReadMemEx(0x4000084C, 0x4 Bytes, Flags = 0x02000004) +T3F74 26395:406.720 CPU_ReadMem(4 bytes @ 0x4000084C) +T3F74 26395:415.472 failed +T3F74 26395:415.511 - 8.825ms returns -1 (0xFFFFFFFF) +T3F74 26395:422.927 JLINK_ReadMemEx(0x00000000, 0x3C Bytes, Flags = 0x02000000) +T3F74 26395:422.961 CPU_ReadMem(4 bytes @ 0x40023844) +T3F74 26395:432.386 CPU_ReadMem(60 bytes @ 0x08000000) +T3F74 26395:441.222 failed +T3F74 26395:441.256 - 18.337ms returns -1 (0xFFFFFFFF) +T3F74 26395:441.292 JLINK_ReadMemEx(0x00000000, 0x3C Bytes, Flags = 0x02000000) +T3F74 26395:441.314 CPU_ReadMem(60 bytes @ 0x08000000) +T3F74 26395:450.126 failed +T3F74 26395:450.155 - 8.869ms returns -1 (0xFFFFFFFF) +T3F74 26395:450.186 JLINK_ReadMemEx(0x00000000, 0x10 Bytes, Flags = 0x02000000) +T3F74 26395:450.205 CPU_ReadMem(16 bytes @ 0x08000000) +T3F74 26395:459.179 failed +T3F74 26395:459.208 - 9.028ms returns -1 (0xFFFFFFFF) +T3F74 26395:459.240 JLINK_ReadMemEx(0x00000000, 0x4 Bytes, Flags = 0x02000000) +T3F74 26395:459.258 CPU_ReadMem(4 bytes @ 0x08000000) +T3F74 26395:468.178 failed +T3F74 26395:468.207 - 8.974ms returns -1 (0xFFFFFFFF) +T3F74 26395:468.239 JLINK_ReadMemEx(0x00000000, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:468.257 CPU_ReadMem(2 bytes @ 0x08000000) +T3F74 26395:477.167 failed +T3F74 26395:477.197 - 8.965ms returns -1 (0xFFFFFFFF) +T3F74 26395:477.229 JLINK_ReadMemEx(0x00000000, 0x1 Bytes, Flags = 0x02000000) +T3F74 26395:477.247 CPU_ReadMem(1 bytes @ 0x08000000) +T3F74 26395:486.180 failed +T3F74 26395:486.209 - 8.987ms returns -1 (0xFFFFFFFF) +T3F74 26395:486.242 JLINK_ReadMemEx(0x00000000, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:486.261 CPU_ReadMem(2 bytes @ 0x08000000) +T3F74 26395:495.172 failed +T3F74 26395:495.202 - 8.966ms returns -1 (0xFFFFFFFF) +T3F74 26395:495.233 JLINK_ReadMemEx(0x00000000, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:495.252 CPU_ReadMem(2 bytes @ 0x08000000) +T3F74 26395:504.172 failed +T3F74 26395:504.202 - 8.975ms returns -1 (0xFFFFFFFF) +T3F74 26395:504.234 JLINK_ReadMemEx(0x00000000, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:504.253 CPU_ReadMem(2 bytes @ 0x08000000) +T3F74 26395:513.266 failed +T3F74 26395:513.350 - 9.124ms returns -1 (0xFFFFFFFF) +T3F74 26395:513.375 JLINK_ReadMemEx(0x00000000, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:513.397 CPU_ReadMem(2 bytes @ 0x08000000) +T3F74 26395:522.198 failed +T3F74 26395:522.231 - 8.864ms returns -1 (0xFFFFFFFF) +T3F74 26395:522.256 JLINK_ReadMemEx(0x00000000, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:522.278 CPU_ReadMem(2 bytes @ 0x08000000) +T3F74 26395:531.160 failed +T3F74 26395:531.190 - 8.940ms returns -1 (0xFFFFFFFF) +T3F74 26395:531.211 JLINK_ReadMemEx(0x00000000, 0x1 Bytes, Flags = 0x02000000) +T3F74 26395:531.233 CPU_ReadMem(1 bytes @ 0x08000000) +T3F74 26395:540.168 failed +T3F74 26395:540.197 - 8.993ms returns -1 (0xFFFFFFFF) +T3F74 26395:540.382 JLINK_ReadMemEx(0x00000002, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:540.408 CPU_ReadMem(2 bytes @ 0x08000002) +T3F74 26395:549.878 failed +T3F74 26395:549.908 - 9.533ms returns -1 (0xFFFFFFFF) +T3F74 26395:549.927 JLINK_ReadMemEx(0x00000002, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:549.945 CPU_ReadMem(2 bytes @ 0x08000002) +T3F74 26395:558.891 failed +T3F74 26395:558.925 - 9.006ms returns -1 (0xFFFFFFFF) +T3F74 26395:558.947 JLINK_ReadMemEx(0x00000002, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:558.970 CPU_ReadMem(2 bytes @ 0x08000002) +T3F74 26395:567.915 failed +T3F74 26395:567.944 - 9.004ms returns -1 (0xFFFFFFFF) +T3F74 26395:567.975 JLINK_ReadMemEx(0x00000002, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:567.994 CPU_ReadMem(2 bytes @ 0x08000002) +T3F74 26395:576.969 failed +T3F74 26395:577.012 - 9.048ms returns -1 (0xFFFFFFFF) +T3F74 26395:577.045 JLINK_ReadMemEx(0x00000002, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:577.102 CPU_ReadMem(2 bytes @ 0x08000002) +T3F74 26395:586.786 failed +T3F74 26395:586.815 - 9.777ms returns -1 (0xFFFFFFFF) +T3F74 26395:586.836 JLINK_ReadMemEx(0x00000002, 0x1 Bytes, Flags = 0x02000000) +T3F74 26395:586.864 CPU_ReadMem(1 bytes @ 0x08000002) +T3F74 26395:595.750 failed +T3F74 26395:595.784 - 8.955ms returns -1 (0xFFFFFFFF) +T3F74 26395:595.842 JLINK_ReadMemEx(0x00000002, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:595.864 CPU_ReadMem(2 bytes @ 0x08000002) +T3F74 26395:604.771 failed +T3F74 26395:604.800 - 8.965ms returns -1 (0xFFFFFFFF) +T3F74 26395:604.821 JLINK_ReadMemEx(0x00000002, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:604.841 CPU_ReadMem(2 bytes @ 0x08000002) +T3F74 26395:613.800 failed +T3F74 26395:613.829 - 9.015ms returns -1 (0xFFFFFFFF) +T3F74 26395:613.850 JLINK_ReadMemEx(0x00000002, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:613.873 CPU_ReadMem(2 bytes @ 0x08000002) +T3F74 26395:623.878 failed +T3F74 26395:623.962 - 10.131ms returns -1 (0xFFFFFFFF) +T3F74 26395:624.016 JLINK_ReadMemEx(0x00000002, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:624.036 CPU_ReadMem(2 bytes @ 0x08000002) +T3F74 26395:633.655 failed +T3F74 26395:633.684 - 9.675ms returns -1 (0xFFFFFFFF) +T3F74 26395:633.705 JLINK_ReadMemEx(0x00000002, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:633.728 CPU_ReadMem(2 bytes @ 0x08000002) +T3F74 26395:642.654 failed +T3F74 26395:642.683 - 8.984ms returns -1 (0xFFFFFFFF) +T3F74 26395:642.715 JLINK_ReadMemEx(0x00000002, 0x1 Bytes, Flags = 0x02000000) +T3F74 26395:642.734 CPU_ReadMem(1 bytes @ 0x08000002) +T3F74 26395:651.739 failed +T3F74 26395:651.768 - 9.060ms returns -1 (0xFFFFFFFF) +T3F74 26395:651.800 JLINK_ReadMemEx(0x00000004, 0x3C Bytes, Flags = 0x02000000) +T3F74 26395:651.819 CPU_ReadMem(60 bytes @ 0x08000004) +T3F74 26395:660.776 failed +T3F74 26395:660.805 - 9.011ms returns -1 (0xFFFFFFFF) +T3F74 26395:660.825 JLINK_ReadMemEx(0x00000004, 0x3C Bytes, Flags = 0x02000000) +T3F74 26395:660.846 CPU_ReadMem(60 bytes @ 0x08000004) +T3F74 26395:670.845 failed +T3F74 26395:670.927 - 10.121ms returns -1 (0xFFFFFFFF) +T3F74 26395:670.985 JLINK_ReadMemEx(0x00000004, 0xC Bytes, Flags = 0x02000000) +T3F74 26395:671.045 CPU_ReadMem(12 bytes @ 0x08000004) +T3F74 26395:680.889 failed +T3F74 26395:680.964 - 9.987ms returns -1 (0xFFFFFFFF) +T3F74 26395:680.988 JLINK_ReadMemEx(0x00000004, 0x4 Bytes, Flags = 0x02000000) +T3F74 26395:681.010 CPU_ReadMem(4 bytes @ 0x08000004) +T3F74 26395:689.863 failed +T3F74 26395:689.897 - 8.916ms returns -1 (0xFFFFFFFF) +T3F74 26395:689.922 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:689.943 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:698.662 failed +T3F74 26395:698.691 - 8.776ms returns -1 (0xFFFFFFFF) +T3F74 26395:698.712 JLINK_ReadMemEx(0x00000004, 0x1 Bytes, Flags = 0x02000000) +T3F74 26395:698.737 CPU_ReadMem(1 bytes @ 0x08000004) +T3F74 26395:707.636 failed +T3F74 26395:707.665 - 8.960ms returns -1 (0xFFFFFFFF) +T3F74 26395:707.686 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:707.709 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:716.421 failed +T3F74 26395:716.454 - 8.775ms returns -1 (0xFFFFFFFF) +T3F74 26395:716.478 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:716.500 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:725.517 failed +T3F74 26395:725.546 - 9.075ms returns -1 (0xFFFFFFFF) +T3F74 26395:725.567 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:725.590 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:734.546 failed +T3F74 26395:734.624 - 9.065ms returns -1 (0xFFFFFFFF) +T3F74 26395:734.649 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:734.670 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:744.386 failed +T3F74 26395:744.415 - 9.773ms returns -1 (0xFFFFFFFF) +T3F74 26395:744.436 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:744.459 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:753.389 failed +T3F74 26395:753.428 - 8.999ms returns -1 (0xFFFFFFFF) +T3F74 26395:753.460 JLINK_ReadMemEx(0x00000004, 0x1 Bytes, Flags = 0x02000000) +T3F74 26395:753.479 CPU_ReadMem(1 bytes @ 0x08000004) +T3F74 26395:762.368 failed +T3F74 26395:762.452 - 9.000ms returns -1 (0xFFFFFFFF) +T3F74 26395:762.501 JLINK_ReadMemEx(0x00000004, 0x3C Bytes, Flags = 0x02000000) +T3F74 26395:762.523 CPU_ReadMem(60 bytes @ 0x08000004) +T3F74 26395:771.482 failed +T3F74 26395:771.517 - 9.024ms returns -1 (0xFFFFFFFF) +T3F74 26395:771.542 JLINK_ReadMemEx(0x00000004, 0x3C Bytes, Flags = 0x02000000) +T3F74 26395:771.563 CPU_ReadMem(60 bytes @ 0x08000004) +T3F74 26395:780.482 failed +T3F74 26395:780.565 - 9.031ms returns -1 (0xFFFFFFFF) +T3F74 26395:780.589 JLINK_ReadMemEx(0x00000004, 0xC Bytes, Flags = 0x02000000) +T3F74 26395:780.610 CPU_ReadMem(12 bytes @ 0x08000004) +T3F74 26395:789.496 failed +T3F74 26395:789.525 - 8.943ms returns -1 (0xFFFFFFFF) +T3F74 26395:789.594 JLINK_ReadMemEx(0x00000004, 0x4 Bytes, Flags = 0x02000000) +T3F74 26395:789.614 CPU_ReadMem(4 bytes @ 0x08000004) +T3F74 26395:798.633 failed +T3F74 26395:798.663 - 9.076ms returns -1 (0xFFFFFFFF) +T3F74 26395:798.696 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:798.714 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:807.632 failed +T3F74 26395:807.661 - 8.973ms returns -1 (0xFFFFFFFF) +T3F74 26395:807.683 JLINK_ReadMemEx(0x00000004, 0x1 Bytes, Flags = 0x02000000) +T3F74 26395:807.703 CPU_ReadMem(1 bytes @ 0x08000004) +T3F74 26395:816.632 failed +T3F74 26395:816.661 - 8.985ms returns -1 (0xFFFFFFFF) +T3F74 26395:816.693 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:816.711 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:825.653 failed +T3F74 26395:825.686 - 9.001ms returns -1 (0xFFFFFFFF) +T3F74 26395:825.710 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:825.732 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:834.522 failed +T3F74 26395:834.552 - 8.848ms returns -1 (0xFFFFFFFF) +T3F74 26395:834.573 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:834.597 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:843.593 failed +T3F74 26395:843.627 - 9.062ms returns -1 (0xFFFFFFFF) +T3F74 26395:843.651 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:843.673 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:852.613 failed +T3F74 26395:852.642 - 8.998ms returns -1 (0xFFFFFFFF) +T3F74 26395:852.673 JLINK_ReadMemEx(0x00000004, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:852.692 CPU_ReadMem(2 bytes @ 0x08000004) +T3F74 26395:861.633 failed +T3F74 26395:861.663 - 8.996ms returns -1 (0xFFFFFFFF) +T3F74 26395:861.684 JLINK_ReadMemEx(0x00000004, 0x1 Bytes, Flags = 0x02000000) +T3F74 26395:861.706 CPU_ReadMem(1 bytes @ 0x08000004) +T3F74 26395:870.611 failed +T3F74 26395:870.640 - 8.963ms returns -1 (0xFFFFFFFF) +T3F74 26395:870.673 JLINK_ReadMemEx(0x00000006, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:870.692 CPU_ReadMem(2 bytes @ 0x08000006) +T3F74 26395:879.620 failed +T3F74 26395:879.649 - 8.983ms returns -1 (0xFFFFFFFF) +T3F74 26395:879.670 JLINK_ReadMemEx(0x00000006, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:879.693 CPU_ReadMem(2 bytes @ 0x08000006) +T3F74 26395:888.414 failed +T3F74 26395:888.447 - 8.785ms returns -1 (0xFFFFFFFF) +T3F74 26395:888.471 JLINK_ReadMemEx(0x00000006, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:888.493 CPU_ReadMem(2 bytes @ 0x08000006) +T3F74 26395:897.483 failed +T3F74 26395:897.513 - 9.049ms returns -1 (0xFFFFFFFF) +T3F74 26395:897.546 JLINK_ReadMemEx(0x00000006, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:897.565 CPU_ReadMem(2 bytes @ 0x08000006) +T3F74 26395:906.502 failed +T3F74 26395:906.531 - 8.992ms returns -1 (0xFFFFFFFF) +T3F74 26395:906.552 JLINK_ReadMemEx(0x00000006, 0x2 Bytes, Flags = 0x02000000) +T3F74 26395:906.572 CPU_ReadMem(2 bytes @ 0x08000006) +T3F74 26395:915.339 failed +T3F74 26395:915.373 - 8.829ms returns -1 (0xFFFFFFFF) +T3F74 26395:915.406 JLINK_ReadMemEx(0x00000006, 0x1 Bytes, Flags = 0x02000000) +T3F74 26395:915.438 CPU_ReadMem(1 bytes @ 0x08000006) +T3F74 26395:924.355 failed +T3F74 26395:924.384 - 8.984ms returns -1 (0xFFFFFFFF) +T3F74 26405:057.744 JLINK_HasError() +T3F74 26405:066.869 JLINK_Close() +T3F74 26405:090.630 - 23.797ms +T3F74 26405:090.678 +T3F74 26405:090.702 Closed diff --git a/MDK-ARM/JLinkSettings.ini b/MDK-ARM/JLinkSettings.ini new file mode 100644 index 0000000..39b6d05 --- /dev/null +++ b/MDK-ARM/JLinkSettings.ini @@ -0,0 +1,39 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/MDK-ARM/RTE/_uksvep_2_2_v1/RTE_Components.h b/MDK-ARM/RTE/_uksvep_2_2_v1/RTE_Components.h new file mode 100644 index 0000000..3480eb1 --- /dev/null +++ b/MDK-ARM/RTE/_uksvep_2_2_v1/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'uksvep_2_2_v1' + * Target: 'uksvep_2_2_v1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/MDK-ARM/startup_stm32f103xe.lst b/MDK-ARM/startup_stm32f103xe.lst new file mode 100644 index 0000000..f5dc5fd --- /dev/null +++ b/MDK-ARM/startup_stm32f103xe.lst @@ -0,0 +1,1461 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************** (C) COPYRIGHT 2017 STMicroelectron + ics ******************** + 2 00000000 ;* File Name : startup_stm32f103xe.s + 3 00000000 ;* Author : MCD Application Team + 4 00000000 ;* Description : STM32F103xE Devices vector table + for MDK-ARM toolchain. + 5 00000000 ;* This module performs: + 6 00000000 ;* - Set the initial SP + 7 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 8 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 9 00000000 ;* - Configure the clock system + 10 00000000 ;* - Branches to __main in the C li + brary (which eventually + 11 00000000 ;* calls main()). + 12 00000000 ;* After Reset the Cortex-M3 proces + sor is in Thread mode, + 13 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 14 00000000 ;******************************************************* + *********************** + 15 00000000 ;* @attention + 16 00000000 ;* + 17 00000000 ;* Copyright (c) 2017 STMicroelectronics. + 18 00000000 ;* All rights reserved. + 19 00000000 ;* + 20 00000000 ;* This software component is licensed by ST under BSD 3 + -Clause license, + 21 00000000 ;* the "License"; You may not use this file except in co + mpliance with the + 22 00000000 ;* License. You may obtain a copy of the License at: + 23 00000000 ;* opensource.org/licenses/BSD-3- + Clause + 24 00000000 ;* + 25 00000000 ;******************************************************* + *********************** + 26 00000000 + 27 00000000 ; Amount of memory (in bytes) allocated for Stack + 28 00000000 ; Tailor this value to your application needs + 29 00000000 ; Stack Configuration + 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 31 00000000 ; + 32 00000000 + 33 00000000 00000400 + Stack_Size + EQU 0x400 + 34 00000000 + 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 36 00000000 Stack_Mem + SPACE Stack_Size + 37 00000400 __initial_sp + 38 00000400 + 39 00000400 ; Heap Configuration + 40 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 41 00000400 ; + 42 00000400 + 43 00000400 00000200 + + + +ARM Macro Assembler Page 2 + + + Heap_Size + EQU 0x200 + 44 00000400 + 45 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 46 00000000 __heap_base + 47 00000000 Heap_Mem + SPACE Heap_Size + 48 00000200 __heap_limit + 49 00000200 + 50 00000200 PRESERVE8 + 51 00000200 THUMB + 52 00000200 + 53 00000200 + 54 00000200 ; Vector Table Mapped to Address 0 at Reset + 55 00000200 AREA RESET, DATA, READONLY + 56 00000000 EXPORT __Vectors + 57 00000000 EXPORT __Vectors_End + 58 00000000 EXPORT __Vectors_Size + 59 00000000 + 60 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 61 00000004 00000000 DCD Reset_Handler ; Reset Handler + 62 00000008 00000000 DCD NMI_Handler ; NMI Handler + 63 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 64 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 65 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 66 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 67 0000001C 00000000 DCD 0 ; Reserved + 68 00000020 00000000 DCD 0 ; Reserved + 69 00000024 00000000 DCD 0 ; Reserved + 70 00000028 00000000 DCD 0 ; Reserved + 71 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 72 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 73 00000034 00000000 DCD 0 ; Reserved + 74 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 75 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 76 00000040 + 77 00000040 ; External Interrupts + 78 00000040 00000000 DCD WWDG_IRQHandler + ; Window Watchdog + 79 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX + TI Line detect + 80 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper + 81 0000004C 00000000 DCD RTC_IRQHandler ; RTC + 82 00000050 00000000 DCD FLASH_IRQHandler ; Flash + 83 00000054 00000000 DCD RCC_IRQHandler ; RCC + 84 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0 + 85 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1 + + + +ARM Macro Assembler Page 3 + + + 86 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2 + 87 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3 + 88 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4 + 89 0000006C 00000000 DCD DMA1_Channel1_IRQHandler + ; DMA1 Channel 1 + 90 00000070 00000000 DCD DMA1_Channel2_IRQHandler + ; DMA1 Channel 2 + 91 00000074 00000000 DCD DMA1_Channel3_IRQHandler + ; DMA1 Channel 3 + 92 00000078 00000000 DCD DMA1_Channel4_IRQHandler + ; DMA1 Channel 4 + 93 0000007C 00000000 DCD DMA1_Channel5_IRQHandler + ; DMA1 Channel 5 + 94 00000080 00000000 DCD DMA1_Channel6_IRQHandler + ; DMA1 Channel 6 + 95 00000084 00000000 DCD DMA1_Channel7_IRQHandler + ; DMA1 Channel 7 + 96 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + + 97 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB + High Priority or C + AN1 TX + 98 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US + B Low Priority or + CAN1 RX0 + 99 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + 100 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE + 101 0000009C 00000000 DCD EXTI9_5_IRQHandler + ; EXTI Line 9..5 + 102 000000A0 00000000 DCD TIM1_BRK_IRQHandler + ; TIM1 Break + 103 000000A4 00000000 DCD TIM1_UP_IRQHandler + ; TIM1 Update + 104 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1 + Trigger and Commuta + tion + 105 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + 106 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2 + 107 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3 + 108 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4 + 109 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event + + 110 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error + + 111 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event + + 112 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error + + 113 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1 + 114 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2 + 115 000000D4 00000000 DCD USART1_IRQHandler ; USART1 + 116 000000D8 00000000 DCD USART2_IRQHandler ; USART2 + 117 000000DC 00000000 DCD USART3_IRQHandler ; USART3 + 118 000000E0 00000000 DCD EXTI15_10_IRQHandler + ; EXTI Line 15..10 + 119 000000E4 00000000 DCD RTC_Alarm_IRQHandler ; RTC Alar + m through EXTI Line + + + + +ARM Macro Assembler Page 4 + + + 120 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake + up from suspend + 121 000000EC 00000000 DCD TIM8_BRK_IRQHandler + ; TIM8 Break + 122 000000F0 00000000 DCD TIM8_UP_IRQHandler + ; TIM8 Update + 123 000000F4 00000000 DCD TIM8_TRG_COM_IRQHandler ; TIM8 + Trigger and Commuta + tion + 124 000000F8 00000000 DCD TIM8_CC_IRQHandler ; TIM8 Captu + re Compare + 125 000000FC 00000000 DCD ADC3_IRQHandler ; ADC3 + 126 00000100 00000000 DCD FSMC_IRQHandler ; FSMC + 127 00000104 00000000 DCD SDIO_IRQHandler ; SDIO + 128 00000108 00000000 DCD TIM5_IRQHandler ; TIM5 + 129 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3 + 130 00000110 00000000 DCD UART4_IRQHandler ; UART4 + 131 00000114 00000000 DCD UART5_IRQHandler ; UART5 + 132 00000118 00000000 DCD TIM6_IRQHandler ; TIM6 + 133 0000011C 00000000 DCD TIM7_IRQHandler ; TIM7 + 134 00000120 00000000 DCD DMA2_Channel1_IRQHandler + ; DMA2 Channel1 + 135 00000124 00000000 DCD DMA2_Channel2_IRQHandler + ; DMA2 Channel2 + 136 00000128 00000000 DCD DMA2_Channel3_IRQHandler + ; DMA2 Channel3 + 137 0000012C 00000000 DCD DMA2_Channel4_5_IRQHandler ; DM + A2 Channel4 & Chann + el5 + 138 00000130 __Vectors_End + 139 00000130 + 140 00000130 00000130 + __Vectors_Size + EQU __Vectors_End - __Vectors + 141 00000130 + 142 00000130 AREA |.text|, CODE, READONLY + 143 00000000 + 144 00000000 ; Reset handler + 145 00000000 Reset_Handler + PROC + 146 00000000 EXPORT Reset_Handler [WEAK +] + 147 00000000 IMPORT __main + 148 00000000 IMPORT SystemInit + 149 00000000 4809 LDR R0, =SystemInit + 150 00000002 4780 BLX R0 + 151 00000004 4809 LDR R0, =__main + 152 00000006 4700 BX R0 + 153 00000008 ENDP + 154 00000008 + 155 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 156 00000008 + 157 00000008 NMI_Handler + PROC + 158 00000008 EXPORT NMI_Handler [WEA +K] + 159 00000008 E7FE B . + 160 0000000A ENDP + + + +ARM Macro Assembler Page 5 + + + 162 0000000A HardFault_Handler + PROC + 163 0000000A EXPORT HardFault_Handler [WEA +K] + 164 0000000A E7FE B . + 165 0000000C ENDP + 167 0000000C MemManage_Handler + PROC + 168 0000000C EXPORT MemManage_Handler [WEA +K] + 169 0000000C E7FE B . + 170 0000000E ENDP + 172 0000000E BusFault_Handler + PROC + 173 0000000E EXPORT BusFault_Handler [WEA +K] + 174 0000000E E7FE B . + 175 00000010 ENDP + 177 00000010 UsageFault_Handler + PROC + 178 00000010 EXPORT UsageFault_Handler [WEA +K] + 179 00000010 E7FE B . + 180 00000012 ENDP + 181 00000012 SVC_Handler + PROC + 182 00000012 EXPORT SVC_Handler [WEA +K] + 183 00000012 E7FE B . + 184 00000014 ENDP + 186 00000014 DebugMon_Handler + PROC + 187 00000014 EXPORT DebugMon_Handler [WEA +K] + 188 00000014 E7FE B . + 189 00000016 ENDP + 190 00000016 PendSV_Handler + PROC + 191 00000016 EXPORT PendSV_Handler [WEA +K] + 192 00000016 E7FE B . + 193 00000018 ENDP + 194 00000018 SysTick_Handler + PROC + 195 00000018 EXPORT SysTick_Handler [WEA +K] + 196 00000018 E7FE B . + 197 0000001A ENDP + 198 0000001A + 199 0000001A Default_Handler + PROC + 200 0000001A + 201 0000001A EXPORT WWDG_IRQHandler [WEA +K] + 202 0000001A EXPORT PVD_IRQHandler [WEA +K] + 203 0000001A EXPORT TAMPER_IRQHandler [WEA +K] + 204 0000001A EXPORT RTC_IRQHandler [WEA + + + +ARM Macro Assembler Page 6 + + +K] + 205 0000001A EXPORT FLASH_IRQHandler [WEA +K] + 206 0000001A EXPORT RCC_IRQHandler [WEA +K] + 207 0000001A EXPORT EXTI0_IRQHandler [WEA +K] + 208 0000001A EXPORT EXTI1_IRQHandler [WEA +K] + 209 0000001A EXPORT EXTI2_IRQHandler [WEA +K] + 210 0000001A EXPORT EXTI3_IRQHandler [WEA +K] + 211 0000001A EXPORT EXTI4_IRQHandler [WEA +K] + 212 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA +K] + 213 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA +K] + 214 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA +K] + 215 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA +K] + 216 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA +K] + 217 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA +K] + 218 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA +K] + 219 0000001A EXPORT ADC1_2_IRQHandler [WEA +K] + 220 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA +K] + 221 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA +K] + 222 0000001A EXPORT CAN1_RX1_IRQHandler [WEA +K] + 223 0000001A EXPORT CAN1_SCE_IRQHandler [WEA +K] + 224 0000001A EXPORT EXTI9_5_IRQHandler [WEA +K] + 225 0000001A EXPORT TIM1_BRK_IRQHandler [WEA +K] + 226 0000001A EXPORT TIM1_UP_IRQHandler [WEA +K] + 227 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA +K] + 228 0000001A EXPORT TIM1_CC_IRQHandler [WEA +K] + 229 0000001A EXPORT TIM2_IRQHandler [WEA +K] + 230 0000001A EXPORT TIM3_IRQHandler [WEA +K] + 231 0000001A EXPORT TIM4_IRQHandler [WEA +K] + 232 0000001A EXPORT I2C1_EV_IRQHandler [WEA +K] + 233 0000001A EXPORT I2C1_ER_IRQHandler [WEA +K] + + + +ARM Macro Assembler Page 7 + + + 234 0000001A EXPORT I2C2_EV_IRQHandler [WEA +K] + 235 0000001A EXPORT I2C2_ER_IRQHandler [WEA +K] + 236 0000001A EXPORT SPI1_IRQHandler [WEA +K] + 237 0000001A EXPORT SPI2_IRQHandler [WEA +K] + 238 0000001A EXPORT USART1_IRQHandler [WEA +K] + 239 0000001A EXPORT USART2_IRQHandler [WEA +K] + 240 0000001A EXPORT USART3_IRQHandler [WEA +K] + 241 0000001A EXPORT EXTI15_10_IRQHandler [WEA +K] + 242 0000001A EXPORT RTC_Alarm_IRQHandler [WE +AK] + 243 0000001A EXPORT USBWakeUp_IRQHandler [WEA +K] + 244 0000001A EXPORT TIM8_BRK_IRQHandler [WEA +K] + 245 0000001A EXPORT TIM8_UP_IRQHandler [WEA +K] + 246 0000001A EXPORT TIM8_TRG_COM_IRQHandler [WEA +K] + 247 0000001A EXPORT TIM8_CC_IRQHandler [WEA +K] + 248 0000001A EXPORT ADC3_IRQHandler [WEA +K] + 249 0000001A EXPORT FSMC_IRQHandler [WEA +K] + 250 0000001A EXPORT SDIO_IRQHandler [WEA +K] + 251 0000001A EXPORT TIM5_IRQHandler [WEA +K] + 252 0000001A EXPORT SPI3_IRQHandler [WEA +K] + 253 0000001A EXPORT UART4_IRQHandler [WEA +K] + 254 0000001A EXPORT UART5_IRQHandler [WEA +K] + 255 0000001A EXPORT TIM6_IRQHandler [WEA +K] + 256 0000001A EXPORT TIM7_IRQHandler [WEA +K] + 257 0000001A EXPORT DMA2_Channel1_IRQHandler [WEA +K] + 258 0000001A EXPORT DMA2_Channel2_IRQHandler [WEA +K] + 259 0000001A EXPORT DMA2_Channel3_IRQHandler [WEA +K] + 260 0000001A EXPORT DMA2_Channel4_5_IRQHandler [WEA +K] + 261 0000001A + 262 0000001A WWDG_IRQHandler + 263 0000001A PVD_IRQHandler + 264 0000001A TAMPER_IRQHandler + 265 0000001A RTC_IRQHandler + + + +ARM Macro Assembler Page 8 + + + 266 0000001A FLASH_IRQHandler + 267 0000001A RCC_IRQHandler + 268 0000001A EXTI0_IRQHandler + 269 0000001A EXTI1_IRQHandler + 270 0000001A EXTI2_IRQHandler + 271 0000001A EXTI3_IRQHandler + 272 0000001A EXTI4_IRQHandler + 273 0000001A DMA1_Channel1_IRQHandler + 274 0000001A DMA1_Channel2_IRQHandler + 275 0000001A DMA1_Channel3_IRQHandler + 276 0000001A DMA1_Channel4_IRQHandler + 277 0000001A DMA1_Channel5_IRQHandler + 278 0000001A DMA1_Channel6_IRQHandler + 279 0000001A DMA1_Channel7_IRQHandler + 280 0000001A ADC1_2_IRQHandler + 281 0000001A USB_HP_CAN1_TX_IRQHandler + 282 0000001A USB_LP_CAN1_RX0_IRQHandler + 283 0000001A CAN1_RX1_IRQHandler + 284 0000001A CAN1_SCE_IRQHandler + 285 0000001A EXTI9_5_IRQHandler + 286 0000001A TIM1_BRK_IRQHandler + 287 0000001A TIM1_UP_IRQHandler + 288 0000001A TIM1_TRG_COM_IRQHandler + 289 0000001A TIM1_CC_IRQHandler + 290 0000001A TIM2_IRQHandler + 291 0000001A TIM3_IRQHandler + 292 0000001A TIM4_IRQHandler + 293 0000001A I2C1_EV_IRQHandler + 294 0000001A I2C1_ER_IRQHandler + 295 0000001A I2C2_EV_IRQHandler + 296 0000001A I2C2_ER_IRQHandler + 297 0000001A SPI1_IRQHandler + 298 0000001A SPI2_IRQHandler + 299 0000001A USART1_IRQHandler + 300 0000001A USART2_IRQHandler + 301 0000001A USART3_IRQHandler + 302 0000001A EXTI15_10_IRQHandler + 303 0000001A RTC_Alarm_IRQHandler + 304 0000001A USBWakeUp_IRQHandler + 305 0000001A TIM8_BRK_IRQHandler + 306 0000001A TIM8_UP_IRQHandler + 307 0000001A TIM8_TRG_COM_IRQHandler + 308 0000001A TIM8_CC_IRQHandler + 309 0000001A ADC3_IRQHandler + 310 0000001A FSMC_IRQHandler + 311 0000001A SDIO_IRQHandler + 312 0000001A TIM5_IRQHandler + 313 0000001A SPI3_IRQHandler + 314 0000001A UART4_IRQHandler + 315 0000001A UART5_IRQHandler + 316 0000001A TIM6_IRQHandler + 317 0000001A TIM7_IRQHandler + 318 0000001A DMA2_Channel1_IRQHandler + 319 0000001A DMA2_Channel2_IRQHandler + 320 0000001A DMA2_Channel3_IRQHandler + 321 0000001A DMA2_Channel4_5_IRQHandler + 322 0000001A E7FE B . + 323 0000001C + 324 0000001C ENDP + + + +ARM Macro Assembler Page 9 + + + 325 0000001C + 326 0000001C ALIGN + 327 0000001C + 328 0000001C ;******************************************************* + ************************ + 329 0000001C ; User Stack and Heap initialization + 330 0000001C ;******************************************************* + ************************ + 331 0000001C IF :DEF:__MICROLIB + 338 0000001C + 339 0000001C IMPORT __use_two_region_memory + 340 0000001C EXPORT __user_initial_stackheap + 341 0000001C + 342 0000001C __user_initial_stackheap + 343 0000001C + 344 0000001C 4804 LDR R0, = Heap_Mem + 345 0000001E 4905 LDR R1, =(Stack_Mem + Stack_Size) + 346 00000020 4A05 LDR R2, = (Heap_Mem + Heap_Size) + 347 00000022 4B06 LDR R3, = Stack_Mem + 348 00000024 4770 BX LR + 349 00000026 + 350 00000026 00 00 ALIGN + 351 00000028 + 352 00000028 ENDIF + 353 00000028 + 354 00000028 END + 00000000 + 00000000 + 00000000 + 00000400 + 00000200 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=uksvep_2_2_v1\startup_stm32f103xe.d -ouksvep_2_2_v1\startup_stm32f +103xe.o -I.\RTE\_uksvep_2_2_v1 -Id:\Keil\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\In +clude -Id:\Keil\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include --predefine="_ +_UVISION_VERSION SETA 529" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_HD + SETA 1" --list=startup_stm32f103xe.lst startup_stm32f103xe.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 35 in file startup_stm32f103xe.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 36 in file startup_stm32f103xe.s + Uses + At line 345 in file startup_stm32f103xe.s + At line 347 in file startup_stm32f103xe.s + +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 37 in file startup_stm32f103xe.s + Uses + At line 60 in file startup_stm32f103xe.s +Comment: __initial_sp used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 45 in file startup_stm32f103xe.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 47 in file startup_stm32f103xe.s + Uses + At line 344 in file startup_stm32f103xe.s + At line 346 in file startup_stm32f103xe.s + +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 46 in file startup_stm32f103xe.s + Uses + None +Comment: __heap_base unused +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 48 in file startup_stm32f103xe.s + Uses + None +Comment: __heap_limit unused +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 55 in file startup_stm32f103xe.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 60 in file startup_stm32f103xe.s + Uses + At line 56 in file startup_stm32f103xe.s + At line 140 in file startup_stm32f103xe.s + +__Vectors_End 00000130 + +Symbol: __Vectors_End + Definitions + At line 138 in file startup_stm32f103xe.s + Uses + At line 57 in file startup_stm32f103xe.s + At line 140 in file startup_stm32f103xe.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 142 in file startup_stm32f103xe.s + Uses + None +Comment: .text unused +ADC1_2_IRQHandler 0000001A + +Symbol: ADC1_2_IRQHandler + Definitions + At line 280 in file startup_stm32f103xe.s + Uses + At line 96 in file startup_stm32f103xe.s + At line 219 in file startup_stm32f103xe.s + +ADC3_IRQHandler 0000001A + +Symbol: ADC3_IRQHandler + Definitions + At line 309 in file startup_stm32f103xe.s + Uses + At line 125 in file startup_stm32f103xe.s + At line 248 in file startup_stm32f103xe.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 172 in file startup_stm32f103xe.s + Uses + At line 65 in file startup_stm32f103xe.s + At line 173 in file startup_stm32f103xe.s + +CAN1_RX1_IRQHandler 0000001A + +Symbol: CAN1_RX1_IRQHandler + Definitions + At line 283 in file startup_stm32f103xe.s + Uses + At line 99 in file startup_stm32f103xe.s + At line 222 in file startup_stm32f103xe.s + +CAN1_SCE_IRQHandler 0000001A + +Symbol: CAN1_SCE_IRQHandler + Definitions + At line 284 in file startup_stm32f103xe.s + Uses + At line 100 in file startup_stm32f103xe.s + At line 223 in file startup_stm32f103xe.s + +DMA1_Channel1_IRQHandler 0000001A + +Symbol: DMA1_Channel1_IRQHandler + Definitions + At line 273 in file startup_stm32f103xe.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + At line 89 in file startup_stm32f103xe.s + At line 212 in file startup_stm32f103xe.s + +DMA1_Channel2_IRQHandler 0000001A + +Symbol: DMA1_Channel2_IRQHandler + Definitions + At line 274 in file startup_stm32f103xe.s + Uses + At line 90 in file startup_stm32f103xe.s + At line 213 in file startup_stm32f103xe.s + +DMA1_Channel3_IRQHandler 0000001A + +Symbol: DMA1_Channel3_IRQHandler + Definitions + At line 275 in file startup_stm32f103xe.s + Uses + At line 91 in file startup_stm32f103xe.s + At line 214 in file startup_stm32f103xe.s + +DMA1_Channel4_IRQHandler 0000001A + +Symbol: DMA1_Channel4_IRQHandler + Definitions + At line 276 in file startup_stm32f103xe.s + Uses + At line 92 in file startup_stm32f103xe.s + At line 215 in file startup_stm32f103xe.s + +DMA1_Channel5_IRQHandler 0000001A + +Symbol: DMA1_Channel5_IRQHandler + Definitions + At line 277 in file startup_stm32f103xe.s + Uses + At line 93 in file startup_stm32f103xe.s + At line 216 in file startup_stm32f103xe.s + +DMA1_Channel6_IRQHandler 0000001A + +Symbol: DMA1_Channel6_IRQHandler + Definitions + At line 278 in file startup_stm32f103xe.s + Uses + At line 94 in file startup_stm32f103xe.s + At line 217 in file startup_stm32f103xe.s + +DMA1_Channel7_IRQHandler 0000001A + +Symbol: DMA1_Channel7_IRQHandler + Definitions + At line 279 in file startup_stm32f103xe.s + Uses + At line 95 in file startup_stm32f103xe.s + At line 218 in file startup_stm32f103xe.s + +DMA2_Channel1_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + +Symbol: DMA2_Channel1_IRQHandler + Definitions + At line 318 in file startup_stm32f103xe.s + Uses + At line 134 in file startup_stm32f103xe.s + At line 257 in file startup_stm32f103xe.s + +DMA2_Channel2_IRQHandler 0000001A + +Symbol: DMA2_Channel2_IRQHandler + Definitions + At line 319 in file startup_stm32f103xe.s + Uses + At line 135 in file startup_stm32f103xe.s + At line 258 in file startup_stm32f103xe.s + +DMA2_Channel3_IRQHandler 0000001A + +Symbol: DMA2_Channel3_IRQHandler + Definitions + At line 320 in file startup_stm32f103xe.s + Uses + At line 136 in file startup_stm32f103xe.s + At line 259 in file startup_stm32f103xe.s + +DMA2_Channel4_5_IRQHandler 0000001A + +Symbol: DMA2_Channel4_5_IRQHandler + Definitions + At line 321 in file startup_stm32f103xe.s + Uses + At line 137 in file startup_stm32f103xe.s + At line 260 in file startup_stm32f103xe.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 186 in file startup_stm32f103xe.s + Uses + At line 72 in file startup_stm32f103xe.s + At line 187 in file startup_stm32f103xe.s + +Default_Handler 0000001A + +Symbol: Default_Handler + Definitions + At line 199 in file startup_stm32f103xe.s + Uses + None +Comment: Default_Handler unused +EXTI0_IRQHandler 0000001A + +Symbol: EXTI0_IRQHandler + Definitions + At line 268 in file startup_stm32f103xe.s + Uses + At line 84 in file startup_stm32f103xe.s + At line 207 in file startup_stm32f103xe.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + +EXTI15_10_IRQHandler 0000001A + +Symbol: EXTI15_10_IRQHandler + Definitions + At line 302 in file startup_stm32f103xe.s + Uses + At line 118 in file startup_stm32f103xe.s + At line 241 in file startup_stm32f103xe.s + +EXTI1_IRQHandler 0000001A + +Symbol: EXTI1_IRQHandler + Definitions + At line 269 in file startup_stm32f103xe.s + Uses + At line 85 in file startup_stm32f103xe.s + At line 208 in file startup_stm32f103xe.s + +EXTI2_IRQHandler 0000001A + +Symbol: EXTI2_IRQHandler + Definitions + At line 270 in file startup_stm32f103xe.s + Uses + At line 86 in file startup_stm32f103xe.s + At line 209 in file startup_stm32f103xe.s + +EXTI3_IRQHandler 0000001A + +Symbol: EXTI3_IRQHandler + Definitions + At line 271 in file startup_stm32f103xe.s + Uses + At line 87 in file startup_stm32f103xe.s + At line 210 in file startup_stm32f103xe.s + +EXTI4_IRQHandler 0000001A + +Symbol: EXTI4_IRQHandler + Definitions + At line 272 in file startup_stm32f103xe.s + Uses + At line 88 in file startup_stm32f103xe.s + At line 211 in file startup_stm32f103xe.s + +EXTI9_5_IRQHandler 0000001A + +Symbol: EXTI9_5_IRQHandler + Definitions + At line 285 in file startup_stm32f103xe.s + Uses + At line 101 in file startup_stm32f103xe.s + At line 224 in file startup_stm32f103xe.s + +FLASH_IRQHandler 0000001A + +Symbol: FLASH_IRQHandler + Definitions + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 266 in file startup_stm32f103xe.s + Uses + At line 82 in file startup_stm32f103xe.s + At line 205 in file startup_stm32f103xe.s + +FSMC_IRQHandler 0000001A + +Symbol: FSMC_IRQHandler + Definitions + At line 310 in file startup_stm32f103xe.s + Uses + At line 126 in file startup_stm32f103xe.s + At line 249 in file startup_stm32f103xe.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 162 in file startup_stm32f103xe.s + Uses + At line 63 in file startup_stm32f103xe.s + At line 163 in file startup_stm32f103xe.s + +I2C1_ER_IRQHandler 0000001A + +Symbol: I2C1_ER_IRQHandler + Definitions + At line 294 in file startup_stm32f103xe.s + Uses + At line 110 in file startup_stm32f103xe.s + At line 233 in file startup_stm32f103xe.s + +I2C1_EV_IRQHandler 0000001A + +Symbol: I2C1_EV_IRQHandler + Definitions + At line 293 in file startup_stm32f103xe.s + Uses + At line 109 in file startup_stm32f103xe.s + At line 232 in file startup_stm32f103xe.s + +I2C2_ER_IRQHandler 0000001A + +Symbol: I2C2_ER_IRQHandler + Definitions + At line 296 in file startup_stm32f103xe.s + Uses + At line 112 in file startup_stm32f103xe.s + At line 235 in file startup_stm32f103xe.s + +I2C2_EV_IRQHandler 0000001A + +Symbol: I2C2_EV_IRQHandler + Definitions + At line 295 in file startup_stm32f103xe.s + Uses + At line 111 in file startup_stm32f103xe.s + At line 234 in file startup_stm32f103xe.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +MemManage_Handler 0000000C + +Symbol: MemManage_Handler + Definitions + At line 167 in file startup_stm32f103xe.s + Uses + At line 64 in file startup_stm32f103xe.s + At line 168 in file startup_stm32f103xe.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 157 in file startup_stm32f103xe.s + Uses + At line 62 in file startup_stm32f103xe.s + At line 158 in file startup_stm32f103xe.s + +PVD_IRQHandler 0000001A + +Symbol: PVD_IRQHandler + Definitions + At line 263 in file startup_stm32f103xe.s + Uses + At line 79 in file startup_stm32f103xe.s + At line 202 in file startup_stm32f103xe.s + +PendSV_Handler 00000016 + +Symbol: PendSV_Handler + Definitions + At line 190 in file startup_stm32f103xe.s + Uses + At line 74 in file startup_stm32f103xe.s + At line 191 in file startup_stm32f103xe.s + +RCC_IRQHandler 0000001A + +Symbol: RCC_IRQHandler + Definitions + At line 267 in file startup_stm32f103xe.s + Uses + At line 83 in file startup_stm32f103xe.s + At line 206 in file startup_stm32f103xe.s + +RTC_Alarm_IRQHandler 0000001A + +Symbol: RTC_Alarm_IRQHandler + Definitions + At line 303 in file startup_stm32f103xe.s + Uses + At line 119 in file startup_stm32f103xe.s + At line 242 in file startup_stm32f103xe.s + +RTC_IRQHandler 0000001A + +Symbol: RTC_IRQHandler + Definitions + At line 265 in file startup_stm32f103xe.s + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 81 in file startup_stm32f103xe.s + At line 204 in file startup_stm32f103xe.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 145 in file startup_stm32f103xe.s + Uses + At line 61 in file startup_stm32f103xe.s + At line 146 in file startup_stm32f103xe.s + +SDIO_IRQHandler 0000001A + +Symbol: SDIO_IRQHandler + Definitions + At line 311 in file startup_stm32f103xe.s + Uses + At line 127 in file startup_stm32f103xe.s + At line 250 in file startup_stm32f103xe.s + +SPI1_IRQHandler 0000001A + +Symbol: SPI1_IRQHandler + Definitions + At line 297 in file startup_stm32f103xe.s + Uses + At line 113 in file startup_stm32f103xe.s + At line 236 in file startup_stm32f103xe.s + +SPI2_IRQHandler 0000001A + +Symbol: SPI2_IRQHandler + Definitions + At line 298 in file startup_stm32f103xe.s + Uses + At line 114 in file startup_stm32f103xe.s + At line 237 in file startup_stm32f103xe.s + +SPI3_IRQHandler 0000001A + +Symbol: SPI3_IRQHandler + Definitions + At line 313 in file startup_stm32f103xe.s + Uses + At line 129 in file startup_stm32f103xe.s + At line 252 in file startup_stm32f103xe.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 181 in file startup_stm32f103xe.s + Uses + At line 71 in file startup_stm32f103xe.s + At line 182 in file startup_stm32f103xe.s + +SysTick_Handler 00000018 + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: SysTick_Handler + Definitions + At line 194 in file startup_stm32f103xe.s + Uses + At line 75 in file startup_stm32f103xe.s + At line 195 in file startup_stm32f103xe.s + +TAMPER_IRQHandler 0000001A + +Symbol: TAMPER_IRQHandler + Definitions + At line 264 in file startup_stm32f103xe.s + Uses + At line 80 in file startup_stm32f103xe.s + At line 203 in file startup_stm32f103xe.s + +TIM1_BRK_IRQHandler 0000001A + +Symbol: TIM1_BRK_IRQHandler + Definitions + At line 286 in file startup_stm32f103xe.s + Uses + At line 102 in file startup_stm32f103xe.s + At line 225 in file startup_stm32f103xe.s + +TIM1_CC_IRQHandler 0000001A + +Symbol: TIM1_CC_IRQHandler + Definitions + At line 289 in file startup_stm32f103xe.s + Uses + At line 105 in file startup_stm32f103xe.s + At line 228 in file startup_stm32f103xe.s + +TIM1_TRG_COM_IRQHandler 0000001A + +Symbol: TIM1_TRG_COM_IRQHandler + Definitions + At line 288 in file startup_stm32f103xe.s + Uses + At line 104 in file startup_stm32f103xe.s + At line 227 in file startup_stm32f103xe.s + +TIM1_UP_IRQHandler 0000001A + +Symbol: TIM1_UP_IRQHandler + Definitions + At line 287 in file startup_stm32f103xe.s + Uses + At line 103 in file startup_stm32f103xe.s + At line 226 in file startup_stm32f103xe.s + +TIM2_IRQHandler 0000001A + +Symbol: TIM2_IRQHandler + Definitions + At line 290 in file startup_stm32f103xe.s + Uses + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + + At line 106 in file startup_stm32f103xe.s + At line 229 in file startup_stm32f103xe.s + +TIM3_IRQHandler 0000001A + +Symbol: TIM3_IRQHandler + Definitions + At line 291 in file startup_stm32f103xe.s + Uses + At line 107 in file startup_stm32f103xe.s + At line 230 in file startup_stm32f103xe.s + +TIM4_IRQHandler 0000001A + +Symbol: TIM4_IRQHandler + Definitions + At line 292 in file startup_stm32f103xe.s + Uses + At line 108 in file startup_stm32f103xe.s + At line 231 in file startup_stm32f103xe.s + +TIM5_IRQHandler 0000001A + +Symbol: TIM5_IRQHandler + Definitions + At line 312 in file startup_stm32f103xe.s + Uses + At line 128 in file startup_stm32f103xe.s + At line 251 in file startup_stm32f103xe.s + +TIM6_IRQHandler 0000001A + +Symbol: TIM6_IRQHandler + Definitions + At line 316 in file startup_stm32f103xe.s + Uses + At line 132 in file startup_stm32f103xe.s + At line 255 in file startup_stm32f103xe.s + +TIM7_IRQHandler 0000001A + +Symbol: TIM7_IRQHandler + Definitions + At line 317 in file startup_stm32f103xe.s + Uses + At line 133 in file startup_stm32f103xe.s + At line 256 in file startup_stm32f103xe.s + +TIM8_BRK_IRQHandler 0000001A + +Symbol: TIM8_BRK_IRQHandler + Definitions + At line 305 in file startup_stm32f103xe.s + Uses + At line 121 in file startup_stm32f103xe.s + At line 244 in file startup_stm32f103xe.s + +TIM8_CC_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + +Symbol: TIM8_CC_IRQHandler + Definitions + At line 308 in file startup_stm32f103xe.s + Uses + At line 124 in file startup_stm32f103xe.s + At line 247 in file startup_stm32f103xe.s + +TIM8_TRG_COM_IRQHandler 0000001A + +Symbol: TIM8_TRG_COM_IRQHandler + Definitions + At line 307 in file startup_stm32f103xe.s + Uses + At line 123 in file startup_stm32f103xe.s + At line 246 in file startup_stm32f103xe.s + +TIM8_UP_IRQHandler 0000001A + +Symbol: TIM8_UP_IRQHandler + Definitions + At line 306 in file startup_stm32f103xe.s + Uses + At line 122 in file startup_stm32f103xe.s + At line 245 in file startup_stm32f103xe.s + +UART4_IRQHandler 0000001A + +Symbol: UART4_IRQHandler + Definitions + At line 314 in file startup_stm32f103xe.s + Uses + At line 130 in file startup_stm32f103xe.s + At line 253 in file startup_stm32f103xe.s + +UART5_IRQHandler 0000001A + +Symbol: UART5_IRQHandler + Definitions + At line 315 in file startup_stm32f103xe.s + Uses + At line 131 in file startup_stm32f103xe.s + At line 254 in file startup_stm32f103xe.s + +USART1_IRQHandler 0000001A + +Symbol: USART1_IRQHandler + Definitions + At line 299 in file startup_stm32f103xe.s + Uses + At line 115 in file startup_stm32f103xe.s + At line 238 in file startup_stm32f103xe.s + +USART2_IRQHandler 0000001A + +Symbol: USART2_IRQHandler + Definitions + At line 300 in file startup_stm32f103xe.s + Uses + At line 116 in file startup_stm32f103xe.s + + + +ARM Macro Assembler Page 11 Alphabetic symbol ordering +Relocatable symbols + + At line 239 in file startup_stm32f103xe.s + +USART3_IRQHandler 0000001A + +Symbol: USART3_IRQHandler + Definitions + At line 301 in file startup_stm32f103xe.s + Uses + At line 117 in file startup_stm32f103xe.s + At line 240 in file startup_stm32f103xe.s + +USBWakeUp_IRQHandler 0000001A + +Symbol: USBWakeUp_IRQHandler + Definitions + At line 304 in file startup_stm32f103xe.s + Uses + At line 120 in file startup_stm32f103xe.s + At line 243 in file startup_stm32f103xe.s + +USB_HP_CAN1_TX_IRQHandler 0000001A + +Symbol: USB_HP_CAN1_TX_IRQHandler + Definitions + At line 281 in file startup_stm32f103xe.s + Uses + At line 97 in file startup_stm32f103xe.s + At line 220 in file startup_stm32f103xe.s + +USB_LP_CAN1_RX0_IRQHandler 0000001A + +Symbol: USB_LP_CAN1_RX0_IRQHandler + Definitions + At line 282 in file startup_stm32f103xe.s + Uses + At line 98 in file startup_stm32f103xe.s + At line 221 in file startup_stm32f103xe.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 177 in file startup_stm32f103xe.s + Uses + At line 66 in file startup_stm32f103xe.s + At line 178 in file startup_stm32f103xe.s + +WWDG_IRQHandler 0000001A + +Symbol: WWDG_IRQHandler + Definitions + At line 262 in file startup_stm32f103xe.s + Uses + At line 78 in file startup_stm32f103xe.s + At line 201 in file startup_stm32f103xe.s + +__user_initial_stackheap 0000001C + +Symbol: __user_initial_stackheap + + + +ARM Macro Assembler Page 12 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 342 in file startup_stm32f103xe.s + Uses + At line 340 in file startup_stm32f103xe.s +Comment: __user_initial_stackheap used once +73 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 43 in file startup_stm32f103xe.s + Uses + At line 47 in file startup_stm32f103xe.s + At line 346 in file startup_stm32f103xe.s + +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 33 in file startup_stm32f103xe.s + Uses + At line 36 in file startup_stm32f103xe.s + At line 345 in file startup_stm32f103xe.s + +__Vectors_Size 00000130 + +Symbol: __Vectors_Size + Definitions + At line 140 in file startup_stm32f103xe.s + Uses + At line 58 in file startup_stm32f103xe.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 148 in file startup_stm32f103xe.s + Uses + At line 149 in file startup_stm32f103xe.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 147 in file startup_stm32f103xe.s + Uses + At line 151 in file startup_stm32f103xe.s +Comment: __main used once +__use_two_region_memory 00000000 + +Symbol: __use_two_region_memory + Definitions + At line 339 in file startup_stm32f103xe.s + Uses + None +Comment: __use_two_region_memory unused +3 symbols +426 symbols in table diff --git a/MDK-ARM/startup_stm32f103xe.s b/MDK-ARM/startup_stm32f103xe.s new file mode 100644 index 0000000..40bc8e6 --- /dev/null +++ b/MDK-ARM/startup_stm32f103xe.s @@ -0,0 +1,356 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f103xe.s +;* Author : MCD Application Team +;* Description : STM32F103xE Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2017 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/MDK-ARM/uksvep_2_2_v1.uvguix.dimas b/MDK-ARM/uksvep_2_2_v1.uvguix.dimas new file mode 100644 index 0000000..9ac2193 --- /dev/null +++ b/MDK-ARM/uksvep_2_2_v1.uvguix.dimas @@ -0,0 +1,3842 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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new file mode 100644 index 0000000..c1d21e0 --- /dev/null +++ b/MDK-ARM/uksvep_2_2_v1.uvprojx @@ -0,0 +1,1608 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
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HcmV?d00001 diff --git a/MDK-ARM/uksvep_2_2_v1/ecan.d b/MDK-ARM/uksvep_2_2_v1/ecan.d new file mode 100644 index 0000000..e677cbe --- /dev/null +++ b/MDK-ARM/uksvep_2_2_v1/ecan.d @@ -0,0 +1,37 @@ +uksvep_2_2_v1\ecan.o: ..\Core\Src\ecan.c +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h +uksvep_2_2_v1\ecan.o: ../Core/Inc/stm32f1xx_hal_conf.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h +uksvep_2_2_v1\ecan.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h +uksvep_2_2_v1\ecan.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h +uksvep_2_2_v1\ecan.o: ../Drivers/CMSIS/Include/core_cm3.h +uksvep_2_2_v1\ecan.o: d:\Keil\ARM\ARMCC\Bin\..\include\stdint.h +uksvep_2_2_v1\ecan.o: ../Drivers/CMSIS/Include/cmsis_version.h +uksvep_2_2_v1\ecan.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +uksvep_2_2_v1\ecan.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +uksvep_2_2_v1\ecan.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +uksvep_2_2_v1\ecan.o: d:\Keil\ARM\ARMCC\Bin\..\include\stddef.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h +uksvep_2_2_v1\ecan.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h 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../Core/Inc/stm32f1xx_hal_conf.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h +uksvep_2_2_v1\gpio.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h +uksvep_2_2_v1\gpio.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h +uksvep_2_2_v1\gpio.o: ../Drivers/CMSIS/Include/core_cm3.h +uksvep_2_2_v1\gpio.o: d:\Keil\ARM\ARMCC\Bin\..\include\stdint.h +uksvep_2_2_v1\gpio.o: ../Drivers/CMSIS/Include/cmsis_version.h +uksvep_2_2_v1\gpio.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +uksvep_2_2_v1\gpio.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +uksvep_2_2_v1\gpio.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +uksvep_2_2_v1\gpio.o: d:\Keil\ARM\ARMCC\Bin\..\include\stddef.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h +uksvep_2_2_v1\gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h +uksvep_2_2_v1\gpio.o: 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+uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h +uksvep_2_2_v1\lampa.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h +uksvep_2_2_v1\lampa.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h +uksvep_2_2_v1\lampa.o: ../Drivers/CMSIS/Include/core_cm3.h +uksvep_2_2_v1\lampa.o: d:\Keil\ARM\ARMCC\Bin\..\include\stdint.h +uksvep_2_2_v1\lampa.o: ../Drivers/CMSIS/Include/cmsis_version.h +uksvep_2_2_v1\lampa.o: ../Drivers/CMSIS/Include/cmsis_compiler.h +uksvep_2_2_v1\lampa.o: ../Drivers/CMSIS/Include/cmsis_armcc.h +uksvep_2_2_v1\lampa.o: ../Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +uksvep_2_2_v1\lampa.o: d:\Keil\ARM\ARMCC\Bin\..\include\stddef.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h +uksvep_2_2_v1\lampa.o: ../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h +uksvep_2_2_v1\lampa.o: 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