Начало

Bin/UKSSTMS320F28335.hex

@@ -0,0 +1,887 @@
+:20000000AA080000000000000000000000000000000000008BB2CB01000001B400FF00DE93
+:2000200000000000C1C081C1400101C3C003800241C201C6C006800741C70005C1C581C4C4
+:20004000400401CCC00C800D41CD000FC1CF81CE400E000AC1CA81CB400B01C9C0098008A5
+:2000600041C801D8C018801941D9001BC1DB81DA401A001EC1DE81DF401F01DDC01D801CD4
+:2000800041DC0014C1D481D5401501D7C017801641D601D2C012801341D30011C1D181D053
+:2000A000401001F0C030803141F10033C1F381F240320036C1F681F7403701F5C0358034E5
+:2000C00041F4003CC1FC81FD403D01FFC03F803E41FE01FAC03A803B41FB0039C1F981F8A3
+:2000E00040380028C1E881E9402901EBC02B802A41EA01EEC02E802F41EF002DC1ED81EC34
+:20010000402C01E4C024802541E50027C1E781E640260022C1E281E3402301E1C021802054
+:2001200041E001A0C060806141A10063C1A381A240620066C1A681A7406701A5C065806443
+:2001400041A4006CC1AC81AD406D01AFC06F806E41AE01AAC06A806B41AB0069C1A981A8A2
+:2001600040680078C1B881B9407901BBC07B807A41BA01BEC07E807F41BF007DC1BD81BCD3
+:20018000407C01B4C074807541B50077C1B781B640760072C1B281B3407301B1C071807054
+:2001A00041B00050C190819140510193C053805241920196C056805741970055C1958194A2
+:2001C0004054019CC05C805D419D005FC19F819E405E005AC19A819B405B0199C0598058A4
+:2001E00041980188C04880494189004BC18B818A404A004EC18E818F404F018DC04D804C33
+:20020000418C0044C184818540450187C047804641860182C042804341830041C181818051
+:200220004040FFFF92D700000000EEFFC0D80000E6127D391358FA3F6AEF74BF0000000074
+:200240000000000000000000000000000000000000000000FFFFF8D700000000FFFFF9D703
+:2002600000000000FFFF7DD800002003FEFF7ED800000000FA43FFFFBCD800000000FFFFE8
+:2002800003DF00000000FFFF04DF00000000FFFF05DF00000000FFFF06DF00000000FEFFD9
+:2002A00008DF000000000000FEFF0ADF000000000000FCFF0CDF000000000000000000008B
+:2002C000F4FFC2DD0000000000000000000044A00000F8A0000095A000009AA00000FFFFA3
+:2002E000DADD00000000FFFFDBDD00000000FFFFDCDD00000000FFFFDDDD00000000FEFF25
+:2003000014DF000000000000FEFF16DF000000000000FEFF18DF000000000000FEFF1ADF0E
+:20032000000000000000FFFF1CDF00000000FFFF1DDF00000000FFFF1EDF00000000FFFFD1
+:200340001FDF00000000FFFF20DF00000000FFFF2ADF00000000FEFF2CDF0000FCB30000E4
+:20036000FEFF2EDF0000FCB30000FEFF30DF000000000000FEFF32DF000000000000FFFFAC
+:2003800000D700000000FFFF44D300000100FFFFF6DD00000A00FFFFF7DD00000100FFFFC4
+:1203A00077D700000000FFFF7ED70000000000000000AA
+:2003B2000134000000801F76BF010D1A000806001F76BF010F1A0008060008FE03E2440130
+:2003D20003E24200AFE2440110E7080000776FE800F0007703E24600AFE2420201E8E8FA0F
+:2003F200AFE2440120E751000DE8B89E00E70800007703E24800AFE24600AFE24601AFE29F
+:20041200480200E3484100E78900007710E70800407664B302E8010250E800004076EEB0E8
+:2004320088FE06001B76F0FF0500BDA8BDA0BDC2BDC3BDAB00E2BD0003E2BD0003E2BD018C
+:2004520003E2BD0203E2BD0330E6000669FF42291656227601021F76770301562800237624
+:2004720000102676391110291A761F767403028A7FD094CC0080CEFF04ED69FF40765EA703
+:200492001F767C032092C0561D011F765E03000A1F765E030092145208681F765E03002BD1
+:2004B2001F765E03BF560101009B1F765E03009A15401F767403BD56A901028A7FD00052A7
+:2004D200B156A80194920190A8CA05EC69FF40760580046F69FF407600801F765F03390A52
+:2004F2001F765F0339920A521E681F765F03392B1F765F033D9206EC1F76BF010D1A0010A7
+:20051200056F1F76BF010B1A00101F765F033F9206EC1F76BF010D1A0040056F1F76BF018C
+:200532000B1A00401F76730324921F765F0339540EED1F767403028A944009EE1F76BF014C
+:200552000B1A00101F76BF010B1A0040009A1F76610330931F767403B056A901028300D42F
+:200572000052B156A40195920190A4CE0AEC1F765E0313921F765F0338961F765F033A2B8F
+:200592001F767403028A1F7661039492019030961F765F03380A1F765F0338921F765E034B
+:2005B200135420681F765F03382B1F765F033A0A1F765F033A4003EF019A026F009A1F7607
+:2005D2005F033B961F765F033A92079003EC019A026F009A1F765F033C961F76BF010F1AA0
+:2005F20000801F767403028A94CC4000C5FF1DEC1F767403028A1F765F0394CC8000C6FF30
+:200612003D961F767403028A1F765F0394CC8000C6FF3E961F767403028A1F765F0394CCFE
+:200632008000C6FF3F964D6F1F767403028A94400EEF1F765F033B921F765F033D961F7646
+:200652005F033E961F765F033F963B6F1F765E03154005EF1F765F033D2B056F1F765F03D3
+:20067200BF563D011F765E0315CC0400C1FF1F765F03B0563E0125ED1F765E0315CC08004D
+:20069200C2FF08EC1F765F033B921F765F033E96186F1F765E0315CC1000C3FF0FEC009A3F
+:2006B2001F765F0300D43C93B056A9011F765F030052B156A4013E7C046F1F765F033E2B5C
+:2006D200AFE2BE03AFE2BE02AFE2BE01AFE2BE0080E2BE00BE87BEC5BEC4BE83BE8A0300D0
+:2006F200F1FF1776027602FE1F765E031328E803008F94111F765E0316A80F021F765E03E8
+:20071200181E1F765E03008F983A1AA8412B419218521363013B008FC8D741850156A4002E
+:20073200C42B4185008FE0D70156A4004192C496410A41921852EF641F767C0300920152B0
+:2007520003EC025261ED1F765F03BF5608031F765F03BF5609031F765F03BF560A031F7619
+:200772005F03BF560B031F765F03BF560C031F765F03BF560D031F765F03BF5610041F76F6
+:200792005F03BF5611041F765F03BF5612041F765F03BF5613041F765F03BF5614021F76BF
+:2007B2005F03BF562C0D1F765F03BF5615021F765F03BF562D0C1F765F03BF5616021F7656
+:2007D2005F03BF562E0F1F765F03BF5617021F765F03BF562F0E1F767403028A0CDCC41A87
+:2007F20000401F767403028A0DDCC41A00401F767403028A0EDCC41A00401F767403028AD0
+:200812000FDCC41A00401F767C030092035203EC04522DED1F765F03BF5608031F765F0355
+:20083200BF5609031F765F03BF560A031F765F03BF560B031F765F03BF560C031F765F0340
+:20085200BF560D031F765F03BF560F041F765F03BF5610041F765F03BF5611041F765F030A
+:20087200BF5612041F765F03BF561304412B419204520E63013B008F9CD7035641010156E2
+:20089200A4000002C41E410A41920452F464412B41921C520E63013B008F48DC035641014A
+:2008B2000156A4000002C41E410A41921C52F464412B419220520E63013B008F00D8035645
+:2008D20041010156A4000002C41E410A41922052F464412B419228521063412D008F00D9FB
+:2008F2001235408FC0D80156A4001202407642B3410A41922852F264412B41920452106388
+:20091200412D008F00DC1235408FC0D80156A4001202407642B3410A41920452F264412B4E
+:20093200419218520D63013B008F80DC41850156A400C41800E0410A41921852F5641F76DE
+:200952005E03BF56120C82FE060002FE412B419202521863422B429208521063013B008F84
+:2009720082D7035641030156A40042850156A400C42B420A42920852F264410A4192025281
+:20099200EA64412B419218523663013B008FC8D741850156A400C4922AEC4193A892A2FF6F
+:2009B200008D82D7CBFFA894A3FFA9850156A0004192109BC00031B3A92D019B67FFC0991F
+:2009D200013B4192008D82D7189CA993A2FFCBFFA894A3FFA9850156A0004192189C109B80
+:2009F200C00031B3A92D019B67FFC099410A41921852CC64412B419203521463013B008F82
+:200A120082D74185408F8AD70156A4004192039CA9850156A500C492C596410A41920352BA
+:200A3200EE641F765E03031A80001F765E03BF5610701F767C030092035205631F765E03DB
+:200A5200111A0F001F765E03111A00E082FE060006FE467D459744A8419600520EEC448A43
+:200A7200013B4585C40F0362019A116F448A01020156C40046920B6F448AC40603ED009AAB
+:200A9200066F448A01024156C400469286FE060008FE44A84196448AC492459647961F7607
+:200AB2007403088A013B41850156A400C4CC0020CCFF14ED1F767403088A41850156A40043
+:200AD200C4CC00E046961F767403088A41850156A400469247CAC496096F1F767403088A00
+:200AF20041850156A4004792C49847CC0001C7FF00BE00D40CEC1F767403088341850156D6
+:200B1200A500C5CC0040CDFFB156A6011F7674030883A693B156A40141850156A500A4925F
+:200B3200019088FFC5CDFFFDA8CAC5961F767403088341850156A50000D41F765E03009B72
+:200B5200C5CC0002C8FFB056A8010053B156A40114921F765E03A9CD0100A4CB0191A9CCF2
+:200B7200FEFFA9CB149788FE060006FEA6A3437C42974196442B1F767C030592B056450A90
+:200B920003ED4528B80B4392425401D00A63649BC00020B3A828FF0FA99F4255B256A00083
+:200BB2001F767403013B008F48DC0883035641010156A40041850156A500C5CD0100A85DAD
+:200BD200A092459340765583005203EC441A0100A9A9448803ECA4A9C47E86FE060006FEA1
+:200BF20042974196442B452B013B008FF0DC41850156A400C492425422624185008FF0DC6B
+:200C12000156A400408F71D841850156A500C492C55415654185008FB0D80156A400408F5D
+:200C320075D841850156A500C492C5964185008FB0D80156A400C42BBF5645014185008F6B
+:200C5200F0DC0156A400C492425422654185008FF0DC0156A400408F71D841850156A50052
+:200C7200C492C55415624185008FB4D80156A400408F79D841850156A500C492C596008F7E
+:200C9200B4D841850156A400C42BBF56450145924EEC432B439204521463013B008F79D86E
+:200CB2004385408F75D80156A40043850156A500C5924494C4944496430A43920452EE6454
+:200CD2001F7661033D92049C445406631F7661033D92049C44961F7661033D92FC9C44545F
+:200CF20006651F7661033D92FC9C449644921F7661033D9602E85043C8E244010BE800003C
+:200D12004076EEB01F766103AFE23E0120E7400002E8010C4076EEB01F766103AFE23E0149
+:200D320010E740001F76610303E23E00013B008F71D841850156A4004292C4964185008FF6
+:200D5200B0D80156A400C40A4185008FB4D80156A400C40A1F766103AFE23E008CE600004C
+:200D720000770077A9BF120F86FE0600BDB212FE4396512B522B1F765E034392129E4B96B3
+:200D9200013B008FE0D743850156A4001F765E03C492129E4C96009B009A4B40BD56A901A1
+:200DB2000052B156A8014D974B92A0FF4E964E2D43930331A892A1FFCCFFA894A2FF019C37
+:200DD20082FFAB724F3F4E0804001F767403088A43850156A400C4CC0080CEFF19EC1F76A3
+:200DF2007403088A43850156A400C42B1F767403088A43850156A400C41A00801F7674035B
+:200E12000A8A43850156A400C42BEFFFBD024385008F46D70156A400C4E2C400007703E298
+:200E320046008CE6000000770077A9BF120FA9934B9240761C845196013B008F80DC4B9217
+:200E5200689CAFE246008CE60000A9850156A400A9BF120FC496008FC0D703564B01015605
+:200E7200A400408FC0D703564B010156A500A48BAFE2C500AFE2460120E7080002E85133DB
+:200E92000BE801004076EEB0AFE2C10110E74000007703E2C100008F00DC013B408FC0D744
+:200EB2004B2D12350156A40003564B010156A500AFE2C500407640B2013B008F40D88CE672
+:200ED200000043850156A400A9BF120FC4961F7662033C920DED4385008F40D80156A4002E
+:200EF200C488408FF0DC4B850156A500C57E1F767403028A7FD094CC1000C3FF10EC43850D
+:200F1200008F40D80156A4001F767403C4880A8A43850156A400C47EEFFF36024385008FAF
+:200F320040D80156A400408F80D8035643010156A500C8E2C400AFE2460120E70800AFE2E6
+:200F5200C50100E70800007703E2480003564B01008FB4D7408FB4D70156A40003564B016D
+:200F72000156A500AFE2C500AFE24801AFE2480200E75100A48B20E7080002E8D9290CE802
+:200F920001004076EEB0AFE2C10110E74000007703E2C100013B008FB4D703564B010156F1
+:200FB200A400AFE2C400407664B3013B008FA8D703564B010156A40003E2C4004D920BECF0
+:200FD200AFE248001F766203AFE6000003E23800EFFFD400AFE248001F766203AFE238011B
+:200FF20040760A801F76620303E23A00008F00D9432D12350156A400407640B201E8A9FD35
+:2010120008E899274076EEB003E24A001F7674030E8A013B43850156A400AFE24A011F7677
+:201032006203C8E2C400009A94E6010014ADB256A9013C96AFE24A0012E8401614AD05631D
+:2010520090E503E24A00512B43921F767403FF9C0A8AAFE24A008CE60000A9850156A400D8
+:20107200A9BF120FC4961F7674030A8A43850156A4005192C4961F766203408FB4D7AFE2F6
+:201092004802AFE2380103564E01008FB4D71F766203AFE248000156A400AFE2380310E7D7
+:2010B2009A0003564E010156A50010E70800A48B00E71100AFE2C50020E7080002E8D92969
+:2010D2000CE801004076EEB0AFE2C10110E74000007703E2C100013B008FB4D703564E0110
+:2010F2000156A400AFE2C400407664B3013B008FA8D703564E010156A40003E2C400008F9C
+:20111200A8D703564C010156A4001F7674030A83AFE2C4008CE600004F850156A500A9BF05
+:20113200120FC5961F767403008FA8D703564B010156A4000A834F92019CAFE2C4008CE695
+:201152000000A9850156A500A9BF120FC596008FA8D703564E010156A4001F767403AFE221
+:20117200C4008CE600000A8A4F92029CA9850156A400A9BF120FC49601E8A9FDAFE24800A0
+:2011920008E899274076EEB01F7674030C8A013B43850156A40001E861FCC8E2C4020EE8EC
+:2011B200696600E75100007794E6080014AD0565521A2000521A000103564B01008FA8D746
+:2011D2000156A400C406461E03564C01008FA8D70156A400AFE2C400AFE2460194E601007D
+:2011F20014AD096303564C01008FA8D70156A400C406461E03564E01008FA8D70156A40022
+:20121200AFE2C400AFE2460194E6010014AD096303564E01008FA8D70156A400C406461E08
+:201232001F767403088A43850156A400C4CC0040CDFF5096008FA8D703564B010156A4000B
+:2012520000D1AFE2C400AFE2460120E708004076EEB001E861F20EE8696694E6080014ADD7
+:2012720006651F7662033C92B056A101013B008F9CD71F765E0303564B0100D50156A400D8
+:201292001693A19240765583005207EC521A0400509203ED521A0001013B008FA8D703563B
+:2012B2004E010156A40000D1AFE2C400AFE2460120E708004076EEB001E861F20EE8696670
+:2012D20094E6080014AD06651F7662033C92B056A101013B008F9CD71F765E0303564E0102
+:2012F20000D50156A4001693A19240765583005207EC521A0400509203ED521A00014D92CF
+:201312003DED1F76620301E8A9FDAFE23A0008E899274076EEB01F7674030C8A013B438593
+:201332000156A400C8E2C401007794E6080014AD0765521A2000509203ED521A00011F76AB
+:20135200620301E8A9FDAFE23A0008E899274076EEB01F7674030E8A013B43850156A40015
+:20137200C8E2C401007794E6080014AD0763521A0800509203ED521A0001AD5C439292DCC9
+:201392004076758392FEBE8B060008FE419600520AED1F765E0314921F765E0315961F76B6
+:2013B2005E03142B1F765E0303561201415424651F767403088A013B41850156A400C4CCD0
+:2013D2000080CEFF19EC1F767403088A41850156A400C42B1F767403088A41850156A400FC
+:2013F200C41A00801F7674030A8A41850156A400C42BEFFFD000013B008F46D7418501566A
+:20141200A400C4E2C400007703E244001F767403028A7FD094CC1000C3FF0EEC1F767403ED
+:201432000A8A8CE6000041850156A400A9BF120FC496EFFFB0004185008F40D8AFE244020E
+:201452000156A400408F80D8807658D803564101C8E2C4010156A50041850156A60020E762
+:201472005100AFE2C50200E75100C8E2C60202E8401C10E751000CE8000020E708000077FF
+:2014920003E244001F76740350E800480A8A8CE6000041850156A400A9BF120FC496AFE24A
+:2014B20044008CE6000000770077A9BF120F4596472B008FC8D741850156A400C492035206
+:2014D20003ED4828F4014185008FC8D70156A400C4920452B15648644185008F46D701568E
+:2014F200A400AD8887DEC493485C41924076E283479245ED1F767403088A013B41850156B1
+:20151200A400C4CC0040CDFF46961F7674030C8A41850156A400C492FB9C45540B631F76B1
+:201532007403088A41850156A400C4CC2000C4FF0AED1F7674030C8A41850156A400C492AC
+:2015520045540C63471A2000469219ED471A00011F765E03141A0400126F1F7674030E8A63
+:2015720041850156A400C49245540963471A1000469205ED1F765E03141A0800479205EC0C
+:201592001F765E03141A1000AD5C419287DC4076758388FE06001B76F0FF00E2BD0030E657
+:2015B2000006422916562376391110292576006F1B76F0FF00E2BD0030E600064229165604
+:2015D2002376390110292576006F1B76F0FF00E2BD0030E6000642291656237639011029C5
+:2015F2002576006F1B76F0FF00E2BD0030E60006422916562376390110292576006F1B7616
+:20161200F0FF00E2BD0030E600064229165610292576006F1B76F0FF00E2BD0030E60006B9
+:201632004229165610292576006F1B76F0FF00E2BD0030E600064229165610292576006F29
+:201652001B76F0FF00E2BD0030E600064229165610292576006F1B76F0FF00E2BD0030E6EE
+:2016720000064229165610292576006F1B76F0FF00E2BD0030E60006422916561029257652
+:20169200006F1B76F0FF00E2BD0030E600064229165610292576006F1B76F0FF00E2BD0055
+:2016B20030E600064229165610292576006F1B76F0FF00E2BD0030E6000642291656102997
+:2016D2002576006F1B76F0FF00E2BD0030E600064229165610292576006F1B76F0FF00E237
+:2016F200BD0030E600064229165610292576006F1B76F0FF00E2BD0030E6000642291656D3
+:2017120010292576006F1B76F0FF00E2BD0030E600064229165610292576006F1B76F0FF9F
+:2017320000E2BD0030E600064229165610292576006F1B76F0FF00E2BD0030E6000642291C
+:20175200165610292576006F1B76F0FF00E2BD0030E6000602FE422916561F76330022923A
+:20177200419623760100267601011F7633002218FA001F7633002128FFFF1029103B1F7624
+:201792003300419222962576006F1B76F0FF00E2BD0030E6000602FE422916561F76330095
+:2017B2002292419623760100267601011F7633002218F8001F7633002128FFFF1029103BC7
+:2017D2001F763300419222962576006F1B76F0FF00E2BD0030E6000602FE422916561F76F3
+:2017F200330022924196237601011F76330022921F763300222B1F7633002128FFFF1029A5
+:20181200103B1F763300419222962576006F1B76F0FF00E2BD0030E6000602FE42291656FC
+:201832001F76330022924196237601011F763300221868001F7633002128FFFF1029103BAB
+:201852001F763300419222962576006F1B76F0FF00E2BD0030E6000602FE422916561F7672
+:2018720033002292419623760100267601011F763300221848001F7633002128FFFF1029CE
+:20189200103B1F763300419222962576006F1B76F0FF00E2BD0030E6000602FE422916567C
+:2018B2001F7633002292419623760100267601011F76330022921F763300222B1F76330032
+:2018D2002128FFFF1029103B1F763300419222962576006F1B76F0FF00E2BD0030E6000693
+:2018F20002FE422916561F7633002292419623760100267601011F763300221878001F7665
+:2019120033002128FFFF1029103B1F763300419222962576006F1B76F0FF00E2BD0030E625
+:20193200000602FE422916561F7633002492419623760200267600001F76330024180E001A
+:201952001F7633002128FFFF1029103B1F763300419224962576006F1B76F0FF00E2BD0064
+:2019720030E6000602FE422916561F7633002492419623760200267600001F7633002418D2
+:201992000C001F7633002128FFFF1029103B1F763300419224962576006F1B76F0FF00E2D5
+:2019B200BD0030E6000602FE422916561F7633002492419623760200267600001F76330011
+:2019D200241808001F7633002128FFFF1029103B1F763300419224962576006F1B76F0FF3F
+:2019F20000E2BD0030E6000602FE422916561F7633002492419623760200267600001F7622
+:201A1200330024921F763300242B1F7633002128FFFF1029103B1F76330041922496257631
+:201A3200006F1B76F0FF00E2BD0030E6000602FE422916561F763300249241962376020023
+:201A5200267600001F76330024180F001F7633002128FFFF1029103B1F76330041922496DD
+:201A72002576006F1B76F0FF00E2BD0030E6000602FE422916561F7633002492419623764A
+:201A92000200267600001F76330024181F001F7633002128FFFF1029103B1F763300419245
+:201AB20024962576006F1B76F0FF00E2BD0030E6000602FE422916561F76330026924196E7
+:201AD2002376040026763D011F76330026183E001F7633002128FFFF1029103B1F763300DE
+:201AF200419226962576006F1B76F0FF00E2BD0030E6000602FE422916561F7633002692A9
+:201B120041962376040026763D011F76330026921F763300262B1F7633002128FFFF102984
+:201B3200103B1F763300419226962576006F1B76F0FF00E2BD0030E6000602FE42291656D5
+:201B52001F763300269241962376040026763D011F76330026921F763300262B1F76330044
+:201B72002128FFFF1029103B1F763300419226962576006F1B76F0FF00E2BD0030E60006EC
+:201B920002FE422916561F763300269241962376040026763D011F763300261826001F76CD
+:201BB20033002128FFFF1029103B1F763300419226962576006F1B76F0FF00E2BD0030E67F
+:201BD200000602FE422916561F763300269241962376040026763D011F763300261826001C
+:201BF2001F7633002128FFFF1029103B1F763300419226962576006F1B76F0FF00E2BD00C0
+:201C120030E6000602FE422916561F763300269241962376040026763D011F763300269271
+:201C32001F763300262B1F7633002128FFFF1029103B1F763300419226962576006F1B76F4
+:201C5200F0FF00E2BD0030E6000602FE422916561F76330028924196237608002676080152
+:201C72001F763300281802001F7633002128FFFF1029103B1F763300419228962576006F52
+:201C92001B76F0FF00E2BD0030E6000602FE422916561F7633002A92419623760800267688
+:201CB20008011F76330028921F763300282B1F7633002128FFFF1029103B1F76330041923E
+:201CD20028962576006F1B76F0FF00E2BD0030E6000602FE422916561F76330028924196BF
+:201CF20023760800267608011F763300281803001F7633002128FFFF1029103B1F76330026
+:201D1200419228962576006F1B76F0FF00E2BD0030E6000602FE422916561F763300289282
+:201D3200419623760800267608011F763300281803001F7633002128FFFF1029103B1F7641
+:201D52003300419228962576006F1B76F0FF00E2BD0030E6000602FE422916561F763300C9
+:201D72002892419623760800267608011F76330028180F001F7633002128FFFF1029103BD0
+:201D92001F763300419228962576006F1B76F0FF00E2BD0030E6000602FE422916561F7627
+:201DB20033002892419623760800267608011F76330028180F001F7633002128FFFF1029A8
+:201DD200103B1F763300419228962576006F1B76F0FF00E2BD0030E6000602FE4229165631
+:201DF2001F7633002A92419623761000267610011F7633002A1802001F7633002128FFFF05
+:201E12001029103B1F76330041922A962576006F1B76F0FF00E2BD0030E6000602FE422921
+:201E320016561F7633002A92419623761000267610011F7633002A921F7633002A2B1F763D
+:201E520033002128FFFF1029103B1F76330041922A962576006F1B76F0FF00E2BD0030E6D8
+:201E7200000602FE422916561F7633002C92419623762000267639011F7633002C18320049
+:201E92001F7633002128FFFF1029103B1F76330041922C962576006F1B76F0FF00E2BD0017
+:201EB20030E6000602FE422916561F7633002C92419623762000267639011F7633002C92AB
+:201ED2001F7633002C2B1F7633002128FFFF1029103B1F76330041922C962576006F1B7646
+:201EF200F0FF00E2BD0030E6000602FE422916561F7633002C924196237620002676390163
+:201F12001F7633002C1833001F7633002128FFFF1029103B1F76330041922C962576006F76
+:201F32001B76F0FF00E2BD0030E6000602FE422916561F7633002C924196237620002676CB
+:201F520039011F7633002C1837001F7633002128FFFF1029103B1F76330041922C96257667
+:201F7200006F1B76F0FF00E2BD0030E6000602FE422916561F7633002C92419623762000B8
+:201F9200267639011F7633002C1822001F7633002128FFFF1029103B1F76330041922C963B
+:201FB2002576006F1B76F0FF00E2BD0030E6000602FE422916561F7633002C9241962376FD
+:201FD2002000267639011F7633002C921F7633002C2B1F7633002128FFFF1029103B1F762C
+:201FF200330041922C962576006F1B76F0FF00E2BD0030E6000602FE422916561F76330023
+:202012002E92419623764000267600001F7633002E183E001F7633002128FFFF1029103BC3
+:202032001F76330041922E962576006F1B76F0FF00E2BD0030E6000602FE422916561F767E
+:2020520033002E92419623764000267600001F7633002E1838001F7633002128FFFF1029A1
+:20207200103B1F76330041922E962576006F1B76F0FF00E2BD0030E6000602FE4229165688
+:202092001F7633002E92419623764000267600001F7633002E1838001F7633002128FFFF05
+:2020B2001029103B1F76330041922E962576006F1B76F0FF00E2BD0030E6000602FE42297B
+:2020D20016561F7633002E92419623764000267600001F7633002E1820001F76330021286F
+:2020F200FFFF1029103B1F76330041922E962576006F1B76F0FF00E2BD0030E6000602FEA8
+:20211200422916561F7633002E92419623764000267600001F7633002E1828001F76330004
+:202132002128FFFF1029103B1F76330041922E962576006F1B76F0FF00E2BD0030E600061E
+:2021520002FE422916561F7633002E92419623764000267600001F7633002E921F76330072
+:202172002E2B1F7633002128FFFF1029103B1F76330041922E962576006F1B76F0FF00E296
+:20219200BD0030E6000602FE422916561F7633003092419623768000267600001F7633009F
+:2021B2002C921F7633002C2B1F7633002128FFFF1029103B1F763300419230962576006F32
+:2021D2001B76F0FF00E2BD0030E6000602FE422916561F76330030924196237680002676C5
+:2021F20000001F763300301801001F7633002128FFFF1029103B1F7633004192309625762D
+:20221200006F1B76F0FF00E2BD0030E6000602FE422916561F7633003092419623768000B1
+:20223200267600001F7633002C1823001F7633002128FFFF1029103B1F76330041923096CD
+:202252002576006F1B76F0FF00E2BD0030E6000602FE422916561F76330030924196237656
+:202272008000267600001F763300301803001F7633002128FFFF1029103B1F7633004192EF
+:2022920030962576006F1B76F0FF00E2BD0030E6000602FE422916561F76330032924196E7
+:2022B20023760001267600011F76330032921F763300322B1F7633002128FFFF1029103B91
+:2022D2001F763300419232962576006F1B76F0FF00E2BD0030E6000602FE422916561F76D8
+:2022F20033003292419623760001267600011F76330032921F763300322B1F763300212805
+:20231200FFFF1029103B1F763300419232962576006F1B76F0FF00E2BD0030E6000602FE81
+:20233200422916561F7633003292419623760001267600011F76330032921F763300322B69
+:202352001F7633002128FFFF1029103B1F763300419232962576006F1B76F0FF00E2BD004C
+:2023720030E6000602FE422916561F7633003292419623760001267600011F763300329232
+:202392001F763300322B1F7633002128FFFF1029103B1F763300419232962576006F1B7675
+:2023B200F0FF00E2BD0030E6000602FE422916561F763300329241962376000126760001F0
+:2023D2001F76330032921F763300322B1F7633002128FFFF1029103B1F7633004192329644
+:2023F2002576006F1B76F0FF00E2BD0030E6000602FE422916561F763300329241962376B3
+:202412000001267600011F76330032921F763300322B1F7633002128FFFF1029103B1F7633
+:202432003300419232962576006F1B76F0FF00E2BD0030E6000602FE422916561F763300D8
+:202452003292419623760001267600011F76330032183F001F7633002128FFFF1029103BB4
+:202472001F763300419232962576006F1B76F0FF00E2BD0030E6000602FE422916561F7636
+:2024920033003292419623760001267600011F76330032187F001F7633002128FFFF10294C
+:2024B200103B1F763300419232962576006F1B76F0FF00E2BD0030E6000602FE4229165640
+:2024D2001F7633003892419623760008267600001F76330038189E001F7633002128FFFF7F
+:2024F2001029103B1F763300419238962576006F1B76F0FF00E2BD0030E6000602FE42292D
+:2025120016561F7633003892419623760008267600001F76330038189C001F7633002128D2
+:20253200FFFF1029103B1F763300419238962576006F1B76F0FF00E2BD0030E6000602FE59
+:20255200422916561F7633003892419623760008267600001F763300381890001F7633007C
+:202572002128FFFF1029103B1F763300419238962576006F1B76F0FF00E2BD0030E60006D0
+:2025920002FE422916561F7633003892419623760008267600001F763300381890001F766F
+:2025B20033002128FFFF1029103B1F763300419238962576006F1B76F0FF00E2BD0030E663
+:2025D200000602FE422916561F7633003892419623760008267600001F76330038921F763F
+:2025F2003300382B1F7633002128FFFF1029103B1F763300419238962576006F1B76F0FFAD
+:2026120000E2BD0030E6000602FE422916561F7633003892419623760008267600001F76DB
+:20263200330038189F001F7633002128FFFF1029103B1F763300419238962576006F1B76CF
+:20265200F0FF00E2BD0030E6000602FE422916561F76330038924196237600082676000041
+:202672001F76330038921F763300382B1F7633002128FFFF1029103B1F763300419238968F
+:202692002576006F1B76F0FF00E2BD0030E60006422916562576006F1B76F0FF00E2BD00E3
+:2026B20030E60006422916562576006F1B76F0FF00E2BD0030E60006422916562576006FEF
+:2026D2001B76F0FF0500BDA8BDA0BDC2BDC3BDAB00E2BD0003E2BD0003E2BD0103E2BD02B2
+:2026F20003E2BD0330E6000602FE69FF422916561F7633003292419623760001267600012E
+:202712001F76330032921F763300322B1F7633002128FFFF1029008F00D069FF4076489752
+:20273200008F00D04076C192103B1F7633004192329682FEAFE2BE03AFE2BE02AFE2BE01FE
+:20275200AFE2BE0080E2BE00BE87BEC5BEC4BE83BE8A0300F1FF177602761B76F0FF0500A8
+:20277200BDA8BDA0BDC2BDC3BDAB00E2BD0003E2BD0003E2BD0103E2BD0203E2BD0330E6DB
+:20279200000602FE69FF422916561F7633003292419623760001267600011F7633003292BC
+:2027B2001F763300322B1F7633002128FFFF1029008F80D369FF40764897008F80D3407623
+:2027D200C192103B1F7633004192329682FEAFE2BE03AFE2BE02AFE2BE01AFE2BE0080E2C2
+:2027F200BE00BE87BEC5BEC4BE83BE8A0300F1FF177602761B76F0FF0500BDA8BDA0BDC278
+:20281200BDC3BDAB00E2BD0003E2BD0003E2BD0103E2BD0203E2BD0330E6000602FE69FF0D
+:20283200422916561F7633003292419623760001267600011F76330032921F763300322B64
+:202852001F7633002128FFFF1029008F00D069FF40764897008F00D040765E94103B1F76DB
+:2028720033004192329682FEAFE2BE03AFE2BE02AFE2BE01AFE2BE0080E2BE00BE87BEC5CE
+:20289200BEC4BE83BE8A0300F1FF177602761B76F0FF0500BDA8BDA0BDC2BDC3BDAB00E293
+:2028B200BD0003E2BD0003E2BD0103E2BD0203E2BD0330E6000602FE69FF422916561F76CB
+:2028D20033003292419623760001267600011F76330032921F763300322B1F76330021281F
+:2028F200FFFF1029008F80D369FF40764897008F80D340765E94103B1F7633004192329678
+:2029120082FEAFE2BE03AFE2BE02AFE2BE01AFE2BE0080E2BE00BE87BEC5BEC4BE83BE8AF0
+:202932000300F1FF1776027604FE42A8428AC48AECCC4000C5FF16ED1F7633002192A9CDD7
+:20295200FFFEC7FF01901F7633000150019087FFA8CA2196428AC48A0BDCC41A4000EFFFAB
+:202972008001428AC48AFC92FF904396428AC48AECCC8000C6FF0AEC428AC48ACC18DFFFCB
+:20299200428AC48ACC1A2000D26F428A008DA0019492CDED428A008D3B039492015216EDD7
+:2029B200428A008D3D03BF569401428A0002008D3403941E428A008D3F03942B428A008DCB
+:2029D2003E03942B428A0DD0942B428A008D3F039492ADED428A008D3D039492C156E2006A
+:2029F200428A008D3E0394924BED1F760403029243541FEC1F7677033792435403ED00524A
+:202A120018ED428A008D31039492435406ED428A008D330394920DED1F7677033692435445
+:202A320024ED005222EC428A008D330394921DED428A4392008D320394964206008F3E03AF
+:202A52000156A400019BC492A995C497428A013BA9850156A4000ED043929496089A428A62
+:202A720040764C95EFFF64FF428A008D3F03BF569401428A008D3D03942BEFFF59FF420631
+:202A9200008F3E030156A400019BC492A995C497428A013BA9850156A4000ED043929496C0
+:202AB200428A008D3E039492075210ED428A0DD0949210520BED428A008D3303949206ED1D
+:202AD20043921F765C030A9C1096428A008D3E03949202523DED428A43920DD09496428A1D
+:202AF200949203521668428A94924252126642839558008F00D7949203520B68428A0DD01E
+:202B1200949233521CED428A0CD094923A5217EC428A099A40764C95428A008D3E03942B33
+:202B3200428A008D3D03BF569401428A008D3F03942B428A0DD0942BEFFFFAFE428A0DD0EF
+:202B52009492335205ED428A008D3D03942B42830DD095584283008F00D79492008D3E03C0
+:202B7200955408694283008F90019585A40FE8FFDFFE428A099A40764C95428A008D3D03D4
+:202B9200942B428A008D3F03BF569401428A008DA001BF569401428A0DD0942BEFFFC8FE5F
+:202BB2004283F5C4208F0000A9A8A60F08664283F5C42F8F0000A9A8A60F08674283208F3D
+:202BD2000000F5A842830AD095A8428A0CD094923A52C056ADFE428A008DA001949208EC3B
+:202BF200428A008D3F03BF569401EFFFA1FE4206008F34030156A400C4C4A692019001DEB8
+:202C1200C4C2449609EC4283F58AA9A80109F51E4392C498066F428AF48A03564308C496AD
+:202C3200428A008D34039406428AE40FE8FF80FE428A339A0FD09496428A0CD09496099A1D
+:202C5200428A40764C95428A008D3F03BF569401428A008DA001BF569401EFFF69FE84FE3F
+:202C7200060004FE42A8428A008D3A0394923CED4206008F38030156A4000102C407C41EAE
+:202C9200428A008D3603940F0568428AC48ABF56E402428A08D0948A4283849295A8428AC5
+:202CB200C48A09D09496428A4283008D36039406008D3803950F5766428AC48AE4CC40008D
+:202CD200C5FFFBEC428A099A40764C95428AD492025205ED1F76BF01081A0400428A008DE5
+:202CF2009E01942B406F4206008F38030156A400C4C4A692019001DEC4C24396428A428388
+:202D1200008D36039406008D3803950F0566428AC48ABF56E40243920DEC428A08D0948AC5
+:202D32004283849295A8428AC48AFF9009D094960B6F428A428308D0948AC58309D0C49245
+:202D5200A7FFFF909596428A4283008D36039406008D3803950F0766428AC48AE4CC40002D
+:202D7200C5FFFBEC1F7633002192A9CDFFFEC7FF01901F7633000150019087FFA8CA2196F8
+:202D920084FE060002FE412B419246520D63013B008F00D741850156A4004192C496410A77
+:202DB20041924652F5641F765C03BF56330C1F765C03BF56340C1F765C03BF5635081F76D1
+:202DD2005C03BF5636091F765C03BF5637101F765C03BF5638081F765C03BF56390C1F76B2
+:202DF2005C03BF563A0C1F765C03BF563B051F764D030492FE9C1F765C033D961F764D03FD
+:202E120004921F765D03FF9C01961F765C03BF563E081F765C03BF5603081F765C03BF5677
+:202E320006081F765C03BF56100D1F765C03BF56051B1F765C03BF563C1282FE060004FE44
+:202E5200439642A8439208520BED089A428A01D54E9B40760797428A008D3B03942B4392CA
+:202E720009520CED089A428A01D54E9B40760797428A008D3B03BF56940184FE060008FE9C
+:202E9200461E44A042A8472B471B30750566470A471B3075FD69428AD492025205ED1F763F
+:202EB200BF010818FBFF472B471B10270566470A471B1027FD69428A4606008D3603941ED0
+:202ED200428A440608D00109941E428A008D3A03942B428AC48AE4CC4000C5FFFBEC428A60
+:202EF200089A40764C95428A008D38030102941E460F0C67428AC48ABF56E401428AC4834F
+:202F1200448A09D0C4929596216F4283448AC58309D0C4929596428AC48AE4CC4000C5FFE4
+:202F3200FBEC472B471BE8030566470A471BE803FD69428A099A40764C95428AD4920252DE
+:202F520005ED1F76BF01081A0400009A88FE060006FE461E44A042A8428AD492025205ED1E
+:202F72001F76BF010818FBFF428A4606008D3603941E428A08D04406941E428A008D3A030A
+:202F9200BF569401428AC48AE4CC4000C5FFFBEC428A089A40764C95428A008D3803010224
+:202FB200941E428AC48ABF56E4014283448A09D0C583C492A7FFFF909596009A86FE0600AB
+:202FD20006FE441E42A81F765D0384E2440188E23A0050E809404076EEB088E60000007791
+:202FF20003E24600428AC48A4692A7FFFF90D496428AC48A4692FF90DC9686FE060002FE86
+:2030120041961F764D0304961F764003BF5602011F764E03BF56020282FE060008FE441E6B
+:20303200417C4192015231ED008F50701F76400300A8008F00D048A822761F76BE0109CC9E
+:20305200FFF3A91A00041F76BE0109961F76BE0109CCFFFCA91A00011F76BE0109961F7642
+:203072003700008F8D9100A81F763700008F279202A81F763300321A01001F763300321ACB
+:203092000200237600011A764192025239ED008F50771F764E0300A8008F80D348A8227657
+:2030B2001F76BE0107CCFFCFA91A00201F76BE0107961F76BE0107CCFF3FA91A00801F76F8
+:2030D200BE0107961F76BE011618CFFF1F76BE011A1A04001F763700008FDA9104A81F769F
+:2030F2003700008F749206A81F763300321A04001F763300321A0800237600011A76488A14
+:203112004192D496488AC406461E01D569FF089A488A4E9B40760797468A0CDCC41A00409B
+:20313200468A0CDCC418FFDF468ACC18BFFF468ACC18DFFF468ACC18F7FF468ACC18FBFFAF
+:20315200468ACC1A0200468ACC1A0100468A0ADCC418FFBF468A0BDCC4CCE0FF0150C496CD
+:203172004076EF94488A440640760D96488AD492025205ED1F76BF01081A0400488AC48A76
+:20319200BF56E402099A488A40764C95488A0CD0942B488A008D9E01942B488A008D330357
+:2031B200942B468A0BDCC41A4000468ACC1A200088FE060008FE457D4497439642A8428AD5
+:2031D200C406481E43921D6509521B63488AFF9CC4CDF8FF0790A8CAC496136F488AC418F5
+:2031F200DFFF166F488AC41A2000488AC418BFFF0F6F488AC41A2000488AC41A4000086F69
+:2032120044924552F7EC4E52EAEC4F52ECEC4592015204ED488AC4187FFF4592025204EDFA
+:20323200488AC41A8000488AC418EFFF488AC418F7FF88FE060002FE42A8428A0002008D3B
+:203252004203941E82FE060002FE42A882FE060002FE412B4192805209674158008F80DC6A
+:20327200942B410A41928052F9681F767303BF5624081F767C0302921F7673033E961F76C4
+:203292007303BF56250A1F767303BF5626C91F767C030092015203EC02526DED1F767403B1
+:2032B2000C8ABF56C43C1F7674030C8ABF56CC3C1F7674030C8ABF56D43C1F7674030C8A29
+:2032D200BF56DC3C1F7674030C8ABF56E43C1F7674030C8ABF56EC3C1F7674030C8A08D07F
+:2032F200BF5694321F7674030C8A09D0BF5694321F7674030C8A0AD0BF5694321F76740328
+:203312000C8A0BD0BF5694321F7674030E8ABF56C4321F7674030E8ABF56CC321F767403DD
+:203332000E8ABF56D4321F7674030E8ABF56DC321F7674030E8ABF56E4321F7674030E8A8E
+:20335200BF56EC321F7674030E8A08D0BF56942D1F7674030E8A09D0BF56942D1F76740377
+:203372000E8A0AD0BF56942D1F7674030E8A0BD0BF56942D1F767C030092035203EC04525E
+:2033920077ED1F7674030C8ABF56C4321F7674030C8ABF56CC321F7674030C8ABF56D43298
+:2033B2001F7674030C8ABF56DC321F7674030C8ABF56E43C1F7674030C8ABF56EC3C1F76EB
+:2033D20074030C8ABF56FC321F7674030C8A08D0BF5694321F7674030C8A09D0BF569432E0
+:2033F2001F7674030C8A0AD0BF5694321F7674030C8A0BD0BF56943C1F7674030E8ABF5649
+:20341200C42D1F7674030E8ABF56CC2D1F7674030E8ABF56D42D1F7674030E8ABF56DC2D7B
+:203432001F7674030E8ABF56E4321F7674030E8ABF56EC321F7674030E8ABF56FC2D1F765D
+:2034520074030E8A08D0BF56942D1F7674030E8A09D0BF56942D1F7674030E8A0AD0BF56B7
+:20347200942D1F7674030E8A0BD0BF569432412B41920C5213674158008FC8D794920AED24
+:203492001F7674030C8A942B41581F7674030E8A942B410A41920C52EF681F767C0306923E
+:2034B2002EECBF56410C41921052116741581F7674030C8A9428880941581F7674030E8A0C
+:2034D2009428B605410A41921052F1681F767403028A0CDCC41A00401F767403028A0DDC6B
+:2034F200C41A00401F767403028A0EDCC41A00401F767403028A0FDCC41A004082FE0600D5
+:20351200BDB202FE008F80DC1F76740302A81F76740308A81F767403008F98DC0AA81F7677
+:203532007403008FB0DC0CA81F767403008FC8DC0EA8A9287E3FA8280201008F40DD40767B
+:20355200D09F008F40DD809A4076EEAF42961F7677030092425422ED421BFFFF1FEC1F76B8
+:2035720076033E921F767C03025418ED412B419280520E671F767403415841590283008FA8
+:2035920040DD94929D96410A41928052F4681F767403028A7FD0942B0A6F407655971F7601
+:2035B2007403028A7FD0942B407629991F767C03009203521F63412B419204521B670C9C34
+:2035D200A958408F40D8008FC0D7410E30FFC8E295000156A40003E2C4008CE6000041585F
+:2035F200408FF0DCA9BF120F9596410A41920452E76882FEBE8B060002FE422B412B41922C
+:203612008052156741581F7674030283008F40DD9592945408EC1F7674030283959294968F
+:20363200BF564201410A41928052ED68429211EC008F40DD809A4076EEAF1F76770300964C
+:20365200A9287E3F008F40DDA82802014076859F82FE06000CFE1F767C0301920152C056D1
+:203672006201442B44920C52E3FFAE000356440245964592407606AF429620FFF401407644
+:20369200FDB34592019C407606AF419620FFF4014076FDB34592469C407606AF439620FF1C
+:2036B200F4014076FDB3029AAD5C82DC4076EEAF435412EC013B008FC8D744850156A40084
+:2036D200C492035206ED42284A01BF56411E046F422B4128110142924696C4E241000077A8
+:2036F20003E24A004592029C407606AF429620FFF4014076FDB34592039C407606AF41969F
+:2037120020FFF4014076FDB34592489C407606AF439620FFF4014076FDB3029AAD5C82DCA1
+:203732004076EEAF435413EC013B008FC8D744850156A400C492035206ED4228A00F412840
+:203752006801056F4228CE0E4128D90142924796C4E24100007703E24C00013B008F40D8CE
+:2037720044850156A4004692C496AFE24A00008F58D88CE6000044850156A400A9BF120FE8
+:20379200C4964792AFE24A00AFE24C01469E20E70800A985A9BD160F0077007700770077A3
+:2037B20089E609004076EEB0013B008F80D8035644010156A40003E2C400440A44920C5244
+:2037D200E4FF56FFBF56440C44921052E3FF83000356440245964592407606AF429620FFEA
+:2037F200F4014076FDB34592019C407606AF419620FFF4014076FDB34592469C407606AF08
+:20381200439620FFF4014076FDB3029AAD5C82DC4076EEAF435404EC4228FF07412B4292B6
+:203832004696C4E24100007703E24A004592029C407606AF429620FFF4014076FDB3459204
+:20385200039C407606AF419620FFF4014076FDB34592489C407606AF439620FFF401407632
+:20387200FDB3029AAD5C82DC4076EEAF435404EC42280609412B42924796C4E241000077B5
+:2038920003E24C00013B008F40D844850156A4004692C496AFE24A00008F58D88CE6000000
+:2038B20044850156A400A9BF120FC49602E8D123C8E247004076EEB0013B008F80D80356B0
+:2038D20044010156A40003E2C400440A4492105280641F767C03009203522463442B4492BC
+:2038F200045220630C9C013B408F40D8A9850156A500008FC0D7035644010156A400C8E27F
+:20391200C500408FF0DC03E2C4008CE6000044850156A500A9BF120FC596440A44920452F7
+:20393200E2648CFE0600BDB206FE42A8428A11D0949244964283428A12D113D003569D0840
+:2039520094CA4596428A1F767703008DA10137929496428A008DA201BF569403428A008D1E
+:20397200A301035645019496462B459246542C691F767403028A46924494A95894CC00FFA9
+:20399200C7FFA988008DA10103564601039CA9804206A70DA98A947E1F767403028A4692D6
+:2039B2004494A9589492FF90008DA101A98803564601049CA9804206A70DA98A947E460A0D
+:2039D20045924654D6664328FFFF008FA1014206435D0156A40003564501039CA90E407600
+:2039F2009CAF4396008DA10103564501039CA9884206A60DA98A4392FF9094960356450198
+:203A1200049CA9884206A60DA98A4392A7FFFF90949603564501059CA9884206A60DA98AC2
+:203A3200942B03564501069CA9884206A60DA98A942B03564501079CA9884206A60DA98AB5
+:203A5200942B03564501089CA9884206A60DA98A942B428A008D9E01BF569401408FA10121
+:203A7200428A42060156A50003564501089CA90E40766C9586FEBE8B0600BDB206FE42A843
+:203A9200452B459208521167458842060ED0A60DA98A42069480408DA101A60DA98A9C7F56
+:203AB200450A45920852F168428A11D0949243964283428A12D113D003569D0894CA4496E2
+:203AD20043581F767403028A44929496428A008D9E01BF569401408FA1014206428A015623
+:203AF200A5000A0240766C9586FEBE8B060002FE421E428AC49282FE060004FE437C421E50
+:203B1200428A4392C49684FE0600BDB206FE42A8428A008DA001949271EC428A942B428ADF
+:203B32000FD094924396013B4385008F00D70156A400C492035209684385008F00D701568F
+:203B5200A400C41B90011069428AD492025205ED1F76BF01081A0400428A099A40764C95CD
+:203B7200A928FFFF4D6F4392335207ED428A43920CD094964392446F4385008F00D70156A6
+:203B9200A400C492FE9CA9804206008F00D7A70DA61E43850156A4000ED10ED0C492FF9CBF
+:203BB200A9804206A70DA98A03569C08A68A94CA44964528FFFF428A408F00D7438501563A
+:203BD200A5000EDCC592455DFE9CA90E40769CAF4596445407ED428A43920CD09496439216
+:203BF2000F6F428AD492025205ED1F76BF01081A0400428A099A40764C95A928FFFF86FEE9
+:203C1200BE8B0600BDB204FE439642A8428A4283008D3203408DA10194929D96428A008D9B
+:203C3200A20143929496000201195AFF443F008FA101445D42060156A400020240769CAFBE
+:203C52004496428A008DA301FF909496008DA401428A4492A7FFFF909496428A008DA50190
+:203C7200942B428A008DA601942B408FA101428A42060156A500060240766C9584FEBE8BA9
+:203C920006000AFE461E44A846C5AC281F00013B44C4A7062256A70740FF0156A60048C259
+:203CB200488AC49249960202421E4606C000E0B258FF04EC49CCFF00046F4992A7FFFF900B
+:203CD2008AFE060004FE42A8428A13D09492FF90A90E441E428A12D09492FF90A9884406FD
+:203CF20037FFA6AF441E428A11D09492FF90A988440637FFA6AF441E428A10D09492FF909A
+:203D1200A988440637FFA6AF441E428A17D042839492FF90A90EE51E428A16D042C44283C5
+:203D32009492FF90A980E50637FFA7AFE61E428A15D0428342C49492FF90A980E50637FF9D
+:203D5200A7AFE61E428A14D0428342C49492FF90A980E50637FFA7AFE61E428A02020156FC
+:203D7200E400428A4406F41E428A0AD04406941E1F767C03BF561E013A9A428A40762F9C1A
+:203D920084FE0600BDB204FE42A8428A42830AD0E4060219958A40766E9C428A42C4A95D07
+:203DB200E4060119968A40766E9C0356A908A5944496428A4283408D32030ED09C92959626
+:203DD200428A0FD0BF5694334328FFFF428A0202435D0EDC40769CAF4396428A42830AD042
+:203DF200E4060219958A435D4076BBAF4396449243540BED428A339A40762F9C428A008D1C
+:203E12003C03BF569401116F428A008D3C03942B428AD492025205ED1F76BF01081A0400DD
+:203E3200428A099A40764C9584FEBE8B0600BDB208FE42A8428A13D09492FF90A90E441EBD
+:203E5200428A12D09492FF90A988440637FFA6AF441E428A11D09492FF90A988440637FF72
+:203E7200A6AF441E428A10D09492FF90A988440637FFA6AF441E2FFF0040440F1566431819
+:203E9200FF0F4492407606AF469620FFF4014076FDB34492019C407606AF459620FFF4019E
+:203EB2004076FDB3196F2FFF0020440F0A664318FF0FAD5C4492049B86DC4076D09F0C6F08
+:203ED2004318FF0F44064076A49B4696010244074076A49B4596428A4283008D3203408D0E
+:203EF200A10194929D96428A008DA201BF569438428A4692008DA301FF9094964692428AA6
+:203F1200A7FF008DA401FF909496428A008DA501942B428A008DA601942B4728FFFF008F85
+:203F3200A1014206475D0156A400060240769CAF4796428A4792008DA701FF909496008DE0
+:203F5200A801428A4792A7FFFF909496428A008DA901942B428A008DAA01942B408FA101AC
+:203F7200428A42060156A5000A0240766C9588FEBE8B060006FE42A8428A13D09492FF9035
+:203F9200A90E441E428A12D09492FF90A988440637FFA6AF441E428A11D09492FF90A98898
+:203FB200440637FFA6AF441E428A10D09492FF90A988440637FFA6AF441E452B428A15D0CE
+:203FD20045939492A8384596428A14D045939492A83845962FFF0004440F08664318FF0060
+:203FF200449245934076AAAE146F2FFF0002440F0A664318FF00AD5C4492029B85DC407690
+:20401200859F076F4318FF00455C44064076AA9B428A399A40762F9C86FE0600BDB208FE95
+:2040320042A81F767C03BF562001428A13D09492FF90A90E441E428A12D09492FF90A98829
+:20405200440637FFA6AF441E428A11D09492FF90A988440637FFA6AF441E428A10D094927B
+:20407200FF90A988440637FFA6AF441E428A17D09492FF90A90E461E428A16D09492FF904D
+:20409200A988460637FFA6AF461E428A15D09492FF90A988460637FFA6AF461E428A14D020
+:2040B2009492FF90A988460637FFA6AF461E428A4283008D3203408DA10194929D96428AE6
+:2040D200008DA201BF569434008FFFFF48A8008FA101485D42060156A400020240769CAF26
+:2040F200A90E481E485D448A46064076BBAFA90E481E408FA101428A42060156A500010211
+:2041120040766C95428A008DA101BF569434408FA101428A42060156A500010240766C95C3
+:20413200428AC48AE4CC4000C5FFFBEC428A460644834076D595428AC48AE4CC4000C5FFEB
+:20415200FBEC428A4892008DA101FF9094964892428AA7FF008DA201FF909496428A008D4A
+:20417200A301942B428A008DA401942B408FA1014206428A0156A500060240766C951F7638
+:204192007C03202B88FEBE8B06000AFE42A8428A13D09492FF90A90E441E428A12D094922B
+:2041B200FF90A988440637FFA6AF441E428A11D09492FF90A988440637FFA6AF441E428A60
+:2041D20010D09492FF90A988440637FFA6AF441E428A17D09492FF90A90E461E428A16D09B
+:2041F2009492FF90A988460637FFA6AF461E428A15D09492FF90A988460637FFA6AF461EBA
+:20421200428A14D09492FF90A988460637FFA6AF461E428A1BD09492FF90A90E481E428A66
+:204232001AD09492FF90A988480637FFA6AF481E428A19D09492FF90A988480637FFA6AFE9
+:20425200481E428A18D09492FF90A988480637FFA6AF481E428A1CD09492FF904996428AF5
+:204272001DD09492FF904A96186F4406468A48C4A6934076859F176F4A9208EC4406468A7A
+:2042920048C4A69340767FAF0E6F4406468A48C4A6934076D09F076F49920452E7EC055211
+:2042B200ECEC056F428A3C9A40762F9C8AFE060006FE459744A841961F7677030002301EED
+:2042D2001F76300014282040008FC2DD40769FA00052FBEC45934592D0FF0190A8944596E9
+:2042F2002DEC4192209B1F90A99F4697459246542A5646081F76770344060E1E1F7677035E
+:20431200460E101E1F76770303564101A90E121E008FC2DD408FCEDD4076AAA0008FC2DDA2
+:2043320040769FA00052FBEC460E0156440046924172469245744592D5ED1F763000142898
+:20435200104086FE060006FE459744A841961F7677030002301E1F76300014282040008F7F
+:20437200C2DD40769FA00052FBEC45934592D0FF0190A89445962DEC4192209B1F90A99F9A
+:204392004697459246542A5646081F7677034406141E1F767703460E161E1F767703035665
+:2043B2004101A90E181E008FC2DD408FD4DD4076B5A0008FC2DD40769FA00052FBEC460E53
+:2043D2000156440046924172469245744592D5ED1F7630001428104086FE060002FE1F760B
+:2043F200770306C5008FC2DD673E22761F763400008FC0A01CA81A7669FF407662B01F762A
+:204412005D030F8F404242A83806C000D1B2A9BD120F0077007702E84116008FEEDD89E620
+:2044320000004076B3B02376002082FE060002FE42A822761F76BE0108CCFCFF01501F7687
+:20445200BE0108961F76BE0108CCF3FF04501F76BE0108961F76BE0108CCCFFF10501F76A2
+:20447200BE0108961F76BE0108183FFF1F76BE010B1A08001F76BF010118F7FF1A761F7611
+:20449200C101BF5600071F76C101BF56011F1F76C101022B1F76C101BF56040C1F76C10149
+:2044B2000A2800801F76C1010B2B1F76C1010C2B1F76C101BF560F10428AD42B428A0002F9
+:2044D200C41E1F76C101001A800082FE69FF06001F76BF01011A080006001F76BF0101181D
+:2044F200F7FF060002FE42A8428AD492039003EC009A026F019A82FE060004FE44A042A814
+:20451200428A4406C41E428AD41A010084FE060004FE44A042A8428A4406C41E428AD41ACC
+:20453200020084FE06001B76F0FF0500BDA8BDA0BDC2BDC3BDAB00E2BD0003E2BD0003E20B
+:20455200BD0103E2BD0203E2BD0330E6000669FF42291656227601021F76770301563000B6
+:204572001F76770308C5008FC2DD69FF673E1A76AFE2BE03AFE2BE02AFE2BE01AFE2BE0040
+:2045920080E2BE00BE87BEC5BEC4BE83BE8A0300F1FF1776027602FE42A8EFFFBE01428ABB
+:2045B200D4400CEF1F767703BF561B01428AD41A0400428A0AD094C5673E428AD441CC5635
+:2045D200BE011F767703BF561B0D428AD41A0800428A0AD094C5673EEFFFB1011F76C10161
+:2045F200BF5600871F76C101082800061F76C101021A20001F767703BF561B02EFFF9F011E
+:204612001F76C10102CC4000C5FFC15698011F76C10107921F7677031D96428A08D094C500
+:20463200673E1F767703BF561B03EFFF8801428A0AD094C5673E1F76C101BF5600871F76DE
+:20465200C101082800021F76C101021A20001F767703BF561B04EFFF72011F76C10102CCF8
+:204672004000C5FFC1566B011F76C10107921F7677031D961F767703BF561B05EFFF5F015D
+:204692001F76C101BF56008F428AC48A1F76C101E49208961F76C101021A20001F767703E6
+:2046B200BF561B06EFFF4B011F76C10102CC4000C5FFC15644011F76C10107921F767703F4
+:2046D2001D961F767703BF561B07EFFF38011F76C101BF56008F428AC48A1F7677031C5810
+:2046F200C48A1F76C101949208961F7677031C0A1F76C101021A20001F767703BF561B0830
+:20471200EFFF1D011F76C10102CC4000C5FFC15616011F76C10107921F7677031D96428AA6
+:20473200C48A1F7677031C0ED40F0BED428A08D094C5673E1F767703BF561B09EFFFFF002E
+:204752001F767703BF561B07EFFFF900428A0AD094C5673E1F76C101BF5600871F76C1012C
+:20477200082800051F76C101021A20001F767703BF561B0AEFFFE3001F76C10102CC4000E0
+:20479200C5FFC156DC001F76C10107921F7677031D961F767703BF561B0BEFFFD0001F7601
+:2047B200C101082B1F76C101021A20001F767703BF561B0CEFFFC3001F76C10102CC4000FE
+:2047D200C5FFC156BC00428A08D094C5673E1F76C10107401F767703BD561B09CD56AF00D8
+:2047F200428AD418FBFF428AD418FEFF1F7677031B2B1F7677031C2BEFFFA1001F76C101AF
+:20481200BF5600871F76C101082800031F76C101021A20001F767703BF561B0EEFFF8F0003
+:204832001F76C10102CC4000C5FFC15688001F76C10107921F7677031D961F767703BF56C8
+:204852001B0F7C6F1F76C101BF56008F428AC48A1F76C101E49208961F76C101021A20001E
+:204872001F767703BF561B10696F1F76C10102CC4000C5FF63EC1F76C10107921F76770388
+:204892001D961F767703BF561B11586F1F76C101BF56008F1F76C101082B1F76C101021A44
+:2048B20020001F767703BF561B12486F1F76C10102CC4000C5FF42EC428AC48A1F7677033E
+:2048D2001C58C48A1F76C101079294961F7677031C0A1F767703BF561B13306F428AC48AAA
+:2048F2001F7677031C0ED40F12ED428A08D094C5673E1F7677031B2B1F7677031C2B428A72
+:20491200D418F7FF428AD418FDFF186F1F767703BF561B11136F1F7677031B9213520E6601
+:204932000356A901C0765AC1A988A706A60DA71EA92401DFA824A71E207682FE0600BDB2F2
+:20495200BDAAAD5A40FE86DA42974196AA281C80AB2800E07EA9A92800E0A8280C80F21E24
+:2049720042920263422B42920F52B256420F227641921DED008F006078A8008F00617AA85B
+:20499200008FC0607CA81F76BE0109CCFFCFA91A00101F76BE0109961F76BE0109CCFF3F0E
+:2049B2001F76BE01A91A004009961C6F008F006278A8008F00637AA8008FC0627CA81F76D5
+:2049D200BE0107CCFFFCA91A00021F76BE0107961F76BE0107CCFFF31F76BE01A91A00084A
+:2049F2000796788A08022AD0941E788A2CD0941E7A8AD41E7A8A0AD0941E7A8A12D0941E82
+:204A1200788A0002C41E7A8A013B42857E07C41E08D07A8A42857E072009941E10D1429278
+:204A320001907A8AA985F20730099C1E788AAA28FFFFAB28FEFFD4A9788A0702C41E788AA7
+:204A5200000208D00119941E788A00020CD00119941E788A00021ED00119941E788A000230
+:204A720022D00119941E788A000218D00119941E0002621E621A0080621A0040621A0020D8
+:204A9200621A0002621A8000621A0010788A14D06206941E18D0788A94CC1000C3FFFCECFA
+:204AB200788A16D09406601E60CCFFFCA91A000160965FCC00FF05505F96601A780060CC71
+:204AD200F8FF02506096788A6006941E6218FFEF788A14D06206941E18D0788A94CC1000A9
+:204AF200C3FFFCED7C83088F7064C5A87C83D5A8788A010230D0941E788A32D00002941E37
+:204B1200788A2ED0941E561E788A24D00602941E788A26D00002941E561A0100551A02001F
+:204B3200561A0200561A0400788A20D05606941E1F763700008FA0A408A81F763300321A1A
+:204B520010001F763700008F0BA50AA81F763300321A2000237600011A761F767C03000202
+:204B7200121E1F767C03101E1F767C031C2B1F767C03141EC0FEBE86BE8B69FF06000EFE4B
+:204B9200459744A84196005207ED008F00604CA8008F00614EA81F767C031D920FEC4C8AC1
+:204BB20008D094060190009B58FF08ED4C8A0AD094060190009B58FF49EC4C8A010208D046
+:204BD200941E4C8A0AD0941E448A013B45850156A400C4855AFFAA18000045853FFFABCAFF
+:204BF200AACBA81A00E0481E448A4592029CA9850156A400C4855AFF448A4592019CA985A8
+:204C12000156A400AA180000C4853FFFABCAAACB4A1E4E8A4806F41E4E8A4A06E41E2276F2
+:204C32004C8A2ED00002941E1A764C8A0102E41E1F767C03BF561D011F767C03019201522E
+:204C520005ED1F76BF010F1A10008EFE69FF06000EFE42A8428AF406481E428AE4064A1E88
+:204C72004806439743CC0080469643CC0040459643CC002044964318FF1F48924D964A06D6
+:204C92004C974A924B96469209EC43928052066743584D92008F80DC9496430A459209ECD9
+:204CB20043928052066743584C92008F80DC9496430A449209EC43928052066743584B929C
+:204CD200008F80DC94961F767C030192015206ED1F76BF010F1A0200056F1F76BF010F1A4E
+:204CF20001008EFE06001B76F0FF0500BDA8BDA0BDC2BDC3BDAB00E2BD0003E2BD0003E23B
+:204D1200BD0103E2BD0203E2BD0330E6000604FE69FF422916560102421E1F76330032922E
+:204D3200449623760001267600011F76330032921F763300322B1F7633002128FFFF102957
+:204D52001F7680011E921F904396432D42063B56421E1F76800142060C1E013B008F006196
+:204D720069FF035643030156A400407655A41F7633002192A9CDFFFE1F763300C7FF019063
+:204D92000150019087FFA8CA2196103B1F7633004492329684FEAFE2BE03AFE2BE02AFE209
+:204DB200BE01AFE2BE0080E2BE00BE87BEC5BEC4BE83BE8A0300F1FF177602761B76F0FF68
+:204DD20000E2BD0030E6000602FE422916561F7633003292419623760001267600011F7600
+:204DF200330032921F763300322B1F7633002128FFFF102901021F768001061E1F767C03EC
+:204E12001C0A1F7633002192A9CDFFFEC7FF1F76330001900150019087FFA8CA2196103B71
+:204E32001F7633004192329682FE80E2BE00F1FF1776027608FE2276008F5BA61F76350070
+:204E52000AA81A7669FF4076D4B31F763300221A2000237601001F767C0301920152C0568B
+:204E720086001F76C401021A0F001F76C40103CCF0FF0B501F76C40103961F76C40103CC86
+:204E92000FFFA0501F76C40103961F76C40103CCFFF0A91A00091F76C40103961F76C401DE
+:204EB20003CCFF0FA91A00801F76C40103961F76C4010418F0FF1F76C40104CC0FFF1050D0
+:204ED2001F76C40104961F76C40104CCFFF0A91A00041F76C40104961F76C40104CCFF0FC0
+:204EF200A91A00301F76C40104961F76C40105CCF0FF05501F76C40105961F76C40105CC2A
+:204F12000FFF20501F76C40105961F76C40105CCFFF0A91A00061F76C40105961F76C401DA
+:204F320005CCFF0FA91A00701F76C40105961F76C401061A0F001F76C40106CC0FFFD05075
+:204F52001F76C40106961F76C40106CCFFF0A91A000E1F76C40106961F76C40106CCFF0F2D
+:204F72001F76C401A91A00C006961F76C401011A00011F76C401011A00081F76C401191A26
+:204F920010001F76C401001A10001F76C401011A00401F763300BF5621011F76A001191A4E
+:204FB20000081F76A00119CCFFF8A91A00041F76A00119961F76A0011ACCFFFCA91A00013E
+:204FD2001F76A0011A961F76A001BF5609801F76A00100CC7FFCA91A00011F76A0010096F8
+:204FF2001F76A00100CCFFE3A91A00081F76A00100961F76A001013B019A00CD001CD9FF56
+:20501200A82D66FFA985441E1F76A00100CC8003C6FF0AEC1F76A00100CC8003C6FF80FFAB
+:20503200A985461E036F0102461E44871F765D0344564600421E3806C000D1B2008FB80B20
+:2050520042A8C000D1B2481E1F76A001489205961F76A0010018FCFF88FE06001B76F0FFAB
+:205072000500BDA8BDA0BDC2BDC3BDAB00E2BD0003E2BD0003E2BD0103E2BD0203E2BD03C3
+:2050920030E6000604FE69FF422916561F7633002292449623760100267601011F7633004B
+:2050B200221848001F7633002128FFFF10291F76BF010B1A00041F767C032092C056A10019
+:2050D2001F765D033792C1569C001F767C0301920152C05696001F767C0324061F767C0355
+:2050F2001019260F07671F767C0322061F767C03261E432B439210527A63013B008FC8D752
+:2051120043850156A400C49261EC4385008F08710156A400C492C3FFA90EA9BD120F00777F
+:205132000077007700778BE60000007703E242001F767C031E9216ED1F767403028A7FD03B
+:2051520094CC0001C7FF0EED1F767C03268A8CE600001F767C03A9A80109261EA9BF120FA9
+:20517200C4964385008FC8D70156A400C49202520EEC432D008F00D9AFE2420069FF1235D4
+:205192000156A400407640B203E24200AFE24200013B008F46D78CE6000043850156A40043
+:2051B200A9BF120FC4964385008FC8D70156A400C492025206ED439269FF4076E384136F90
+:2051D200439269FF4076F2870E6F1F7674030A8A43850156A400C42B4385008F80DC015678
+:2051F200A400C42B430A4392105288641F765E0314921F765E0315961F765E03142B1F7693
+:20521200BF010D1A00041F76C401011A00401F76C401191A10001F763300BF562101103BF5
+:205232001F7633004492229684FEAFE2BE03AFE2BE02AFE2BE01AFE2BE0080E2BE00BE87DD
+:20525200BEC5BEC4BE83BE8A0300F1FF17760276407678A7049A029B407680A7407618A853
+:2052720006001F76C00121920F90045213ED1F76C00111CC8001C6FF02520CED22761F7625
+:20529200C001BF5625551F76C001BF5625AA1A76016F69FF060022761F76C001BF56296870
+:2052B2001A7669FF060006FE449743961F76C00111CC0800C2FF02EC25761F76C00111CC6E
+:2052D2008001C6FF07EC22761F76C00111187FFE1A7622761F76C001111A400043921F769C
+:2052F200C0010F9021CDF0FF1F76C001A8CA21961A764392B156A901A90E461E69FFA92876
+:2053120080C3A828C901AC1E44564600461E407678A71F76C001119201900152FBED22765E
+:205332001F76C0011118BFFF1A764492015203EC02520DED22761F76C001039011CD7FFE4C
+:205352001F76C00186FFA8CA11961A7644920BED46C4013BAC281E00A60640FF2256A607A1
+:2053720041FF461E449201520BED46C4013BAC281E00A60640FF2256A60741FF461E449294
+:2053920002520AED46C4AC281F00013BA6062256A60740FF461E439218ED4492035215EDFC
+:2053B20022761F76C00111CC7FFE1F76C001A91A0001119669FF20FFDA054076FDB31F7671
+:2053D200C001111A80011A7646061F765D03381E86FE69FF060004FE22761F76C001BF5630
+:2053F2001A011F76C0011B2B1F76C0011A9206EC1F76C00103561A01026F019AA90E441E01
+:205412001F765D0369FF4406421E3806C000D1B2441E1F765D0344063C1E1F76C0011B92F4
+:2054320006EC1F76C00103561B01026F019AA90E441E1F765D034406421E3806C000D1B258
+:20545200441E1F765D0344063A1E1F762C0035CCF8FF1F762C00015035961F762C00341A9C
+:2054720004001F762C003418F7FF1F76C0011C1A0800787680001F76C0011C1A10001F76E0
+:20549200C0011C1A00041F76C0011C1A00081F76C0011C1A20001F76C0011C1A00011F769D
+:2054B200C0011C1A00101F76C0011C1A00201F76C0011C1A00401F76C0011C1A00801F76BA
+:2054D200C0011C18FBFF1F76C0011D1A01001F76C0011D1A02001F76C0011D1A04001F7688
+:2054F200C0011D1A08001F76C0011D1A10001F76C0011D1A20001F76C0011C1A04001F762B
+:20551200C0011D1A00041F76C0011D1A00081F76C0011D1A00101F76C0011D1A00201F7609
+:20553200C0011D1A00011F76C0011D1A00021F76C0011D1A00401F76C0011D1A00801F7662
+:20555200C001201A00011F76C001201A00021F76C001201A00041F76C001201A00081F76EA
+:20557200C001201A00101F76C001201A00201A7684FE69FF060002FE22761F762B0020283E
+:20559200FFFF1F762B002128FFFF1F762B002228FFFF1F762B002328FFFF1F762B002428D7
+:2055B200FFFF1F762B002528FFFF1F762B002628FFFF1F762B002728FFFF1A761F76FFCFC4
+:2055D200389241961F76FFCF399241961F76FFCF3A9241961F76FFCF3B9241961F76FFCFA3
+:2055F2003C9241961F76FFCF3D9241961F76FFCF3E9241961F76FFCF3F9241961F762B0016
+:205612002F4003EE019A026F009A82FE69FF060022761F762C0035CCF8FF01501F762C0021
+:2056320035961F762C003418FCFF1F762C003418F7FF1F762C00341A04001F762C00201A74
+:2056520060001F762C00201A1C001F762C00201A03001F762C00201A00301F762C00201A9D
+:20567200000E1F762C00201A80011F762C00211A40001F762C00201A00401F762C00201A1C
+:2056920000801F762C00211A03001F762C002C1A60001F762C002C1A1C001F762C002C1AE8
+:2056B20003001F762C002C1A00301F762C002C1A000E1F762C002C1A80011F762C002D1AF9
+:2056D20040001F762C002C1A00401F762C002C1A00801F762C002D1A03001F762C002E1A96
+:2056F20060001F762C002E1A1C001F762C002E1A03001F762C002E1A00301F762C002E1AC5
+:20571200000E1F762C002E1A80011F762C002F1A40001F762C002E1A00401F762C002E1A43
+:2057320000801F762C002F1A03001F762C00381A07001F762C00381A38001A7669FF4076B7
+:2057520057AA07F6007769FF060022761F76BE01181A03001F76BE01181A0C001F76BE014D
+:20577200181A30001F76BE01181AC0001F76BE01181A00031F76BE01181A000C1F76BE0100
+:20579200181A00301F76BE01181A00C01F76BE01191A03001F76BE01191A0C001F76BE01DE
+:2057B200191A30001F76BE01191AC0001F76BE01191A00031F76BE01191A000C1F76BE01BC
+:2057D200191A00301F76BE01191A00C01F76BE01141A03001F76BE01141A0C001F76BE01A6
+:2057F200141A30001F76BE01141AC0001F76BE01141A00031F76BE01141A000C1F76BE0190
+:20581200141A00301F76BE01141A00C01F76BE01151A03001F76BE01151A0C001F76BE016D
+:20583200151A30001F76BE01151AC0001F76BE01151A00031F76BE01151A000C1F76BE014B
+:20585200151A00301F76BE01151A00C069FF407657AA060022761F76BE01261A03001F76AB
+:20587200BE01261A0C001F76BE01261A30001F76BE01261AC0001F76BE01261A00031F76C7
+:20589200BE01261A000C1F76BE01261A00301F76BE01261A00C01F76BE01271A03001F76A6
+:2058B200BE01271A0C001F76BE01271A30001F76BE01271AC0001F76BE01271A00031F7683
+:2058D200BE01271A000C1F76BE01271A00301F76BE01271A00C01F76BE01171A03001F7673
+:2058F200BE01171A0C001F76BE01171A30001F76BE01171AC0001F76BE01171A00031F7683
+:20591200BE01171A000C1F76BE01171A00301F76BE01171A00C01F76BE01281A03001F7651
+:20593200BE01281A0C001F76BE01281A30001F76BE01281AC0001F76BE01281A00031F76FE
+:20595200BE01281A000C1F76BE01281A00301F76BE01281A00C01F76BE01161A00C01F7633
+:20597200BE01091A00C01F76BE01091A00301F76BE01091A000C1F76BE01161A30001F7600
+:20599200BE01161AC0001F76BE01161A00301F76BE01161A00031F76BE01161A000C1F76E6
+:2059B200BE01091A00031A7669FF060002FE2276008F3F801F7634001AA81A7669FF1F76F4
+:2059D2005D030F8F4042380642A8C000D1B2A9BD120F0077007702E8D11F008FE6DD89E6BA
+:2059F20000004076B3B01F7630000C2820402376001082FE060006FE407655A7103B69FF8B
+:205A12004076E6B1267600002F760000407684B3407676B14076C6AC1F76BF010C1A010078
+:205A32001F76BF010B1A0100412B41920A521263012920FF50C34076D0B11F76BF010F1AB8
+:205A520001001F76BF010E1A0100410A41920A52F0641F76BF010A1A01001F76BF010B1AF3
+:205A720001004076DAAC1F767C030092109B4076E8B30D9A40762C9601D4418F00C2A9A066
+:205A920040763B9602D4418F00C2A9A040763B961F767C03009A02934076CCA240761BA05D
+:205AB200407603AB4076FBB2407635B2407647A54076A081407688AE078F20A1A9A84076AD
+:205AD200D0B1407657994076AD984076D2821F767C0302921F7673033E9622761F76C00113
+:205AF200BF56292F1A761F765D03BF5637011F765E030192C15689001F765E03012B412B9E
+:205B120041920252E3FF8100013B008FE5DC41850156A400C49274EC4185008FFADD015663
+:205B3200A400408FE5DCC492019CA988C49641850156A500A692C55463684185008FFADD97
+:205B52000156A400013BC42B4185008FFCDD0156A400C492805207684185008FFCDD0156C8
+:205B7200A400C42B4185008FFCDD0156A400408F82D7C492C3FFA95803564103008FFCDD11
+:205B92000156A50041850156A400C4930F91A82D959262FF43961CED4185008FFCDD01567B
+:205BB200A400C492109CA988A618F0FF4185008FFCDD0156A400C47EC86F013B008FFCDD09
+:205BD20041850156A400C40A4392A0FF43964340F5EF016F013B008FFCDD41850156A4009B
+:205BF20069FFC493009A008F80DC4076ECA3013B008FFCDD41850156A400C4080300410A8B
+:205C120041920252826469FF4076BAAD1F767403028A7FD094CC0400C1FF09EC1F767403D4
+:205C3200028A7FDCC418FBFF407629991F767403028A7FD094CC0800C2FF09EC1F7674030C
+:205C5200028A7FDCC418F7FF4076AD981F767403028A7FD094CC2000C4FF09EC1F76740353
+:205C7200028A7FDCC418DFFF407657991F767403028A7FD094CC0200C0FF09EC1F767403C2
+:205C9200028A7FDCC418FDFF40765597412B41920252E3FF2EFF005205EC008F00D046A85F
+:205CB200046F008F80D346A8468A4076B29B4296A91BFFFF39EC1F76BF010F1A0100216FEE
+:205CD200468A40768F9C306F468A4076EF9C2C6F468A4076449D286F468A4076E79D246F1B
+:205CF200468A40763B9E206F468A4076F29E1C6F468A4076C09A186F468A40766A9B146F8E
+:205D120038520C623852E5EC0352F3EC0652F5EC3352DBEC3452E5EC076F3952DEEC3A52B7
+:205D3200D0EC3C52E2EC410A41920252B564EFFFE0FE22761F76BE011618FCFF1F76BE0179
+:205D52001818FCFF1F76BE011A1A01001F76BE011B1A01001A7669FF060002FE22761F76C8
+:205D7200BE01061800001F76BE01071800FF1F76BE0108183F001F76BE01091800FF1F7606
+:205D9200BE011618C0FF0F8F00F0ABA81F76BE01AB93AA9218C11F76BE0119C01F76BE013C
+:205DB2000B18EFFF1F76BE010B18DFFF1F76BE010B18BFFF1F76BE011B18F7FF1A761F7694
+:205DD2007C03002B422B412B4192645212631F76BF01009B019200BEC5FF0190B056A601ED
+:205DF200A692B156A8014273410A41926452F0644292325204651F767C03000A422B412B14
+:205E12004192645212631F76BF01009B019200BEC3FF0190B056A601A692B156A801427394
+:205E3200410A41926452F0644292325205651F767C0300080200422B412B41926452126371
+:205E52001F76BF01009B019200BEC4FF0190B056A601A692B156A8014273410A419264527D
+:205E7200F0644292325205651F767C03000804001F767C03035600011F767C0302961F762B
+:205E92007C03000A422B412B4192645212631F76BF01009B099200BEC2FF0190B056A60148
+:205EB200A692B156A8014273410A41926452F0644292325204651F767C03020A1F767C0316
+:205ED2000092015203EC025205ED1F767C03BF560601015207EC025205EC035203EC045241
+:205EF20005ED1F767C03BF56010122760E6F088F00001F76BE010AA8AA2813DCAB28070026
+:205F12001F76BE011AA9066F1F767C0301920152EFEC1A7682FE69FF060002FE0002421E2E
+:205F32001F76BF0100CC8000C6FF06ED00021F767C030C1E0D6F038F90D01F767C03A9A8E3
+:205F52000C0F066501021F767C0301560C00038F90D01F767C03A9A80C0F03650102421EF2
+:205F72001F76BF0100CC4000C5FF06ED00021F767C030E1E0B6FA9A81F767C030E0F06654E
+:205F920001021F767C0301560E00A9A81F767C030E0F046502024207421E1F767C03009235
+:205FB200035213631F76BF0101CC0004C9FF04ED04024207421E1F76BF0101CC8000C6FF0F
+:205FD20004ED08024207421E1F76BF01009B099200D4013BC2FF0190B056A8010053B15615
+:205FF200A4010356A404A9854207421E1F76BF01009B00D401CC4000C5FFB056A80100537B
+:20601200B156A4010356A405A9854207421E1F76BF01009B00D401CC1000C3FFB056A801D7
+:206032000053B156A4010356A406A9854207421E1F76BF01009B00D401CC2000C4FFB056FB
+:20605200A8010053B156A4010356A407A9854207421E1F767C03429207961F767403028A8E
+:2060720017D01F767C030792949682FE060022761F76BE011C18FEFF1F76BE011C18FDFF29
+:206092001F76BE01121A03001F76BE01121A0C001F76BE0116CCFCFF01501F76BE0116965D
+:2060B2001F76BE0116CCF3FF1F76BE01045016961A7669FF0600407664AE1F76E401BF56FD
+:2060D20007501F76E4010918DFFF1F76E401BF560C0E1F76E401BF56030A1F76E401BF560A
+:2060F20004051F76E401092B1F76E401091A00041F76E401091A2000060002FE42974196C3
+:206112001F76E40109CC0008CAFF015204EDA92855554E6F1F76E40102CC0010CBFF01525C
+:2061320004EDA9280010446F1F76E401BF5605041F76E4010928206E035641011F76E401E2
+:20615200C7FF08961F76E40102CC1000C3FFFBEC035641011F76E40108961F76E40102CCCD
+:206172001000C3FFFBEC42921F76E401A7FF08961F76E40102CC1000C3FFFBEC42921F7658
+:20619200E40108961F76E40102CC1000C3FFFBEC1F76E40109CC0008CAFF0152FAEC1F767B
+:2061B200E40102CC0010CBFF0152FAEC009A82FE060004FE41961F76E40109CC0008CAFFEE
+:2061D200015204EDA92855556C6F1F76E40102CC0010CBFF015204EDA9280010626F1F7666
+:2061F200E401BF5605021F76E4010928206E035641011F76E401C7FF0896008FFFFF44A861
+:206212001F76E40102CC1000C3FF06ED4406A98A81DC44A8F6ED035641011F76E401089603
+:20623200008FFFFF44A81F76E40109CC0008CAFF015206ED4406A98A81DC44A8F5ED1F7630
+:20625200E401BF5605021F76E4010928206C008FFFFF44A81F76E40102CC0800C2FF06ED77
+:206272004406A98A81DC44A8F6ED1F76E40106934292A8384296008FFFFF44A81F76E401D1
+:2062920002CC0800C2FF06ED4406A98A81DC44A8F6ED1F76E40142930692A83C4297429241
+:2062B20084FE060006FE459744A84196462B4592465414654192410A407606AF448A013BB3
+:2062D200A98846850156A400C47E20FFF4014076FDB3460A45924654EE6286FE060006FE5A
+:2062F200461E44A8417D4606A98A81DC46A814EC4483859244A04158A0F2008F00DEA09228
+:20631200FF90A9584192C7FF947041964606A98A81DC46A8EEED419286FE06000CFE461EF7
+:2063320044A8417D00024C1E46064C0F28694CCC01004796448A01294C0640FF0156A40083
+:20635200C4924896479205ED48CC00FFC7FF49964792015204ED4892FF9049964992417083
+:20637200008F00DEFF90A9584192C7FF9470419601024C074C1E46064C0FDA6641928CFE96
+:20639200060006FE439642A84428FFFF452B4392455436694558428A9492FF9044F2462B72
+:2063B200469208521067444007EF4492C0FFA91C01A04496046F4492C0FF4496460A4692C9
+:2063D2000852F2684558428A94CC00FFC7FF44F2462B469208521067444007EF4492C0FF0A
+:2063F200A91C01A04496046F4492C0FF4496460A46920852F268450A43924554CC664492C8
+:2064120086FE060008FE421E0129420647FFA81A00FF441E472B47922052146344060856C3
+:206432000080461E460605ECAA280031AB2B46A9440630FF46704571441E470A479220527E
+:20645200EE6442A34406AC281800AB1800FF2256FF90009BABCAAACB441E4206440F03ED82
+:20647200019A026F009A88FE0600008F000C1F7677031EA8AA28FFFFAB28FFFF1F76300002
+:2064920002A91F763000062B1F763000072B1F763000041A10001F763000041A200000025A
+:2064B2001F767703201E1F767703008F080C26A81F767703008F100C2EA81F7630000AA9F5
+:2064D2001F76300012A91F7630000E2B1F7630000F2B1F763000162B1F763000172B1F768B
+:2064F20030000C1A10001F763000141A10001F7630000C1A20001F763000141A20001F766E
+:206512007703281E1F767703301E060008FE03E2460103E2440042A8428A4406E41E428A1D
+:206532004606F41EAFE24400AFE2460100E70800007788E60000007703E24800428AC48AAC
+:206552004806D41E428AC48AF42B428AC48AFC2B428AC48AE41A1000428AC48AE41A20000F
+:20657200428AC48AE418FFFB428AC48AE418FFF7428AC48AE41A0040428A0002D41E88FE4F
+:206592000600BD3ABDB2BDAABDA202FE0129A9BF120F58FF5B61A85C7F91A8088000421E4D
+:2065B200A493D6FFA85CA9BF160F6761A85D7F91A8088000A859A958A593D6FFA85DA493D4
+:2065D200A571A8180001A697A418FF00A518FF007FDCA492A59EA7964D64A90801FF3E620B
+:2065F200A193A09236FFA859A958420635FF0EF6A11FA95BA3010AF6A11F2D56A204A32D4B
+:20661200A03640FF0BF6A11F33FF009B30FF54FFA20CA39540FFA70801001FF677FF2009BA
+:2066320040FFA70801001FF677FF5AFFA7922265A90801FF1363A9A946FF7F91A85BA95AE1
+:20665200A625A79596FFA20CA395A9BD120F82FEBE82BE86BE8BBE8E0600009B57FFA808DF
+:206672007FFF5AFFA693F260A8280080AA71AB92ED6F20FF0000EA6F5AFFA493A8180001D9
+:2066920096FFA85CA9A9A8087FFFA81C0080A4CBDD6F1F76C001201A0010407657AA2276E1
+:2066B2001F762C003518F8FF1F762C00341A03001F762C003418F7FF1F762C003418FBFFA7
+:2066D2001F762C002ECC9FFF1F762C0020502E961F762C002ECCE3FF1F762C0008502E96E0
+:2066F2001F762C002ECCFCFF1F762C0001502E961F762C002ECCFFCF1F762C00A91A0010DF
+:206712002E961F762C002ECCFFF11F762C00A91A00062E961F762C002E187FFE1F762C0065
+:206732002F18BFFF1F762C002E18FFBF1F762C002E18FF7F1F762C002F1A03001A7607F65E
+:20675200007769FF060004FE421E0129420640FF421E0002441E4206440F0A691002407695
+:20677200FDB301024407441E4206440FF86684FE0600103B1F7633002018FEFF1F76330016
+:20679200222B1F763300242B1F763300262B1F763300282B1F7633002A2B1F7633002C2B13
+:2067B2001F7633002E2B1F763300302B1F763300322B1F763300342B1F763300362B1F7679
+:2067D2003300382B1F763300232B1F763300252B1F763300272B1F763300292B1F763300E5
+:2067F2002B2B1F7633002D2B1F7633002F2B1F763300312B1F763300332B1F763300352B7D
+:206812001F763300372B1F763300392B69FF06001F763300201A01001F7633002128FFFF90
+:20683200102969FF0600BDB2BDAABDA203E2BD0403E2BD0506FE03E2440042A808D00CD151
+:2068520042C54283AFE2440142C4428A4286AFE2F70050E80200428212E3958B42C50ED06A
+:2068720012E3D6CCAFE2C40000E39F4208E3E295AFE2930140E74921007710E70800007751
+:2068920003E24600428A42830CD00ED194069D1E428A4606941E428A428308D0F406951E3A
+:2068B200428A4406F41EAFE2460086FEAFE2BE05AFE2BE04BE82BE86BE8B0600AD280004F0
+:2068D20069FF1F5616561A5610E6000240291F76000002291B762276A92801B4A82800004D
+:2068F20001091B61C07601B404290F6F009BA92401DF046C0429A82401DFA61EA1F78624D3
+:20691200A706A1810109A71EA92403635CFF043BA95901DF0900ECFF1A76A928FFFFA828F5
+:20693200FFFF01090E61FF76FFFF066F01DFBDC3A71E673EBEC5A92401DFA82458FFF76072
+:206952004076A0B34076BDB3022904295F565AFF42065F56421E00021FF617564200AB06BC
+:20697200325602292076022904295F565AFF420656FF421E00021FF61756420032560229E0
+:2069920020765AFF00021FF617564200A9A920765AFF00021FF617564200207602FE208FE4
+:2069B20000001F767C0322A81F767C03208F00FA24A81F767C0322061F767C03261E1F7635
+:2069D2007C03282B1F767C032206421E066F428AC42B01024207421E1F767C032406420FCC
+:2069F200F76682FE0600A85CA971A697013BA98556FFA95DA48556FFA95CA5920FF6A41F00
+:206A1200A64F026C5CFF2076A696A85C013BA98556FFA95DA48556FFA95CA5920FF6A41F89
+:206A3200A64F026C5DFFA89220765AFFAB92A4C5A48E07ECFF9CA988859287960E00FEFF86
+:206A5200AB92A988A9A9A60F10ECAA930EECA9A9FF9DA85CBF76FEFF859287960E00FEFF19
+:206A7200859287960C00F8FFA08A06000000A0E514AD0962A0E51F765D0314AD90E5B45632
+:206A92003E01156F4FE803C092E601008CB5050000E7CA00007700E78A000077CFE812F09F
+:206AB200007700E75100007700E74000060006FE008F00C044A8008F000D46A82276412BA4
+:206AD200419280520D63448A84C444A8468AA9A80209461EC4C2410A41928052F5641A769E
+:206AF20086FE69FF0600A928FFFFAA28FFFFAB28FFFFA828FFFFAB0F04ED00D400BE0B6F9D
+:206B1200A927A928FFFFA92FA4A9C488A928FFFF0209A98AA692407628AB06000077006F99
+:206B32001F767C03BDB22EC5A959673E1F767C0332C5A70603ECA192673E1F767C0330065D
+:206B520003ECA71E673E4076BBB3BE8B060022761F76C0011C1A080069FF787680001A76C5
+:206B72001F76C401BF5618E0028FE64969FFA9A84076FDB3060002FE429741961F767703F8
+:206B920037961F7677034292369682FE06001F767C032CA806001F767C032EA806000600FD
+:086BB2000119C356FFFF0600A4
+:206BBA002B0000002EC122761F762A00001A01001F762A0006CCFFF0A91A00051F762A0028
+:206BDA0006961F762A0006CCF0FF05501F762A0006961F762A0007CCE0FF08501F762A0047
+:1C6BFA0007961F762A00041AFF011F762A00051AFF011A7607F6007769FF0600B5
+:206C16000301000000C06F9100006F9100006F9100006F9100006F9100006F9100006F919A
+:206C360000006F9100006F9100006F9100006F9100006F9100006F910000F8880000058930
+:206C56000000128900001F8900008391000037890000428900004D89000058890000638999
+:206C760000006E89000079890000848900008F8900009A890000A5890000B0890000BB8912
+:206C96000000C6890000D1890000F289000083910000138A0000348A0000538A0000748A70
+:206CB6000000978A0000B88A0000D98A0000FA8A00001B8B00003E8B00005F8B0000839107
+:206CD600000083910000808B0000A18B0000C48B0000E78B0000088C0000298C0000839135
+:206CF6000000839100004C8C00006D8C0000908C0000B18C0000D28C0000F38C000083914F
+:206D1600000083910000148D0000358D000083910000839100008391000083910000839182
+:206D3600000083910000588D0000798D00009C8D0000BD8D0000DE8D0000FF8D00008391C0
+:206D5600000083910000228E0000438E0000648E0000858E0000A68E0000C78E00008391E6
+:206D7600000083910000EA8E00000D8F000083910000839100002E8F00004F8F00008391FE
+:206D9600000083910000708F0000938F0000B68F0000D98F0000FC8F00001F9000004290EF
+:206DB60000006390000083910000839100008391000083910000839100008391000083913E
+:206DD6000000839100008391000083910000839100008391000083910000839100008391FD
+:206DF60000008391000084900000A5900000C6900000E790000008910000839100002B91EA
+:0C6E160000004C91000033000B000A004B
+:206E2200280000005AC1FCA000001BA100002DA1000044A100005AA100006DA1000081A1D7
+:206E4200000094A10000AFA10000D3A10000E9A10000FCA1000009A200002BA200003DA2B9
+:186E620000004FA2000062A2000073A2000083A200009BA200000000AC
+:00000001FF

Bin/UKSSTMS320F28335.map

@@ -0,0 +1,34 @@
+********************************************************************************
+TMS320C2000 Hex Converter                                                 v5.2.7
+********************************************************************************
+
+INPUT FILE NAME: <D:\project2833\ICE_22220_4\bin\UKSSTMS320F28335.out>
+OUTPUT FORMAT:   Binary
+
+PHYSICAL MEMORY PARAMETERS
+   Default data width   :  16
+   Default memory width :   8 (LS-->MS)
+   Default output width :   8
+
+BOOT LOADER PARAMETERS
+   Table Type:		  SERIAL PORT (SCI 8 bit Mode)
+   Entry Point:		  0x0000b28b
+
+
+OUTPUT TRANSLATION MAP
+--------------------------------------------------------------------------------
+00000000..003fffff  Page=0  Memory Width=8  ROM Width=8
+--------------------------------------------------------------------------------
+   OUTPUT FILES: D:\project2833\ICE_22220_4\bin\UKSSTMS320F28335.bin [b0..b7]
+
+   CONTENTS: 00000000..00006e79   BOOT TABLE
+                           .cinit : dest=0000b401  size=000001cb  width=00000002
+                            .text : dest=00008000  size=00003401  width=00000002
+                         ramfuncs : dest=0000c12e  size=0000002b  width=00000002
+                          .econst : dest=0000c000  size=00000103  width=00000002
+                          .switch : dest=0000c15a  size=00000028  width=00000002
+
+--------------------------------------------------------------------------------
+00000000..003fffff  Page=1  Memory Width=8  ROM Width=8  "*DEFAULT PAGE 1*"
+--------------------------------------------------------------------------------
+   NO CONTENTS

Debug.lkf

@@ -0,0 +1,29 @@
+-z -c -e_c_int00 -m"D:/project2833/ICE_22220_4/UKSSTMS320F28335.map" -o"D:/project2833/ICE_22220_4/bin/UKSSTMS320F28335.out" -stack0x3f0 -w -x -i"D:/CCStudio_v3.3PLA/C2000/xdais/lib" -i"D:/CCStudio_v3.3PLA/bios_5_33_05/packages/ti/bios/lib" -i"D:/CCStudio_v3.3PLA/bios_5_33_05/packages/ti/rtdx/lib/c2000" -i"D:/CCStudio_v3.3PLA/C2000/cgtools/lib" -l"rts2800_fpu32.lib"
+"D:\project2833\ICE_22220_4\F28335.cmd"
+"D:\project2833\ICE_22220_4\Source\External\v120\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
+"D:\project2833\ICE_22220_4\Debug\ADC.obj"
+"D:\project2833\ICE_22220_4\Debug\bios.obj"
+"D:\project2833\ICE_22220_4\Debug\cntrl_adr.obj"
+"D:\project2833\ICE_22220_4\Debug\crc16.obj"
+"D:\project2833\ICE_22220_4\Debug\DSP2833x_Adc.obj"
+"D:\project2833\ICE_22220_4\Debug\DSP2833x_ADC_cal.obj"
+"D:\project2833\ICE_22220_4\Debug\DSP2833x_CpuTimers.obj"
+"D:\project2833\ICE_22220_4\Debug\DSP2833x_GlobalVariableDefs.obj"
+"D:\project2833\ICE_22220_4\Debug\DSP2833x_PieCtrl.obj"
+"D:\project2833\ICE_22220_4\Debug\DSP2833x_SWPrioritizedDefaultIsr.obj"
+"D:\project2833\ICE_22220_4\Debug\DSP2833x_SWPrioritizedPieVect.obj"
+"D:\project2833\ICE_22220_4\Debug\DSP2833x_SysCtrl.obj"
+"D:\project2833\ICE_22220_4\Debug\DSP2833x_usDelay.obj"
+"D:\project2833\ICE_22220_4\Debug\DSP2833x_Xintf.obj"
+"D:\project2833\ICE_22220_4\Debug\ecan.obj"
+"D:\project2833\ICE_22220_4\Debug\filter_bat2.obj"
+"D:\project2833\ICE_22220_4\Debug\i2c.obj"
+"D:\project2833\ICE_22220_4\Debug\log_to_mem.obj"
+"D:\project2833\ICE_22220_4\Debug\main.obj"
+"D:\project2833\ICE_22220_4\Debug\measure.obj"
+"D:\project2833\ICE_22220_4\Debug\message.obj"
+"D:\project2833\ICE_22220_4\Debug\peripher.obj"
+"D:\project2833\ICE_22220_4\Debug\RS485.obj"
+"D:\project2833\ICE_22220_4\Debug\spise2p.obj"
+"D:\project2833\ICE_22220_4\Debug\tools.obj"
+"D:\project2833\ICE_22220_4\Libraries\rts2800_fpu32.lib"

F28335.cmd

@@ -0,0 +1,206 @@
+/*
+// TI File $Revision: /main/10 $
+// Checkin $Date: July 9, 2008   13:43:56 $
+//###########################################################################
+//
+// FILE:	F28335.cmd
+//
+// TITLE:	Linker Command File For F28335 Device
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+/* ======================================================
+// For Code Composer Studio V2.2 and later
+// ---------------------------------------
+// In addition to this memory linker command file, 
+// add the header linker command file directly to the project. 
+// The header linker command file is required to link the
+// peripheral structures to the proper locations within 
+// the memory map.
+//
+// The header linker files are found in <base>\DSP2833x_Headers\cmd
+//   
+// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
+// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
+========================================================= */
+
+/* ======================================================
+// For Code Composer Studio prior to V2.2
+// --------------------------------------
+// 1) Use one of the following -l statements to include the 
+// header linker command file in the project. The header linker
+// file is required to link the peripheral structures to the proper 
+// locations within the memory map                                    */
+
+/* Uncomment this line to include file only for non-BIOS applications */
+/* -l DSP2833x_Headers_nonBIOS.cmd */
+
+/* Uncomment this line to include file only for BIOS applications */
+/* -l DSP2833x_Headers_BIOS.cmd */
+
+/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
+   library search path under project->build options, linker tab, 
+   library search path (-i).
+/*========================================================= */
+
+/* Define the memory block start/length for the F28335  
+   PAGE 0 will be used to organize program sections
+   PAGE 1 will be used to organize data sections
+
+    Notes: 
+          Memory blocks on F28335 are uniform (ie same
+          physical memory) in both PAGE 0 and PAGE 1.  
+          That is the same memory region should not be
+          defined for both PAGE 0 and PAGE 1.
+          Doing so will result in corruption of program 
+          and/or data. 
+          
+          L0/L1/L2 and L3 memory blocks are mirrored - that is
+          they can be accessed in high memory or low memory.
+          For simplicity only one instance is used in this
+          linker file. 
+          
+          Contiguous SARAM memory blocks can be combined 
+          if required to create a larger memory block. 
+ */
+
+
+MEMORY
+{
+PAGE 0:    /* Program Memory */
+           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
+
+   ZONE0       : origin = 0x004000, length = 0x001000     /* XINTF zone 0 */
+   RAML0       : origin = 0x008000, length = 0x004000     /* on-chip RAM block L0 */
+/*   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
+/*   RAML2       : origin = 0x00A000, length = 0x001000     /* on-chip RAM block L2 */
+//   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
+   RAML4       : origin = 0x00C000, length = 0x001000     /* on-chip RAM block L1 */
+
+   ZONE6       : origin = 0x0100000, length = 0x100000    /* XINTF zone 6 */ 
+   FLASHH      : origin = 0x300000, length = 0x008000     /* on-chip FLASH */
+   FLASHG      : origin = 0x308000, length = 0x008000     /* on-chip FLASH */
+   FLASHF      : origin = 0x310000, length = 0x008000     /* on-chip FLASH */
+   FLASHE      : origin = 0x318000, length = 0x008000     /* on-chip FLASH */
+   FLASHD      : origin = 0x320000, length = 0x008000     /* on-chip FLASH */
+   FLASHC      : origin = 0x328000, length = 0x008000     /* on-chip FLASH */
+   FLASHA      : origin = 0x338000, length = 0x007F80     /* on-chip FLASH */
+   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
+   BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
+   CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
+   OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
+   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */
+   
+   IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
+   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
+   FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
+   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */        
+   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
+   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
+
+PAGE 1 :   /* Data Memory */
+           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
+           /* Registers remain on PAGE1                                                  */
+   
+   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
+   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
+   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAML5       : origin = 0x00D000, length = 0x003000     /* on-chip RAM block L1 */
+/*   RAML6       : origin = 0x00E000, length = 0x001000     /* on-chip RAM block L1 */
+/*   RAML7       : origin = 0x00F000, length = 0x001000     /* on-chip RAM block L1 */
+   ZONE7A      : origin = 0x0200000, length = 0x00FC00    /* XINTF zone 7 - program space */ 
+   ZONE7B      : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
+   FLASHB      : origin = 0x330000, length = 0x008000     /* on-chip FLASH */
+}
+
+/* Allocate sections to memory blocks.
+   Note:
+         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
+                   execution when booting to flash
+         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
+*/ 
+ 
+SECTIONS
+{
+ 
+   /* Allocate program areas: */
+   .cinit              : > RAML0      PAGE = 0
+   .pinit              : > RAML0      PAGE = 0
+   .text               : > RAML0      PAGE = 0
+   codestart           : > BEGIN       PAGE = 0
+   ramfuncs            : LOAD = RAML4, 
+                         RUN = RAML4, 
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         PAGE = 0
+
+   csmpasswds          : > CSM_PWL     PAGE = 0
+   csm_rsvd            : > CSM_RSVD    PAGE = 0
+   
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMM1       PAGE = 1
+   .ebss               : > RAML5       PAGE = 1
+   .esysmem            : > RAML0      PAGE = 0
+
+   .logg               : > ZONE7A      PAGE = 1
+
+   /* Initalized sections go in Flash */
+   /* For SDFlash to program these, they must be allocated to page 0 */
+   .econst             : > RAML4      PAGE = 0
+   .switch             : > RAML4      PAGE = 0      
+
+   /* Allocate IQ math areas: */
+   IQmath              : > FLASHC      PAGE = 0                  /* Math Code */
+   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD 
+   
+   /* Uncomment the section below if calling the IQNexp() or IQexp()
+      functions from the IQMath.lib library in order to utilize the 
+      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
+      is 1 wait-state). If this section is not uncommented, IQmathTables2
+      will be loaded into other memory (SARAM, Flash, etc.) and will take
+      up space, but 0 wait-state is possible.
+   */
+   /*
+   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
+   {
+   
+              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
+   
+   }
+   */
+   
+   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
+         
+   /* Allocate DMA-accessible RAM sections: * /
+   DMARAML4         : > RAML4,     PAGE = 1
+   DMARAML5         : > RAML5,     PAGE = 1
+/*   DMARAML6         : > RAML6,     PAGE = 1
+   DMARAML7         : > RAML7,     PAGE = 1
+*/   
+   /* Allocate 0x400 of XINTF Zone 7 to storing data */
+   ZONE7DATA        : > ZONE7B,    PAGE = 1
+
+   /* .reset is a standard section used by the compiler.  It contains the */ 
+   /* the address of the start of _c_int00 for C Code.   /*
+   /* When using the boot ROM this section and the CPU vector */
+   /* table is not needed.  Thus the default type is set here to  */
+   /* DSECT  */ 
+   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
+   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
+   
+   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
+   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
+

Source/External/v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd

@@ -0,0 +1,176 @@
+/*
+// TI File $Revision: /main/9 $
+// Checkin $Date: July 9, 2008   13:43:25 $
+//###########################################################################
+//
+// FILE:    28332_RAM_lnk.cmd
+//
+// TITLE:   Linker Command File For 28332 examples that run out of RAM
+//
+//          This ONLY includes all SARAM blocks on the 28332 device.
+//          This does not include flash or OTP. 
+//
+//          Keep in mind that L0 and L1 are protected by the code
+//          security module.
+//
+//          What this means is in most cases you will want to move to 
+//          another memory map file which has more memory defined.  
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+/* ======================================================
+// For Code Composer Studio V2.2 and later
+// ---------------------------------------
+// In addition to this memory linker command file, 
+// add the header linker command file directly to the project. 
+// The header linker command file is required to link the
+// peripheral structures to the proper locations within 
+// the memory map.
+//
+// The header linker files are found in <base>\DSP2833x_Headers\cmd
+//   
+// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
+// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
+========================================================= */
+
+/* ======================================================
+// For Code Composer Studio prior to V2.2
+// --------------------------------------
+// 1) Use one of the following -l statements to include the 
+// header linker command file in the project. The header linker
+// file is required to link the peripheral structures to the proper 
+// locations within the memory map                                    */
+
+/* Uncomment this line to include file only for non-BIOS applications */
+/* -l DSP2833x_Headers_nonBIOS.cmd */
+
+/* Uncomment this line to include file only for BIOS applications */
+/* -l DSP2833x_Headers_BIOS.cmd */
+
+/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
+   library search path under project->build options, linker tab, 
+   library search path (-i).
+/*========================================================= */
+
+/* Define the memory block start/length for the F28332  
+   PAGE 0 will be used to organize program sections
+   PAGE 1 will be used to organize data sections
+
+   Notes: 
+         Memory blocks on F28332 are uniform (ie same
+         physical memory) in both PAGE 0 and PAGE 1.  
+         That is the same memory region should not be
+         defined for both PAGE 0 and PAGE 1.
+         Doing so will result in corruption of program 
+         and/or data. 
+         
+         L0/L1/L2 and L3 memory blocks are mirrored - that is
+         they can be accessed in high memory or low memory.
+         For simplicity only one instance is used in this
+         linker file. 
+         
+         Contiguous SARAM memory blocks can be combined 
+         if required to create a larger memory block. 
+*/
+
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode      */
+   /* BOOT_RSVD is used by the boot ROM for stack.               */
+   /* This section is only reserved to keep the BOOT ROM from    */
+   /* corrupting this area during the debug process              */
+   
+   BEGIN      : origin = 0x000000, length = 0x000002     /* Boot to M0 will go here                      */
+   BOOT_RSVD  : origin = 0x000002, length = 0x00004E     /* Part of M0, BOOT rom will use this for stack */               
+   RAMM0      : origin = 0x000050, length = 0x0003B0
+
+   RAML0      : origin = 0x008000, length = 0x001000    
+   RAML1      : origin = 0x009000, length = 0x001000    
+   RAML2      : origin = 0x00A000, length = 0x001000    
+   RAML3      : origin = 0x00B000, length = 0x001000   
+   ZONE7A     : origin = 0x200000, length = 0x00FC00     /* XINTF zone 7 - program space */ 
+   CSM_RSVD   : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
+   CSM_PWL    : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA            */
+   ADC_CAL    : origin = 0x380080, length = 0x000009
+   RESET      : origin = 0x3FFFC0, length = 0x000002   
+   IQTABLES   : origin = 0x3FE000, length = 0x000b50
+   IQTABLES2  : origin = 0x3FEB50, length = 0x00008c
+   FPUTABLES  : origin = 0x3FEBDC, length = 0x0006A0
+   BOOTROM    : origin = 0x3FF27C, length = 0x000D44  
+
+   
+
+         
+PAGE 1 : 
+   RAMM1      : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAML4      : origin = 0x00C000, length = 0x001000    
+   RAML5      : origin = 0x00D000, length = 0x001000    
+   ZONE7B     : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
+}
+ 
+ 
+SECTIONS
+{
+   /* Setup for "boot to SARAM" mode: 
+      The codestart section (found in DSP28_CodeStartBranch.asm)
+      re-directs execution to the start of user code.  */
+   codestart        : > BEGIN,     PAGE = 0
+   ramfuncs         : > RAML0,     PAGE = 0  
+   .text            : > RAML1,     PAGE = 0
+   .cinit           : > RAML0,     PAGE = 0
+   .pinit           : > RAML0,     PAGE = 0
+   .switch          : > RAML0,     PAGE = 0
+   
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : > RAML4,     PAGE = 1
+   .econst          : > RAML5,     PAGE = 1      
+   .esysmem         : > RAMM1,     PAGE = 1
+
+   IQmath           : > RAML1,     PAGE = 0
+   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD 
+   
+   /* Uncomment the section below if calling the IQNexp() or IQexp()
+      functions from the IQMath.lib library in order to utilize the 
+      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
+      is 1 wait-state). If this section is not uncommented, IQmathTables2
+      will be loaded into other memory (SARAM, Flash, etc.) and will take
+      up space, but 0 wait-state is possible.
+   */
+   /*
+   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
+   {
+   
+              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
+   
+   }
+   */
+   
+   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
+   
+   DMARAML4         : > RAML4,     PAGE = 1
+   DMARAML5         : > RAML5,     PAGE = 1
+   
+   ZONE7DATA        : > ZONE7B,    PAGE = 1   
+
+
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used                    */
+   csm_rsvd         : > CSM_RSVD   PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
+   csmpasswds       : > CSM_PWL    PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
+   
+   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
+   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD
+
+     
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/

Source/External/v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd

@@ -0,0 +1,178 @@
+/*
+// TI File $Revision: /main/8 $
+// Checkin $Date: July 9, 2008   13:43:30 $
+//###########################################################################
+//
+// FILE:    28334_RAM_lnk.cmd
+//
+// TITLE:   Linker Command File For 28334 examples that run out of RAM
+//
+//          This ONLY includes all SARAM blocks on the 28334 device.
+//          This does not include flash or OTP. 
+//
+//          Keep in mind that L0 and L1 are protected by the code
+//          security module.
+//
+//          What this means is in most cases you will want to move to 
+//          another memory map file which has more memory defined.  
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+/* ======================================================
+// For Code Composer Studio V2.2 and later
+// ---------------------------------------
+// In addition to this memory linker command file, 
+// add the header linker command file directly to the project. 
+// The header linker command file is required to link the
+// peripheral structures to the proper locations within 
+// the memory map.
+//
+// The header linker files are found in <base>\DSP2833x_Headers\cmd
+//   
+// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
+// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
+========================================================= */
+
+/* ======================================================
+// For Code Composer Studio prior to V2.2
+// --------------------------------------
+// 1) Use one of the following -l statements to include the 
+// header linker command file in the project. The header linker
+// file is required to link the peripheral structures to the proper 
+// locations within the memory map                                    */
+
+/* Uncomment this line to include file only for non-BIOS applications */
+/* -l DSP2833x_Headers_nonBIOS.cmd */
+
+/* Uncomment this line to include file only for BIOS applications */
+/* -l DSP2833x_Headers_BIOS.cmd */
+
+/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
+   library search path under project->build options, linker tab, 
+   library search path (-i).
+/*========================================================= */
+
+/* Define the memory block start/length for the F28334  
+   PAGE 0 will be used to organize program sections
+   PAGE 1 will be used to organize data sections
+
+   Notes: 
+         Memory blocks on F28334 are uniform (ie same
+         physical memory) in both PAGE 0 and PAGE 1.  
+         That is the same memory region should not be
+         defined for both PAGE 0 and PAGE 1.
+         Doing so will result in corruption of program 
+         and/or data. 
+         
+         L0/L1/L2 and L3 memory blocks are mirrored - that is
+         they can be accessed in high memory or low memory.
+         For simplicity only one instance is used in this
+         linker file. 
+         
+         Contiguous SARAM memory blocks can be combined 
+         if required to create a larger memory block. 
+*/
+
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode      */
+   /* BOOT_RSVD is used by the boot ROM for stack.               */
+   /* This section is only reserved to keep the BOOT ROM from    */
+   /* corrupting this area during the debug process              */
+   
+   BEGIN      : origin = 0x000000, length = 0x000002     /* Boot to M0 will go here                      */
+   BOOT_RSVD  : origin = 0x000002, length = 0x00004E     /* Part of M0, BOOT rom will use this for stack */               
+   RAMM0      : origin = 0x000050, length = 0x0003B0
+
+   RAML0      : origin = 0x008000, length = 0x001000    
+   RAML1      : origin = 0x009000, length = 0x001000    
+   RAML2      : origin = 0x00A000, length = 0x001000    
+   RAML3      : origin = 0x00B000, length = 0x001000
+   ZONE7A     : origin = 0x200000, length = 0x00FC00     /* XINTF zone 7 - program space */ 
+   CSM_RSVD   : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
+   CSM_PWL    : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA            */
+   ADC_CAL    : origin = 0x380080, length = 0x000009
+   RESET      : origin = 0x3FFFC0, length = 0x000002
+   IQTABLES   : origin = 0x3FE000, length = 0x000b50
+   IQTABLES2  : origin = 0x3FEB50, length = 0x00008c
+   FPUTABLES  : origin = 0x3FEBDC, length = 0x0006A0
+   BOOTROM    : origin = 0x3FF27C, length = 0x000D44  
+         
+
+         
+PAGE 1 : 
+   RAMM1      : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAML4      : origin = 0x00C000, length = 0x001000    
+   RAML5      : origin = 0x00D000, length = 0x001000    
+   RAML6      : origin = 0x00E000, length = 0x001000    
+   RAML7      : origin = 0x00F000, length = 0x001000   
+   ZONE7B     : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
+}
+ 
+ 
+SECTIONS
+{
+   /* Setup for "boot to SARAM" mode: 
+      The codestart section (found in DSP28_CodeStartBranch.asm)
+      re-directs execution to the start of user code.  */
+   codestart        : > BEGIN,     PAGE = 0
+   ramfuncs         : > RAML0,     PAGE = 0  
+   .text            : > RAML1,     PAGE = 0
+   .cinit           : > RAML0,     PAGE = 0
+   .pinit           : > RAML0,     PAGE = 0
+   .switch          : > RAML0,     PAGE = 0
+   
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : > RAML4,     PAGE = 1
+   .econst          : > RAML5,     PAGE = 1      
+   .esysmem         : > RAMM1,     PAGE = 1
+
+   IQmath           : > RAML1,     PAGE = 0
+   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD 
+   
+   /* Uncomment the section below if calling the IQNexp() or IQexp()
+      functions from the IQMath.lib library in order to utilize the 
+      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
+      is 1 wait-state). If this section is not uncommented, IQmathTables2
+      will be loaded into other memory (SARAM, Flash, etc.) and will take
+      up space, but 0 wait-state is possible.
+   */
+   /*
+   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
+   {
+   
+              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
+   
+   }
+   */
+   
+   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
+   
+   DMARAML4         : > RAML4,     PAGE = 1
+   DMARAML5         : > RAML5,     PAGE = 1
+   DMARAML6         : > RAML6,     PAGE = 1
+   DMARAML7         : > RAML7,     PAGE = 1
+   
+   ZONE7DATA        : > ZONE7B,    PAGE = 1  
+   
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used                    */
+   csm_rsvd         : > CSM_RSVD   PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
+   csmpasswds       : > CSM_PWL    PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
+   
+   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
+   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD
+
+     
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/

Source/External/v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd

@@ -0,0 +1,176 @@
+/*
+// TI File $Revision: /main/10 $
+// Checkin $Date: July 9, 2008   13:43:36 $
+//###########################################################################
+//
+// FILE:    28335_RAM_lnk.cmd
+//
+// TITLE:   Linker Command File For 28335 examples that run out of RAM
+//
+//          This ONLY includes all SARAM blocks on the 28335 device.
+//          This does not include flash or OTP. 
+//
+//          Keep in mind that L0 and L1 are protected by the code
+//          security module.
+//
+//          What this means is in most cases you will want to move to 
+//          another memory map file which has more memory defined.  
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+/* ======================================================
+// For Code Composer Studio V2.2 and later
+// ---------------------------------------
+// In addition to this memory linker command file, 
+// add the header linker command file directly to the project. 
+// The header linker command file is required to link the
+// peripheral structures to the proper locations within 
+// the memory map.
+//
+// The header linker files are found in <base>\DSP2833x_Headers\cmd
+//   
+// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
+// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
+========================================================= */
+
+/* ======================================================
+// For Code Composer Studio prior to V2.2
+// --------------------------------------
+// 1) Use one of the following -l statements to include the 
+// header linker command file in the project. The header linker
+// file is required to link the peripheral structures to the proper 
+// locations within the memory map                                    */
+
+/* Uncomment this line to include file only for non-BIOS applications */
+/* -l DSP2833x_Headers_nonBIOS.cmd */
+
+/* Uncomment this line to include file only for BIOS applications */
+/* -l DSP2833x_Headers_BIOS.cmd */
+
+/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
+   library search path under project->build options, linker tab, 
+   library search path (-i).
+/*========================================================= */
+
+/* Define the memory block start/length for the F28335  
+   PAGE 0 will be used to organize program sections
+   PAGE 1 will be used to organize data sections
+
+   Notes: 
+         Memory blocks on F28335 are uniform (ie same
+         physical memory) in both PAGE 0 and PAGE 1.  
+         That is the same memory region should not be
+         defined for both PAGE 0 and PAGE 1.
+         Doing so will result in corruption of program 
+         and/or data. 
+         
+         L0/L1/L2 and L3 memory blocks are mirrored - that is
+         they can be accessed in high memory or low memory.
+         For simplicity only one instance is used in this
+         linker file. 
+         
+         Contiguous SARAM memory blocks can be combined 
+         if required to create a larger memory block. 
+*/
+
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode      */
+   /* BOOT_RSVD is used by the boot ROM for stack.               */
+   /* This section is only reserved to keep the BOOT ROM from    */
+   /* corrupting this area during the debug process              */
+   
+   BEGIN      : origin = 0x000000, length = 0x000002     /* Boot to M0 will go here                      */
+   BOOT_RSVD  : origin = 0x000002, length = 0x00004E     /* Part of M0, BOOT rom will use this for stack */               
+   RAMM0      : origin = 0x000050, length = 0x0003B0
+
+   RAML0      : origin = 0x008000, length = 0x001000    
+   RAML1      : origin = 0x009000, length = 0x001000    
+   RAML2      : origin = 0x00A000, length = 0x001000    
+   RAML3      : origin = 0x00B000, length = 0x001000 
+   ZONE7A     : origin = 0x200000, length = 0x00FC00    /* XINTF zone 7 - program space */ 
+   CSM_RSVD   : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
+   CSM_PWL    : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA            */
+   ADC_CAL    : origin = 0x380080, length = 0x000009
+   RESET      : origin = 0x3FFFC0, length = 0x000002
+   IQTABLES   : origin = 0x3FE000, length = 0x000b50
+   IQTABLES2  : origin = 0x3FEB50, length = 0x00008c
+   FPUTABLES  : origin = 0x3FEBDC, length = 0x0006A0
+   BOOTROM    : origin = 0x3FF27C, length = 0x000D44               
+
+         
+PAGE 1 : 
+   RAMM1      : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAML4      : origin = 0x00C000, length = 0x001000    
+   RAML5      : origin = 0x00D000, length = 0x001000    
+   RAML6      : origin = 0x00E000, length = 0x001000    
+   RAML7      : origin = 0x00F000, length = 0x001000 
+   ZONE7B     : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
+}
+ 
+ 
+SECTIONS
+{
+   /* Setup for "boot to SARAM" mode: 
+      The codestart section (found in DSP28_CodeStartBranch.asm)
+      re-directs execution to the start of user code.  */
+   codestart        : > BEGIN,     PAGE = 0
+   ramfuncs         : > RAML0,     PAGE = 0  
+   .text            : > RAML1,     PAGE = 0
+   .cinit           : > RAML0,     PAGE = 0
+   .pinit           : > RAML0,     PAGE = 0
+   .switch          : > RAML0,     PAGE = 0
+   
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : > RAML4,     PAGE = 1
+   .econst          : > RAML5,     PAGE = 1      
+   .esysmem         : > RAMM1,     PAGE = 1
+
+   IQmath           : > RAML1,     PAGE = 0
+   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD 
+   
+   /* Uncomment the section below if calling the IQNexp() or IQexp()
+      functions from the IQMath.lib library in order to utilize the 
+      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
+      is 1 wait-state). If this section is not uncommented, IQmathTables2
+      will be loaded into other memory (SARAM, Flash, etc.) and will take
+      up space, but 0 wait-state is possible.
+   */
+   /*
+   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
+   {
+   
+              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
+   
+   }
+   */   
+
+   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
+      
+   DMARAML4         : > RAML4,     PAGE = 1
+   DMARAML5         : > RAML5,     PAGE = 1
+   DMARAML6         : > RAML6,     PAGE = 1
+   DMARAML7         : > RAML7,     PAGE = 1
+   
+   ZONE7DATA        : > ZONE7B,    PAGE = 1  
+
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used                    */
+   csm_rsvd         : > CSM_RSVD   PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
+   csmpasswds       : > CSM_PWL    PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
+   
+   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
+   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD
+     
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/

Source/External/v120/DSP2833x_common/cmd/F28332.cmd

@@ -0,0 +1,197 @@
+/*
+// TI File $Revision: /main/9 $
+// Checkin $Date: July 9, 2008   13:43:41 $
+//###########################################################################
+//
+// FILE:	F28332.cmd
+//
+// TITLE:	Linker Command File For F28332 Device
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+/* ======================================================
+// For Code Composer Studio V2.2 and later
+// ---------------------------------------
+// In addition to this memory linker command file, 
+// add the header linker command file directly to the project. 
+// The header linker command file is required to link the
+// peripheral structures to the proper locations within 
+// the memory map.
+//
+// The header linker files are found in <base>\DSP2833x_Headers\cmd
+//   
+// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
+// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
+========================================================= */
+
+/* ======================================================
+// For Code Composer Studio prior to V2.2
+// --------------------------------------
+// 1) Use one of the following -l statements to include the 
+// header linker command file in the project. The header linker
+// file is required to link the peripheral structures to the proper 
+// locations within the memory map                                    */
+
+/* Uncomment this line to include file only for non-BIOS applications */
+/* -l DSP2833x_Headers_nonBIOS.cmd */
+
+/* Uncomment this line to include file only for BIOS applications */
+/* -l DSP2833x_Headers_BIOS.cmd */
+
+/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
+   library search path under project->build options, linker tab, 
+   library search path (-i).
+/*========================================================= */
+
+/* Define the memory block start/length for the F28332  
+   PAGE 0 will be used to organize program sections
+   PAGE 1 will be used to organize data sections
+
+    Notes: 
+          Memory blocks on F28332 are uniform (ie same
+          physical memory) in both PAGE 0 and PAGE 1.  
+          That is the same memory region should not be
+          defined for both PAGE 0 and PAGE 1.
+          Doing so will result in corruption of program 
+          and/or data. 
+          
+          L0/L1/L2 and L3 memory blocks are mirrored - that is
+          they can be accessed in high memory or low memory.
+          For simplicity only one instance is used in this
+          linker file. 
+          
+          Contiguous SARAM memory blocks can be combined 
+          if required to create a larger memory block. 
+ */
+
+
+MEMORY
+{
+PAGE 0:    /* Program Memory */
+           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
+
+   ZONE0       : origin = 0x004000, length = 0x001000     /* XINTF zone 0 */
+   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
+   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
+   RAML2       : origin = 0x00A000, length = 0x001000     /* on-chip RAM block L2 */
+   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
+   ZONE6       : origin = 0x100000, length = 0x100000     /* XINTF zone 6 */ 
+   ZONE7A      : origin = 0x200000, length = 0x00FC00     /* XINTF zone 7 - program space */ 
+   FLASHD      : origin = 0x330000, length = 0x004000     /* on-chip FLASH */
+   FLASHC      : origin = 0x334000, length = 0x004000     /* on-chip FLASH */
+   FLASHA      : origin = 0x33C000, length = 0x003F80     /* on-chip FLASH */
+   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
+   BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
+   CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
+   OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
+   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */
+   
+   IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
+   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
+   FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
+   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */        
+   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
+   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
+
+PAGE 1 :   /* Data Memory */
+           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
+           /* Registers remain on PAGE1                                                  */
+   
+   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
+   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
+   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAML4       : origin = 0x00C000, length = 0x001000     /* on-chip RAM block L1 */
+   RAML5       : origin = 0x00D000, length = 0x001000     /* on-chip RAM block L1 */
+   ZONE7B      : origin = 0x20FC00, length = 0x0000400    /* XINTF zone 7 - data space */
+   FLASHB      : origin = 0x338000, length = 0x004000     /* on-chip FLASH */
+   
+}
+
+/* Allocate sections to memory blocks.
+   Note:
+         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
+                   execution when booting to flash
+         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
+*/ 
+ 
+SECTIONS
+{
+ 
+   /* Allocate program areas: */
+   .cinit              : > FLASHA      PAGE = 0
+   .pinit              : > FLASHA,     PAGE = 0
+   .text               : > FLASHA      PAGE = 0
+   codestart           : > BEGIN       PAGE = 0
+   ramfuncs            : LOAD = FLASHD, 
+                         RUN = RAML0, 
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         PAGE = 0
+
+   csmpasswds          : > CSM_PWL     PAGE = 0
+   csm_rsvd            : > CSM_RSVD    PAGE = 0
+   
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMM1       PAGE = 1
+   .ebss               : > RAML4       PAGE = 1
+   .esysmem            : > RAMM1       PAGE = 1
+
+   /* Initalized sections go in Flash */
+   /* For SDFlash to program these, they must be allocated to page 0 */
+   .econst             : > FLASHA      PAGE = 0
+   .switch             : > FLASHA      PAGE = 0      
+
+   /* Allocate IQ math areas: */
+   IQmath              : > FLASHC      PAGE = 0                  /* Math Code */
+   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD 
+   
+   /* Uncomment the section below if calling the IQNexp() or IQexp()
+      functions from the IQMath.lib library in order to utilize the 
+      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
+      is 1 wait-state). If this section is not uncommented, IQmathTables2
+      will be loaded into other memory (SARAM, Flash, etc.) and will take
+      up space, but 0 wait-state is possible.
+   */
+   /*
+   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
+   {
+   
+              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
+   
+   }
+   */
+   
+   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
+   
+   /* Allocate DMA-accessible RAM sections: */
+   DMARAML4         : > RAML4,     PAGE = 1
+   DMARAML5         : > RAML5,     PAGE = 1
+   
+   /* Allocate 0x400 of XINTF Zone 7 to storing data */
+   ZONE7DATA        : > ZONE7B,    PAGE = 1
+
+   /* .reset is a standard section used by the compiler.  It contains the */ 
+   /* the address of the start of _c_int00 for C Code.   /*
+   /* When using the boot ROM this section and the CPU vector */
+   /* table is not needed.  Thus the default type is set here to  */
+   /* DSECT  */ 
+   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
+   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
+   
+   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
+   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD
+
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
+

Source/External/v120/DSP2833x_common/cmd/F28334.cmd

@@ -0,0 +1,203 @@
+/*
+// TI File $Revision: /main/9 $
+// Checkin $Date: July 9, 2008   13:43:49 $
+//###########################################################################
+//
+// FILE:	F28334.cmd
+//
+// TITLE:	Linker Command File For F28334 Device
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+/* ======================================================
+// For Code Composer Studio V2.2 and later
+// ---------------------------------------
+// In addition to this memory linker command file, 
+// add the header linker command file directly to the project. 
+// The header linker command file is required to link the
+// peripheral structures to the proper locations within 
+// the memory map.
+//
+// The header linker files are found in <base>\DSP2833x_Headers\cmd
+//   
+// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
+// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
+========================================================= */
+
+/* ======================================================
+// For Code Composer Studio prior to V2.2
+// --------------------------------------
+// 1) Use one of the following -l statements to include the 
+// header linker command file in the project. The header linker
+// file is required to link the peripheral structures to the proper 
+// locations within the memory map                                    */
+
+/* Uncomment this line to include file only for non-BIOS applications */
+/* -l DSP2833x_Headers_nonBIOS.cmd */
+
+/* Uncomment this line to include file only for BIOS applications */
+/* -l DSP2833x_Headers_BIOS.cmd */
+
+/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
+   library search path under project->build options, linker tab, 
+   library search path (-i).
+/*========================================================= */
+
+/* Define the memory block start/length for the F28334  
+   PAGE 0 will be used to organize program sections
+   PAGE 1 will be used to organize data sections
+
+    Notes: 
+          Memory blocks on F28334 are uniform (ie same
+          physical memory) in both PAGE 0 and PAGE 1.  
+          That is the same memory region should not be
+          defined for both PAGE 0 and PAGE 1.
+          Doing so will result in corruption of program 
+          and/or data. 
+          
+          L0/L1/L2 and L3 memory blocks are mirrored - that is
+          they can be accessed in high memory or low memory.
+          For simplicity only one instance is used in this
+          linker file. 
+          
+          Contiguous SARAM memory blocks can be combined 
+          if required to create a larger memory block. 
+ */
+
+
+MEMORY
+{
+PAGE 0:    /* Program Memory */
+           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
+
+   ZONE0       : origin = 0x004000, length = 0x001000     /* XINTF zone 0 */
+   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
+   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
+   RAML2       : origin = 0x00A000, length = 0x001000     /* on-chip RAM block L2 */
+   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
+   ZONE6       : origin = 0x100000, length = 0x0100000    /* XINTF zone 6 */ 
+   ZONE7A      : origin = 0x200000, length = 0x000FC00    /* XINTF zone 7 - program space */ 
+   FLASHH      : origin = 0x320000, length = 0x004000     /* on-chip FLASH */
+   FLASHG      : origin = 0x324000, length = 0x004000     /* on-chip FLASH */
+   FLASHF      : origin = 0x328000, length = 0x004000     /* on-chip FLASH */
+   FLASHE      : origin = 0x32C000, length = 0x004000     /* on-chip FLASH */
+   FLASHD      : origin = 0x330000, length = 0x004000     /* on-chip FLASH */
+   FLASHC      : origin = 0x334000, length = 0x004000     /* on-chip FLASH */
+   FLASHA      : origin = 0x33C000, length = 0x003F80     /* on-chip FLASH */
+   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
+   BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
+   CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
+   OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
+   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */
+   
+   IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
+   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
+   FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
+   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */          
+   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
+   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
+
+PAGE 1 :   /* Data Memory */
+           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
+           /* Registers remain on PAGE1                                                  */
+   
+   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
+   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
+   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAML4       : origin = 0x00C000, length = 0x001000     /* on-chip RAM block L1 */
+   RAML5       : origin = 0x00D000, length = 0x001000     /* on-chip RAM block L1 */
+   RAML6       : origin = 0x00E000, length = 0x001000     /* on-chip RAM block L1 */
+   RAML7       : origin = 0x00F000, length = 0x001000     /* on-chip RAM block L1 */
+   ZONE7B      : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
+   FLASHB      : origin = 0x338000, length = 0x004000     /* on-chip FLASH */
+}
+
+/* Allocate sections to memory blocks.
+   Note:
+         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
+                   execution when booting to flash
+         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
+*/ 
+ 
+SECTIONS
+{
+ 
+   /* Allocate program areas: */
+   .cinit              : > FLASHA      PAGE = 0
+   .pinit              : > FLASHA,     PAGE = 0
+   .text               : > FLASHA      PAGE = 0
+   codestart           : > BEGIN       PAGE = 0
+   ramfuncs            : LOAD = FLASHD, 
+                         RUN = RAML0, 
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         PAGE = 0
+
+   csmpasswds          : > CSM_PWL     PAGE = 0
+   csm_rsvd            : > CSM_RSVD    PAGE = 0
+   
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMM1       PAGE = 1
+   .ebss               : > RAML4       PAGE = 1
+   .esysmem            : > RAMM1       PAGE = 1
+
+   /* Initalized sections go in Flash */
+   /* For SDFlash to program these, they must be allocated to page 0 */
+   .econst             : > FLASHA      PAGE = 0
+   .switch             : > FLASHA      PAGE = 0      
+
+   /* Allocate IQ math areas: */
+   IQmath              : > FLASHC      PAGE = 0                  /* Math Code */
+   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD 
+   
+   /* Uncomment the section below if calling the IQNexp() or IQexp()
+      functions from the IQMath.lib library in order to utilize the 
+      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
+      is 1 wait-state). If this section is not uncommented, IQmathTables2
+      will be loaded into other memory (SARAM, Flash, etc.) and will take
+      up space, but 0 wait-state is possible.
+   */
+   /*
+   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
+   {
+   
+              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
+   
+   }
+   */
+   
+   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
+      
+   /* Allocate DMA-accessible RAM sections: */
+   DMARAML4         : > RAML4,     PAGE = 1
+   DMARAML5         : > RAML5,     PAGE = 1
+   DMARAML6         : > RAML6,     PAGE = 1
+   DMARAML7         : > RAML7,     PAGE = 1
+   
+   /* Allocate 0x400 of XINTF Zone 7 to storing data */
+   ZONE7DATA        : > ZONE7B,    PAGE = 1
+
+   /* .reset is a standard section used by the compiler.  It contains the */ 
+   /* the address of the start of _c_int00 for C Code.   /*
+   /* When using the boot ROM this section and the CPU vector */
+   /* table is not needed.  Thus the default type is set here to  */
+   /* DSECT  */ 
+   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
+   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
+   
+   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
+   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
+

Source/External/v120/DSP2833x_common/cmd/F28335.cmd

@@ -0,0 +1,203 @@
+/*
+// TI File $Revision: /main/10 $
+// Checkin $Date: July 9, 2008   13:43:56 $
+//###########################################################################
+//
+// FILE:	F28335.cmd
+//
+// TITLE:	Linker Command File For F28335 Device
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+/* ======================================================
+// For Code Composer Studio V2.2 and later
+// ---------------------------------------
+// In addition to this memory linker command file, 
+// add the header linker command file directly to the project. 
+// The header linker command file is required to link the
+// peripheral structures to the proper locations within 
+// the memory map.
+//
+// The header linker files are found in <base>\DSP2833x_Headers\cmd
+//   
+// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
+// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
+========================================================= */
+
+/* ======================================================
+// For Code Composer Studio prior to V2.2
+// --------------------------------------
+// 1) Use one of the following -l statements to include the 
+// header linker command file in the project. The header linker
+// file is required to link the peripheral structures to the proper 
+// locations within the memory map                                    */
+
+/* Uncomment this line to include file only for non-BIOS applications */
+/* -l DSP2833x_Headers_nonBIOS.cmd */
+
+/* Uncomment this line to include file only for BIOS applications */
+/* -l DSP2833x_Headers_BIOS.cmd */
+
+/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
+   library search path under project->build options, linker tab, 
+   library search path (-i).
+/*========================================================= */
+
+/* Define the memory block start/length for the F28335  
+   PAGE 0 will be used to organize program sections
+   PAGE 1 will be used to organize data sections
+
+    Notes: 
+          Memory blocks on F28335 are uniform (ie same
+          physical memory) in both PAGE 0 and PAGE 1.  
+          That is the same memory region should not be
+          defined for both PAGE 0 and PAGE 1.
+          Doing so will result in corruption of program 
+          and/or data. 
+          
+          L0/L1/L2 and L3 memory blocks are mirrored - that is
+          they can be accessed in high memory or low memory.
+          For simplicity only one instance is used in this
+          linker file. 
+          
+          Contiguous SARAM memory blocks can be combined 
+          if required to create a larger memory block. 
+ */
+
+
+MEMORY
+{
+PAGE 0:    /* Program Memory */
+           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
+
+   ZONE0       : origin = 0x004000, length = 0x001000     /* XINTF zone 0 */
+   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
+   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
+   RAML2       : origin = 0x00A000, length = 0x001000     /* on-chip RAM block L2 */
+   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
+   ZONE6       : origin = 0x0100000, length = 0x100000    /* XINTF zone 6 */ 
+   ZONE7A      : origin = 0x0200000, length = 0x00FC00    /* XINTF zone 7 - program space */ 
+   FLASHH      : origin = 0x300000, length = 0x008000     /* on-chip FLASH */
+   FLASHG      : origin = 0x308000, length = 0x008000     /* on-chip FLASH */
+   FLASHF      : origin = 0x310000, length = 0x008000     /* on-chip FLASH */
+   FLASHE      : origin = 0x318000, length = 0x008000     /* on-chip FLASH */
+   FLASHD      : origin = 0x320000, length = 0x008000     /* on-chip FLASH */
+   FLASHC      : origin = 0x328000, length = 0x008000     /* on-chip FLASH */
+   FLASHA      : origin = 0x338000, length = 0x007F80     /* on-chip FLASH */
+   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
+   BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
+   CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
+   OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
+   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */
+   
+   IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
+   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
+   FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
+   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */        
+   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
+   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
+
+PAGE 1 :   /* Data Memory */
+           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
+           /* Registers remain on PAGE1                                                  */
+   
+   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
+   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
+   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAML4       : origin = 0x00C000, length = 0x001000     /* on-chip RAM block L1 */
+   RAML5       : origin = 0x00D000, length = 0x001000     /* on-chip RAM block L1 */
+   RAML6       : origin = 0x00E000, length = 0x001000     /* on-chip RAM block L1 */
+   RAML7       : origin = 0x00F000, length = 0x001000     /* on-chip RAM block L1 */
+   ZONE7B      : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
+   FLASHB      : origin = 0x330000, length = 0x008000     /* on-chip FLASH */
+}
+
+/* Allocate sections to memory blocks.
+   Note:
+         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
+                   execution when booting to flash
+         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
+*/ 
+ 
+SECTIONS
+{
+ 
+   /* Allocate program areas: */
+   .cinit              : > FLASHA      PAGE = 0
+   .pinit              : > FLASHA,     PAGE = 0
+   .text               : > FLASHA      PAGE = 0
+   codestart           : > BEGIN       PAGE = 0
+   ramfuncs            : LOAD = FLASHD, 
+                         RUN = RAML0, 
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         PAGE = 0
+
+   csmpasswds          : > CSM_PWL     PAGE = 0
+   csm_rsvd            : > CSM_RSVD    PAGE = 0
+   
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMM1       PAGE = 1
+   .ebss               : > RAML4       PAGE = 1
+   .esysmem            : > RAMM1       PAGE = 1
+
+   /* Initalized sections go in Flash */
+   /* For SDFlash to program these, they must be allocated to page 0 */
+   .econst             : > FLASHA      PAGE = 0
+   .switch             : > FLASHA      PAGE = 0      
+
+   /* Allocate IQ math areas: */
+   IQmath              : > FLASHC      PAGE = 0                  /* Math Code */
+   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD 
+   
+   /* Uncomment the section below if calling the IQNexp() or IQexp()
+      functions from the IQMath.lib library in order to utilize the 
+      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
+      is 1 wait-state). If this section is not uncommented, IQmathTables2
+      will be loaded into other memory (SARAM, Flash, etc.) and will take
+      up space, but 0 wait-state is possible.
+   */
+   /*
+   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
+   {
+   
+              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
+   
+   }
+   */
+   
+   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
+         
+   /* Allocate DMA-accessible RAM sections: */
+   DMARAML4         : > RAML4,     PAGE = 1
+   DMARAML5         : > RAML5,     PAGE = 1
+   DMARAML6         : > RAML6,     PAGE = 1
+   DMARAML7         : > RAML7,     PAGE = 1
+   
+   /* Allocate 0x400 of XINTF Zone 7 to storing data */
+   ZONE7DATA        : > ZONE7B,    PAGE = 1
+
+   /* .reset is a standard section used by the compiler.  It contains the */ 
+   /* the address of the start of _c_int00 for C Code.   /*
+   /* When using the boot ROM this section and the CPU vector */
+   /* table is not needed.  Thus the default type is set here to  */
+   /* DSECT  */ 
+   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
+   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
+   
+   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
+   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
+

Source/External/v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h

@@ -0,0 +1,147 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006   13:45:37 $
+//###########################################################################
+//
+// FILE:    DSP2833x_DefaultIsr.h
+//
+// TITLE:   DSP2833x Devices Default Interrupt Service Routines Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_DEFAULT_ISR_H
+#define DSP2833x_DEFAULT_ISR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//---------------------------------------------------------------------------
+// Default Interrupt Service Routine Declarations:
+// 
+// The following function prototypes are for the 
+// default ISR routines used with the default PIE vector table.
+// This default vector table is found in the DSP2833x_PieVect.h 
+// file.  
+//
+
+// Non-Peripheral Interrupts:
+interrupt void INT13_ISR(void);     // XINT13 or CPU-Timer 1
+interrupt void INT14_ISR(void);     // CPU-Timer2
+interrupt void DATALOG_ISR(void);   // Datalogging interrupt
+interrupt void RTOSINT_ISR(void);   // RTOS interrupt
+interrupt void EMUINT_ISR(void);    // Emulation interrupt
+interrupt void NMI_ISR(void);       // Non-maskable interrupt
+interrupt void ILLEGAL_ISR(void);   // Illegal operation TRAP
+interrupt void USER1_ISR(void);     // User Defined trap 1
+interrupt void USER2_ISR(void);     // User Defined trap 2
+interrupt void USER3_ISR(void);     // User Defined trap 3
+interrupt void USER4_ISR(void);     // User Defined trap 4
+interrupt void USER5_ISR(void);     // User Defined trap 5
+interrupt void USER6_ISR(void);     // User Defined trap 6
+interrupt void USER7_ISR(void);     // User Defined trap 7
+interrupt void USER8_ISR(void);     // User Defined trap 8
+interrupt void USER9_ISR(void);     // User Defined trap 9
+interrupt void USER10_ISR(void);    // User Defined trap 10
+interrupt void USER11_ISR(void);    // User Defined trap 11
+interrupt void USER12_ISR(void);    // User Defined trap 12
+
+// Group 1 PIE Interrupt Service Routines:
+interrupt void  SEQ1INT_ISR(void);   // ADC Sequencer 1 ISR
+interrupt void  SEQ2INT_ISR(void);   // ADC Sequencer 2 ISR
+interrupt void  XINT1_ISR(void);     // External interrupt 1
+interrupt void  XINT2_ISR(void);     // External interrupt 2
+interrupt void  ADCINT_ISR(void);    // ADC
+interrupt void  TINT0_ISR(void);     // Timer 0
+interrupt void  WAKEINT_ISR(void);   // WD
+
+// Group 2 PIE Interrupt Service Routines:
+interrupt void EPWM1_TZINT_ISR(void);    // EPWM-1
+interrupt void EPWM2_TZINT_ISR(void);    // EPWM-2
+interrupt void EPWM3_TZINT_ISR(void);    // EPWM-3
+interrupt void EPWM4_TZINT_ISR(void);    // EPWM-4
+interrupt void EPWM5_TZINT_ISR(void);    // EPWM-5
+interrupt void EPWM6_TZINT_ISR(void);    // EPWM-6
+      
+// Group 3 PIE Interrupt Service Routines:
+interrupt void EPWM1_INT_ISR(void);    // EPWM-1
+interrupt void EPWM2_INT_ISR(void);    // EPWM-2
+interrupt void EPWM3_INT_ISR(void);    // EPWM-3
+interrupt void EPWM4_INT_ISR(void);    // EPWM-4
+interrupt void EPWM5_INT_ISR(void);    // EPWM-5
+interrupt void EPWM6_INT_ISR(void);    // EPWM-6
+      
+// Group 4 PIE Interrupt Service Routines:
+interrupt void ECAP1_INT_ISR(void);    // ECAP-1
+interrupt void ECAP2_INT_ISR(void);    // ECAP-2
+interrupt void ECAP3_INT_ISR(void);    // ECAP-3
+interrupt void ECAP4_INT_ISR(void);    // ECAP-4
+interrupt void ECAP5_INT_ISR(void);    // ECAP-5
+interrupt void ECAP6_INT_ISR(void);    // ECAP-6
+     
+// Group 5 PIE Interrupt Service Routines:
+interrupt void EQEP1_INT_ISR(void);    // EQEP-1
+interrupt void EQEP2_INT_ISR(void);    // EQEP-2
+
+// Group 6 PIE Interrupt Service Routines:
+interrupt void SPIRXINTA_ISR(void);   // SPI-A
+interrupt void SPITXINTA_ISR(void);   // SPI-A
+interrupt void MRINTA_ISR(void);      // McBSP-A
+interrupt void MXINTA_ISR(void);      // McBSP-A
+interrupt void MRINTB_ISR(void);      // McBSP-B
+interrupt void MXINTB_ISR(void);      // McBSP-B
+
+// Group 7 PIE Interrupt Service Routines:
+interrupt void DINTCH1_ISR(void);     // DMA-Channel 1
+interrupt void DINTCH2_ISR(void);     // DMA-Channel 2
+interrupt void DINTCH3_ISR(void);     // DMA-Channel 3
+interrupt void DINTCH4_ISR(void);     // DMA-Channel 4
+interrupt void DINTCH5_ISR(void);     // DMA-Channel 5
+interrupt void DINTCH6_ISR(void);     // DMA-Channel 6
+
+// Group 8 PIE Interrupt Service Routines: 
+interrupt void I2CINT1A_ISR(void);     // I2C-A
+interrupt void I2CINT2A_ISR(void);     // I2C-A
+interrupt void SCIRXINTC_ISR(void);    // SCI-C
+interrupt void SCITXINTC_ISR(void);    // SCI-C
+   
+// Group 9 PIE Interrupt Service Routines:
+interrupt void SCIRXINTA_ISR(void);    // SCI-A
+interrupt void SCITXINTA_ISR(void);    // SCI-A
+interrupt void SCIRXINTB_ISR(void);    // SCI-B
+interrupt void SCITXINTB_ISR(void);    // SCI-B
+interrupt void ECAN0INTA_ISR(void);    // eCAN-A
+interrupt void ECAN1INTA_ISR(void);    // eCAN-A
+interrupt void ECAN0INTB_ISR(void);    // eCAN-B
+interrupt void ECAN1INTB_ISR(void);    // eCAN-B
+
+// Group 10 PIE Interrupt Service Routines:
+ 
+// Group 11 PIE Interrupt Service Routines: 
+
+// Group 12 PIE Interrupt Service Routines: 
+interrupt void  XINT3_ISR(void);     // External interrupt 3
+interrupt void  XINT4_ISR(void);     // External interrupt 4
+interrupt void  XINT5_ISR(void);     // External interrupt 5
+interrupt void  XINT6_ISR(void);     // External interrupt 6
+interrupt void  XINT7_ISR(void);     // External interrupt 7
+interrupt void  LVF_ISR(void);       // Latched overflow flag
+interrupt void  LUF_ISR(void);       // Latched underflow flag
+
+// Catch-all for Reserved Locations For testing purposes:
+interrupt void PIE_RESERVED(void);       // Reserved for test
+interrupt void rsvd_ISR(void);           // for test
+interrupt void INT_NOTUSED_ISR(void);    // for unused interrupts
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif    // end of DSP2833x_DEFAULT_ISR_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/include/DSP2833x_Dma_defines.h

@@ -0,0 +1,81 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: August 14, 2007   16:32:29 $
+//###########################################################################
+//
+// FILE:   DSP2833x_Dma_defines.h
+//
+// TITLE:  #defines used in DMA examples
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_DMA_DEFINES_H
+#define DSP2833x_DMA_DEFINES_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// MODE
+//==========================
+// PERINTSEL bits
+#define DMA_SEQ1INT 1
+#define DMA_SEQ2INT 2
+#define DMA_XINT1   3
+#define DMA_XINT2   4
+#define DMA_XINT3   5
+#define DMA_XINT4   6
+#define DMA_XINT5   7
+#define DMA_XINT6   8
+#define DMA_XINT7   9
+#define DMA_XINT13  10
+#define DMA_TINT0   11
+#define DMA_TINT1   12
+#define DMA_TINT2   13
+#define DMA_MXEVTA  14
+#define DMA_MREVTA  15
+#define DMA_MXREVTB 16
+#define DMA_MREVTB  17
+// OVERINTE bit
+#define	OVRFLOW_DISABLE	0x0
+#define	OVEFLOW_ENABLE	0x1
+// PERINTE bit
+#define	PERINT_DISABLE	0x0
+#define	PERINT_ENABLE   0x1
+// CHINTMODE bits
+#define	CHINT_BEGIN		0x0
+#define	CHINT_END     	0x1
+// ONESHOT bits
+#define	ONESHOT_DISABLE	0x0
+#define	ONESHOT_ENABLE	0x1
+// CONTINOUS bit
+#define	CONT_DISABLE	0x0
+#define	CONT_ENABLE 	0x1
+// SYNCE bit
+#define	SYNC_DISABLE	0x0
+#define	SYNC_ENABLE     0x1
+// SYNCSEL bit
+#define	SYNC_SRC		0x0
+#define	SYNC_DST        0x1
+// DATASIZE bit
+#define	SIXTEEN_BIT    	0x0
+#define	THIRTYTWO_BIT   0x1
+// CHINTE bit
+#define	CHINT_DISABLE	0x0
+#define	CHINT_ENABLE   	0x1
+
+
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif   // - end of DSP2833x_EPWM_DEFINES_H
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/include/DSP2833x_EPwm_defines.h

@@ -0,0 +1,164 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006   13:45:39 $
+//###########################################################################
+//
+// FILE:   DSP2833x_EPwm_defines.h
+//
+// TITLE:  #defines used in ePWM examples examples
+// 
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_EPWM_DEFINES_H
+#define DSP2833x_EPWM_DEFINES_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TBCTL (Time-Base Control)
+//==========================
+// CTRMODE bits
+#define	TB_COUNT_UP		0x0
+#define	TB_COUNT_DOWN	0x1
+#define	TB_COUNT_UPDOWN	0x2
+#define	TB_FREEZE		0x3
+// PHSEN bit
+#define	TB_DISABLE		0x0
+#define	TB_ENABLE		0x1
+// PRDLD bit
+#define	TB_SHADOW		0x0
+#define	TB_IMMEDIATE	0x1
+// SYNCOSEL bits
+#define	TB_SYNC_IN		0x0
+#define	TB_CTR_ZERO		0x1
+#define	TB_CTR_CMPB		0x2
+#define	TB_SYNC_DISABLE	0x3
+// HSPCLKDIV and CLKDIV bits
+#define	TB_DIV1			0x0
+#define	TB_DIV2			0x1
+#define	TB_DIV4			0x2
+// PHSDIR bit
+#define	TB_DOWN			0x0
+#define	TB_UP			0x1
+
+// CMPCTL (Compare Control)
+//==========================
+// LOADAMODE and LOADBMODE bits
+#define	CC_CTR_ZERO		0x0
+#define	CC_CTR_PRD		0x1
+#define	CC_CTR_ZERO_PRD	0x2
+#define	CC_LD_DISABLE	0x3
+// SHDWAMODE and SHDWBMODE bits
+#define	CC_SHADOW		0x0
+#define	CC_IMMEDIATE	0x1
+
+// AQCTLA and AQCTLB (Action Qualifier Control)
+//=============================================
+// ZRO, PRD, CAU, CAD, CBU, CBD bits
+#define	AQ_NO_ACTION	0x0
+#define	AQ_CLEAR		0x1
+#define	AQ_SET			0x2
+#define	AQ_TOGGLE		0x3
+
+// DBCTL (Dead-Band Control)
+//==========================
+// OUT MODE bits
+#define	DB_DISABLE		0x0
+#define	DBA_ENABLE		0x1
+#define	DBB_ENABLE		0x2
+#define	DB_FULL_ENABLE	0x3
+// POLSEL bits
+#define	DB_ACTV_HI		0x0
+#define	DB_ACTV_LOC		0x1
+#define	DB_ACTV_HIC		0x2
+#define	DB_ACTV_LO		0x3
+// IN MODE
+#define DBA_ALL         0x0
+#define DBB_RED_DBA_FED 0x1
+#define DBA_RED_DBB_FED 0x2
+#define DBB_ALL         0x3
+
+// CHPCTL (chopper control)
+//==========================
+// CHPEN bit
+#define	CHP_DISABLE		0x0
+#define	CHP_ENABLE		0x1
+// CHPFREQ bits
+#define	CHP_DIV1		0x0
+#define	CHP_DIV2		0x1
+#define	CHP_DIV3		0x2
+#define	CHP_DIV4		0x3
+#define	CHP_DIV5		0x4
+#define	CHP_DIV6		0x5
+#define	CHP_DIV7		0x6
+#define	CHP_DIV8		0x7
+// CHPDUTY bits
+#define	CHP1_8TH		0x0
+#define	CHP2_8TH		0x1
+#define	CHP3_8TH		0x2
+#define	CHP4_8TH		0x3
+#define	CHP5_8TH		0x4
+#define	CHP6_8TH		0x5
+#define	CHP7_8TH		0x6
+
+// TZSEL (Trip Zone Select)
+//==========================
+// CBCn and OSHTn bits
+#define	TZ_DISABLE		0x0
+#define	TZ_ENABLE		0x1
+
+// TZCTL (Trip Zone Control)
+//==========================
+// TZA and TZB bits
+#define	TZ_HIZ			0x0
+#define	TZ_FORCE_HI		0x1
+#define	TZ_FORCE_LO		0x2
+#define	TZ_NO_CHANGE	0x3
+
+// ETSEL (Event Trigger Select)
+//=============================
+#define	ET_CTR_ZERO		0x1
+#define	ET_CTR_PRD		0x2
+#define	ET_CTRU_CMPA	0x4
+#define	ET_CTRD_CMPA	0x5
+#define	ET_CTRU_CMPB	0x6
+#define	ET_CTRD_CMPB	0x7
+
+// ETPS (Event Trigger Pre-scale)
+//===============================
+// INTPRD, SOCAPRD, SOCBPRD bits
+#define	ET_DISABLE		0x0
+#define	ET_1ST			0x1
+#define	ET_2ND			0x2
+#define	ET_3RD			0x3
+
+
+//--------------------------------
+// HRPWM (High Resolution PWM)
+//================================
+// HRCNFG
+#define	HR_Disable		0x0
+#define	HR_REP			0x1
+#define	HR_FEP			0x2
+#define	HR_BEP			0x3
+
+#define	HR_CMP			0x0
+#define	HR_PHS			0x1
+
+#define	HR_CTR_ZERO		0x0
+#define	HR_CTR_PRD		0x1
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif   // - end of DSP2833x_EPWM_DEFINES_H
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/include/DSP2833x_Examples.h

@@ -0,0 +1,143 @@
+// TI File $Revision: /main/9 $
+// Checkin $Date: July 2, 2008   14:31:12 $
+//###########################################################################
+//
+// FILE:   DSP2833x_Examples.h
+//
+// TITLE:  DSP2833x Device Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_EXAMPLES_H
+#define DSP2833x_EXAMPLES_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*-----------------------------------------------------------------------------
+      Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
+-----------------------------------------------------------------------------*/
+//#define DSP28_DIVSEL   0   // Enable /4 for SYSCLKOUT
+//#define DSP28_DIVSEL   1 // Enable /4 for SYSCKOUT
+#define DSP28_DIVSEL     2 // Enable /2 for SYSCLKOUT
+//#define DSP28_DIVSEL     3 // Enable /1 for SYSCLKOUT
+
+#define DSP28_PLLCR	CLKMULT*2
+
+//#define DSP28_PLLCR   10
+//#define DSP28_PLLCR    9
+//#define DSP28_PLLCR    8
+//#define DSP28_PLLCR    7
+//#define DSP28_PLLCR    6
+//#define DSP28_PLLCR    5
+//#define DSP28_PLLCR    4
+//#define DSP28_PLLCR    3
+//#define DSP28_PLLCR    2
+//#define DSP28_PLLCR    1
+//#define DSP28_PLLCR    0  // PLL is bypassed in this mode
+//----------------------------------------------------------------------------
+
+
+/*-----------------------------------------------------------------------------
+      Specify the clock rate of the CPU (SYSCLKOUT) in nS.
+
+      Take into account the input clock frequency and the PLL multiplier
+      selected in step 1.
+
+      Use one of the values provided, or define your own.
+      The trailing L is required tells the compiler to treat
+      the number as a 64-bit value.
+
+      Only one statement should be uncommented.
+
+      Example 1:150 MHz devices:
+                CLKIN is a 30MHz crystal.
+
+                In step 1 the user specified PLLCR = 0xA for a
+                150Mhz CPU clock (SYSCLKOUT = 150MHz).
+
+                In this case, the CPU_RATE will be 6.667L
+                Uncomment the line:  #define CPU_RATE  6.667L
+
+      Example 2:  100 MHz devices:
+                  CLKIN is a 20MHz crystal.
+
+	              In step 1 the user specified PLLCR = 0xA for a
+	              100Mhz CPU clock (SYSCLKOUT = 100MHz).
+
+	              In this case, the CPU_RATE will be 10.000L
+                  Uncomment the line:  #define CPU_RATE  10.000L
+-----------------------------------------------------------------------------*/
+#define CPU_RATE    6.667L   // for a 150MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE    7.143L   // for a 140MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE    8.333L   // for a 120MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE   10.000L   // for a 100MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE   13.330L   // for a 75MHz CPU clock speed (SYSCLKOUT)
+//#define CPU_RATE   20.000L   // for a 50MHz CPU clock speed  (SYSCLKOUT)
+//#define CPU_RATE   33.333L   // for a 30MHz CPU clock speed  (SYSCLKOUT)
+//#define CPU_RATE   41.667L   // for a 24MHz CPU clock speed  (SYSCLKOUT)
+//#define CPU_RATE   50.000L   // for a 20MHz CPU clock speed  (SYSCLKOUT)
+//#define CPU_RATE   66.667L   // for a 15MHz CPU clock speed  (SYSCLKOUT)
+//#define CPU_RATE  100.000L   // for a 10MHz CPU clock speed  (SYSCLKOUT)
+
+//----------------------------------------------------------------------------
+
+/*-----------------------------------------------------------------------------
+      Target device (in DSP2833x_Device.h) determines CPU frequency
+      (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
+      (for 28332). User does not have to change anything here.
+-----------------------------------------------------------------------------*/
+#if DSP28_28332                   // DSP28_28332 device only
+  #define CPU_FRQ_100MHZ    1     // 100 Mhz CPU Freq (20 MHz input freq)
+  #define CPU_FRQ_150MHZ    0
+#else
+  #define CPU_FRQ_100MHZ    0     // DSP28_28335||DSP28_28334
+  #define CPU_FRQ_150MHZ    1     // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
+#endif
+
+
+//---------------------------------------------------------------------------
+// Include Example Header Files:
+//
+
+#include "DSP2833x_GlobalPrototypes.h"         // Prototypes for global functions within the
+                                              // .c files.
+
+#include "DSP2833x_ePwm_defines.h"             // Macros used for PWM examples.
+#include "DSP2833x_Dma_defines.h"              // Macros used for DMA examples.
+#include "DSP2833x_I2C_defines.h"              // Macros used for I2C examples.
+
+#define PARTNO_28335  0xEF
+#define PARTNO_28334  0xEE
+#define PARTNO_28332  0xED
+#define PARTNO_28235  0xE8
+#define PARTNO_28234  0xE7
+#define PARTNO_28232  0xE6
+
+
+// Include files not used with DSP/BIOS
+#ifndef DSP28_BIOS
+#include "DSP2833x_DefaultISR.h"
+#endif
+
+
+// DO NOT MODIFY THIS LINE.
+#define DELAY_US(A)  DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L)
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif  // end of DSP2833x_EXAMPLES_H definition
+
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/include/DSP2833x_GlobalPrototypes.h

@@ -0,0 +1,207 @@
+// TI File $Revision: /main/11 $
+// Checkin $Date: May 12, 2008   14:30:08 $
+//###########################################################################
+//
+// FILE:   DSP2833x_GlobalPrototypes.h
+//
+// TITLE:  Global prototypes for DSP2833x Examples
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_GLOBALPROTOTYPES_H
+#define DSP2833x_GLOBALPROTOTYPES_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*---- shared global function prototypes -----------------------------------*/
+extern void InitAdc(void);
+
+extern void DMAInitialize(void);
+// DMA Channel 1
+extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH1(void);
+// DMA Channel 2
+extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH2(void);
+// DMA Channel 3
+extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH3(void);
+// DMA Channel 4
+extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH4(void);
+// DMA Channel 5
+extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
+extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH5(void);
+// DMA Channel 6
+extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
+extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep);
+extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
+extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
+extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
+extern void StartDMACH6(void);
+
+extern void InitPeripherals(void);
+#if DSP28_ECANA
+extern void InitECan(void);
+extern void InitECana(void);
+extern void InitECanGpio(void);
+extern void InitECanaGpio(void);
+#endif // endif DSP28_ECANA
+#if DSP28_ECANB
+extern void InitECanb(void);
+extern void InitECanbGpio(void);
+#endif // endif DSP28_ECANB
+extern void InitECap(void);
+extern void InitECapGpio(void);
+extern void InitECap1Gpio(void);
+extern void InitECap2Gpio(void);
+#if DSP28_ECAP3
+extern void InitECap3Gpio(void);
+#endif // endif DSP28_ECAP3
+#if DSP28_ECAP4
+extern void InitECap4Gpio(void);
+#endif // endif DSP28_ECAP4
+#if DSP28_ECAP5
+extern void InitECap5Gpio(void);
+#endif // endif DSP28_ECAP5
+#if DSP28_ECAP6
+extern void InitECap6Gpio(void);
+#endif // endif DSP28_ECAP6
+extern void InitEPwm(void);
+extern void InitEPwmGpio(void);
+extern void InitEPwm1Gpio(void);
+extern void InitEPwm2Gpio(void);
+extern void InitEPwm3Gpio(void);
+#if DSP28_EPWM4
+extern void InitEPwm4Gpio(void);
+#endif // endif DSP28_EPWM4
+#if DSP28_EPWM5
+extern void InitEPwm5Gpio(void);
+#endif // endif DSP28_EPWM5
+#if DSP28_EPWM6
+extern void InitEPwm6Gpio(void);
+#endif // endif DSP28_EPWM6
+#if DSP28_EQEP1
+extern void InitEQep(void);
+extern void InitEQepGpio(void);
+extern void InitEQep1Gpio(void);
+#endif // if DSP28_EQEP1
+#if DSP28_EQEP2
+extern void InitEQep2Gpio(void);
+#endif // endif DSP28_EQEP2
+extern void InitGpio(void);
+extern void InitI2CGpio(void);
+
+extern void InitMcbsp(void);
+extern void InitMcbspa(void);
+extern void delay_loop(void);
+extern void InitMcbspaGpio(void);
+extern void InitMcbspa8bit(void);
+extern void InitMcbspa12bit(void);
+extern void InitMcbspa16bit(void);
+extern void InitMcbspa20bit(void);
+extern void InitMcbspa24bit(void);
+extern void InitMcbspa32bit(void);
+#if DSP28_MCBSPB
+extern void InitMcbspb(void);
+extern void InitMcbspbGpio(void);
+extern void InitMcbspb8bit(void);
+extern void InitMcbspb12bit(void);
+extern void InitMcbspb16bit(void);
+extern void InitMcbspb20bit(void);
+extern void InitMcbspb24bit(void);
+extern void InitMcbspb32bit(void);
+#endif // endif DSP28_MCBSPB
+
+extern void InitPieCtrl(void);
+extern void InitPieVectTable(void);
+
+extern void InitSci(void);
+extern void InitSciGpio(void);
+extern void InitSciaGpio(void);
+#if DSP28_SCIB
+extern void InitScibGpio(void);
+#endif // endif DSP28_SCIB
+#if DSP28_SCIC
+extern void InitScicGpio(void);
+#endif
+extern void InitSpi(void);
+extern void InitSpiGpio(void);
+extern void InitSpiaGpio(void);
+extern void InitSysCtrl(void);
+extern void InitTzGpio(void);
+extern void InitXIntrupt(void);
+extern void XintfInit(void);
+extern void InitXintf16Gpio();
+extern void InitXintf32Gpio();
+extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
+extern void InitPeripheralClocks(void);
+extern void EnableInterrupts(void);
+extern void DSP28x_usDelay(Uint32 Count);
+extern void ADC_cal (void);
+#define KickDog ServiceDog     // For compatiblity with previous versions
+extern void ServiceDog(void);
+extern void DisableDog(void);
+extern Uint16 CsmUnlock(void);
+
+// DSP28_DBGIER.asm
+extern void SetDBGIER(Uint16 dbgier);
+
+//                 CAUTION
+// This function MUST be executed out of RAM. Executing it
+// out of OTP/Flash will yield unpredictable results
+extern void InitFlash(void);
+
+
+void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
+
+
+//---------------------------------------------------------------------------
+// External symbols created by the linker cmd file
+// DSP28 examples will use these to relocate code from one LOAD location
+// in either Flash or XINTF to a different RUN location in internal
+// RAM
+extern Uint16 RamfuncsLoadStart;
+extern Uint16 RamfuncsLoadEnd;
+extern Uint16 RamfuncsRunStart;
+
+extern Uint16 XintffuncsLoadStart;
+extern Uint16 XintffuncsLoadEnd;
+extern Uint16 XintffuncsRunStart;
+
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif   // - end of DSP2833x_GLOBALPROTOTYPES_H
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/include/DSP2833x_I2c_defines.h

@@ -0,0 +1,117 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: April 16, 2008   17:16:47 $
+//###########################################################################
+//
+// FILE:	DSP2833x_I2cExample.h
+//
+// TITLE:	2833x I2C Example Code Definitions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP2833x_I2C_DEFINES_H
+#define DSP2833x_I2C_DEFINES_H
+
+//--------------------------------------------
+// Defines
+//--------------------------------------------
+
+// Error Messages
+#define I2C_ERROR               0xFFFF
+#define I2C_ARB_LOST_ERROR      0x0001
+#define I2C_NACK_ERROR          0x0002
+#define I2C_BUS_BUSY_ERROR      0x1000
+#define I2C_STP_NOT_READY_ERROR 0x5555
+#define I2C_NO_FLAGS            0xAAAA
+#define I2C_SUCCESS             0x0000
+
+// Clear Status Flags
+#define I2C_CLR_AL_BIT          0x0001
+#define I2C_CLR_NACK_BIT        0x0002
+#define I2C_CLR_ARDY_BIT        0x0004
+#define I2C_CLR_RRDY_BIT        0x0008
+#define I2C_CLR_SCD_BIT         0x0020
+
+// Interrupt Source Messages
+#define I2C_NO_ISRC             0x0000
+#define I2C_ARB_ISRC            0x0001
+#define I2C_NACK_ISRC           0x0002
+#define I2C_ARDY_ISRC           0x0003
+#define I2C_RX_ISRC             0x0004
+#define I2C_TX_ISRC             0x0005
+#define I2C_SCD_ISRC            0x0006
+#define I2C_AAS_ISRC            0x0007
+
+// I2CMSG structure defines
+#define I2C_NO_STOP  0
+#define I2C_YES_STOP 1
+#define I2C_RECEIVE  0
+#define I2C_TRANSMIT 1
+#define I2C_MAX_BUFFER_SIZE 16
+
+// I2C Slave State defines
+#define I2C_NOTSLAVE      0
+#define I2C_ADDR_AS_SLAVE 1
+#define I2C_ST_MSG_READY  2
+
+// I2C Slave Receiver messages defines
+#define I2C_SND_MSG1 1
+#define I2C_SND_MSG2 2
+
+// I2C State defines
+#define I2C_IDLE               0
+#define I2C_SLAVE_RECEIVER     1
+#define I2C_SLAVE_TRANSMITTER  2
+#define I2C_MASTER_RECEIVER    3
+#define I2C_MASTER_TRANSMITTER 4
+
+// I2C  Message Commands for I2CMSG struct
+#define I2C_MSGSTAT_INACTIVE          0x0000
+#define I2C_MSGSTAT_SEND_WITHSTOP     0x0010
+#define I2C_MSGSTAT_WRITE_BUSY        0x0011
+#define I2C_MSGSTAT_SEND_NOSTOP       0x0020
+#define I2C_MSGSTAT_SEND_NOSTOP_BUSY  0x0021
+#define I2C_MSGSTAT_RESTART           0x0022
+#define I2C_MSGSTAT_READ_BUSY         0x0023
+
+// Generic defines
+#define I2C_TRUE  1
+#define I2C_FALSE 0
+#define I2C_YES   1
+#define I2C_NO    0
+#define I2C_DUMMY_BYTE 0
+
+
+//--------------------------------------------
+// Structures
+//--------------------------------------------
+
+// I2C Message Structure
+struct I2CMSG {
+  Uint16 MsgStatus;				// Word stating what state msg is in:
+  								//   I2C_MSGCMD_INACTIVE = do not send msg
+  								//   I2C_MSGCMD_BUSY = msg start has been sent,
+  								//                     awaiting stop
+  								//   I2C_MSGCMD_SEND_WITHSTOP = command to send
+  								//       master trans msg complete with a stop bit
+  								//   I2C_MSGCMD_SEND_NOSTOP = command to send
+  								//       master trans msg without the stop bit
+  								//   I2C_MSGCMD_RESTART = command to send a restart
+  								//       as a master receiver with a stop bit
+  Uint16 SlaveAddress;			// I2C address of slave msg is intended for
+  Uint16 NumOfBytes;			// Num of valid bytes in (or to be put in MsgBuffer)
+  Uint16 MemoryHighAddr;		// EEPROM address of data associated with msg (high byte)
+  Uint16 MemoryLowAddr;			// EEPROM address of data associated with msg (low byte)
+  Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE];	// Array holding msg data - max that
+  										    // MAX_BUFFER_SIZE can be is 16 due to
+  										    // the FIFO's
+};
+
+
+#endif  // end of DSP2833x_I2C_DEFINES_H definition
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/include/DSP28x_Project.h

@@ -0,0 +1,22 @@
+
+// TI File $Revision: /main/1 $
+// Checkin $Date: April 22, 2008   14:35:56 $
+//###########################################################################
+//
+// FILE:   DSP28x_Project.h
+//
+// TITLE:  DSP28x Project Headerfile and Examples Include File
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#ifndef DSP28x_PROJECT_H
+#define DSP28x_PROJECT_H
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+#endif  // end of DSP28x_PROJECT_H definition
+

Source/External/v120/DSP2833x_common/include/SFO.h

@@ -0,0 +1,52 @@
+//###########################################################################
+//
+// FILE:   SFO.H
+//
+// TITLE:  Scale Factor Optimizer Library Interface Header
+//
+//
+//###########################################################################
+//
+//  Ver | dd mmm yyyy | Who  | Description of changes
+// =====|=============|======|===============================================
+//  0.01| 09 Jan 2004 | TI   | New module
+//###########################################################################
+
+
+//============================================================================
+// Description:		This header provides the function call interface
+// 			for the scale factor optimizer for the 'F2833x.
+//============================================================================
+
+
+//============================================================================
+// Multiple include Guard
+//============================================================================
+#ifndef __4090522384024n8273240x3438jx43087401r34ru32r0___
+#define __4090522384024n8273240x3438jx43087401r34ru32r0___
+
+//============================================================================
+// C++ namespace
+//============================================================================
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//============================================================================
+// Function prototypes for MEP SFO
+//============================================================================
+void SFO_MepEn(int nEpwmModule);
+void SFO_MepDis(int nEpwmModule);
+
+//============================================================================
+// Multiple include Guard
+//============================================================================
+#endif // End: Multiple include Guard
+
+//============================================================================
+// C++ namespace
+//============================================================================
+#ifdef __cplusplus
+}
+#endif /* extern "C" */

Source/External/v120/DSP2833x_common/include/SFO_V5.h

@@ -0,0 +1,70 @@
+
+//###########################################################################
+//
+// FILE:   SFO_V5.H
+//
+// TITLE:  Scale Factor Optimizer Library V5 Interface Header
+//
+//
+//###########################################################################
+//
+//  Ver | dd mmm yyyy | Who  | Description of changes
+// =====|=============|======|===============================================
+//  0.01| 09 Jan 2004 | TI   | New module
+//  0.02| 22 Jun 2007 | TI   | New version (V5) with support for more channels
+//###########################################################################
+
+
+//============================================================================
+// Description:		This header provides the function call interface
+// 			        for the scale factor optimizer V5. For more
+//                  information on the SFO function usage and
+//                  limitations, see the HRPWM Reference Guide
+//                  (spru924) on the TI website.
+//============================================================================
+
+
+//============================================================================
+// Multiple include Guard
+//============================================================================
+#ifndef _SFO_V5_H
+#define _SFO_V5_H
+
+//============================================================================
+// C++ namespace
+//============================================================================
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//============================================================================
+// USER MUST UPDATE THIS CONSTANT FOR NUMBER OF HRPWM CHANNELS USED + 1
+//============================================================================
+#define PWM_CH	7	// Equal # of HRPWM channels PLUS 1
+                    // i.e. PWM_CH is 7 for 6 channels, 5 for 4 channels etc.
+
+//============================================================================
+// Function prototypes for MEP SFO
+//============================================================================
+
+int SFO_MepEn_V5(int nEpwmModule);  // MEP-Enable V5 Calibration Function
+int SFO_MepDis_V5(int nEpwmModule); // MEP-Disable V5  Calibration Function
+
+//============================================================================
+// Useful Defines when Using SFO Functions
+//============================================================================
+#define SFO_INCOMPLETE      0
+#define SFO_COMPLETE        1
+#define SFO_OUTRANGE_ERROR  2
+
+//============================================================================
+// Multiple include Guard
+//============================================================================
+#endif // End: Multiple include Guard
+
+//============================================================================
+// C++ namespace
+//============================================================================
+#ifdef __cplusplus
+}
+#endif /* extern "C" */

Source/External/v120/DSP2833x_common/source/DSP2833x_ADC_cal.asm

@@ -0,0 +1,42 @@
+;; TI File $Revision: /main/1 $
+;; Checkin $Date: July 30, 2007   10:29:23 $
+;;###########################################################################
+;;
+;; FILE:    ADC_cal.asm
+;;
+;; TITLE:   2833x Boot Rom ADC Cal routine.
+;;
+;; Functions:
+;;
+;;     _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers 
+;; Notes:
+;;
+;;###########################################################################
+;; $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+;; $Release Date: August 1, 2008 $
+;;###########################################################################
+
+    .def _ADC_cal
+	.asg "0x711C",   ADCREFSEL_LOC
+
+;-----------------------------------------------
+; _ADC_cal
+;-----------------------------------------------
+;-----------------------------------------------
+; This is the ADC cal routine.This routine is programmed into 
+; reserved memory by the factory. 0xAAAA and 0xBBBB are place- 
+; holders for calibration data.  
+;The actual values programmed by TI are device specific. 
+;
+; This function assumes that the clocks have been
+; enabled to the ADC module.
+;-----------------------------------------------
+
+    .sect ".adc_cal"
+
+_ADC_cal
+    MOVW  DP,   #ADCREFSEL_LOC >> 6
+    MOV   @28,  #0xAAAA            ; actual value may not be 0xAAAA
+    MOV   @29,  #0xBBBB             ; actual value may not be 0xBBBB
+    LRETR
+;eof ----------

Source/External/v120/DSP2833x_common/source/DSP2833x_Adc.c

@@ -0,0 +1,64 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: October 23, 2007   13:34:09 $
+//###########################################################################
+//
+// FILE:	DSP2833x_Adc.c
+//
+// TITLE:	DSP2833x ADC Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+#define ADC_usDELAY  5000L
+
+//---------------------------------------------------------------------------
+// InitAdc:
+//---------------------------------------------------------------------------
+// This function initializes ADC to a known state.
+//
+void InitAdc(void)
+{
+    extern void DSP28x_usDelay(Uint32 Count);
+
+
+    // *IMPORTANT*
+	// The ADC_cal function, which  copies the ADC calibration values from TI reserved
+	// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
+	// Boot ROM. If the boot ROM code is bypassed during the debug process, the
+	// following function MUST be called for the ADC to function according
+	// to specification. The clocks to the ADC MUST be enabled before calling this
+	// function.
+	// See the device data manual and/or the ADC Reference
+	// Manual for more information.
+
+	    EALLOW;
+		SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
+		ADC_cal();
+		EDIS;
+
+
+
+
+    // To powerup the ADC the ADCENCLK bit should be set first to enable
+    // clocks, followed by powering up the bandgap, reference circuitry, and ADC core.
+    // Before the first conversion is performed a 5ms delay must be observed
+	// after power up to give all analog circuits time to power up and settle
+
+    // Please note that for the delay function below to operate correctly the
+	// CPU_RATE define statement in the DSP2833x_Examples.h file must
+	// contain the correct CPU clock period in nanoseconds.
+
+    AdcRegs.ADCTRL3.all = 0x00E0;  // Power up bandgap/reference/ADC circuits
+    DELAY_US(ADC_usDELAY);         // Delay before converting ADC channels
+//pause_us(50L);
+}
+
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_CSMPasswords.asm

@@ -0,0 +1,67 @@
+;// TI File $Revision: /main/3 $
+;// Checkin $Date: June 26, 2007   16:41:07 $
+;//###########################################################################
+;//
+;// FILE:	DSP2833x_CSMPasswords.asm
+;//
+;// TITLE:	DSP2833x Code Security Module Passwords.
+;// 
+;// DESCRIPTION:
+;//
+;//         This file is used to specify password values to
+;//         program into the CSM password locations in Flash
+;//         at 0x33FFF8 - 0x33FFFF.
+;//
+;//         In addition, the reserved locations 0x33FF80 - 0X33fff5 are 
+;//         all programmed to 0x0000
+;//
+;//###########################################################################
+;//
+;// Original source based on D.A.
+;// 
+;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+;// $Release Date: August 1, 2008 $
+;//###########################################################################
+
+; The "csmpasswords" section contains the actual CSM passwords that will be
+; linked and programmed into to the CSM password locations (PWL) in flash.  
+; These passwords must be known in order to unlock the CSM module. 
+; All 0xFFFF's (erased) is the default value for the password locations (PWL).
+
+; It is recommended that all passwords be left as 0xFFFF during code
+; development.  Passwords of 0xFFFF do not activate code security and dummy 
+; reads of the CSM PWL registers is all that is required to unlock the CSM.  
+; When code development is complete, modify the passwords to activate the
+; code security module.
+
+      .sect "csmpasswds"
+
+      .int	0xFFFF		;PWL0 (LSW of 128-bit password)
+      .int	0xFFFF		;PWL1
+      .int	0xFFFF		;PWL2
+      .int	0xFFFF		;PWL3
+      .int	0xFFFF		;PWL4
+      .int	0xFFFF		;PWL5
+      .int	0xFFFF		;PWL6
+      .int	0xFFFF		;PWL7 (MSW of 128-bit password)
+	
+;----------------------------------------------------------------------
+
+; For code security operation, all addresses between 0x33FF80 and
+; 0X33fff5 cannot be used as program code or data.  These locations
+; must be programmed to 0x0000 when the code security password locations
+; (PWL) are programmed.  If security is not a concern, then these addresses
+; can be used for code or data.  
+
+; The section "csm_rsvd" can be used to program these locations to 0x0000.
+
+        .sect "csm_rsvd"
+        .loop (33FFF5h - 33FF80h + 1)
+              .int 0x0000
+        .endloop
+
+;//===========================================================================
+;// End of file.
+;//===========================================================================
+
+      

Source/External/v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm

@@ -0,0 +1,86 @@
+;// TI File $Revision: /main/1 $
+;// Checkin $Date: August 18, 2006   13:45:55 $
+;//###########################################################################
+;//
+;// FILE:  DSP2833x_CodeStartBranch.asm	
+;//
+;// TITLE: Branch for redirecting code execution after boot. 
+;//
+;// For these examples, code_start is the first code that is executed after
+;// exiting the boot ROM code. 
+;//
+;// The codestart section in the linker cmd file is used to physically place
+;// this code at the correct memory location.  This section should be placed 
+;// at the location the BOOT ROM will re-direct the code to.  For example, 
+;// for boot to FLASH this code will be located at 0x3f7ff6. 
+;//
+;// In addition, the example DSP2833x projects are setup such that the codegen
+;// entry point is also set to the code_start label.  This is done by linker 
+;// option -e in the project build options.  When the debugger loads the code,
+;// it will automatically set the PC to the "entry point" address indicated by
+;// the -e linker option.  In this case the debugger is simply assigning the PC, 
+;// it is not the same as a full reset of the device. 
+;// 
+;// The compiler may warn that the entry point for the project is other then
+;//  _c_init00.  _c_init00 is the C environment setup and is run before 
+;// main() is entered. The code_start code will re-direct the execution 
+;// to _c_init00 and thus there is no worry and this warning can be ignored. 
+;// 
+;//###########################################################################
+;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+;// $Release Date: August 1, 2008 $
+;//###########################################################################
+
+
+***********************************************************************
+
+WD_DISABLE	.set	1		;set to 1 to disable WD, else set to 0
+
+    .ref _c_int00
+    .global code_start
+
+***********************************************************************
+* Function: codestart section
+*
+* Description: Branch to code starting point
+***********************************************************************
+
+    .sect "codestart"
+
+code_start:
+    .if WD_DISABLE == 1
+        LB wd_disable       ;Branch to watchdog disable code
+    .else
+        LB _c_int00         ;Branch to start of boot.asm in RTS library
+    .endif
+
+;end codestart section
+
+
+***********************************************************************
+* Function: wd_disable
+*
+* Description: Disables the watchdog timer
+***********************************************************************
+    .if WD_DISABLE == 1
+
+    .text
+wd_disable:
+    SETC OBJMODE        ;Set OBJMODE for 28x object code
+    EALLOW              ;Enable EALLOW protected register access
+    MOVZ DP, #7029h>>6  ;Set data page for WDCR register
+    MOV @7029h, #0068h  ;Set WDDIS bit in WDCR to disable WD
+    EDIS                ;Disable EALLOW protected register access
+    LB _c_int00         ;Branch to start of boot.asm in RTS library
+
+    .endif
+
+;end wd_disable
+
+
+
+	.end
+	
+;//===========================================================================
+;// End of file.
+;//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_CpuTimers.c

@@ -0,0 +1,115 @@
+// TI File $Revision: /main/3 $
+// Checkin $Date: March 16, 2007   08:37:30 $
+//###########################################################################
+//
+// FILE:	DSP2833x_CpuTimers.c
+//
+// TITLE:	CPU 32-bit Timers Initialization & Support Functions.
+//
+// NOTES:   CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
+//          other realtime operating systems.
+//
+//          Do not use these two timers in your application if you ever plan
+//          on integrating DSP-BIOS or another realtime OS.
+//
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // Headerfile Include File
+#include "DSP2833x_Examples.h"   // Examples Include File
+
+struct CPUTIMER_VARS CpuTimer0;
+
+// CpuTimer 1 and CpuTimer2 are used by DSP BIOS & other RTOS. Comment out if using DSP BIOS or other RTOS.
+struct CPUTIMER_VARS CpuTimer1;
+struct CPUTIMER_VARS CpuTimer2;
+
+//---------------------------------------------------------------------------
+// InitCpuTimers:
+//---------------------------------------------------------------------------
+// This function initializes all three CPU timers to a known state.
+//
+void InitCpuTimers(void)
+{
+    // CPU Timer 0
+	// Initialize address pointers to respective timer registers:
+	CpuTimer0.RegsAddr = &CpuTimer0Regs;
+	// Initialize timer period to maximum:
+	CpuTimer0Regs.PRD.all  = 0xFFFFFFFF;
+	// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
+	CpuTimer0Regs.TPR.all  = 0;
+	CpuTimer0Regs.TPRH.all = 0;
+	// Make sure timer is stopped:
+	CpuTimer0Regs.TCR.bit.TSS = 1;
+	// Reload all counter register with period value:
+	CpuTimer0Regs.TCR.bit.TRB = 1;
+	// Reset interrupt counters:
+	CpuTimer0.InterruptCount = 0;
+
+
+// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
+// Do not use these two timers if you ever plan on integrating
+// DSP-BIOS or another realtime OS.
+//
+// Initialize address pointers to respective timer registers:
+	CpuTimer1.RegsAddr = &CpuTimer1Regs;
+	CpuTimer2.RegsAddr = &CpuTimer2Regs;
+	// Initialize timer period to maximum:
+	CpuTimer1Regs.PRD.all  = 0xFFFFFFFF;
+	CpuTimer2Regs.PRD.all  = 0xFFFFFFFF;
+    // Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
+	CpuTimer1Regs.TPR.all  = 0;
+	CpuTimer1Regs.TPRH.all = 0;
+	CpuTimer2Regs.TPR.all  = 0;
+	CpuTimer2Regs.TPRH.all = 0;
+    // Make sure timers are stopped:
+	CpuTimer1Regs.TCR.bit.TSS = 1;
+	CpuTimer2Regs.TCR.bit.TSS = 1;
+	// Reload all counter register with period value:
+	CpuTimer1Regs.TCR.bit.TRB = 1;
+	CpuTimer2Regs.TCR.bit.TRB = 1;
+	// Reset interrupt counters:
+	CpuTimer1.InterruptCount = 0;
+	CpuTimer2.InterruptCount = 0;
+
+}
+
+//---------------------------------------------------------------------------
+// ConfigCpuTimer:
+//---------------------------------------------------------------------------
+// This function initializes the selected timer to the period specified
+// by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz"
+// and the period in "uSeconds". The timer is held in the stopped state
+// after configuration.
+//
+void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
+{
+	Uint32 	temp;
+
+	// Initialize timer period:
+	Timer->CPUFreqInMHz = Freq;
+	Timer->PeriodInUSec = Period;
+	temp = (long) (Freq * Period);
+	Timer->RegsAddr->PRD.all = temp;
+
+	// Set pre-scale counter to divide by 1 (SYSCLKOUT):
+	Timer->RegsAddr->TPR.all  = 0;
+	Timer->RegsAddr->TPRH.all  = 0;
+
+	// Initialize timer control register:
+	Timer->RegsAddr->TCR.bit.TSS = 1;      // 1 = Stop timer, 0 = Start/Restart Timer
+	Timer->RegsAddr->TCR.bit.TRB = 1;      // 1 = reload timer
+	Timer->RegsAddr->TCR.bit.SOFT = 0;
+	Timer->RegsAddr->TCR.bit.FREE = 0;     // Timer Free Run Disabled
+	Timer->RegsAddr->TCR.bit.TIE = 1;      // 0 = Disable/ 1 = Enable Timer Interrupt
+
+	// Reset interrupt counter:
+	Timer->InterruptCount = 0;
+}
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_DBGIER.asm

@@ -0,0 +1,28 @@
+;// TI File $Revision: /main/1 $
+;// Checkin $Date: August 18, 2006   13:46:03 $
+;//###########################################################################
+;//
+;// FILE:  DSP2833x_DBGIER.asm
+;//
+;// TITLE: Set the DBGIER register
+;//
+;// DESCRIPTION:
+;//  
+;//  Function to set the DBGIER register (for realtime emulation).
+;//  Function Prototype: void SetDBGIER(Uint16)
+;//  Useage: SetDBGIER(value);
+;//  Input Parameters: Uint16 value = value to put in DBGIER register. 
+;//  Return Value: none          
+;//
+;//###########################################################################
+;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+;// $Release Date: August 1, 2008 $
+;//###########################################################################	
+		.global _SetDBGIER
+		.text
+		
+_SetDBGIER:
+		MOV 	*SP++,AL
+		POP 	DBGIER
+		LRETR
+		

Source/External/v120/DSP2833x_common/source/DSP2833x_DMA.c

@@ -0,0 +1,590 @@
+//###########################################################################
+//
+// FILE:	DSP2833x_DMA.c
+//
+// TITLE:	DSP2833x Device DMA Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // Headerfile Include File
+#include "DSP2833x_Examples.h"   // Examples Include File
+
+// This function initializes the DMA to a known state.
+//
+void DMAInitialize(void)
+{
+	EALLOW;
+
+	// Perform a hard reset on DMA
+	DmaRegs.DMACTRL.bit.HARDRESET = 1;
+    asm (" nop"); // one NOP required after HARDRESET
+
+	// Allow DMA to run free on emulation suspend
+	DmaRegs.DEBUGCTRL.bit.FREE = 1;
+
+	EDIS;
+}
+
+
+void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+	EALLOW;
+	// Set up SOURCE address:
+	DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;	// Point to beginning of source buffer
+	DmaRegs.CH1.SRC_ADDR_SHADOW =     (Uint32)DMA_Source;
+
+	// Set up DESTINATION address:
+	DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;	    // Point to beginning of destination buffer
+	DmaRegs.CH1.DST_ADDR_SHADOW =     (Uint32)DMA_Dest;
+
+
+	EDIS;
+}
+
+void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
+{
+	EALLOW;
+
+	// Set up BURST registers:
+	DmaRegs.CH1.BURST_SIZE.all = bsize;	                // Number of words(X-1) x-ferred in a burst
+	DmaRegs.CH1.SRC_BURST_STEP = srcbstep;			    // Increment source addr between each word x-ferred
+	DmaRegs.CH1.DST_BURST_STEP = desbstep;              // Increment dest addr between each word x-ferred
+
+
+	EDIS;
+}
+
+void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+	EALLOW;
+
+	// Set up TRANSFER registers:
+	DmaRegs.CH1.TRANSFER_SIZE = tsize;                  // Number of bursts per transfer, DMA interrupt will occur after completed transfer
+	DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep;			// TRANSFER_STEP is ignored when WRAP occurs
+	DmaRegs.CH1.DST_TRANSFER_STEP = deststep;			// TRANSFER_STEP is ignored when WRAP occurs
+
+	EDIS;
+}
+
+void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
+{
+	EALLOW;
+
+		// Set up WRAP registers:
+	DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize;				// Wrap source address after N bursts
+    DmaRegs.CH1.SRC_WRAP_STEP = srcwstep;			    // Step for source wrap
+
+	DmaRegs.CH1.DST_WRAP_SIZE = deswsize;				// Wrap destination address after N bursts
+	DmaRegs.CH1.DST_WRAP_STEP = deswstep;				// Step for destination wrap
+
+	EDIS;
+}
+
+
+void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
+{
+	EALLOW;
+
+	// Set up MODE Register:
+	DmaRegs.CH1.MODE.bit.PERINTSEL = persel;	    // Passed DMA channel as peripheral interrupt source
+	DmaRegs.CH1.MODE.bit.PERINTE = perinte;       	// Peripheral interrupt enable
+	DmaRegs.CH1.MODE.bit.ONESHOT = oneshot;       	// Oneshot enable
+	DmaRegs.CH1.MODE.bit.CONTINUOUS = cont;    		// Continous enable
+	DmaRegs.CH1.MODE.bit.SYNCE = synce;         	// Peripheral sync enable/disable
+	DmaRegs.CH1.MODE.bit.SYNCSEL = syncsel;       	// Sync effects source or destination
+	DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte;         // Enable/disable the overflow interrupt
+	DmaRegs.CH1.MODE.bit.DATASIZE = datasize;      	// 16-bit/32-bit data size transfers
+	DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode;		// Generate interrupt to CPU at beginning/end of transfer
+	DmaRegs.CH1.MODE.bit.CHINTE = chinte;        	// Channel Interrupt to CPU enable
+
+	// Clear any spurious flags:
+	DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;  		// Clear any spurious interrupt flags
+	DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1;    		// Clear any spurious sync flags
+	DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; 	     	// Clear any spurious sync error flags
+
+	// Initialize PIE vector for CPU interrupt:
+	PieCtrlRegs.PIEIER7.bit.INTx1 = 1;              // Enable DMA CH1 interrupt in PIE
+
+	EDIS;
+}
+
+// This function starts DMA Channel 1.
+void StartDMACH1(void)
+{
+	EALLOW;
+	DmaRegs.CH1.CONTROL.bit.RUN = 1;
+	EDIS;
+}
+
+void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+	EALLOW;
+
+	// Set up SOURCE address:
+	DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;	// Point to beginning of source buffer
+	DmaRegs.CH2.SRC_ADDR_SHADOW =     (Uint32)DMA_Source;
+
+	// Set up DESTINATION address:
+	DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;	    // Point to beginning of destination buffer
+	DmaRegs.CH2.DST_ADDR_SHADOW =     (Uint32)DMA_Dest;
+
+
+	EDIS;
+}
+
+void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
+{
+	EALLOW;
+
+	// Set up BURST registers:
+	DmaRegs.CH2.BURST_SIZE.all = bsize;	                // Number of words(X-1) x-ferred in a burst
+	DmaRegs.CH2.SRC_BURST_STEP = srcbstep;			    // Increment source addr between each word x-ferred
+	DmaRegs.CH2.DST_BURST_STEP = desbstep;              // Increment dest addr between each word x-ferred
+
+
+	EDIS;
+}
+
+void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+	EALLOW;
+
+		// Set up TRANSFER registers:
+	DmaRegs.CH2.TRANSFER_SIZE = tsize;                  // Number of bursts per transfer, DMA interrupt will occur after completed transfer
+	DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep;			// TRANSFER_STEP is ignored when WRAP occurs
+	DmaRegs.CH2.DST_TRANSFER_STEP = deststep;			// TRANSFER_STEP is ignored when WRAP occurs
+
+	EDIS;
+}
+
+void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
+{
+	EALLOW;
+
+		// Set up WRAP registers:
+	DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize;				// Wrap source address after N bursts
+    DmaRegs.CH2.SRC_WRAP_STEP = srcwstep;			    // Step for source wrap
+
+	DmaRegs.CH2.DST_WRAP_SIZE = deswsize;				// Wrap destination address after N bursts
+	DmaRegs.CH2.DST_WRAP_STEP = deswstep;				// Step for destination wrap
+
+	EDIS;
+}
+
+
+void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
+{
+	EALLOW;
+
+		// Set up MODE Register:
+	DmaRegs.CH2.MODE.bit.PERINTSEL = persel;	    // Passed DMA channel as peripheral interrupt source
+	DmaRegs.CH2.MODE.bit.PERINTE = perinte;       	// Peripheral interrupt enable
+	DmaRegs.CH2.MODE.bit.ONESHOT = oneshot;       	// Oneshot enable
+	DmaRegs.CH2.MODE.bit.CONTINUOUS = cont;    		// Continous enable
+	DmaRegs.CH2.MODE.bit.SYNCE = synce;         	// Peripheral sync enable/disable
+	DmaRegs.CH2.MODE.bit.SYNCSEL = syncsel;       	// Sync effects source or destination
+	DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte;         // Enable/disable the overflow interrupt
+	DmaRegs.CH2.MODE.bit.DATASIZE = datasize;      	// 16-bit/32-bit data size transfers
+	DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode;		// Generate interrupt to CPU at beginning/end of transfer
+	DmaRegs.CH2.MODE.bit.CHINTE = chinte;        	// Channel Interrupt to CPU enable
+
+	// Clear any spurious flags:
+	DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1;  		// Clear any spurious interrupt flags
+	DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1;    		// Clear any spurious sync flags
+	DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; 	     	// Clear any spurious sync error flags
+
+	// Initialize PIE vector for CPU interrupt:
+	PieCtrlRegs.PIEIER7.bit.INTx2 = 1;              // Enable DMA CH2 interrupt in PIE
+
+	EDIS;
+}
+
+
+
+// This function starts DMA Channel 2.
+void StartDMACH2(void)
+{
+	EALLOW;
+	DmaRegs.CH2.CONTROL.bit.RUN = 1;
+	EDIS;
+}
+
+
+
+void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+	EALLOW;
+
+	// Set up SOURCE address:
+	DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;	// Point to beginning of source buffer
+	DmaRegs.CH3.SRC_ADDR_SHADOW =     (Uint32)DMA_Source;
+
+	// Set up DESTINATION address:
+	DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;	    // Point to beginning of destination buffer
+	DmaRegs.CH3.DST_ADDR_SHADOW =     (Uint32)DMA_Dest;
+
+
+	EDIS;
+}
+
+void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
+{
+	EALLOW;
+
+	// Set up BURST registers:
+	DmaRegs.CH3.BURST_SIZE.all = bsize;	                // Number of words(X-1) x-ferred in a burst
+	DmaRegs.CH3.SRC_BURST_STEP = srcbstep;			    // Increment source addr between each word x-ferred
+	DmaRegs.CH3.DST_BURST_STEP = desbstep;              // Increment dest addr between each word x-ferred
+
+
+	EDIS;
+}
+
+void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+	EALLOW;
+
+		// Set up TRANSFER registers:
+	DmaRegs.CH3.TRANSFER_SIZE = tsize;                  // Number of bursts per transfer, DMA interrupt will occur after completed transfer
+	DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep;			// TRANSFER_STEP is ignored when WRAP occurs
+	DmaRegs.CH3.DST_TRANSFER_STEP = deststep;			// TRANSFER_STEP is ignored when WRAP occurs
+
+	EDIS;
+}
+
+void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
+{
+	EALLOW;
+
+			// Set up WRAP registers:
+	DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize;				// Wrap source address after N bursts
+    DmaRegs.CH3.SRC_WRAP_STEP = srcwstep;			    // Step for source wrap
+
+	DmaRegs.CH3.DST_WRAP_SIZE = deswsize;				// Wrap destination address after N bursts
+	DmaRegs.CH3.DST_WRAP_STEP = deswstep;				// Step for destination wrap
+
+	EDIS;
+}
+
+
+void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
+{
+	EALLOW;
+
+	// Set up MODE Register:
+	DmaRegs.CH3.MODE.bit.PERINTSEL = persel;	    // Passed DMA channel as peripheral interrupt source
+	DmaRegs.CH3.MODE.bit.PERINTE = perinte;       	// Peripheral interrupt enable
+	DmaRegs.CH3.MODE.bit.ONESHOT = oneshot;       	// Oneshot enable
+	DmaRegs.CH3.MODE.bit.CONTINUOUS = cont;    		// Continous enable
+	DmaRegs.CH3.MODE.bit.SYNCE = synce;         	// Peripheral sync enable/disable
+	DmaRegs.CH3.MODE.bit.SYNCSEL = syncsel;       	// Sync effects source or destination
+	DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte;         // Enable/disable the overflow interrupt
+	DmaRegs.CH3.MODE.bit.DATASIZE = datasize;      	// 16-bit/32-bit data size transfers
+	DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode;		// Generate interrupt to CPU at beginning/end of transfer
+	DmaRegs.CH3.MODE.bit.CHINTE = chinte;        	// Channel Interrupt to CPU enable
+
+	// Clear any spurious flags:
+	DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1;  		// Clear any spurious interrupt flags
+	DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1;    		// Clear any spurious sync flags
+	DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; 	     	// Clear any spurious sync error flags
+
+	// Initialize PIE vector for CPU interrupt:
+	PieCtrlRegs.PIEIER7.bit.INTx3 = 1;              // Enable DMA CH3 interrupt in PIE
+
+	EDIS;
+}
+
+// This function starts DMA Channel 3.
+void StartDMACH3(void)
+{
+	EALLOW;
+	DmaRegs.CH3.CONTROL.bit.RUN = 1;
+	EDIS;
+}
+
+
+void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+	EALLOW;
+
+	// Set up SOURCE address:
+	DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;	// Point to beginning of source buffer
+	DmaRegs.CH4.SRC_ADDR_SHADOW =     (Uint32)DMA_Source;
+
+	// Set up DESTINATION address:
+	DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;	    // Point to beginning of destination buffer
+	DmaRegs.CH4.DST_ADDR_SHADOW =     (Uint32)DMA_Dest;
+
+
+	EDIS;
+}
+
+void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
+{
+	EALLOW;
+
+	// Set up BURST registers:
+	DmaRegs.CH4.BURST_SIZE.all = bsize;	                // Number of words(X-1) x-ferred in a burst
+	DmaRegs.CH4.SRC_BURST_STEP = srcbstep;			    // Increment source addr between each word x-ferred
+	DmaRegs.CH4.DST_BURST_STEP = desbstep;              // Increment dest addr between each word x-ferred
+
+
+	EDIS;
+}
+
+void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+	EALLOW;
+
+	// Set up TRANSFER registers:
+	DmaRegs.CH4.TRANSFER_SIZE = tsize;                  // Number of bursts per transfer, DMA interrupt will occur after completed transfer
+	DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep;			// TRANSFER_STEP is ignored when WRAP occurs
+	DmaRegs.CH4.DST_TRANSFER_STEP = deststep;			// TRANSFER_STEP is ignored when WRAP occurs
+
+	EDIS;
+}
+
+void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
+{
+	EALLOW;
+
+		// Set up WRAP registers:
+	DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize;				// Wrap source address after N bursts
+    DmaRegs.CH4.SRC_WRAP_STEP = srcwstep;			    // Step for source wrap
+
+	DmaRegs.CH4.DST_WRAP_SIZE = deswsize;				// Wrap destination address after N bursts
+	DmaRegs.CH4.DST_WRAP_STEP = deswstep;				// Step for destination wrap
+
+	EDIS;
+}
+
+
+void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
+{
+	EALLOW;
+
+		// Set up MODE Register:
+	DmaRegs.CH4.MODE.bit.PERINTSEL = persel;	    // Passed DMA channel as peripheral interrupt source
+	DmaRegs.CH4.MODE.bit.PERINTE = perinte;       	// Peripheral interrupt enable
+	DmaRegs.CH4.MODE.bit.ONESHOT = oneshot;       	// Oneshot enable
+	DmaRegs.CH4.MODE.bit.CONTINUOUS = cont;    		// Continous enable
+	DmaRegs.CH4.MODE.bit.SYNCE = synce;         	// Peripheral sync enable/disable
+	DmaRegs.CH4.MODE.bit.SYNCSEL = syncsel;       	// Sync effects source or destination
+	DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte;         // Enable/disable the overflow interrupt
+	DmaRegs.CH4.MODE.bit.DATASIZE = datasize;      	// 16-bit/32-bit data size transfers
+	DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode;		// Generate interrupt to CPU at beginning/end of transfer
+	DmaRegs.CH4.MODE.bit.CHINTE = chinte;        	// Channel Interrupt to CPU enable
+
+	// Clear any spurious flags:
+	DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1;  		// Clear any spurious interrupt flags
+	DmaRegs.CH4.CONTROL.bit.SYNCCLR = 1;    		// Clear any spurious sync flags
+	DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; 	     	// Clear any spurious sync error flags
+
+	// Initialize PIE vector for CPU interrupt:
+	PieCtrlRegs.PIEIER7.bit.INTx4 = 1;              // Enable DMA CH4 interrupt in PIE
+
+	EDIS;
+}
+
+
+// This function starts DMA Channel 4.
+void StartDMACH4(void)
+{
+	EALLOW;
+	DmaRegs.CH4.CONTROL.bit.RUN = 1;
+	EDIS;
+}
+
+
+void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+	EALLOW;
+
+	// Set up SOURCE address:
+	DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;	// Point to beginning of source buffer
+	DmaRegs.CH5.SRC_ADDR_SHADOW =     (Uint32)DMA_Source;
+
+	// Set up DESTINATION address:
+	DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;	    // Point to beginning of destination buffer
+	DmaRegs.CH5.DST_ADDR_SHADOW =     (Uint32)DMA_Dest;
+
+
+	EDIS;
+}
+
+void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
+{
+	EALLOW;
+
+
+	// Set up BURST registers:
+	DmaRegs.CH5.BURST_SIZE.all = bsize;	                // Number of words(X-1) x-ferred in a burst
+	DmaRegs.CH5.SRC_BURST_STEP = srcbstep;			    // Increment source addr between each word x-ferred
+	DmaRegs.CH5.DST_BURST_STEP = desbstep;              // Increment dest addr between each word x-ferred
+
+	EDIS;
+}
+
+void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+	EALLOW;
+
+
+		// Set up TRANSFER registers:
+	DmaRegs.CH5.TRANSFER_SIZE = tsize;                  // Number of bursts per transfer, DMA interrupt will occur after completed transfer
+	DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep;			// TRANSFER_STEP is ignored when WRAP occurs
+	DmaRegs.CH5.DST_TRANSFER_STEP = deststep;			// TRANSFER_STEP is ignored when WRAP occurs
+
+	EDIS;
+}
+
+void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
+{
+	EALLOW;
+
+
+		// Set up WRAP registers:
+	DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize;				// Wrap source address after N bursts
+    DmaRegs.CH5.SRC_WRAP_STEP = srcwstep;			    // Step for source wrap
+
+	DmaRegs.CH5.DST_WRAP_SIZE = deswsize;				// Wrap destination address after N bursts
+	DmaRegs.CH5.DST_WRAP_STEP = deswstep;				// Step for destination wrap
+
+	EDIS;
+}
+
+
+void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
+{
+	EALLOW;
+
+		// Set up MODE Register:
+	DmaRegs.CH5.MODE.bit.PERINTSEL = persel;	    // Passed DMA channel as peripheral interrupt source
+	DmaRegs.CH5.MODE.bit.PERINTE = perinte;       	// Peripheral interrupt enable
+	DmaRegs.CH5.MODE.bit.ONESHOT = oneshot;       	// Oneshot enable
+	DmaRegs.CH5.MODE.bit.CONTINUOUS = cont;    		// Continous enable
+	DmaRegs.CH5.MODE.bit.SYNCE = synce;         	// Peripheral sync enable/disable
+	DmaRegs.CH5.MODE.bit.SYNCSEL = syncsel;       	// Sync effects source or destination
+	DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte;         // Enable/disable the overflow interrupt
+	DmaRegs.CH5.MODE.bit.DATASIZE = datasize;      	// 16-bit/32-bit data size transfers
+	DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode;		// Generate interrupt to CPU at beginning/end of transfer
+	DmaRegs.CH5.MODE.bit.CHINTE = chinte;        	// Channel Interrupt to CPU enable
+
+	// Clear any spurious flags:
+	DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1;  		// Clear any spurious interrupt flags
+	DmaRegs.CH5.CONTROL.bit.SYNCCLR = 1;    		// Clear any spurious sync flags
+	DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; 	     	// Clear any spurious sync error flags
+
+	// Initialize PIE vector for CPU interrupt:
+	PieCtrlRegs.PIEIER7.bit.INTx5 = 1;              // Enable DMA CH5 interrupt in PIE
+
+	EDIS;
+}
+
+// This function starts DMA Channel 5.
+void StartDMACH5(void)
+{
+	EALLOW;
+	DmaRegs.CH5.CONTROL.bit.RUN = 1;
+	EDIS;
+}
+
+
+
+void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
+{
+	EALLOW;
+
+	// Set up SOURCE address:
+	DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source;	// Point to beginning of source buffer
+	DmaRegs.CH6.SRC_ADDR_SHADOW =     (Uint32)DMA_Source;
+
+	// Set up DESTINATION address:
+	DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest;	    // Point to beginning of destination buffer
+	DmaRegs.CH6.DST_ADDR_SHADOW =     (Uint32)DMA_Dest;
+
+
+	EDIS;
+}
+
+void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep)
+{
+	EALLOW;
+
+	// Set up BURST registers:
+	DmaRegs.CH6.BURST_SIZE.all = bsize;	                // Number of words(X-1) x-ferred in a burst
+	DmaRegs.CH6.SRC_BURST_STEP = srcbstep;				    // Increment source addr between each word x-ferred
+	DmaRegs.CH6.DST_BURST_STEP = desbstep;                // Increment dest addr between each word x-ferred
+
+
+	EDIS;
+}
+
+void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
+{
+	EALLOW;
+
+	// Set up TRANSFER registers:
+	DmaRegs.CH6.TRANSFER_SIZE = tsize;                  // Number of bursts per transfer, DMA interrupt will occur after completed transfer
+	DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep;			// TRANSFER_STEP is ignored when WRAP occurs
+	DmaRegs.CH6.DST_TRANSFER_STEP = deststep;			// TRANSFER_STEP is ignored when WRAP occurs
+
+	EDIS;
+}
+
+void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
+{
+	EALLOW;
+
+		// Set up WRAP registers:
+	DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize;				// Wrap source address after N bursts
+    DmaRegs.CH6.SRC_WRAP_STEP = srcwstep;			    // Step for source wrap
+
+	DmaRegs.CH6.DST_WRAP_SIZE = deswsize;				// Wrap destination address after N bursts
+	DmaRegs.CH6.DST_WRAP_STEP = deswstep;				// Step for destination wrap
+
+	EDIS;
+}
+
+
+void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
+{
+	EALLOW;
+
+		// Set up MODE Register:
+	DmaRegs.CH6.MODE.bit.PERINTSEL = persel;	    // Passed DMA channel as peripheral interrupt source
+	DmaRegs.CH6.MODE.bit.PERINTE = perinte;       	// Peripheral interrupt enable
+	DmaRegs.CH6.MODE.bit.ONESHOT = oneshot;       	// Oneshot enable
+	DmaRegs.CH6.MODE.bit.CONTINUOUS = cont;    		// Continous enable
+	DmaRegs.CH6.MODE.bit.SYNCE = synce;         	// Peripheral sync enable/disable
+	DmaRegs.CH6.MODE.bit.SYNCSEL = syncsel;       	// Sync effects source or destination
+	DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte;         // Enable/disable the overflow interrupt
+	DmaRegs.CH6.MODE.bit.DATASIZE = datasize;      	// 16-bit/32-bit data size transfers
+	DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode;		// Generate interrupt to CPU at beginning/end of transfer
+	DmaRegs.CH6.MODE.bit.CHINTE = chinte;        	// Channel Interrupt to CPU enable
+
+	// Clear any spurious flags:
+	DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1;  		// Clear any spurious interrupt flags
+	DmaRegs.CH6.CONTROL.bit.SYNCCLR = 1;    		// Clear any spurious sync flags
+	DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; 	     	// Clear any spurious sync error flags
+
+	// Initialize PIE vector for CPU interrupt:
+	PieCtrlRegs.PIEIER7.bit.INTx6 = 1;              // Enable DMA CH6 interrupt in PIE
+
+	EDIS;
+}
+
+// This function starts DMA Channel 6.
+void StartDMACH6(void)
+{
+	EALLOW;
+	DmaRegs.CH6.CONTROL.bit.RUN = 1;
+	EDIS;
+}
+
+//===========================================================================
+// No more.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_DisInt.asm

@@ -0,0 +1,65 @@
+;// TI File $Revision: /main/1 $
+;// Checkin $Date: August 18, 2006   13:46:09 $
+;//###########################################################################
+;//
+;// FILE:  DSP2833x_DisInt.asm	
+;//
+;// TITLE: Disable and Restore INTM and DBGM
+;// 
+;// Function Prototypes:
+;//
+;//      Uint16 DSP28x_DisableInt();
+;// and  void DSP28x_RestoreInt(Uint16 Stat0);
+;//
+;// Usage:
+;//
+;//      DSP28x_DisableInt() sets both the INTM and DBGM
+;//      bits to disable maskable interrupts.  Before doing
+;//      this, the current value of ST1 is stored on the stack
+;//      so that the values can be restored later.  The value
+;//      of ST1 before the masks are set is returned to the
+;//      user in AL.  This is then used to restore their state
+;//      via the DSP28x_RestoreInt(Uint16 ST1) function.
+;//
+;// Example
+;//
+;//   Uint16 StatusReg1    
+;//   StatusReg1 = DSP28x_DisableInt();
+;//
+;//   ... May also want to disable INTM here
+;// 
+;//   ... code here
+;//
+;//   DSP28x_RestoreInt(StatusReg1);
+;//
+;//   ... Restore INTM enable
+;//
+;//###########################################################################
+;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+;// $Release Date: August 1, 2008 $
+;//###########################################################################
+
+
+
+
+   .def _DSP28x_DisableInt
+   .def _DSP28x_RestoreInt
+
+
+_DSP28x_DisableInt:
+    PUSH  ST1
+    SETC  INTM,DBGM
+    MOV   AL, *--SP
+    LRETR
+
+_DSP28x_RestoreInt:
+    MOV   *SP++, AL
+    POP   ST1
+    LRETR
+
+
+;//===========================================================================
+;// End of file.
+;//===========================================================================
+
+   

Source/External/v120/DSP2833x_common/source/DSP2833x_ECan.c

@@ -0,0 +1,404 @@
+// TI File $Revision: /main/8 $
+// Checkin $Date: June 25, 2008   15:19:07 $
+//###########################################################################
+//
+// FILE:	DSP2833x_ECan.c
+//
+// TITLE:	DSP2833x Enhanced CAN Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+
+//---------------------------------------------------------------------------
+// InitECan:
+//---------------------------------------------------------------------------
+// This function initializes the eCAN module to a known state.
+//
+void InitECan(void)
+{
+   InitECana();
+#if DSP28_ECANB
+   InitECanb();
+#endif // if DSP28_ECANB
+}
+
+void InitECana(void)		// Initialize eCAN-A module
+{
+/* Create a shadow register structure for the CAN control registers. This is
+ needed, since only 32-bit access is allowed to these registers. 16-bit access
+ to these registers could potentially corrupt the register contents or return
+ false data. This is especially true while writing to/reading from a bit
+ (or group of bits) among bits 16 - 31 */
+
+struct ECAN_REGS ECanaShadow;
+
+	EALLOW;		// EALLOW enables access to protected bits
+
+/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
+
+    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
+    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
+    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
+
+    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
+    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
+    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
+
+/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
+									// HECC mode also enables time-stamping feature
+
+	ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
+	ECanaShadow.CANMC.bit.SCB = 1;
+	ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
+
+/* Initialize all bits of 'Master Control Field' to zero */
+// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
+// all bits (including reserved bits) of MSGCTRL must be initialized to zero
+
+    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
+    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
+
+// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
+//	as a matter of precaution.
+
+	ECanaRegs.CANTA.all	= 0xFFFFFFFF;	/* Clear all TAn bits */
+
+	ECanaRegs.CANRMP.all = 0xFFFFFFFF;	/* Clear all RMPn bits */
+
+	ECanaRegs.CANGIF0.all = 0xFFFFFFFF;	/* Clear all interrupt flag bits */
+	ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
+
+
+/* Configure bit timing parameters for eCANA*/
+	ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
+	ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
+    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
+
+    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
+
+    do
+	{
+	    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
+    } while(ECanaShadow.CANES.bit.CCE != 1 );  		// Wait for CCE bit to be set..
+
+    ECanaShadow.CANBTC.all = 0;
+
+    #if (CPU_FRQ_150MHZ)                       // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
+		/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
+		   See Note at End of File */
+			ECanaShadow.CANBTC.bit.BRPREG = 4;
+			ECanaShadow.CANBTC.bit.TSEG2REG = 2;
+			ECanaShadow.CANBTC.bit.TSEG1REG = 10;
+    #endif
+	#if (CPU_FRQ_100MHZ)                       // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
+	/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
+	   See Note at End of File */
+	    ECanaShadow.CANBTC.bit.BRPREG = 4;
+		ECanaShadow.CANBTC.bit.TSEG2REG = 1;
+		ECanaShadow.CANBTC.bit.TSEG1REG = 6;
+	#endif
+
+
+    ECanaShadow.CANBTC.bit.SAM = 1;
+    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
+
+    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
+	ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
+    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
+
+    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
+
+    do
+    {
+       ECanaShadow.CANES.all = ECanaRegs.CANES.all;
+    } while(ECanaShadow.CANES.bit.CCE != 0 ); 		// Wait for CCE bit to be  cleared..
+
+/* Disable all Mailboxes  */
+ 	ECanaRegs.CANME.all = 0;		// Required before writing the MSGIDs
+
+    EDIS;
+}
+
+
+#if (DSP28_ECANB)
+void InitECanb(void)		// Initialize eCAN-B module
+{
+/* Create a shadow register structure for the CAN control registers. This is
+ needed, since only 32-bit access is allowed to these registers. 16-bit access
+ to these registers could potentially corrupt the register contents or return
+ false data. This is especially true while writing to/reading from a bit
+ (or group of bits) among bits 16 - 31 */
+
+struct ECAN_REGS ECanbShadow;
+
+   EALLOW;		// EALLOW enables access to protected bits
+
+/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
+
+    ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
+    ECanbShadow.CANTIOC.bit.TXFUNC = 1;
+    ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;
+
+    ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
+    ECanbShadow.CANRIOC.bit.RXFUNC = 1;
+    ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;
+
+/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
+
+	ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
+	ECanbShadow.CANMC.bit.SCB = 1;
+	ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
+
+/* Initialize all bits of 'Master Control Field' to zero */
+// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
+// all bits (including reserved bits) of MSGCTRL must be initialized to zero
+
+    ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
+    ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;
+
+// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
+//	as a matter of precaution.
+
+	ECanbRegs.CANTA.all	= 0xFFFFFFFF;	/* Clear all TAn bits */
+
+	ECanbRegs.CANRMP.all = 0xFFFFFFFF;	/* Clear all RMPn bits */
+
+	ECanbRegs.CANGIF0.all = 0xFFFFFFFF;	/* Clear all interrupt flag bits */
+	ECanbRegs.CANGIF1.all = 0xFFFFFFFF;
+
+
+/* Configure bit timing parameters for eCANB*/
+
+	ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
+	ECanbShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
+    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
+
+    ECanbShadow.CANES.all = ECanbRegs.CANES.all;
+
+    do
+	{
+	    ECanbShadow.CANES.all = ECanbRegs.CANES.all;
+	} while(ECanbShadow.CANES.bit.CCE != 1 ); 		// Wait for CCE bit to be  cleared..
+
+
+    ECanbShadow.CANBTC.all = 0;
+
+    #if (CPU_FRQ_150MHZ)                       // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
+	/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
+	   See Note at end of file */
+		ECanbShadow.CANBTC.bit.BRPREG = 4;
+		ECanbShadow.CANBTC.bit.TSEG2REG = 2;
+		ECanbShadow.CANBTC.bit.TSEG1REG = 10;
+	#endif
+	#if (CPU_FRQ_100MHZ)                       // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
+	/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
+	   See Note at end of file */
+	    ECanbShadow.CANBTC.bit.BRPREG = 4;
+		ECanbShadow.CANBTC.bit.TSEG2REG = 1;
+		ECanbShadow.CANBTC.bit.TSEG1REG = 6;
+	#endif
+
+    ECanbShadow.CANBTC.bit.SAM = 1;
+    ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;
+
+    ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
+	ECanbShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
+    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
+
+    ECanbShadow.CANES.all = ECanbRegs.CANES.all;
+
+    do
+    {
+        ECanbShadow.CANES.all = ECanbRegs.CANES.all;
+    } while(ECanbShadow.CANES.bit.CCE != 0 ); 		// Wait for CCE bit to be  cleared..
+
+
+/* Disable all Mailboxes  */
+ 	ECanbRegs.CANME.all = 0;		// Required before writing the MSGIDs
+
+    EDIS;
+}
+#endif // if DSP28_ECANB
+
+
+//---------------------------------------------------------------------------
+// Example: InitECanGpio:
+//---------------------------------------------------------------------------
+// This function initializes GPIO pins to function as eCAN pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.
+//
+// Caution:
+// Only one GPIO pin should be enabled for CANTXA/B operation.
+// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
+// Comment out other unwanted lines.
+
+
+void InitECanGpio(void)
+{
+   InitECanaGpio();
+#if (DSP28_ECANB)
+   InitECanbGpio();
+#endif // if DSP28_ECANB
+}
+
+void InitECanaGpio(void)
+{
+   EALLOW;
+
+/* Enable internal pull-up for the selected CAN pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+	GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;	    // Enable pull-up for GPIO30 (CANRXA)
+//	GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0;	    // Enable pull-up for GPIO18 (CANRXA)
+
+	GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;	    // Enable pull-up for GPIO31 (CANTXA)
+//	GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0;	    // Enable pull-up for GPIO19 (CANTXA)
+
+/* Set qualification for selected CAN pins to asynch only */
+// Inputs are synchronized to SYSCLKOUT by default.
+// This will select asynch (no qualification) for the selected pins.
+
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)
+//  GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3;   // Asynch qual for GPIO18 (CANRXA)
+
+
+/* Configure eCAN-A pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAN functional pins.
+
+	GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;	// Configure GPIO30 for CANRXA operation
+//  GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;	// Configure GPIO18 for CANRXA operation
+	GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;	// Configure GPIO31 for CANTXA operation
+//  GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3;	// Configure GPIO19 for CANTXA operation
+
+    EDIS;
+}
+
+#if (DSP28_ECANB)
+void InitECanbGpio(void)
+{
+   EALLOW;
+
+/* Enable internal pull-up for the selected CAN pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+	GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0;	  // Enable pull-up for GPIO8  (CANTXB)
+//  GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0;   // Enable pull-up for GPIO12 (CANTXB)
+//  GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;   // Enable pull-up for GPIO16 (CANTXB)
+//  GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0;   // Enable pull-up for GPIO20 (CANTXB)
+
+	GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0;	  // Enable pull-up for GPIO10 (CANRXB)
+//  GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0;   // Enable pull-up for GPIO13 (CANRXB)
+//  GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;   // Enable pull-up for GPIO17 (CANRXB)
+//  GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0;   // Enable pull-up for GPIO21 (CANRXB)
+
+/* Set qualification for selected CAN pins to asynch only */
+// Inputs are synchronized to SYSCLKOUT by default.
+// This will select asynch (no qualification) for the selected pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB)
+//  GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB)
+//  GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
+//  GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)
+
+/* Configure eCAN-B pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAN functional pins.
+
+	GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2;   // Configure GPIO8 for CANTXB operation
+//  GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2;  // Configure GPIO12 for CANTXB operation
+//  GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2;  // Configure GPIO16 for CANTXB operation
+//  GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3;  // Configure GPIO20 for CANTXB operation
+
+	GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2;  // Configure GPIO10 for CANRXB operation
+//  GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2;  // Configure GPIO13 for CANRXB operation
+//  GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2;  // Configure GPIO17 for CANRXB operation
+//  GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3;  // Configure GPIO21 for CANRXB operation
+
+    EDIS;
+}
+#endif // if DSP28_ECANB
+
+/*
+Note: Bit timing parameters must be chosen based on the network parameters such
+as the sampling point desired and the propagation delay of the network.
+The propagation delay is a function of length of the cable, delay introduced by
+the transceivers and opto/galvanic-isolators (if any).
+
+The parameters used in this file must be changed taking into account the above
+mentioned factors in order to arrive at the bit-timing parameters suitable
+for a network.
+
+*/

Source/External/v120/DSP2833x_common/source/DSP2833x_ECap.c

@@ -0,0 +1,255 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: March 15, 2007   16:54:36 $
+//###########################################################################
+//
+// FILE:   DSP2833x_ECap.c
+//
+// TITLE:  DSP2833x eCAP Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// InitECap:
+//---------------------------------------------------------------------------
+// This function initializes the eCAP(s) to a known state.
+//
+void InitECap(void)
+{
+   // Initialize eCAP1/2/3
+
+   //tbd...
+
+}
+
+//---------------------------------------------------------------------------
+// Example: InitECapGpio:
+//---------------------------------------------------------------------------
+// This function initializes GPIO pins to function as ECAP pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.
+//
+// Caution:
+// For each eCAP peripheral
+// Only one GPIO pin should be enabled for ECAP operation.
+// Comment out other unwanted lines.
+
+void InitECapGpio()
+{
+
+   InitECap1Gpio();
+#if (DSP28_ECAP2)
+   InitECap2Gpio();
+#endif // endif DSP28_ECAP2
+#if (DSP28_ECAP3)
+   InitECap3Gpio();
+#endif // endif DSP28_ECAP3
+#if (DSP28_ECAP4)
+   InitECap4Gpio();
+#endif // endif DSP28_ECAP4
+#if (DSP28_ECAP5)
+   InitECap5Gpio();
+#endif // endif DSP28_ECAP5
+#if (DSP28_ECAP6)
+   InitECap6Gpio();
+#endif // endif DSP28_ECAP6
+}
+
+void InitECap1Gpio(void)
+{
+   EALLOW;
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0;      // Enable pull-up on GPIO5 (CAP1)
+   GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0;     // Enable pull-up on GPIO24 (CAP1)
+// GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0;     // Enable pull-up on GPIO34 (CAP1)
+
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+// GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0;    // Synch to SYSCLKOUT GPIO5 (CAP1)
+   GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0;   // Synch to SYSCLKOUT GPIO24 (CAP1)
+// GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0;   // Synch to SYSCLKOUT GPIO34 (CAP1)
+
+/* Configure eCAP-1 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAP1 functional pins.
+// Comment out other unwanted lines.
+
+// GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3;     // Configure GPIO5 as CAP1
+   GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1;    // Configure GPIO24 as CAP1
+// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 1;    // Configure GPIO24 as CAP1
+
+    EDIS;
+}
+
+#if DSP28_ECAP2
+void InitECap2Gpio(void)
+{
+   EALLOW;
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0;     // Enable pull-up on GPIO7 (CAP2)
+// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0;    // Enable pull-up on GPIO25 (CAP2)
+// GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0;    // Enable pull-up on GPIO37 (CAP2)
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0;    // Synch to SYSCLKOUT GPIO7 (CAP2)
+// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0;   // Synch to SYSCLKOUT GPIO25 (CAP2)
+// GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0;   // Synch to SYSCLKOUT GPIO37 (CAP2)
+
+/* Configure eCAP-2 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAP2 functional pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3;    // Configure GPIO7 as CAP2
+// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1;   // Configure GPIO25 as CAP2
+// GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3;   // Configure GPIO37 as CAP2
+
+    EDIS;
+}
+#endif // endif DSP28_ECAP2
+
+#if DSP28_ECAP3
+void InitECap3Gpio(void)
+{
+   EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0;      // Enable pull-up on GPIO9 (CAP3)
+// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0;     // Enable pull-up on GPIO26 (CAP3)
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0;    // Synch to SYSCLKOUT GPIO9 (CAP3)
+// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0;   // Synch to SYSCLKOUT GPIO26 (CAP3)
+
+/* Configure eCAP-3 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAP3 functional pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 3;     // Configure GPIO9 as CAP3
+// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1;    // Configure GPIO26 as CAP3
+
+    EDIS;
+}
+#endif // endif DSP28_ECAP3
+
+
+#if DSP28_ECAP4
+void InitECap4Gpio(void)
+{
+   EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0;   // Enable pull-up on GPIO11 (CAP4)
+// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0;   // Enable pull-up on GPIO27 (CAP4)
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Synch to SYSCLKOUT GPIO11 (CAP4)
+// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Synch to SYSCLKOUT GPIO27 (CAP4)
+
+/* Configure eCAP-4 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAP4 functional pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3;  // Configure GPIO11 as CAP4
+// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1;  // Configure GPIO27 as CAP4
+
+    EDIS;
+}
+#endif // endif DSP28_ECAP4
+
+
+#if DSP28_ECAP5
+void InitECap5Gpio(void)
+{
+   EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0;     // Enable pull-up on GPIO3 (CAP5)
+// GpioCtrlRegs.GPBPUD.bit.GPIO48 = 0;    // Enable pull-up on GPIO48 (CAP5)
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0;  // Synch to SYSCLKOUT GPIO3 (CAP5)
+// GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0; // Synch to SYSCLKOUT GPIO48 (CAP5)
+
+/* Configure eCAP-5 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAP5 functional pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2;   // Configure GPIO3 as CAP5
+// GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 1;  // Configure GPIO48 as CAP5
+
+    EDIS;
+}
+#endif // endif DSP28_ECAP5
+
+
+#if DSP28_ECAP6
+void InitECap6Gpio(void)
+{
+   EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0;     // Enable pull-up on GPIO1 (CAP6)
+// GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0;    // Enable pull-up on GPIO49 (CAP6)
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0;  // Synch to SYSCLKOUT GPIO1 (CAP6)
+// GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0; // Synch to SYSCLKOUT GPIO49 (CAP6)
+
+/* Configure eCAP-5 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eCAP6 functional pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2;   // Configure GPIO1 as CAP6
+// GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 1;  // Configure GPIO49 as CAP6
+
+    EDIS;
+}
+#endif // endif DSP28_ECAP6
+
+
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_EPwm.c

@@ -0,0 +1,316 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006   13:46:19 $
+//###########################################################################
+//
+// FILE:   DSP2833x_EPwm.c
+//
+// TITLE:  DSP2833x ePWM Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// InitEPwm: 
+//---------------------------------------------------------------------------
+// This function initializes the ePWM(s) to a known state.
+//
+void InitEPwm(void)
+{
+   // Initialize ePWM1/2/3/4/5/6
+
+   //tbd...
+ 
+}
+
+//---------------------------------------------------------------------------
+// Example: InitEPwmGpio: 
+//---------------------------------------------------------------------------
+// This function initializes GPIO pins to function as ePWM pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.  
+// 
+
+void InitEPwmGpio(void)
+{
+   InitEPwm1Gpio();
+   InitEPwm2Gpio();
+   InitEPwm3Gpio();
+#if DSP28_EPWM4
+   InitEPwm4Gpio();
+#endif // endif DSP28_EPWM4
+#if DSP28_EPWM5    
+   InitEPwm5Gpio();
+#endif // endif DSP28_EPWM5
+#if DSP28_EPWM6
+   InitEPwm6Gpio();
+#endif // endif DSP28_EPWM6 
+}
+
+void InitEPwm1Gpio(void)
+{
+   EALLOW;
+   
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user. 
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0;    // Enable pull-up on GPIO0 (EPWM1A)
+    GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0;    // Enable pull-up on GPIO1 (EPWM1B)   
+   
+/* Configure ePWM-1 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be ePWM1 functional pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;   // Configure GPIO0 as EPWM1A
+    GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;   // Configure GPIO1 as EPWM1B
+   
+    EDIS;
+}
+
+void InitEPwm2Gpio(void)
+{
+   EALLOW;
+	
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user. 
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0;    // Enable pull-up on GPIO2 (EPWM2A)
+    GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0;    // Enable pull-up on GPIO3 (EPWM3B)
+
+/* Configure ePWM-2 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be ePWM2 functional pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;   // Configure GPIO2 as EPWM2A
+    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;   // Configure GPIO3 as EPWM2B
+   
+    EDIS;
+}
+
+void InitEPwm3Gpio(void)
+{
+   EALLOW;
+   
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user. 
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0;    // Enable pull-up on GPIO4 (EPWM3A)
+    GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0;    // Enable pull-up on GPIO5 (EPWM3B)
+       
+/* Configure ePWM-3 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be ePWM3 functional pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;   // Configure GPIO4 as EPWM3A
+    GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;   // Configure GPIO5 as EPWM3B
+	
+    EDIS;
+}
+
+
+#if DSP28_EPWM4
+void InitEPwm4Gpio(void)
+{
+   EALLOW;
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user. 
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0;    // Enable pull-up on GPIO6 (EPWM4A)
+    GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0;    // Enable pull-up on GPIO7 (EPWM4B)
+
+/* Configure ePWM-4 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be ePWM4 functional pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1;   // Configure GPIO6 as EPWM4A
+    GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1;   // Configure GPIO7 as EPWM4B
+	
+    EDIS;
+}
+#endif // endif DSP28_EPWM4  
+
+
+#if DSP28_EPWM5
+void InitEPwm5Gpio(void)
+{
+   EALLOW;
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user. 
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0;    // Enable pull-up on GPIO8 (EPWM5A)
+    GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0;    // Enable pull-up on GPIO9 (EPWM5B)
+
+/* Configure ePWM-5 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be ePWM5 functional pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1;   // Configure GPIO8 as EPWM5A
+    GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1;   // Configure GPIO9 as EPWM5B
+	
+    EDIS;
+}
+#endif // endif DSP28_EPWM5
+
+
+#if DSP28_EPWM6
+void InitEPwm6Gpio(void)
+{
+   EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user. 
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0;    // Enable pull-up on GPIO10 (EPWM6A)
+    GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0;    // Enable pull-up on GPIO11 (EPWM6B)
+
+/* Configure ePWM-6 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be ePWM6 functional pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1;   // Configure GPIO10 as EPWM6A
+    GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;   // Configure GPIO11 as EPWM6B
+	
+    EDIS;
+}
+#endif // endif DSP28_EPWM6  
+
+//---------------------------------------------------------------------------
+// Example: InitEPwmSyncGpio: 
+//---------------------------------------------------------------------------
+// This function initializes GPIO pins to function as ePWM Synch pins
+//
+
+void InitEPwmSyncGpio(void)
+{
+
+   EALLOW;
+
+/* Configure EPWMSYNCI  */
+   
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user. 
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0;    // Enable pull-up on GPIO6 (EPWMSYNCI)
+// GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0;   // Enable pull-up on GPIO32 (EPWMSYNCI)    
+
+/* Set qualification for selected pins to asynch only */
+// This will select synch to SYSCLKOUT for the selected pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0;   // Synch to SYSCLKOUT GPIO6 (EPWMSYNCI)
+// GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0;  // Synch to SYSCLKOUT GPIO32 (EPWMSYNCI)    
+
+/* Configure EPwmSync pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be EPwmSync functional pins.
+// Comment out other unwanted lines.   
+
+   GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 2;    // Enable pull-up on GPIO6 (EPWMSYNCI)
+// GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2;   // Enable pull-up on GPIO32 (EPWMSYNCI)    
+
+
+
+/* Configure EPWMSYNC0  */
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user. 
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+// GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0;    // Enable pull-up on GPIO6 (EPWMSYNC0)
+   GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0;   // Enable pull-up on GPIO33 (EPWMSYNC0)    
+
+// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3;    // Enable pull-up on GPIO6 (EPWMSYNC0)
+   GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2;   // Enable pull-up on GPIO33 (EPWMSYNC0)    
+
+}
+
+
+
+//---------------------------------------------------------------------------
+// Example: InitTzGpio: 
+//---------------------------------------------------------------------------
+// This function initializes GPIO pins to function as Trip Zone (TZ) pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.  
+// 
+
+void InitTzGpio(void)
+{
+   EALLOW;
+   
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user. 
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+   GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0;    // Enable pull-up on GPIO12 (TZ1)
+   GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0;    // Enable pull-up on GPIO13 (TZ2)
+   GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0;    // Enable pull-up on GPIO14 (TZ3)
+   GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0;    // Enable pull-up on GPIO15 (TZ4)
+
+   GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;    // Enable pull-up on GPIO16 (TZ5)
+// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0;    // Enable pull-up on GPIO28 (TZ5)
+
+   GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;    // Enable pull-up on GPIO17 (TZ6) 
+// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;    // Enable pull-up on GPIO29 (TZ6)  
+   
+/* Set qualification for selected pins to asynch only */
+// Inputs are synchronized to SYSCLKOUT by default.  
+// This will select asynch (no qualification) for the selected pins.
+// Comment out other unwanted lines.
+
+   GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3;  // Asynch input GPIO12 (TZ1)
+   GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3;  // Asynch input GPIO13 (TZ2)
+   GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3;  // Asynch input GPIO14 (TZ3)
+   GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3;  // Asynch input GPIO15 (TZ4)
+
+   GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3;  // Asynch input GPIO16 (TZ5)
+// GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3;  // Asynch input GPIO28 (TZ5)
+
+   GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3;  // Asynch input GPIO17 (TZ6) 
+// GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3;  // Asynch input GPIO29 (TZ6)  
+
+   
+/* Configure TZ pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be TZ functional pins.
+// Comment out other unwanted lines.   
+   GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1;  // Configure GPIO12 as TZ1
+   GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1;  // Configure GPIO13 as TZ2
+   GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1;  // Configure GPIO14 as TZ3
+   GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1;  // Configure GPIO15 as TZ4
+
+   GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3;  // Configure GPIO16 as TZ5
+// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3;  // Configure GPIO28 as TZ5
+
+   GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3;  // Configure GPIO17 as TZ6               
+// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3;  // Configure GPIO29 as TZ6  
+
+   EDIS;
+}
+
+
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_EQep.c

@@ -0,0 +1,154 @@
+// TI File $Revision: /main/3 $
+// Checkin $Date: July 27, 2007   11:55:20 $
+//###########################################################################
+//
+// FILE:   DSP2833x_EQep.c
+//
+// TITLE:  DSP2833x eQEP Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// InitEQep:
+//---------------------------------------------------------------------------
+// This function initializes the eQEP(s) to a known state.
+//
+void InitEQep(void)
+{
+   // Initialize eQEP1/2
+
+   //tbd...
+
+}
+
+//---------------------------------------------------------------------------
+// Example: InitEQepGpio:
+//---------------------------------------------------------------------------
+// This function initializes GPIO pins to function as eQEP pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.
+//
+// Caution:
+// For each eQEP peripheral
+// Only one GPIO pin should be enabled for EQEPxA operation.
+// Only one GPIO pin should be enabled for EQEPxB operation.
+// Only one GPIO pin should be enabled for EQEPxS operation.
+// Only one GPIO pin should be enabled for EQEPxI operation.
+// Comment out other unwanted lines.
+
+void InitEQepGpio()
+{
+#if DSP28_EQEP1
+   InitEQep1Gpio();
+#endif  // endif DSP28_EQEP1
+#if DSP28_EQEP2
+   InitEQep2Gpio();
+#endif // endif DSP28_EQEP2
+}
+
+#if DSP28_EQEP1
+void InitEQep1Gpio(void)
+{
+   EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0;   // Enable pull-up on GPIO20 (EQEP1A)
+    GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0;   // Enable pull-up on GPIO21 (EQEP1B)
+    GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0;   // Enable pull-up on GPIO22 (EQEP1S)
+    GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0;   // Enable pull-up on GPIO23 (EQEP1I)
+
+//    GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0;   // Enable pull-up on GPIO50 (EQEP1A)
+//    GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0;   // Enable pull-up on GPIO51 (EQEP1B)
+//    GpioCtrlRegs.GPBPUD.bit.GPIO52 = 0;   // Enable pull-up on GPIO52 (EQEP1S)
+//    GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0;   // Enable pull-up on GPIO53 (EQEP1I)
+
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0;   // Sync to SYSCLKOUT GPIO20 (EQEP1A)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0;   // Sync to SYSCLKOUT GPIO21 (EQEP1B)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0;   // Sync to SYSCLKOUT GPIO22 (EQEP1S)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0;   // Sync to SYSCLKOUT GPIO23 (EQEP1I)
+
+//    GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0;   // Sync to SYSCLKOUT GPIO50 (EQEP1A)
+//    GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0;   // Sync to SYSCLKOUT GPIO51 (EQEP1B)
+//    GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0;   // Sync to SYSCLKOUT GPIO52 (EQEP1S)
+//    GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0;   // Sync to SYSCLKOUT GPIO53 (EQEP1I)
+
+/* Configure eQEP-1 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eQEP1 functional pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1;   // Configure GPIO20 as EQEP1A
+    GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1;   // Configure GPIO21 as EQEP1B
+    GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1;   // Configure GPIO22 as EQEP1S
+    GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1;   // Configure GPIO23 as EQEP1I
+
+//    GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1;   // Configure GPIO50 as EQEP1A
+//    GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1;   // Configure GPIO51 as EQEP1B
+//    GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1;   // Configure GPIO52 as EQEP1S
+//    GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1;   // Configure GPIO53 as EQEP1I
+
+
+    EDIS;
+}
+#endif // if DSP28_EQEP1
+
+
+
+#if DSP28_EQEP2
+void InitEQep2Gpio(void)
+{
+   EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0;    // Enable pull-up on GPIO24 (EQEP2A)
+    GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0;    // Enable pull-up on GPIO25 (EQEP2B)
+    GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0;    // Enable pull-up on GPIO26 (EQEP2I)
+    GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0;    // Enable pull-up on GPIO27 (EQEP2S)
+
+// Inputs are synchronized to SYSCLKOUT by default.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0;  // Sync to SYSCLKOUT GPIO24 (EQEP2A)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0;  // Sync to SYSCLKOUT GPIO25 (EQEP2B)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0;  // Sync to SYSCLKOUT GPIO26 (EQEP2I)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0;  // Sync to SYSCLKOUT GPIO27 (EQEP2S)
+
+/* Configure eQEP-2 pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be eQEP2 functional pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2;   // Configure GPIO24 as EQEP2A
+    GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2;   // Configure GPIO25 as EQEP2B
+    GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2;   // Configure GPIO26 as EQEP2I
+    GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2;   // Configure GPIO27 as EQEP2S
+
+
+    EDIS;
+}
+#endif // endif DSP28_EQEP2
+
+
+
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_Gpio.c

@@ -0,0 +1,69 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006   13:46:25 $
+//###########################################################################
+//
+// FILE:	DSP2833x_Gpio.c
+//
+// TITLE:	DSP2833x General Purpose I/O Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// InitGpio: 
+//---------------------------------------------------------------------------
+// This function initializes the Gpio to a known (default) state.
+//
+// For more details on configuring GPIO's as peripheral functions,
+// refer to the individual peripheral examples and/or GPIO setup example. 
+void InitGpio(void)
+{
+   EALLOW;
+   
+   // Each GPIO pin can be: 
+   // a) a GPIO input/output
+   // b) peripheral function 1
+   // c) peripheral function 2
+   // d) peripheral function 3
+   // By default, all are GPIO Inputs 
+   GpioCtrlRegs.GPAMUX1.all = 0x0000;     // GPIO functionality GPIO0-GPIO15
+   GpioCtrlRegs.GPAMUX2.all = 0x0000;     // GPIO functionality GPIO16-GPIO31
+   GpioCtrlRegs.GPBMUX1.all = 0x0000;     // GPIO functionality GPIO32-GPIO39
+   GpioCtrlRegs.GPBMUX2.all = 0x0000;     // GPIO functionality GPIO48-GPIO63
+   GpioCtrlRegs.GPCMUX1.all = 0x0000;     // GPIO functionality GPIO64-GPIO79
+   GpioCtrlRegs.GPCMUX2.all = 0x0000;     // GPIO functionality GPIO80-GPIO95
+
+   GpioCtrlRegs.GPADIR.all = 0x0000;      // GPIO0-GPIO31 are inputs
+   GpioCtrlRegs.GPBDIR.all = 0x0000;      // GPIO32-GPIO63 are inputs   
+   GpioCtrlRegs.GPCDIR.all = 0x0000;      // GPI064-GPIO95 are inputs
+
+   // Each input can have different qualification
+   // a) input synchronized to SYSCLKOUT
+   // b) input qualified by a sampling window
+   // c) input sent asynchronously (valid for peripheral inputs only)
+   GpioCtrlRegs.GPAQSEL1.all = 0x0000;    // GPIO0-GPIO15 Synch to SYSCLKOUT 
+   GpioCtrlRegs.GPAQSEL2.all = 0x0000;    // GPIO16-GPIO31 Synch to SYSCLKOUT
+   GpioCtrlRegs.GPBQSEL1.all = 0x0000;    // GPIO32-GPIO39 Synch to SYSCLKOUT 
+   GpioCtrlRegs.GPBQSEL2.all = 0x0000;    // GPIO48-GPIO63 Synch to SYSCLKOUT 
+
+   // Pull-ups can be enabled or disabled. 
+   GpioCtrlRegs.GPAPUD.all = 0x0000;      // Pullup's enabled GPIO0-GPIO31
+   GpioCtrlRegs.GPBPUD.all = 0x0000;      // Pullup's enabled GPIO32-GPIO63
+   GpioCtrlRegs.GPCPUD.all = 0x0000;      // Pullup's enabled GPIO64-GPIO79
+
+   //GpioCtrlRegs.GPAPUD.all = 0xFFFF;    // Pullup's disabled GPIO0-GPIO31
+   //GpioCtrlRegs.GPBPUD.all = 0xFFFF;    // Pullup's disabled GPIO32-GPIO34
+   //GpioCtrlRegs.GPCPUD.all = 0xFFFF     // Pullup's disabled GPIO64-GPIO79
+
+   EDIS;
+
+}	
+	
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_I2C.c

@@ -0,0 +1,76 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006   13:46:27 $
+//###########################################################################
+//
+// FILE:	DSP2833x_I2C.c
+//
+// TITLE:	DSP2833x SCI Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// InitI2C: 
+//---------------------------------------------------------------------------
+// This function initializes the I2C to a known state.
+//
+void InitI2C(void)
+{
+	// Initialize I2C-A:
+
+	//tbd...
+}	
+
+//---------------------------------------------------------------------------
+// Example: InitI2CGpio: 
+//---------------------------------------------------------------------------
+// This function initializes GPIO pins to function as I2C pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.  
+// 
+// Caution: 
+// Only one GPIO pin should be enabled for SDAA operation.
+// Only one GPIO pin shoudl be enabled for SCLA operation. 
+// Comment out other unwanted lines.
+
+void InitI2CGpio()
+{
+
+   EALLOW;
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled disabled by the user.  
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+	GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0;    // Enable pull-up for GPIO32 (SDAA)
+	GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0;	   // Enable pull-up for GPIO33 (SCLA)
+
+/* Set qualification for selected pins to asynch only */
+// This will select asynch (no qualification) for the selected pins.
+// Comment out other unwanted lines.
+
+	GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3;  // Asynch input GPIO32 (SDAA)
+    GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3;  // Asynch input GPIO33 (SCLA)
+
+/* Configure SCI pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be I2C functional pins.
+// Comment out other unwanted lines.
+
+	GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1;   // Configure GPIO32 for SDAA operation
+	GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1;   // Configure GPIO33 for SCLA operation
+	
+    EDIS;
+}
+
+
+	
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_Mcbsp.c

@@ -0,0 +1,349 @@
+  // TI File $Revision: /main/16 $
+// Checkin $Date: October 3, 2007   14:50:19 $
+//###########################################################################
+//
+// FILE:	DSP2833x_McBSP.c
+//
+// TITLE:	DSP2833x Device McBSP Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate
+// generator (SRG) cycles required for the Mcbsp initialization routine.
+// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock
+// generator (CLKG) cycles required for the Mcbsp initialization routine.
+// For the functions defined in Mcbsp.c, MCBSP_INIT_DELAY and MCBSP_CLKG_DELAY
+// are based off of either a 150 MHz SYSCLKOUT (default) or a 100 MHz SYSCLKOUT.
+//
+// CPU_FRQ_100MHZ and CPU_FRQ_150MHZ are defined in DSP2833x_Examples.h
+//---------------------------------------------------------------------------
+
+#if CPU_FRQ_150MHZ                                          // For 150 MHz SYSCLKOUT(default)
+  #define CPU_SPD              150E6
+  #define MCBSP_SRG_FREQ       CPU_SPD/4                    // SRG input is LSPCLK (SYSCLKOUT/4) for examples
+#endif
+#if CPU_FRQ_100MHZ                                          // For 100 MHz SYSCLKOUT
+  #define CPU_SPD              100E6
+  #define MCBSP_SRG_FREQ       CPU_SPD/4                    // SRG input is LSPCLK (SYSCLKOUT/4) for examples
+#endif
+
+#define CLKGDV_VAL           1
+#define MCBSP_INIT_DELAY     2*(CPU_SPD/MCBSP_SRG_FREQ)                  // # of CPU cycles in 2 SRG cycles-init delay
+#define MCBSP_CLKG_DELAY     2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL))) // # of CPU cycles in 2 CLKG cycles-init delay
+//---------------------------------------------------------------------------
+// InitMcbsp:
+//---------------------------------------------------------------------------
+// This function initializes the McBSP to a known state.
+//
+
+void delay_loop(void);		// Delay function used for SRG initialization
+void clkg_delay_loop(void); // Delay function used for CLKG initialization
+
+void InitMcbsp(void)
+{
+	InitMcbspa();
+	#if DSP28_MCBSPB
+	  InitMcbspb();
+	#endif               // end DSP28_MCBSPB
+}
+
+void InitMcbspa(void)
+{
+// McBSP-A register settings
+
+    McbspaRegs.SPCR2.all=0x0000;		// Reset FS generator, sample rate generator & transmitter
+	McbspaRegs.SPCR1.all=0x0000;		// Reset Receiver, Right justify word
+	McbspaRegs.SPCR1.bit.DLB = 1;       // Enable loopback mode for test. Comment out for normal McBSP transfer mode.
+
+
+	McbspaRegs.MFFINT.all=0x0;			// Disable all interrupts
+
+    McbspaRegs.RCR2.all=0x0;			// Single-phase frame, 1 word/frame, No companding	(Receive)
+    McbspaRegs.RCR1.all=0x0;
+
+    McbspaRegs.XCR2.all=0x0;			// Single-phase frame, 1 word/frame, No companding	(Transmit)
+    McbspaRegs.XCR1.all=0x0;
+
+    McbspaRegs.PCR.bit.FSXM = 1;		// FSX generated internally, FSR derived from an external source
+	McbspaRegs.PCR.bit.CLKXM = 1;		// CLKX generated internally, CLKR derived from an external source
+
+    McbspaRegs.SRGR2.bit.CLKSM = 1;		// CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
+	McbspaRegs.SRGR2.bit.FPER = 31;		// FPER = 32 CLKG periods
+
+    McbspaRegs.SRGR1.bit.FWID = 0;              // Frame Width = 1 CLKG period
+    McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;	// CLKG frequency = LSPCLK/(CLKGDV+1)
+
+    delay_loop();                // Wait at least 2 SRG clock cycles
+
+    McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
+	clkg_delay_loop();           // Wait at least 2 CLKG cycles
+	McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
+	McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
+    McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
+
+}
+
+
+#if (DSP28_MCBSPB)
+void InitMcbspb(void)
+{
+
+// McBSP-B register settings
+
+    McbspbRegs.SPCR2.all=0x0000;		// Reset FS generator, sample rate generator & transmitter
+	McbspbRegs.SPCR1.all=0x0000;		// Reset Receiver, Right justify word
+	McbspbRegs.SPCR1.bit.DLB = 1;       // Enable loopback mode for test. Comment out for normal McBSP transfer mode.
+
+	McbspbRegs.MFFINT.all=0x0;			// Disable all interrupts
+
+    McbspbRegs.RCR2.all=0x0;			// Single-phase frame, 1 word/frame, No companding	(Receive)
+    McbspbRegs.RCR1.all=0x0;
+
+    McbspbRegs.XCR2.all=0x0;			// Single-phase frame, 1 word/frame, No companding	(Transmit)
+    McbspbRegs.XCR1.all=0x0;
+
+    McbspbRegs.SRGR2.bit.CLKSM = 1;		// CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
+	McbspbRegs.SRGR2.bit.FPER = 31;		// FPER = 32 CLKG periods
+
+    McbspbRegs.SRGR1.bit.FWID = 0;              // Frame Width = 1 CLKG period
+    McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;	// CLKG frequency = LSPCLK/(CLKGDV+1)
+
+   	McbspbRegs.PCR.bit.FSXM = 1;		// FSX generated internally, FSR derived from an external source
+	McbspbRegs.PCR.bit.CLKXM = 1;		// CLKX generated internally, CLKR derived from an external source
+    delay_loop();                // Wait at least 2 SRG clock cycles
+    McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
+	clkg_delay_loop();           // Wait at least 2 CLKG cycles
+	McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset
+	McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset
+    McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
+
+}
+
+
+#endif // end DSP28_MCBSPB
+
+// McBSP-A Data Lengths
+void InitMcbspa8bit(void)
+{
+    McbspaRegs.RCR1.bit.RWDLEN1=0;     // 8-bit word
+    McbspaRegs.XCR1.bit.XWDLEN1=0;     // 8-bit word
+}
+
+void InitMcbspa12bit(void)
+{
+    McbspaRegs.RCR1.bit.RWDLEN1=1;     // 12-bit word
+    McbspaRegs.XCR1.bit.XWDLEN1=1;     // 12-bit word
+}
+
+void InitMcbspa16bit(void)
+{
+    McbspaRegs.RCR1.bit.RWDLEN1=2;      // 16-bit word
+    McbspaRegs.XCR1.bit.XWDLEN1=2;      // 16-bit word
+}
+
+void InitMcbspa20bit(void)
+{
+    McbspaRegs.RCR1.bit.RWDLEN1=3;     // 20-bit word
+    McbspaRegs.XCR1.bit.XWDLEN1=3;     // 20-bit word
+}
+
+void InitMcbspa24bit(void)
+{
+    McbspaRegs.RCR1.bit.RWDLEN1=4;     // 24-bit word
+    McbspaRegs.XCR1.bit.XWDLEN1=4;     // 24-bit word
+}
+
+void InitMcbspa32bit(void)
+{
+    McbspaRegs.RCR1.bit.RWDLEN1=5;     // 32-bit word
+    McbspaRegs.XCR1.bit.XWDLEN1=5;     // 32-bit word
+}
+
+// McBSP-B Data Lengths
+#if (DSP28_MCBSPB)
+
+void InitMcbspb8bit(void)
+{
+    McbspbRegs.RCR1.bit.RWDLEN1=0;     // 8-bit word
+    McbspbRegs.XCR1.bit.XWDLEN1=0;     // 8-bit word
+}
+
+void InitMcbspb12bit(void)
+{
+    McbspbRegs.RCR1.bit.RWDLEN1=1;     // 12-bit word
+    McbspbRegs.XCR1.bit.XWDLEN1=1;     // 12-bit word
+}
+
+void InitMcbspb16bit(void)
+{
+    McbspbRegs.RCR1.bit.RWDLEN1=2;      // 16-bit word
+    McbspbRegs.XCR1.bit.XWDLEN1=2;      // 16-bit word
+}
+
+void InitMcbspb20bit(void)
+{
+    McbspbRegs.RCR1.bit.RWDLEN1=3;     // 20-bit word
+    McbspbRegs.XCR1.bit.XWDLEN1=3;     // 20-bit word
+}
+
+void InitMcbspb24bit(void)
+{
+    McbspbRegs.RCR1.bit.RWDLEN1=4;     // 24-bit word
+    McbspbRegs.XCR1.bit.XWDLEN1=4;     // 24-bit word
+}
+
+void InitMcbspb32bit(void)
+{
+    McbspbRegs.RCR1.bit.RWDLEN1=5;     // 32-bit word
+    McbspbRegs.XCR1.bit.XWDLEN1=5;     // 32-bit word
+}
+
+#endif //end DSP28_MCBSPB
+
+
+
+void InitMcbspGpio(void)
+{
+	InitMcbspaGpio();
+	#if DSP28_MCBSPB
+	  InitMcbspbGpio();
+	#endif               // end DSP28_MCBSPB
+}
+
+void InitMcbspaGpio(void)
+{
+	EALLOW;
+
+/* Configure McBSP-A pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be McBSP functional pins.
+// Comment out other unwanted lines.
+
+	GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2;	// GPIO20 is MDXA pin
+	GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2;	// GPIO21 is MDRA pin
+    GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2;	// GPIO22 is MCLKXA pin
+    GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2;		// GPIO7 is MCLKRA pin (Comment as needed)
+	//GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1;	// GPIO58 is MCLKRA pin (Comment as needed)
+    GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2;	// GPIO23 is MFSXA pin
+    GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2;		// GPIO5 is MFSRA pin (Comment as needed)
+	//GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1;	// GPIO59 is MFSRA pin (Comment as needed)
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+	GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0;     // Enable pull-up on GPIO20 (MDXA)
+	GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0;     // Enable pull-up on GPIO21 (MDRA)
+	GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0;     // Enable pull-up on GPIO22 (MCLKXA)
+	GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0;      // Enable pull-up on GPIO7 (MCLKRA) (Comment as needed)
+	//GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0;   // Enable pull-up on GPIO58 (MCLKRA) (Comment as needed)
+	GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0;     // Enable pull-up on GPIO23 (MFSXA)
+	GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0;      // Enable pull-up on GPIO5 (MFSRA) (Comment as needed)
+	//GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0;   // Enable pull-up on GPIO59 (MFSRA) (Comment as needed)
+
+/* Set qualification for selected input pins to asynch only */
+// This will select asynch (no qualification) for the selected pins.
+// Comment out other unwanted lines.
+
+
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3;   // Asynch input GPIO21 (MDRA)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3;   // Asynch input GPIO22 (MCLKXA)
+    GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3;    // Asynch input GPIO7 (MCLKRA) (Comment as needed)
+    //GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58(MCLKRA) (Comment as needed)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3;   // Asynch input GPIO23 (MFSXA)
+    GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3;    // Asynch input GPIO5 (MFSRA) (Comment as needed)
+    //GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (MFSRA) (Comment as needed)
+
+	EDIS;
+}
+
+#if DSP28_MCBSPB
+void InitMcbspbGpio(void)
+{
+    EALLOW;
+/* Configure McBSP-A pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be McBSP functional pins.
+// Comment out other unwanted lines.
+
+	//GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3;	// GPIO12 is MDXB pin (Comment as needed)
+	GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3;	// GPIO24 is MDXB pin (Comment as needed)
+	//GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3;	// GPIO13 is MDRB pin (Comment as needed)
+	GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3;	// GPIO25 is MDRB pin (Comment as needed)
+	//GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3;	// GPIO14 is MCLKXB pin (Comment as needed)
+	GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3;	// GPIO26 is MCLKXB pin (Comment as needed)
+	GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3;		// GPIO3 is MCLKRB pin (Comment as needed)
+	//GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1;	// GPIO60 is MCLKRB pin (Comment as needed)
+	//GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3;	// GPIO15 is MFSXB pin (Comment as needed)
+	GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3;	// GPIO27 is MFSXB pin (Comment as needed)
+	GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3;		// GPIO1 is MFSRB pin (Comment as needed)
+	//GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1;	// GPIO61 is MFSRB pin (Comment as needed)
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+	GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0;	    // Enable pull-up on GPIO24 (MDXB) (Comment as needed)
+	//GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0;	// Enable pull-up on GPIO12 (MDXB) (Comment as needed)
+	GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0;	    // Enable pull-up on GPIO25 (MDRB) (Comment as needed)
+	//GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0;	// Enable pull-up on GPIO13 (MDRB) (Comment as needed)
+	GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0;	    // Enable pull-up on GPIO26 (MCLKXB) (Comment as needed)
+	//GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0;	// Enable pull-up on GPIO14 (MCLKXB) (Comment as needed)
+	GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0;		// Enable pull-up on GPIO3 (MCLKRB) (Comment as needed)
+	//GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0;	// Enable pull-up on GPIO60 (MCLKRB) (Comment as needed)
+	GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0;	    // Enable pull-up on GPIO27 (MFSXB) (Comment as needed)
+	//GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0;	// Enable pull-up on GPIO15 (MFSXB) (Comment as needed)
+	GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0;		// Enable pull-up on GPIO1 (MFSRB) (Comment as needed)
+	//GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0;	// Enable pull-up on GPIO61 (MFSRB) (Comment as needed)
+
+
+/* Set qualification for selected input pins to asynch only */
+// This will select asynch (no qualification) for the selected pins.
+// Comment out other unwanted lines.
+     GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3;   // Asynch input GPIO25 (MDRB) (Comment as needed)
+    //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (MDRB) (Comment as needed)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3;   // Asynch input GPIO26(MCLKXB) (Comment as needed)
+    //GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (MCLKXB) (Comment as needed)
+    GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3;    // Asynch input GPIO3 (MCLKRB) (Comment as needed)
+    //GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO60 (MCLKRB) (Comment as needed)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3;   // Asynch input GPIO27 (MFSXB) (Comment as needed)
+	//GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (MFSXB) (Comment as needed)
+	GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3;    // Asynch input GPIO1 (MFSRB) (Comment as needed)
+	//GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO61 (MFSRB) (Comment as needed)
+
+
+	EDIS;
+}
+#endif                // end DSP28_MCBSPB
+
+void delay_loop(void)
+{
+    long      i;
+    for (i = 0; i < MCBSP_INIT_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles
+}
+
+void clkg_delay_loop(void)
+{
+    long      i;
+    for (i = 0; i < MCBSP_CLKG_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles
+}
+//===========================================================================
+// No more.
+//===========================================================================
+
+
+
+
+
+
+
+
+
+
+

Source/External/v120/DSP2833x_common/source/DSP2833x_MemCopy.c

@@ -0,0 +1,45 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006   13:46:33 $
+//###########################################################################
+//
+// FILE:	DSP2833x_MemCopy.c
+//
+// TITLE:	Memory Copy Utility
+//
+// ASSUMPTIONS:
+//
+//          
+//
+// DESCRIPTION:
+//
+//          This function will copy the specified memory contents from
+//          one location to another. 
+// 
+//          Uint16 *SourceAddr        Pointer to the first word to be moved
+//                                    SourceAddr < SourceEndAddr
+//          Uint16* SourceEndAddr     Pointer to the last word to be moved
+//          Uint16* DestAddr          Pointer to the first destination word
+//
+//          No checks are made for invalid memory locations or that the
+//          end address is > then the first start address.
+// 
+//          
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"
+
+void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr)
+{
+    while(SourceAddr < SourceEndAddr)
+    { 
+       *DestAddr++ = *SourceAddr++;
+    }
+    return;
+}
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_PieCtrl.c

@@ -0,0 +1,83 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006   13:46:35 $
+//###########################################################################
+//
+// FILE:	DSP2833x_PieCtrl.c
+//
+// TITLE:	DSP2833x Device PIE Control Register Initialization Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// InitPieCtrl: 
+//---------------------------------------------------------------------------
+// This function initializes the PIE control registers to a known state.
+//
+void InitPieCtrl(void)
+{
+    // Disable Interrupts at the CPU level:
+    DINT;
+
+    // Disable the PIE
+    PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
+
+	// Clear all PIEIER registers:
+	PieCtrlRegs.PIEIER1.all = 0;
+	PieCtrlRegs.PIEIER2.all = 0;
+	PieCtrlRegs.PIEIER3.all = 0;	
+	PieCtrlRegs.PIEIER4.all = 0;
+	PieCtrlRegs.PIEIER5.all = 0;
+	PieCtrlRegs.PIEIER6.all = 0;
+	PieCtrlRegs.PIEIER7.all = 0;
+	PieCtrlRegs.PIEIER8.all = 0;
+	PieCtrlRegs.PIEIER9.all = 0;
+	PieCtrlRegs.PIEIER10.all = 0;
+	PieCtrlRegs.PIEIER11.all = 0;
+	PieCtrlRegs.PIEIER12.all = 0;
+
+	// Clear all PIEIFR registers:
+	PieCtrlRegs.PIEIFR1.all = 0;
+	PieCtrlRegs.PIEIFR2.all = 0;
+	PieCtrlRegs.PIEIFR3.all = 0;	
+	PieCtrlRegs.PIEIFR4.all = 0;
+	PieCtrlRegs.PIEIFR5.all = 0;
+	PieCtrlRegs.PIEIFR6.all = 0;
+	PieCtrlRegs.PIEIFR7.all = 0;
+	PieCtrlRegs.PIEIFR8.all = 0;
+	PieCtrlRegs.PIEIFR9.all = 0;
+	PieCtrlRegs.PIEIFR10.all = 0;
+	PieCtrlRegs.PIEIFR11.all = 0;
+	PieCtrlRegs.PIEIFR12.all = 0;
+
+
+}	
+
+//---------------------------------------------------------------------------
+// EnableInterrupts: 
+//---------------------------------------------------------------------------
+// This function enables the PIE module and CPU interrupts
+//
+void EnableInterrupts()
+{
+
+    // Enable the PIE
+    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
+    		
+	// Enables PIE to drive a pulse into the CPU 
+	PieCtrlRegs.PIEACK.all = 0xFFFF;  
+
+	// Enable Interrupts at the CPU level 
+    EINT;
+
+}
+
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_PieVect.c

@@ -0,0 +1,204 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006   13:46:38 $
+//###########################################################################
+//
+// FILE:	DSP2833x_PieVect.c
+//
+// TITLE:	DSP2833x Devices PIE Vector Table Initialization Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+const struct PIE_VECT_TABLE PieVectTableInit = {
+
+      PIE_RESERVED,  // 0  Reserved space
+      PIE_RESERVED,  // 1  Reserved space 
+      PIE_RESERVED,  // 2  Reserved space 
+      PIE_RESERVED,  // 3  Reserved space 
+      PIE_RESERVED,  // 4  Reserved space 
+      PIE_RESERVED,  // 5  Reserved space 
+      PIE_RESERVED,  // 6  Reserved space 
+      PIE_RESERVED,  // 7  Reserved space 
+      PIE_RESERVED,  // 8  Reserved space 
+      PIE_RESERVED,  // 9  Reserved space 
+      PIE_RESERVED,  // 10 Reserved space 
+      PIE_RESERVED,  // 11 Reserved space 
+      PIE_RESERVED,  // 12 Reserved space 
+
+
+// Non-Peripheral Interrupts
+      INT13_ISR,     // XINT13 or CPU-Timer 1
+      INT14_ISR,     // CPU-Timer2
+      DATALOG_ISR,   // Datalogging interrupt
+      RTOSINT_ISR,   // RTOS interrupt
+      EMUINT_ISR,    // Emulation interrupt
+      NMI_ISR,       // Non-maskable interrupt
+      ILLEGAL_ISR,   // Illegal operation TRAP
+      USER1_ISR,     // User Defined trap 1
+      USER2_ISR,     // User Defined trap 2
+      USER3_ISR,     // User Defined trap 3
+      USER4_ISR,     // User Defined trap 4
+      USER5_ISR,     // User Defined trap 5
+      USER6_ISR,     // User Defined trap 6
+      USER7_ISR,     // User Defined trap 7
+      USER8_ISR,     // User Defined trap 8
+      USER9_ISR,     // User Defined trap 9
+      USER10_ISR,    // User Defined trap 10
+      USER11_ISR,    // User Defined trap 11
+      USER12_ISR,    // User Defined trap 12
+
+// Group 1 PIE Vectors
+      SEQ1INT_ISR,     // 1.1 ADC  
+      SEQ2INT_ISR,     // 1.2 ADC  
+      rsvd_ISR,        // 1.3
+      XINT1_ISR,       // 1.4     
+      XINT2_ISR,       // 1.5
+      ADCINT_ISR,      // 1.6 ADC
+      TINT0_ISR,       // 1.7 Timer 0
+      WAKEINT_ISR,     // 1.8 WD, Low Power
+
+// Group 2 PIE Vectors
+      EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone
+      EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone
+      EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone
+      EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone
+      EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone
+      EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone                        
+      rsvd_ISR,        // 2.7
+      rsvd_ISR,        // 2.8
+      
+// Group 3 PIE Vectors
+      EPWM1_INT_ISR,   // 3.1 EPWM-1 Interrupt
+      EPWM2_INT_ISR,   // 3.2 EPWM-2 Interrupt
+      EPWM3_INT_ISR,   // 3.3 EPWM-3 Interrupt
+      EPWM4_INT_ISR,   // 3.4 EPWM-4 Interrupt
+      EPWM5_INT_ISR,   // 3.5 EPWM-5 Interrupt
+      EPWM6_INT_ISR,   // 3.6 EPWM-6 Interrupt                        
+      rsvd_ISR,        // 3.7
+      rsvd_ISR,        // 3.8
+      
+// Group 4 PIE Vectors
+      ECAP1_INT_ISR,   // 4.1 ECAP-1
+      ECAP2_INT_ISR,   // 4.2 ECAP-2
+      ECAP3_INT_ISR,   // 4.3 ECAP-3
+      ECAP4_INT_ISR,   // 4.4 ECAP-4            
+      ECAP5_INT_ISR,   // 4.5 ECAP-5     
+      ECAP6_INT_ISR,   // 4.6 ECAP-6          
+      rsvd_ISR,        // 4.7      
+      rsvd_ISR,        // 4.8      
+      
+// Group 5 PIE Vectors
+      EQEP1_INT_ISR,   // 5.1 EQEP-1
+      EQEP2_INT_ISR,   // 5.2 EQEP-2
+      rsvd_ISR,        // 5.3      
+      rsvd_ISR,        // 5.4           
+      rsvd_ISR,        // 5.5      
+      rsvd_ISR,        // 5.6      
+      rsvd_ISR,        // 5.7      
+      rsvd_ISR,        // 5.8   
+
+
+// Group 6 PIE Vectors
+      SPIRXINTA_ISR,   // 6.1 SPI-A
+      SPITXINTA_ISR,   // 6.2 SPI-A
+      MRINTA_ISR,      // 6.3 McBSP-A
+      MXINTA_ISR,      // 6.4 McBSP-A
+      MRINTB_ISR,      // 6.5 McBSP-B
+      MXINTB_ISR,      // 6.6 McBSP-B
+      rsvd_ISR,        // 6.7 
+      rsvd_ISR,        // 6.8                  
+
+      
+// Group 7 PIE Vectors
+      DINTCH1_ISR,     // 7.1  DMA channel 1    
+      DINTCH2_ISR,     // 7.2  DMA channel 2
+      DINTCH3_ISR,     // 7.3  DMA channel 3      
+      DINTCH4_ISR,     // 7.4  DMA channel 4           
+      DINTCH5_ISR,     // 7.5  DMA channel 5      
+      DINTCH6_ISR,     // 7.6  DMA channel 6      
+      rsvd_ISR,        // 7.7      
+      rsvd_ISR,        // 7.8   
+
+// Group 8 PIE Vectors
+      I2CINT1A_ISR,    // 8.1  I2C    
+      I2CINT2A_ISR,    // 8.2  I2C
+      rsvd_ISR,        // 8.3      
+      rsvd_ISR,        // 8.4           
+      SCIRXINTC_ISR,   // 8.5  SCI-C
+      SCITXINTC_ISR,   // 8.6  SCI-C      
+      rsvd_ISR,        // 8.7      
+      rsvd_ISR,        // 8.8    
+      
+// Group 9 PIE Vectors     
+      SCIRXINTA_ISR,   // 9.1 SCI-A
+      SCITXINTA_ISR,   // 9.2 SCI-A
+      SCIRXINTB_ISR,   // 9.3 SCI-B
+      SCITXINTB_ISR,   // 9.4 SCI-B
+      ECAN0INTA_ISR,   // 9.5 eCAN-A
+      ECAN1INTA_ISR,   // 9.6 eCAN-A
+      ECAN0INTB_ISR,   // 9.7 eCAN-B
+      ECAN1INTB_ISR,   // 9.8 eCAN-B
+      
+// Group 10 PIE Vectors
+      rsvd_ISR,        // 10.1      
+      rsvd_ISR,        // 10.2
+      rsvd_ISR,        // 10.3      
+      rsvd_ISR,        // 10.4           
+      rsvd_ISR,        // 10.5      
+      rsvd_ISR,        // 10.6      
+      rsvd_ISR,        // 10.7      
+      rsvd_ISR,        // 10.8    
+            
+// Group 11 PIE Vectors
+      rsvd_ISR,        // 11.1      
+      rsvd_ISR,        // 11.2
+      rsvd_ISR,        // 11.3      
+      rsvd_ISR,        // 11.4           
+      rsvd_ISR,        // 11.5      
+      rsvd_ISR,        // 11.6      
+      rsvd_ISR,        // 11.7      
+      rsvd_ISR,        // 11.8
+        
+// Group 12 PIE Vectors
+      XINT3_ISR,       // 12.1      
+      XINT4_ISR,       // 12.2
+      XINT5_ISR,       // 12.3      
+      XINT6_ISR,       // 12.4           
+      XINT7_ISR,       // 12.5      
+      rsvd_ISR,        // 12.6      
+      LVF_ISR,         // 12.7      
+      LUF_ISR,         // 12.8   
+};
+
+
+//---------------------------------------------------------------------------
+// InitPieVectTable: 
+//---------------------------------------------------------------------------
+// This function initializes the PIE vector table to a known state.
+// This function must be executed after boot time.
+//
+
+void InitPieVectTable(void)
+{
+	int16	i;
+	Uint32 *Source = (void *) &PieVectTableInit;
+	Uint32 *Dest = (void *) &PieVectTable;
+		
+	EALLOW;	
+	for(i=0; i < 128; i++)
+		*Dest++ = *Source++;	
+	EDIS;
+
+	// Enable the PIE Vector Table
+	PieCtrlRegs.PIECTRL.bit.ENPIE = 1;	
+			
+}
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_SWPrioritizedPieVect.c

@@ -0,0 +1,511 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: April 4, 2007   14:25:31 $
+//###########################################################################
+//
+// FILE:   DSP2833x_SWPiroritizedPieVect.c
+//
+// TITLE:  DSP2833x Devices SW Prioritized PIE Vector Table Initialization.
+//
+//###########################################################################
+// 
+// Original Source by A.T.
+//
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+#include "DSP2833x_SWPrioritizedIsrLevels.h" 
+
+const struct PIE_VECT_TABLE PieVectTableInit = {
+
+      PIE_RESERVED,       // Reserved space
+      PIE_RESERVED,       // reserved
+      PIE_RESERVED,       // reserved
+      PIE_RESERVED,       // reserved
+      PIE_RESERVED,       // reserved
+      PIE_RESERVED,       // reserved
+      PIE_RESERVED,       // reserved
+      PIE_RESERVED,       // reserved
+      PIE_RESERVED,       // reserved
+      PIE_RESERVED,       // reserved
+      PIE_RESERVED,       // reserved
+      PIE_RESERVED,       // reserved
+      PIE_RESERVED,       // reserved
+
+// Non-Peripheral Interrupts:
+      #if (INT13PL != 0)
+      INT13_ISR,    // XINT13
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+      
+      #if (INT14PL != 0)
+      INT14_ISR,     // CPU-Timer2
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+      
+      #if (INT15PL != 0)
+      DATALOG_ISR,   // Datalogging interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (INT16PL != 0)
+      RTOSINT_ISR,   // RTOS interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      rsvd_ISR,      // reserved interrupt
+      NMI_ISR,       // Non-maskable interrupt
+      ILLEGAL_ISR,   // Illegal operation TRAP
+      USER1_ISR,     // User Defined trap 1
+      USER2_ISR,     // User Defined trap 2
+      USER3_ISR,     // User Defined trap 3
+      USER4_ISR,     // User Defined trap 4
+      USER5_ISR,     // User Defined trap 5
+      USER6_ISR,     // User Defined trap 6
+      USER7_ISR,     // User Defined trap 7
+      USER8_ISR,     // User Defined trap 8
+      USER9_ISR,     // User Defined trap 9
+      USER10_ISR,    // User Defined trap 10
+      USER11_ISR,    // User Defined trap 11
+      USER12_ISR,    // User Defined trap 12
+
+// Group 1 PIE Vectors:
+      #if (G11PL != 0)
+      SEQ1INT_ISR,   // ADC
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G12PL != 0)
+      SEQ2INT_ISR,   // ADC 
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      rsvd_ISR,
+
+      #if (G14PL != 0)
+      XINT1_ISR,     // External
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G15PL != 0)
+      XINT2_ISR,     // External
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G16PL != 0)
+      ADCINT_ISR,    // ADC
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G17PL != 0)
+      TINT0_ISR,     // Timer 0
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G18PL != 0)
+      WAKEINT_ISR,   // WD & Low Power
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+// Group 2 PIE Vectors:
+      #if (G21PL != 0)
+      EPWM1_TZINT_ISR,   // ePWM1 Trip Zone
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G22PL != 0)
+      EPWM2_TZINT_ISR,   // ePWM2 Trip Zone
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G23PL != 0)
+      EPWM3_TZINT_ISR,   // ePWM3 Trip Zone
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G24PL != 0)
+      EPWM4_TZINT_ISR,   // ePWM4 Trip Zone
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G25PL != 0)
+      EPWM5_TZINT_ISR,   // ePWM5 Trip Zone
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G26PL != 0)
+      EPWM6_TZINT_ISR,   // ePWM6 Trip Zone
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      rsvd_ISR,
+      rsvd_ISR,
+      
+// Group 3 PIE Vectors:
+      #if (G31PL != 0)
+      EPWM1_INT_ISR,     // ePWM1 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G32PL != 0)
+      EPWM2_INT_ISR,     // ePWM2 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G33PL != 0)
+      EPWM3_INT_ISR,     // ePWM3 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G34PL != 0)
+      EPWM4_INT_ISR,     // ePWM4 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G35PL != 0)
+      EPWM5_INT_ISR,     // ePWM5 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G36PL != 0)
+      EPWM6_INT_ISR,     // ePWM6 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      rsvd_ISR,
+      rsvd_ISR,
+      
+// Group 4 PIE Vectors:
+      #if (G41PL != 0)
+      ECAP1_INT_ISR,     // eCAP1 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G42PL != 0)
+      ECAP2_INT_ISR,     // eCAP2 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G43PL != 0)
+      ECAP3_INT_ISR,     // eCAP3 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G44PL != 0)
+      ECAP4_INT_ISR,     // eCAP4 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G45PL != 0)
+      ECAP5_INT_ISR,     // eCAP5 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G46PL != 0)
+      ECAP6_INT_ISR,     // eCAP6 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      rsvd_ISR,
+      rsvd_ISR,          
+     
+// Group 5 PIE Vectors:
+      #if (G51PL != 0)
+      EQEP1_INT_ISR,     // eQEP1 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G52PL != 0)
+      EQEP2_INT_ISR,     // eQEP2 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      rsvd_ISR,
+      rsvd_ISR,
+      rsvd_ISR,
+      rsvd_ISR,
+      rsvd_ISR,
+      rsvd_ISR,            
+
+// Group 6 PIE Vectors:
+      #if (G61PL != 0)
+      SPIRXINTA_ISR,  // SPI-A
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G62PL != 0)
+      SPITXINTA_ISR,  // SPI-A
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G63PL != 0)
+      MRINTB_ISR,     // McBSP-B
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G64PL != 0)
+      MXINTB_ISR,     // McBSP-B
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G65PL != 0)
+      MRINTA_ISR,     // McBSP-A
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G66PL != 0)
+      MXINTA_ISR,     // McBSP-A
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      rsvd_ISR,
+	  rsvd_ISR,
+      
+// Group 7 PIE Vectors:
+      #if (G71PL != 0)
+      DINTCH1_ISR,     // DMA-Channel 1 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G72PL != 0)
+      DINTCH2_ISR,     // DMA-Channel 2 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G73PL != 0)
+      DINTCH3_ISR,     // DMA-Channel 3 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G74PL != 0)
+      DINTCH4_ISR,     // DMA-Channel 4 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G75PL != 0)
+      DINTCH5_ISR,     // DMA-Channel 5 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G76PL != 0)
+      DINTCH6_ISR,     // DMA-Channel 6 Interrupt
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      rsvd_ISR,
+      rsvd_ISR,         
+
+// Group 8 PIE Vectors:
+      #if (G81PL != 0)
+      I2CINT1A_ISR,    // I2C-A
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G82PL != 0)
+      I2CINT2A_ISR,    // I2C-A
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+           
+      rsvd_ISR,     
+      rsvd_ISR,  
+         
+      #if (G85PL != 0)
+      SCIRXINTC_ISR,    // SCI-C
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G86PL != 0)
+      SCITXINTC_ISR,    // SCI-C
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+          
+      rsvd_ISR,     
+      rsvd_ISR,     
+      
+// Group 9 PIE Vectors:
+      #if (G91PL != 0)
+      SCIRXINTA_ISR,    // SCI-A
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G92PL != 0)
+      SCITXINTA_ISR,    // SCI-A
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G93PL != 0)
+      SCIRXINTB_ISR,    // SCI-B
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G94PL != 0)
+      SCITXINTB_ISR,    // SCI-B
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G95PL != 0)
+      ECAN0INTA_ISR,    // eCAN-A
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G96PL != 0)
+      ECAN1INTA_ISR,   // eCAN-A
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G97PL != 0)
+      ECAN0INTB_ISR,   // eCAN-B
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G98PL != 0)
+      ECAN1INTB_ISR,   // eCAN-B
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+      
+// Group 10 PIE Vectors
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+            
+// Group 11 PIE Vectors
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+      rsvd_ISR,     
+
+// Group 12 PIE Vectors
+      #if (G121PL != 0)
+      XINT3_ISR,       // External interrupt 3
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G122PL != 0)
+      XINT4_ISR,       // External interrupt 4
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G123PL != 0)
+      XINT5_ISR,       // External interrupt 5
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G124PL != 0)
+      XINT6_ISR,       // External interrupt 6
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G125PL != 0)
+      XINT7_ISR,       // External interrupt 7
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      rsvd_ISR,
+
+      #if (G127PL != 0)
+      LVF_ISR,         // Latched overflow flag  
+      #else
+      INT_NOTUSED_ISR,
+      #endif
+
+      #if (G128PL != 0)
+      LUF_ISR,         // Latched underflow flag
+      #else
+      INT_NOTUSED_ISR,
+      #endif   
+};
+
+//---------------------------------------------------------------------------
+// InitPieVectTable: 
+//---------------------------------------------------------------------------
+// This function initializes the PIE vector table to a known state.
+// This function must be executed after boot time.
+//
+
+void InitPieVectTable(void)
+{
+   int16 i;
+   Uint32 *Source = (void *) &PieVectTableInit;
+   Uint32 *Dest = (void *) &PieVectTable;
+
+   EALLOW;
+   for(i=0; i < 128; i++) {
+      *Dest++ = *Source++;
+   }
+   EDIS;
+}
+
+//===========================================================================
+// No more.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_Sci.c

@@ -0,0 +1,168 @@
+// TI File $Revision: /main/2 $
+// Checkin $Date: March 1, 2007   16:06:07 $
+//###########################################################################
+//
+// FILE:	DSP2833x_Sci.c
+//
+// TITLE:	DSP2833x SCI Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// InitSci: 
+//---------------------------------------------------------------------------
+// This function initializes the SCI(s) to a known state.
+//
+void InitSci(void)
+{
+	// Initialize SCI-A:
+
+	//tbd...
+ 	
+
+	// Initialize SCI-B:
+
+	//tbd...
+  
+      // Initialize SCI-C:
+
+      //tbd...
+}	
+
+//---------------------------------------------------------------------------
+// Example: InitSciGpio: 
+//---------------------------------------------------------------------------
+// This function initializes GPIO pins to function as SCI pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.  
+// 
+// Caution: 
+// Only one GPIO pin should be enabled for SCITXDA/B operation.
+// Only one GPIO pin shoudl be enabled for SCIRXDA/B operation. 
+// Comment out other unwanted lines.
+
+void InitSciGpio()
+{
+   InitSciaGpio();
+#if DSP28_SCIB   
+   InitScibGpio();
+#endif // if DSP28_SCIB  
+#if DSP28_SCIC
+   InitScicGpio();
+#endif // if DSP28_SCIC
+}
+
+void InitSciaGpio()
+{
+   EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled disabled by the user.  
+// This will enable the pullups for the specified pins.
+
+	GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0;    // Enable pull-up for GPIO28 (SCIRXDA)
+	GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;	   // Enable pull-up for GPIO29 (SCITXDA)
+
+/* Set qualification for selected pins to asynch only */
+// Inputs are synchronized to SYSCLKOUT by default.  
+// This will select asynch (no qualification) for the selected pins.
+
+	GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3;  // Asynch input GPIO28 (SCIRXDA)
+
+/* Configure SCI-A pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be SCI functional pins.
+
+	GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1;   // Configure GPIO28 for SCIRXDA operation
+	GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1;   // Configure GPIO29 for SCITXDA operation
+	
+    EDIS;
+}
+
+#if DSP28_SCIB 
+void InitScibGpio()
+{
+   EALLOW;
+	
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled disabled by the user.  
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+//  GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0;     // Enable pull-up for GPIO9  (SCITXDB)
+//  GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0;    // Enable pull-up for GPIO14 (SCITXDB)
+	GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0;	   // Enable pull-up for GPIO18 (SCITXDB)
+//  GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0;    // Enable pull-up for GPIO22 (SCITXDB)
+
+	
+//  GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0;    // Enable pull-up for GPIO11 (SCIRXDB)
+//  GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0;    // Enable pull-up for GPIO15 (SCIRXDB)
+    GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0;	   // Enable pull-up for GPIO19 (SCIRXDB)
+//  GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0;    // Enable pull-up for GPIO23 (SCIRXDB)
+
+/* Set qualification for selected pins to asynch only */
+// This will select asynch (no qualification) for the selected pins.
+// Comment out other unwanted lines.
+
+//  GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3;  // Asynch input GPIO11 (SCIRXDB)
+//  GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3;  // Asynch input GPIO15 (SCIRXDB)
+	GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3;  // Asynch input GPIO19 (SCIRXDB)
+//  GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3;  // Asynch input GPIO23 (SCIRXDB)
+
+/* Configure SCI-B pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be SCI functional pins.
+// Comment out other unwanted lines.
+
+//  GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2;    // Configure GPIO9 for SCITXDB operation
+//  GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2;   // Configure GPIO14 for SCITXDB operation
+	GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2;   // Configure GPIO18 for SCITXDB operation
+//  GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3;   // Configure GPIO22 for SCITXDB operation
+	
+//  GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2;   // Configure GPIO11 for SCIRXDB operation
+//  GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2;   // Configure GPIO15 for SCIRXDB operation
+    GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2;   // Configure GPIO19 for SCIRXDB operation
+//  GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3;   // Configure GPIO23 for SCIRXDB operation
+	
+    EDIS;
+}
+#endif // if DSP28_SCIB 
+
+#if DSP28_SCIC
+void InitScicGpio()
+{
+   EALLOW;
+
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled disabled by the user.  
+// This will enable the pullups for the specified pins.
+
+	GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0;    // Enable pull-up for GPIO62 (SCIRXDC)
+	GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0;	   // Enable pull-up for GPIO63 (SCITXDC)
+
+/* Set qualification for selected pins to asynch only */
+// Inputs are synchronized to SYSCLKOUT by default.  
+// This will select asynch (no qualification) for the selected pins.
+
+	GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3;  // Asynch input GPIO62 (SCIRXDC)
+
+/* Configure SCI-C pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be SCI functional pins.
+
+	GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1;   // Configure GPIO62 for SCIRXDC operation
+	GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1;   // Configure GPIO63 for SCITXDC operation
+	
+    EDIS;
+}
+#endif // if DSP28_SCIC 
+
+	
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_Spi.c

@@ -0,0 +1,107 @@
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 18, 2006   13:46:44 $
+//###########################################################################
+//
+// FILE:   DSP2833x_Spi.c
+//
+// TITLE:  DSP2833x SPI Initialization & Support Functions.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// InitSPI: 
+//---------------------------------------------------------------------------
+// This function initializes the SPI(s) to a known state.
+//
+void InitSpi(void)
+{
+   // Initialize SPI-A/B/C/D
+
+   //tbd...
+ 
+}
+
+//---------------------------------------------------------------------------
+// Example: InitSpiGpio: 
+//---------------------------------------------------------------------------
+// This function initializes GPIO pins to function as SPI pins
+//
+// Each GPIO pin can be configured as a GPIO pin or up to 3 different
+// peripheral functional pins. By default all pins come up as GPIO
+// inputs after reset.  
+// 
+// Caution: 
+// For each SPI peripheral
+// Only one GPIO pin should be enabled for SPISOMO operation.
+// Only one GPIO pin should be enabled for SPISOMI operation. 
+// Only one GPIO pin should be enabled for SPICLKA operation. 
+// Only one GPIO pin should be enabled for SPISTEA operation. 
+// Comment out other unwanted lines.
+
+void InitSpiGpio()
+{
+
+   InitSpiaGpio();
+}
+
+void InitSpiaGpio()
+{
+
+   EALLOW;
+/* Enable internal pull-up for the selected pins */
+// Pull-ups can be enabled or disabled by the user.  
+// This will enable the pullups for the specified pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;   // Enable pull-up on GPIO16 (SPISIMOA)
+    GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;   // Enable pull-up on GPIO17 (SPISOMIA)
+    GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0;   // Enable pull-up on GPIO18 (SPICLKA)
+    GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0;   // Enable pull-up on GPIO19 (SPISTEA)
+
+
+//    GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0;   // Enable pull-up on GPIO54 (SPISIMOA)
+//    GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0;   // Enable pull-up on GPIO55 (SPISOMIA)
+//    GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0;   // Enable pull-up on GPIO56 (SPICLKA)
+//    GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0;   // Enable pull-up on GPIO57 (SPISTEA)
+
+/* Set qualification for selected pins to asynch only */
+// This will select asynch (no qualification) for the selected pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA)
+    GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA)
+
+//    GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA)
+//    GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA)
+//    GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA)
+//    GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA)
+
+    
+/* Configure SPI-A pins using GPIO regs*/
+// This specifies which of the possible GPIO pins will be SPI functional pins.
+// Comment out other unwanted lines.
+
+    GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
+    GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
+    GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
+    GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA
+
+//    GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA
+//    GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA
+//    GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA
+//    GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA
+
+    EDIS;
+}
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_SysCtrl.c

@@ -0,0 +1,415 @@
+// TI File $Revision: /main/7 $
+// Checkin $Date: September 20, 2007   13:30:31 $
+//###########################################################################
+//
+// FILE:   DSP2833x_SysCtrl.c
+//
+// TITLE:  DSP2833x Device System Control Initialization & Support Functions.
+//
+// DESCRIPTION:
+//
+//         Example initialization of system resources.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+
+#include "DSP2833x_Device.h"     // Headerfile Include File
+#include "DSP2833x_Examples.h"   // Examples Include File
+
+#include "RS485.h"
+#include "message.h"
+
+// Functions that will be run from RAM need to be assigned to
+// a different section.  This section will then be mapped to a load and
+// run address using the linker cmd file.
+
+#pragma CODE_SECTION(InitFlash, "ramfuncs");
+
+//---------------------------------------------------------------------------
+// InitSysCtrl:
+//---------------------------------------------------------------------------
+// This function initializes the System Control registers to a known state.
+// - Disables the watchdog
+// - Set the PLLCR for proper SYSCLKOUT frequency
+// - Set the pre-scaler for the high and low frequency peripheral clocks
+// - Enable the clocks to the peripherals
+
+long SYSCLKOUT, LSPCLK, HSPCLK;
+
+void InitSysCtrl(void)
+{
+
+   // Disable the watchdog
+   DisableDog();
+
+   // Initialize the PLL control: PLLCR and DIVSEL
+   // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
+   InitPll(DSP28_PLLCR,DSP28_DIVSEL);
+
+   // Initialize the peripheral clocks
+   InitPeripheralClocks();
+}
+
+
+//---------------------------------------------------------------------------
+// Example: InitFlash:
+//---------------------------------------------------------------------------
+// This function initializes the Flash Control registers
+
+//                   CAUTION
+// This function MUST be executed out of RAM. Executing it
+// out of OTP/Flash will yield unpredictable results
+
+void InitFlash(void)
+{
+   EALLOW;
+   //Enable Flash Pipeline mode to improve performance
+   //of code executed from Flash.
+   FlashRegs.FOPT.bit.ENPIPE = 1;
+
+   //                CAUTION
+   //Minimum waitstates required for the flash operating
+   //at a given CPU rate must be characterized by TI.
+   //Refer to the datasheet for the latest information.
+#if CPU_FRQ_150MHZ
+   //Set the Paged Waitstate for the Flash
+   FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;
+
+   //Set the Random Waitstate for the Flash
+   FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
+
+   //Set the Waitstate for the OTP
+   FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;
+#endif
+
+#if CPU_FRQ_100MHZ
+   //Set the Paged Waitstate for the Flash
+   FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
+
+   //Set the Random Waitstate for the Flash
+   FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
+
+   //Set the Waitstate for the OTP
+   FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
+#endif
+   //                CAUTION
+   //ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
+   FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
+   FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
+   EDIS;
+
+   //Force a pipeline flush to ensure that the write to
+   //the last register configured occurs before returning.
+
+   asm(" RPT #7 || NOP");
+}
+
+
+//---------------------------------------------------------------------------
+// Example: ServiceDog:
+//---------------------------------------------------------------------------
+// This function resets the watchdog timer.
+// Enable this function for using ServiceDog in the application
+
+void ServiceDog(void)
+{
+	if(SysCtrlRegs.PLLCR.bit.DIV == DSP28_PLLCR)
+	if(SysCtrlRegs.PLLSTS.bit.DIVSEL == DSP28_DIVSEL)
+	{
+	    EALLOW;
+	    SysCtrlRegs.WDKEY = 0x0055;
+	    SysCtrlRegs.WDKEY = 0x00AA;
+	    EDIS;
+		return;
+}	}
+
+
+//---------------------------------------------------------------------------
+// Example: DisableDog:
+//---------------------------------------------------------------------------
+// This function disables the watchdog timer.
+
+void DisableDog(void)
+{
+    EALLOW;
+    SysCtrlRegs.WDCR= 0x0068;
+    EDIS;
+}
+
+//---------------------------------------------------------------------------
+// Example: InitPll:
+//---------------------------------------------------------------------------
+// This function initializes the PLLCR register.
+
+void InitPll(Uint16 divval, Uint16 divsel)
+{
+  long clkVal;
+
+   // Make sure the PLL is not running in limp mode
+   if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
+   {
+      // Missing external clock has been detected
+      // Replace this line with a call to an appropriate
+      // SystemShutdown(); function.
+      asm("        ESTOP0");
+   }
+
+   // DIVSEL MUST be 0 before PLLCR can be changed from
+   // 0x0000. It is set to 0 by an external reset XRSn
+   // This puts us in 1/4
+   if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
+   {
+       EALLOW;
+       SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
+       EDIS;
+   }
+
+   // Change the PLLCR
+//   if (SysCtrlRegs.PLLCR.bit.DIV != val)
+   {
+
+      EALLOW;
+      // Before setting PLLCR turn off missing clock detect logic
+      SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
+      SysCtrlRegs.PLLCR.bit.DIV = divval;
+      EDIS;
+
+	clkVal = (divval)?divval:1;
+	clkVal = XCLKIN * clkVal;
+
+      // Optional: Wait for PLL to lock.
+      // During this time the CPU will switch to OSCCLK/2 until
+      // the PLL is stable.  Once the PLL is stable the CPU will
+      // switch to the new PLL value.
+      //
+      // This time-to-lock is monitored by a PLL lock counter.
+      //
+      // Code is not required to sit and wait for the PLL to lock.
+      // However, if the code does anything that is timing critical,
+      // and requires the correct clock be locked, then it is best to
+      // wait until this switching has completed.
+
+      // Wait for the PLL lock bit to be set.
+
+      // The watchdog should be disabled before this loop, or fed within
+      // the loop via ServiceDog().
+
+	  // Uncomment to disable the watchdog
+      DisableDog();
+
+      while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
+      {
+	      // Uncomment to service the watchdog
+          // ServiceDog();
+      }
+
+      EALLOW;
+      SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
+      EDIS;
+    }
+
+    // If switching to 1/2
+	if((divsel == 1)||(divsel == 2))
+	{
+		EALLOW;
+	    SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
+	    EDIS;
+	}
+
+	if(divsel == 0) clkVal /= 4;
+	if(divsel == 1) clkVal /= 4;
+	if(divsel == 2) clkVal /= 2;
+ 
+ 	// If switching to 1/1
+	// * First go to 1/2 and let the power settle
+	//   The time required will depend on the system, this is only an example
+	// * Then switch to 1/1
+
+	if((divval == 0) && (divsel == 3))
+	{
+		EALLOW;
+	    SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
+	    DELAY_US(50L);
+//		pause_us(50L);
+	    SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
+	    EDIS;
+	}
+
+	SYSCLKOUT = clkVal;
+}
+
+//--------------------------------------------------------------------------
+// Example: InitPeripheralClocks:
+//---------------------------------------------------------------------------
+// This function initializes the clocks to the peripheral modules.
+// First the high and low clock prescalers are set
+// Second the clocks are enabled to each peripheral.
+// To reduce power, leave clocks to unused peripherals disabled
+//
+// Note: If a peripherals clock is not enabled then you cannot
+// read or write to the registers for that peripheral
+
+void InitPeripheralClocks(void)
+{
+  long Val;
+
+   EALLOW;
+
+// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
+
+#if CLKMULT == 0
+   SysCtrlRegs.HISPCP.all = 0x0000;
+#endif   
+#if CLKMULT == 1
+   SysCtrlRegs.HISPCP.all = 0x0000;
+#endif   
+#if CLKMULT == 2
+   SysCtrlRegs.HISPCP.all = 0x0001;
+#endif   
+#if CLKMULT == 3
+   SysCtrlRegs.HISPCP.all = 0x0002;
+#endif   
+#if CLKMULT == 4
+   SysCtrlRegs.HISPCP.all = 0x0002;
+#endif   
+#if CLKMULT == 5
+   SysCtrlRegs.HISPCP.all = 0x0003;
+#endif
+   
+   SysCtrlRegs.LOSPCP.all = 0x0000;
+
+	Val =	(SysCtrlRegs.HISPCP.all)?
+			 SysCtrlRegs.HISPCP.all*2 : 1;
+	Val = SYSCLKOUT / Val;
+
+	HSPCLK = Val;
+
+	Val =	(SysCtrlRegs.LOSPCP.all)?
+			 SysCtrlRegs.LOSPCP.all*2 : 1;
+	Val = SYSCLKOUT / Val;
+	LSPCLK = Val;
+
+// XCLKOUT to SYSCLKOUT ratio.  By default XCLKOUT = 1/4 SYSCLKOUT
+   // XTIMCLK = SYSCLKOUT/2
+   XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
+   // XCLKOUT = XTIMCLK/2
+   XintfRegs.XINTCNF2.bit.CLKMODE = 1;
+   // Enable XCLKOUT
+   XintfRegs.XINTCNF2.bit.CLKOFF = 0;
+
+// Peripheral clock enables set for the selected peripherals.
+// If you are not using a peripheral leave the clock off
+// to save on power.
+//
+// Note: not all peripherals are available on all 2833x derivates.
+// Refer to the datasheet for your particular device.
+//
+// This function is not written to be an example of efficient code.
+
+   SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;    // ADC
+
+   // *IMPORTANT*
+   // The ADC_cal function, which  copies the ADC calibration values from TI reserved
+   // OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
+   // Boot ROM. If the boot ROM code is bypassed during the debug process, the
+   // following function MUST be called for the ADC to function according
+   // to specification. The clocks to the ADC MUST be enabled before calling this
+   // function.
+   // See the device data manual and/or the ADC Reference
+   // Manual for more information.
+
+   ADC_cal();
+
+
+   SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1;   // I2C
+   SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1;   // SCI-A
+   SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1;   // SCI-B
+   SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1;   // SCI-C
+   SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1;   // SPI-A
+   SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
+   SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B
+   SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1;    // eCAN-A
+   SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1;    // eCAN-B
+
+   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;   // Disable TBCLK within the ePWM
+   SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1;  // ePWM1
+   SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1;  // ePWM2
+   SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1;  // ePWM3
+   SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1;  // ePWM4
+   SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1;  // ePWM5
+   SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1;  // ePWM6
+   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;   // Enable TBCLK within the ePWM
+
+   SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1;  // eCAP3
+   SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1;  // eCAP4
+   SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1;  // eCAP5
+   SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1;  // eCAP6
+   SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1;  // eCAP1
+   SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1;  // eCAP2
+   SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1;  // eQEP1
+   SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1;  // eQEP2
+
+   SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
+   SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
+   SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
+
+   SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1;       // DMA Clock
+   SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;     // XTIMCLK
+   SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1;    // GPIO input clock
+
+   EDIS;
+}
+
+//---------------------------------------------------------------------------
+// Example: CsmUnlock:
+//---------------------------------------------------------------------------
+// This function unlocks the CSM. User must replace 0xFFFF's with current
+// password for the DSP. Returns 1 if unlock is successful.
+
+#define STATUS_FAIL          0
+#define STATUS_SUCCESS       1
+
+Uint16 CsmUnlock()
+{
+    volatile Uint16 temp;
+
+    // Load the key registers with the current password. The 0xFFFF's are dummy
+	// passwords.  User should replace them with the correct password for the DSP.
+
+    EALLOW;
+    CsmRegs.KEY0 = 0xFFFF;
+    CsmRegs.KEY1 = 0xFFFF;
+    CsmRegs.KEY2 = 0xFFFF;
+    CsmRegs.KEY3 = 0xFFFF;
+    CsmRegs.KEY4 = 0xFFFF;
+    CsmRegs.KEY5 = 0xFFFF;
+    CsmRegs.KEY6 = 0xFFFF;
+    CsmRegs.KEY7 = 0xFFFF;
+    EDIS;
+
+    // Perform a dummy read of the password locations
+    // if they match the key values, the CSM will unlock
+
+    temp = CsmPwl.PSWD0;
+    temp = CsmPwl.PSWD1;
+    temp = CsmPwl.PSWD2;
+    temp = CsmPwl.PSWD3;
+    temp = CsmPwl.PSWD4;
+    temp = CsmPwl.PSWD5;
+    temp = CsmPwl.PSWD6;
+    temp = CsmPwl.PSWD7;
+
+    // If the CSM unlocked, return succes, otherwise return
+    // failure.
+    if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS;
+    else return STATUS_FAIL;
+
+}
+
+
+//===========================================================================
+// End of file.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_Xintf.c

@@ -0,0 +1,242 @@
+// TI File $Revision: /main/5 $
+// Checkin $Date: August 16, 2007   11:06:26 $
+//###########################################################################
+//
+// FILE:   DSP2833x_Xintf.c
+//
+// TITLE:   DSP2833x Device External Interface Init & Support Functions.
+//
+// DESCRIPTION:
+//
+//          Example initialization function for the external interface (XINTF).
+//          This example configures the XINTF to its default state.  For an
+//          example of how this function being used refer to the
+//          examples/run_from_xintf project.
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
+#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File
+
+//---------------------------------------------------------------------------
+// InitXINTF:
+//---------------------------------------------------------------------------
+// This function initializes the External Interface the default reset state.
+//
+// Do not modify the timings of the XINTF while running from the XINTF.  Doing
+// so can yield unpredictable results
+
+
+void InitXintf(void)
+{
+    // This shows how to write to the XINTF registers.  The
+    // values used here are the default state after reset.
+    // Different hardware will require a different configuration.
+
+    // For an example of an XINTF configuration used with the
+    // F28335 eZdsp, refer to the examples/run_from_xintf project.
+
+    // Any changes to XINTF timing should only be made by code
+    // running outside of the XINTF.
+
+    // All Zones---------------------------------
+    // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
+    EALLOW;
+    XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
+    // No write buffering
+    XintfRegs.XINTCNF2.bit.WRBUFF = 0;
+    // XCLKOUT is enabled
+    XintfRegs.XINTCNF2.bit.CLKOFF = 0;
+    // XCLKOUT = XTIMCLK/2
+    XintfRegs.XINTCNF2.bit.CLKMODE = 1;
+
+
+    // Zone 0------------------------------------
+    // When using ready, ACTIVE must be 1 or greater
+    // Lead must always be 1 or greater
+    // Zone write timing
+    XintfRegs.XTIMING0.bit.XWRLEAD = 3;
+    XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
+    XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
+    // Zone read timing
+    XintfRegs.XTIMING0.bit.XRDLEAD = 3;
+    XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
+    XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
+
+    // double all Zone read/write lead/active/trail timing
+    XintfRegs.XTIMING0.bit.X2TIMING = 1;
+
+    // Zone will sample XREADY signal
+    XintfRegs.XTIMING0.bit.USEREADY = 1;
+    XintfRegs.XTIMING0.bit.READYMODE = 1;  // sample asynchronous
+
+    // Size must be either:
+    // 0,1 = x32 or
+    // 1,1 = x16 other values are reserved
+    XintfRegs.XTIMING0.bit.XSIZE = 3;
+
+    // Zone 6------------------------------------
+    // When using ready, ACTIVE must be 1 or greater
+    // Lead must always be 1 or greater
+    // Zone write timing
+    XintfRegs.XTIMING6.bit.XWRLEAD = 3;
+    XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
+    XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
+    // Zone read timing
+    XintfRegs.XTIMING6.bit.XRDLEAD = 3;
+    XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
+    XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
+
+    // double all Zone read/write lead/active/trail timing
+    XintfRegs.XTIMING6.bit.X2TIMING = 1;
+
+    // Zone will sample XREADY signal
+    XintfRegs.XTIMING6.bit.USEREADY = 1;
+    XintfRegs.XTIMING6.bit.READYMODE = 1;  // sample asynchronous
+
+    // Size must be either:
+    // 0,1 = x32 or
+    // 1,1 = x16 other values are reserved
+    XintfRegs.XTIMING6.bit.XSIZE = 3;
+
+
+    // Zone 7------------------------------------
+    // When using ready, ACTIVE must be 1 or greater
+    // Lead must always be 1 or greater
+    // Zone write timing
+    XintfRegs.XTIMING7.bit.XWRLEAD = 3;
+    XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
+    XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
+    // Zone read timing
+    XintfRegs.XTIMING7.bit.XRDLEAD = 3;
+    XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
+    XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
+
+    // double all Zone read/write lead/active/trail timing
+    XintfRegs.XTIMING7.bit.X2TIMING = 1;
+
+    // Zone will sample XREADY signal
+    XintfRegs.XTIMING7.bit.USEREADY = 1;
+    XintfRegs.XTIMING7.bit.READYMODE = 1;  // sample asynchronous
+
+    // Size must be either:
+    // 0,1 = x32 or
+    // 1,1 = x16 other values are reserved
+    XintfRegs.XTIMING7.bit.XSIZE = 3;
+
+    // Bank switching
+    // Assume Zone 7 is slow, so add additional BCYC cycles
+    // when ever switching from Zone 7 to another Zone.
+    // This will help avoid bus contention.
+    XintfRegs.XBANK.bit.BANK = 7;
+    XintfRegs.XBANK.bit.BCYC = 7;
+    EDIS;
+   //Force a pipeline flush to ensure that the write to
+   //the last register configured occurs before returning.
+
+   InitXintf16Gpio();
+// InitXintf32Gpio();
+
+   asm(" RPT #7 || NOP");
+
+}
+
+void InitXintf32Gpio()
+{
+     EALLOW;
+     GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3;  // XD31
+     GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3;  // XD30
+     GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3;  // XD29
+     GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3;  // XD28
+     GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3;  // XD27
+     GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3;  // XD26
+     GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3;  // XD25
+     GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3;  // XD24
+     GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3;  // XD23
+     GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3;  // XD22
+     GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3;  // XD21
+     GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3;  // XD20
+     GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3;  // XD19
+     GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3;  // XD18
+     GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3;  // XD17
+     GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3;  // XD16
+
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3;  // XD31 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3;  // XD30 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3;  // XD29 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3;  // XD28 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3;  // XD27 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3;  // XD26 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3;  // XD25 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3;  // XD24 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3;  // XD23 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3;  // XD22 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3;  // XD21 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3;  // XD20 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3;  // XD19 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3;  // XD18 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3;  // XD17 asynchronous input
+     GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3;  // XD16 asynchronous input
+
+
+     InitXintf16Gpio();
+}
+
+void InitXintf16Gpio()
+{
+     EALLOW;
+     GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3;  // XD15
+     GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3;  // XD14
+     GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3;  // XD13
+     GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3;  // XD12
+     GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3;  // XD11
+     GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3;  // XD10
+     GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3;  // XD19
+     GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3;  // XD8
+     GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3;  // XD7
+     GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3;  // XD6
+     GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3;  // XD5
+     GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3;  // XD4
+     GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3;  // XD3
+     GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3;  // XD2
+     GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3;  // XD1
+     GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3;  // XD0
+
+     GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3;  // XA0/XWE1n
+     GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3;  // XA1
+     GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3;  // XA2
+     GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3;  // XA3
+     GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3;  // XA4
+     GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3;  // XA5
+     GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3;  // XA6
+     GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3;  // XA7
+
+     GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3;  // XA8
+     GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3;  // XA9
+     GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3;  // XA10
+     GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3;  // XA11
+     GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3;  // XA12
+     GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3;  // XA13
+     GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3;  // XA14
+     GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3;  // XA15
+     GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3;  // XA16
+     GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3;  // XA17
+     GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3;  // XA18
+     GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3;  // XA19
+
+     GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3;  // XREADY
+	 GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3;  // XRNW
+     GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3;  // XWE0
+
+     GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3;  // XZCS0
+     GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3;  // XZCS7
+     GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3;  // XZCS6
+     EDIS;
+}
+
+//===========================================================================
+// No more.
+//===========================================================================

Source/External/v120/DSP2833x_common/source/DSP2833x_usDelay.asm

@@ -0,0 +1,76 @@
+;// TI File $Revision: /main/4 $
+;// Checkin $Date: July 30, 2007   10:28:57 $
+;//###########################################################################
+;//
+;// FILE:  DSP2833x_usDelay.asm
+;//
+;// TITLE: Simple delay function
+;//
+;// DESCRIPTION:
+;//  
+;// This is a simple delay function that can be used to insert a specified
+;// delay into code.  
+;// 
+;// This function is only accurate if executed from internal zero-waitstate
+;// SARAM. If it is executed from waitstate memory then the delay will be
+;// longer then specified. 
+;// 
+;// To use this function:
+;//
+;//  1 - update the CPU clock speed in the DSP2833x_Examples.h
+;//    file. For example:
+;//    #define CPU_RATE 6.667L // for a 150MHz CPU clock speed
+;//    or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed 
+;//
+;//  2 - Call this function by using the DELAY_US(A) macro
+;//    that is defined in the DSP2833x_Examples.h file.  This macro
+;//    will convert the number of microseconds specified
+;//    into a loop count for use with this function.  
+;//    This count will be based on the CPU frequency you specify.
+;//
+;//  3 - For the most accurate delay 
+;//    - Execute this function in 0 waitstate RAM.  
+;//    - Disable interrupts before calling the function
+;//      If you do not disable interrupts, then think of
+;//      this as an "at least" delay function as the actual
+;//      delay may be longer. 
+;//
+;//  The C assembly call from the DELAY_US(time) macro will
+;//  look as follows: 
+;//
+;//  extern void Delay(long LoopCount);                
+;//
+;//        MOV   AL,#LowLoopCount
+;//        MOV   AH,#HighLoopCount
+;//        LCR   _Delay
+;//
+;//  Or as follows (if count is less then 16-bits):
+;//
+;//        MOV   ACC,#LoopCount
+;//        LCR   _Delay
+;//
+;//
+;//###########################################################################
+;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+;// $Release Date: August 1, 2008 $
+;//###########################################################################	
+
+       .def _DSP28x_usDelay
+       .sect ".text"
+
+        .global  __DSP28x_usDelay
+_DSP28x_usDelay:
+        SUB    ACC,#1
+        BF     _DSP28x_usDelay,GEQ    ;; Loop if ACC >= 0
+        LRETR 
+
+;There is a 9/10 cycle overhead and each loop
+;takes five cycles. The LoopCount is given by
+;the following formula:
+;  DELAY_CPU_CYCLES = 9 + 5*LoopCount
+; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
+; The macro DELAY_US(A) performs this calculation for you
+;
+;//===========================================================================
+;// End of file.
+;//===========================================================================

Source/External/v120/DSP2833x_examples/adc_dma/Example_2833xAdcToDMA.c

@@ -0,0 +1,212 @@
+//###########################################################################
+//
+// FILE:   Example_2833xAdcToDMA.c
+//
+// TITLE:  DSP2833x ADC To DMA
+// ASSUMPTIONS:
+//
+//    This program requires the DSP2833x header files.
+//
+//    Make sure the CPU clock speed is properly defined in
+//    DSP2833x_Examples.h before compiling this example.
+//
+//    Connect the signals to be converted to channel A0, A1, A2, and A3.
+//
+//    As supplied, this project is configured for "boot to SARAM"
+//    operation.  The 2833x Boot Mode table is shown below.
+//    For information on configuring the boot mode of an eZdsp,
+//    please refer to the documentation included with the eZdsp,
+//
+//       $Boot_Table:
+//
+//         GPIO87   GPIO86     GPIO85   GPIO84
+//          XA15     XA14       XA13     XA12
+//           PU       PU         PU       PU
+//        ==========================================
+//            1        1          1        1    Jump to Flash
+//            1        1          1        0    SCI-A boot
+//            1        1          0        1    SPI-A boot
+//            1        1          0        0    I2C-A boot
+//            1        0          1        1    eCAN-A boot
+//            1        0          1        0    McBSP-A boot
+//            1        0          0        1    Jump to XINTF x16
+//            1        0          0        0    Jump to XINTF x32
+//            0        1          1        1    Jump to OTP
+//            0        1          1        0    Parallel GPIO I/O boot
+//            0        1          0        1    Parallel XINTF boot
+//            0        1          0        0    Jump to SARAM	    <- "boot to SARAM"
+//            0        0          1        1    Branch to check boot mode
+//            0        0          1        0    Boot to flash, bypass ADC cal
+//            0        0          0        1    Boot to SARAM, bypass ADC cal
+//            0        0          0        0    Boot to SCI-A, bypass ADC cal
+//                                              Boot_Table_End$
+//
+//
+// DESCRIPTION:
+//
+// ADC is setup to convert 4 channels for each SOC received, with  total of 10 SOCs.
+// Each SOC initiates 4 conversions.
+// DMA is set up to capture the data on each SEQ1_INT.  DMA will re-sort   
+// the data by channel sequentially, i.e. all channel0 data will be together
+// all channel1 data will be together.
+//
+// Code should stop in local_DINTCH1_ISR when complete
+//
+// Watch Variables:
+//      DMABuf1
+//
+//###########################################################################
+//
+// Original source by: M.P.
+//
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
+
+// ADC start parameters
+#if (CPU_FRQ_150MHZ)     // Default - 150 MHz SYSCLKOUT
+  #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3)   = 25.0 MHz
+#endif
+#if (CPU_FRQ_100MHZ)
+  #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2)   = 25.0 MHz
+#endif
+#define ADC_CKPS   0x1   // ADC module clock = HSPCLK/2*ADC_CKPS   = 25.0MHz/(1*2) = 12.5MHz
+#define ADC_SHCLK  0xf   // S/H width in ADC module periods                        = 16 ADC clocks
+#define AVG        1000  // Average sample limit
+#define ZOFFSET    0x00  // Average Zero offset
+#define BUF_SIZE   40    // Sample buffer size
+
+// Global variable for this example
+Uint16 j=0;
+
+#pragma DATA_SECTION(DMABuf1,"DMARAML4");
+volatile Uint16 DMABuf1[40];
+
+volatile Uint16 *DMADest;
+volatile Uint16 *DMASource;
+interrupt void local_DINTCH1_ISR(void);
+
+void main(void)
+{
+   Uint16 i;
+// Step 1. Initialize System Control:
+// PLL, WatchDog, enable Peripheral Clocks
+// This example function is found in the DSP2833x_SysCtrl.c file.
+   InitSysCtrl();
+
+// Specific clock setting for this example:
+   EALLOW;
+   SysCtrlRegs.HISPCP.all = ADC_MODCLK;	// HSPCLK = SYSCLKOUT/ADC_MODCLK
+   EDIS;
+
+// Step 2. Initialize GPIO:
+// This example function is found in the DSP2833x_Gpio.c file and
+// illustrates how to set the GPIO to it's default state.
+// InitGpio();  // Skipped for this example
+
+// Step 3. Clear all interrupts and initialize PIE vector table:
+// Disable CPU interrupts
+   DINT;
+
+// Initialize the PIE control registers to their default state.
+// The default state is all PIE interrupts disabled and flags
+// are cleared.
+// This function is found in the DSP2833x_PieCtrl.c file.
+   InitPieCtrl();
+
+// Disable CPU interrupts and clear all CPU interrupt flags:
+   IER = 0x0000;
+   IFR = 0x0000;
+
+// Initialize the PIE vector table with pointers to the shell Interrupt
+// Service Routines (ISR).
+// This will populate the entire table, even if the interrupt
+// is not used in this example.  This is useful for debug purposes.
+// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
+// This function is found in DSP2833x_PieVect.c.
+   InitPieVectTable();
+
+// Interrupts that are used in this example are re-mapped to
+// ISR functions found within this file.
+   EALLOW;	// Allow access to EALLOW protected registers
+   PieVectTable.DINTCH1= &local_DINTCH1_ISR;
+   EDIS;   // Disable access to EALLOW protected registers
+      
+   IER = M_INT7 ;	                             //Enable INT7 (7.1 DMA Ch1)
+   EnableInterrupts();
+   
+// Step 4. Initialize all the Device Peripherals:
+// This function is found in DSP2833x_InitPeripherals.c
+// InitPeripherals(); // Not required for this example
+   InitAdc();  // For this example, init the ADC
+
+// Specific ADC setup for this example:
+   AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;
+   AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;
+   AdcRegs.ADCTRL1.bit.SEQ_CASC = 0;        // 0 Non-Cascaded Mode
+   AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;
+   AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;
+   AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;
+   AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1;
+   AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2;
+   AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3;
+   AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x0;
+   AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x1;
+   AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x2;
+   AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x3;
+   AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 3;   // Set up ADC to perform 4 conversions for every SOC
+   
+//Step 5. User specific code, enable interrupts:
+  // Initialize DMA 
+	DMAInitialize();
+
+	// Clear Table
+   for (i=0; i<BUF_SIZE; i++)
+   {
+     DMABuf1[i] = 0;
+   }
+
+	
+// Configure DMA Channel
+    DMADest   = &DMABuf1[0];              //Point DMA destination to the beginning of the array
+	DMASource = &AdcMirror.ADCRESULT0;    //Point DMA source to ADC result register base
+	DMACH1AddrConfig(DMADest,DMASource);
+	DMACH1BurstConfig(3,1,10);
+	DMACH1TransferConfig(9,1,0);
+	DMACH1WrapConfig(1,0,0,1);
+	DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,SYNC_DISABLE,SYNC_SRC,
+	                 OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE); 
+
+ 
+
+ 
+
+	StartDMACH1();
+
+   
+
+   // Start SEQ1
+   AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x1;
+   for(i=0;i<10;i++){
+    	for(j=0;j<1000;j++){}
+        AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;    //Normally ADC will be tied to ePWM, or timed routine
+   }	                                     //For this example will re-start manually                   
+
+}
+
+// INT7.1
+interrupt void local_DINTCH1_ISR(void)     // DMA Channel 1
+{
+  
+  // To receive more interrupts from this PIE group, acknowledge this interrupt 
+   PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
+
+  // Next two lines for debug only to halt the processor here
+  // Remove after inserting ISR Code
+   asm ("      ESTOP0");
+   for(;;);
+}
+
+

Source/External/v120/DSP2833x_examples/adc_dma/Example_2833xAdcToDMA.gel

@@ -0,0 +1,36 @@
+/*
+// TI File $Revision: /main/1 $
+// Checkin $Date: August 14, 2007   14:20:30 $
+//###########################################################################
+//
+// This .gel file can be used to help load and build the example project.
+// It should be unloaded from Code Composer Studio before loading another 
+// project. 
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+menuitem "DSP2833x ADC SOC Example"
+
+hotmenu Load_and_Build_Project()
+{
+   GEL_ProjectLoad("Example_2833xAdcToDMA.pjt");
+   GEL_ProjectBuild("Example_2833xAdcToDMA.pjt");
+   Setup_WatchWindow();
+}
+
+hotmenu Load_Code()
+{
+   GEL_Load(".\\debug\\Example_2833xAdcToDMA.out");
+   Setup_WatchWindow();
+}
+
+hotmenu Setup_WatchWindow()
+{
+   GEL_WatchReset();
+   GEL_WatchAdd("AdcRegs,x");
+   GEL_WatchAdd("DMABuf1,x");
+}

Source/External/v120/DSP2833x_examples/adc_dma/Example_2833xAdcToDMA.pjt

@@ -0,0 +1,47 @@
+; Code Composer Project File, Version 2.0 (do not modify or remove this line)
+
+[Project Settings]
+ProjectName="DSP28"
+ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_dma\"
+ProjectType=Executable
+CPUFamily=TMS320C28XX
+Tool="Compiler"
+Tool="CustomBuilder"
+Tool="DspBiosBuilder"
+Tool="Linker"
+Config="Debug"
+Config="Release"
+
+[Source Files]
+Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
+Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm"
+Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_DMA.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm"
+Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
+Source="Example_2833xAdcToDMA.c"
+Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd"
+Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
+
+["Compiler" Settings: "Debug"]
+Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_dma\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_dma\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28
+
+["Compiler" Settings: "Release"]
+Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_dma\Release" -d"LARGE_MODEL" -ml -v28
+
+["DspBiosBuilder" Settings: "Debug"]
+Options=-v28
+
+["DspBiosBuilder" Settings: "Release"]
+Options=-v28
+
+["Linker" Settings: "Debug"]
+Options=-q -c -ecode_start -m".\Debug\Example_2833xAdcToDMA.map" -o".\Debug\Example_2833xAdcToDMA.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib"
+
+["Linker" Settings: "Release"]
+Options=-q -c -o".\Release\Example_2833xAdcToDMA.out" -x
+

Source/External/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.c

@@ -0,0 +1,266 @@
+// TI File $Revision: /main/10 $
+// Checkin $Date: April 21, 2008   15:40:51 $
+//###########################################################################
+//
+// FILE:   Example_2833xAdcSeq_ovdTest.c
+//
+// TITLE:  DSP2833x ADC Seq Override mode Test.
+//
+// ASSUMPTIONS:
+//
+//    This program requires the DSP2833x header files.
+//
+//    Make sure the CPU clock speed is properly defined in
+//    DSP2833x_Examples.h before compiling this example.
+//
+//    Connect the signal to be converted to Channel A0.
+//
+//    As supplied, this project is configured for "boot to SARAM"
+//    operation.  The 2833x Boot Mode table is shown below.
+//    For information on configuring the boot mode of an eZdsp,
+//    please refer to the documentation included with the eZdsp,
+//
+//       $Boot_Table:
+//
+//         GPIO87   GPIO86     GPIO85   GPIO84
+//          XA15     XA14       XA13     XA12
+//           PU       PU         PU       PU
+//        ==========================================
+//            1        1          1        1    Jump to Flash
+//            1        1          1        0    SCI-A boot
+//            1        1          0        1    SPI-A boot
+//            1        1          0        0    I2C-A boot
+//            1        0          1        1    eCAN-A boot
+//            1        0          1        0    McBSP-A boot
+//            1        0          0        1    Jump to XINTF x16
+//            1        0          0        0    Jump to XINTF x32
+//            0        1          1        1    Jump to OTP
+//            0        1          1        0    Parallel GPIO I/O boot
+//            0        1          0        1    Parallel XINTF boot
+//            0        1          0        0    Jump to SARAM	    <- "boot to SARAM"
+//            0        0          1        1    Branch to check boot mode
+//            0        0          1        0    Boot to flash, bypass ADC cal
+//            0        0          0        1    Boot to SARAM, bypass ADC cal
+//            0        0          0        0    Boot to SCI-A, bypass ADC cal
+//                                              Boot_Table_End$
+//
+// DESCRIPTION:
+//
+//    Channel A0 is converted forever and logged in a buffer (SampleTable)
+//    Using sequencer1 in sequencer override mode. Sequencer is Sequential mode
+//    with sample rate of1/(3*40ns) =8.3MHz
+//
+//    Open a memory window to SampletTable to observe the buffer
+//    RUN for a while and stop and see the table contents.
+//
+//       Watch Variables:
+//          SampleTable - Log of converted values.
+//          GPIO34      - Toggles on every ADC sequencer flag
+//
+//###########################################################################
+//
+// Original source by: S.S.
+//
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
+
+// Determine when the shift to right justify the data takes place
+// Only one of these should be defined as 1.
+// The other two should be defined as 0.
+#define POST_SHIFT   0  // Shift results after the entire sample table is full
+#define INLINE_SHIFT 1  // Shift results as the data is taken from the results regsiter
+#define NO_SHIFT     0  // Do not shift the results
+
+// ADC start parameters
+#if (CPU_FRQ_150MHZ)     // Default - 150 MHz SYSCLKOUT
+  #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3)   = 25.0 MHz
+#endif
+#if (CPU_FRQ_100MHZ)
+  #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2)   = 25.0 MHz
+#endif
+#define ADC_CKPS   0x0   // ADC module clock = HSPCLK/1      = 25.5MHz/(1)   = 25.0 MHz
+#define ADC_SHCLK  0x1   // S/H width in ADC module periods                  = 2 ADC cycle
+#define AVG        1000  // Average sample limit
+#define ZOFFSET    0x00  // Average Zero offset
+#define BUF_SIZE   1024  // Sample buffer size
+
+// Global variable for this example
+Uint16 SampleTable[BUF_SIZE];
+
+
+main()
+{
+   Uint16 i;
+   Uint16 array_index;
+
+
+// Step 1. Initialize System Control:
+// PLL, WatchDog, enable Peripheral Clocks
+// This example function is found in the DSP2833x_SysCtrl.c file.
+   InitSysCtrl();
+
+// Specific clock setting for this example:
+   EALLOW;
+   SysCtrlRegs.HISPCP.all = ADC_MODCLK;	// HSPCLK = SYSCLKOUT/ADC_MODCLK
+   EDIS;
+
+// Step 2. Initialize GPIO:
+// This example function is found in the DSP2833x_Gpio.c file and
+// illustrates how to set the GPIO to it's default state.
+// InitGpio();  // Skipped for this example
+// Enable the pin GPIO34 as output
+   EALLOW;
+   GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;    // GPIO pin
+   GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;     // Output pin
+   EDIS;
+
+// Step 3. Clear all interrupts and initialize PIE vector table:
+// Disable CPU interrupts
+   DINT;
+
+// Initialize the PIE control registers to their default state.
+// The default state is all PIE interrupts disabled and flags
+// are cleared.
+// This function is found in the DSP2833x_PieCtrl.c file.
+   InitPieCtrl();
+
+// Disable CPU interrupts and clear all CPU interrupt flags:
+   IER = 0x0000;
+   IFR = 0x0000;
+
+// Initialize the PIE vector table with pointers to the shell Interrupt
+// Service Routines (ISR).
+// This will populate the entire table, even if the interrupt
+// is not used in this example.  This is useful for debug purposes.
+// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
+// This function is found in DSP2833x_PieVect.c.
+   InitPieVectTable();
+
+// Step 4. Initialize all the Device Peripherals:
+// This function is found in DSP2833x_InitPeripherals.c
+// InitPeripherals(); // Not required for this example
+   InitAdc();         // For this example, init the ADC
+
+// Specific ADC setup for this example:
+   AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;  // Sequential mode: Sample rate   = 1/[(2+ACQ_PS)*ADC clock in ns]
+                        //                     = 1/(3*40ns) =8.3MHz (for 150 MHz SYSCLKOUT)
+					    //                     = 1/(3*80ns) =4.17MHz (for 100 MHz SYSCLKOUT)
+					    // If Simultaneous mode enabled: Sample rate = 1/[(3+ACQ_PS)*ADC clock in ns]
+   AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;
+   AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;        // 1  Cascaded mode
+   AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;
+   AdcRegs.ADCTRL1.bit.CONT_RUN = 1;       // Setup continuous run
+
+   AdcRegs.ADCTRL1.bit.SEQ_OVRD = 1;       // Enable Sequencer override feature
+   AdcRegs.ADCCHSELSEQ1.all = 0x0;         // Initialize all ADC channel selects to A0
+   AdcRegs.ADCCHSELSEQ2.all = 0x0;
+   AdcRegs.ADCCHSELSEQ3.all = 0x0;
+   AdcRegs.ADCCHSELSEQ4.all = 0x0;
+   AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x7;  // convert and store in 8 results registers
+
+
+// Step 5. User specific code, enable interrupts:
+
+
+// Clear SampleTable
+   for (i=0; i<BUF_SIZE; i++)
+   {
+     SampleTable[i] = 0;
+   }
+
+// Start SEQ1
+   AdcRegs.ADCTRL2.all = 0x2000;
+
+   for(;;)
+   {  // Take ADC data and log them in SampleTable array
+
+     // Initalize the array index.  This points to the current
+     // location within the SampleTable
+     array_index = 0;
+
+     for (i=0; i<(BUF_SIZE/16); i++)
+     {
+       // Wait for int1
+       while (AdcRegs.ADCST.bit.INT_SEQ1== 0){}
+       GpioDataRegs.GPBSET.bit.GPIO34 = 1;  // Set GPIO34 for monitoring  -optional
+
+       AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
+
+#if INLINE_SHIFT
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT0)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT1)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT2)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT3)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT4)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT5)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT6)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT7)>>4);
+
+#endif //-- INLINE_SHIFT
+
+#if NO_SHIFT || POST_SHIFT
+
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT0));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT1));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT2));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT3));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT4));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT5));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT6));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT7));
+
+#endif //-- NO_SHIFT || POST_SHIFT
+
+       while (AdcRegs.ADCST.bit.INT_SEQ1== 0){}
+ 	   GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1;  // Clear GPIO34 for monitoring  -optional
+       AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
+
+#if INLINE_SHIFT
+
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT8)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT9)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT10)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT11)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT12)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT13)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT14)>>4);
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT15)>>4);
+
+#endif //-- INLINE_SHIFT
+
+#if NO_SHIFT || POST_SHIFT
+
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT8));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT9));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT10));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT11));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT12));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT13));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT14));
+       SampleTable[array_index++]= ( (AdcRegs.ADCRESULT15));
+#endif // -- NO_SHIFT || POST_SHIFT
+
+	}
+
+
+#if POST_SHIFT
+    // For post shifting, shift the ADC results
+    // in the SampleTable buffer after the buffer is full.
+    for (i=0; i<BUF_SIZE; i++)
+    {
+      SampleTable[i] = ((SampleTable[i]) >>4);
+    }
+#endif // -- POST_SHIFT
+
+    GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1;  // Clear GPIO34 for monitoring  -optional
+  }
+}
+
+//===========================================================================
+// No more.
+//===========================================================================
+
+

Source/External/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.gel

@@ -0,0 +1,39 @@
+/*
+// TI File $Revision: /main/5 $
+// Checkin $Date: August 9, 2007   17:11:35 $
+//###########################################################################
+//
+// This .gel file can be used to help load and build the example project.
+// It should be unloaded from Code Composer Studio before loading another 
+// project. 
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+menuitem "DSP2833x ADC Seq_ovd Test"
+
+
+hotmenu Load_and_Build_Project()
+{
+   GEL_ProjectLoad("Example_2833xAdcSeq_ovdTest.pjt");
+   GEL_ProjectBuild("Example_2833xAdcSeq_ovdTest.pjt");
+   Setup_WatchWindow();
+}
+
+hotmenu Load_Code()
+{
+   GEL_Load(".\\debug\\Example_2833xAdcSeq_ovdTest.out");
+   Setup_WatchWindow();
+}
+
+hotmenu Setup_WatchWindow()
+{
+   GEL_WatchReset();
+   GEL_WatchAdd("SampleTable,x");
+   GEL_WatchAdd("AdcRegs,x",);
+}
+
+

Source/External/v120/DSP2833x_examples/adc_seq_ovd_test/Example_2833xAdcSeq_ovdTest.pjt

@@ -0,0 +1,45 @@
+; Code Composer Project File, Version 2.0 (do not modify or remove this line)
+
+[Project Settings]
+ProjectName="DSP2833x"
+ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\"
+ProjectType=Executable
+CPUFamily=TMS320C28XX
+Tool="Compiler"
+Tool="DspBiosBuilder"
+Tool="Linker"
+Config="Debug"
+Config="Release"
+
+[Source Files]
+Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
+Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm"
+Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm"
+Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
+Source="Example_2833xAdcSeq_ovdTest.c"
+Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd"
+Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
+
+["Compiler" Settings: "Debug"]
+Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28
+
+["Compiler" Settings: "Release"]
+Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seq_ovd_test\Release" -d"LARGE_MODEL" -ml -v28
+
+["DspBiosBuilder" Settings: "Debug"]
+Options=-v28
+
+["DspBiosBuilder" Settings: "Release"]
+Options=-v28
+
+["Linker" Settings: "Debug"]
+Options=-q -c -ecode_start -m".\Debug\Example_2833xAdcSeq_ovdTest.map" -o".\Debug\Example_2833xAdcSeq_ovdTest.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib"
+
+["Linker" Settings: "Release"]
+Options=-q -c -o".\Release\Example_2833xAdcSeq_ovdTest.out" -x
+

Source/External/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.c

@@ -0,0 +1,164 @@
+// TI File $Revision: /main/10 $
+// Checkin $Date: April 21, 2008   15:40:57 $
+//###########################################################################
+//
+// FILE:   Example_2833xAdcSeqModeTest.c
+//
+// TITLE:  DSP2833x ADC Seq Mode Test.
+//
+// ASSUMPTIONS:
+//
+//    This program requires the DSP2833x header files.
+//
+//    Make sure the CPU clock speed is properly defined in
+//    DSP2833x_Examples.h before compiling this example.
+//
+//    Connect the signal to be converted to channel A0.
+//
+//    As supplied, this project is configured for "boot to SARAM"
+//    operation.  The 2833x Boot Mode table is shown below.
+//    For information on configuring the boot mode of an eZdsp,
+//    please refer to the documentation included with the eZdsp,
+//
+//       $Boot_Table:
+//
+//         GPIO87   GPIO86     GPIO85   GPIO84
+//          XA15     XA14       XA13     XA12
+//           PU       PU         PU       PU
+//        ==========================================
+//            1        1          1        1    Jump to Flash
+//            1        1          1        0    SCI-A boot
+//            1        1          0        1    SPI-A boot
+//            1        1          0        0    I2C-A boot
+//            1        0          1        1    eCAN-A boot
+//            1        0          1        0    McBSP-A boot
+//            1        0          0        1    Jump to XINTF x16
+//            1        0          0        0    Jump to XINTF x32
+//            0        1          1        1    Jump to OTP
+//            0        1          1        0    Parallel GPIO I/O boot
+//            0        1          0        1    Parallel XINTF boot
+//            0        1          0        0    Jump to SARAM	    <- "boot to SARAM"
+//            0        0          1        1    Branch to check boot mode
+//            0        0          1        0    Boot to flash, bypass ADC cal
+//            0        0          0        1    Boot to SARAM, bypass ADC cal
+//            0        0          0        0    Boot to SCI-A, bypass ADC cal
+//                                              Boot_Table_End$
+//
+// DESCRIPTION:
+//
+//    Channel A0 is converted forever and logged in a buffer (SampleTable)
+//
+//    Open a memory window to SampleTable to observe the buffer
+//    RUN for a while and stop and see the table contents.
+//
+//       Watch Variables:
+//          SampleTable - Log of converted values.
+//
+//###########################################################################
+//
+// Original source by: S.S.
+//
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
+
+// ADC start parameters
+#if (CPU_FRQ_150MHZ)     // Default - 150 MHz SYSCLKOUT
+  #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3)   = 25.0 MHz
+#endif
+#if (CPU_FRQ_100MHZ)
+  #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2)   = 25.0 MHz
+#endif
+#define ADC_CKPS   0x1   // ADC module clock = HSPCLK/2*ADC_CKPS   = 25.0MHz/(1*2) = 12.5MHz
+#define ADC_SHCLK  0xf   // S/H width in ADC module periods                        = 16 ADC clocks
+#define AVG        1000  // Average sample limit
+#define ZOFFSET    0x00  // Average Zero offset
+#define BUF_SIZE   2048  // Sample buffer size
+
+// Global variable for this example
+Uint16 SampleTable[BUF_SIZE];
+
+main()
+{
+   Uint16 i;
+
+// Step 1. Initialize System Control:
+// PLL, WatchDog, enable Peripheral Clocks
+// This example function is found in the DSP2833x_SysCtrl.c file.
+   InitSysCtrl();
+
+// Specific clock setting for this example:
+   EALLOW;
+   SysCtrlRegs.HISPCP.all = ADC_MODCLK;	// HSPCLK = SYSCLKOUT/ADC_MODCLK
+   EDIS;
+
+// Step 2. Initialize GPIO:
+// This example function is found in the DSP2833x_Gpio.c file and
+// illustrates how to set the GPIO to it's default state.
+// InitGpio();  // Skipped for this example
+
+// Step 3. Clear all interrupts and initialize PIE vector table:
+// Disable CPU interrupts
+   DINT;
+
+// Initialize the PIE control registers to their default state.
+// The default state is all PIE interrupts disabled and flags
+// are cleared.
+// This function is found in the DSP2833x_PieCtrl.c file.
+   InitPieCtrl();
+
+// Disable CPU interrupts and clear all CPU interrupt flags:
+   IER = 0x0000;
+   IFR = 0x0000;
+
+// Initialize the PIE vector table with pointers to the shell Interrupt
+// Service Routines (ISR).
+// This will populate the entire table, even if the interrupt
+// is not used in this example.  This is useful for debug purposes.
+// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
+// This function is found in DSP2833x_PieVect.c.
+   InitPieVectTable();
+
+// Step 4. Initialize all the Device Peripherals:
+// This function is found in DSP2833x_InitPeripherals.c
+// InitPeripherals(); // Not required for this example
+   InitAdc();  // For this example, init the ADC
+
+// Specific ADC setup for this example:
+   AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;
+   AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;
+   AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;        // 1  Cascaded mode
+   AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;
+   AdcRegs.ADCTRL1.bit.CONT_RUN = 1;       // Setup continuous run
+
+
+// Step 5. User specific code, enable interrupts:
+
+
+// Clear SampleTable
+   for (i=0; i<BUF_SIZE; i++)
+   {
+     SampleTable[i] = 0;
+   }
+
+   // Start SEQ1
+   AdcRegs.ADCTRL2.all = 0x2000;
+
+   // Take ADC data and log the in SampleTable array
+   for(;;)
+   {
+     for (i=0; i<AVG; i++)
+     {
+        while (AdcRegs.ADCST.bit.INT_SEQ1== 0) {} // Wait for interrupt
+        AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
+        SampleTable[i] =((AdcRegs.ADCRESULT0>>4) );
+     }
+   }
+}
+
+//===========================================================================
+// No more.
+//===========================================================================
+

Source/External/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.gel

@@ -0,0 +1,37 @@
+/*
+// TI File $Revision: /main/5 $
+// Checkin $Date: August 9, 2007   17:11:47 $
+//###########################################################################
+//
+// This .gel file can be used to help load and build the example project.
+// It should be unloaded from Code Composer Studio before loading another 
+// project. 
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+menuitem "DSP2833x ADC Seq Test"
+
+hotmenu Load_and_Build_Project()
+{
+   GEL_ProjectLoad("Example_2833xAdcSeqModeTest.pjt");
+   GEL_ProjectBuild("Example_2833xAdcSeqModeTest.pjt");
+   Setup_WatchWindow();
+}
+
+hotmenu Load_Code()
+{
+   GEL_Load(".\\debug\\Example_2833xAdcSeqModeTest.out");
+   Setup_WatchWindow();
+}
+
+
+hotmenu Setup_WatchWindow()
+{
+   GEL_WatchReset();
+   GEL_WatchAdd("SampleTable,x");
+   GEL_WatchAdd("AdcRegs,x");
+}

Source/External/v120/DSP2833x_examples/adc_seqmode_test/Example_2833xAdcSeqModeTest.pjt

@@ -0,0 +1,45 @@
+; Code Composer Project File, Version 2.0 (do not modify or remove this line)
+
+[Project Settings]
+ProjectName="DSP2833x"
+ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\"
+ProjectType=Executable
+CPUFamily=TMS320C28XX
+Tool="Compiler"
+Tool="DspBiosBuilder"
+Tool="Linker"
+Config="Debug"
+Config="Release"
+
+[Source Files]
+Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
+Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm"
+Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm"
+Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
+Source="Example_2833xAdcSeqModeTest.c"
+Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd"
+Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
+
+["Compiler" Settings: "Debug"]
+Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28
+
+["Compiler" Settings: "Release"]
+Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_seqmode_test\Release" -d"LARGE_MODEL" -ml -v28
+
+["DspBiosBuilder" Settings: "Debug"]
+Options=-v28
+
+["DspBiosBuilder" Settings: "Release"]
+Options=-v28
+
+["Linker" Settings: "Debug"]
+Options=-q -c -ecode_start -m".\Debug\Example_2833xAdcSeqModeTest.map" -o".\Debug\Example_2833xAdcSeqModeTest.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib"
+
+["Linker" Settings: "Release"]
+Options=-q -c -o".\Release\Example_2833xAdcSeqModeTest.out" -x
+

Source/External/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.c

@@ -0,0 +1,203 @@
+// TI File $Revision: /main/11 $
+// Checkin $Date: April 21, 2008   15:41:01 $
+//###########################################################################
+//
+// FILE:   Example_2833xAdc.c
+//
+// TITLE:  DSP2833x ADC Example Program.
+//
+// ASSUMPTIONS:
+//
+//   This program requires the DSP2833x header files.
+//
+//   Make sure the CPU clock speed is properly defined in
+//   DSP2833x_Examples.h before compiling this example.
+//
+//   Connect signals to be converted to A2 and A3.
+//
+//    As supplied, this project is configured for "boot to SARAM"
+//    operation.  The 2833x Boot Mode table is shown below.
+//    For information on configuring the boot mode of an eZdsp,
+//    please refer to the documentation included with the eZdsp,
+//
+//       $Boot_Table:
+//
+//         GPIO87   GPIO86     GPIO85   GPIO84
+//          XA15     XA14       XA13     XA12
+//           PU       PU         PU       PU
+//        ==========================================
+//            1        1          1        1    Jump to Flash
+//            1        1          1        0    SCI-A boot
+//            1        1          0        1    SPI-A boot
+//            1        1          0        0    I2C-A boot
+//            1        0          1        1    eCAN-A boot
+//            1        0          1        0    McBSP-A boot
+//            1        0          0        1    Jump to XINTF x16
+//            1        0          0        0    Jump to XINTF x32
+//            0        1          1        1    Jump to OTP
+//            0        1          1        0    Parallel GPIO I/O boot
+//            0        1          0        1    Parallel XINTF boot
+//            0        1          0        0    Jump to SARAM	    <- "boot to SARAM"
+//            0        0          1        1    Branch to check boot mode
+//            0        0          1        0    Boot to flash, bypass ADC cal
+//            0        0          0        1    Boot to SARAM, bypass ADC cal
+//            0        0          0        0    Boot to SCI-A, bypass ADC cal
+//                                              Boot_Table_End$
+//
+// DESCRIPTION:
+//
+//   This example sets up the PLL in x10/2 mode.
+//
+//   For 150 MHz devices (default)
+//   divides SYSCLKOUT by six to reach a 25.0Mhz HSPCLK
+//   (assuming a 30Mhz XCLKIN).
+//
+//   For 100 MHz devices:
+//   divides SYSCLKOUT by four to reach a 25.0Mhz HSPCLK
+//   (assuming a 20Mhz XCLKIN).
+//
+//   Interrupts are enabled and the ePWM1 is setup to generate a periodic
+//   ADC SOC on SEQ1. Two channels are converted, ADCINA3 and ADCINA2.
+//
+//   Watch Variables:
+//
+//         Voltage1[10]     Last 10 ADCRESULT0 values
+//         Voltage2[10]     Last 10 ADCRESULT1 values
+//         ConversionCount  Current result number 0-9
+//         LoopCount        Idle loop counter
+//
+//
+//###########################################################################
+//
+// Original Author: D.F.
+//
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
+
+// Prototype statements for functions found within this file.
+interrupt void adc_isr(void);
+
+// Global variables used in this example:
+Uint16 LoopCount;
+Uint16 ConversionCount;
+Uint16 Voltage1[10];
+Uint16 Voltage2[10];
+
+
+main()
+{
+
+// Step 1. Initialize System Control:
+// PLL, WatchDog, enable Peripheral Clocks
+// This example function is found in the DSP2833x_SysCtrl.c file.
+   InitSysCtrl();
+
+
+   EALLOW;
+   #if (CPU_FRQ_150MHZ)     // Default - 150 MHz SYSCLKOUT
+     #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3)   = 25.0 MHz
+   #endif
+   #if (CPU_FRQ_100MHZ)
+     #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2)   = 25.0 MHz
+   #endif
+   EDIS;
+
+// Step 2. Initialize GPIO:
+// This example function is found in the DSP2833x_Gpio.c file and
+// illustrates how to set the GPIO to it's default state.
+// InitGpio();  // Skipped for this example
+
+// Step 3. Clear all interrupts and initialize PIE vector table:
+// Disable CPU interrupts
+   DINT;
+
+// Initialize the PIE control registers to their default state.
+// The default state is all PIE interrupts disabled and flags
+// are cleared.
+// This function is found in the DSP2833x_PieCtrl.c file.
+   InitPieCtrl();
+
+// Disable CPU interrupts and clear all CPU interrupt flags:
+   IER = 0x0000;
+   IFR = 0x0000;
+
+// Initialize the PIE vector table with pointers to the shell Interrupt
+// Service Routines (ISR).
+// This will populate the entire table, even if the interrupt
+// is not used in this example.  This is useful for debug purposes.
+// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
+// This function is found in DSP2833x_PieVect.c.
+   InitPieVectTable();
+
+// Interrupts that are used in this example are re-mapped to
+// ISR functions found within this file.
+   EALLOW;  // This is needed to write to EALLOW protected register
+   PieVectTable.ADCINT = &adc_isr;
+   EDIS;    // This is needed to disable write to EALLOW protected registers
+
+// Step 4. Initialize all the Device Peripherals:
+// This function is found in DSP2833x_InitPeripherals.c
+// InitPeripherals(); // Not required for this example
+   InitAdc();  // For this example, init the ADC
+
+// Step 5. User specific code, enable interrupts:
+
+// Enable ADCINT in PIE
+   PieCtrlRegs.PIEIER1.bit.INTx6 = 1;
+   IER |= M_INT1; // Enable CPU Interrupt 1
+   EINT;          // Enable Global interrupt INTM
+   ERTM;          // Enable Global realtime interrupt DBGM
+
+   LoopCount = 0;
+   ConversionCount = 0;
+
+// Configure ADC
+   AdcRegs.ADCMAXCONV.all = 0x0001;       // Setup 2 conv's on SEQ1
+   AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x3; // Setup ADCINA3 as 1st SEQ1 conv.
+   AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x2; // Setup ADCINA2 as 2nd SEQ1 conv.
+   AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1
+   AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;  // Enable SEQ1 interrupt (every EOS)
+
+// Assumes ePWM1 clock is already enabled in InitSysCtrl();
+   EPwm1Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group
+   EPwm1Regs.ETSEL.bit.SOCASEL = 4;       // Select SOC from from CPMA on upcount
+   EPwm1Regs.ETPS.bit.SOCAPRD = 1;        // Generate pulse on 1st event
+   EPwm1Regs.CMPA.half.CMPA = 0x0080;	  // Set compare A value
+   EPwm1Regs.TBPRD = 0xFFFF;              // Set period for ePWM1
+   EPwm1Regs.TBCTL.bit.CTRMODE = 0;		  // count up and start
+
+// Wait for ADC interrupt
+   for(;;)
+   {
+      LoopCount++;
+   }
+
+}
+
+
+interrupt void  adc_isr(void)
+{
+
+  Voltage1[ConversionCount] = AdcRegs.ADCRESULT0 >>4;
+  Voltage2[ConversionCount] = AdcRegs.ADCRESULT1 >>4;
+
+  // If 40 conversions have been logged, start over
+  if(ConversionCount == 9)
+  {
+     ConversionCount = 0;
+  }
+  else ConversionCount++;
+
+  // Reinitialize for next ADC sequence
+  AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;         // Reset SEQ1
+  AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;       // Clear INT SEQ1 bit
+  PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;   // Acknowledge interrupt to PIE
+
+  return;
+}
+
+
+

Source/External/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.gel

@@ -0,0 +1,40 @@
+/*
+// TI File $Revision: /main/5 $
+// Checkin $Date: August 9, 2007   17:11:59 $
+//###########################################################################
+//
+// This .gel file can be used to help load and build the example project.
+// It should be unloaded from Code Composer Studio before loading another 
+// project. 
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+menuitem "DSP2833x ADC SOC Example"
+
+hotmenu Load_and_Build_Project()
+{
+   GEL_ProjectLoad("Example_2833xAdcSoc.pjt");
+   GEL_ProjectBuild("Example_2833xAdcSoc.pjt");
+   Setup_WatchWindow();
+}
+
+hotmenu Load_Code()
+{
+   GEL_Load(".\\debug\\Example_2833xAdcSoc.out");
+   Setup_WatchWindow();
+}
+
+hotmenu Setup_WatchWindow()
+{
+   GEL_WatchReset();
+   GEL_WatchAdd("Voltage1,x");
+   GEL_WatchAdd("Voltage2,x");
+   GEL_WatchAdd("LoopCount,x");
+   GEL_WatchAdd("ConversionCount,d");
+   GEL_WatchAdd("AdcRegs,x");
+   GEL_WatchAdd("EPwm1Regs,x");
+}

Source/External/v120/DSP2833x_examples/adc_soc/Example_2833xAdcSoc.pjt

@@ -0,0 +1,46 @@
+; Code Composer Project File, Version 2.0 (do not modify or remove this line)
+
+[Project Settings]
+ProjectName="DSP28"
+ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\"
+ProjectType=Executable
+CPUFamily=TMS320C28XX
+Tool="Compiler"
+Tool="DspBiosBuilder"
+Tool="Linker"
+Config="Debug"
+Config="Release"
+
+[Source Files]
+Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c"
+
+Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
+Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm"
+Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm"
+Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
+Source="Example_2833xAdcSoc.c"
+Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd"
+Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
+
+["Compiler" Settings: "Debug"]
+Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28
+
+["Compiler" Settings: "Release"]
+Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\adc_soc\Release" -d"LARGE_MODEL" -ml -v28
+
+["DspBiosBuilder" Settings: "Debug"]
+Options=-v28
+
+["DspBiosBuilder" Settings: "Release"]
+Options=-v28
+
+["Linker" Settings: "Debug"]
+Options=-q -c -ecode_start -m".\Debug\Example_2833xAdcSoc.map" -o".\Debug\Example_2833xAdcSoc.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib"
+
+["Linker" Settings: "Release"]
+Options=-q -c -o".\Release\Example_2833xAdcSoc.out" -x
+

Source/External/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.c

@@ -0,0 +1,189 @@
+// TI File $Revision: /main/14 $
+// Checkin $Date: April 21, 2008   15:41:07 $
+//###########################################################################
+//
+// FILE:    Example_2833xCpuTimer.c
+//
+// TITLE:   DSP2833x Device Getting Started Program.
+//
+// ASSUMPTIONS:
+//
+//    This program requires the DSP2833x header files.
+//
+//    Other then boot mode configuration, no other hardware configuration
+//    is required.
+//
+//
+//    As supplied, this project is configured for "boot to SARAM"
+//    operation.  The 2833x Boot Mode table is shown below.
+//    For information on configuring the boot mode of an eZdsp,
+//    please refer to the documentation included with the eZdsp,
+//
+//       $Boot_Table:
+//
+//         GPIO87   GPIO86     GPIO85   GPIO84
+//          XA15     XA14       XA13     XA12
+//           PU       PU         PU       PU
+//        ==========================================
+//            1        1          1        1    Jump to Flash
+//            1        1          1        0    SCI-A boot
+//            1        1          0        1    SPI-A boot
+//            1        1          0        0    I2C-A boot
+//            1        0          1        1    eCAN-A boot
+//            1        0          1        0    McBSP-A boot
+//            1        0          0        1    Jump to XINTF x16
+//            1        0          0        0    Jump to XINTF x32
+//            0        1          1        1    Jump to OTP
+//            0        1          1        0    Parallel GPIO I/O boot
+//            0        1          0        1    Parallel XINTF boot
+//            0        1          0        0    Jump to SARAM	    <- "boot to SARAM"
+//            0        0          1        1    Branch to check boot mode
+//            0        0          1        0    Boot to flash, bypass ADC cal
+//            0        0          0        1    Boot to SARAM, bypass ADC cal
+//            0        0          0        0    Boot to SCI-A, bypass ADC cal
+//                                              Boot_Table_End$
+//
+// DESCRIPTION:
+//
+//    This example configures CPU Timer0, 1, and 2 and increments
+//    a counter each time the timers assert an interrupt.
+//
+//       Watch Variables:
+//          CpuTimer0.InterruptCount
+//          CpuTimer1.InterruptCount
+//          CpuTimer2.InterruptCount
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+
+
+#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
+
+// Prototype statements for functions found within this file.
+interrupt void cpu_timer0_isr(void);
+interrupt void cpu_timer1_isr(void);
+interrupt void cpu_timer2_isr(void);
+
+void main(void)
+{
+
+// Step 1. Initialize System Control:
+// PLL, WatchDog, enable Peripheral Clocks
+// This example function is found in the DSP2833x_SysCtrl.c file.
+   InitSysCtrl();
+
+// Step 2. Initalize GPIO:
+// This example function is found in the DSP2833x_Gpio.c file and
+// illustrates how to set the GPIO to it's default state.
+// InitGpio();  // Skipped for this example
+
+
+// Step 3. Clear all interrupts and initialize PIE vector table:
+// Disable CPU interrupts
+   DINT;
+
+// Initialize the PIE control registers to their default state.
+// The default state is all PIE interrupts disabled and flags
+// are cleared.
+// This function is found in the DSP2833x_PieCtrl.c file.
+   InitPieCtrl();
+
+// Disable CPU interrupts and clear all CPU interrupt flags:
+   IER = 0x0000;
+   IFR = 0x0000;
+
+// Initialize the PIE vector table with pointers to the shell Interrupt
+// Service Routines (ISR).
+// This will populate the entire table, even if the interrupt
+// is not used in this example.  This is useful for debug purposes.
+// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
+// This function is found in DSP2833x_PieVect.c.
+   InitPieVectTable();
+
+// Interrupts that are used in this example are re-mapped to
+// ISR functions found within this file.
+   EALLOW;  // This is needed to write to EALLOW protected registers
+   PieVectTable.TINT0 = &cpu_timer0_isr;
+   PieVectTable.XINT13 = &cpu_timer1_isr;
+   PieVectTable.TINT2 = &cpu_timer2_isr;
+   EDIS;    // This is needed to disable write to EALLOW protected registers
+
+// Step 4. Initialize the Device Peripheral. This function can be
+//         found in DSP2833x_CpuTimers.c
+   InitCpuTimers();   // For this example, only initialize the Cpu Timers
+
+#if (CPU_FRQ_150MHZ)
+// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
+// 150MHz CPU Freq, 1 second Period (in uSeconds)
+
+   ConfigCpuTimer(&CpuTimer0, 150, 1000000);
+   ConfigCpuTimer(&CpuTimer1, 150, 1000000);
+   ConfigCpuTimer(&CpuTimer2, 150, 1000000);
+#endif
+
+#if (CPU_FRQ_100MHZ)
+// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
+// 100MHz CPU Freq, 1 second Period (in uSeconds)
+
+   ConfigCpuTimer(&CpuTimer0, 100, 1000000);
+   ConfigCpuTimer(&CpuTimer1, 100, 1000000);
+   ConfigCpuTimer(&CpuTimer2, 100, 1000000);
+#endif
+// To ensure precise timing, use write-only instructions to write to the entire register. Therefore, if any
+// of the configuration bits are changed in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h), the
+// below settings must also be updated.
+
+   CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
+   CpuTimer1Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
+   CpuTimer2Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
+
+// Step 5. User specific code, enable interrupts:
+
+
+// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
+// which is connected to CPU-Timer 1, and CPU int 14, which is connected
+// to CPU-Timer 2:
+   IER |= M_INT1;
+   IER |= M_INT13;
+   IER |= M_INT14;
+
+// Enable TINT0 in the PIE: Group 1 interrupt 7
+   PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
+
+// Enable global Interrupts and higher priority real-time debug events:
+   EINT;   // Enable Global interrupt INTM
+   ERTM;   // Enable Global realtime interrupt DBGM
+
+// Step 6. IDLE loop. Just sit and loop forever (optional):
+   for(;;);
+
+}
+
+
+interrupt void cpu_timer0_isr(void)
+{
+   CpuTimer0.InterruptCount++;
+
+   // Acknowledge this interrupt to receive more interrupts from group 1
+   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
+}
+
+interrupt void cpu_timer1_isr(void)
+{
+   CpuTimer1.InterruptCount++;
+   // The CPU acknowledges the interrupt.
+   EDIS;
+}
+
+interrupt void cpu_timer2_isr(void)
+{  EALLOW;
+   CpuTimer2.InterruptCount++;
+   // The CPU acknowledges the interrupt.
+   EDIS;
+}
+
+//===========================================================================
+// No more.
+//===========================================================================

Source/External/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.gel

@@ -0,0 +1,43 @@
+/*
+// TI File $Revision: /main/6 $
+// Checkin $Date: August 9, 2007   17:12:13 $
+//###########################################################################
+//
+// This .gel file can be used to help load and build the example project.
+// It should be unloaded from Code Composer Studio before loading another 
+// project. 
+//
+//###########################################################################
+// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
+// $Release Date: August 1, 2008 $
+//###########################################################################
+*/
+
+menuitem "DSP2833x CpuTimerExample"
+
+hotmenu Load_and_Build_Project()
+{
+   GEL_ProjectLoad("Example_2833xCpuTimer.pjt");
+   GEL_ProjectBuild("Example_2833xCpuTimer.pjt");
+   Setup_WatchWindow();
+}
+
+hotmenu Load_Code()
+{
+   GEL_Load(".\\debug\\Example_2833xCpuTimer.out");
+   Setup_WatchWindow();
+}
+
+hotmenu Setup_WatchWindow()
+{
+   GEL_WatchReset();
+   GEL_WatchAdd("CpuTimer0.InterruptCount",,"CPU ISR Count");
+   GEL_WatchAdd("CpuTimer0",,"CPU Timer Variables");
+   GEL_WatchAdd("CpuTimer0Regs,x");
+   GEL_WatchAdd("CpuTimer1.InterruptCount",,"CPU ISR Count");
+   GEL_WatchAdd("CpuTimer1",,"CPU Timer Variables");
+   GEL_WatchAdd("CpuTimer1Regs,x");
+   GEL_WatchAdd("CpuTimer2.InterruptCount",,"CPU ISR Count");
+   GEL_WatchAdd("CpuTimer2",,"CPU Timer Variables");
+   GEL_WatchAdd("CpuTimer2Regs,x");
+}

Source/External/v120/DSP2833x_examples/cpu_timer/Example_2833xCpuTimer.pjt

@@ -0,0 +1,46 @@
+; Code Composer Project File, Version 2.0 (do not modify or remove this line)
+
+[Project Settings]
+ProjectName="DSP2833x"
+ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\"
+ProjectType=Executable
+CPUFamily=TMS320C28XX
+Tool="Compiler"
+Tool="CustomBuilder"
+Tool="DspBiosBuilder"
+Tool="Linker"
+Config="Debug"
+Config="Release"
+
+[Source Files]
+Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
+Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm"
+Source="..\..\DSP2833x_common\source\DSP2833x_CpuTimers.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c"
+Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm"
+Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
+Source="Example_2833xCpuTimer.c"
+Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd"
+Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
+
+["Compiler" Settings: "Debug"]
+Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28
+
+["Compiler" Settings: "Release"]
+Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\cpu_timer\Release" -d"LARGE_MODEL" -ml -v28
+
+["DspBiosBuilder" Settings: "Debug"]
+Options=-v28
+
+["DspBiosBuilder" Settings: "Release"]
+Options=-v28
+
+["Linker" Settings: "Debug"]
+Options=-q -c -ecode_start -m".\Debug\Example_2833xCpuTimer.map" -o".\Debug\Example_2833xCpuTimer.out" -stack0x200 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib"
+
+["Linker" Settings: "Release"]
+Options=-q -c -o".\Release\Example_2833xCpuTimer.out" -x
+