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beef10a15b
altera/MainController/MainController.bdf
sokolovstanislav beef10a15b В описании предыдущего коммита ошибка: память определялась как синхронная. 
Увеличили размерность памяти 8х32. Со стороны контроллера ввели ножки nBL. Это выбор байта (от 0 до 3) в ячейки памяти. Добавили описание блока памяти. После синтеза, который стал занимать намного больше времени, блок памяти перестал определятся как синхронная память. Данные по загрузке ПЛИС:
Total logic elements    10,706 / 24,624 ( 43 % )
Total combinational functions  6,603 / 24,624 ( 27 % )
Dedicated logic registers  8,249 / 24,624 ( 33 % )
Total registers    8249
Total pins    25 / 149 ( 17 % )
Total PLLs    1 / 4 ( 25 % )
2024-03-14 11:27:47 +03:00

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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