library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
  
entity RAM9X8 is		
	port(
		clk : in std_logic;
		
		data : inout std_logic_vector(7 downto 0);
		address : in std_logic_vector(8 downto 0);
		we : in std_logic;
		oe : in std_logic;
		ce : in std_logic		
	);
end entity;

architecture behavorial of RAM9X8 is

type mem is array (511 downto 0) of std_logic_vector(7 downto 0);
signal memory : mem;

signal wePrev : std_logic := '0';
signal oePrev : std_logic := '0';
signal cePrev : std_logic := '0';

type MemoryMachine is (Waiting, Starting, Writing, Reading);
signal stateMM : MemoryMachine := Waiting;

begin	

	process(clk)
		variable addr : integer range 0 to 511 := 0;
	begin
		if rising_edge(clk) then
			case stateMM is
				when Waiting => 
					if ce = '0' and cePrev = '1' then
						stateMM <= Starting;
					else
						data <= (others => 'Z');
					end if;
				when Starting => 
					addr := conv_integer(address);
					if oe = '0' then
						stateMM <= Reading;							
					else 
						stateMM <= Writing;
					end if;	
				when Reading =>
					data <= memory(addr);
					if oe = '1' and oePrev = '0' then
						stateMM <= Waiting;
					elsif ce = '1' then
						stateMM <= Waiting;
					end if;					
				when Writing =>
					if we = '0' and wePrev = '1' then
						memory(addr) <= data;
						stateMM <= Waiting;
					elsif ce = '1' then
						stateMM <= Waiting;
					end if;					
				when others =>
			end case;
			
			oePrev <= oe;		
			cePrev <= ce;
			wePrev <= we;
			
			memory(0) <= x"AA";
			memory(1) <= x"BB";
			memory(2) <= x"CC";
			memory(3) <= x"DD";
			memory(4) <= x"EE";
			memory(5) <= x"FF";
			memory(6) <= x"01";
			memory(7) <= x"23";
			memory(8) <= x"45";
			memory(9) <= memory(9) + 1;
		end if;
	end process;
	
end behavorial;