library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
  
entity RAM9X8 is		
	port(
		-- clk : in std_logic;
		
		data : inout std_logic_vector(7 downto 0);
		address : in std_logic_vector(8 downto 0);
		we : in std_logic;
		oe : in std_logic;
		ce : in std_logic	
	);
end entity;

architecture behavorial of RAM9X8 is

type mem is array (511 downto 0) of std_logic_vector(7 downto 0);
signal memory : mem;

--signal cePrev : std_logic := '0';

--type MemoryMachine is (Waiting, ReadingAddress, WritingData, ReadingData);
--signal stateMM : MemoryMachine := Waiting;

begin
	
--	process (CLK_FPGA, nCS, nOE, bWE, A)
--   begin
--		-- Фильтрация и синхронизация сигналов от процессора
--		if rising_edge(CLK_FPGA) then
--			-- Пример фильтрации сигналов nCS, nOE и bWE
--         filtered_we <= we;
--         filtered_oe <= oe;
--         filtered_ce <= ce;
--
--			-- Пример фильтрации и синхронизации сигнала адреса A
--			--filtered_A <= A;
--		end if;
--   end process;
--	
	process (we, oe, ce, address)
		variable addr : integer range 0 to 511 := 0;
	begin
		if (ce = '0') then  -- Если микросхема выбрана
			if (oe = '0') then  -- Если сигнал чтения активен
				addr := conv_integer(address);
				case addr is
					when 0 => data <= x"AA";
					when 1 => data <= x"BB";
					when 2 => data <= x"CC";
					when 3 => data <= x"DD";
					when 4 => data <= x"EE";
					when 5 => data <= x"FF";
					when 6 => data <= x"01";
					when 7 => data <= x"23";
					when 8 => data <= x"45";
					when 9 => data <= x"67";
					when others => data <= (others => 'Z');  -- Для остальных адресов разрешить чтение
				end case;				
			elsif (we = '0') then  -- Если сигнал записи активен
				addr := conv_integer(address);
				memory(addr) <= data;
			else
				data <= (others => 'Z');  -- Запретить запись на шину
			end if;
		else
			data <= (others => 'Z');  -- Запретить запись на шину
		end if;
	end process;

--	process(clk)
--		variable addr : integer range 0 to 511 := 0;
--	begin
--		if rising_edge(clk) then
--			case stateMM is
--				when Waiting => 
--					if ce = '0' and cePrev = '1' then
--						stateMM <= ReadingAddress;
--					end if;
--					data <= (others => 'Z');
--				when ReadingAddress =>
--					addr := conv_integer(address);
--					if oe = '0' then
--						stateMM <= ReadingData;
--						data <= (others => '0');
--					elsif we = '0' then
--						stateMM <= WritingData;
--					elsif ce = '1' then
--						stateMM <= Waiting;
--					end if;
--				when ReadingData =>
--					data <= memory(addr);
--					if ce = '1' then
--						stateMM <= Waiting;
--					end if;				
--				when WritingData =>
--					memory(addr) <= data;
--					stateMM <= Waiting;					
--				when others =>
--			end case;			
--			memory(0) <= x"AA";
--			memory(1) <= x"BB";
--			memory(2) <= x"CC";
--			memory(3) <= x"DD";
--			memory(4) <= x"EE";
--			memory(5) <= x"FF";
--			memory(6) <= x"01";
--			memory(7) <= x"23";
--			memory(8) <= x"45";
--			memory(9) <= memory(9) + 1;
--		end if;
--	end process;
	
end behavorial;