library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity RAM is
	port(
		clk : in std_logic;
		data : in std_logic_vector(15 downto 0);
		address : in std_logic_vector(7 downto 0);
		clkMCU : in std_logic;
		dataMCU : inout std_logic_vector(15 downto 0);
		addressMCU : inout std_logic_vector(7 downto 0);
		-- write when 0, read when 1
		wr : in std_logic
	);
end entity;

architecture behavorial of RAM is

type mem is array (255 downto 0) of std_logic_vector(15 downto 0);
signal memory : mem;

signal clkMCUPrev : std_logic := '0';

begin

	process(clk)
		variable addr : integer range 0 to 255;
	begin
		if rising_edge(clk) then
			if clkMCU = '1' and clkMCUPrev = '0' then
				addr := conv_integer(addressMCU); -- переменной addr присваивается новое значение сразу. Удобно для преобразования типов.
				if (wr = '0') then
					memory(addr) <= dataMCU; -- тут уже новое значение переменной addr
				else
					dataMCU <= memory(addr);
				end if;
			end if;
			clkMCUPrev <= clkMCU;
		end if;
	end process;
	
end behavorial;