From f3a7b565e424af1cae151df09f5e7d8cacb71470 Mon Sep 17 00:00:00 2001 From: sokolovstanislav Date: Tue, 19 Mar 2024 18:39:41 +0300 Subject: [PATCH] =?UTF-8?q?=D0=92=D0=B2=D0=B5=D0=BB=D0=B8=20=D1=84=D0=B0?= =?UTF-8?q?=D0=B7=D0=BE=D0=B2=D1=8B=D0=B9=20=D1=81=D0=B4=D0=B2=D0=B8=D0=B3?= =?UTF-8?q?=20=D0=BD=D0=B0=204=20=D1=82=D0=B0=D0=BA=D1=82=D0=B0=20=D0=B4?= =?UTF-8?q?=D0=BB=D1=8F=20=D1=81=D0=B8=D0=B3=D0=BD=D0=B0=D0=BB=D0=B0=20WE,?= =?UTF-8?q?=20=D1=82=D0=B0=D0=BA=20=D0=BA=D0=B0=D0=BA=20=D0=B2=20=D1=80?= =?UTF-8?q?=D0=B5=D0=B6=D0=B8=D0=BC=D0=B5=20=D0=B7=D0=B0=D0=BF=D0=B8=D1=81?= =?UTF-8?q?=D0=B8=20=D0=BD=D0=B5=20=D1=83=D1=81=D0=BF=D0=B5=D0=B2=D0=B0?= =?UTF-8?q?=D0=BB=D0=B8=20=D0=B2=D1=8B=D1=81=D1=82=D0=B0=D0=B2=D0=BB=D1=8F?= =?UTF-8?q?=D1=82=D1=8C=D1=81=D1=8F=20=D0=B4=D0=B0=D0=BD=D0=BD=D1=8B=D0=B5?= =?UTF-8?q?=20=D0=BD=D0=B0=20=D1=88=D0=B8=D0=BD=D1=83=20=D0=B4=D0=B0=D0=BD?= =?UTF-8?q?=D0=BD=D1=8B=D1=85=20=D0=B8=20=D0=9F=D0=9B=D0=98=D0=A1=20=D0=B7?= =?UTF-8?q?=D0=B0=D1=87=D0=B8=D1=82=D1=8B=D0=B2=D0=B0=D0=BB=D0=B0=20=D0=BD?= =?UTF-8?q?=D1=83=D0=BB=D0=B8=20=D0=BF=D0=BE=20=D0=B2=D1=81=D0=B5=D0=BC=20?= =?UTF-8?q?=D0=B1=D0=B8=D1=82=D0=B0=D0=BC.=20=D0=AD=D1=82=D0=BE=20=D0=BF?= =?UTF-8?q?=D0=BE=D0=BC=D0=BE=D0=B3=D0=BB=D0=BE=20=D1=81=D1=82=D0=B0=D0=B1?= =?UTF-8?q?=D0=B8=D0=BB=D0=B8=D0=B7=D0=B8=D1=80=D0=BE=D0=B2=D0=B0=D1=82?= =?UTF-8?q?=D1=8C=20=D0=B7=D0=B0=D0=BF=D0=B8=D1=81=D1=8C.=20=D0=A7=D1=82?= =?UTF-8?q?=D0=B5=D0=BD=D0=B8=D0=B5=20=D1=80=D0=B0=D0=B1=D0=BE=D1=82=D0=B0?= =?UTF-8?q?=D0=B5=D1=82=20=D1=85=D0=BE=D1=80=D0=BE=D1=88=D0=BE.=20=D0=9F?= =?UTF-8?q?=D0=BE=D0=BB=D0=BD=D1=8B=D0=B9=20=D1=86=D0=B8=D0=BA=D0=BB=20?= =?UTF-8?q?=D0=B7=D0=B0=D0=BF=D0=B8=D1=81=D0=B8=20=D0=B8=D0=BB=D0=B8=20?= =?UTF-8?q?=D1=87=D1=82=D0=B5=D0=BD=D0=B8=D1=8F=20=D0=B1=D0=B2=D1=83=D1=85?= =?UTF-8?q?=20=D0=B1=D0=B0=D0=B9=D1=82=20=D1=80=D0=B0=D0=B2=D0=B5=D0=BD=20?= =?UTF-8?q?=D0=BF=D1=80=D0=B8=D0=BC=D0=B5=D1=80=D0=BD=D0=BE=20200=D0=BD?= =?UTF-8?q?=D1=81.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- MainController/DigitalFilter3.bsf | 50 ++++++ MainController/DigitalFilter3.vhd | 48 ++++++ MainController/DigitalFilterBlock.bdf | 14 +- MainController/MainController.bdf | 195 ++++++++++++---------- MainController/MainController.qsf | 4 +- MainController/RAM9X8.vhd | 97 ++--------- MainController/RAM9X8_SerialBusMaster.vhd | 87 ++++------ 7 files changed, 262 insertions(+), 233 deletions(-) create mode 100644 MainController/DigitalFilter3.bsf create mode 100644 MainController/DigitalFilter3.vhd diff --git a/MainController/DigitalFilter3.bsf b/MainController/DigitalFilter3.bsf new file mode 100644 index 0000000..6812dc2 --- /dev/null +++ b/MainController/DigitalFilter3.bsf @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 160 96) + (text "DigitalFilter3" (rect 5 0 51 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "input" (rect 0 0 17 12)(font "Arial" )) + (text "input" (rect 21 43 38 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 32) + (output) + (text "output" (rect 0 0 23 12)(font "Arial" )) + (text "output" (rect 100 27 123 39)(font "Arial" )) + (line (pt 144 32)(pt 128 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 128 64)(line_width 1)) + ) +) diff --git a/MainController/DigitalFilter3.vhd b/MainController/DigitalFilter3.vhd new file mode 100644 index 0000000..0404635 --- /dev/null +++ b/MainController/DigitalFilter3.vhd @@ -0,0 +1,48 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity DigitalFilter3 is + port( + clk : in STD_LOGIC; + input : in STD_LOGIC; + output : out STD_LOGIC + ); +end DigitalFilter3; + +architecture Behavioral of DigitalFilter3 is + signal count : natural range 0 to 3 := 0; + signal latch : std_logic := '0'; +begin + + process(clk) + begin + if rising_edge(clk) then + if input = '1' then + if latch = '0' then + latch <= '1'; + count <= 0; + else + if count < 3 then + count <= count + 1; + else + output <= '1'; + count <= 0; + end if; + end if; + else + if latch = '1' then + latch <= '0'; + count <= 0; + else + if count < 3 then + count <= count + 1; + else + output <= '0'; + count <= 0; + end if; + end if; + end if; + end if; + end process; + +end Behavioral; \ No newline at end of file diff --git a/MainController/DigitalFilterBlock.bdf b/MainController/DigitalFilterBlock.bdf index f483296..d1df107 100644 --- a/MainController/DigitalFilterBlock.bdf +++ b/MainController/DigitalFilterBlock.bdf @@ -23,7 +23,7 @@ applicable agreement for further details. (input) (rect 416 -80 584 -64) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) - (text "clk" (rect 5 0 20 12)(font "Arial" )) + (text "clk" (rect 5 0 19 12)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -39,7 +39,7 @@ applicable agreement for further details. (input) (rect 416 -48 584 -32) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) - (text "cein" (rect 5 0 26 12)(font "Arial" )) + (text "cein" (rect 5 0 25 12)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -55,7 +55,7 @@ applicable agreement for further details. (input) (rect 416 40 584 56) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) - (text "oein" (rect 5 0 26 12)(font "Arial" )) + (text "oein" (rect 5 0 25 12)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -71,7 +71,7 @@ applicable agreement for further details. (input) (rect 416 128 584 144) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) - (text "wein" (rect 5 0 27 12)(font "Arial" )) + (text "wein" (rect 5 0 26 12)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -87,7 +87,7 @@ applicable agreement for further details. (input) (rect 416 216 584 232) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) - (text "addressin[8..0]" (rect 5 0 79 12)(font "Arial" )) + (text "addressin[8..0]" (rect 5 0 78 12)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -484,8 +484,8 @@ applicable agreement for further details. ) (symbol (rect 792 88 936 168) - (text "DigitalFilter2" (rect 5 0 66 12)(font "Arial" )) - (text "inst11" (rect 8 64 37 76)(font "Arial" )) + (text "DigitalFilter3" (rect 5 0 66 12)(font "Arial" )) + (text "inst" (rect 8 64 25 76)(font "Arial" )) (port (pt 0 32) (input) diff --git a/MainController/MainController.bdf b/MainController/MainController.bdf index 4893a3a..2bae05e 100644 --- a/MainController/MainController.bdf +++ b/MainController/MainController.bdf @@ -327,7 +327,7 @@ applicable agreement for further details. (symbol (rect 704 208 936 336) (text "DigitalFilterBlock" (rect 5 0 95 14)(font "Arial" (font_size 8))) - (text "inst7" (rect 8 112 31 124)(font "Arial" )) + (text "inst12" (rect 8 112 37 124)(font "Arial" )) (port (pt 0 32) (input) @@ -395,10 +395,53 @@ applicable agreement for further details. (rectangle (rect 16 16 216 112)) ) ) +(symbol + (rect 1040 256 1232 368) + (text "RAM9X8" (rect 5 0 46 12)(font "Arial" )) + (text "inst13" (rect 8 96 37 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "address[8..0]" (rect 0 0 64 12)(font "Arial" )) + (text "address[8..0]" (rect 21 27 85 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "we" (rect 0 0 12 12)(font "Arial" )) + (text "we" (rect 21 43 33 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "oe" (rect 0 0 11 12)(font "Arial" )) + (text "oe" (rect 21 59 32 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 0 80) + (input) + (text "ce" (rect 0 0 11 12)(font "Arial" )) + (text "ce" (rect 21 75 32 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)) + ) + (port + (pt 192 32) + (bidir) + (text "data[7..0]" (rect 0 0 47 12)(font "Arial" )) + (text "data[7..0]" (rect 135 27 182 39)(font "Arial" )) + (line (pt 192 32)(pt 176 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 176 96)) + ) +) (symbol (rect 1040 544 1368 688) (text "RAM9X8_SerialBusMaster" (rect 5 0 131 12)(font "Arial" )) - (text "inst11" (rect 8 128 37 140)(font "Arial" )) + (text "inst4" (rect 8 128 31 140)(font "Arial" )) (port (pt 0 32) (input) @@ -495,50 +538,7 @@ applicable agreement for further details. (drawing (rectangle (rect 16 16 312 128)) ) - (annotation_block (parameter)(rect 1056 688 1352 792)) -) -(symbol - (rect 1040 256 1232 368) - (text "RAM9X8" (rect 5 0 46 12)(font "Arial" )) - (text "inst3" (rect 8 96 31 108)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "address[8..0]" (rect 0 0 64 12)(font "Arial" )) - (text "address[8..0]" (rect 21 27 85 39)(font "Arial" )) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "we" (rect 0 0 12 12)(font "Arial" )) - (text "we" (rect 21 43 33 55)(font "Arial" )) - (line (pt 0 48)(pt 16 48)) - ) - (port - (pt 0 64) - (input) - (text "oe" (rect 0 0 11 12)(font "Arial" )) - (text "oe" (rect 21 59 32 71)(font "Arial" )) - (line (pt 0 64)(pt 16 64)) - ) - (port - (pt 0 80) - (input) - (text "ce" (rect 0 0 11 12)(font "Arial" )) - (text "ce" (rect 21 75 32 87)(font "Arial" )) - (line (pt 0 80)(pt 16 80)) - ) - (port - (pt 192 32) - (bidir) - (text "data[7..0]" (rect 0 0 47 12)(font "Arial" )) - (text "data[7..0]" (rect 135 27 182 39)(font "Arial" )) - (line (pt 192 32)(pt 176 32)(line_width 3)) - ) - (drawing - (rectangle (rect 16 16 176 96)) - ) + (annotation_block (parameter)(rect 1040 432 1333 530)) ) (connector (pt 560 32) @@ -577,10 +577,6 @@ applicable agreement for further details. (pt 544 304) (bus) ) -(connector - (pt 608 32) - (pt 608 136) -) (connector (pt 1040 336) (pt 952 336) @@ -652,59 +648,86 @@ applicable agreement for further details. (pt 704 240) (pt 680 240) ) -(connector - (pt 680 240) - (pt 680 576) -) -(connector - (pt 680 576) - (pt 1016 576) -) (connector (pt 544 408) (pt 1440 408) (bus) ) -(connector - (pt 952 32) - (pt 1336 32) -) -(connector - (pt 952 32) - (pt 952 240) -) (connector (pt 952 240) (pt 952 336) ) -(connector - (pt 968 136) - (pt 1336 136) -) -(connector - (pt 968 136) - (pt 968 256) -) (connector (pt 968 256) (pt 968 320) ) (connector - (pt 856 120) - (pt 1016 120) -) -(connector - (pt 1016 120) - (pt 1016 576) -) -(connector - (pt 1440 408) + (pt 1232 288) (pt 1440 288) (bus) ) (connector - (pt 1232 288) + (pt 680 240) + (pt 680 -16) +) +(connector + (pt 680 -16) + (pt 936 -16) +) +(connector + (pt 824 32) + (pt 1336 32) +) +(connector + (pt 856 120) + (pt 936 120) +) +(connector + (pt 936 -16) + (pt 936 120) +) +(connector + (pt 608 32) + (pt 608 136) +) +(connector + (pt 1040 576) + (pt 608 576) +) +(connector + (pt 608 136) + (pt 608 576) +) +(connector + (pt 1000 592) + (pt 1040 592) + (bus) +) +(connector + (pt 1040 608) + (pt 984 608) +) +(connector + (pt 1040 624) + (pt 968 624) +) +(connector + (pt 1040 640) + (pt 952 640) +) +(connector + (pt 1368 576) + (pt 1440 576) + (bus) +) +(connector (pt 1440 288) + (pt 1440 408) + (bus) +) +(connector + (pt 1440 408) + (pt 1440 576) (bus) ) (junction (pt 608 32)) @@ -712,5 +735,5 @@ applicable agreement for further details. (junction (pt 984 304)) (junction (pt 968 320)) (junction (pt 952 336)) -(junction (pt 952 240)) -(junction (pt 968 256)) +(junction (pt 608 136)) +(junction (pt 1440 408)) diff --git a/MainController/MainController.qsf b/MainController/MainController.qsf index 243531c..4d0863d 100644 --- a/MainController/MainController.qsf +++ b/MainController/MainController.qsf @@ -120,4 +120,6 @@ set_location_assignment PIN_18 -to SBclk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBclk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdatain set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBdataout -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name VHDL_FILE DigitalFilter3.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[8] \ No newline at end of file diff --git a/MainController/RAM9X8.vhd b/MainController/RAM9X8.vhd index 0f04ab4..7a0702b 100644 --- a/MainController/RAM9X8.vhd +++ b/MainController/RAM9X8.vhd @@ -4,63 +4,41 @@ use ieee.std_logic_unsigned.all; entity RAM9X8 is port( - -- clk : in std_logic; - data : inout std_logic_vector(7 downto 0); address : in std_logic_vector(8 downto 0); we : in std_logic; oe : in std_logic; - ce : in std_logic + ce : in std_logic ); end entity; architecture behavorial of RAM9X8 is type mem is array (511 downto 0) of std_logic_vector(7 downto 0); -signal memory : mem; - ---signal cePrev : std_logic := '0'; - ---type MemoryMachine is (Waiting, ReadingAddress, WritingData, ReadingData); ---signal stateMM : MemoryMachine := Waiting; +signal memory : mem; begin --- process (CLK_FPGA, nCS, nOE, bWE, A) --- begin --- -- Фильтрация и синхронизация сигналов от процессора --- if rising_edge(CLK_FPGA) then --- -- Пример фильтрации сигналов nCS, nOE и bWE --- filtered_we <= we; --- filtered_oe <= oe; --- filtered_ce <= ce; --- --- -- Пример фильтрации и синхронизации сигнала адреса A --- --filtered_A <= A; --- end if; --- end process; --- - process (we, oe, ce, address) + process (we, oe, ce) variable addr : integer range 0 to 511 := 0; begin if (ce = '0') then -- Если микросхема выбрана - if (oe = '0') then -- Если сигнал чтения активен - addr := conv_integer(address); + addr := conv_integer(address); + if (oe = '0') then -- Если сигнал чтения активен case addr is when 0 => data <= x"AA"; - when 1 => data <= x"BB"; - when 2 => data <= x"CC"; - when 3 => data <= x"DD"; - when 4 => data <= x"EE"; - when 5 => data <= x"FF"; - when 6 => data <= x"01"; - when 7 => data <= x"23"; - when 8 => data <= x"45"; - when 9 => data <= x"67"; - when others => data <= (others => 'Z'); -- Для остальных адресов разрешить чтение - end case; + when 1 => data <= x"BB"; + when 2 => data <= x"CC"; + when 3 => data <= x"DD"; + when 4 => data <= x"EE"; + when 5 => data <= x"FF"; + when 6 => data <= x"01"; + when 7 => data <= x"23"; + when 8 => data <= x"45"; + when 9 => data <= x"67"; + when others => data <= not memory(addr); + end case; elsif (we = '0') then -- Если сигнал записи активен - addr := conv_integer(address); memory(addr) <= data; else data <= (others => 'Z'); -- Запретить запись на шину @@ -69,48 +47,5 @@ begin data <= (others => 'Z'); -- Запретить запись на шину end if; end process; - --- process(clk) --- variable addr : integer range 0 to 511 := 0; --- begin --- if rising_edge(clk) then --- case stateMM is --- when Waiting => --- if ce = '0' and cePrev = '1' then --- stateMM <= ReadingAddress; --- end if; --- data <= (others => 'Z'); --- when ReadingAddress => --- addr := conv_integer(address); --- if oe = '0' then --- stateMM <= ReadingData; --- data <= (others => '0'); --- elsif we = '0' then --- stateMM <= WritingData; --- elsif ce = '1' then --- stateMM <= Waiting; --- end if; --- when ReadingData => --- data <= memory(addr); --- if ce = '1' then --- stateMM <= Waiting; --- end if; --- when WritingData => --- memory(addr) <= data; --- stateMM <= Waiting; --- when others => --- end case; --- memory(0) <= x"AA"; --- memory(1) <= x"BB"; --- memory(2) <= x"CC"; --- memory(3) <= x"DD"; --- memory(4) <= x"EE"; --- memory(5) <= x"FF"; --- memory(6) <= x"01"; --- memory(7) <= x"23"; --- memory(8) <= x"45"; --- memory(9) <= memory(9) + 1; --- end if; --- end process; end behavorial; \ No newline at end of file diff --git a/MainController/RAM9X8_SerialBusMaster.vhd b/MainController/RAM9X8_SerialBusMaster.vhd index 99e79ed..97262d4 100644 --- a/MainController/RAM9X8_SerialBusMaster.vhd +++ b/MainController/RAM9X8_SerialBusMaster.vhd @@ -30,16 +30,6 @@ end entity; architecture behavorial of RAM9X8_SerialBusMaster is -type mem is array (511 downto 0) of std_logic_vector(DATA_BUS_WIDTH - 1 downto 0); -signal memory : mem; - -signal wePrev : std_logic := '0'; -signal oePrev : std_logic := '0'; -signal cePrev : std_logic := '0'; - -type MemoryMachine is (Waiting, Writing, Reading); -signal stateMM : MemoryMachine := Waiting; - signal dataBufIn : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); signal dataBufOut : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); signal cmdBuf : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downto 0); @@ -64,26 +54,13 @@ signal startPrev : std_logic := '0'; begin - process(clk) + process (we, oe, ce) variable addr : integer range 0 to 511 := 0; begin - if rising_edge(clk) then - case stateMM is - when Waiting => - if ce = '0' and cePrev = '1' then - addr := conv_integer(address); - if (addr = REG_ADDR_DATA_UPPER_BYTE or addr = REG_ADDR_DATA_LOWER_BYTE or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE) then - if oe = '0' then - stateMM <= Reading; - else - stateMM <= Writing; - end if; - end if; - else - start <= '0'; - data <= (others => 'Z'); - end if; - when Reading => + if (ce = '0') then -- Если микросхема выбрана + addr := conv_integer(address); + if (addr = REG_ADDR_DATA_UPPER_BYTE or addr = REG_ADDR_DATA_LOWER_BYTE or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE) then + if (oe = '0') then -- Если сигнал чтения активен case addr is when REG_ADDR_DATA_UPPER_BYTE => data <= dataBufOut(15 downto 8); @@ -93,37 +70,31 @@ begin data <= cmdBuf(15 downto 8); when REG_ADDR_CMD_LOWER_BYTE => data <= cmdBuf(7 downto 0); + when others => + data <= (others => 'Z'); -- Запретить запись на шину + end case; + elsif (we = '0') then -- Если сигнал записи активен + case addr is + when REG_ADDR_DATA_UPPER_BYTE => + dataBufIn(15 downto 8) <= data; + when REG_ADDR_DATA_LOWER_BYTE => + dataBufIn(7 downto 0) <= data; + when REG_ADDR_CMD_UPPER_BYTE => + cmdBuf(15 downto 8) <= data; + when REG_ADDR_CMD_LOWER_BYTE => + cmdBuf(7 downto 0) <= data; + start <= '1'; when others => - end case; - if oe = '1' and oePrev = '0' then - stateMM <= Waiting; - elsif ce = '1' then - stateMM <= Waiting; - end if; - when Writing => - if we = '0' and wePrev = '1' then - case addr is - when REG_ADDR_DATA_UPPER_BYTE => - dataBufIn(15 downto 8) <= data; - when REG_ADDR_DATA_LOWER_BYTE => - dataBufIn(7 downto 0) <= data; - when REG_ADDR_CMD_UPPER_BYTE => - cmdBuf(15 downto 8) <= data; - when REG_ADDR_CMD_LOWER_BYTE => - cmdBuf(7 downto 0) <= data; - start <= '1'; - when others => - end case; - stateMM <= Waiting; - elsif ce = '1' then - stateMM <= Waiting; - end if; - when others => - end case; - - oePrev <= oe; - cePrev <= ce; - wePrev <= we; + data <= (others => 'Z'); -- Запретить запись на шину + end case; + else + data <= (others => 'Z'); -- Запретить запись на шину + end if; + else + data <= (others => 'Z'); -- Запретить запись на шину + end if; + else + data <= (others => 'Z'); -- Запретить запись на шину end if; end process;