diff --git a/MainController/DigitalFilter2.bsf b/MainController/DigitalFilter2.bsf
new file mode 100644
index 0000000..1292581
--- /dev/null
+++ b/MainController/DigitalFilter2.bsf
@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 160 96)
+	(text "DigitalFilter2" (rect 5 0 51 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input" (rect 0 0 17 12)(font "Arial" ))
+		(text "input" (rect 21 43 38 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 32)
+		(output)
+		(text "output" (rect 0 0 23 12)(font "Arial" ))
+		(text "output" (rect 100 27 123 39)(font "Arial" ))
+		(line (pt 144 32)(pt 128 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 128 64)(line_width 1))
+	)
+)
diff --git a/MainController/DigitalFilter2.vhd b/MainController/DigitalFilter2.vhd
new file mode 100644
index 0000000..f687c00
--- /dev/null
+++ b/MainController/DigitalFilter2.vhd
@@ -0,0 +1,48 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity DigitalFilter2 is
+	 port(
+		 clk : in STD_LOGIC;
+		 input : in STD_LOGIC;
+		 output : out STD_LOGIC
+	     );
+end DigitalFilter2;
+
+architecture Behavioral of DigitalFilter2 is
+	signal count : natural range 0 to 1 := 0;
+	signal latch : std_logic := '0';
+begin	
+	
+	process(clk)		
+	begin		
+		if rising_edge(clk) then 
+			if input = '1' then	
+				if latch = '0' then
+					latch <= '1';
+					count <= 0;
+				else
+					if count < 1 then 
+						count <= count + 1;
+					else 
+						output <= '1';
+						count <= 0;
+					end if;
+				end if;	
+			else
+				if latch = '1' then
+					latch <= '0';
+					count <= 0;
+				else
+					if count < 1 then 
+						count <= count + 1;
+					else 
+						output <= '0';
+						count <= 0;
+					end if;
+				end if;	
+			end if;
+		end if;
+	end process;
+	
+end Behavioral;
\ No newline at end of file
diff --git a/MainController/MainController.bdf b/MainController/MainController.bdf
index bc6e3e9..9096d09 100644
--- a/MainController/MainController.bdf
+++ b/MainController/MainController.bdf
@@ -38,7 +38,7 @@ applicable agreement for further details.
 )
 (pin
 	(input)
-	(rect 376 248 544 264)
+	(rect 376 288 544 304)
 	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
 	(text "nOE" (rect 5 0 26 12)(font "Arial" ))
 	(pt 168 8)
@@ -51,11 +51,11 @@ applicable agreement for further details.
 		(line (pt 109 12)(pt 113 8))
 	)
 	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 320 248 376 264))
+	(annotation_block (location)(rect 320 288 376 304))
 )
 (pin
 	(input)
-	(rect 376 264 544 280)
+	(rect 376 376 544 392)
 	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
 	(text "nWE" (rect 5 0 28 12)(font "Arial" ))
 	(pt 168 8)
@@ -68,11 +68,11 @@ applicable agreement for further details.
 		(line (pt 109 12)(pt 113 8))
 	)
 	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 320 264 376 280))
+	(annotation_block (location)(rect 320 376 376 392))
 )
 (pin
 	(input)
-	(rect 376 280 544 296)
+	(rect 376 464 544 480)
 	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
 	(text "nCE" (rect 5 0 26 12)(font "Arial" ))
 	(pt 168 8)
@@ -85,11 +85,11 @@ applicable agreement for further details.
 		(line (pt 109 12)(pt 113 8))
 	)
 	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 320 280 376 296))
+	(annotation_block (location)(rect 320 464 376 480))
 )
 (pin
 	(input)
-	(rect 376 296 544 312)
+	(rect 376 480 544 496)
 	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
 	(text "nBL[1..0]" (rect 5 0 49 12)(font "Arial" ))
 	(pt 168 8)
@@ -102,13 +102,13 @@ applicable agreement for further details.
 		(line (pt 109 12)(pt 113 8))
 	)
 	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 248 312 304 344))
+	(annotation_block (location)(rect 248 496 304 528))
 )
 (pin
 	(input)
 	(rect 376 216 544 232)
 	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
-	(text "Address[8..0]" (rect 5 0 72 12)(font "Arial" ))
+	(text "Address[8..0]" (rect 5 0 71 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 84 12)(pt 109 12))
@@ -259,7 +259,7 @@ applicable agreement for further details.
 (symbol
 	(rect 952 176 1144 320)
 	(text "RAM9X8" (rect 5 0 46 12)(font "Arial" ))
-	(text "inst3" (rect 8 128 31 140)(font "Arial" ))
+	(text "inst6" (rect 8 128 31 140)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
@@ -306,9 +306,109 @@ applicable agreement for further details.
 		(rectangle (rect 16 16 176 128))
 	)
 )
-(connector
-	(pt 560 256)
-	(pt 560 624)
+(symbol
+	(rect 472 136 504 168)
+	(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
+	(text "inst8" (rect 3 21 26 33)(font "Arial" )(invisible))
+	(port
+		(pt 16 0)
+		(output)
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(line (pt 16 8)(pt 16 0))
+	)
+	(drawing
+		(line (pt 8 8)(pt 16 16))
+		(line (pt 16 16)(pt 24 8))
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(symbol
+	(rect 632 248 776 328)
+	(text "DigitalFilter2" (rect 5 0 66 12)(font "Arial" ))
+	(text "inst9" (rect 8 64 31 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 27 35 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input" (rect 0 0 23 12)(font "Arial" ))
+		(text "input" (rect 21 43 44 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 144 32)
+		(output)
+		(text "output" (rect 0 0 30 12)(font "Arial" ))
+		(text "output" (rect 98 27 128 39)(font "Arial" ))
+		(line (pt 144 32)(pt 128 32))
+	)
+	(drawing
+		(rectangle (rect 16 16 128 64))
+	)
+)
+(symbol
+	(rect 632 336 776 416)
+	(text "DigitalFilter2" (rect 5 0 66 12)(font "Arial" ))
+	(text "inst10" (rect 8 64 37 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 27 35 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input" (rect 0 0 23 12)(font "Arial" ))
+		(text "input" (rect 21 43 44 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 144 32)
+		(output)
+		(text "output" (rect 0 0 30 12)(font "Arial" ))
+		(text "output" (rect 98 27 128 39)(font "Arial" ))
+		(line (pt 144 32)(pt 128 32))
+	)
+	(drawing
+		(rectangle (rect 16 16 128 64))
+	)
+)
+(symbol
+	(rect 632 424 776 504)
+	(text "DigitalFilter2" (rect 5 0 66 12)(font "Arial" ))
+	(text "inst11" (rect 8 64 37 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 27 35 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input" (rect 0 0 23 12)(font "Arial" ))
+		(text "input" (rect 21 43 44 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 144 32)
+		(output)
+		(text "output" (rect 0 0 30 12)(font "Arial" ))
+		(text "output" (rect 98 27 128 39)(font "Arial" ))
+		(line (pt 144 32)(pt 128 32))
+	)
+	(drawing
+		(rectangle (rect 16 16 128 64))
+	)
 )
 (connector
 	(pt 576 240)
@@ -368,14 +468,6 @@ applicable agreement for further details.
 	(pt 856 240)
 	(bus)
 )
-(connector
-	(pt 544 272)
-	(pt 872 272)
-)
-(connector
-	(pt 544 288)
-	(pt 888 288)
-)
 (connector
 	(pt 608 208)
 	(pt 952 208)
@@ -385,30 +477,10 @@ applicable agreement for further details.
 	(pt 1168 208)
 	(bus)
 )
-(connector
-	(pt 872 272)
-	(pt 872 240)
-)
-(connector
-	(pt 872 240)
-	(pt 952 240)
-)
-(connector
-	(pt 888 288)
-	(pt 888 272)
-)
-(connector
-	(pt 888 272)
-	(pt 952 272)
-)
 (connector
 	(pt 608 136)
 	(pt 608 208)
 )
-(connector
-	(pt 608 208)
-	(pt 608 624)
-)
 (connector
 	(pt 544 224)
 	(pt 592 224)
@@ -419,22 +491,109 @@ applicable agreement for further details.
 	(pt 952 224)
 	(bus)
 )
-(connector
-	(pt 544 256)
-	(pt 560 256)
-)
-(connector
-	(pt 560 256)
-	(pt 952 256)
-)
 (connector
 	(pt 1144 208)
 	(pt 1168 208)
 	(bus)
 )
+(connector
+	(pt 632 120)
+	(pt 488 120)
+)
+(connector
+	(pt 488 136)
+	(pt 488 120)
+)
+(connector
+	(pt 560 624)
+	(pt 560 296)
+)
+(connector
+	(pt 632 280)
+	(pt 608 280)
+)
+(connector
+	(pt 608 208)
+	(pt 608 280)
+)
+(connector
+	(pt 544 296)
+	(pt 560 296)
+)
+(connector
+	(pt 560 296)
+	(pt 632 296)
+)
+(connector
+	(pt 776 280)
+	(pt 872 280)
+)
+(connector
+	(pt 872 280)
+	(pt 872 256)
+)
+(connector
+	(pt 952 256)
+	(pt 872 256)
+)
+(connector
+	(pt 544 384)
+	(pt 632 384)
+)
+(connector
+	(pt 632 368)
+	(pt 608 368)
+)
+(connector
+	(pt 608 280)
+	(pt 608 368)
+)
+(connector
+	(pt 776 368)
+	(pt 888 368)
+)
+(connector
+	(pt 888 368)
+	(pt 888 240)
+)
+(connector
+	(pt 952 240)
+	(pt 888 240)
+)
+(connector
+	(pt 776 456)
+	(pt 904 456)
+)
+(connector
+	(pt 904 456)
+	(pt 904 272)
+)
+(connector
+	(pt 952 272)
+	(pt 904 272)
+)
+(connector
+	(pt 632 472)
+	(pt 544 472)
+)
+(connector
+	(pt 632 456)
+	(pt 608 456)
+)
+(connector
+	(pt 608 368)
+	(pt 608 456)
+)
+(connector
+	(pt 608 456)
+	(pt 608 624)
+)
 (junction (pt 592 224))
-(junction (pt 560 256))
 (junction (pt 576 240))
 (junction (pt 608 136))
 (junction (pt 608 32))
 (junction (pt 608 208))
+(junction (pt 608 280))
+(junction (pt 560 296))
+(junction (pt 608 368))
+(junction (pt 608 456))
diff --git a/MainController/MainController.qsf b/MainController/MainController.qsf
index e4d699c..7977875 100644
--- a/MainController/MainController.qsf
+++ b/MainController/MainController.qsf
@@ -109,4 +109,10 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nBL[1]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nBL[0]
 set_global_assignment -name VHDL_FILE RAM9X8.vhd
 set_location_assignment PIN_195 -to Address[8]
+set_global_assignment -name VHDL_FILE DigitalFilter8.vhd
+set_global_assignment -name VHDL_FILE DigitalFilter16.vhd
+set_global_assignment -name VHDL_FILE RAM9X8_SerialBusMaster.vhd
+set_location_assignment PIN_46 -to SerialBusIn
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SerialBusIn
+set_global_assignment -name VHDL_FILE DigitalFilter2.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/MainController/RAM9X8.vhd b/MainController/RAM9X8.vhd
index 62f22c8..d52dfe8 100644
--- a/MainController/RAM9X8.vhd
+++ b/MainController/RAM9X8.vhd
@@ -23,37 +23,48 @@ signal wePrev : std_logic := '0';
 signal oePrev : std_logic := '0';
 signal cePrev : std_logic := '0';
 
-type MemoryMachine is (Waiting, Starting, Writing, Reading);
+type MemoryMachine is (Waiting, ReadingAddress, WritingData, ReadingData);
 signal stateMM : MemoryMachine := Waiting;
 
 begin	
 
 	process(clk)
 		variable addr : integer range 0 to 511 := 0;
+		variable count : integer range 0 to 2 := 0;
 	begin
 		if rising_edge(clk) then
 			case stateMM is
 				when Waiting => 
 					if ce = '0' and cePrev = '1' then
-						stateMM <= Starting;
-					else
-						data <= (others => 'Z');
+						stateMM <= ReadingAddress;
 					end if;
-				when Starting => 
-					addr := conv_integer(address);
-					if oe = '0' then
-						stateMM <= Reading;							
-					else 
-						stateMM <= Writing;
-					end if;	
-				when Reading =>
+					count := 0;
+					data <= (others => 'Z');
+				when ReadingAddress =>	
+					--if ce = '0' then
+						if count < 2 then
+							count := count + 1;
+						else
+							count := 0;
+							addr := conv_integer(address);
+							if oe = '0' then
+								stateMM <= ReadingData;
+								data <= (others => '0');		
+							else 
+								stateMM <= WritingData;
+							end if;
+						end if;
+					--else
+						--stateMM <= Waiting;
+					--end if;
+				when ReadingData =>
 					data <= memory(addr);
 					if oe = '1' and oePrev = '0' then
 						stateMM <= Waiting;
 					elsif ce = '1' then
 						stateMM <= Waiting;
 					end if;					
-				when Writing =>
+				when WritingData =>
 					if we = '0' and wePrev = '1' then
 						memory(addr) <= data;
 						stateMM <= Waiting;
diff --git a/MainController/RAM9X8_SerialBusMaster.vhd b/MainController/RAM9X8_SerialBusMaster.vhd
new file mode 100644
index 0000000..4316e8a
--- /dev/null
+++ b/MainController/RAM9X8_SerialBusMaster.vhd
@@ -0,0 +1,360 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+  
+entity RAM9X8_SerialBusMaster is	
+	generic(
+		REG_ADDR_DATA_UPPER_BYTE : integer := 0;
+		REG_ADDR_DATA_LOWER_BYTE : integer := 1;
+		REG_ADDR_CMD_UPPER_BYTE : integer := 2;
+		REG_ADDR_CMD_LOWER_BYTE : integer := 3;
+		
+		DATA_BUS_WIDTH : integer := 8;
+		ADDRESS_BUS_WIDTH : integer := 9
+	);
+	
+	port(
+		clk : in std_logic;
+		
+		data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
+		address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
+		we : in std_logic;
+		oe : in std_logic;
+		ce : in std_logic;	
+	
+		sbclk : out std_logic := '0';
+      sbdataout : out std_logic := '0';
+      sbdatain : in std_logic;
+	);
+end entity;
+
+architecture behavorial of RAM9X8_SerialBusMaster is
+
+type mem is array (511 downto 0) of std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
+signal memory : mem;
+
+signal wePrev : std_logic := '0';
+signal oePrev : std_logic := '0';
+signal cePrev : std_logic := '0';
+
+type MemoryMachine is (Waiting, Writing, Reading);
+signal stateMM : MemoryMachine := Waiting;
+
+signal dataBufIn : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downro 0);
+signal dataBufOut : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downro 0);
+signal cmdBuf : std_logic_vector(DATA_BUS_WIDTH*2 - 1 downro 0);
+
+signal direction : std_logic := '0';
+signal addressToTransmit : std_logic_vector(7 downto 0) := x"00";
+signal dataToTransmit : std_logic_vector(15 downto 0) := x"0000";
+signal dataFromDevices : std_logic_vector(15 downto 0) := x"0000";
+    
+type   CommunicationState_start  is (Waiting, TransmiteAddress, TransmiteData, TransmiteCRC, TransmiteCheck, ReceiveData, ReceiveCRC, ReceiveCheck);  
+signal CommunicationState  : CommunicationState_start := Waiting ;
+	
+signal resetCRC : std_logic := '1';
+signal CRC : std_logic_vector(3 downto 0) := x"0";
+signal bufCRC : std_logic_vector(3 downto 0) := x"0";
+signal dataCRC : std_logic_vector(31 downto 0) := x"00000000";                                                -- переключает 
+signal readyCRC : std_logic := '0';                                                -- готовность контрольной суммы
+	
+signal lineBusy : std_logic := '1';
+
+begin	
+
+	process(clk)
+		variable addr : integer range 0 to 2^ADDRESS_BUS_WIDTH := 0;
+	begin
+		if rising_edge(clk) then
+			case stateMM is
+				when Waiting => 
+					if ce = '0' and cePrev = '1' then 
+						addr := conv_integer(address);
+						if (addr == REG_ADDR_DATA_UPPER_BYTE or addr == REG_ADDR_DATA_LOWER_BYTE or addr == REG_ADDR_CMD_UPPER_BYTE or addr == REG_ADDR_CMD_LOWER_BYTE) then
+							if oe = '0' then
+								stateMM <= Reading;							
+							else 
+								stateMM <= Writing;
+							end if;
+						end if;	
+					else
+						start <= '0';
+						data <= (others => 'Z');
+					end if;
+				when Reading =>
+					case addr is
+						when REG_ADDR_DATA_UPPER_BYTE =>
+							data <= dataBufOut(15 downto 8);
+						when REG_ADDR_DATA_LOWER_BYTE =>
+							data <= dataBufOut(7 downto 0);
+						when REG_ADDR_CMD_UPPER_BYTE =>
+							data <= cmdBuf(15 downto 8);
+						when REG_ADDR_CMD_LOWER_BYTE =>
+							data <= cmdBuf(7 downto 0);
+						when others =>
+					end case;	
+					if oe = '1' and oePrev = '0' then
+						stateMM <= Waiting;
+					elsif ce = '1' then
+						stateMM <= Waiting;
+					end if;					
+				when Writing =>
+					if we = '0' and wePrev = '1' then
+						case addr is
+							when REG_ADDR_DATA_UPPER_BYTE =>
+								dataBufIn(15 downto 8) <= data;
+							when REG_ADDR_DATA_LOWER_BYTE =>
+								dataBufIn(7 downto 0) <= data;
+							when REG_ADDR_CMD_UPPER_BYTE =>
+								cmdBuf(15 downto 8) <= data;
+							when REG_ADDR_CMD_LOWER_BYTE =>
+								cmdBuf(7 downto 0) <= data;
+								start <= '1';
+							when others =>
+						end case;
+						stateMM <= Waiting;
+					elsif ce = '1' then
+						stateMM <= Waiting;
+					end if;					
+				when others =>
+			end case;
+			
+			oePrev <= oe;		
+			cePrev <= ce;
+			wePrev <= we;
+		end if;
+	end process;
+	
+	process(clk) is
+		variable count : integer range 0 to 255 := 0;
+		variable countValue : integer range 0 to 255 := 63;
+		variable state : integer range 0 to 1 := 1;
+		variable bitCnt : integer range -1 to 31 := 0;
+		variable latch : integer range 0 to 1 := 0;
+	begin
+		if(rising_edge (clk)) then
+			case CommunicationState is
+				when Waiting =>
+					sbclk <= '0';
+					bitCnt := 8;
+					latch := 0;
+					resetCRC <= '1';
+					sbdataout <= '0';
+					lineBusy <= '0';
+					count := 0;
+					state := 1;
+					if start = '1' and  startPrev = '0' then                               
+						direction <= cmdBuf(15);
+                  dataCRC(24) <= cmdBuf(15);
+                  addressToTransmit(7 downto 0) <= cmdBuf(7 downto 0);
+                  dataCRC(23 downto 16) <= cmdBuf(7 downto 0);
+                  dataToTransmit <= dataBufIn;
+                  dataCRC(15 downto 0) <= dataBufIn; 
+                  CommunicationState <= TransmitAddress;
+                  lineBusy <= '1';
+               end if;
+				when TransmitAddress =>	 
+					if bitCnt = -1 then
+						if direction = '1' then
+							CommunicationState <= TransmitData;
+							resetCRC <= '0';
+						else
+							CommunicationState <= ReceiveData;
+						end if;
+						bitCnt := 15;                      
+					else 
+						if count < countValue and state = 1 then
+							if latch = 0 then 
+								sbdataout <= direction;
+							else 
+								sbdataout <= addressToTransmit(bitCnt);
+                     end if;                           
+							sbclk <= '0';
+                     count := count + 1;
+                  elsif count = countValue and state = '1' then
+							latch := 1;	                   
+							count := 0;
+							state := 0;	                   
+						elsif count < countValue and state = '0' then 
+							sbclk <= '1'; 
+							count := count + 1;   
+						elsif count = countValue and state = '0' then  
+							count := 0;
+							state := 1;
+							bitCnt := bitCnt - 1;
+						end if; 
+					end if;      
+			   when TransmitData =>	
+					if bitCnt = -1 then
+						CommunicationState <= TransmitCRC;	                             
+	               bitCnt := 3;
+	            else 
+						if count < countValue and state = 1 then
+							sbdataout <= data(bitCnt);
+							sbclk <= '0';
+							count := count + 1;
+						elsif count = countValue and state = 1 then	                   
+							count := 0;
+							state := 0;	                   
+						elsif count < countValue and state = 0 then 
+							sbclk <= '1'; 
+							count := count + 1;   
+						elsif count = countValue and state = 0 then  
+							count := 0;;
+							state := 1;
+							bitCnt := bitCnt - 1;
+						end if; 
+					end if;
+				when TransmitCRC =>	
+					if readyCRC = '1' then
+						if bitCnt = -1 then
+							CommunicationState <= TransmitCheck;
+							errors(1) <= '0';
+						else 
+							if count < count and state = 1 then
+								sbdataout <= CRC(bitCnt);
+								sbclk <= '0';
+								count := count + 1;
+							elsif count = countValue and state = 1 then	                   
+								count := 0;
+								state := 0;	                   
+							elsif count < countValue and state = 0 then 
+								sbclk <= '1'; 
+								count := count + 1;   
+							elsif count = countValue and state = 0 then  
+								count := 0;
+								state := 1;
+								bitCnt := bitCnt - 1;
+							end if; 
+						end if;    		
+					else 
+						CommunicationState <= Waiting;
+						errors(1) <= '1';
+						countError1 <= countError1 + 1;
+					end if; 
+			   when TransmitCheck =>
+					if count < countValue and state = 1 then
+						sbclk <= '0';
+						count := count + 1;
+					else	                   
+						count := 0;
+						state := 0;
+						if sbdatain = '0' then                           
+							countSuccessfulTransmite <= countSuccessfulTransmite + 1;
+							errors(0) <= '0';
+						else
+							errors(0) <= '1';
+							countError0 <= countError0 + 1;
+						end if;
+						CommunicationState <= Waiting;
+					end if;    
+			   when ReceiveData =>
+					if bitCnt = -1 then
+						CommunicationState <= ReceiveCRC;	                             
+						bitCnt <= 3;
+					else 
+						if count < countValue and state = 1 then
+							sbclk <= '0';
+							count := count + 1;
+						elsif count = countValue and state = 1 then
+							dataFromDevices(bitCnt) <= sbdatain;	                   
+							count := 0;
+                     state := 0;	                   
+                  elsif count < countValue and state = 0 then 
+							sbclk <= '1'; 
+							count := count + 1;   
+						elsif count = countValue and state = '0' then  
+							count := 0;
+							state := 1;
+							bitCnt := bitCnt - 1;
+						end if;
+					end if;
+				when ReceiveCRC =>
+					if bitCnt = -1 then
+						CommunicationState <= ReceiveCheck;
+					else 
+						if count < countValue and state = 1 then
+							sbclk <= '0';
+							count := count + 1;
+						elsif count = countValue and state = 1 then
+							bufCRC(BitCnt) <= sbdatain;	                   
+							count := 0;
+							state := 0;
+							if bitCnt = 0 then
+								dataCRC(24) <= direction;
+								dataCRC(23 downto 16) <= addressToTransmit;
+								dataCRC(15 downto 0) <= dataFromDevices(15 downto 0);
+								resetCRC <= '0';
+							end if;	                   
+						elsif count < countValue and state = 0 then 
+							sbclk <= '1'; 
+							count := count + 1;                                   
+                  elsif count = countValue and state = 0 then  
+                     count := 0;
+                     state := 1;
+                     bitCnt := bitCnt - 1;
+                  end if;
+               end if;
+				when ReceiveCheck =>
+					if readyCRC = '1' then
+						if bufCRC = CRC then
+							countSuccessfulReceive <= countSuccessfulReceive + 1;
+							dataBufOut <= dataFromDevices;
+							errors(3) <= '0'; 
+						else
+							errors(3) <= '1';
+							countError3 <= countError3 + 1;   
+                  end if;
+						errors(2) <= '0'; 
+					else 
+						errors(2) <= '1';
+						countError2 <= countError2 + 1;    
+					end if;
+					CommunicationState <= Waiting;     
+				when others =>
+			end case;
+      startPrev <= start;
+		end if;
+	end process;
+	
+	process(clk)  
+		variable lacth : integer range 0 to 1 := 0;
+		variable bitCnt : integer range -1 to 24 := 0;
+	begin
+		if rising_edge(clk) then
+			if resetCRC = '1' then
+				bitCnt := 24; 
+				CRC <= x"0";
+				lacth := 0;
+				readyCRC <= '0';
+			else
+				if readyCRC = '0' then
+					if lacth = 0 then
+						if bitCnt /= -1  then
+							CRC(3) <= CRC(2) xor CRC(3);
+							CRC(2) <= CRC(1) xor CRC(0);	
+							CRC(1) <= CRC(0);
+							CRC(0) <=  dataCRC(bitCnt) xor CRC(1);											
+							bitCnt := bitCnt - 1;
+						else
+							bitCnt := 3;
+							lacth := 1;
+						end if;   
+					else
+						if bitCnt /= -1  then
+							CRC(3) <= CRC(2) xor CRC(3);
+							CRC(2) <= CRC(1) xor CRC(0);	
+							CRC(1) <= CRC(0);	
+							CRC(0) <= '1' xor CRC(1);	
+							bitCnt := bitCnt - 1;	 
+						else
+							readyCRC <= '1';
+							countreadyCRC <= countreadyCRC + 1;
+						end if;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+	
+end behavorial;
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