diff --git a/MainController/MainController.bdf b/MainController/MainController.bdf index 246509c..f645a27 100644 --- a/MainController/MainController.bdf +++ b/MainController/MainController.bdf @@ -121,6 +121,40 @@ applicable agreement for further details. ) (annotation_block (location)(rect 1320 40 1376 56)) ) +(pin + (output) + (rect 1144 64 1320 80) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "FPGA_LED_2" (rect 90 0 158 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1320 64 1376 80)) +) +(pin + (output) + (rect 1144 88 1320 104) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "FPGA_LED_3" (rect 90 0 158 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1320 88 1376 104)) +) (pin (bidir) (rect 368 232 544 248) @@ -206,9 +240,9 @@ applicable agreement for further details. ) ) (symbol - (rect 952 176 1152 352) + (rect 952 176 1152 384) (text "RAM" (rect 5 0 28 12)(font "Arial" )) - (text "inst1" (rect 8 160 31 172)(font "Arial" )) + (text "inst3" (rect 8 192 31 204)(font "Arial" )) (port (pt 0 32) (input) @@ -226,38 +260,52 @@ applicable agreement for further details. (port (pt 0 64) (input) - (text "wr0" (rect 0 0 16 12)(font "Arial" )) - (text "wr0" (rect 21 59 37 71)(font "Arial" )) + (text "we0" (rect 0 0 18 12)(font "Arial" )) + (text "we0" (rect 21 59 39 71)(font "Arial" )) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) - (text "clk0" (rect 0 0 20 12)(font "Arial" )) - (text "clk0" (rect 21 75 41 87)(font "Arial" )) + (text "oe0" (rect 0 0 17 12)(font "Arial" )) + (text "oe0" (rect 21 75 38 87)(font "Arial" )) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) - (text "address1[7..0]" (rect 0 0 70 12)(font "Arial" )) - (text "address1[7..0]" (rect 21 91 91 103)(font "Arial" )) - (line (pt 0 96)(pt 16 96)(line_width 3)) + (text "ce0" (rect 0 0 17 12)(font "Arial" )) + (text "ce0" (rect 21 91 38 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) - (text "wr1" (rect 0 0 16 12)(font "Arial" )) - (text "wr1" (rect 21 107 37 119)(font "Arial" )) - (line (pt 0 112)(pt 16 112)) + (text "address1[7..0]" (rect 0 0 70 12)(font "Arial" )) + (text "address1[7..0]" (rect 21 107 91 119)(font "Arial" )) + (line (pt 0 112)(pt 16 112)(line_width 3)) ) (port (pt 0 128) (input) - (text "clk1" (rect 0 0 20 12)(font "Arial" )) - (text "clk1" (rect 21 123 41 135)(font "Arial" )) + (text "we1" (rect 0 0 18 12)(font "Arial" )) + (text "we1" (rect 21 123 39 135)(font "Arial" )) (line (pt 0 128)(pt 16 128)) ) + (port + (pt 0 144) + (input) + (text "oe1" (rect 0 0 17 12)(font "Arial" )) + (text "oe1" (rect 21 139 38 151)(font "Arial" )) + (line (pt 0 144)(pt 16 144)) + ) + (port + (pt 0 160) + (input) + (text "ce1" (rect 0 0 17 12)(font "Arial" )) + (text "ce1" (rect 21 155 38 167)(font "Arial" )) + (line (pt 0 160)(pt 16 160)) + ) (port (pt 200 32) (bidir) @@ -273,7 +321,7 @@ applicable agreement for further details. (line (pt 200 48)(pt 184 48)(line_width 3)) ) (drawing - (rectangle (rect 16 16 184 160)) + (rectangle (rect 16 16 184 192)) ) ) (connector @@ -302,34 +350,10 @@ applicable agreement for further details. (pt 784 136) (pt 832 136) ) -(connector - (pt 832 192) - (pt 848 192) -) -(connector - (pt 832 136) - (pt 832 192) -) -(connector - (pt 544 272) - (pt 848 272) -) -(connector - (pt 544 256) - (pt 560 256) -) -(connector - (pt 560 256) - (pt 848 256) -) (connector (pt 608 48) (pt 608 152) ) -(connector - (pt 608 152) - (pt 608 624) -) (connector (pt 608 48) (pt 632 48) @@ -338,36 +362,6 @@ applicable agreement for further details. (pt 752 48) (pt 1144 48) ) -(connector - (pt 544 224) - (pt 592 224) - (bus) -) -(connector - (pt 592 224) - (pt 952 224) - (bus) -) -(connector - (pt 936 240) - (pt 936 160) - (bus) -) -(connector - (pt 544 240) - (pt 576 240) - (bus) -) -(connector - (pt 576 240) - (pt 936 240) - (bus) -) -(connector - (pt 936 160) - (pt 1168 160) - (bus) -) (connector (pt 1168 160) (pt 1168 208) @@ -379,10 +373,109 @@ applicable agreement for further details. (bus) ) (connector + (pt 544 224) + (pt 592 224) + (bus) +) +(connector + (pt 592 224) + (pt 952 224) + (bus) +) +(connector + (pt 952 208) + (pt 832 208) +) +(connector + (pt 544 256) + (pt 560 256) +) +(connector + (pt 560 256) + (pt 952 256) +) +(connector + (pt 544 272) + (pt 904 272) +) +(connector + (pt 904 272) + (pt 904 240) +) +(connector + (pt 952 240) + (pt 904 240) +) +(connector + (pt 920 288) (pt 544 288) - (pt 848 288) +) +(connector + (pt 920 288) + (pt 920 272) +) +(connector + (pt 920 272) + (pt 952 272) +) +(connector + (pt 888 240) + (pt 888 160) + (bus) +) +(connector + (pt 1168 160) + (pt 888 160) + (bus) +) +(connector + (pt 544 240) + (pt 576 240) + (bus) +) +(connector + (pt 576 240) + (pt 888 240) + (bus) +) +(connector + (pt 832 72) + (pt 1144 72) +) +(connector + (pt 832 136) + (pt 832 72) +) +(connector + (pt 784 152) + (pt 856 152) +) +(connector + (pt 856 152) + (pt 856 96) +) +(connector + (pt 856 96) + (pt 1144 96) +) +(connector + (pt 832 208) + (pt 832 304) +) +(connector + (pt 832 304) + (pt 608 304) +) +(connector + (pt 608 152) + (pt 608 304) +) +(connector + (pt 608 304) + (pt 608 624) ) (junction (pt 608 152)) (junction (pt 592 224)) (junction (pt 560 256)) (junction (pt 576 240)) +(junction (pt 608 304)) diff --git a/MainController/MainController.qsf b/MainController/MainController.qsf index 6613a1b..0151a4b 100644 --- a/MainController/MainController.qsf +++ b/MainController/MainController.qsf @@ -99,4 +99,8 @@ set_location_assignment PIN_217 -to nOE set_location_assignment PIN_218 -to nWE set_location_assignment PIN_219 -to nCE set_location_assignment PIN_31 -to FPGA_CLK +set_location_assignment PIN_167 -to FPGA_LED_2 +set_location_assignment PIN_168 -to FPGA_LED_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_3 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/MainController/RAM.bsf b/MainController/RAM.bsf index 4a53d03..12b4098 100644 --- a/MainController/RAM.bsf +++ b/MainController/RAM.bsf @@ -20,9 +20,9 @@ applicable agreement for further details. */ (header "symbol" (version "1.1")) (symbol - (rect 16 16 216 192) + (rect 16 16 216 224) (text "RAM" (rect 5 0 29 12)(font "Arial" )) - (text "inst" (rect 8 160 20 172)(font "Arial" )) + (text "inst" (rect 8 192 20 204)(font "Arial" )) (port (pt 0 32) (input) @@ -40,38 +40,52 @@ applicable agreement for further details. (port (pt 0 64) (input) - (text "wr0" (rect 0 0 14 12)(font "Arial" )) - (text "wr0" (rect 21 59 35 71)(font "Arial" )) + (text "we0" (rect 0 0 15 12)(font "Arial" )) + (text "we0" (rect 21 59 36 71)(font "Arial" )) (line (pt 0 64)(pt 16 64)(line_width 1)) ) (port (pt 0 80) (input) - (text "clk0" (rect 0 0 15 12)(font "Arial" )) - (text "clk0" (rect 21 75 36 87)(font "Arial" )) + (text "oe0" (rect 0 0 14 12)(font "Arial" )) + (text "oe0" (rect 21 75 35 87)(font "Arial" )) (line (pt 0 80)(pt 16 80)(line_width 1)) ) (port (pt 0 96) (input) - (text "address1[7..0]" (rect 0 0 55 12)(font "Arial" )) - (text "address1[7..0]" (rect 21 91 76 103)(font "Arial" )) - (line (pt 0 96)(pt 16 96)(line_width 3)) + (text "ce0" (rect 0 0 14 12)(font "Arial" )) + (text "ce0" (rect 21 91 35 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 1)) ) (port (pt 0 112) (input) - (text "wr1" (rect 0 0 12 12)(font "Arial" )) - (text "wr1" (rect 21 107 33 119)(font "Arial" )) - (line (pt 0 112)(pt 16 112)(line_width 1)) + (text "address1[7..0]" (rect 0 0 55 12)(font "Arial" )) + (text "address1[7..0]" (rect 21 107 76 119)(font "Arial" )) + (line (pt 0 112)(pt 16 112)(line_width 3)) ) (port (pt 0 128) (input) - (text "clk1" (rect 0 0 14 12)(font "Arial" )) - (text "clk1" (rect 21 123 35 135)(font "Arial" )) + (text "we1" (rect 0 0 14 12)(font "Arial" )) + (text "we1" (rect 21 123 35 135)(font "Arial" )) (line (pt 0 128)(pt 16 128)(line_width 1)) ) + (port + (pt 0 144) + (input) + (text "oe1" (rect 0 0 12 12)(font "Arial" )) + (text "oe1" (rect 21 139 33 151)(font "Arial" )) + (line (pt 0 144)(pt 16 144)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "ce1" (rect 0 0 12 12)(font "Arial" )) + (text "ce1" (rect 21 155 33 167)(font "Arial" )) + (line (pt 0 160)(pt 16 160)(line_width 1)) + ) (port (pt 200 32) (bidir) @@ -87,6 +101,6 @@ applicable agreement for further details. (line (pt 200 48)(pt 184 48)(line_width 3)) ) (drawing - (rectangle (rect 16 16 184 160)(line_width 1)) + (rectangle (rect 16 16 184 192)(line_width 1)) ) ) diff --git a/MainController/RAM.vhd b/MainController/RAM.vhd index 24832e1..5b01e8e 100644 --- a/MainController/RAM.vhd +++ b/MainController/RAM.vhd @@ -10,13 +10,15 @@ entity RAM is data0 : inout std_logic_vector(7 downto 0); address0 : in std_logic_vector(7 downto 0); - wr0 : in std_logic; - clk0 : in std_logic; + we0 : in std_logic; + oe0 : in std_logic; + ce0 : in std_logic; data1 : inout std_logic_vector(7 downto 0); address1 : in std_logic_vector(7 downto 0); - wr1 : in std_logic; - clk1 : in std_logic + we1 : in std_logic; + oe1 : in std_logic; + ce1 : in std_logic ); end entity; @@ -25,46 +27,134 @@ architecture behavorial of RAM is type mem is array (255 downto 0) of std_logic_vector(7 downto 0); signal memory : mem; -signal clk0Prev : std_logic := '0'; -signal clk1Prev : std_logic := '0'; +signal we0Prev : std_logic := '0'; +signal oe0Prev : std_logic := '0'; +signal ce0Prev : std_logic := '0'; + +signal we1Prev : std_logic := '0'; +signal oe1Prev : std_logic := '0'; +signal ce1Prev : std_logic := '0'; + +type MemoryMachine is (Waiting, Writing, Reading); +signal stateMM0 : MemoryMachine := Waiting; +signal stateMM1 : MemoryMachine := Waiting; begin + -- автомат для работы с памятью со стороны контроллера process(clk) - variable addr0 : integer range 0 to 255; - variable addr1 : integer range 0 to 255; + variable addr : integer range 0 to 255 := 0; begin if rising_edge(clk) then - - if clk1 = '1' and clk1Prev = '0' then - addr1 := conv_integer(address1); -- переменной addr1 присваивается новое значение сразу. Удобно для преобразования типов. - if (wr1 = '0') then - memory(addr1) <= data1; -- тут уже новое значение переменной addr1 - else - data1 <= memory(addr1); - end if; - end if; - if clk1 = '0' and clk1Prev = '1' then - data1 <= (others => 'Z'); - end if; - - clk1Prev <= clk1; - - if clk0 = '1' and clk0Prev = '0' then - addr0 := conv_integer(address0); -- переменной addr0 присваивается новое значение сразу. Удобно для преобразования типов. - if (wr0 = '0') then - memory(addr0) <= data0; -- тут уже новое значение переменной addr0 - else - data0 <= memory(addr0); - end if; - end if; - if clk0 = '0' and clk0Prev = '1' then - data0 <= (others => 'Z'); - end if; - - clk0Prev <= clk0; - + case stateMM0 is + when Waiting => + if ce0 = '0' and ce0Prev = '1' then + addr := conv_integer(address0); + if oe0 = '0' then -- этот if можно перенести на следующий такт, чтобы успела установиться ножка output enable + stateMM0 <= Reading; + else + stateMM0 <= Writing; + end if; + else + addr := 0; + data0 <= (others => 'Z'); + end if; + when Reading => + data0 <= memory(addr); + if oe0 = '1' and oe0Prev = '0' then + stateMM0 <= Waiting; + elsif ce0 = '1' then + stateMM0 <= Waiting; + end if; + when Writing => + if we0 = '0' and we0Prev = '1' then + memory(addr) <= data0; + stateMM0 <= Waiting; + elsif ce0 = '1' then + stateMM0 <= Waiting; + end if; + when others => + end case; + oe0Prev <= oe0; + ce0Prev <= ce0; + we0Prev <= we0; end if; end process; + -- автомат для работы с памятью со стороны контроллера + process(clk) + variable addr : integer range 0 to 255 := 0; + begin + if rising_edge(clk) then + case stateMM1 is + when Waiting => + if ce1 = '0' and ce1Prev = '1' then + addr := conv_integer(address1); + if oe1 = '0' then -- этот if можно перенести на следующий такт, чтобы успела установиться ножка output enable + stateMM1 <= Reading; + else + stateMM1 <= Writing; + end if; + else + addr := 0; + data1 <= (others => 'Z'); + end if; + when Reading => + data1 <= memory(addr); + if oe1 = '1' and oe1Prev = '0' then + stateMM1 <= Waiting; + elsif ce0 = '1' then + stateMM1 <= Waiting; + end if; + when Writing => + if we1 = '0' and we1Prev = '1' then + memory(addr) <= data1; + stateMM1 <= Waiting; + elsif ce0 = '1' then + stateMM1 <= Waiting; + end if; + when others => + end case; + oe1Prev <= oe1; + ce1Prev <= ce1; + we1Prev <= we1; + end if; + end process; + + +-- process(clk) +-- variable addr : integer range 0 to 255; +-- begin +-- if rising_edge(clk) then +-- if clk = '1' and clkPrev = '0' then +-- addr := conv_integer(address1); -- переменной addr1 присваивается новое значение сразу. Удобно для преобразования типов. +-- if (wr1 = '0') then +-- memory(addr1) <= data1; -- тут уже новое значение переменной addr1 +-- else +-- data1 <= memory(addr1); +-- end if; +-- end if; +-- if clk1 = '0' and clk1Prev = '1' then +-- data1 <= (others => 'Z'); +-- end if; +-- +-- clk1Prev <= clk1; +-- +-- if clk0 = '1' and clk0Prev = '0' then +-- addr0 := conv_integer(address0); -- переменной addr0 присваивается новое значение сразу. Удобно для преобразования типов. +-- if (wr0 = '0') then +-- memory(addr0) <= data0; -- тут уже новое значение переменной addr0 +-- else +-- data0 <= memory(addr0); +-- end if; +-- end if; +-- if clk0 = '0' and clk0Prev = '1' then +-- data0 <= (others => 'Z'); +-- end if; +-- +-- clk0Prev <= clk0; +-- +-- end if; +-- end process; + end behavorial; \ No newline at end of file diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.ammdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.ammdb index 74bcb72..bc576a4 100644 Binary files a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.ammdb and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.ammdb differ diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.cdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.cdb index e970138..8e5080d 100644 Binary files a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.cdb and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.cdb differ diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.hdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.hdb index 5370598..cf55485 100644 Binary files a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.hdb and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.hdb differ diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.rcfdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.rcfdb index 4a036e2..41c5420 100644 Binary files a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.rcfdb and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.rcfdb differ diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.cdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.cdb index 9b00d66..fd6494d 100644 Binary files a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.cdb and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.cdb differ diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.dpi b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.dpi index 0be2cf6..627b2cb 100644 Binary files a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.dpi and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.dpi differ diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.cdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.cdb index 577fdb8..866ab39 100644 Binary files a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.cdb and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.cdb differ diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hb_info b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hb_info index 8210c55..f5c15cc 100644 Binary files a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hb_info and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hb_info differ diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hdb index 9fc9c60..05f4a2e 100644 Binary files a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hdb and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hdb differ diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.sig b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.sig index ef58eaa..5c0fb82 100644 --- a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.sig +++ b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.sig @@ -1 +1 @@ -d1187c24d5e18b5b14f48701f0f8928b \ No newline at end of file +5609c04c14c15587f66e4a304a24bc35 \ No newline at end of file diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hdb index d0f2a76..e54c832 100644 Binary files a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hdb and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hdb differ diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.kpt b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.kpt index 6859430..f7ea92c 100644 Binary files a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.kpt and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.kpt differ diff --git a/MainController/output_files/MainController.done b/MainController/output_files/MainController.done index 63617f0..0bec26f 100644 --- a/MainController/output_files/MainController.done +++ b/MainController/output_files/MainController.done @@ -1 +1 @@ -Tue Mar 12 16:24:29 2024 +Tue Mar 12 17:46:57 2024 diff --git a/MainController/output_files/MainController.eda.rpt b/MainController/output_files/MainController.eda.rpt index 39ab5c2..475ea24 100644 --- a/MainController/output_files/MainController.eda.rpt +++ b/MainController/output_files/MainController.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for MainController -Tue Mar 12 16:24:29 2024 +Tue Mar 12 17:46:57 2024 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -36,7 +36,7 @@ applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Tue Mar 12 16:24:29 2024 ; +; EDA Netlist Writer Status ; Successful - Tue Mar 12 17:46:57 2024 ; ; Revision Name ; MainController ; ; Top-level Entity Name ; MainController ; ; Family ; Cyclone III ; @@ -88,7 +88,7 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version - Info: Processing started: Tue Mar 12 16:24:28 2024 + Info: Processing started: Tue Mar 12 17:46:56 2024 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off MainController -c MainController Info (204019): Generated file MainController_8_1200mv_85c_slow.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file MainController_8_1200mv_0c_slow.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool @@ -99,8 +99,8 @@ Info (204019): Generated file MainController_8_1200mv_0c_vhd_slow.sdo in folder Info (204019): Generated file MainController_min_1200mv_0c_vhd_fast.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file MainController_vhd.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 4567 megabytes - Info: Processing ended: Tue Mar 12 16:24:29 2024 + Info: Peak virtual memory: 4577 megabytes + Info: Processing ended: Tue Mar 12 17:46:57 2024 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/MainController/output_files/MainController.fit.rpt b/MainController/output_files/MainController.fit.rpt index 7f87d40..84b636f 100644 --- a/MainController/output_files/MainController.fit.rpt +++ b/MainController/output_files/MainController.fit.rpt @@ -1,5 +1,5 @@ Fitter report for MainController -Tue Mar 12 16:24:22 2024 +Tue Mar 12 17:46:50 2024 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -23,25 +23,28 @@ Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version 15. Dual Purpose and Dedicated Pins 16. I/O Bank Usage 17. All Package Pins - 18. Fitter Resource Utilization by Entity - 19. Delay Chain Summary - 20. Pad To Core Delay Chain Fanout - 21. Control Signals - 22. Global & Other Fast Signals - 23. Non-Global High Fan-Out Signals - 24. Routing Usage Summary - 25. LAB Logic Elements - 26. LAB-wide Signals - 27. LAB Signals Sourced - 28. LAB Signals Sourced Out - 29. LAB Distinct Inputs - 30. I/O Rules Summary - 31. I/O Rules Details - 32. I/O Rules Matrix - 33. Fitter Device Options - 34. Operating Settings and Conditions - 35. Fitter Messages - 36. Fitter Suppressed Messages + 18. PLL Summary + 19. PLL Usage + 20. Fitter Resource Utilization by Entity + 21. Delay Chain Summary + 22. Pad To Core Delay Chain Fanout + 23. Control Signals + 24. Global & Other Fast Signals + 25. Non-Global High Fan-Out Signals + 26. Fitter RAM Summary + 27. Routing Usage Summary + 28. LAB Logic Elements + 29. LAB-wide Signals + 30. LAB Signals Sourced + 31. LAB Signals Sourced Out + 32. LAB Distinct Inputs + 33. I/O Rules Summary + 34. I/O Rules Details + 35. I/O Rules Matrix + 36. Fitter Device Options + 37. Operating Settings and Conditions + 38. Fitter Messages + 39. Fitter Suppressed Messages @@ -67,22 +70,22 @@ applicable agreement for further details. +----------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+---------------------------------------------+ -; Fitter Status ; Successful - Tue Mar 12 16:24:21 2024 ; +; Fitter Status ; Successful - Tue Mar 12 17:46:50 2024 ; ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; ; Revision Name ; MainController ; ; Top-level Entity Name ; MainController ; ; Family ; Cyclone III ; ; Device ; EP3C25Q240C8 ; ; Timing Models ; Final ; -; Total logic elements ; 34 / 24,624 ( < 1 % ) ; -; Total combinational functions ; 34 / 24,624 ( < 1 % ) ; -; Dedicated logic registers ; 25 / 24,624 ( < 1 % ) ; -; Total registers ; 25 ; -; Total pins ; 21 / 149 ( 14 % ) ; +; Total logic elements ; 95 / 24,624 ( < 1 % ) ; +; Total combinational functions ; 67 / 24,624 ( < 1 % ) ; +; Dedicated logic registers ; 80 / 24,624 ( < 1 % ) ; +; Total registers ; 80 ; +; Total pins ; 23 / 149 ( 15 % ) ; ; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 608,256 ( 0 % ) ; +; Total memory bits ; 2,048 / 608,256 ( < 1 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; -; Total PLLs ; 0 / 4 ( 0 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; +------------------------------------+---------------------------------------------+ @@ -171,6 +174,8 @@ applicable agreement for further details. ; Pin Name ; Reason ; +------------+------------------------+ ; FPGA_LED_1 ; Missing drive strength ; +; FPGA_LED_2 ; Missing drive strength ; +; FPGA_LED_3 ; Missing drive strength ; ; Data[7] ; Missing drive strength ; ; Data[6] ; Missing drive strength ; ; Data[5] ; Missing drive strength ; @@ -188,8 +193,8 @@ applicable agreement for further details. ; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; +---------------------+--------------------+----------------------------+--------------------------+ ; Placement (by node) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 121 ) ; 0.00 % ( 0 / 121 ) ; 0.00 % ( 0 / 121 ) ; -; -- Achieved ; 0.00 % ( 0 / 121 ) ; 0.00 % ( 0 / 121 ) ; 0.00 % ( 0 / 121 ) ; +; -- Requested ; 0.00 % ( 0 / 224 ) ; 0.00 % ( 0 / 224 ) ; 0.00 % ( 0 / 224 ) ; +; -- Achieved ; 0.00 % ( 0 / 224 ) ; 0.00 % ( 0 / 224 ) ; 0.00 % ( 0 / 224 ) ; ; ; ; ; ; ; Routing (by net) ; ; ; ; ; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; @@ -212,8 +217,8 @@ applicable agreement for further details. +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ ; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ -; Top ; 0.00 % ( 0 / 111 ) ; N/A ; Source File ; N/A ; ; -; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ; +; Top ; 0.00 % ( 0 / 211 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 13 ) ; N/A ; Source File ; N/A ; ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ @@ -223,54 +228,54 @@ applicable agreement for further details. The pin-out file can be found in D:/GITEA/altera/MainController/output_files/MainController.pin. -+---------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+-----------------------+ -; Resource ; Usage ; -+---------------------------------------------+-----------------------+ -; Total logic elements ; 34 / 24,624 ( < 1 % ) ; -; -- Combinational with no register ; 9 ; -; -- Register only ; 0 ; -; -- Combinational with a register ; 25 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 8 ; -; -- 3 input functions ; 1 ; -; -- <=2 input functions ; 25 ; -; -- Register only ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 11 ; -; -- arithmetic mode ; 23 ; -; ; ; -; Total registers* ; 25 / 25,294 ( < 1 % ) ; -; -- Dedicated logic registers ; 25 / 24,624 ( < 1 % ) ; -; -- I/O registers ; 0 / 670 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 4 / 1,539 ( < 1 % ) ; -; Virtual pins ; 0 ; -; I/O pins ; 21 / 149 ( 14 % ) ; -; -- Clock pins ; 1 / 8 ( 13 % ) ; -; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; -; ; ; -; Global signals ; 1 ; -; M9Ks ; 0 / 66 ( 0 % ) ; -; Total block memory bits ; 0 / 608,256 ( 0 % ) ; -; Total block memory implementation bits ; 0 / 608,256 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; -; PLLs ; 0 / 4 ( 0 % ) ; -; Global clocks ; 1 / 20 ( 5 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; Impedance control blocks ; 0 / 4 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Maximum fan-out ; 25 ; -; Highest non-global fan-out ; 25 ; -; Total fan-out ; 194 ; -; Average fan-out ; 1.62 ; -+---------------------------------------------+-----------------------+ ++-------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+---------------------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------------------+ +; Total logic elements ; 95 / 24,624 ( < 1 % ) ; +; -- Combinational with no register ; 15 ; +; -- Register only ; 28 ; +; -- Combinational with a register ; 52 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 20 ; +; -- 3 input functions ; 20 ; +; -- <=2 input functions ; 27 ; +; -- Register only ; 28 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 44 ; +; -- arithmetic mode ; 23 ; +; ; ; +; Total registers* ; 80 / 25,294 ( < 1 % ) ; +; -- Dedicated logic registers ; 80 / 24,624 ( < 1 % ) ; +; -- I/O registers ; 0 / 670 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 8 / 1,539 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 23 / 149 ( 15 % ) ; +; -- Clock pins ; 1 / 8 ( 13 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; Global signals ; 3 ; +; M9Ks ; 1 / 66 ( 2 % ) ; +; Total block memory bits ; 2,048 / 608,256 ( < 1 % ) ; +; Total block memory implementation bits ; 9,216 / 608,256 ( 2 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; +; PLLs ; 1 / 4 ( 25 % ) ; +; Global clocks ; 3 / 20 ( 15 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 2% / 2% / 2% ; +; Maximum fan-out ; 81 ; +; Highest non-global fan-out ; 30 ; +; Total fan-out ; 516 ; +; Average fan-out ; 2.20 ; ++---------------------------------------------+---------------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. @@ -282,51 +287,53 @@ The pin-out file can be found in D:/GITEA/altera/MainController/output_files/Mai +---------------------------------------------+----------------------+--------------------------------+ ; Difficulty Clustering Region ; Low ; Low ; ; ; ; ; -; Total logic elements ; 34 / 24624 ( < 1 % ) ; 0 / 24624 ( 0 % ) ; -; -- Combinational with no register ; 9 ; 0 ; -; -- Register only ; 0 ; 0 ; -; -- Combinational with a register ; 25 ; 0 ; +; Total logic elements ; 95 / 24624 ( < 1 % ) ; 0 / 24624 ( 0 % ) ; +; -- Combinational with no register ; 15 ; 0 ; +; -- Register only ; 28 ; 0 ; +; -- Combinational with a register ; 52 ; 0 ; ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -; -- 4 input functions ; 8 ; 0 ; -; -- 3 input functions ; 1 ; 0 ; -; -- <=2 input functions ; 25 ; 0 ; -; -- Register only ; 0 ; 0 ; +; -- 4 input functions ; 20 ; 0 ; +; -- 3 input functions ; 20 ; 0 ; +; -- <=2 input functions ; 27 ; 0 ; +; -- Register only ; 28 ; 0 ; ; ; ; ; ; Logic elements by mode ; ; ; -; -- normal mode ; 11 ; 0 ; +; -- normal mode ; 44 ; 0 ; ; -- arithmetic mode ; 23 ; 0 ; ; ; ; ; -; Total registers ; 25 ; 0 ; -; -- Dedicated logic registers ; 25 / 24624 ( < 1 % ) ; 0 / 24624 ( 0 % ) ; +; Total registers ; 80 ; 0 ; +; -- Dedicated logic registers ; 80 / 24624 ( < 1 % ) ; 0 / 24624 ( 0 % ) ; ; -- I/O registers ; 0 ; 0 ; ; ; ; ; -; Total LABs: partially or completely used ; 4 / 1539 ( < 1 % ) ; 0 / 1539 ( 0 % ) ; +; Total LABs: partially or completely used ; 8 / 1539 ( < 1 % ) ; 0 / 1539 ( 0 % ) ; ; ; ; ; ; Virtual pins ; 0 ; 0 ; -; I/O pins ; 21 ; 0 ; +; I/O pins ; 23 ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; 0 / 132 ( 0 % ) ; -; Total memory bits ; 0 ; 0 ; -; Total RAM block bits ; 0 ; 0 ; -; Clock control block ; 1 / 24 ( 4 % ) ; 0 / 24 ( 0 % ) ; +; Total memory bits ; 2048 ; 0 ; +; Total RAM block bits ; 9216 ; 0 ; +; PLL ; 0 / 4 ( 0 % ) ; 1 / 4 ( 25 % ) ; +; M9K ; 1 / 66 ( 1 % ) ; 0 / 66 ( 0 % ) ; +; Clock control block ; 1 / 24 ( 4 % ) ; 2 / 24 ( 8 % ) ; ; ; ; ; ; Connections ; ; ; -; -- Input Connections ; 8 ; 0 ; +; -- Input Connections ; 10 ; 1 ; ; -- Registered Input Connections ; 0 ; 0 ; -; -- Output Connections ; 8 ; 0 ; +; -- Output Connections ; 9 ; 2 ; ; -- Registered Output Connections ; 0 ; 0 ; ; ; ; ; ; Internal Connections ; ; ; -; -- Total Connections ; 189 ; 5 ; -; -- Registered Connections ; 53 ; 0 ; +; -- Total Connections ; 508 ; 11 ; +; -- Registered Connections ; 161 ; 0 ; ; ; ; ; ; External Connections ; ; ; -; -- Top ; 16 ; 0 ; -; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; -- Top ; 16 ; 3 ; +; -- hard_block:auto_generated_inst ; 3 ; 0 ; ; ; ; ; ; Partition Interface ; ; ; -; -- Input Ports ; 12 ; 0 ; -; -- Output Ports ; 1 ; 0 ; +; -- Input Ports ; 12 ; 1 ; +; -- Output Ports ; 3 ; 2 ; ; -- Bidir Ports ; 8 ; 0 ; ; ; ; ; ; Registered Ports ; ; ; @@ -350,18 +357,18 @@ The pin-out file can be found in D:/GITEA/altera/MainController/output_files/Mai +------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; +------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ -; Address[0] ; 196 ; 7 ; 38 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; Address[1] ; 231 ; 8 ; 14 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; Address[2] ; 234 ; 8 ; 7 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; Address[3] ; 233 ; 8 ; 7 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; Address[4] ; 232 ; 8 ; 14 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; Address[5] ; 235 ; 8 ; 7 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; Address[6] ; 230 ; 8 ; 14 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; Address[7] ; 195 ; 7 ; 38 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; FPGA_CLK ; 31 ; 1 ; 0 ; 16 ; 0 ; 25 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nCE ; 219 ; 8 ; 20 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nOE ; 217 ; 8 ; 20 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nWE ; 218 ; 8 ; 20 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; Address[0] ; 196 ; 7 ; 38 ; 34 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; Address[1] ; 231 ; 8 ; 14 ; 34 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; Address[2] ; 234 ; 8 ; 7 ; 34 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; Address[3] ; 233 ; 8 ; 7 ; 34 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; Address[4] ; 232 ; 8 ; 14 ; 34 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; Address[5] ; 235 ; 8 ; 7 ; 34 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; Address[6] ; 230 ; 8 ; 14 ; 34 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; Address[7] ; 195 ; 7 ; 38 ; 34 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; FPGA_CLK ; 31 ; 1 ; 0 ; 16 ; 0 ; 82 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nCE ; 219 ; 8 ; 20 ; 34 ; 14 ; 15 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nOE ; 217 ; 8 ; 20 ; 34 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nWE ; 218 ; 8 ; 20 ; 34 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ @@ -371,23 +378,25 @@ The pin-out file can be found in D:/GITEA/altera/MainController/output_files/Mai ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; +------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ ; FPGA_LED_1 ; 166 ; 6 ; 53 ; 22 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; FPGA_LED_2 ; 167 ; 6 ; 53 ; 23 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; FPGA_LED_3 ; 168 ; 6 ; 53 ; 23 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Bidir Pins ; -+---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; -+---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+----------------------+---------------------+ -; Data[0] ; 194 ; 7 ; 40 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; Data[1] ; 189 ; 7 ; 45 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; Data[2] ; 188 ; 7 ; 45 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; Data[3] ; 187 ; 7 ; 45 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; Data[4] ; 226 ; 8 ; 16 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; Data[5] ; 224 ; 8 ; 16 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; Data[6] ; 223 ; 8 ; 18 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; Data[7] ; 221 ; 8 ; 18 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -+---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+----------------------+---------------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Bidir Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+----------------------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+----------------------------------+---------------------+ +; Data[0] ; 194 ; 7 ; 40 ; 34 ; 7 ; 2 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; RAM:inst3|data0[0]~en (inverted) ; - ; +; Data[1] ; 189 ; 7 ; 45 ; 34 ; 21 ; 2 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; RAM:inst3|data0[1]~en (inverted) ; - ; +; Data[2] ; 188 ; 7 ; 45 ; 34 ; 14 ; 2 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; RAM:inst3|data0[2]~en (inverted) ; - ; +; Data[3] ; 187 ; 7 ; 45 ; 34 ; 7 ; 2 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; RAM:inst3|data0[3]~en (inverted) ; - ; +; Data[4] ; 226 ; 8 ; 16 ; 34 ; 14 ; 2 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; RAM:inst3|data0[4]~en (inverted) ; - ; +; Data[5] ; 224 ; 8 ; 16 ; 34 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; RAM:inst3|data0[5]~en (inverted) ; - ; +; Data[6] ; 223 ; 8 ; 18 ; 34 ; 21 ; 2 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; RAM:inst3|data0[6]~en (inverted) ; - ; +; Data[7] ; 221 ; 8 ; 18 ; 34 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; RAM:inst3|data0[7]~en (inverted) ; - ; ++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+----------------------------------+---------------------+ +-------------------------------------------------------------------------------------------------------------------------------------+ @@ -408,6 +417,8 @@ The pin-out file can be found in D:/GITEA/altera/MainController/output_files/Mai ; 158 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; ; 158 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; ; 162 ; DIFFIO_R4n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; +; 167 ; DIFFIO_R3n, nWE ; Use as regular IO ; FPGA_LED_2 ; Dual Purpose Pin ; +; 168 ; DIFFIO_R3p, nOE ; Use as regular IO ; FPGA_LED_3 ; Dual Purpose Pin ; ; 194 ; DIFFIO_T20p, PADD0 ; Use as regular IO ; Data[0] ; Dual Purpose Pin ; ; 196 ; DIFFIO_T19n, PADD1 ; Use as regular IO ; Address[0] ; Dual Purpose Pin ; ; 218 ; DIFFIO_T10n, DATA2 ; Use as regular IO ; nWE ; Dual Purpose Pin ; @@ -431,7 +442,7 @@ The pin-out file can be found in D:/GITEA/altera/MainController/output_files/Mai ; 3 ; 0 / 20 ( 0 % ) ; 2.5V ; -- ; ; 4 ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; ; 5 ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; -; 6 ; 2 / 15 ( 13 % ) ; 3.3V ; -- ; +; 6 ; 4 / 15 ( 27 % ) ; 3.3V ; -- ; ; 7 ; 6 / 20 ( 30 % ) ; 3.3V ; -- ; ; 8 ; 13 / 22 ( 59 % ) ; 3.3V ; -- ; +----------+------------------+---------------+--------------+ @@ -609,8 +620,8 @@ The pin-out file can be found in D:/GITEA/altera/MainController/output_files/Mai ; 164 ; 163 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; 165 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 166 ; 164 ; 6 ; FPGA_LED_1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 167 ; 165 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; 168 ; 166 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 167 ; 165 ; 6 ; FPGA_LED_2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 168 ; 166 ; 6 ; FPGA_LED_3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 169 ; 167 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; ; 170 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 171 ; 169 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; @@ -687,14 +698,71 @@ The pin-out file can be found in D:/GITEA/altera/MainController/output_files/Mai Note: Pin directions (input, output or bidir) are based on device operating in user mode. -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+--------------+ -; |MainController ; 34 (0) ; 25 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; 9 (0) ; 0 (0) ; 25 (0) ; |MainController ; work ; -; |LedBlink:inst2| ; 34 (34) ; 25 (25) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 25 (25) ; |MainController|LedBlink:inst2 ; work ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+--------------+ ++-------------------------------------------------------------------------------------------------------------+ +; PLL Summary ; ++-------------------------------+-----------------------------------------------------------------------------+ +; Name ; AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|pll1 ; ++-------------------------------+-----------------------------------------------------------------------------+ +; SDC pin name ; inst|altpll_component|auto_generated|pll1 ; +; PLL mode ; Normal ; +; Compensate clock ; clock0 ; +; Compensated input/output pins ; -- ; +; Switchover type ; -- ; +; Input frequency 0 ; 25.0 MHz ; +; Input frequency 1 ; -- ; +; Nominal PFD frequency ; 25.0 MHz ; +; Nominal VCO frequency ; 600.0 MHz ; +; VCO post scale K counter ; 2 ; +; VCO frequency control ; Auto ; +; VCO phase shift step ; 208 ps ; +; VCO multiply ; -- ; +; VCO divide ; -- ; +; Freq min lock ; 12.5 MHz ; +; Freq max lock ; 27.09 MHz ; +; M VCO Tap ; 0 ; +; M Initial ; 1 ; +; M value ; 24 ; +; N value ; 1 ; +; Charge pump current ; setting 1 ; +; Loop filter resistance ; setting 24 ; +; Loop filter capacitance ; setting 0 ; +; Bandwidth ; 450 kHz to 980 kHz ; +; Bandwidth type ; Medium ; +; Real time reconfigurable ; Off ; +; Scan chain MIF file ; -- ; +; Preserve PLL counter order ; Off ; +; PLL location ; PLL_1 ; +; Inclk0 signal ; FPGA_CLK ; +; Inclk1 signal ; -- ; +; Inclk0 signal type ; Dedicated Pin ; +; Inclk1 signal type ; -- ; ++-------------------------------+-----------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Usage ; ++-----------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+--------------------------------------------------+ +; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ; ++-----------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+--------------------------------------------------+ +; AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_clk[0] ; clock0 ; 4 ; 1 ; 100.0 MHz ; 0 (0 ps) ; 7.50 (208 ps) ; 50/50 ; C0 ; 6 ; 3/3 Even ; -- ; 1 ; 0 ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_clk[1] ; clock1 ; 8 ; 1 ; 200.0 MHz ; 0 (0 ps) ; 15.00 (208 ps) ; 50/50 ; C1 ; 3 ; 2/1 Odd ; -- ; 1 ; 0 ; inst|altpll_component|auto_generated|pll1|clk[1] ; ++-----------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+--------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++--------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++--------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------+--------------+ +; |MainController ; 95 (0) ; 80 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 23 ; 0 ; 15 (0) ; 28 (0) ; 52 (0) ; |MainController ; work ; +; |AlteraPLL:inst| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |MainController|AlteraPLL:inst ; work ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |MainController|AlteraPLL:inst|altpll:altpll_component ; work ; +; |AlteraPLL_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |MainController|AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated ; work ; +; |LedBlink:inst2| ; 36 (36) ; 25 (25) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 25 (25) ; |MainController|LedBlink:inst2 ; work ; +; |RAM:inst3| ; 59 (59) ; 55 (55) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 28 (28) ; 27 (27) ; |MainController|RAM:inst3 ; work ; +; |altsyncram:memory_rtl_0| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |MainController|RAM:inst3|altsyncram:memory_rtl_0 ; work ; +; |altsyncram_8bi1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |MainController|RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated ; work ; ++--------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -704,212 +772,402 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; +------------+----------+---------------+---------------+-----------------------+-----+------+ ; FPGA_LED_1 ; Output ; -- ; -- ; -- ; -- ; -- ; -; Address[7] ; Input ; -- ; -- ; -- ; -- ; -- ; -; Address[6] ; Input ; -- ; -- ; -- ; -- ; -- ; -; Address[5] ; Input ; -- ; -- ; -- ; -- ; -- ; -; Address[4] ; Input ; -- ; -- ; -- ; -- ; -- ; -; Address[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -; Address[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -; Address[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -; Address[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -; nOE ; Input ; -- ; -- ; -- ; -- ; -- ; -; nWE ; Input ; -- ; -- ; -- ; -- ; -- ; -; nCE ; Input ; -- ; -- ; -- ; -- ; -- ; -; Data[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; Data[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; Data[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; Data[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; Data[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; Data[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; Data[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; Data[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; FPGA_LED_2 ; Output ; -- ; -- ; -- ; -- ; -- ; +; FPGA_LED_3 ; Output ; -- ; -- ; -- ; -- ; -- ; +; Data[7] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Data[6] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Data[5] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Data[4] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Data[3] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Data[2] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Data[1] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Data[0] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; ; FPGA_CLK ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; nCE ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; nWE ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Address[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Address[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Address[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Address[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Address[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Address[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Address[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Address[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; nOE ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +------------+----------+---------------+---------------+-----------------------+-----+------+ -+---------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+---------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+---------------------+-------------------+---------+ -; Address[7] ; ; ; -; Address[6] ; ; ; -; Address[5] ; ; ; -; Address[4] ; ; ; -; Address[3] ; ; ; -; Address[2] ; ; ; -; Address[1] ; ; ; -; Address[0] ; ; ; -; nOE ; ; ; -; nWE ; ; ; -; nCE ; ; ; -; Data[7] ; ; ; -; Data[6] ; ; ; -; Data[5] ; ; ; -; Data[4] ; ; ; -; Data[3] ; ; ; -; Data[2] ; ; ; -; Data[1] ; ; ; -; Data[0] ; ; ; -; FPGA_CLK ; ; ; -+---------------------+-------------------+---------+ ++--------------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++--------------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++--------------------------------------------------------------------------------------+-------------------+---------+ +; Data[7] ; ; ; +; - RAM:inst3|memory_rtl_0_bypass[24]~feeder ; 0 ; 6 ; +; - RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0 ; 0 ; 6 ; +; Data[6] ; ; ; +; - RAM:inst3|memory_rtl_0_bypass[23]~feeder ; 0 ; 6 ; +; - RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0 ; 0 ; 6 ; +; Data[5] ; ; ; +; - RAM:inst3|memory_rtl_0_bypass[22]~feeder ; 0 ; 6 ; +; - RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0 ; 0 ; 6 ; +; Data[4] ; ; ; +; - RAM:inst3|memory_rtl_0_bypass[21]~feeder ; 0 ; 6 ; +; - RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0 ; 0 ; 6 ; +; Data[3] ; ; ; +; - RAM:inst3|memory_rtl_0_bypass[20] ; 0 ; 6 ; +; - RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0 ; 0 ; 6 ; +; Data[2] ; ; ; +; - RAM:inst3|memory_rtl_0_bypass[19] ; 0 ; 6 ; +; - RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0 ; 0 ; 6 ; +; Data[1] ; ; ; +; - RAM:inst3|memory_rtl_0_bypass[18] ; 1 ; 6 ; +; - RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0 ; 1 ; 6 ; +; Data[0] ; ; ; +; - RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0 ; 1 ; 6 ; +; - RAM:inst3|memory_rtl_0_bypass[17] ; 1 ; 6 ; +; FPGA_CLK ; ; ; +; nCE ; ; ; +; - RAM:inst3|ce0Prev ; 0 ; 6 ; +; - RAM:inst3|Selector74~0 ; 0 ; 6 ; +; - RAM:inst3|addr~0 ; 0 ; 6 ; +; - RAM:inst3|addr~1 ; 0 ; 6 ; +; - RAM:inst3|addr~2 ; 0 ; 6 ; +; - RAM:inst3|addr~3 ; 0 ; 6 ; +; - RAM:inst3|addr~4 ; 0 ; 6 ; +; - RAM:inst3|addr~5 ; 0 ; 6 ; +; - RAM:inst3|addr~6 ; 0 ; 6 ; +; - RAM:inst3|addr~7 ; 0 ; 6 ; +; - RAM:inst3|Selector4~0 ; 0 ; 6 ; +; - RAM:inst3|Selector3~1 ; 0 ; 6 ; +; - RAM:inst3|Selector3~2 ; 0 ; 6 ; +; - RAM:inst3|Selector2~0 ; 0 ; 6 ; +; - RAM:inst3|Selector3~3 ; 0 ; 6 ; +; nWE ; ; ; +; - RAM:inst3|we0Prev ; 0 ; 6 ; +; - RAM:inst3|memory~48 ; 0 ; 6 ; +; Address[0] ; ; ; +; - RAM:inst3|addr~0 ; 0 ; 6 ; +; Address[1] ; ; ; +; - RAM:inst3|addr~1 ; 1 ; 6 ; +; Address[2] ; ; ; +; - RAM:inst3|addr~2 ; 1 ; 6 ; +; Address[3] ; ; ; +; - RAM:inst3|addr~3 ; 1 ; 6 ; +; Address[4] ; ; ; +; - RAM:inst3|addr~4 ; 0 ; 6 ; +; Address[5] ; ; ; +; - RAM:inst3|addr~5 ; 0 ; 6 ; +; Address[6] ; ; ; +; - RAM:inst3|addr~6 ; 0 ; 6 ; +; Address[7] ; ; ; +; - RAM:inst3|addr~7 ; 0 ; 6 ; +; nOE ; ; ; +; - RAM:inst3|Selector4~0 ; 0 ; 6 ; +; - RAM:inst3|oe0Prev ; 0 ; 6 ; +; - RAM:inst3|Selector3~0 ; 0 ; 6 ; +; - RAM:inst3|Selector3~3 ; 0 ; 6 ; ++--------------------------------------------------------------------------------------+-------------------+---------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+----------------------------+--------------------+---------+-------------+--------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+----------------------------+--------------------+---------+-------------+--------+----------------------+------------------+---------------------------+ -; FPGA_CLK ; PIN_31 ; 25 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ; -; LedBlink:inst2|LessThan0~8 ; LCCOMB_X51_Y13_N26 ; 25 ; Sync. clear ; no ; -- ; -- ; -- ; -+----------------------------+--------------------+---------+-------------+--------+----------------------+------------------+---------------------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-----------------------------+--------------------+---------+---------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-----------------------------+--------------------+---------+---------------+--------+----------------------+------------------+---------------------------+ +; FPGA_CLK ; PIN_31 ; 2 ; Clock ; no ; -- ; -- ; -- ; +; FPGA_CLK ; PIN_31 ; 81 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; +; LedBlink:inst2|LessThan0~10 ; LCCOMB_X26_Y28_N30 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ; +; RAM:inst3|Selector3~2 ; LCCOMB_X27_Y29_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; RAM:inst3|Selector74~0 ; LCCOMB_X27_Y29_N26 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; RAM:inst3|data0[0]~en ; FF_X35_Y33_N23 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; RAM:inst3|data0[1]~en ; FF_X35_Y33_N21 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; RAM:inst3|data0[2]~en ; FF_X35_Y33_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; RAM:inst3|data0[3]~en ; FF_X35_Y33_N9 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; RAM:inst3|data0[4]~en ; FF_X35_Y33_N7 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; RAM:inst3|data0[5]~en ; FF_X35_Y33_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; RAM:inst3|data0[6]~en ; FF_X35_Y33_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; RAM:inst3|data0[7]~en ; FF_X35_Y33_N17 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; RAM:inst3|memory~48 ; LCCOMB_X27_Y29_N20 ; 3 ; Write enable ; no ; -- ; -- ; -- ; +; RAM:inst3|stateMM0.Waiting ; FF_X27_Y29_N9 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; ++-----------------------------+--------------------+---------+---------------+--------+----------------------+------------------+---------------------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; FPGA_CLK ; PIN_31 ; 25 ; 13 ; Global Clock ; GCLK4 ; -- ; -+----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-----------------------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-----------------------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_clk[0] ; PLL_1 ; 1 ; 0 ; Global Clock ; GCLK3 ; -- ; +; AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_clk[1] ; PLL_1 ; 1 ; 0 ; Global Clock ; GCLK4 ; -- ; +; FPGA_CLK ; PIN_31 ; 81 ; 0 ; Global Clock ; GCLK2 ; -- ; ++-----------------------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -+-----------------------------------------+ -; Non-Global High Fan-Out Signals ; -+-------------------------------+---------+ -; Name ; Fan-Out ; -+-------------------------------+---------+ -; LedBlink:inst2|LessThan0~8 ; 25 ; -; LedBlink:inst2|counter[4] ; 3 ; -; LedBlink:inst2|counter[16] ; 3 ; -; LedBlink:inst2|counter[15] ; 3 ; -; LedBlink:inst2|ledBuf ; 2 ; -; LedBlink:inst2|counter[11] ; 2 ; -; LedBlink:inst2|counter[10] ; 2 ; -; LedBlink:inst2|counter[9] ; 2 ; -; LedBlink:inst2|counter[8] ; 2 ; -; LedBlink:inst2|counter[7] ; 2 ; -; LedBlink:inst2|counter[5] ; 2 ; -; LedBlink:inst2|counter[3] ; 2 ; -; LedBlink:inst2|counter[2] ; 2 ; -; LedBlink:inst2|counter[1] ; 2 ; -; LedBlink:inst2|counter[0] ; 2 ; -; LedBlink:inst2|counter[6] ; 2 ; -; LedBlink:inst2|counter[12] ; 2 ; -; LedBlink:inst2|counter[13] ; 2 ; -; LedBlink:inst2|counter[23] ; 2 ; -; LedBlink:inst2|counter[22] ; 2 ; -; LedBlink:inst2|counter[21] ; 2 ; -; LedBlink:inst2|counter[20] ; 2 ; -; LedBlink:inst2|counter[19] ; 2 ; -; LedBlink:inst2|counter[18] ; 2 ; -; LedBlink:inst2|counter[17] ; 2 ; -; LedBlink:inst2|counter[14] ; 2 ; -; LedBlink:inst2|ledBuf~0 ; 1 ; -; LedBlink:inst2|LessThan0~7 ; 1 ; -; LedBlink:inst2|LessThan0~6 ; 1 ; -; LedBlink:inst2|LessThan0~5 ; 1 ; -; LedBlink:inst2|LessThan0~4 ; 1 ; -; LedBlink:inst2|LessThan0~3 ; 1 ; -; LedBlink:inst2|LessThan0~2 ; 1 ; -; LedBlink:inst2|LessThan0~1 ; 1 ; -; LedBlink:inst2|LessThan0~0 ; 1 ; -; LedBlink:inst2|counter[23]~70 ; 1 ; -; LedBlink:inst2|counter[22]~69 ; 1 ; -; LedBlink:inst2|counter[22]~68 ; 1 ; -; LedBlink:inst2|counter[21]~67 ; 1 ; -; LedBlink:inst2|counter[21]~66 ; 1 ; -; LedBlink:inst2|counter[20]~65 ; 1 ; -; LedBlink:inst2|counter[20]~64 ; 1 ; -; LedBlink:inst2|counter[19]~63 ; 1 ; -; LedBlink:inst2|counter[19]~62 ; 1 ; -; LedBlink:inst2|counter[18]~61 ; 1 ; -; LedBlink:inst2|counter[18]~60 ; 1 ; -; LedBlink:inst2|counter[17]~59 ; 1 ; -; LedBlink:inst2|counter[17]~58 ; 1 ; -; LedBlink:inst2|counter[16]~57 ; 1 ; -; LedBlink:inst2|counter[16]~56 ; 1 ; -; LedBlink:inst2|counter[15]~55 ; 1 ; -; LedBlink:inst2|counter[15]~54 ; 1 ; -; LedBlink:inst2|counter[14]~53 ; 1 ; -; LedBlink:inst2|counter[14]~52 ; 1 ; -; LedBlink:inst2|counter[13]~51 ; 1 ; -; LedBlink:inst2|counter[13]~50 ; 1 ; -; LedBlink:inst2|counter[12]~49 ; 1 ; -; LedBlink:inst2|counter[12]~48 ; 1 ; -; LedBlink:inst2|counter[11]~47 ; 1 ; -; LedBlink:inst2|counter[11]~46 ; 1 ; -; LedBlink:inst2|counter[10]~45 ; 1 ; -; LedBlink:inst2|counter[10]~44 ; 1 ; -; LedBlink:inst2|counter[9]~43 ; 1 ; -; LedBlink:inst2|counter[9]~42 ; 1 ; -; LedBlink:inst2|counter[8]~41 ; 1 ; -; LedBlink:inst2|counter[8]~40 ; 1 ; -; LedBlink:inst2|counter[7]~39 ; 1 ; -; LedBlink:inst2|counter[7]~38 ; 1 ; -; LedBlink:inst2|counter[6]~37 ; 1 ; -; LedBlink:inst2|counter[6]~36 ; 1 ; -; LedBlink:inst2|counter[5]~35 ; 1 ; -; LedBlink:inst2|counter[5]~34 ; 1 ; -; LedBlink:inst2|counter[4]~33 ; 1 ; -; LedBlink:inst2|counter[4]~32 ; 1 ; -; LedBlink:inst2|counter[3]~31 ; 1 ; -; LedBlink:inst2|counter[3]~30 ; 1 ; -; LedBlink:inst2|counter[2]~29 ; 1 ; -; LedBlink:inst2|counter[2]~28 ; 1 ; -; LedBlink:inst2|counter[1]~27 ; 1 ; -; LedBlink:inst2|counter[1]~26 ; 1 ; -; LedBlink:inst2|counter[0]~25 ; 1 ; -; LedBlink:inst2|counter[0]~24 ; 1 ; -+-------------------------------+---------+ ++--------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++----------------------------------------------------------------------------------------+---------+ +; RAM:inst3|stateMM0.Waiting ; 30 ; +; LedBlink:inst2|LessThan0~10 ; 24 ; +; RAM:inst3|Selector74~0 ; 16 ; +; nCE~input ; 15 ; +; RAM:inst3|ce0Prev ; 13 ; +; RAM:inst3|memory~39 ; 8 ; +; nOE~input ; 4 ; +; LedBlink:inst2|counter[16] ; 4 ; +; LedBlink:inst2|counter[15] ; 4 ; +; RAM:inst3|addr~7 ; 3 ; +; RAM:inst3|addr~6 ; 3 ; +; RAM:inst3|addr~5 ; 3 ; +; RAM:inst3|addr~4 ; 3 ; +; RAM:inst3|addr~3 ; 3 ; +; RAM:inst3|addr~2 ; 3 ; +; RAM:inst3|addr~1 ; 3 ; +; RAM:inst3|addr~0 ; 3 ; +; RAM:inst3|memory~48 ; 3 ; +; LedBlink:inst2|counter[13] ; 3 ; +; LedBlink:inst2|counter[4] ; 3 ; +; nWE~input ; 2 ; +; Data[0]~input ; 2 ; +; Data[1]~input ; 2 ; +; Data[2]~input ; 2 ; +; Data[3]~input ; 2 ; +; Data[4]~input ; 2 ; +; Data[5]~input ; 2 ; +; Data[6]~input ; 2 ; +; Data[7]~input ; 2 ; +; RAM:inst3|Selector3~2 ; 2 ; +; RAM:inst3|Selector3~1 ; 2 ; +; RAM:inst3|addr[7] ; 2 ; +; RAM:inst3|addr[6] ; 2 ; +; RAM:inst3|addr[5] ; 2 ; +; RAM:inst3|addr[4] ; 2 ; +; RAM:inst3|addr[3] ; 2 ; +; RAM:inst3|addr[2] ; 2 ; +; RAM:inst3|addr[1] ; 2 ; +; RAM:inst3|addr[0] ; 2 ; +; RAM:inst3|stateMM0.Writing ; 2 ; +; LedBlink:inst2|LessThan0~9 ; 2 ; +; LedBlink:inst2|LessThan0~6 ; 2 ; +; LedBlink:inst2|LessThan0~5 ; 2 ; +; LedBlink:inst2|LessThan0~4 ; 2 ; +; LedBlink:inst2|ledBuf ; 2 ; +; LedBlink:inst2|counter[23] ; 2 ; +; LedBlink:inst2|counter[22] ; 2 ; +; LedBlink:inst2|counter[21] ; 2 ; +; LedBlink:inst2|counter[20] ; 2 ; +; LedBlink:inst2|counter[19] ; 2 ; +; LedBlink:inst2|counter[18] ; 2 ; +; LedBlink:inst2|counter[17] ; 2 ; +; LedBlink:inst2|counter[14] ; 2 ; +; LedBlink:inst2|counter[12] ; 2 ; +; LedBlink:inst2|counter[11] ; 2 ; +; LedBlink:inst2|counter[10] ; 2 ; +; LedBlink:inst2|counter[9] ; 2 ; +; LedBlink:inst2|counter[8] ; 2 ; +; LedBlink:inst2|counter[7] ; 2 ; +; LedBlink:inst2|counter[6] ; 2 ; +; LedBlink:inst2|counter[5] ; 2 ; +; LedBlink:inst2|counter[3] ; 2 ; +; LedBlink:inst2|counter[2] ; 2 ; +; LedBlink:inst2|counter[1] ; 2 ; +; LedBlink:inst2|counter[0] ; 2 ; +; Address[7]~input ; 1 ; +; Address[6]~input ; 1 ; +; Address[5]~input ; 1 ; +; Address[4]~input ; 1 ; +; Address[3]~input ; 1 ; +; Address[2]~input ; 1 ; +; Address[1]~input ; 1 ; +; Address[0]~input ; 1 ; +; FPGA_CLK~input ; 1 ; +; RAM:inst3|stateMM0.Waiting~_wirecell ; 1 ; +; RAM:inst3|Selector3~3 ; 1 ; +; RAM:inst3|Selector2~0 ; 1 ; +; RAM:inst3|Selector3~0 ; 1 ; +; RAM:inst3|oe0Prev ; 1 ; +; RAM:inst3|Selector4~0 ; 1 ; +; RAM:inst3|we0Prev ; 1 ; +; RAM:inst3|memory~47 ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[17] ; 1 ; +; RAM:inst3|memory~46 ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[18] ; 1 ; +; RAM:inst3|memory~45 ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[19] ; 1 ; +; RAM:inst3|memory~44 ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[20] ; 1 ; +; RAM:inst3|memory~43 ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[21] ; 1 ; +; RAM:inst3|memory~42 ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[22] ; 1 ; +; RAM:inst3|memory~41 ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[23] ; 1 ; +; RAM:inst3|stateMM0.Reading ; 1 ; +; RAM:inst3|memory~40 ; 1 ; +; RAM:inst3|memory~38 ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[14] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[16] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[15] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[13] ; 1 ; +; RAM:inst3|memory~37 ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[10] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[12] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[11] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[9] ; 1 ; +; RAM:inst3|memory~36 ; 1 ; +; RAM:inst3|memory~35 ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[6] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[8] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[7] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[5] ; 1 ; +; RAM:inst3|memory~34 ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[2] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[4] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[3] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[1] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[0] ; 1 ; +; RAM:inst3|memory_rtl_0_bypass[24] ; 1 ; +; RAM:inst3|data0[0]~en ; 1 ; +; RAM:inst3|data0[0]~reg0 ; 1 ; +; RAM:inst3|data0[1]~en ; 1 ; +; RAM:inst3|data0[1]~reg0 ; 1 ; +; RAM:inst3|data0[2]~en ; 1 ; +; RAM:inst3|data0[2]~reg0 ; 1 ; +; RAM:inst3|data0[3]~en ; 1 ; +; RAM:inst3|data0[3]~reg0 ; 1 ; +; RAM:inst3|data0[4]~en ; 1 ; +; RAM:inst3|data0[4]~reg0 ; 1 ; +; RAM:inst3|data0[5]~en ; 1 ; +; RAM:inst3|data0[5]~reg0 ; 1 ; +; RAM:inst3|data0[6]~en ; 1 ; +; RAM:inst3|data0[6]~reg0 ; 1 ; +; RAM:inst3|data0[7]~en ; 1 ; +; RAM:inst3|data0[7]~reg0 ; 1 ; +; LedBlink:inst2|ledBuf~0 ; 1 ; +; LedBlink:inst2|LessThan0~8 ; 1 ; +; LedBlink:inst2|LessThan0~7 ; 1 ; +; LedBlink:inst2|LessThan0~3 ; 1 ; +; LedBlink:inst2|LessThan0~2 ; 1 ; +; LedBlink:inst2|LessThan0~1 ; 1 ; +; LedBlink:inst2|LessThan0~0 ; 1 ; +; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a1 ; 1 ; +; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a2 ; 1 ; +; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a3 ; 1 ; +; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a4 ; 1 ; +; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a5 ; 1 ; +; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a6 ; 1 ; +; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a7 ; 1 ; +; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0 ; 1 ; +; LedBlink:inst2|counter[23]~70 ; 1 ; +; LedBlink:inst2|counter[22]~69 ; 1 ; +; LedBlink:inst2|counter[22]~68 ; 1 ; +; LedBlink:inst2|counter[21]~67 ; 1 ; +; LedBlink:inst2|counter[21]~66 ; 1 ; +; LedBlink:inst2|counter[20]~65 ; 1 ; +; LedBlink:inst2|counter[20]~64 ; 1 ; +; LedBlink:inst2|counter[19]~63 ; 1 ; +; LedBlink:inst2|counter[19]~62 ; 1 ; +; LedBlink:inst2|counter[18]~61 ; 1 ; +; LedBlink:inst2|counter[18]~60 ; 1 ; +; LedBlink:inst2|counter[17]~59 ; 1 ; +; LedBlink:inst2|counter[17]~58 ; 1 ; +; LedBlink:inst2|counter[16]~57 ; 1 ; +; LedBlink:inst2|counter[16]~56 ; 1 ; +; LedBlink:inst2|counter[15]~55 ; 1 ; +; LedBlink:inst2|counter[15]~54 ; 1 ; +; LedBlink:inst2|counter[14]~53 ; 1 ; +; LedBlink:inst2|counter[14]~52 ; 1 ; +; LedBlink:inst2|counter[13]~51 ; 1 ; +; LedBlink:inst2|counter[13]~50 ; 1 ; +; LedBlink:inst2|counter[12]~49 ; 1 ; +; LedBlink:inst2|counter[12]~48 ; 1 ; +; LedBlink:inst2|counter[11]~47 ; 1 ; +; LedBlink:inst2|counter[11]~46 ; 1 ; +; LedBlink:inst2|counter[10]~45 ; 1 ; +; LedBlink:inst2|counter[10]~44 ; 1 ; +; LedBlink:inst2|counter[9]~43 ; 1 ; +; LedBlink:inst2|counter[9]~42 ; 1 ; +; LedBlink:inst2|counter[8]~41 ; 1 ; +; LedBlink:inst2|counter[8]~40 ; 1 ; +; LedBlink:inst2|counter[7]~39 ; 1 ; +; LedBlink:inst2|counter[7]~38 ; 1 ; +; LedBlink:inst2|counter[6]~37 ; 1 ; +; LedBlink:inst2|counter[6]~36 ; 1 ; +; LedBlink:inst2|counter[5]~35 ; 1 ; +; LedBlink:inst2|counter[5]~34 ; 1 ; +; LedBlink:inst2|counter[4]~33 ; 1 ; +; LedBlink:inst2|counter[4]~32 ; 1 ; +; LedBlink:inst2|counter[3]~31 ; 1 ; +; LedBlink:inst2|counter[3]~30 ; 1 ; +; LedBlink:inst2|counter[2]~29 ; 1 ; +; LedBlink:inst2|counter[2]~28 ; 1 ; +; LedBlink:inst2|counter[1]~27 ; 1 ; +; LedBlink:inst2|counter[1]~26 ; 1 ; +; LedBlink:inst2|counter[0]~25 ; 1 ; +; LedBlink:inst2|counter[0]~24 ; 1 ; +; AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_fbout ; 1 ; ++----------------------------------------------------------------------------------------+---------+ -+-----------------------------------------------+ -; Routing Usage Summary ; -+-----------------------+-----------------------+ -; Routing Resource Type ; Usage ; -+-----------------------+-----------------------+ -; Block interconnects ; 20 / 71,559 ( < 1 % ) ; -; C16 interconnects ; 0 / 2,597 ( 0 % ) ; -; C4 interconnects ; 4 / 46,848 ( < 1 % ) ; -; Direct links ; 11 / 71,559 ( < 1 % ) ; -; Global clocks ; 1 / 20 ( 5 % ) ; -; Local interconnects ; 30 / 24,624 ( < 1 % ) ; -; R24 interconnects ; 0 / 2,496 ( 0 % ) ; -; R4 interconnects ; 4 / 62,424 ( < 1 % ) ; -+-----------------------+-----------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++-----------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------+----------------------+-----------------+-----------------+---------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ; ++-----------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------+----------------------+-----------------+-----------------+---------------+ +; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 256 ; 8 ; 256 ; 8 ; yes ; no ; yes ; no ; 2048 ; 256 ; 8 ; 256 ; 8 ; 2048 ; 1 ; None ; M9K_X33_Y29_N0 ; Old data ; Old data ; Old data ; No - Unknown ; ++-----------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------+----------------------+-----------------+-----------------+---------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. -+--------------------------------------------------------------------------+ -; LAB Logic Elements ; -+--------------------------------------------+-----------------------------+ -; Number of Logic Elements (Average = 8.50) ; Number of LABs (Total = 4) ; -+--------------------------------------------+-----------------------------+ -; 1 ; 2 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 2 ; -+--------------------------------------------+-----------------------------+ ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 114 / 71,559 ( < 1 % ) ; +; C16 interconnects ; 25 / 2,597 ( < 1 % ) ; +; C4 interconnects ; 119 / 46,848 ( < 1 % ) ; +; Direct links ; 6 / 71,559 ( < 1 % ) ; +; Global clocks ; 3 / 20 ( 15 % ) ; +; Local interconnects ; 62 / 24,624 ( < 1 % ) ; +; R24 interconnects ; 25 / 2,496 ( 1 % ) ; +; R4 interconnects ; 118 / 62,424 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 11.88) ; Number of LABs (Total = 8) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 2 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 1 ; +; 15 ; 0 ; +; 16 ; 4 ; ++---------------------------------------------+-----------------------------+ +------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+-----------------------------+ -; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 4) ; +; LAB-wide Signals (Average = 1.63) ; Number of LABs (Total = 8) ; +------------------------------------+-----------------------------+ -; 1 Clock ; 3 ; +; 1 Clock ; 8 ; +; 1 Clock enable ; 4 ; ; 1 Sync. clear ; 1 ; +------------------------------------+-----------------------------+ @@ -917,16 +1175,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+-----------------------------+ -; Number of Signals Sourced (Average = 14.75) ; Number of LABs (Total = 4) ; +; Number of Signals Sourced (Average = 20.75) ; Number of LABs (Total = 8) ; +----------------------------------------------+-----------------------------+ ; 0 ; 0 ; -; 1 ; 1 ; -; 2 ; 1 ; +; 1 ; 0 ; +; 2 ; 0 ; ; 3 ; 0 ; ; 4 ; 0 ; -; 5 ; 0 ; +; 5 ; 1 ; ; 6 ; 0 ; -; 7 ; 0 ; +; 7 ; 1 ; ; 8 ; 0 ; ; 9 ; 0 ; ; 10 ; 0 ; @@ -936,45 +1194,78 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 14 ; 0 ; ; 15 ; 0 ; ; 16 ; 0 ; -; 17 ; 0 ; +; 17 ; 1 ; ; 18 ; 0 ; ; 19 ; 0 ; ; 20 ; 0 ; ; 21 ; 0 ; ; 22 ; 0 ; -; 23 ; 0 ; +; 23 ; 1 ; ; 24 ; 0 ; ; 25 ; 0 ; ; 26 ; 0 ; ; 27 ; 0 ; -; 28 ; 2 ; +; 28 ; 3 ; +; 29 ; 0 ; +; 30 ; 1 ; +----------------------------------------------+-----------------------------+ +-------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+-----------------------------+ -; Number of Signals Sourced Out (Average = 2.00) ; Number of LABs (Total = 4) ; +; Number of Signals Sourced Out (Average = 7.00) ; Number of LABs (Total = 8) ; +-------------------------------------------------+-----------------------------+ ; 0 ; 0 ; -; 1 ; 3 ; -; 2 ; 0 ; -; 3 ; 0 ; +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 1 ; ; 4 ; 0 ; ; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 1 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 1 ; +-------------------------------------------------+-----------------------------+ +---------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +---------------------------------------------+-----------------------------+ -; Number of Distinct Inputs (Average = 3.00) ; Number of LABs (Total = 4) ; +; Number of Distinct Inputs (Average = 8.75) ; Number of LABs (Total = 8) ; +---------------------------------------------+-----------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; -; 2 ; 2 ; -; 3 ; 0 ; -; 4 ; 2 ; +; 2 ; 0 ; +; 3 ; 2 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 1 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 1 ; +---------------------------------------------+-----------------------------+ @@ -984,10 +1275,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; I/O Rules Statistic ; Total ; +----------------------------------+-------+ ; Total I/O Rules ; 30 ; -; Number of I/O Rules Passed ; 10 ; +; Number of I/O Rules Passed ; 9 ; ; Number of I/O Rules Failed ; 0 ; ; Number of I/O Rules Unchecked ; 0 ; -; Number of I/O Rules Inapplicable ; 20 ; +; Number of I/O Rules Inapplicable ; 21 ; +----------------------------------+-------+ @@ -1016,7 +1307,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; ; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; ; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Pass ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; ; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; ; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ; ; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; @@ -1034,31 +1325,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ ; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ -; Total Pass ; 21 ; 0 ; 21 ; 0 ; 0 ; 21 ; 21 ; 0 ; 21 ; 21 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; 20 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; 0 ; +; Total Pass ; 23 ; 0 ; 23 ; 0 ; 0 ; 23 ; 23 ; 0 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 ; 0 ; 0 ; ; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 0 ; 21 ; 0 ; 21 ; 21 ; 0 ; 0 ; 21 ; 0 ; 0 ; 21 ; 21 ; 21 ; 21 ; 1 ; 21 ; 21 ; 1 ; 21 ; 21 ; 13 ; 21 ; 21 ; 21 ; 21 ; 21 ; 21 ; 0 ; 21 ; 21 ; +; Total Inapplicable ; 0 ; 23 ; 0 ; 23 ; 23 ; 0 ; 0 ; 23 ; 0 ; 0 ; 23 ; 23 ; 23 ; 23 ; 3 ; 23 ; 23 ; 3 ; 23 ; 23 ; 23 ; 23 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 23 ; 23 ; ; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; FPGA_LED_1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Address[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Address[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Address[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Address[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Address[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Address[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Address[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Address[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nOE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nWE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nCE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Data[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Data[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Data[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Data[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Data[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Data[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Data[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; Data[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FPGA_LED_2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FPGA_LED_3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Data[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Data[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Data[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Data[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Data[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Data[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Data[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Data[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ; FPGA_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nCE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nWE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Address[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Address[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Address[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Address[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Address[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Address[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Address[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Address[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nOE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ @@ -1107,6 +1400,9 @@ Info (119006): Selected device EP3C25Q240C8 for design "MainController" Info (21077): Core supply voltage is 1.2V Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C +Info (15535): Implemented PLL "AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|pll1" as Cyclone III PLL type + Info (15099): Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_clk[0] port + Info (15099): Implementing clock multiplication of 8, clock division of 1, and phase shift of 0 degrees (0 ps) for AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_clk[1] port Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info (176445): Device EP3C16Q240C8 is compatible @@ -1118,17 +1414,27 @@ Info (169124): Fitter converted 5 user pins into dedicated programming pins Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 24 Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 162 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Critical Warning (332012): Synopsys Design Constraints File file not found: 'MainController.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained generated clocks found in the design Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. -Info (176353): Automatically promoted node FPGA_CLK~input (placed in PIN 31 (CLK0, DIFFCLK_0p)) +Info (176353): Automatically promoted node AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_1) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info (176353): Automatically promoted node AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C1 of PLL_1) Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info (176353): Automatically promoted node FPGA_CLK~input (placed in PIN 31 (CLK0, DIFFCLK_0p)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176219): No registers were packed into other blocks -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Warning (15058): PLL "AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins +Warning (15064): PLL "AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|pll1" output port clk[0] feeds output pin "FPGA_LED_2~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning (15064): PLL "AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|pll1" output port clk[1] feeds output pin "FPGA_LED_3~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning @@ -1136,28 +1442,18 @@ Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources - Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22 -Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 + Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 0.34 seconds. + Info (170200): Optimizations that may affect the design's timing were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.20 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 Warning (169177): 20 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. - Info (169178): Pin Address[7] uses I/O standard 3.3-V LVTTL at 195 - Info (169178): Pin Address[6] uses I/O standard 3.3-V LVTTL at 230 - Info (169178): Pin Address[5] uses I/O standard 3.3-V LVTTL at 235 - Info (169178): Pin Address[4] uses I/O standard 3.3-V LVTTL at 232 - Info (169178): Pin Address[3] uses I/O standard 3.3-V LVTTL at 233 - Info (169178): Pin Address[2] uses I/O standard 3.3-V LVTTL at 234 - Info (169178): Pin Address[1] uses I/O standard 3.3-V LVTTL at 231 - Info (169178): Pin Address[0] uses I/O standard 3.3-V LVTTL at 196 - Info (169178): Pin nOE uses I/O standard 3.3-V LVTTL at 217 - Info (169178): Pin nWE uses I/O standard 3.3-V LVTTL at 218 - Info (169178): Pin nCE uses I/O standard 3.3-V LVTTL at 219 Info (169178): Pin Data[7] uses I/O standard 3.3-V LVTTL at 221 Info (169178): Pin Data[6] uses I/O standard 3.3-V LVTTL at 223 Info (169178): Pin Data[5] uses I/O standard 3.3-V LVTTL at 224 @@ -1167,21 +1463,23 @@ Warning (169177): 20 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5- Info (169178): Pin Data[1] uses I/O standard 3.3-V LVTTL at 189 Info (169178): Pin Data[0] uses I/O standard 3.3-V LVTTL at 194 Info (169178): Pin FPGA_CLK uses I/O standard 3.3-V LVTTL at 31 -Warning (169064): Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results - Info (169065): Pin Data[7] has a permanently disabled output enable - Info (169065): Pin Data[6] has a permanently disabled output enable - Info (169065): Pin Data[5] has a permanently disabled output enable - Info (169065): Pin Data[4] has a permanently disabled output enable - Info (169065): Pin Data[3] has a permanently disabled output enable - Info (169065): Pin Data[2] has a permanently disabled output enable - Info (169065): Pin Data[1] has a permanently disabled output enable - Info (169065): Pin Data[0] has a permanently disabled output enable + Info (169178): Pin nCE uses I/O standard 3.3-V LVTTL at 219 + Info (169178): Pin nWE uses I/O standard 3.3-V LVTTL at 218 + Info (169178): Pin Address[0] uses I/O standard 3.3-V LVTTL at 196 + Info (169178): Pin Address[1] uses I/O standard 3.3-V LVTTL at 231 + Info (169178): Pin Address[2] uses I/O standard 3.3-V LVTTL at 234 + Info (169178): Pin Address[3] uses I/O standard 3.3-V LVTTL at 233 + Info (169178): Pin Address[4] uses I/O standard 3.3-V LVTTL at 232 + Info (169178): Pin Address[5] uses I/O standard 3.3-V LVTTL at 235 + Info (169178): Pin Address[6] uses I/O standard 3.3-V LVTTL at 230 + Info (169178): Pin Address[7] uses I/O standard 3.3-V LVTTL at 195 + Info (169178): Pin nOE uses I/O standard 3.3-V LVTTL at 217 Info (144001): Generated suppressed messages file D:/GITEA/altera/MainController/output_files/MainController.fit.smsg -Info: Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings Info: Peak virtual memory: 5391 megabytes - Info: Processing ended: Tue Mar 12 16:24:22 2024 + Info: Processing ended: Tue Mar 12 17:46:50 2024 Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:06 + Info: Total CPU time (on all processors): 00:00:05 +----------------------------+ diff --git a/MainController/output_files/MainController.fit.summary b/MainController/output_files/MainController.fit.summary index 97c41d7..a9944fe 100644 --- a/MainController/output_files/MainController.fit.summary +++ b/MainController/output_files/MainController.fit.summary @@ -1,16 +1,16 @@ -Fitter Status : Successful - Tue Mar 12 16:24:21 2024 +Fitter Status : Successful - Tue Mar 12 17:46:50 2024 Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version Revision Name : MainController Top-level Entity Name : MainController Family : Cyclone III Device : EP3C25Q240C8 Timing Models : Final -Total logic elements : 34 / 24,624 ( < 1 % ) - Total combinational functions : 34 / 24,624 ( < 1 % ) - Dedicated logic registers : 25 / 24,624 ( < 1 % ) -Total registers : 25 -Total pins : 21 / 149 ( 14 % ) +Total logic elements : 95 / 24,624 ( < 1 % ) + Total combinational functions : 67 / 24,624 ( < 1 % ) + Dedicated logic registers : 80 / 24,624 ( < 1 % ) +Total registers : 80 +Total pins : 23 / 149 ( 15 % ) Total virtual pins : 0 -Total memory bits : 0 / 608,256 ( 0 % ) +Total memory bits : 2,048 / 608,256 ( < 1 % ) Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % ) -Total PLLs : 0 / 4 ( 0 % ) +Total PLLs : 1 / 4 ( 25 % ) diff --git a/MainController/output_files/MainController.flow.rpt b/MainController/output_files/MainController.flow.rpt index f92f1d4..b51a9ef 100644 --- a/MainController/output_files/MainController.flow.rpt +++ b/MainController/output_files/MainController.flow.rpt @@ -1,5 +1,5 @@ Flow report for MainController -Tue Mar 12 16:24:29 2024 +Tue Mar 12 17:46:57 2024 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -40,22 +40,22 @@ applicable agreement for further details. +----------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+---------------------------------------------+ -; Flow Status ; Successful - Tue Mar 12 16:24:29 2024 ; +; Flow Status ; Successful - Tue Mar 12 17:46:57 2024 ; ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; ; Revision Name ; MainController ; ; Top-level Entity Name ; MainController ; ; Family ; Cyclone III ; ; Device ; EP3C25Q240C8 ; ; Timing Models ; Final ; -; Total logic elements ; 34 / 24,624 ( < 1 % ) ; -; Total combinational functions ; 34 / 24,624 ( < 1 % ) ; -; Dedicated logic registers ; 25 / 24,624 ( < 1 % ) ; -; Total registers ; 25 ; -; Total pins ; 21 / 149 ( 14 % ) ; +; Total logic elements ; 95 / 24,624 ( < 1 % ) ; +; Total combinational functions ; 67 / 24,624 ( < 1 % ) ; +; Dedicated logic registers ; 80 / 24,624 ( < 1 % ) ; +; Total registers ; 80 ; +; Total pins ; 23 / 149 ( 15 % ) ; ; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 608,256 ( 0 % ) ; +; Total memory bits ; 2,048 / 608,256 ( < 1 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; -; Total PLLs ; 0 / 4 ( 0 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; +------------------------------------+---------------------------------------------+ @@ -64,7 +64,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/12/2024 16:24:14 ; +; Start date & time ; 03/12/2024 17:46:43 ; ; Main task ; Compilation ; ; Revision Name ; MainController ; +-------------------+---------------------+ @@ -75,7 +75,7 @@ applicable agreement for further details. +-------------------------------------+--------------------------------+---------------+-------------+----------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+--------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 30902508249626.171024985402028 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 30902508249626.171025480308064 ; -- ; -- ; -- ; ; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ; ; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ; ; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; @@ -97,12 +97,12 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4707 MB ; 00:00:02 ; -; Fitter ; 00:00:04 ; 1.0 ; 5391 MB ; 00:00:06 ; -; Assembler ; 00:00:01 ; 1.0 ; 4590 MB ; 00:00:01 ; +; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4712 MB ; 00:00:02 ; +; Fitter ; 00:00:05 ; 1.0 ; 5391 MB ; 00:00:05 ; +; Assembler ; 00:00:01 ; 1.0 ; 4585 MB ; 00:00:01 ; ; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4700 MB ; 00:00:01 ; -; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4550 MB ; 00:00:01 ; -; Total ; 00:00:09 ; -- ; -- ; 00:00:11 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4565 MB ; 00:00:01 ; +; Total ; 00:00:11 ; -- ; -- ; 00:00:10 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/MainController/output_files/MainController.jdi b/MainController/output_files/MainController.jdi index e8b8caf..f7b89df 100644 --- a/MainController/output_files/MainController.jdi +++ b/MainController/output_files/MainController.jdi @@ -1,6 +1,6 @@ - + diff --git a/MainController/output_files/MainController.map.rpt b/MainController/output_files/MainController.map.rpt index c05a413..790be23 100644 --- a/MainController/output_files/MainController.map.rpt +++ b/MainController/output_files/MainController.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for MainController -Tue Mar 12 16:24:16 2024 +Tue Mar 12 17:46:44 2024 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -13,15 +13,26 @@ Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version 5. Analysis & Synthesis Source Files Read 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity - 8. Analysis & Synthesis IP Cores Summary - 9. Registers Removed During Synthesis - 10. Removed Registers Triggering Further Register Optimizations - 11. General Register Statistics - 12. Inverted Register Statistics - 13. Parameter Settings for User Entity Instance: AlteraPLL:inst|altpll:altpll_component - 14. altpll Parameter Settings by Entity Instance - 15. Elapsed Time Per Partition - 16. Analysis & Synthesis Messages + 8. Analysis & Synthesis RAM Summary + 9. Analysis & Synthesis IP Cores Summary + 10. State Machine - |MainController|RAM:inst3|stateMM1 + 11. State Machine - |MainController|RAM:inst3|stateMM0 + 12. Registers Removed During Synthesis + 13. Removed Registers Triggering Further Register Optimizations + 14. General Register Statistics + 15. Inverted Register Statistics + 16. Registers Added for RAM Pass-Through Logic + 17. Registers Packed Into Inferred Megafunctions + 18. Multiplexer Restructuring Statistics (Restructuring Performed) + 19. Source assignments for RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated + 20. Source assignments for RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated + 21. Parameter Settings for User Entity Instance: AlteraPLL:inst|altpll:altpll_component + 22. Parameter Settings for Inferred Entity Instance: RAM:inst3|altsyncram:memory_rtl_1 + 23. Parameter Settings for Inferred Entity Instance: RAM:inst3|altsyncram:memory_rtl_0 + 24. altpll Parameter Settings by Entity Instance + 25. altsyncram Parameter Settings by Entity Instance + 26. Elapsed Time Per Partition + 27. Analysis & Synthesis Messages @@ -47,20 +58,20 @@ applicable agreement for further details. +----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Mar 12 16:24:16 2024 ; +; Analysis & Synthesis Status ; Successful - Tue Mar 12 17:46:44 2024 ; ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ; ; Revision Name ; MainController ; ; Top-level Entity Name ; MainController ; ; Family ; Cyclone III ; -; Total logic elements ; 34 ; -; Total combinational functions ; 34 ; -; Dedicated logic registers ; 25 ; -; Total registers ; 25 ; -; Total pins ; 21 ; +; Total logic elements ; 102 ; +; Total combinational functions ; 67 ; +; Dedicated logic registers ; 80 ; +; Total registers ; 80 ; +; Total pins ; 23 ; ; Total virtual pins ; 0 ; -; Total memory bits ; 0 ; +; Total memory bits ; 2,048 ; ; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 0 ; +; Total PLLs ; 1 ; +------------------------------------+---------------------------------------------+ @@ -168,65 +179,94 @@ applicable agreement for further details. +----------------------------+-------------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+ -; MainController.bdf ; yes ; User Block Diagram/Schematic File ; D:/GITEA/altera/MainController/MainController.bdf ; ; -; AlteraPLL.vhd ; yes ; User Wizard-Generated File ; D:/GITEA/altera/MainController/AlteraPLL.vhd ; ; -; RAM.vhd ; yes ; User VHDL File ; D:/GITEA/altera/MainController/RAM.vhd ; ; -; LedBlink.vhd ; yes ; User VHDL File ; D:/GITEA/altera/MainController/LedBlink.vhd ; ; -; altpll.tdf ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altpll.tdf ; ; -; aglobal131.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ; -; stratix_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_pll.inc ; ; -; stratixii_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratixii_pll.inc ; ; -; cycloneii_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; -; db/alterapll_altpll.v ; yes ; Auto-Generated Megafunction ; D:/GITEA/altera/MainController/db/alterapll_altpll.v ; ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------+---------+ +; MainController.bdf ; yes ; User Block Diagram/Schematic File ; D:/GITEA/altera/MainController/MainController.bdf ; ; +; AlteraPLL.vhd ; yes ; User Wizard-Generated File ; D:/GITEA/altera/MainController/AlteraPLL.vhd ; ; +; RAM.vhd ; yes ; User VHDL File ; D:/GITEA/altera/MainController/RAM.vhd ; ; +; LedBlink.vhd ; yes ; User VHDL File ; D:/GITEA/altera/MainController/LedBlink.vhd ; ; +; altpll.tdf ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altpll.tdf ; ; +; aglobal131.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ; +; stratix_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_pll.inc ; ; +; stratixii_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratixii_pll.inc ; ; +; cycloneii_pll.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; +; db/alterapll_altpll.v ; yes ; Auto-Generated Megafunction ; D:/GITEA/altera/MainController/db/alterapll_altpll.v ; ; +; altsyncram.tdf ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altsyncram.tdf ; ; +; stratix_ram_block.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; +; lpm_mux.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/lpm_mux.inc ; ; +; lpm_decode.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/lpm_decode.inc ; ; +; a_rdenreg.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; +; altrom.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altrom.inc ; ; +; altram.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altram.inc ; ; +; altdpram.inc ; yes ; Megafunction ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altdpram.inc ; ; +; db/altsyncram_lkc1.tdf ; yes ; Auto-Generated Megafunction ; D:/GITEA/altera/MainController/db/altsyncram_lkc1.tdf ; ; +; db/altsyncram_8bi1.tdf ; yes ; Auto-Generated Megafunction ; D:/GITEA/altera/MainController/db/altsyncram_8bi1.tdf ; ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------+---------+ -+--------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+----------------------------+ -; Resource ; Usage ; -+---------------------------------------------+----------------------------+ -; Estimated Total logic elements ; 34 ; -; ; ; -; Total combinational functions ; 34 ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 8 ; -; -- 3 input functions ; 1 ; -; -- <=2 input functions ; 25 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 11 ; -; -- arithmetic mode ; 23 ; -; ; ; -; Total registers ; 25 ; -; -- Dedicated logic registers ; 25 ; -; -- I/O registers ; 0 ; -; ; ; -; I/O pins ; 21 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Maximum fan-out node ; LedBlink:inst2|LessThan0~8 ; -; Maximum fan-out ; 25 ; -; Total fan-out ; 188 ; -; Average fan-out ; 1.72 ; -+---------------------------------------------+----------------------------+ ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; Estimated Total logic elements ; 102 ; +; ; ; +; Total combinational functions ; 67 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 20 ; +; -- 3 input functions ; 20 ; +; -- <=2 input functions ; 27 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 44 ; +; -- arithmetic mode ; 23 ; +; ; ; +; Total registers ; 80 ; +; -- Dedicated logic registers ; 80 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 23 ; +; Total memory bits ; 2048 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 1 ; +; -- PLLs ; 1 ; +; ; ; +; Maximum fan-out node ; FPGA_CLK~input ; +; Maximum fan-out ; 89 ; +; Total fan-out ; 622 ; +; Average fan-out ; 2.96 ; ++---------------------------------------------+----------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+ -; |MainController ; 34 (0) ; 25 (0) ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; |MainController ; work ; -; |LedBlink:inst2| ; 34 (34) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|LedBlink:inst2 ; work ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++--------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++--------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------+--------------+ +; |MainController ; 67 (0) ; 80 (0) ; 2048 ; 0 ; 0 ; 0 ; 23 ; 0 ; |MainController ; work ; +; |AlteraPLL:inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|AlteraPLL:inst ; work ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|AlteraPLL:inst|altpll:altpll_component ; work ; +; |AlteraPLL_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated ; work ; +; |LedBlink:inst2| ; 36 (36) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|LedBlink:inst2 ; work ; +; |RAM:inst3| ; 31 (31) ; 55 (55) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|RAM:inst3 ; work ; +; |altsyncram:memory_rtl_0| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|RAM:inst3|altsyncram:memory_rtl_0 ; work ; +; |altsyncram_8bi1:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MainController|RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated ; work ; ++--------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++-----------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++-----------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+ +; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 256 ; 8 ; 256 ; 8 ; 2048 ; None ; ++-----------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+ + + +-----------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis IP Cores Summary ; +--------+--------------+---------+--------------+--------------+--------------------------------+----------------------------------------------+ @@ -236,2194 +276,66 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------+--------------+---------+--------------+--------------+--------------------------------+----------------------------------------------+ +Encoding Type: One-Hot ++---------------------------------------------------------------------------+ +; State Machine - |MainController|RAM:inst3|stateMM1 ; ++------------------+------------------+------------------+------------------+ +; Name ; stateMM1.Reading ; stateMM1.Writing ; stateMM1.Waiting ; ++------------------+------------------+------------------+------------------+ +; stateMM1.Waiting ; 0 ; 0 ; 0 ; +; stateMM1.Writing ; 0 ; 1 ; 1 ; +; stateMM1.Reading ; 1 ; 0 ; 1 ; ++------------------+------------------+------------------+------------------+ + + +Encoding Type: One-Hot ++---------------------------------------------------------------------------+ +; State Machine - |MainController|RAM:inst3|stateMM0 ; ++------------------+------------------+------------------+------------------+ +; Name ; stateMM0.Reading ; stateMM0.Writing ; stateMM0.Waiting ; ++------------------+------------------+------------------+------------------+ +; stateMM0.Waiting ; 0 ; 0 ; 0 ; +; stateMM0.Writing ; 0 ; 1 ; 1 ; +; stateMM0.Reading ; 1 ; 0 ; 1 ; ++------------------+------------------+------------------+------------------+ + + +---------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; -+------------------------------------------+--------------------------------------+ -; Register name ; Reason for Removal ; -+------------------------------------------+--------------------------------------+ -; RAM:inst1|data0[2]~en ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data1[7]~reg0 ; Lost fanout ; -; RAM:inst1|data1[7]~en ; Lost fanout ; -; RAM:inst1|data1[6]~reg0 ; Lost fanout ; -; RAM:inst1|data1[6]~en ; Lost fanout ; -; RAM:inst1|data1[5]~reg0 ; Lost fanout ; -; RAM:inst1|data1[5]~en ; Lost fanout ; -; RAM:inst1|data1[4]~reg0 ; Lost fanout ; -; RAM:inst1|data1[4]~en ; Lost fanout ; -; RAM:inst1|data1[3]~reg0 ; Lost fanout ; -; RAM:inst1|data1[3]~en ; Lost fanout ; -; RAM:inst1|data1[2]~reg0 ; Lost fanout ; -; RAM:inst1|data1[2]~en ; Lost fanout ; -; RAM:inst1|data1[1]~reg0 ; Lost fanout ; -; RAM:inst1|data1[1]~en ; Lost fanout ; -; RAM:inst1|data1[0]~reg0 ; Lost fanout ; -; RAM:inst1|data1[0]~en ; Lost fanout ; -; RAM:inst1|clk1Prev ; Lost fanout ; -; RAM:inst1|memory[0][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[7]~reg0 ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[6]~reg0 ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[5]~reg0 ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[4]~reg0 ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[3]~reg0 ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[2]~reg0 ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[1]~reg0 ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[1]~en ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[0]~en ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[0]~reg0 ; Stuck at GND due to stuck port clock ; -; RAM:inst1|clk0Prev ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[3]~en ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[4]~en ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[5]~en ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[6]~en ; Stuck at GND due to stuck port clock ; -; RAM:inst1|data0[7]~en ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[0][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[0][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[0][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[0][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[0][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[0][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[0][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[1][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[1][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[1][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[1][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[1][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[1][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[1][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[1][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[2][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[2][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[2][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[2][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[2][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[2][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[2][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[2][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[3][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[3][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[3][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[3][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[3][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[3][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[3][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[3][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[4][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[4][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[4][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[4][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[4][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[4][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[4][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[4][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[5][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[5][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[5][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[5][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[5][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[5][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[5][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[5][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[6][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[6][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[6][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[6][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[6][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[6][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[6][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[6][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[7][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[7][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[7][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[7][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[7][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[7][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[7][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[7][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[8][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[8][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[8][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[8][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[8][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[8][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[8][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[8][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[9][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[9][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[9][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[9][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[9][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[9][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[9][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[9][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[10][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[10][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[10][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[10][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[10][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[10][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[10][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[10][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[11][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[11][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[11][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[11][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[11][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[11][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[11][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[11][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[12][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[12][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[12][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[12][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[12][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[12][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[12][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[12][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[13][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[13][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[13][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[13][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[13][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[13][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[13][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[13][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[14][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[14][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[14][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[14][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[14][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[14][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[14][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[14][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[15][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[15][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[15][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[15][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[15][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[15][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[15][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[15][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[16][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[16][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[16][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[16][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[16][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[16][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[16][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[16][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[17][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[17][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[17][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[17][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[17][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[17][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[17][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[17][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[18][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[18][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[18][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[18][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[18][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[18][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[18][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[18][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[19][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[19][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[19][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[19][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[19][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[19][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[19][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[19][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[20][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[20][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[20][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[20][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[20][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[20][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[20][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[20][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[21][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[21][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[21][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[21][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[21][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[21][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[21][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[21][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[22][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[22][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[22][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[22][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[22][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[22][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[22][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[22][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[23][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[23][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[23][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[23][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[23][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[23][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[23][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[23][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[24][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[24][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[24][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[24][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[24][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[24][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[24][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[24][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[25][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[25][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[25][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[25][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[25][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[25][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[25][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[25][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[26][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[26][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[26][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[26][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[26][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[26][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[26][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[26][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[27][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[27][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[27][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[27][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[27][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[27][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[27][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[27][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[28][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[28][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[28][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[28][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[28][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[28][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[28][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[28][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[29][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[29][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[29][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[29][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[29][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[29][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[29][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[29][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[30][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[30][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[30][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[30][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[30][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[30][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[30][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[30][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[31][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[31][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[31][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[31][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[31][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[31][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[31][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[31][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[32][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[32][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[32][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[32][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[32][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[32][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[32][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[32][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[33][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[33][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[33][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[33][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[33][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[33][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[33][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[33][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[34][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[34][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[34][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[34][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[34][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[34][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[34][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[34][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[35][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[35][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[35][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[35][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[35][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[35][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[35][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[35][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[36][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[36][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[36][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[36][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[36][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[36][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[36][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[36][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[37][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[37][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[37][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[37][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[37][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[37][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[37][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[37][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[38][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[38][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[38][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[38][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[38][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[38][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[38][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[38][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[39][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[39][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[39][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[39][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[39][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[39][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[39][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[39][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[40][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[40][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[40][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[40][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[40][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[40][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[40][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[40][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[41][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[41][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[41][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[41][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[41][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[41][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[41][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[41][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[42][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[42][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[42][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[42][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[42][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[42][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[42][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[42][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[43][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[43][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[43][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[43][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[43][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[43][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[43][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[43][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[44][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[44][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[44][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[44][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[44][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[44][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[44][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[44][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[45][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[45][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[45][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[45][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[45][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[45][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[45][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[45][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[46][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[46][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[46][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[46][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[46][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[46][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[46][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[46][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[47][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[47][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[47][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[47][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[47][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[47][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[47][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[47][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[48][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[48][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[48][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[48][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[48][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[48][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[48][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[48][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[49][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[49][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[49][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[49][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[49][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[49][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[49][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[49][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[50][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[50][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[50][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[50][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[50][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[50][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[50][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[50][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[51][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[51][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[51][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[51][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[51][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[51][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[51][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[51][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[52][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[52][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[52][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[52][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[52][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[52][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[52][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[52][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[53][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[53][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[53][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[53][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[53][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[53][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[53][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[53][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[54][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[54][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[54][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[54][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[54][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[54][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[54][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[54][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[55][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[55][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[55][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[55][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[55][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[55][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[55][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[55][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[56][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[56][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[56][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[56][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[56][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[56][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[56][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[56][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[57][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[57][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[57][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[57][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[57][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[57][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[57][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[57][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[58][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[58][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[58][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[58][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[58][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[58][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[58][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[58][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[59][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[59][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[59][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[59][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[59][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[59][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[59][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[59][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[60][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[60][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[60][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[60][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[60][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[60][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[60][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[60][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[61][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[61][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[61][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[61][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[61][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[61][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[61][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[61][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[62][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[62][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[62][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[62][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[62][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[62][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[62][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[62][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[63][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[63][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[63][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[63][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[63][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[63][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[63][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[63][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[64][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[64][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[64][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[64][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[64][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[64][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[64][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[64][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[65][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[65][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[65][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[65][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[65][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[65][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[65][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[65][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[66][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[66][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[66][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[66][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[66][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[66][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[66][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[66][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[67][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[67][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[67][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[67][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[67][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[67][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[67][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[67][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[68][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[68][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[68][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[68][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[68][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[68][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[68][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[68][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[69][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[69][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[69][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[69][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[69][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[69][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[69][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[69][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[70][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[70][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[70][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[70][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[70][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[70][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[70][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[70][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[71][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[71][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[71][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[71][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[71][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[71][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[71][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[71][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[72][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[72][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[72][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[72][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[72][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[72][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[72][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[72][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[73][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[73][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[73][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[73][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[73][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[73][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[73][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[73][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[74][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[74][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[74][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[74][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[74][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[74][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[74][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[74][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[75][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[75][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[75][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[75][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[75][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[75][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[75][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[75][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[76][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[76][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[76][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[76][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[76][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[76][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[76][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[76][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[77][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[77][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[77][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[77][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[77][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[77][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[77][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[77][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[78][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[78][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[78][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[78][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[78][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[78][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[78][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[78][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[79][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[79][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[79][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[79][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[79][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[79][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[79][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[79][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[80][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[80][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[80][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[80][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[80][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[80][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[80][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[80][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[81][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[81][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[81][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[81][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[81][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[81][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[81][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[81][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[82][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[82][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[82][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[82][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[82][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[82][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[82][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[82][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[83][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[83][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[83][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[83][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[83][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[83][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[83][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[83][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[84][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[84][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[84][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[84][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[84][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[84][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[84][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[84][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[85][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[85][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[85][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[85][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[85][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[85][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[85][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[85][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[86][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[86][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[86][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[86][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[86][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[86][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[86][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[86][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[87][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[87][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[87][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[87][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[87][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[87][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[87][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[87][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[88][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[88][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[88][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[88][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[88][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[88][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[88][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[88][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[89][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[89][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[89][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[89][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[89][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[89][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[89][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[89][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[90][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[90][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[90][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[90][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[90][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[90][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[90][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[90][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[91][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[91][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[91][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[91][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[91][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[91][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[91][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[91][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[92][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[92][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[92][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[92][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[92][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[92][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[92][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[92][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[93][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[93][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[93][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[93][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[93][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[93][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[93][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[93][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[94][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[94][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[94][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[94][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[94][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[94][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[94][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[94][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[95][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[95][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[95][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[95][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[95][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[95][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[95][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[95][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[96][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[96][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[96][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[96][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[96][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[96][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[96][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[96][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[97][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[97][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[97][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[97][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[97][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[97][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[97][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[97][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[98][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[98][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[98][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[98][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[98][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[98][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[98][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[98][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[99][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[99][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[99][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[99][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[99][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[99][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[99][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[99][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[100][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[100][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[100][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[100][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[100][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[100][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[100][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[100][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[101][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[101][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[101][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[101][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[101][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[101][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[101][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[101][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[102][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[102][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[102][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[102][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[102][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[102][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[102][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[102][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[103][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[103][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[103][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[103][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[103][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[103][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[103][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[103][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[104][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[104][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[104][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[104][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[104][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[104][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[104][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[104][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[105][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[105][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[105][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[105][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[105][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[105][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[105][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[105][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[106][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[106][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[106][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[106][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[106][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[106][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[106][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[106][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[107][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[107][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[107][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[107][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[107][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[107][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[107][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[107][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[108][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[108][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[108][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[108][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[108][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[108][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[108][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[108][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[109][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[109][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[109][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[109][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[109][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[109][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[109][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[109][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[110][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[110][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[110][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[110][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[110][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[110][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[110][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[110][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[111][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[111][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[111][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[111][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[111][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[111][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[111][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[111][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[112][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[112][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[112][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[112][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[112][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[112][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[112][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[112][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[113][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[113][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[113][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[113][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[113][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[113][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[113][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[113][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[114][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[114][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[114][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[114][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[114][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[114][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[114][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[114][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[115][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[115][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[115][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[115][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[115][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[115][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[115][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[115][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[116][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[116][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[116][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[116][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[116][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[116][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[116][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[116][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[117][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[117][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[117][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[117][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[117][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[117][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[117][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[117][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[118][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[118][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[118][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[118][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[118][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[118][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[118][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[118][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[119][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[119][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[119][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[119][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[119][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[119][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[119][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[119][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[120][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[120][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[120][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[120][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[120][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[120][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[120][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[120][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[121][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[121][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[121][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[121][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[121][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[121][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[121][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[121][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[122][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[122][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[122][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[122][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[122][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[122][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[122][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[122][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[123][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[123][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[123][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[123][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[123][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[123][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[123][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[123][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[124][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[124][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[124][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[124][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[124][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[124][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[124][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[124][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[125][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[125][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[125][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[125][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[125][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[125][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[125][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[125][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[126][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[126][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[126][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[126][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[126][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[126][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[126][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[126][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[127][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[127][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[127][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[127][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[127][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[127][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[127][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[127][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[128][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[128][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[128][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[128][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[128][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[128][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[128][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[128][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[129][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[129][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[129][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[129][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[129][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[129][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[129][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[129][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[130][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[130][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[130][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[130][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[130][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[130][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[130][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[130][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[131][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[131][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[131][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[131][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[131][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[131][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[131][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[131][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[132][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[132][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[132][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[132][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[132][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[132][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[132][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[132][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[133][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[133][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[133][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[133][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[133][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[133][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[133][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[133][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[134][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[134][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[134][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[134][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[134][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[134][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[134][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[134][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[135][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[135][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[135][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[135][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[135][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[135][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[135][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[135][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[136][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[136][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[136][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[136][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[136][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[136][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[136][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[136][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[137][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[137][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[137][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[137][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[137][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[137][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[137][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[137][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[138][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[138][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[138][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[138][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[138][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[138][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[138][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[138][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[139][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[139][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[139][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[139][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[139][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[139][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[139][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[139][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[140][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[140][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[140][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[140][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[140][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[140][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[140][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[140][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[141][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[141][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[141][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[141][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[141][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[141][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[141][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[141][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[142][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[142][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[142][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[142][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[142][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[142][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[142][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[142][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[143][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[143][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[143][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[143][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[143][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[143][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[143][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[143][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[144][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[144][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[144][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[144][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[144][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[144][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[144][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[144][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[145][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[145][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[145][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[145][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[145][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[145][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[145][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[145][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[146][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[146][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[146][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[146][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[146][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[146][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[146][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[146][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[147][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[147][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[147][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[147][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[147][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[147][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[147][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[147][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[148][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[148][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[148][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[148][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[148][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[148][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[148][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[148][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[149][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[149][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[149][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[149][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[149][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[149][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[149][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[149][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[150][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[150][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[150][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[150][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[150][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[150][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[150][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[150][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[151][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[151][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[151][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[151][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[151][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[151][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[151][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[151][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[152][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[152][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[152][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[152][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[152][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[152][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[152][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[152][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[153][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[153][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[153][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[153][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[153][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[153][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[153][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[153][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[154][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[154][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[154][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[154][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[154][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[154][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[154][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[154][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[155][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[155][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[155][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[155][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[155][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[155][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[155][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[155][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[156][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[156][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[156][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[156][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[156][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[156][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[156][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[156][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[157][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[157][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[157][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[157][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[157][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[157][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[157][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[157][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[158][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[158][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[158][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[158][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[158][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[158][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[158][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[158][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[159][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[159][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[159][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[159][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[159][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[159][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[159][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[159][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[160][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[160][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[160][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[160][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[160][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[160][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[160][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[160][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[161][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[161][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[161][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[161][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[161][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[161][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[161][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[161][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[162][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[162][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[162][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[162][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[162][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[162][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[162][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[162][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[163][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[163][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[163][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[163][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[163][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[163][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[163][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[163][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[164][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[164][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[164][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[164][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[164][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[164][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[164][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[164][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[165][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[165][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[165][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[165][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[165][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[165][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[165][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[165][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[166][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[166][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[166][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[166][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[166][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[166][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[166][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[166][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[167][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[167][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[167][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[167][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[167][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[167][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[167][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[167][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[168][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[168][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[168][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[168][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[168][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[168][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[168][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[168][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[169][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[169][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[169][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[169][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[169][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[169][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[169][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[169][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[170][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[170][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[170][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[170][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[170][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[170][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[170][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[170][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[171][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[171][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[171][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[171][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[171][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[171][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[171][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[171][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[172][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[172][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[172][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[172][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[172][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[172][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[172][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[172][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[173][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[173][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[173][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[173][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[173][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[173][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[173][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[173][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[174][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[174][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[174][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[174][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[174][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[174][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[174][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[174][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[175][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[175][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[175][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[175][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[175][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[175][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[175][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[175][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[176][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[176][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[176][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[176][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[176][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[176][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[176][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[176][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[177][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[177][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[177][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[177][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[177][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[177][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[177][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[177][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[178][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[178][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[178][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[178][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[178][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[178][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[178][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[178][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[179][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[179][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[179][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[179][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[179][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[179][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[179][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[179][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[180][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[180][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[180][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[180][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[180][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[180][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[180][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[180][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[181][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[181][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[181][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[181][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[181][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[181][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[181][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[181][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[182][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[182][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[182][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[182][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[182][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[182][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[182][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[182][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[183][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[183][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[183][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[183][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[183][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[183][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[183][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[183][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[184][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[184][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[184][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[184][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[184][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[184][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[184][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[184][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[185][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[185][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[185][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[185][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[185][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[185][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[185][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[185][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[186][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[186][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[186][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[186][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[186][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[186][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[186][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[186][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[187][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[187][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[187][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[187][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[187][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[187][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[187][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[187][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[188][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[188][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[188][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[188][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[188][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[188][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[188][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[188][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[189][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[189][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[189][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[189][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[189][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[189][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[189][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[189][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[190][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[190][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[190][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[190][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[190][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[190][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[190][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[190][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[191][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[191][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[191][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[191][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[191][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[191][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[191][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[191][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[192][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[192][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[192][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[192][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[192][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[192][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[192][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[192][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[193][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[193][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[193][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[193][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[193][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[193][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[193][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[193][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[194][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[194][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[194][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[194][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[194][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[194][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[194][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[194][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[195][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[195][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[195][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[195][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[195][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[195][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[195][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[195][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[196][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[196][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[196][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[196][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[196][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[196][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[196][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[196][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[197][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[197][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[197][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[197][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[197][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[197][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[197][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[197][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[198][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[198][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[198][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[198][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[198][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[198][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[198][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[198][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[199][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[199][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[199][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[199][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[199][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[199][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[199][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[199][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[200][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[200][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[200][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[200][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[200][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[200][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[200][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[200][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[201][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[201][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[201][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[201][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[201][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[201][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[201][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[201][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[202][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[202][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[202][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[202][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[202][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[202][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[202][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[202][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[203][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[203][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[203][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[203][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[203][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[203][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[203][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[203][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[204][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[204][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[204][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[204][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[204][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[204][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[204][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[204][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[205][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[205][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[205][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[205][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[205][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[205][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[205][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[205][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[206][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[206][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[206][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[206][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[206][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[206][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[206][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[206][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[207][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[207][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[207][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[207][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[207][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[207][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[207][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[207][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[208][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[208][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[208][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[208][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[208][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[208][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[208][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[208][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[209][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[209][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[209][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[209][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[209][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[209][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[209][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[209][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[210][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[210][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[210][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[210][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[210][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[210][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[210][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[210][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[211][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[211][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[211][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[211][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[211][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[211][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[211][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[211][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[212][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[212][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[212][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[212][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[212][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[212][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[212][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[212][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[213][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[213][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[213][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[213][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[213][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[213][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[213][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[213][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[214][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[214][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[214][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[214][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[214][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[214][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[214][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[214][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[215][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[215][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[215][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[215][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[215][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[215][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[215][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[215][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[216][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[216][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[216][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[216][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[216][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[216][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[216][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[216][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[217][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[217][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[217][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[217][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[217][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[217][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[217][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[217][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[218][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[218][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[218][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[218][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[218][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[218][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[218][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[218][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[219][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[219][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[219][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[219][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[219][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[219][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[219][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[219][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[220][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[220][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[220][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[220][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[220][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[220][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[220][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[220][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[221][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[221][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[221][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[221][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[221][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[221][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[221][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[221][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[222][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[222][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[222][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[222][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[222][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[222][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[222][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[222][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[223][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[223][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[223][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[223][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[223][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[223][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[223][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[223][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[224][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[224][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[224][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[224][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[224][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[224][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[224][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[224][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[225][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[225][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[225][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[225][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[225][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[225][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[225][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[225][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[226][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[226][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[226][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[226][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[226][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[226][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[226][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[226][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[227][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[227][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[227][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[227][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[227][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[227][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[227][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[227][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[228][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[228][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[228][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[228][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[228][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[228][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[228][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[228][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[229][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[229][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[229][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[229][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[229][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[229][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[229][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[229][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[230][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[230][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[230][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[230][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[230][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[230][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[230][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[230][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[231][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[231][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[231][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[231][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[231][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[231][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[231][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[231][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[232][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[232][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[232][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[232][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[232][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[232][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[232][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[232][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[233][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[233][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[233][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[233][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[233][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[233][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[233][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[233][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[234][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[234][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[234][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[234][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[234][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[234][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[234][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[234][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[235][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[235][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[235][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[235][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[235][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[235][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[235][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[235][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[236][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[236][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[236][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[236][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[236][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[236][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[236][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[236][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[237][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[237][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[237][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[237][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[237][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[237][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[237][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[237][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[238][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[238][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[238][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[238][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[238][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[238][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[238][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[238][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[239][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[239][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[239][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[239][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[239][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[239][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[239][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[239][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[240][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[240][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[240][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[240][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[240][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[240][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[240][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[240][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[241][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[241][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[241][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[241][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[241][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[241][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[241][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[241][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[242][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[242][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[242][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[242][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[242][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[242][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[242][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[242][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[243][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[243][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[243][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[243][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[243][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[243][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[243][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[243][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[244][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[244][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[244][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[244][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[244][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[244][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[244][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[244][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[245][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[245][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[245][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[245][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[245][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[245][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[245][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[245][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[246][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[246][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[246][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[246][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[246][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[246][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[246][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[246][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[247][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[247][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[247][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[247][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[247][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[247][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[247][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[247][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[248][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[248][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[248][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[248][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[248][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[248][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[248][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[248][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[249][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[249][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[249][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[249][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[249][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[249][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[249][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[249][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[250][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[250][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[250][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[250][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[250][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[250][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[250][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[250][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[251][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[251][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[251][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[251][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[251][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[251][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[251][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[251][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[252][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[252][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[252][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[252][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[252][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[252][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[252][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[252][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[253][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[253][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[253][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[253][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[253][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[253][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[253][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[253][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[254][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[254][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[254][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[254][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[254][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[254][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[254][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[254][7] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[255][0] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[255][1] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[255][2] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[255][3] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[255][4] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[255][5] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[255][6] ; Stuck at GND due to stuck port clock ; -; RAM:inst1|memory[255][7] ; Stuck at GND due to stuck port clock ; -; Total Number of Removed Registers = 2082 ; ; -+------------------------------------------+--------------------------------------+ ++----------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++----------------------------------------+----------------------------------------+ +; RAM:inst3|oe1Prev ; Lost fanout ; +; RAM:inst3|ce1Prev ; Stuck at GND due to stuck port data_in ; +; RAM:inst3|we1Prev ; Stuck at GND due to stuck port data_in ; +; RAM:inst3|\process_1:addr[0..7] ; Stuck at GND due to stuck port data_in ; +; RAM:inst3|data1[0]~en ; Lost fanout ; +; RAM:inst3|data1[1]~en ; Lost fanout ; +; RAM:inst3|data1[2]~en ; Lost fanout ; +; RAM:inst3|data1[3]~en ; Lost fanout ; +; RAM:inst3|data1[4]~en ; Lost fanout ; +; RAM:inst3|data1[5]~en ; Lost fanout ; +; RAM:inst3|data1[6]~en ; Lost fanout ; +; RAM:inst3|data1[7]~en ; Lost fanout ; +; RAM:inst3|stateMM1.Reading ; Lost fanout ; +; RAM:inst3|stateMM1.Writing ; Stuck at GND due to stuck port data_in ; +; RAM:inst3|stateMM1.Waiting ; Lost fanout ; +; Total Number of Removed Registers = 22 ; ; ++----------------------------------------+----------------------------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Removed Registers Triggering Further Register Optimizations ; -+-------------------------+-------------------------+-------------------------------------------------------------------------------+ -; Register name ; Reason for Removal ; Registers Removed due to This Register ; -+-------------------------+-------------------------+-------------------------------------------------------------------------------+ -; RAM:inst1|data0[2]~en ; Stuck at GND ; RAM:inst1|memory[0][2], RAM:inst1|memory[1][2], RAM:inst1|memory[2][2], ; -; ; due to stuck port clock ; RAM:inst1|memory[3][2], RAM:inst1|memory[4][2], RAM:inst1|memory[5][2], ; -; ; ; RAM:inst1|memory[6][2], RAM:inst1|memory[7][2], RAM:inst1|memory[8][2], ; -; ; ; RAM:inst1|memory[9][2], RAM:inst1|memory[10][2], RAM:inst1|memory[11][2], ; -; ; ; RAM:inst1|memory[12][2], RAM:inst1|memory[13][2], RAM:inst1|memory[14][2], ; -; ; ; RAM:inst1|memory[15][2], RAM:inst1|memory[16][2], RAM:inst1|memory[17][2], ; -; ; ; RAM:inst1|memory[18][2], RAM:inst1|memory[19][2], RAM:inst1|memory[20][2], ; -; ; ; RAM:inst1|memory[21][2], RAM:inst1|memory[22][2], RAM:inst1|memory[23][2], ; -; ; ; RAM:inst1|memory[24][2], RAM:inst1|memory[25][2], RAM:inst1|memory[26][2], ; -; ; ; RAM:inst1|memory[27][2], RAM:inst1|memory[28][2], RAM:inst1|memory[29][2], ; -; ; ; RAM:inst1|memory[30][2], RAM:inst1|memory[31][2], RAM:inst1|memory[32][2], ; -; ; ; RAM:inst1|memory[33][2], RAM:inst1|memory[34][2], RAM:inst1|memory[35][2], ; -; ; ; RAM:inst1|memory[36][2], RAM:inst1|memory[37][2], RAM:inst1|memory[38][2], ; -; ; ; RAM:inst1|memory[39][2], RAM:inst1|memory[40][2], RAM:inst1|memory[41][2], ; -; ; ; RAM:inst1|memory[42][2], RAM:inst1|memory[43][2], RAM:inst1|memory[44][2], ; -; ; ; RAM:inst1|memory[45][2], RAM:inst1|memory[46][2], RAM:inst1|memory[47][2], ; -; ; ; RAM:inst1|memory[48][2], RAM:inst1|memory[49][2], RAM:inst1|memory[50][2], ; -; ; ; RAM:inst1|memory[51][2], RAM:inst1|memory[52][2], RAM:inst1|memory[53][2], ; -; ; ; RAM:inst1|memory[54][2], RAM:inst1|memory[55][2], RAM:inst1|memory[56][2], ; -; ; ; RAM:inst1|memory[57][2], RAM:inst1|memory[58][2], RAM:inst1|memory[59][2], ; -; ; ; RAM:inst1|memory[60][2], RAM:inst1|memory[61][2], RAM:inst1|memory[62][2], ; -; ; ; RAM:inst1|memory[63][2], RAM:inst1|memory[64][2], RAM:inst1|memory[65][2], ; -; ; ; RAM:inst1|memory[66][2], RAM:inst1|memory[67][2], RAM:inst1|memory[68][2], ; -; ; ; RAM:inst1|memory[69][2], RAM:inst1|memory[70][2], RAM:inst1|memory[71][2], ; -; ; ; RAM:inst1|memory[72][2], RAM:inst1|memory[73][2], RAM:inst1|memory[74][2], ; -; ; ; RAM:inst1|memory[75][2], RAM:inst1|memory[76][2], RAM:inst1|memory[77][2], ; -; ; ; RAM:inst1|memory[78][2], RAM:inst1|memory[79][2], RAM:inst1|memory[80][2], ; -; ; ; RAM:inst1|memory[81][2], RAM:inst1|memory[82][2], RAM:inst1|memory[83][2], ; -; ; ; RAM:inst1|memory[84][2], RAM:inst1|memory[85][2], RAM:inst1|memory[86][2], ; -; ; ; RAM:inst1|memory[87][2], RAM:inst1|memory[88][2], RAM:inst1|memory[89][2], ; -; ; ; RAM:inst1|memory[90][2], RAM:inst1|memory[91][2], RAM:inst1|memory[92][2], ; -; ; ; RAM:inst1|memory[93][2], RAM:inst1|memory[94][2], RAM:inst1|memory[95][2], ; -; ; ; RAM:inst1|memory[96][2], RAM:inst1|memory[97][2], RAM:inst1|memory[98][2], ; -; ; ; RAM:inst1|memory[99][2], RAM:inst1|memory[100][2], RAM:inst1|memory[101][2], ; -; ; ; RAM:inst1|memory[102][2], RAM:inst1|memory[103][2], RAM:inst1|memory[104][2], ; -; ; ; RAM:inst1|memory[105][2], RAM:inst1|memory[106][2], RAM:inst1|memory[107][2], ; -; ; ; RAM:inst1|memory[108][2], RAM:inst1|memory[109][2], RAM:inst1|memory[110][2], ; -; ; ; RAM:inst1|memory[111][2], RAM:inst1|memory[112][2], RAM:inst1|memory[113][2], ; -; ; ; RAM:inst1|memory[114][2], RAM:inst1|memory[115][2], RAM:inst1|memory[116][2], ; -; ; ; RAM:inst1|memory[117][2], RAM:inst1|memory[118][2], RAM:inst1|memory[119][2], ; -; ; ; RAM:inst1|memory[120][2], RAM:inst1|memory[121][2], RAM:inst1|memory[122][2], ; -; ; ; RAM:inst1|memory[123][2], RAM:inst1|memory[124][2], RAM:inst1|memory[125][2], ; -; ; ; RAM:inst1|memory[126][2], RAM:inst1|memory[127][2], RAM:inst1|memory[128][2], ; -; ; ; RAM:inst1|memory[129][2], RAM:inst1|memory[130][2], RAM:inst1|memory[131][2], ; -; ; ; RAM:inst1|memory[132][2], RAM:inst1|memory[133][2], RAM:inst1|memory[134][2], ; -; ; ; RAM:inst1|memory[135][2], RAM:inst1|memory[136][2], RAM:inst1|memory[137][2], ; -; ; ; RAM:inst1|memory[138][2], RAM:inst1|memory[139][2], RAM:inst1|memory[140][2], ; -; ; ; RAM:inst1|memory[141][2], RAM:inst1|memory[142][2], RAM:inst1|memory[143][2], ; -; ; ; RAM:inst1|memory[144][2], RAM:inst1|memory[145][2], RAM:inst1|memory[146][2], ; -; ; ; RAM:inst1|memory[147][2], RAM:inst1|memory[148][2], RAM:inst1|memory[149][2], ; -; ; ; RAM:inst1|memory[150][2], RAM:inst1|memory[151][2], RAM:inst1|memory[152][2], ; -; ; ; RAM:inst1|memory[153][2], RAM:inst1|memory[154][2], RAM:inst1|memory[155][2], ; -; ; ; RAM:inst1|memory[156][2], RAM:inst1|memory[157][2], RAM:inst1|memory[158][2], ; -; ; ; RAM:inst1|memory[159][2], RAM:inst1|memory[160][2], RAM:inst1|memory[161][2], ; -; ; ; RAM:inst1|memory[162][2], RAM:inst1|memory[163][2], RAM:inst1|memory[164][2], ; -; ; ; RAM:inst1|memory[165][2], RAM:inst1|memory[166][2], RAM:inst1|memory[167][2], ; -; ; ; RAM:inst1|memory[168][2], RAM:inst1|memory[169][2], RAM:inst1|memory[170][2], ; -; ; ; RAM:inst1|memory[171][2], RAM:inst1|memory[172][2], RAM:inst1|memory[173][2], ; -; ; ; RAM:inst1|memory[174][2], RAM:inst1|memory[175][2], RAM:inst1|memory[176][2], ; -; ; ; RAM:inst1|memory[177][2], RAM:inst1|memory[178][2], RAM:inst1|memory[179][2], ; -; ; ; RAM:inst1|memory[180][2], RAM:inst1|memory[181][2], RAM:inst1|memory[182][2], ; -; ; ; RAM:inst1|memory[183][2], RAM:inst1|memory[184][2], RAM:inst1|memory[185][2], ; -; ; ; RAM:inst1|memory[186][2], RAM:inst1|memory[187][2], RAM:inst1|memory[188][2], ; -; ; ; RAM:inst1|memory[189][2], RAM:inst1|memory[190][2], RAM:inst1|memory[191][2], ; -; ; ; RAM:inst1|memory[192][2], RAM:inst1|memory[193][2], RAM:inst1|memory[194][2], ; -; ; ; RAM:inst1|memory[195][2], RAM:inst1|memory[196][2], RAM:inst1|memory[197][2], ; -; ; ; RAM:inst1|memory[198][2], RAM:inst1|memory[199][2], RAM:inst1|memory[200][2], ; -; ; ; RAM:inst1|memory[201][2], RAM:inst1|memory[202][2], RAM:inst1|memory[203][2], ; -; ; ; RAM:inst1|memory[204][2], RAM:inst1|memory[205][2], RAM:inst1|memory[206][2], ; -; ; ; RAM:inst1|memory[207][2], RAM:inst1|memory[208][2], RAM:inst1|memory[209][2], ; -; ; ; RAM:inst1|memory[210][2], RAM:inst1|memory[211][2], RAM:inst1|memory[212][2], ; -; ; ; RAM:inst1|memory[213][2], RAM:inst1|memory[214][2], RAM:inst1|memory[215][2], ; -; ; ; RAM:inst1|memory[216][2], RAM:inst1|memory[217][2], RAM:inst1|memory[218][2], ; -; ; ; RAM:inst1|memory[219][2], RAM:inst1|memory[220][2], RAM:inst1|memory[221][2], ; -; ; ; RAM:inst1|memory[222][2], RAM:inst1|memory[223][2], RAM:inst1|memory[224][2], ; -; ; ; RAM:inst1|memory[225][2], RAM:inst1|memory[226][2], RAM:inst1|memory[227][2], ; -; ; ; RAM:inst1|memory[228][2], RAM:inst1|memory[229][2], RAM:inst1|memory[230][2], ; -; ; ; RAM:inst1|memory[231][2], RAM:inst1|memory[232][2], RAM:inst1|memory[233][2], ; -; ; ; RAM:inst1|memory[234][2], RAM:inst1|memory[235][2], RAM:inst1|memory[236][2], ; -; ; ; RAM:inst1|memory[237][2], RAM:inst1|memory[238][2], RAM:inst1|memory[239][2], ; -; ; ; RAM:inst1|memory[240][2], RAM:inst1|memory[241][2], RAM:inst1|memory[242][2], ; -; ; ; RAM:inst1|memory[243][2], RAM:inst1|memory[244][2], RAM:inst1|memory[245][2], ; -; ; ; RAM:inst1|memory[246][2], RAM:inst1|memory[247][2], RAM:inst1|memory[248][2], ; -; ; ; RAM:inst1|memory[249][2], RAM:inst1|memory[250][2], RAM:inst1|memory[251][2], ; -; ; ; RAM:inst1|memory[252][2], RAM:inst1|memory[253][2], RAM:inst1|memory[254][2], ; -; ; ; RAM:inst1|memory[255][2] ; -; RAM:inst1|clk0Prev ; Stuck at GND ; RAM:inst1|data0[3]~en, RAM:inst1|data0[4]~en, RAM:inst1|data0[5]~en, ; -; ; due to stuck port clock ; RAM:inst1|data0[6]~en, RAM:inst1|data0[7]~en ; -; RAM:inst1|data1[7]~reg0 ; Lost Fanouts ; RAM:inst1|clk1Prev ; -; RAM:inst1|memory[0][0] ; Stuck at GND ; RAM:inst1|data0[0]~reg0 ; -; ; due to stuck port clock ; ; -+-------------------------+-------------------------+-------------------------------------------------------------------------------+ ++----------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++----------------------------+---------------------------+-------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++----------------------------+---------------------------+-------------------------------------------------------------+ +; RAM:inst3|ce1Prev ; Stuck at GND ; RAM:inst3|\process_1:addr[0], RAM:inst3|\process_1:addr[1], ; +; ; due to stuck port data_in ; RAM:inst3|\process_1:addr[2], RAM:inst3|\process_1:addr[3], ; +; ; ; RAM:inst3|\process_1:addr[4], RAM:inst3|\process_1:addr[5], ; +; ; ; RAM:inst3|\process_1:addr[6], RAM:inst3|\process_1:addr[7] ; +; RAM:inst3|stateMM1.Writing ; Stuck at GND ; RAM:inst3|stateMM1.Waiting ; +; ; due to stuck port data_in ; ; ++----------------------------+---------------------------+-------------------------------------------------------------+ +------------------------------------------------------+ @@ -2431,12 +343,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 25 ; +; Total registers ; 80 ; ; Number of registers using Synchronous Clear ; 24 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 0 ; +; Number of registers using Clock Enable ; 34 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -2451,6 +363,83 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------+---------+ ++------------------------------------------------------------+ +; Registers Added for RAM Pass-Through Logic ; ++-----------------------------------+------------------------+ +; Register Name ; RAM Name ; ++-----------------------------------+------------------------+ +; RAM:inst3|memory_rtl_0_bypass[0] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[1] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[3] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[4] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[5] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[7] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[8] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[9] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[10] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[11] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[12] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[13] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[14] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[15] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[16] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[17] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[18] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[19] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[20] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[21] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[22] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[23] ; RAM:inst3|memory_rtl_0 ; +; RAM:inst3|memory_rtl_0_bypass[24] ; RAM:inst3|memory_rtl_0 ; ++-----------------------------------+------------------------+ + + ++---------------------------------------------------------+ +; Registers Packed Into Inferred Megafunctions ; ++-------------------------+------------------------+------+ +; Register Name ; Megafunction ; Type ; ++-------------------------+------------------------+------+ +; RAM:inst3|data1[0]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ; +; RAM:inst3|data1[1]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ; +; RAM:inst3|data1[2]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ; +; RAM:inst3|data1[3]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ; +; RAM:inst3|data1[4]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ; +; RAM:inst3|data1[5]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ; +; RAM:inst3|data1[6]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ; +; RAM:inst3|data1[7]~reg0 ; RAM:inst3|memory_rtl_1 ; RAM ; ++-------------------------+------------------------+------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |MainController|RAM:inst3|Selector32 ; +; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |MainController|RAM:inst3|Selector3 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Source assignments for RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated ; ++---------------------------------+--------------------+------+---------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Source assignments for RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated ; ++---------------------------------+--------------------+------+---------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------+ + + +-------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: AlteraPLL:inst|altpll:altpll_component ; +-------------------------------+-----------------------------+-----------------------+ @@ -2825,6 +814,128 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". ++------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: RAM:inst3|altsyncram:memory_rtl_1 ; ++------------------------------------+----------------------+------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+----------------------+------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Untyped ; +; WIDTHAD_A ; 8 ; Untyped ; +; NUMWORDS_A ; 256 ; Untyped ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Untyped ; +; WIDTHAD_B ; 8 ; Untyped ; +; NUMWORDS_B ; 256 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_lkc1 ; Untyped ; ++------------------------------------+----------------------+------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: RAM:inst3|altsyncram:memory_rtl_0 ; ++------------------------------------+----------------------+------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+----------------------+------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Untyped ; +; WIDTHAD_A ; 8 ; Untyped ; +; NUMWORDS_A ; 256 ; Untyped ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Untyped ; +; WIDTHAD_B ; 8 ; Untyped ; +; NUMWORDS_B ; 256 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK0 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_8bi1 ; Untyped ; ++------------------------------------+----------------------+------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + +------------------------------------------------------------------------+ ; altpll Parameter Settings by Entity Instance ; +-------------------------------+----------------------------------------+ @@ -2842,6 +953,37 @@ Note: In order to hide this table in the UI and the text report file, please set +-------------------------------+----------------------------------------+ ++-------------------------------------------------------------------------------+ +; altsyncram Parameter Settings by Entity Instance ; ++-------------------------------------------+-----------------------------------+ +; Name ; Value ; ++-------------------------------------------+-----------------------------------+ +; Number of entity instances ; 2 ; +; Entity Instance ; RAM:inst3|altsyncram:memory_rtl_1 ; +; -- OPERATION_MODE ; DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; RAM:inst3|altsyncram:memory_rtl_0 ; +; -- OPERATION_MODE ; DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK0 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; ++-------------------------------------------+-----------------------------------+ + + +-------------------------------+ ; Elapsed Time Per Partition ; +----------------+--------------+ @@ -2857,7 +999,7 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version - Info: Processing started: Tue Mar 12 16:24:14 2024 + Info: Processing started: Tue Mar 12 17:46:42 2024 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MainController -c MainController Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. Info (12021): Found 1 design units, including 1 entities, in source file maincontroller.bdf @@ -2872,12 +1014,7 @@ Info (12021): Found 2 design units, including 1 entities, in source file ledblin Info (12022): Found design unit 1: LedBlink-Behavioral Info (12023): Found entity 1: LedBlink Info (12127): Elaborating entity "MainController" for the top level hierarchy -Warning (275013): Port "clk" of type RAM and instance "inst1" is missing source signal -Warning (275009): Pin "nOE" not connected -Warning (275009): Pin "nWE" not connected -Warning (275009): Pin "nCE" not connected Info (12128): Elaborating entity "LedBlink" for hierarchy "LedBlink:inst2" -Info (12128): Elaborating entity "RAM" for hierarchy "RAM:inst1" Info (12128): Elaborating entity "AlteraPLL" for hierarchy "AlteraPLL:inst" Info (12128): Elaborating entity "altpll" for hierarchy "AlteraPLL:inst|altpll:altpll_component" Info (12130): Elaborated megafunction instantiation "AlteraPLL:inst|altpll:altpll_component" @@ -2944,33 +1081,102 @@ Info (12133): Instantiated megafunction "AlteraPLL:inst|altpll:altpll_component" Info (12021): Found 1 design units, including 1 entities, in source file db/alterapll_altpll.v Info (12023): Found entity 1: AlteraPLL_altpll Info (12128): Elaborating entity "AlteraPLL_altpll" for hierarchy "AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated" +Info (12128): Elaborating entity "RAM" for hierarchy "RAM:inst3" +Warning (276020): Inferred RAM node "RAM:inst3|memory_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design. +Warning (276027): Inferred dual-clock RAM node "RAM:inst3|memory_rtl_1" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design. +Info (19000): Inferred 2 megafunctions from design logic + Info (276029): Inferred altsyncram megafunction from the following design logic: "RAM:inst3|memory_rtl_0" + Info (286033): Parameter OPERATION_MODE set to DUAL_PORT + Info (286033): Parameter WIDTH_A set to 8 + Info (286033): Parameter WIDTHAD_A set to 8 + Info (286033): Parameter NUMWORDS_A set to 256 + Info (286033): Parameter WIDTH_B set to 8 + Info (286033): Parameter WIDTHAD_B set to 8 + Info (286033): Parameter NUMWORDS_B set to 256 + Info (286033): Parameter ADDRESS_ACLR_A set to NONE + Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED + Info (286033): Parameter ADDRESS_ACLR_B set to NONE + Info (286033): Parameter OUTDATA_ACLR_B set to NONE + Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 + Info (286033): Parameter INDATA_ACLR_A set to NONE + Info (286033): Parameter WRCONTROL_ACLR_A set to NONE + Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA + Info (276029): Inferred altsyncram megafunction from the following design logic: "RAM:inst3|memory_rtl_1" + Info (286033): Parameter OPERATION_MODE set to DUAL_PORT + Info (286033): Parameter WIDTH_A set to 8 + Info (286033): Parameter WIDTHAD_A set to 8 + Info (286033): Parameter NUMWORDS_A set to 256 + Info (286033): Parameter WIDTH_B set to 8 + Info (286033): Parameter WIDTHAD_B set to 8 + Info (286033): Parameter NUMWORDS_B set to 256 + Info (286033): Parameter ADDRESS_ACLR_A set to NONE + Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED + Info (286033): Parameter ADDRESS_ACLR_B set to NONE + Info (286033): Parameter OUTDATA_ACLR_B set to NONE + Info (286033): Parameter ADDRESS_REG_B set to CLOCK1 + Info (286033): Parameter INDATA_ACLR_A set to NONE + Info (286033): Parameter WRCONTROL_ACLR_A set to NONE +Info (12130): Elaborated megafunction instantiation "RAM:inst3|altsyncram:memory_rtl_1" +Info (12133): Instantiated megafunction "RAM:inst3|altsyncram:memory_rtl_1" with the following parameter: + Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" + Info (12134): Parameter "WIDTH_A" = "8" + Info (12134): Parameter "WIDTHAD_A" = "8" + Info (12134): Parameter "NUMWORDS_A" = "256" + Info (12134): Parameter "WIDTH_B" = "8" + Info (12134): Parameter "WIDTHAD_B" = "8" + Info (12134): Parameter "NUMWORDS_B" = "256" + Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" + Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" + Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" + Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" + Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1" + Info (12134): Parameter "INDATA_ACLR_A" = "NONE" + Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_lkc1.tdf + Info (12023): Found entity 1: altsyncram_lkc1 +Info (12130): Elaborated megafunction instantiation "RAM:inst3|altsyncram:memory_rtl_0" +Info (12133): Instantiated megafunction "RAM:inst3|altsyncram:memory_rtl_0" with the following parameter: + Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" + Info (12134): Parameter "WIDTH_A" = "8" + Info (12134): Parameter "WIDTHAD_A" = "8" + Info (12134): Parameter "NUMWORDS_A" = "256" + Info (12134): Parameter "WIDTH_B" = "8" + Info (12134): Parameter "WIDTHAD_B" = "8" + Info (12134): Parameter "NUMWORDS_B" = "256" + Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" + Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" + Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" + Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" + Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" + Info (12134): Parameter "INDATA_ACLR_A" = "NONE" + Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" + Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_8bi1.tdf + Info (12023): Found entity 1: altsyncram_8bi1 Warning (14284): Synthesized away the following node(s): - Warning (14285): Synthesized away the following PLL node(s): - Warning (14320): Synthesized away node "AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_clk[0]" + Warning (14285): Synthesized away the following RAM node(s): + Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a0" + Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a1" + Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a2" + Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a3" + Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a4" + Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a5" + Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a6" + Warning (14320): Synthesized away node "RAM:inst3|altsyncram:memory_rtl_1|altsyncram_lkc1:auto_generated|ram_block1a7" Info (286030): Timing-Driven Synthesis is running -Info (17049): 17 registers lost all their fanouts during netlist optimizations. +Info (17049): 11 registers lost all their fanouts during netlist optimizations. Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" - Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Warning (21074): Design contains 11 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "Address[7]" - Warning (15610): No output dependent on input pin "Address[6]" - Warning (15610): No output dependent on input pin "Address[5]" - Warning (15610): No output dependent on input pin "Address[4]" - Warning (15610): No output dependent on input pin "Address[3]" - Warning (15610): No output dependent on input pin "Address[2]" - Warning (15610): No output dependent on input pin "Address[1]" - Warning (15610): No output dependent on input pin "Address[0]" - Warning (15610): No output dependent on input pin "nOE" - Warning (15610): No output dependent on input pin "nWE" - Warning (15610): No output dependent on input pin "nCE" -Info (21057): Implemented 55 device resources after synthesis - the final resource count might be different + Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 143 device resources after synthesis - the final resource count might be different Info (21058): Implemented 12 input pins - Info (21059): Implemented 1 output pins + Info (21059): Implemented 3 output pins Info (21060): Implemented 8 bidirectional pins - Info (21061): Implemented 34 logic cells -Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 19 warnings - Info: Peak virtual memory: 4707 megabytes - Info: Processing ended: Tue Mar 12 16:24:16 2024 + Info (21061): Implemented 111 logic cells + Info (21064): Implemented 8 RAM segments + Info (21065): Implemented 1 PLLs +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 12 warnings + Info: Peak virtual memory: 4712 megabytes + Info: Processing ended: Tue Mar 12 17:46:44 2024 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/MainController/output_files/MainController.map.summary b/MainController/output_files/MainController.map.summary index 3d15480..f913228 100644 --- a/MainController/output_files/MainController.map.summary +++ b/MainController/output_files/MainController.map.summary @@ -1,14 +1,14 @@ -Analysis & Synthesis Status : Successful - Tue Mar 12 16:24:16 2024 +Analysis & Synthesis Status : Successful - Tue Mar 12 17:46:44 2024 Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version Revision Name : MainController Top-level Entity Name : MainController Family : Cyclone III -Total logic elements : 34 - Total combinational functions : 34 - Dedicated logic registers : 25 -Total registers : 25 -Total pins : 21 +Total logic elements : 102 + Total combinational functions : 67 + Dedicated logic registers : 80 +Total registers : 80 +Total pins : 23 Total virtual pins : 0 -Total memory bits : 0 +Total memory bits : 2,048 Embedded Multiplier 9-bit elements : 0 -Total PLLs : 0 +Total PLLs : 1 diff --git a/MainController/output_files/MainController.pin b/MainController/output_files/MainController.pin index 09c6f59..549661e 100644 --- a/MainController/output_files/MainController.pin +++ b/MainController/output_files/MainController.pin @@ -234,8 +234,8 @@ VCCINT : 163 : power : : 1.2V RESERVED_INPUT_WITH_WEAK_PULLUP : 164 : : : : 6 : GND : 165 : gnd : : : : FPGA_LED_1 : 166 : output : 3.3-V LVTTL : : 6 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : 167 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : 168 : : : : 6 : +FPGA_LED_2 : 167 : output : 3.3-V LVTTL : : 6 : Y +FPGA_LED_3 : 168 : output : 3.3-V LVTTL : : 6 : Y RESERVED_INPUT_WITH_WEAK_PULLUP : 169 : : : : 6 : VCCIO6 : 170 : power : : 3.3V : 6 : RESERVED_INPUT_WITH_WEAK_PULLUP : 171 : : : : 6 : diff --git a/MainController/output_files/MainController.sof b/MainController/output_files/MainController.sof index d61fb47..d5e97c0 100644 Binary files a/MainController/output_files/MainController.sof and b/MainController/output_files/MainController.sof differ diff --git a/MainController/output_files/MainController.sta.rpt b/MainController/output_files/MainController.sta.rpt index 4e1e56d..29a5149 100644 --- a/MainController/output_files/MainController.sta.rpt +++ b/MainController/output_files/MainController.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for MainController -Tue Mar 12 16:24:27 2024 +Tue Mar 12 17:46:55 2024 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version @@ -20,45 +20,65 @@ Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version 12. Slow 1200mV 85C Model Setup: 'FPGA_CLK' 13. Slow 1200mV 85C Model Hold: 'FPGA_CLK' 14. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK' - 15. Clock to Output Times - 16. Minimum Clock to Output Times - 17. Slow 1200mV 85C Model Metastability Report - 18. Slow 1200mV 0C Model Fmax Summary - 19. Slow 1200mV 0C Model Setup Summary - 20. Slow 1200mV 0C Model Hold Summary - 21. Slow 1200mV 0C Model Recovery Summary - 22. Slow 1200mV 0C Model Removal Summary - 23. Slow 1200mV 0C Model Minimum Pulse Width Summary - 24. Slow 1200mV 0C Model Setup: 'FPGA_CLK' - 25. Slow 1200mV 0C Model Hold: 'FPGA_CLK' - 26. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK' - 27. Clock to Output Times - 28. Minimum Clock to Output Times - 29. Slow 1200mV 0C Model Metastability Report - 30. Fast 1200mV 0C Model Setup Summary - 31. Fast 1200mV 0C Model Hold Summary - 32. Fast 1200mV 0C Model Recovery Summary - 33. Fast 1200mV 0C Model Removal Summary - 34. Fast 1200mV 0C Model Minimum Pulse Width Summary - 35. Fast 1200mV 0C Model Setup: 'FPGA_CLK' - 36. Fast 1200mV 0C Model Hold: 'FPGA_CLK' - 37. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK' - 38. Clock to Output Times - 39. Minimum Clock to Output Times - 40. Fast 1200mV 0C Model Metastability Report - 41. Multicorner Timing Analysis Summary - 42. Clock to Output Times - 43. Minimum Clock to Output Times - 44. Board Trace Model Assignments - 45. Input Transition Times - 46. Slow Corner Signal Integrity Metrics - 47. Fast Corner Signal Integrity Metrics - 48. Setup Transfers - 49. Hold Transfers - 50. Report TCCS - 51. Report RSKM - 52. Unconstrained Paths - 53. TimeQuest Timing Analyzer Messages + 15. Setup Times + 16. Hold Times + 17. Clock to Output Times + 18. Minimum Clock to Output Times + 19. Output Enable Times + 20. Minimum Output Enable Times + 21. Output Disable Times + 22. Minimum Output Disable Times + 23. Slow 1200mV 85C Model Metastability Report + 24. Slow 1200mV 0C Model Fmax Summary + 25. Slow 1200mV 0C Model Setup Summary + 26. Slow 1200mV 0C Model Hold Summary + 27. Slow 1200mV 0C Model Recovery Summary + 28. Slow 1200mV 0C Model Removal Summary + 29. Slow 1200mV 0C Model Minimum Pulse Width Summary + 30. Slow 1200mV 0C Model Setup: 'FPGA_CLK' + 31. Slow 1200mV 0C Model Hold: 'FPGA_CLK' + 32. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK' + 33. Setup Times + 34. Hold Times + 35. Clock to Output Times + 36. Minimum Clock to Output Times + 37. Output Enable Times + 38. Minimum Output Enable Times + 39. Output Disable Times + 40. Minimum Output Disable Times + 41. Slow 1200mV 0C Model Metastability Report + 42. Fast 1200mV 0C Model Setup Summary + 43. Fast 1200mV 0C Model Hold Summary + 44. Fast 1200mV 0C Model Recovery Summary + 45. Fast 1200mV 0C Model Removal Summary + 46. Fast 1200mV 0C Model Minimum Pulse Width Summary + 47. Fast 1200mV 0C Model Setup: 'FPGA_CLK' + 48. Fast 1200mV 0C Model Hold: 'FPGA_CLK' + 49. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK' + 50. Setup Times + 51. Hold Times + 52. Clock to Output Times + 53. Minimum Clock to Output Times + 54. Output Enable Times + 55. Minimum Output Enable Times + 56. Output Disable Times + 57. Minimum Output Disable Times + 58. Fast 1200mV 0C Model Metastability Report + 59. Multicorner Timing Analysis Summary + 60. Setup Times + 61. Hold Times + 62. Clock to Output Times + 63. Minimum Clock to Output Times + 64. Board Trace Model Assignments + 65. Input Transition Times + 66. Slow Corner Signal Integrity Metrics + 67. Fast Corner Signal Integrity Metrics + 68. Setup Transfers + 69. Hold Transfers + 70. Report TCCS + 71. Report RSKM + 72. Unconstrained Paths + 73. TimeQuest Timing Analyzer Messages @@ -112,13 +132,15 @@ applicable agreement for further details. +----------------------------+-------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ -; FPGA_CLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { FPGA_CLK } ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++--------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+----------------------------------------------------+------------------------------------------------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++--------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+----------------------------------------------------+------------------------------------------------------+ +; FPGA_CLK ; Base ; 40.000 ; 25.0 MHz ; 0.000 ; 20.000 ; ; ; ; ; ; ; ; ; ; ; { FPGA_CLK } ; +; inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; 50.00 ; 1 ; 4 ; ; ; ; ; false ; FPGA_CLK ; inst|altpll_component|auto_generated|pll1|inclk[0] ; { inst|altpll_component|auto_generated|pll1|clk[0] } ; +; inst|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 5.000 ; 200.0 MHz ; 0.000 ; 2.500 ; 50.00 ; 1 ; 8 ; ; ; ; ; false ; FPGA_CLK ; inst|altpll_component|auto_generated|pll1|inclk[0] ; { inst|altpll_component|auto_generated|pll1|clk[1] } ; ++--------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+----------------------------------------------------+------------------------------------------------------+ +--------------------------------------------------+ @@ -126,7 +148,7 @@ applicable agreement for further details. +------------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+------------+------+ -; 201.86 MHz ; 201.86 MHz ; FPGA_CLK ; ; +; 157.16 MHz ; 157.16 MHz ; FPGA_CLK ; ; +------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -142,7 +164,7 @@ HTML report is unavailable in plain text report export. +----------+--------+-----------------+ ; Clock ; Slack ; End Point TNS ; +----------+--------+-----------------+ -; FPGA_CLK ; -3.954 ; -84.790 ; +; FPGA_CLK ; 33.637 ; 0.000 ; +----------+--------+-----------------+ @@ -151,7 +173,7 @@ HTML report is unavailable in plain text report export. +----------+-------+-----------------+ ; Clock ; Slack ; End Point TNS ; +----------+-------+-----------------+ -; FPGA_CLK ; 0.435 ; 0.000 ; +; FPGA_CLK ; 0.454 ; 0.000 ; +----------+-------+-----------------+ @@ -172,350 +194,502 @@ No paths to report. +----------+--------+-------------------------------+ ; Clock ; Slack ; End Point TNS ; +----------+--------+-------------------------------+ -; FPGA_CLK ; -3.000 ; -40.175 ; +; FPGA_CLK ; 19.618 ; 0.000 ; +----------+--------+-------------------------------+ -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Setup: 'FPGA_CLK' ; -+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ; -; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ; -; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ; -; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ; -; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ; -; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ; -; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ; -; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ; -; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ; -; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ; -; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ; -; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ; -; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ; -; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ; -; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ; -; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ; -; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ; -; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ; -; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ; -; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ; -; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ; -; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ; -; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ; -; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ; -; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ; -; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ; -; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ; -; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ; -; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ; -; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ; -; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ; -; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ; -; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ; -; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ; -; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ; -; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ; -; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ; -; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ; -; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ; -; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ; -; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ; -; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ; -; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ; -; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ; -; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ; -; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ; -; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ; -; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ; -; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ; -; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ; -; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ; -; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ; -; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ; -; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ; -; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ; -; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ; -; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ; -; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ; -; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ; -; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ; -; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ; -; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ; -; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ; -; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ; -; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ; -; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ; -; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ; -; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ; -; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ; -; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ; -; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ; -; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ; -; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ; -; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ; -; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ; -; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ; -; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ; -; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ; -; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ; -; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ; -; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ; -; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ; -; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ; -; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ; -; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ; -; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ; -; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ; -; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ; -; -3.484 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.876 ; -; -3.484 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.876 ; -; -3.484 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.876 ; -; -3.484 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.876 ; -; -3.477 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.869 ; -; -3.477 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.869 ; -; -3.477 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.869 ; -; -3.477 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.869 ; -; -3.475 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.397 ; -; -3.475 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.397 ; -; -3.475 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.397 ; -; -3.475 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.397 ; -+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'FPGA_CLK' ; ++--------+--------------------------------------------------------------------------------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+--------------------------------------------------------------------------------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.637 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.288 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.669 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.256 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.835 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.076 ; 6.090 ; +; 33.931 ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~portb_address_reg0 ; RAM:inst3|data0[5]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.477 ; 5.593 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 33.982 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.940 ; +; 34.070 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[4]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.859 ; +; 34.080 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[7]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.849 ; +; 34.081 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[1]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.848 ; +; 34.081 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[2]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.848 ; +; 34.105 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[6]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.824 ; +; 34.107 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[0]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.822 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.121 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.801 ; +; 34.128 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[3]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.801 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.153 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.769 ; +; 34.303 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[5]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.626 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.319 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.079 ; 5.603 ; +; 34.356 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[4]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.573 ; +; 34.366 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[7]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.563 ; +; 34.367 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[1]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.562 ; +; 34.367 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[2]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.562 ; +; 34.391 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[6]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.538 ; +; 34.393 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[0]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.536 ; +; 34.414 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[3]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.072 ; 5.515 ; ++--------+--------------------------------------------------------------------------------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Hold: 'FPGA_CLK' ; -+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; 0.435 ; LedBlink:inst2|ledBuf ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 0.746 ; -; 0.611 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.392 ; -; 0.612 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.393 ; -; 0.620 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.402 ; -; 0.629 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.411 ; -; 0.629 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.410 ; -; 0.726 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.037 ; -; 0.729 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.040 ; -; 0.729 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.039 ; -; 0.730 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.041 ; -; 0.730 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.041 ; -; 0.731 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.041 ; -; 0.731 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.041 ; -; 0.732 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.042 ; -; 0.733 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.043 ; -; 0.742 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.523 ; -; 0.744 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.054 ; -; 0.746 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.037 ; -; 0.746 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.056 ; -; 0.748 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.039 ; -; 0.749 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.040 ; -; 0.750 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.041 ; -; 0.751 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.532 ; -; 0.758 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.540 ; -; 0.760 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.541 ; -; 0.760 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.542 ; -; 0.763 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.054 ; -; 0.766 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.057 ; -; 0.767 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.549 ; -; 0.769 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.551 ; -; 0.769 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.550 ; -; 0.771 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.062 ; -; 0.776 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.558 ; -; 0.785 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.567 ; -; 0.809 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.590 ; -; 0.858 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.639 ; -; 0.882 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.663 ; -; 0.891 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.672 ; -; 0.892 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.673 ; -; 0.898 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.680 ; -; 0.900 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.682 ; -; 0.900 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.681 ; -; 0.906 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.688 ; -; 0.907 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.689 ; -; 0.909 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.690 ; -; 0.915 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.697 ; -; 0.916 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.697 ; -; 0.916 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.698 ; -; 0.925 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.707 ; -; 0.959 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.250 ; -; 0.960 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.741 ; -; 0.963 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.744 ; -; 0.966 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.257 ; -; 0.973 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.264 ; -; 0.978 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.269 ; -; 0.979 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.270 ; -; 0.986 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.767 ; -; 1.023 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.804 ; -; 1.032 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.813 ; -; 1.038 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.820 ; -; 1.046 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.828 ; -; 1.055 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.837 ; -; 1.056 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.838 ; -; 1.057 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.838 ; -; 1.081 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.392 ; -; 1.085 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.395 ; -; 1.085 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.395 ; -; 1.090 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.400 ; -; 1.091 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.402 ; -; 1.093 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.403 ; -; 1.094 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.404 ; -; 1.098 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.408 ; -; 1.099 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.409 ; -; 1.100 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.411 ; -; 1.103 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.413 ; -; 1.103 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.884 ; -; 1.110 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.401 ; -; 1.117 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.898 ; -; 1.118 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.409 ; -; 1.122 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.903 ; -; 1.126 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.417 ; -; 1.127 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.418 ; -; 1.136 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.427 ; -; 1.138 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.919 ; -; 1.163 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.944 ; -; 1.165 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.571 ; 1.948 ; -; 1.167 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.477 ; -; 1.172 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.953 ; -; 1.186 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.968 ; -; 1.195 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.977 ; -; 1.195 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.977 ; -; 1.195 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.977 ; -; 1.197 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.978 ; -; 1.212 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.523 ; -; 1.216 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.526 ; -; 1.216 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.526 ; -; 1.221 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.532 ; -; 1.223 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.534 ; -; 1.225 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.535 ; -; 1.231 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.542 ; -+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'FPGA_CLK' ; ++-------+-----------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.454 ; RAM:inst3|stateMM0.Waiting ; RAM:inst3|stateMM0.Waiting ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 0.746 ; +; 0.455 ; LedBlink:inst2|ledBuf ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 0.746 ; +; 0.502 ; RAM:inst3|memory_rtl_0_bypass[18] ; RAM:inst3|data0[1]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 0.794 ; +; 0.502 ; RAM:inst3|memory_rtl_0_bypass[19] ; RAM:inst3|data0[2]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 0.794 ; +; 0.502 ; RAM:inst3|memory_rtl_0_bypass[22] ; RAM:inst3|data0[5]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 0.794 ; +; 0.504 ; RAM:inst3|memory_rtl_0_bypass[24] ; RAM:inst3|data0[7]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 0.796 ; +; 0.529 ; RAM:inst3|addr[6] ; RAM:inst3|memory_rtl_0_bypass[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 0.820 ; +; 0.643 ; RAM:inst3|memory_rtl_0_bypass[20] ; RAM:inst3|data0[3]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 0.935 ; +; 0.644 ; RAM:inst3|memory_rtl_0_bypass[21] ; RAM:inst3|data0[4]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 0.936 ; +; 0.695 ; RAM:inst3|ce0Prev ; RAM:inst3|stateMM0.Reading ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 0.987 ; +; 0.695 ; RAM:inst3|ce0Prev ; RAM:inst3|stateMM0.Writing ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 0.987 ; +; 0.725 ; RAM:inst3|addr[7] ; RAM:inst3|memory_rtl_0_bypass[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.016 ; +; 0.741 ; RAM:inst3|memory_rtl_0_bypass[23] ; RAM:inst3|data0[6]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 1.033 ; +; 0.742 ; RAM:inst3|memory_rtl_0_bypass[17] ; RAM:inst3|data0[0]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 1.034 ; +; 0.746 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.037 ; +; 0.746 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.037 ; +; 0.746 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.037 ; +; 0.746 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.037 ; +; 0.747 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.038 ; +; 0.749 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.040 ; +; 0.749 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.040 ; +; 0.749 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.040 ; +; 0.749 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.040 ; +; 0.749 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.040 ; +; 0.749 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.040 ; +; 0.750 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.041 ; +; 0.750 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.041 ; +; 0.750 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.041 ; +; 0.750 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.041 ; +; 0.752 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.043 ; +; 0.752 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.043 ; +; 0.763 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.054 ; +; 0.765 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.056 ; +; 0.766 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.057 ; +; 0.771 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.062 ; +; 0.773 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.064 ; +; 0.775 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.066 ; +; 0.775 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.066 ; +; 0.785 ; RAM:inst3|stateMM0.Waiting ; RAM:inst3|stateMM0.Reading ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 1.077 ; +; 0.786 ; RAM:inst3|stateMM0.Waiting ; RAM:inst3|stateMM0.Writing ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 1.078 ; +; 0.814 ; RAM:inst3|ce0Prev ; RAM:inst3|stateMM0.Waiting ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.080 ; 1.106 ; +; 0.854 ; RAM:inst3|addr[5] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.483 ; 1.591 ; +; 0.939 ; RAM:inst3|addr[4] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.483 ; 1.676 ; +; 1.027 ; RAM:inst3|addr[2] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.483 ; 1.764 ; +; 1.070 ; RAM:inst3|addr[7] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.483 ; 1.807 ; +; 1.101 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.392 ; +; 1.101 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.392 ; +; 1.101 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.392 ; +; 1.102 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.393 ; +; 1.103 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.394 ; +; 1.103 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.394 ; +; 1.104 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.395 ; +; 1.104 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.395 ; +; 1.104 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.076 ; 1.392 ; +; 1.110 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.401 ; +; 1.110 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.401 ; +; 1.110 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.401 ; +; 1.111 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.402 ; +; 1.111 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.402 ; +; 1.111 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.402 ; +; 1.113 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.404 ; +; 1.113 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.404 ; +; 1.117 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.408 ; +; 1.119 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.410 ; +; 1.119 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.410 ; +; 1.120 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.411 ; +; 1.120 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.411 ; +; 1.120 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.411 ; +; 1.122 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.413 ; +; 1.122 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.076 ; 1.410 ; +; 1.126 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.417 ; +; 1.126 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.417 ; +; 1.127 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.418 ; +; 1.135 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.426 ; +; 1.136 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.427 ; +; 1.136 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.427 ; +; 1.136 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.427 ; +; 1.145 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.436 ; +; 1.145 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.436 ; +; 1.230 ; RAM:inst3|we0Prev ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_we_reg ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.471 ; 1.955 ; +; 1.232 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.523 ; +; 1.232 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.523 ; +; 1.232 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.523 ; +; 1.233 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.524 ; +; 1.234 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.525 ; +; 1.234 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.525 ; +; 1.235 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.526 ; +; 1.235 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.526 ; +; 1.235 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.076 ; 1.523 ; +; 1.241 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.532 ; +; 1.241 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.532 ; +; 1.242 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.533 ; +; 1.243 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.534 ; +; 1.243 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.534 ; +; 1.244 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.535 ; +; 1.244 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.076 ; 1.532 ; +; 1.244 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.076 ; 1.532 ; +; 1.248 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.539 ; +; 1.250 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.541 ; +; 1.250 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.541 ; ++-------+-----------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -+--------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK' ; -+--------+--------------+----------------+------------------+----------+------------+--------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+----------+------------+--------------------------------+ -; -3.000 ; 1.000 ; 4.000 ; Port Rate ; FPGA_CLK ; Rise ; FPGA_CLK ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; -; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; -; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; -; 0.325 ; 0.545 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; -; 0.325 ; 0.545 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; -; 0.325 ; 0.545 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; -; 0.325 ; 0.545 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; -; 0.325 ; 0.545 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; -; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; -; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; -; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ; -; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ; -; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ; -; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ; -; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ; -; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; -; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; -; 0.385 ; 0.385 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~input|o ; -; 0.395 ; 0.395 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|inclk[0] ; -; 0.395 ; 0.395 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|outclk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[0]|clk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[15]|clk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[16]|clk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[17]|clk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[18]|clk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[1]|clk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[2]|clk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[4]|clk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[5]|clk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[7]|clk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[8]|clk ; -; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[9]|clk ; -; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[10]|clk ; -; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[11]|clk ; -; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[12]|clk ; -; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[13]|clk ; -; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[14]|clk ; -; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[19]|clk ; -; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[20]|clk ; -; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[21]|clk ; -; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[22]|clk ; -+--------+--------------+----------------+------------------+----------+------------+--------------------------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK' ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------------+ +; 19.618 ; 19.853 ; 0.235 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 19.619 ; 19.854 ; 0.235 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 19.619 ; 19.854 ; 0.235 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_we_reg ; +; 19.621 ; 19.856 ; 0.235 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ; +; 19.757 ; 19.945 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|ce0Prev ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[0]~reg0 ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[1]~reg0 ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[2]~reg0 ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[3]~reg0 ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[4]~reg0 ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[5]~reg0 ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[6]~reg0 ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[7]~reg0 ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[0] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[17] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[18] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[19] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[1] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[20] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[21] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[22] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[23] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[24] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[3] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[5] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[7] ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|oe0Prev ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|stateMM0.Reading ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|stateMM0.Waiting ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|stateMM0.Writing ; +; 19.758 ; 19.946 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|we0Prev ; +; 19.759 ; 19.947 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[0]~en ; +; 19.759 ; 19.947 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[1]~en ; +; 19.759 ; 19.947 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[2]~en ; +; 19.759 ; 19.947 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[3]~en ; +; 19.759 ; 19.947 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[4]~en ; +; 19.759 ; 19.947 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[5]~en ; +; 19.759 ; 19.947 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[6]~en ; +; 19.759 ; 19.947 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[7]~en ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[0] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[1] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[2] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[3] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[4] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[5] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[6] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[7] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[10] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[11] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[12] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[13] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[14] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[15] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[16] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[2] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[4] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[6] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[8] ; +; 19.760 ; 19.948 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[9] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[0] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[1] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[2] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[3] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[4] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[5] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[6] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[7] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[10] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[11] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[12] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[13] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[14] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[15] ; +; 19.830 ; 20.050 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[16] ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------------+ -+------------------------------------------------------------------------+ -; Clock to Output Times ; -+------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------+------------+-------+-------+------------+-----------------+ -; FPGA_LED_1 ; FPGA_CLK ; 7.359 ; 7.560 ; Rise ; FPGA_CLK ; -+------------+------------+-------+-------+------------+-----------------+ ++-------------------------------------------------------------------------+ +; Setup Times ; ++-------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------+------------+-------+-------+------------+-----------------+ +; Address[*] ; FPGA_CLK ; 4.276 ; 4.467 ; Rise ; FPGA_CLK ; +; Address[0] ; FPGA_CLK ; 3.265 ; 3.408 ; Rise ; FPGA_CLK ; +; Address[1] ; FPGA_CLK ; 3.595 ; 3.838 ; Rise ; FPGA_CLK ; +; Address[2] ; FPGA_CLK ; 3.758 ; 4.009 ; Rise ; FPGA_CLK ; +; Address[3] ; FPGA_CLK ; 3.867 ; 4.116 ; Rise ; FPGA_CLK ; +; Address[4] ; FPGA_CLK ; 4.197 ; 4.467 ; Rise ; FPGA_CLK ; +; Address[5] ; FPGA_CLK ; 4.276 ; 4.446 ; Rise ; FPGA_CLK ; +; Address[6] ; FPGA_CLK ; 3.546 ; 3.843 ; Rise ; FPGA_CLK ; +; Address[7] ; FPGA_CLK ; 3.041 ; 3.255 ; Rise ; FPGA_CLK ; +; Data[*] ; FPGA_CLK ; 2.611 ; 2.949 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 2.367 ; 2.631 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 2.611 ; 2.949 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 2.576 ; 2.925 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 2.580 ; 2.915 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 2.384 ; 2.721 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 2.368 ; 2.710 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 2.314 ; 2.657 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 2.351 ; 2.677 ; Rise ; FPGA_CLK ; +; nCE ; FPGA_CLK ; 6.739 ; 6.730 ; Rise ; FPGA_CLK ; +; nOE ; FPGA_CLK ; 5.549 ; 5.716 ; Rise ; FPGA_CLK ; +; nWE ; FPGA_CLK ; 5.354 ; 5.775 ; Rise ; FPGA_CLK ; ++-------------+------------+-------+-------+------------+-----------------+ -+------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------+------------+-------+-------+------------+-----------------+ -; FPGA_LED_1 ; FPGA_CLK ; 7.176 ; 7.373 ; Rise ; FPGA_CLK ; -+------------+------------+-------+-------+------------+-----------------+ ++---------------------------------------------------------------------------+ +; Hold Times ; ++-------------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------+------------+--------+--------+------------+-----------------+ +; Address[*] ; FPGA_CLK ; -1.818 ; -2.116 ; Rise ; FPGA_CLK ; +; Address[0] ; FPGA_CLK ; -1.985 ; -2.228 ; Rise ; FPGA_CLK ; +; Address[1] ; FPGA_CLK ; -2.253 ; -2.575 ; Rise ; FPGA_CLK ; +; Address[2] ; FPGA_CLK ; -2.425 ; -2.773 ; Rise ; FPGA_CLK ; +; Address[3] ; FPGA_CLK ; -2.520 ; -2.839 ; Rise ; FPGA_CLK ; +; Address[4] ; FPGA_CLK ; -2.118 ; -2.492 ; Rise ; FPGA_CLK ; +; Address[5] ; FPGA_CLK ; -2.399 ; -2.691 ; Rise ; FPGA_CLK ; +; Address[6] ; FPGA_CLK ; -2.207 ; -2.527 ; Rise ; FPGA_CLK ; +; Address[7] ; FPGA_CLK ; -1.818 ; -2.116 ; Rise ; FPGA_CLK ; +; Data[*] ; FPGA_CLK ; -1.154 ; -1.422 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; -1.154 ; -1.422 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; -1.302 ; -1.642 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; -1.611 ; -1.913 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; -1.577 ; -1.881 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; -1.251 ; -1.594 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; -1.257 ; -1.614 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; -1.251 ; -1.595 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; -1.565 ; -1.858 ; Rise ; FPGA_CLK ; +; nCE ; FPGA_CLK ; -1.930 ; -2.329 ; Rise ; FPGA_CLK ; +; nOE ; FPGA_CLK ; -2.141 ; -2.437 ; Rise ; FPGA_CLK ; +; nWE ; FPGA_CLK ; -1.920 ; -2.176 ; Rise ; FPGA_CLK ; ++-------------+------------+--------+--------+------------+-----------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data[*] ; FPGA_CLK ; 9.467 ; 8.950 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 7.009 ; 6.766 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 7.283 ; 6.997 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 7.398 ; 7.139 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 7.316 ; 7.015 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 8.372 ; 8.094 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 8.254 ; 7.936 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 9.467 ; 8.950 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 7.543 ; 7.354 ; Rise ; FPGA_CLK ; +; FPGA_LED_1 ; FPGA_CLK ; 7.494 ; 7.753 ; Rise ; FPGA_CLK ; +; FPGA_LED_2 ; FPGA_CLK ; 2.701 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_2 ; FPGA_CLK ; ; 2.542 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_3 ; FPGA_CLK ; 2.700 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; FPGA_LED_3 ; FPGA_CLK ; ; 2.541 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[1] ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data[*] ; FPGA_CLK ; 6.845 ; 6.608 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 6.845 ; 6.608 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 7.110 ; 6.830 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 7.219 ; 6.966 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 7.141 ; 6.848 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 8.154 ; 7.882 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 8.040 ; 7.730 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 9.294 ; 8.778 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 7.358 ; 7.172 ; Rise ; FPGA_CLK ; +; FPGA_LED_1 ; FPGA_CLK ; 7.306 ; 7.558 ; Rise ; FPGA_CLK ; +; FPGA_LED_2 ; FPGA_CLK ; 2.230 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_2 ; FPGA_CLK ; ; 2.073 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_3 ; FPGA_CLK ; 2.229 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; FPGA_LED_3 ; FPGA_CLK ; ; 2.072 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[1] ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Output Enable Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 7.139 ; 7.139 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 7.139 ; 7.139 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 7.496 ; 7.496 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 7.439 ; 7.439 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 7.482 ; 7.482 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 8.096 ; 8.096 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 8.123 ; 8.123 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 7.745 ; 7.745 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 7.864 ; 7.864 ; Rise ; FPGA_CLK ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 6.449 ; 6.495 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 6.449 ; 6.495 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 6.792 ; 6.838 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 6.738 ; 6.784 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 6.779 ; 6.825 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 7.367 ; 7.413 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 7.394 ; 7.440 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 7.031 ; 7.077 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 7.145 ; 7.191 ; Rise ; FPGA_CLK ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Output Disable Times ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 6.753 ; 7.013 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 6.753 ; 7.013 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 7.029 ; 7.289 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 6.990 ; 7.250 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 7.010 ; 7.270 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 7.705 ; 7.965 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 7.724 ; 7.984 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 7.386 ; 7.646 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 7.419 ; 7.679 ; Rise ; FPGA_CLK ; ++-----------+------------+-----------+-----------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 6.328 ; 6.328 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 6.328 ; 6.328 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 6.593 ; 6.593 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 6.556 ; 6.556 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 6.575 ; 6.575 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 7.241 ; 7.241 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 7.260 ; 7.260 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 6.935 ; 6.935 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 6.967 ; 6.967 ; Rise ; FPGA_CLK ; ++-----------+------------+-----------+-----------+------------+-----------------+ ---------------------------------------------- @@ -524,13 +698,13 @@ No paths to report. No synchronizer chains to report. -+-------------------------------------------------+ -; Slow 1200mV 0C Model Fmax Summary ; -+-----------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+-----------+-----------------+------------+------+ -; 214.5 MHz ; 214.5 MHz ; FPGA_CLK ; ; -+-----------+-----------------+------------+------+ ++--------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 169.32 MHz ; 169.32 MHz ; FPGA_CLK ; ; ++------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -539,7 +713,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------+--------+----------------+ ; Clock ; Slack ; End Point TNS ; +----------+--------+----------------+ -; FPGA_CLK ; -3.662 ; -77.889 ; +; FPGA_CLK ; 34.094 ; 0.000 ; +----------+--------+----------------+ @@ -548,7 +722,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------+-------+----------------+ ; Clock ; Slack ; End Point TNS ; +----------+-------+----------------+ -; FPGA_CLK ; 0.384 ; 0.000 ; +; FPGA_CLK ; 0.402 ; 0.000 ; +----------+-------+----------------+ @@ -569,350 +743,502 @@ No paths to report. +----------+--------+------------------------------+ ; Clock ; Slack ; End Point TNS ; +----------+--------+------------------------------+ -; FPGA_CLK ; -3.000 ; -40.175 ; +; FPGA_CLK ; 19.600 ; 0.000 ; +----------+--------+------------------------------+ -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Setup: 'FPGA_CLK' ; -+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ; -; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ; -; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ; -; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ; -; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ; -; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ; -; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ; -; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ; -; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ; -; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ; -; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ; -; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ; -; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ; -; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ; -; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ; -; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ; -; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ; -; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ; -; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ; -; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ; -; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ; -; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ; -; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ; -; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ; -; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ; -; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ; -; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ; -; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ; -; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ; -; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ; -; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ; -; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ; -; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ; -; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ; -; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ; -; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ; -; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ; -; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ; -; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ; -; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ; -; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ; -; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ; -; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ; -; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ; -; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ; -; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ; -; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ; -; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ; -; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ; -; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ; -; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ; -; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ; -; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ; -; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ; -; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ; -; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ; -; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ; -; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ; -; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ; -; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ; -; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ; -; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ; -; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ; -; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ; -; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ; -; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ; -; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ; -; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ; -; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ; -; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ; -; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ; -; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ; -; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ; -; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ; -; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ; -; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ; -; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ; -; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ; -; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ; -; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ; -; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ; -; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ; -; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ; -; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ; -; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ; -; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ; -; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ; -; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ; -; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ; -; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ; -; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ; -; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ; -; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ; -; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ; -; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ; -; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ; -; -3.210 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.381 ; 4.593 ; -; -3.210 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.381 ; 4.593 ; -; -3.210 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.381 ; 4.593 ; -; -3.210 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.381 ; 4.593 ; -+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'FPGA_CLK' ; ++--------+--------------------------------------------------------------------------------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+--------------------------------------------------------------------------------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.094 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.839 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.109 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.824 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.258 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.069 ; 5.675 ; +; 34.338 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[4]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.599 ; +; 34.343 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[2]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.594 ; +; 34.343 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[7]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.594 ; +; 34.344 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[1]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.593 ; +; 34.363 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[6]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.574 ; +; 34.365 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[0]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.572 ; +; 34.375 ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~portb_address_reg0 ; RAM:inst3|data0[5]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.421 ; 5.206 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.378 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.553 ; +; 34.382 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[3]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.555 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.411 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.535 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.396 ; +; 34.551 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[5]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.386 ; +; 34.600 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[4]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.337 ; +; 34.605 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[2]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.332 ; +; 34.605 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[7]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.332 ; +; 34.606 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[1]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.331 ; +; 34.625 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[6]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.312 ; +; 34.627 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[0]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.310 ; +; 34.644 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[3]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.065 ; 5.293 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; +; 34.684 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.071 ; 5.247 ; ++--------+--------------------------------------------------------------------------------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Hold: 'FPGA_CLK' ; -+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; 0.384 ; LedBlink:inst2|ledBuf ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.669 ; -; 0.545 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.283 ; -; 0.546 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.282 ; -; 0.551 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.287 ; -; 0.560 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.298 ; -; 0.563 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.299 ; -; 0.643 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.379 ; -; 0.651 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.389 ; -; 0.667 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.404 ; -; 0.667 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.405 ; -; 0.670 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.406 ; -; 0.676 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.089 ; 0.960 ; -; 0.678 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.963 ; -; 0.679 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.089 ; 0.963 ; -; 0.679 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.964 ; -; 0.679 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.964 ; -; 0.680 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.089 ; 0.964 ; -; 0.680 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.418 ; -; 0.680 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.418 ; -; 0.682 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.420 ; -; 0.682 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.089 ; 0.966 ; -; 0.682 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.967 ; -; 0.683 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.968 ; -; 0.684 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.421 ; -; 0.689 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.974 ; -; 0.693 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.978 ; -; 0.694 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.960 ; -; 0.694 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.430 ; -; 0.697 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.963 ; -; 0.697 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.435 ; -; 0.698 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.964 ; -; 0.699 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.965 ; -; 0.708 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.974 ; -; 0.713 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.979 ; -; 0.716 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.982 ; -; 0.764 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.501 ; -; 0.773 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.511 ; -; 0.785 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.523 ; -; 0.789 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.527 ; -; 0.789 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.526 ; -; 0.789 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.525 ; -; 0.791 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.527 ; -; 0.791 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.528 ; -; 0.795 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.531 ; -; 0.802 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.540 ; -; 0.802 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.540 ; -; 0.806 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.543 ; -; 0.810 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.548 ; -; 0.819 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.557 ; -; 0.826 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.562 ; -; 0.868 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.134 ; -; 0.872 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.138 ; -; 0.872 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.138 ; -; 0.884 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.150 ; -; 0.886 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.622 ; -; 0.892 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.158 ; -; 0.892 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.628 ; -; 0.895 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.633 ; -; 0.899 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.635 ; -; 0.907 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.645 ; -; 0.911 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.647 ; -; 0.916 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.653 ; -; 0.924 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.662 ; -; 0.932 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.670 ; -; 0.997 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.282 ; -; 0.998 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.283 ; -; 0.999 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.089 ; 1.283 ; -; 1.001 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.286 ; -; 1.002 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.287 ; -; 1.002 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.287 ; -; 1.003 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.288 ; -; 1.007 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.744 ; -; 1.013 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.298 ; -; 1.013 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.298 ; -; 1.013 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.298 ; -; 1.013 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.750 ; -; 1.016 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.301 ; -; 1.018 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.284 ; -; 1.018 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.754 ; -; 1.020 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.756 ; -; 1.029 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.767 ; -; 1.030 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.296 ; -; 1.030 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.296 ; -; 1.031 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.316 ; -; 1.032 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.769 ; -; 1.035 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.771 ; -; 1.038 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.304 ; -; 1.038 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.775 ; -; 1.039 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.777 ; -; 1.047 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.313 ; -; 1.084 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.820 ; -; 1.085 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.823 ; -; 1.085 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.823 ; -; 1.085 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.823 ; -; 1.094 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.379 ; -; 1.100 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.385 ; -; 1.100 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.385 ; -; 1.118 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.384 ; -; 1.119 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.404 ; -; 1.120 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.405 ; -+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'FPGA_CLK' ; ++-------+-----------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.402 ; RAM:inst3|stateMM0.Waiting ; RAM:inst3|stateMM0.Waiting ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 0.669 ; +; 0.404 ; LedBlink:inst2|ledBuf ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.070 ; 0.669 ; +; 0.470 ; RAM:inst3|memory_rtl_0_bypass[18] ; RAM:inst3|data0[1]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 0.737 ; +; 0.470 ; RAM:inst3|memory_rtl_0_bypass[19] ; RAM:inst3|data0[2]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 0.737 ; +; 0.470 ; RAM:inst3|memory_rtl_0_bypass[22] ; RAM:inst3|data0[5]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 0.737 ; +; 0.472 ; RAM:inst3|memory_rtl_0_bypass[24] ; RAM:inst3|data0[7]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 0.739 ; +; 0.494 ; RAM:inst3|addr[6] ; RAM:inst3|memory_rtl_0_bypass[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.760 ; +; 0.599 ; RAM:inst3|memory_rtl_0_bypass[20] ; RAM:inst3|data0[3]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 0.866 ; +; 0.600 ; RAM:inst3|memory_rtl_0_bypass[21] ; RAM:inst3|data0[4]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 0.867 ; +; 0.648 ; RAM:inst3|ce0Prev ; RAM:inst3|stateMM0.Writing ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 0.915 ; +; 0.650 ; RAM:inst3|ce0Prev ; RAM:inst3|stateMM0.Reading ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 0.917 ; +; 0.670 ; RAM:inst3|addr[7] ; RAM:inst3|memory_rtl_0_bypass[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.936 ; +; 0.687 ; RAM:inst3|memory_rtl_0_bypass[23] ; RAM:inst3|data0[6]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 0.954 ; +; 0.688 ; RAM:inst3|memory_rtl_0_bypass[17] ; RAM:inst3|data0[0]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 0.955 ; +; 0.693 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.959 ; +; 0.694 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.960 ; +; 0.694 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.960 ; +; 0.695 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.961 ; +; 0.695 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.961 ; +; 0.696 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.962 ; +; 0.696 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.962 ; +; 0.697 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.963 ; +; 0.697 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.963 ; +; 0.697 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.963 ; +; 0.698 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.964 ; +; 0.698 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.964 ; +; 0.698 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.964 ; +; 0.699 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.965 ; +; 0.699 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.965 ; +; 0.701 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.967 ; +; 0.701 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.967 ; +; 0.708 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.974 ; +; 0.711 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.977 ; +; 0.713 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.979 ; +; 0.714 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.980 ; +; 0.721 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.987 ; +; 0.722 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.988 ; +; 0.724 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.990 ; +; 0.741 ; RAM:inst3|stateMM0.Waiting ; RAM:inst3|stateMM0.Reading ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 1.008 ; +; 0.742 ; RAM:inst3|stateMM0.Waiting ; RAM:inst3|stateMM0.Writing ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 1.009 ; +; 0.760 ; RAM:inst3|ce0Prev ; RAM:inst3|stateMM0.Waiting ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.072 ; 1.027 ; +; 0.795 ; RAM:inst3|addr[5] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.427 ; 1.452 ; +; 0.869 ; RAM:inst3|addr[4] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.427 ; 1.526 ; +; 0.933 ; RAM:inst3|addr[2] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.427 ; 1.590 ; +; 0.985 ; RAM:inst3|addr[7] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.427 ; 1.642 ; +; 1.014 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.280 ; +; 1.015 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.281 ; +; 1.016 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.282 ; +; 1.017 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.283 ; +; 1.017 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.283 ; +; 1.017 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.283 ; +; 1.018 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.284 ; +; 1.018 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.284 ; +; 1.018 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.069 ; 1.282 ; +; 1.018 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.284 ; +; 1.018 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.284 ; +; 1.020 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.286 ; +; 1.020 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.286 ; +; 1.020 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.286 ; +; 1.021 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.287 ; +; 1.021 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.287 ; +; 1.022 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.288 ; +; 1.028 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.294 ; +; 1.029 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.295 ; +; 1.030 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.296 ; +; 1.032 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.298 ; +; 1.032 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.298 ; +; 1.032 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.298 ; +; 1.033 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.299 ; +; 1.034 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.300 ; +; 1.035 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.069 ; 1.299 ; +; 1.035 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.301 ; +; 1.036 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.302 ; +; 1.040 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.306 ; +; 1.041 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.307 ; +; 1.045 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.311 ; +; 1.047 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.313 ; +; 1.055 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.321 ; +; 1.056 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.322 ; +; 1.111 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.377 ; +; 1.113 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.379 ; +; 1.113 ; RAM:inst3|we0Prev ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_we_reg ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.416 ; 1.759 ; +; 1.115 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.069 ; 1.379 ; +; 1.115 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.381 ; +; 1.115 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.381 ; +; 1.117 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.383 ; +; 1.117 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.383 ; +; 1.119 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.385 ; +; 1.119 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.385 ; +; 1.126 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.392 ; +; 1.131 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.397 ; +; 1.136 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.402 ; +; 1.138 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.404 ; +; 1.139 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.405 ; +; 1.139 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.069 ; 1.403 ; +; 1.139 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.405 ; +; 1.139 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.405 ; +; 1.140 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.406 ; +; 1.140 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.406 ; +; 1.140 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.069 ; 1.404 ; ++-------+-----------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -+--------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK' ; -+--------+--------------+----------------+------------------+----------+------------+--------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+----------+------------+--------------------------------+ -; -3.000 ; 1.000 ; 4.000 ; Port Rate ; FPGA_CLK ; Rise ; FPGA_CLK ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; -; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; -; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; -; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; -; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; -; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; -; 0.385 ; 0.385 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~input|o ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[0]|clk ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[15]|clk ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[16]|clk ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[17]|clk ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[18]|clk ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[1]|clk ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[2]|clk ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[4]|clk ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[5]|clk ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[7]|clk ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[8]|clk ; -; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[9]|clk ; -; 0.388 ; 0.388 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|inclk[0] ; -; 0.388 ; 0.388 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|outclk ; -; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[10]|clk ; -; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[11]|clk ; -; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[12]|clk ; -; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[13]|clk ; -; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[14]|clk ; -; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[19]|clk ; -; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[20]|clk ; -; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[21]|clk ; -; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[22]|clk ; -+--------+--------------+----------------+------------------+----------+------------+--------------------------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK' ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------------+ +; 19.600 ; 19.830 ; 0.230 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 19.602 ; 19.832 ; 0.230 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 19.602 ; 19.832 ; 0.230 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_we_reg ; +; 19.604 ; 19.834 ; 0.230 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; +; 19.752 ; 19.936 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|ce0Prev ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[0]~reg0 ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[1]~reg0 ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[2]~reg0 ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[3]~reg0 ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[4]~reg0 ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[5]~reg0 ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[6]~reg0 ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[7]~reg0 ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[0] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[17] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[18] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[19] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[1] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[20] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[21] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[22] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[23] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[24] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[3] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[5] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[7] ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|oe0Prev ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|stateMM0.Reading ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|stateMM0.Waiting ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|stateMM0.Writing ; +; 19.753 ; 19.937 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|we0Prev ; +; 19.754 ; 19.938 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[0]~en ; +; 19.754 ; 19.938 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[1]~en ; +; 19.754 ; 19.938 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[2]~en ; +; 19.754 ; 19.938 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[3]~en ; +; 19.754 ; 19.938 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[4]~en ; +; 19.754 ; 19.938 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[5]~en ; +; 19.754 ; 19.938 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[6]~en ; +; 19.754 ; 19.938 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[7]~en ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[0] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[1] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[2] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[3] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[4] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[5] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[6] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[7] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[13] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[14] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[15] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[16] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[2] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[4] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[6] ; +; 19.755 ; 19.939 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[8] ; +; 19.756 ; 19.940 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; +; 19.756 ; 19.940 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[10] ; +; 19.756 ; 19.940 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[11] ; +; 19.756 ; 19.940 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[12] ; +; 19.756 ; 19.940 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[9] ; +; 19.830 ; 19.830 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; 19.830 ; 19.830 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; 19.830 ; 19.830 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst|altpll_component|auto_generated|pll1|observablevcoout ; +; 19.840 ; 20.056 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[10] ; +; 19.840 ; 20.056 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[11] ; +; 19.840 ; 20.056 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[12] ; +; 19.840 ; 20.056 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[9] ; +; 19.841 ; 20.057 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; +; 19.841 ; 20.057 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[0] ; +; 19.841 ; 20.057 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[1] ; +; 19.841 ; 20.057 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[2] ; +; 19.841 ; 20.057 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[3] ; +; 19.841 ; 20.057 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[4] ; +; 19.841 ; 20.057 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[5] ; +; 19.841 ; 20.057 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[6] ; +; 19.841 ; 20.057 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[7] ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------------+ -+------------------------------------------------------------------------+ -; Clock to Output Times ; -+------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------+------------+-------+-------+------------+-----------------+ -; FPGA_LED_1 ; FPGA_CLK ; 6.960 ; 7.231 ; Rise ; FPGA_CLK ; -+------------+------------+-------+-------+------------+-----------------+ ++-------------------------------------------------------------------------+ +; Setup Times ; ++-------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------+------------+-------+-------+------------+-----------------+ +; Address[*] ; FPGA_CLK ; 3.960 ; 3.902 ; Rise ; FPGA_CLK ; +; Address[0] ; FPGA_CLK ; 3.040 ; 2.981 ; Rise ; FPGA_CLK ; +; Address[1] ; FPGA_CLK ; 3.344 ; 3.351 ; Rise ; FPGA_CLK ; +; Address[2] ; FPGA_CLK ; 3.512 ; 3.513 ; Rise ; FPGA_CLK ; +; Address[3] ; FPGA_CLK ; 3.597 ; 3.603 ; Rise ; FPGA_CLK ; +; Address[4] ; FPGA_CLK ; 3.884 ; 3.902 ; Rise ; FPGA_CLK ; +; Address[5] ; FPGA_CLK ; 3.960 ; 3.872 ; Rise ; FPGA_CLK ; +; Address[6] ; FPGA_CLK ; 3.246 ; 3.353 ; Rise ; FPGA_CLK ; +; Address[7] ; FPGA_CLK ; 2.840 ; 2.829 ; Rise ; FPGA_CLK ; +; Data[*] ; FPGA_CLK ; 2.350 ; 2.536 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 2.128 ; 2.251 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 2.350 ; 2.536 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 2.317 ; 2.512 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 2.324 ; 2.513 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 2.143 ; 2.310 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 2.135 ; 2.330 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 2.075 ; 2.264 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 2.120 ; 2.274 ; Rise ; FPGA_CLK ; +; nCE ; FPGA_CLK ; 6.299 ; 5.970 ; Rise ; FPGA_CLK ; +; nOE ; FPGA_CLK ; 5.164 ; 5.023 ; Rise ; FPGA_CLK ; +; nWE ; FPGA_CLK ; 4.823 ; 5.232 ; Rise ; FPGA_CLK ; ++-------------+------------+-------+-------+------------+-----------------+ -+------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------+------------+-------+-------+------------+-----------------+ -; FPGA_LED_1 ; FPGA_CLK ; 6.795 ; 7.059 ; Rise ; FPGA_CLK ; -+------------+------------+-------+-------+------------+-----------------+ ++---------------------------------------------------------------------------+ +; Hold Times ; ++-------------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------+------------+--------+--------+------------+-----------------+ +; Address[*] ; FPGA_CLK ; -1.650 ; -1.774 ; Rise ; FPGA_CLK ; +; Address[0] ; FPGA_CLK ; -1.802 ; -1.900 ; Rise ; FPGA_CLK ; +; Address[1] ; FPGA_CLK ; -2.045 ; -2.196 ; Rise ; FPGA_CLK ; +; Address[2] ; FPGA_CLK ; -2.218 ; -2.386 ; Rise ; FPGA_CLK ; +; Address[3] ; FPGA_CLK ; -2.299 ; -2.434 ; Rise ; FPGA_CLK ; +; Address[4] ; FPGA_CLK ; -1.924 ; -2.131 ; Rise ; FPGA_CLK ; +; Address[5] ; FPGA_CLK ; -2.182 ; -2.322 ; Rise ; FPGA_CLK ; +; Address[6] ; FPGA_CLK ; -1.996 ; -2.165 ; Rise ; FPGA_CLK ; +; Address[7] ; FPGA_CLK ; -1.650 ; -1.774 ; Rise ; FPGA_CLK ; +; Data[*] ; FPGA_CLK ; -1.059 ; -1.193 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; -1.059 ; -1.193 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; -1.183 ; -1.385 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; -1.484 ; -1.629 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; -1.439 ; -1.610 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; -1.132 ; -1.340 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; -1.142 ; -1.382 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; -1.133 ; -1.352 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; -1.440 ; -1.576 ; Rise ; FPGA_CLK ; +; nCE ; FPGA_CLK ; -1.733 ; -1.984 ; Rise ; FPGA_CLK ; +; nOE ; FPGA_CLK ; -1.944 ; -2.061 ; Rise ; FPGA_CLK ; +; nWE ; FPGA_CLK ; -1.723 ; -1.852 ; Rise ; FPGA_CLK ; ++-------------+------------+--------+--------+------------+-----------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data[*] ; FPGA_CLK ; 9.162 ; 8.528 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 6.717 ; 6.373 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 6.992 ; 6.576 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 7.083 ; 6.723 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 7.019 ; 6.593 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 8.019 ; 7.595 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 7.909 ; 7.430 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 9.162 ; 8.528 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 7.215 ; 6.910 ; Rise ; FPGA_CLK ; +; FPGA_LED_1 ; FPGA_CLK ; 7.022 ; 7.427 ; Rise ; FPGA_CLK ; +; FPGA_LED_2 ; FPGA_CLK ; 2.836 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_2 ; FPGA_CLK ; ; 2.656 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_3 ; FPGA_CLK ; 2.836 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; FPGA_LED_3 ; FPGA_CLK ; ; 2.656 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[1] ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data[*] ; FPGA_CLK ; 6.567 ; 6.233 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 6.567 ; 6.233 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 6.832 ; 6.428 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 6.919 ; 6.569 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 6.858 ; 6.444 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 7.817 ; 7.405 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 7.711 ; 7.247 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 9.003 ; 8.375 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 7.045 ; 6.747 ; Rise ; FPGA_CLK ; +; FPGA_LED_1 ; FPGA_CLK ; 6.856 ; 7.249 ; Rise ; FPGA_CLK ; +; FPGA_LED_2 ; FPGA_CLK ; 2.424 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_2 ; FPGA_CLK ; ; 2.247 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_3 ; FPGA_CLK ; 2.424 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; FPGA_LED_3 ; FPGA_CLK ; ; 2.247 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[1] ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Output Enable Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 6.481 ; 6.481 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 6.481 ; 6.481 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 6.835 ; 6.835 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 6.782 ; 6.782 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 6.820 ; 6.820 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 7.396 ; 7.396 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 7.422 ; 7.422 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 7.064 ; 7.064 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 7.206 ; 7.206 ; Rise ; FPGA_CLK ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 6.016 ; 6.016 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 6.016 ; 6.016 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 6.357 ; 6.357 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 6.305 ; 6.305 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 6.342 ; 6.342 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 6.895 ; 6.895 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 6.919 ; 6.919 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 6.575 ; 6.575 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 6.711 ; 6.711 ; Rise ; FPGA_CLK ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Output Disable Times ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 6.160 ; 6.259 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 6.160 ; 6.259 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 6.403 ; 6.502 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 6.370 ; 6.469 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 6.392 ; 6.491 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 7.006 ; 7.105 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 7.026 ; 7.125 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 6.733 ; 6.832 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 6.752 ; 6.851 ; Rise ; FPGA_CLK ; ++-----------+------------+-----------+-----------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 5.803 ; 5.934 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 5.803 ; 5.934 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 6.037 ; 6.168 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 6.005 ; 6.136 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 6.026 ; 6.157 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 6.615 ; 6.746 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 6.634 ; 6.765 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 6.353 ; 6.484 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 6.371 ; 6.502 ; Rise ; FPGA_CLK ; ++-----------+------------+-----------+-----------+------------+-----------------+ --------------------------------------------- @@ -926,7 +1252,7 @@ No synchronizer chains to report. +----------+--------+----------------+ ; Clock ; Slack ; End Point TNS ; +----------+--------+----------------+ -; FPGA_CLK ; -1.072 ; -20.939 ; +; FPGA_CLK ; 37.258 ; 0.000 ; +----------+--------+----------------+ @@ -935,7 +1261,7 @@ No synchronizer chains to report. +----------+-------+----------------+ ; Clock ; Slack ; End Point TNS ; +----------+-------+----------------+ -; FPGA_CLK ; 0.179 ; 0.000 ; +; FPGA_CLK ; 0.186 ; 0.000 ; +----------+-------+----------------+ @@ -956,350 +1282,502 @@ No paths to report. +----------+--------+------------------------------+ ; Clock ; Slack ; End Point TNS ; +----------+--------+------------------------------+ -; FPGA_CLK ; -3.000 ; -35.949 ; +; FPGA_CLK ; 19.206 ; 0.000 ; +----------+--------+------------------------------+ -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Setup: 'FPGA_CLK' ; -+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ; -; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ; -; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ; -; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ; -; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ; -; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ; -; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ; -; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ; -; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ; -; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ; -; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ; -; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ; -; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ; -; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ; -; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ; -; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ; -; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ; -; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ; -; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ; -; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ; -; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ; -; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ; -; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ; -; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ; -; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ; -; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ; -; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ; -; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ; -; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ; -; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ; -; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ; -; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ; -; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ; -; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ; -; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ; -; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ; -; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ; -; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ; -; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ; -; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ; -; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ; -; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ; -; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ; -; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ; -; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ; -; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ; -; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ; -; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ; -; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ; -; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ; -; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ; -; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ; -; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ; -; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ; -; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ; -; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ; -; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ; -; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ; -; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ; -; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ; -; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ; -; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ; -; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ; -; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ; -; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ; -; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ; -; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ; -; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ; -; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ; -; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ; -; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ; -; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ; -; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ; -; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ; -; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ; -; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ; -; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ; -; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ; -; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ; -; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ; -; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ; -; -0.883 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.152 ; 2.022 ; -; -0.883 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.152 ; 2.022 ; -; -0.883 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.152 ; 2.022 ; -; -0.883 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.152 ; 2.022 ; -+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'FPGA_CLK' ; ++--------+----------------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.258 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.695 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.276 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.677 ; +; 37.349 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[6]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.609 ; +; 37.353 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[4]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.605 ; +; 37.354 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[0]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.604 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.358 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.034 ; 2.595 ; +; 37.362 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[7]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.596 ; +; 37.363 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[1]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.595 ; +; 37.363 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[2]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.595 ; +; 37.366 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[3]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.592 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.415 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.536 ; +; 37.445 ; RAM:inst3|memory_rtl_0_bypass[6] ; RAM:inst3|data0[5]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.513 ; +; 37.490 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[6]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.468 ; +; 37.494 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[4]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.464 ; +; 37.495 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[0]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.463 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.448 ; +; 37.503 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[7]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.455 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.447 ; +; 37.504 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[1]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.454 ; +; 37.504 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[2]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.454 ; +; 37.507 ; RAM:inst3|memory_rtl_0_bypass[2] ; RAM:inst3|data0[3]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.451 ; +; 37.524 ; RAM:inst3|memory_rtl_0_bypass[8] ; RAM:inst3|data0[6]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.434 ; +; 37.528 ; RAM:inst3|memory_rtl_0_bypass[8] ; RAM:inst3|data0[4]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.430 ; +; 37.529 ; RAM:inst3|memory_rtl_0_bypass[8] ; RAM:inst3|data0[0]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.429 ; +; 37.537 ; RAM:inst3|memory_rtl_0_bypass[8] ; RAM:inst3|data0[7]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.421 ; +; 37.538 ; RAM:inst3|memory_rtl_0_bypass[8] ; RAM:inst3|data0[1]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.420 ; +; 37.538 ; RAM:inst3|memory_rtl_0_bypass[8] ; RAM:inst3|data0[2]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.420 ; +; 37.541 ; RAM:inst3|memory_rtl_0_bypass[8] ; RAM:inst3|data0[3]~reg0 ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.029 ; 2.417 ; +; 37.586 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.365 ; +; 37.586 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.365 ; +; 37.586 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.365 ; +; 37.586 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.365 ; +; 37.586 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.365 ; +; 37.586 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 40.000 ; -0.036 ; 2.365 ; ++--------+----------------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Hold: 'FPGA_CLK' ; -+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ -; 0.179 ; LedBlink:inst2|ledBuf ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.044 ; 0.307 ; -; 0.248 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.566 ; -; 0.250 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.568 ; -; 0.259 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.577 ; -; 0.262 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.580 ; -; 0.263 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.581 ; -; 0.288 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.417 ; -; 0.289 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.418 ; -; 0.289 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.418 ; -; 0.290 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.419 ; -; 0.290 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.419 ; -; 0.291 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.420 ; -; 0.291 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.420 ; -; 0.292 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.421 ; -; 0.292 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.421 ; -; 0.296 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.417 ; -; 0.296 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.425 ; -; 0.298 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.419 ; -; 0.298 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.427 ; -; 0.299 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.420 ; -; 0.299 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.419 ; -; 0.305 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.425 ; -; 0.308 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.428 ; -; 0.309 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.429 ; -; 0.311 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.629 ; -; 0.314 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.632 ; -; 0.319 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.637 ; -; 0.322 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.640 ; -; 0.325 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.643 ; -; 0.326 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.644 ; -; 0.328 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.646 ; -; 0.329 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.647 ; -; 0.332 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.650 ; -; 0.334 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.652 ; -; 0.337 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.655 ; -; 0.340 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.658 ; -; 0.371 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.492 ; -; 0.371 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.492 ; -; 0.373 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.494 ; -; 0.376 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.497 ; -; 0.377 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.695 ; -; 0.380 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.501 ; -; 0.380 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.698 ; -; 0.382 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.700 ; -; 0.385 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.703 ; -; 0.388 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.706 ; -; 0.388 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.706 ; -; 0.389 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.707 ; -; 0.389 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.707 ; -; 0.391 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.709 ; -; 0.392 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.710 ; -; 0.392 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.710 ; -; 0.395 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.713 ; -; 0.398 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.716 ; -; 0.400 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.718 ; -; 0.401 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.719 ; -; 0.403 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.721 ; -; 0.437 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.566 ; -; 0.439 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.568 ; -; 0.440 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.569 ; -; 0.445 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.763 ; -; 0.445 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.574 ; -; 0.447 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.576 ; -; 0.447 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.576 ; -; 0.448 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.766 ; -; 0.450 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.579 ; -; 0.450 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.579 ; -; 0.450 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.579 ; -; 0.450 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.579 ; -; 0.450 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.579 ; -; 0.451 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.769 ; -; 0.452 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.770 ; -; 0.453 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.582 ; -; 0.454 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.574 ; -; 0.455 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.773 ; -; 0.455 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.773 ; -; 0.457 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.578 ; -; 0.457 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.775 ; -; 0.458 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.578 ; -; 0.458 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.776 ; -; 0.466 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.586 ; -; 0.466 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.784 ; -; 0.467 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.785 ; -; 0.469 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.589 ; -; 0.472 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.790 ; -; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.813 ; -; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.813 ; -; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.813 ; -; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.813 ; -; 0.500 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.629 ; -; 0.502 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.631 ; -; 0.503 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.632 ; -; 0.503 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.632 ; -; 0.505 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.634 ; -; 0.506 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.635 ; -; 0.510 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.631 ; -; 0.511 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.829 ; -; 0.513 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.634 ; -; 0.513 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.642 ; -; 0.514 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.832 ; -+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'FPGA_CLK' ; ++-------+-----------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.186 ; RAM:inst3|stateMM0.Waiting ; RAM:inst3|stateMM0.Waiting ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.307 ; +; 0.187 ; LedBlink:inst2|ledBuf ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.307 ; +; 0.193 ; RAM:inst3|memory_rtl_0_bypass[18] ; RAM:inst3|data0[1]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.313 ; +; 0.194 ; RAM:inst3|memory_rtl_0_bypass[19] ; RAM:inst3|data0[2]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.314 ; +; 0.194 ; RAM:inst3|memory_rtl_0_bypass[22] ; RAM:inst3|data0[5]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.314 ; +; 0.196 ; RAM:inst3|memory_rtl_0_bypass[24] ; RAM:inst3|data0[7]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.316 ; +; 0.206 ; RAM:inst3|addr[6] ; RAM:inst3|memory_rtl_0_bypass[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.326 ; +; 0.253 ; RAM:inst3|memory_rtl_0_bypass[20] ; RAM:inst3|data0[3]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.373 ; +; 0.253 ; RAM:inst3|memory_rtl_0_bypass[21] ; RAM:inst3|data0[4]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.373 ; +; 0.278 ; RAM:inst3|ce0Prev ; RAM:inst3|stateMM0.Reading ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.399 ; +; 0.278 ; RAM:inst3|ce0Prev ; RAM:inst3|stateMM0.Writing ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.399 ; +; 0.280 ; RAM:inst3|addr[7] ; RAM:inst3|memory_rtl_0_bypass[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.400 ; +; 0.294 ; RAM:inst3|memory_rtl_0_bypass[23] ; RAM:inst3|data0[6]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.414 ; +; 0.296 ; RAM:inst3|memory_rtl_0_bypass[17] ; RAM:inst3|data0[0]~reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.416 ; +; 0.297 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.417 ; +; 0.297 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.417 ; +; 0.298 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.418 ; +; 0.298 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.418 ; +; 0.299 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.419 ; +; 0.300 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.420 ; +; 0.301 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.421 ; +; 0.305 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.425 ; +; 0.306 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.426 ; +; 0.307 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.427 ; +; 0.309 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.429 ; +; 0.311 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.431 ; +; 0.311 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.431 ; +; 0.312 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.432 ; +; 0.314 ; RAM:inst3|stateMM0.Waiting ; RAM:inst3|stateMM0.Reading ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.435 ; +; 0.315 ; RAM:inst3|stateMM0.Waiting ; RAM:inst3|stateMM0.Writing ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.436 ; +; 0.329 ; RAM:inst3|ce0Prev ; RAM:inst3|stateMM0.Waiting ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.450 ; +; 0.337 ; RAM:inst3|addr[5] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.229 ; 0.670 ; +; 0.369 ; RAM:inst3|addr[4] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.229 ; 0.702 ; +; 0.408 ; RAM:inst3|addr[2] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.229 ; 0.741 ; +; 0.437 ; RAM:inst3|addr[7] ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.229 ; 0.770 ; +; 0.446 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.566 ; +; 0.447 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.567 ; +; 0.447 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.567 ; +; 0.447 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.567 ; +; 0.448 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.568 ; +; 0.448 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.568 ; +; 0.448 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.568 ; +; 0.448 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.034 ; 0.566 ; +; 0.448 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.568 ; +; 0.454 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.574 ; +; 0.456 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.576 ; +; 0.457 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.577 ; +; 0.457 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.577 ; +; 0.457 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.577 ; +; 0.457 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.577 ; +; 0.458 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.578 ; +; 0.458 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.578 ; +; 0.458 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.578 ; +; 0.459 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.579 ; +; 0.459 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.579 ; +; 0.460 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.580 ; +; 0.460 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.580 ; +; 0.460 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.580 ; +; 0.461 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.581 ; +; 0.462 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.582 ; +; 0.462 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.034 ; 0.580 ; +; 0.464 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.584 ; +; 0.465 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.585 ; +; 0.467 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.587 ; +; 0.468 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.588 ; +; 0.469 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.589 ; +; 0.470 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.590 ; +; 0.472 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.592 ; +; 0.473 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.593 ; +; 0.507 ; RAM:inst3|oe0Prev ; RAM:inst3|stateMM0.Waiting ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.628 ; +; 0.509 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.629 ; +; 0.510 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.630 ; +; 0.510 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.630 ; +; 0.510 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.630 ; +; 0.511 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.631 ; +; 0.511 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.631 ; +; 0.511 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.631 ; +; 0.511 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.034 ; 0.629 ; +; 0.511 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.631 ; +; 0.513 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.633 ; +; 0.513 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.633 ; +; 0.513 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.633 ; +; 0.514 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.634 ; +; 0.514 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.634 ; +; 0.514 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.034 ; 0.632 ; +; 0.514 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.034 ; 0.632 ; +; 0.514 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.634 ; +; 0.517 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.637 ; +; 0.520 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.640 ; +; 0.521 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.641 ; ++-------+-----------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -+--------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK' ; -+--------+--------------+----------------+------------------+----------+------------+--------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+----------+------------+--------------------------------+ -; -3.000 ; 1.000 ; 4.000 ; Port Rate ; FPGA_CLK ; Rise ; FPGA_CLK ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; -; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; -; -0.261 ; -0.077 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; -; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; -; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; -; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ; -; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ; -; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ; -; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ; -; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ; -; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ; -; -0.259 ; -0.075 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; -; -0.259 ; -0.075 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; -; -0.259 ; -0.075 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; -; -0.259 ; -0.075 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; -; -0.232 ; -0.048 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; -; -0.232 ; -0.048 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; -; -0.232 ; -0.048 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; -; -0.232 ; -0.048 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; -; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; -; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; -; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; -; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; -; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; -; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; -; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; -; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; -; -0.081 ; -0.081 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|ledBuf|clk ; -; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[12]|clk ; -; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[13]|clk ; -; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[14]|clk ; -; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[19]|clk ; -; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[20]|clk ; -; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[21]|clk ; -; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[22]|clk ; -; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[23]|clk ; -; -0.079 ; -0.079 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[10]|clk ; -; -0.079 ; -0.079 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[11]|clk ; -; -0.079 ; -0.079 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[3]|clk ; -; -0.079 ; -0.079 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[6]|clk ; -; -0.053 ; -0.053 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~input|o ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[0]|clk ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[15]|clk ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[16]|clk ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[17]|clk ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[18]|clk ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[1]|clk ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[2]|clk ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[4]|clk ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[5]|clk ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[7]|clk ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[8]|clk ; -; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[9]|clk ; -; -0.041 ; -0.041 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|inclk[0] ; -; -0.041 ; -0.041 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|outclk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~input|i ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~input|i ; -; 0.829 ; 1.045 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; -; 0.829 ; 1.045 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; -; 0.829 ; 1.045 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; -; 0.829 ; 1.045 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; -; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; -; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; -; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; -; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; -; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; -; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; -; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; -; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; -; 0.857 ; 1.073 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; -; 0.857 ; 1.073 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; -; 0.857 ; 1.073 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; -; 0.857 ; 1.073 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; -; 0.857 ; 1.073 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; -; 0.858 ; 1.074 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; -; 0.858 ; 1.074 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; -+--------+--------------+----------------+------------------+----------+------------+--------------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK' ; ++--------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------+ +; 19.206 ; 19.436 ; 0.230 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 19.206 ; 19.436 ; 0.230 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_we_reg ; +; 19.207 ; 19.437 ; 0.230 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 19.208 ; 19.438 ; 0.230 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[0] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[1] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[2] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[3] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[4] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[5] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[6] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|addr[7] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[13] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[14] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[15] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[16] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[2] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[4] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[6] ; +; 19.270 ; 19.454 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[8] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|ce0Prev ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[0]~en ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[0]~reg0 ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[1]~en ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[1]~reg0 ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[2]~en ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[2]~reg0 ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[3]~en ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[3]~reg0 ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[4]~en ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[4]~reg0 ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[5]~en ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[5]~reg0 ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[6]~en ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[6]~reg0 ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[7]~en ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|data0[7]~reg0 ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[0] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[10] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[11] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[12] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[17] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[18] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[19] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[1] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[20] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[21] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[22] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[23] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[24] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[3] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[5] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[7] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|memory_rtl_0_bypass[9] ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|oe0Prev ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|stateMM0.Reading ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|stateMM0.Waiting ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|stateMM0.Writing ; +; 19.271 ; 19.455 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; RAM:inst3|we0Prev ; +; 19.410 ; 19.410 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; 19.410 ; 19.410 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; 19.410 ; 19.410 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst|altpll_component|auto_generated|pll1|observablevcoout ; +; 19.447 ; 19.447 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~input|o ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|ledBuf|clk ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst3|ce0Prev|clk ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst3|data0[0]~en|clk ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst3|data0[1]~en|clk ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst3|data0[2]~en|clk ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst3|data0[3]~en|clk ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst3|data0[4]~en|clk ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst3|data0[5]~en|clk ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst3|data0[6]~en|clk ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst3|data0[7]~en|clk ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst3|memory_rtl_0_bypass[0]|clk ; +; 19.449 ; 19.449 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst3|memory_rtl_0_bypass[1]|clk ; ++--------+--------------+----------------+-----------------+----------+------------+--------------------------------------------------------------------------------------------------+ -+------------------------------------------------------------------------+ -; Clock to Output Times ; -+------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------+------------+-------+-------+------------+-----------------+ -; FPGA_LED_1 ; FPGA_CLK ; 3.617 ; 3.589 ; Rise ; FPGA_CLK ; -+------------+------------+-------+-------+------------+-----------------+ ++-------------------------------------------------------------------------+ +; Setup Times ; ++-------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------+------------+-------+-------+------------+-----------------+ +; Address[*] ; FPGA_CLK ; 1.870 ; 2.790 ; Rise ; FPGA_CLK ; +; Address[0] ; FPGA_CLK ; 1.406 ; 2.280 ; Rise ; FPGA_CLK ; +; Address[1] ; FPGA_CLK ; 1.608 ; 2.521 ; Rise ; FPGA_CLK ; +; Address[2] ; FPGA_CLK ; 1.670 ; 2.595 ; Rise ; FPGA_CLK ; +; Address[3] ; FPGA_CLK ; 1.725 ; 2.665 ; Rise ; FPGA_CLK ; +; Address[4] ; FPGA_CLK ; 1.852 ; 2.772 ; Rise ; FPGA_CLK ; +; Address[5] ; FPGA_CLK ; 1.870 ; 2.790 ; Rise ; FPGA_CLK ; +; Address[6] ; FPGA_CLK ; 1.572 ; 2.448 ; Rise ; FPGA_CLK ; +; Address[7] ; FPGA_CLK ; 1.347 ; 2.217 ; Rise ; FPGA_CLK ; +; Data[*] ; FPGA_CLK ; 1.188 ; 2.010 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 1.055 ; 1.824 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 1.188 ; 2.010 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 1.172 ; 1.992 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 1.169 ; 1.978 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 1.110 ; 1.938 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 1.137 ; 1.962 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 1.087 ; 1.899 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 1.097 ; 1.912 ; Rise ; FPGA_CLK ; +; nCE ; FPGA_CLK ; 2.918 ; 3.911 ; Rise ; FPGA_CLK ; +; nOE ; FPGA_CLK ; 2.320 ; 3.258 ; Rise ; FPGA_CLK ; +; nWE ; FPGA_CLK ; 2.406 ; 3.114 ; Rise ; FPGA_CLK ; ++-------------+------------+-------+-------+------------+-----------------+ -+------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------+------------+-------+-------+------------+-----------------+ -; FPGA_LED_1 ; FPGA_CLK ; 3.532 ; 3.507 ; Rise ; FPGA_CLK ; -+------------+------------+-------+-------+------------+-----------------+ ++---------------------------------------------------------------------------+ +; Hold Times ; ++-------------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------+------------+--------+--------+------------+-----------------+ +; Address[*] ; FPGA_CLK ; -0.844 ; -1.640 ; Rise ; FPGA_CLK ; +; Address[0] ; FPGA_CLK ; -0.898 ; -1.692 ; Rise ; FPGA_CLK ; +; Address[1] ; FPGA_CLK ; -1.064 ; -1.890 ; Rise ; FPGA_CLK ; +; Address[2] ; FPGA_CLK ; -1.138 ; -1.979 ; Rise ; FPGA_CLK ; +; Address[3] ; FPGA_CLK ; -1.179 ; -2.027 ; Rise ; FPGA_CLK ; +; Address[4] ; FPGA_CLK ; -1.018 ; -1.859 ; Rise ; FPGA_CLK ; +; Address[5] ; FPGA_CLK ; -1.118 ; -1.954 ; Rise ; FPGA_CLK ; +; Address[6] ; FPGA_CLK ; -1.040 ; -1.852 ; Rise ; FPGA_CLK ; +; Address[7] ; FPGA_CLK ; -0.844 ; -1.640 ; Rise ; FPGA_CLK ; +; Data[*] ; FPGA_CLK ; -0.548 ; -1.342 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; -0.548 ; -1.342 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; -0.644 ; -1.456 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; -0.761 ; -1.594 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; -0.751 ; -1.571 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; -0.614 ; -1.429 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; -0.652 ; -1.468 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; -0.620 ; -1.417 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; -0.751 ; -1.567 ; Rise ; FPGA_CLK ; +; nCE ; FPGA_CLK ; -0.933 ; -1.757 ; Rise ; FPGA_CLK ; +; nOE ; FPGA_CLK ; -0.970 ; -1.777 ; Rise ; FPGA_CLK ; +; nWE ; FPGA_CLK ; -0.868 ; -1.640 ; Rise ; FPGA_CLK ; ++-------------+------------+--------+--------+------------+-----------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data[*] ; FPGA_CLK ; 5.018 ; 4.837 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 3.351 ; 3.367 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 3.472 ; 3.491 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 3.527 ; 3.561 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 3.493 ; 3.513 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 3.971 ; 4.093 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 3.867 ; 3.960 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 5.018 ; 4.837 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 3.616 ; 3.680 ; Rise ; FPGA_CLK ; +; FPGA_LED_1 ; FPGA_CLK ; 3.740 ; 3.668 ; Rise ; FPGA_CLK ; +; FPGA_LED_2 ; FPGA_CLK ; 1.381 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_2 ; FPGA_CLK ; ; 1.342 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_3 ; FPGA_CLK ; 1.380 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; FPGA_LED_3 ; FPGA_CLK ; ; 1.342 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[1] ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data[*] ; FPGA_CLK ; 3.279 ; 3.292 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 3.279 ; 3.292 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 3.395 ; 3.411 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 3.448 ; 3.479 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 3.415 ; 3.432 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 3.873 ; 3.989 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 3.774 ; 3.862 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 4.940 ; 4.754 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 3.533 ; 3.593 ; Rise ; FPGA_CLK ; +; FPGA_LED_1 ; FPGA_CLK ; 3.649 ; 3.582 ; Rise ; FPGA_CLK ; +; FPGA_LED_2 ; FPGA_CLK ; 1.151 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_2 ; FPGA_CLK ; ; 1.111 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_3 ; FPGA_CLK ; 1.150 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; FPGA_LED_3 ; FPGA_CLK ; ; 1.111 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[1] ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ + + ++-----------------------------------------------------------------------+ +; Output Enable Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 4.112 ; 4.093 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 4.112 ; 4.093 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 4.253 ; 4.234 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 4.221 ; 4.202 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 4.244 ; 4.225 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 4.524 ; 4.505 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 4.531 ; 4.512 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 4.376 ; 4.357 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 4.420 ; 4.401 ; Rise ; FPGA_CLK ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-----------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 3.172 ; 3.172 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 3.172 ; 3.172 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 3.307 ; 3.307 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 3.277 ; 3.277 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 3.299 ; 3.299 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 3.567 ; 3.567 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 3.574 ; 3.574 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 3.424 ; 3.424 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 3.467 ; 3.467 ; Rise ; FPGA_CLK ; ++-----------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Output Disable Times ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 4.168 ; 4.168 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 4.168 ; 4.168 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 4.326 ; 4.326 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 4.298 ; 4.298 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 4.320 ; 4.320 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 4.666 ; 4.666 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 4.664 ; 4.664 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 4.513 ; 4.513 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 4.530 ; 4.530 ; Rise ; FPGA_CLK ; ++-----------+------------+-----------+-----------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++-----------+------------+-----------+-----------+------------+-----------------+ +; Data[*] ; FPGA_CLK ; 3.226 ; 3.358 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 3.226 ; 3.358 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 3.378 ; 3.510 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 3.351 ; 3.483 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 3.372 ; 3.504 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 3.703 ; 3.835 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 3.702 ; 3.834 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 3.556 ; 3.688 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 3.573 ; 3.705 ; Rise ; FPGA_CLK ; ++-----------+------------+-----------+-----------+------------+-----------------+ --------------------------------------------- @@ -1308,34 +1786,118 @@ No paths to report. No synchronizer chains to report. -+-------------------------------------------------------------------------------+ -; Multicorner Timing Analysis Summary ; -+------------------+---------+-------+----------+---------+---------------------+ -; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; -+------------------+---------+-------+----------+---------+---------------------+ -; Worst-case Slack ; -3.954 ; 0.179 ; N/A ; N/A ; -3.000 ; -; FPGA_CLK ; -3.954 ; 0.179 ; N/A ; N/A ; -3.000 ; -; Design-wide TNS ; -84.79 ; 0.0 ; 0.0 ; 0.0 ; -40.175 ; -; FPGA_CLK ; -84.790 ; 0.000 ; N/A ; N/A ; -40.175 ; -+------------------+---------+-------+----------+---------+---------------------+ ++------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+--------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+--------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 33.637 ; 0.186 ; N/A ; N/A ; 19.206 ; +; FPGA_CLK ; 33.637 ; 0.186 ; N/A ; N/A ; 19.206 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; FPGA_CLK ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ++------------------+--------+-------+----------+---------+---------------------+ -+------------------------------------------------------------------------+ -; Clock to Output Times ; -+------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------+------------+-------+-------+------------+-----------------+ -; FPGA_LED_1 ; FPGA_CLK ; 7.359 ; 7.560 ; Rise ; FPGA_CLK ; -+------------+------------+-------+-------+------------+-----------------+ ++-------------------------------------------------------------------------+ +; Setup Times ; ++-------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------+------------+-------+-------+------------+-----------------+ +; Address[*] ; FPGA_CLK ; 4.276 ; 4.467 ; Rise ; FPGA_CLK ; +; Address[0] ; FPGA_CLK ; 3.265 ; 3.408 ; Rise ; FPGA_CLK ; +; Address[1] ; FPGA_CLK ; 3.595 ; 3.838 ; Rise ; FPGA_CLK ; +; Address[2] ; FPGA_CLK ; 3.758 ; 4.009 ; Rise ; FPGA_CLK ; +; Address[3] ; FPGA_CLK ; 3.867 ; 4.116 ; Rise ; FPGA_CLK ; +; Address[4] ; FPGA_CLK ; 4.197 ; 4.467 ; Rise ; FPGA_CLK ; +; Address[5] ; FPGA_CLK ; 4.276 ; 4.446 ; Rise ; FPGA_CLK ; +; Address[6] ; FPGA_CLK ; 3.546 ; 3.843 ; Rise ; FPGA_CLK ; +; Address[7] ; FPGA_CLK ; 3.041 ; 3.255 ; Rise ; FPGA_CLK ; +; Data[*] ; FPGA_CLK ; 2.611 ; 2.949 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 2.367 ; 2.631 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 2.611 ; 2.949 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 2.576 ; 2.925 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 2.580 ; 2.915 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 2.384 ; 2.721 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 2.368 ; 2.710 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 2.314 ; 2.657 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 2.351 ; 2.677 ; Rise ; FPGA_CLK ; +; nCE ; FPGA_CLK ; 6.739 ; 6.730 ; Rise ; FPGA_CLK ; +; nOE ; FPGA_CLK ; 5.549 ; 5.716 ; Rise ; FPGA_CLK ; +; nWE ; FPGA_CLK ; 5.354 ; 5.775 ; Rise ; FPGA_CLK ; ++-------------+------------+-------+-------+------------+-----------------+ -+------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+------------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+------------+------------+-------+-------+------------+-----------------+ -; FPGA_LED_1 ; FPGA_CLK ; 3.532 ; 3.507 ; Rise ; FPGA_CLK ; -+------------+------------+-------+-------+------------+-----------------+ ++---------------------------------------------------------------------------+ +; Hold Times ; ++-------------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-------------+------------+--------+--------+------------+-----------------+ +; Address[*] ; FPGA_CLK ; -0.844 ; -1.640 ; Rise ; FPGA_CLK ; +; Address[0] ; FPGA_CLK ; -0.898 ; -1.692 ; Rise ; FPGA_CLK ; +; Address[1] ; FPGA_CLK ; -1.064 ; -1.890 ; Rise ; FPGA_CLK ; +; Address[2] ; FPGA_CLK ; -1.138 ; -1.979 ; Rise ; FPGA_CLK ; +; Address[3] ; FPGA_CLK ; -1.179 ; -2.027 ; Rise ; FPGA_CLK ; +; Address[4] ; FPGA_CLK ; -1.018 ; -1.859 ; Rise ; FPGA_CLK ; +; Address[5] ; FPGA_CLK ; -1.118 ; -1.954 ; Rise ; FPGA_CLK ; +; Address[6] ; FPGA_CLK ; -1.040 ; -1.852 ; Rise ; FPGA_CLK ; +; Address[7] ; FPGA_CLK ; -0.844 ; -1.640 ; Rise ; FPGA_CLK ; +; Data[*] ; FPGA_CLK ; -0.548 ; -1.193 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; -0.548 ; -1.193 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; -0.644 ; -1.385 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; -0.761 ; -1.594 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; -0.751 ; -1.571 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; -0.614 ; -1.340 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; -0.652 ; -1.382 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; -0.620 ; -1.352 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; -0.751 ; -1.567 ; Rise ; FPGA_CLK ; +; nCE ; FPGA_CLK ; -0.933 ; -1.757 ; Rise ; FPGA_CLK ; +; nOE ; FPGA_CLK ; -0.970 ; -1.777 ; Rise ; FPGA_CLK ; +; nWE ; FPGA_CLK ; -0.868 ; -1.640 ; Rise ; FPGA_CLK ; ++-------------+------------+--------+--------+------------+-----------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data[*] ; FPGA_CLK ; 9.467 ; 8.950 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 7.009 ; 6.766 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 7.283 ; 6.997 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 7.398 ; 7.139 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 7.316 ; 7.015 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 8.372 ; 8.094 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 8.254 ; 7.936 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 9.467 ; 8.950 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 7.543 ; 7.354 ; Rise ; FPGA_CLK ; +; FPGA_LED_1 ; FPGA_CLK ; 7.494 ; 7.753 ; Rise ; FPGA_CLK ; +; FPGA_LED_2 ; FPGA_CLK ; 2.836 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_2 ; FPGA_CLK ; ; 2.656 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_3 ; FPGA_CLK ; 2.836 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; FPGA_LED_3 ; FPGA_CLK ; ; 2.656 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[1] ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +; Data[*] ; FPGA_CLK ; 3.279 ; 3.292 ; Rise ; FPGA_CLK ; +; Data[0] ; FPGA_CLK ; 3.279 ; 3.292 ; Rise ; FPGA_CLK ; +; Data[1] ; FPGA_CLK ; 3.395 ; 3.411 ; Rise ; FPGA_CLK ; +; Data[2] ; FPGA_CLK ; 3.448 ; 3.479 ; Rise ; FPGA_CLK ; +; Data[3] ; FPGA_CLK ; 3.415 ; 3.432 ; Rise ; FPGA_CLK ; +; Data[4] ; FPGA_CLK ; 3.873 ; 3.989 ; Rise ; FPGA_CLK ; +; Data[5] ; FPGA_CLK ; 3.774 ; 3.862 ; Rise ; FPGA_CLK ; +; Data[6] ; FPGA_CLK ; 4.940 ; 4.754 ; Rise ; FPGA_CLK ; +; Data[7] ; FPGA_CLK ; 3.533 ; 3.593 ; Rise ; FPGA_CLK ; +; FPGA_LED_1 ; FPGA_CLK ; 3.649 ; 3.582 ; Rise ; FPGA_CLK ; +; FPGA_LED_2 ; FPGA_CLK ; 1.151 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_2 ; FPGA_CLK ; ; 1.111 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; FPGA_LED_3 ; FPGA_CLK ; 1.150 ; ; Rise ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; FPGA_LED_3 ; FPGA_CLK ; ; 1.111 ; Fall ; inst|altpll_component|auto_generated|pll1|clk[1] ; ++------------+------------+-------+-------+------------+--------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1344,6 +1906,8 @@ No synchronizer chains to report. ; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; FPGA_LED_1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; FPGA_LED_2 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; FPGA_LED_3 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; Data[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; Data[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; Data[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; @@ -1362,17 +1926,6 @@ No synchronizer chains to report. +-------------------------+--------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +-------------------------+--------------+-----------------+-----------------+ -; Address[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; Address[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; Address[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; Address[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; Address[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; Address[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; Address[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; Address[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nOE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nWE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nCE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; Data[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; Data[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; Data[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; @@ -1382,6 +1935,17 @@ No synchronizer chains to report. ; Data[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; Data[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; FPGA_CLK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nCE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nWE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; Address[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; Address[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; Address[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; Address[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; Address[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; Address[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; Address[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; Address[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nOE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; @@ -1394,6 +1958,8 @@ No synchronizer chains to report. ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; FPGA_LED_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.01e-07 V ; 3.11 V ; -0.0671 V ; 0.235 V ; 0.176 V ; 6.85e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 5.01e-07 V ; 3.11 V ; -0.0671 V ; 0.235 V ; 0.176 V ; 6.85e-10 s ; 6.31e-10 s ; Yes ; No ; +; FPGA_LED_2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.01e-07 V ; 3.11 V ; -0.0488 V ; 0.191 V ; 0.217 V ; 1.08e-09 s ; 8.59e-10 s ; No ; No ; 3.08 V ; 5.01e-07 V ; 3.11 V ; -0.0488 V ; 0.191 V ; 0.217 V ; 1.08e-09 s ; 8.59e-10 s ; No ; No ; +; FPGA_LED_3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.01e-07 V ; 3.11 V ; -0.0488 V ; 0.191 V ; 0.217 V ; 1.08e-09 s ; 8.59e-10 s ; No ; No ; 3.08 V ; 5.01e-07 V ; 3.11 V ; -0.0488 V ; 0.191 V ; 0.217 V ; 1.08e-09 s ; 8.59e-10 s ; No ; No ; ; Data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ; ; Data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.47e-07 V ; 3.08 V ; -0.00526 V ; 0.185 V ; 0.249 V ; 5.8e-09 s ; 4.45e-09 s ; Yes ; Yes ; 3.08 V ; 7.47e-07 V ; 3.08 V ; -0.00526 V ; 0.185 V ; 0.249 V ; 5.8e-09 s ; 4.45e-09 s ; Yes ; Yes ; ; Data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ; @@ -1413,6 +1979,8 @@ No synchronizer chains to report. ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; FPGA_LED_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.24e-07 V ; 3.6 V ; -0.129 V ; 0.303 V ; 0.209 V ; 4.54e-10 s ; 4.11e-10 s ; No ; No ; 3.46 V ; 1.24e-07 V ; 3.6 V ; -0.129 V ; 0.303 V ; 0.209 V ; 4.54e-10 s ; 4.11e-10 s ; No ; No ; +; FPGA_LED_2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.24e-07 V ; 3.57 V ; -0.0876 V ; 0.318 V ; 0.176 V ; 6.78e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.24e-07 V ; 3.57 V ; -0.0876 V ; 0.318 V ; 0.176 V ; 6.78e-10 s ; 6.15e-10 s ; No ; No ; +; FPGA_LED_3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.24e-07 V ; 3.57 V ; -0.0876 V ; 0.318 V ; 0.176 V ; 6.78e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.24e-07 V ; 3.57 V ; -0.0876 V ; 0.318 V ; 0.176 V ; 6.78e-10 s ; 6.15e-10 s ; No ; No ; ; Data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ; ; Data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.83e-07 V ; 3.48 V ; -0.0176 V ; 0.357 V ; 0.323 V ; 3.9e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.83e-07 V ; 3.48 V ; -0.0176 V ; 0.357 V ; 0.323 V ; 3.9e-09 s ; 3.06e-09 s ; No ; No ; ; Data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ; @@ -1431,7 +1999,7 @@ No synchronizer chains to report. +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; FPGA_CLK ; FPGA_CLK ; 976 ; 0 ; 0 ; 0 ; +; FPGA_CLK ; FPGA_CLK ; 1342 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1441,7 +2009,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; FPGA_CLK ; FPGA_CLK ; 976 ; 0 ; 0 ; 0 ; +; FPGA_CLK ; FPGA_CLK ; 1342 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1465,10 +2033,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 0 ; 0 ; -; Unconstrained Input Port Paths ; 0 ; 0 ; -; Unconstrained Output Ports ; 1 ; 1 ; -; Unconstrained Output Port Paths ; 1 ; 1 ; +; Unconstrained Input Ports ; 19 ; 19 ; +; Unconstrained Input Port Paths ; 87 ; 87 ; +; Unconstrained Output Ports ; 11 ; 11 ; +; Unconstrained Output Port Paths ; 19 ; 19 ; +---------------------------------+-------+------+ @@ -1478,7 +2046,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version - Info: Processing started: Tue Mar 12 16:24:25 2024 + Info: Processing started: Tue Mar 12 17:46:53 2024 Info: Command: quartus_sta MainController -c MainController Info: qsta_default_script.tcl version: #1 Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. @@ -1486,73 +2054,71 @@ Info (21077): Core supply voltage is 1.2V Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Critical Warning (332012): Synopsys Design Constraints File file not found: 'MainController.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks" +Info (332110): Deriving PLL clocks + Info (332110): create_clock -period 40.000 -waveform {0.000 20.000} -name FPGA_CLK FPGA_CLK + Info (332110): create_generated_clock -source {inst|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name {inst|altpll_component|auto_generated|pll1|clk[0]} {inst|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {inst|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 8 -duty_cycle 50.00 -name {inst|altpll_component|auto_generated|pll1|clk[1]} {inst|altpll_component|auto_generated|pll1|clk[1]} Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" -Info (332105): Deriving Clocks - Info (332105): create_clock -period 1.000 -name FPGA_CLK FPGA_CLK +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model -Critical Warning (332148): Timing requirements not met - Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -3.954 +Info (332146): Worst-case setup slack is 33.637 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.954 -84.790 FPGA_CLK -Info (332146): Worst-case hold slack is 0.435 + Info (332119): 33.637 0.000 FPGA_CLK +Info (332146): Worst-case hold slack is 0.454 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.435 0.000 FPGA_CLK + Info (332119): 0.454 0.000 FPGA_CLK Info (332140): No Recovery paths to report Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -3.000 +Info (332146): Worst-case minimum pulse width slack is 19.618 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -40.175 FPGA_CLK + Info (332119): 19.618 0.000 FPGA_CLK Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. -Critical Warning (332148): Timing requirements not met - Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -3.662 +Info (332146): Worst-case setup slack is 34.094 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.662 -77.889 FPGA_CLK -Info (332146): Worst-case hold slack is 0.384 + Info (332119): 34.094 0.000 FPGA_CLK +Info (332146): Worst-case hold slack is 0.402 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.384 0.000 FPGA_CLK + Info (332119): 0.402 0.000 FPGA_CLK Info (332140): No Recovery paths to report Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -3.000 +Info (332146): Worst-case minimum pulse width slack is 19.600 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -40.175 FPGA_CLK + Info (332119): 19.600 0.000 FPGA_CLK Info: Analyzing Fast 1200mV 0C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. -Critical Warning (332148): Timing requirements not met - Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.072 +Info (332146): Worst-case setup slack is 37.258 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.072 -20.939 FPGA_CLK -Info (332146): Worst-case hold slack is 0.179 + Info (332119): 37.258 0.000 FPGA_CLK +Info (332146): Worst-case hold slack is 0.186 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.179 0.000 FPGA_CLK + Info (332119): 0.186 0.000 FPGA_CLK Info (332140): No Recovery paths to report Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -3.000 +Info (332146): Worst-case minimum pulse width slack is 19.206 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -35.949 FPGA_CLK + Info (332119): 19.206 0.000 FPGA_CLK Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4700 megabytes - Info: Processing ended: Tue Mar 12 16:24:27 2024 + Info: Processing ended: Tue Mar 12 17:46:55 2024 Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:01 + Info: Total CPU time (on all processors): 00:00:02 diff --git a/MainController/output_files/MainController.sta.summary b/MainController/output_files/MainController.sta.summary index 2d5126c..2226ab8 100644 --- a/MainController/output_files/MainController.sta.summary +++ b/MainController/output_files/MainController.sta.summary @@ -3,39 +3,39 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1200mV 85C Model Setup 'FPGA_CLK' -Slack : -3.954 -TNS : -84.790 +Slack : 33.637 +TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'FPGA_CLK' -Slack : 0.435 +Slack : 0.454 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'FPGA_CLK' -Slack : -3.000 -TNS : -40.175 +Slack : 19.618 +TNS : 0.000 Type : Slow 1200mV 0C Model Setup 'FPGA_CLK' -Slack : -3.662 -TNS : -77.889 +Slack : 34.094 +TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'FPGA_CLK' -Slack : 0.384 +Slack : 0.402 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'FPGA_CLK' -Slack : -3.000 -TNS : -40.175 +Slack : 19.600 +TNS : 0.000 Type : Fast 1200mV 0C Model Setup 'FPGA_CLK' -Slack : -1.072 -TNS : -20.939 +Slack : 37.258 +TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'FPGA_CLK' -Slack : 0.179 +Slack : 0.186 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'FPGA_CLK' -Slack : -3.000 -TNS : -35.949 +Slack : 19.206 +TNS : 0.000 ------------------------------------------------------------ diff --git a/MainController/simulation/modelsim/MainController.vho b/MainController/simulation/modelsim/MainController.vho index d2c6f05..e2557e0 100644 --- a/MainController/simulation/modelsim/MainController.vho +++ b/MainController/simulation/modelsim/MainController.vho @@ -16,7 +16,7 @@ -- PROGRAM "Quartus II 64-Bit" -- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" --- DATE "03/12/2024 16:24:29" +-- DATE "03/12/2024 17:46:57" -- -- Device: Altera EP3C25Q240C8 Package PQFP240 @@ -37,27 +37,20 @@ ENTITY MainController IS PORT ( FPGA_LED_1 : OUT std_logic; FPGA_CLK : IN std_logic; + FPGA_LED_2 : OUT std_logic; + FPGA_LED_3 : OUT std_logic; Data : INOUT std_logic_vector(7 DOWNTO 0); - Address : IN std_logic_vector(7 DOWNTO 0); - nOE : IN std_logic; nWE : IN std_logic; - nCE : IN std_logic + nOE : IN std_logic; + nCE : IN std_logic; + Address : IN std_logic_vector(7 DOWNTO 0) ); END MainController; -- Design Ports Information -- FPGA_LED_1 => Location: PIN_166, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA --- Address[7] => Location: PIN_195, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[6] => Location: PIN_230, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[5] => Location: PIN_235, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[4] => Location: PIN_232, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[3] => Location: PIN_233, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[2] => Location: PIN_234, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[1] => Location: PIN_231, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[0] => Location: PIN_196, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nOE => Location: PIN_217, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nWE => Location: PIN_218, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nCE => Location: PIN_219, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- FPGA_LED_2 => Location: PIN_167, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +-- FPGA_LED_3 => Location: PIN_168, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[7] => Location: PIN_221, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[6] => Location: PIN_223, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[5] => Location: PIN_224, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -67,6 +60,17 @@ END MainController; -- Data[1] => Location: PIN_189, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[0] => Location: PIN_194, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- FPGA_CLK => Location: PIN_31, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nCE => Location: PIN_219, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nWE => Location: PIN_218, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[0] => Location: PIN_196, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[1] => Location: PIN_231, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[2] => Location: PIN_234, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[3] => Location: PIN_233, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[4] => Location: PIN_232, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[5] => Location: PIN_235, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[6] => Location: PIN_230, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[7] => Location: PIN_195, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nOE => Location: PIN_217, I/O Standard: 3.3-V LVTTL, Current Strength: Default ARCHITECTURE structure OF MainController IS @@ -81,42 +85,152 @@ SIGNAL ww_devclrn : std_logic; SIGNAL ww_devpor : std_logic; SIGNAL ww_FPGA_LED_1 : std_logic; SIGNAL ww_FPGA_CLK : std_logic; -SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0); -SIGNAL ww_nOE : std_logic; +SIGNAL ww_FPGA_LED_2 : std_logic; +SIGNAL ww_FPGA_LED_3 : std_logic; SIGNAL ww_nWE : std_logic; +SIGNAL ww_nOE : std_logic; SIGNAL ww_nCE : std_logic; +SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|pll1_INCLK_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|pll1_CLK_bus\ : std_logic_vector(4 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(35 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(35 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); SIGNAL \FPGA_CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); -SIGNAL \Address[7]~input_o\ : std_logic; -SIGNAL \Address[6]~input_o\ : std_logic; -SIGNAL \Address[5]~input_o\ : std_logic; -SIGNAL \Address[4]~input_o\ : std_logic; -SIGNAL \Address[3]~input_o\ : std_logic; -SIGNAL \Address[2]~input_o\ : std_logic; -SIGNAL \Address[1]~input_o\ : std_logic; -SIGNAL \Address[0]~input_o\ : std_logic; -SIGNAL \nOE~input_o\ : std_logic; -SIGNAL \nWE~input_o\ : std_logic; -SIGNAL \nCE~input_o\ : std_logic; -SIGNAL \Data[7]~input_o\ : std_logic; -SIGNAL \Data[6]~input_o\ : std_logic; -SIGNAL \Data[5]~input_o\ : std_logic; -SIGNAL \Data[4]~input_o\ : std_logic; -SIGNAL \Data[3]~input_o\ : std_logic; -SIGNAL \Data[2]~input_o\ : std_logic; -SIGNAL \Data[1]~input_o\ : std_logic; -SIGNAL \Data[0]~input_o\ : std_logic; -SIGNAL \Data[7]~output_o\ : std_logic; -SIGNAL \Data[6]~output_o\ : std_logic; -SIGNAL \Data[5]~output_o\ : std_logic; -SIGNAL \Data[4]~output_o\ : std_logic; -SIGNAL \Data[3]~output_o\ : std_logic; -SIGNAL \Data[2]~output_o\ : std_logic; -SIGNAL \Data[1]~output_o\ : std_logic; -SIGNAL \Data[0]~output_o\ : std_logic; -SIGNAL \FPGA_LED_1~output_o\ : std_logic; SIGNAL \FPGA_CLK~input_o\ : std_logic; SIGNAL \FPGA_CLK~inputclkctrl_outclk\ : std_logic; +SIGNAL \nCE~input_o\ : std_logic; +SIGNAL \Address[5]~input_o\ : std_logic; +SIGNAL \inst3|ce0Prev~q\ : std_logic; +SIGNAL \inst3|addr~5_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[12]~feeder_combout\ : std_logic; +SIGNAL \nWE~input_o\ : std_logic; +SIGNAL \inst3|we0Prev~q\ : std_logic; +SIGNAL \nOE~input_o\ : std_logic; +SIGNAL \inst3|Selector3~3_combout\ : std_logic; +SIGNAL \inst3|Selector3~2_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Writing~q\ : std_logic; +SIGNAL \inst3|memory~48_combout\ : std_logic; +SIGNAL \inst3|oe0Prev~q\ : std_logic; +SIGNAL \inst3|Selector3~0_combout\ : std_logic; +SIGNAL \inst3|Selector3~1_combout\ : std_logic; +SIGNAL \inst3|Selector2~0_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Waiting~q\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[11]~feeder_combout\ : std_logic; +SIGNAL \Address[4]~input_o\ : std_logic; +SIGNAL \inst3|addr~4_combout\ : std_logic; +SIGNAL \inst3|memory~37_combout\ : std_logic; +SIGNAL \Address[2]~input_o\ : std_logic; +SIGNAL \inst3|addr~2_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[6]~feeder_combout\ : std_logic; +SIGNAL \Address[3]~input_o\ : std_logic; +SIGNAL \inst3|addr~3_combout\ : std_logic; +SIGNAL \inst3|memory~35_combout\ : std_logic; +SIGNAL \Address[0]~input_o\ : std_logic; +SIGNAL \inst3|addr~0_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[2]~feeder_combout\ : std_logic; +SIGNAL \Address[1]~input_o\ : std_logic; +SIGNAL \inst3|addr~1_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[4]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~34_combout\ : std_logic; +SIGNAL \inst3|memory~36_combout\ : std_logic; +SIGNAL \Address[7]~input_o\ : std_logic; +SIGNAL \inst3|addr~7_combout\ : std_logic; +SIGNAL \Address[6]~input_o\ : std_logic; +SIGNAL \inst3|addr~6_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[13]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[16]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~38_combout\ : std_logic; +SIGNAL \inst3|memory~39_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Waiting~_wirecell_combout\ : std_logic; +SIGNAL \Data[0]~input_o\ : std_logic; +SIGNAL \Data[1]~input_o\ : std_logic; +SIGNAL \Data[2]~input_o\ : std_logic; +SIGNAL \Data[3]~input_o\ : std_logic; +SIGNAL \Data[4]~input_o\ : std_logic; +SIGNAL \Data[5]~input_o\ : std_logic; +SIGNAL \Data[6]~input_o\ : std_logic; +SIGNAL \Data[7]~input_o\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[24]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~40_combout\ : std_logic; +SIGNAL \inst3|Selector4~0_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Reading~q\ : std_logic; +SIGNAL \inst3|Selector74~0_combout\ : std_logic; +SIGNAL \inst3|data0[7]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[7]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[7]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[23]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a6\ : std_logic; +SIGNAL \inst3|memory~41_combout\ : std_logic; +SIGNAL \inst3|data0[6]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[6]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[6]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[22]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~42_combout\ : std_logic; +SIGNAL \inst3|data0[5]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[5]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[5]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a4\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[21]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~43_combout\ : std_logic; +SIGNAL \inst3|data0[4]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[4]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[4]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \inst3|memory~44_combout\ : std_logic; +SIGNAL \inst3|data0[3]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[3]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[3]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a2\ : std_logic; +SIGNAL \inst3|memory~45_combout\ : std_logic; +SIGNAL \inst3|data0[2]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[2]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[2]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \inst3|memory~46_combout\ : std_logic; +SIGNAL \inst3|data0[1]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[1]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[1]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \inst3|memory~47_combout\ : std_logic; +SIGNAL \inst3|data0[0]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[0]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[0]~en_q\ : std_logic; SIGNAL \inst2|counter[0]~24_combout\ : std_logic; +SIGNAL \inst2|counter[13]~51\ : std_logic; +SIGNAL \inst2|counter[14]~52_combout\ : std_logic; +SIGNAL \inst2|counter[14]~53\ : std_logic; +SIGNAL \inst2|counter[15]~54_combout\ : std_logic; +SIGNAL \inst2|counter[15]~55\ : std_logic; +SIGNAL \inst2|counter[16]~56_combout\ : std_logic; +SIGNAL \inst2|counter[16]~57\ : std_logic; +SIGNAL \inst2|counter[17]~58_combout\ : std_logic; +SIGNAL \inst2|counter[17]~59\ : std_logic; +SIGNAL \inst2|counter[18]~60_combout\ : std_logic; +SIGNAL \inst2|counter[18]~61\ : std_logic; +SIGNAL \inst2|counter[19]~62_combout\ : std_logic; +SIGNAL \inst2|counter[19]~63\ : std_logic; +SIGNAL \inst2|counter[20]~64_combout\ : std_logic; +SIGNAL \inst2|counter[20]~65\ : std_logic; +SIGNAL \inst2|counter[21]~66_combout\ : std_logic; +SIGNAL \inst2|LessThan0~8_combout\ : std_logic; +SIGNAL \inst2|counter[21]~67\ : std_logic; +SIGNAL \inst2|counter[22]~68_combout\ : std_logic; +SIGNAL \inst2|counter[22]~69\ : std_logic; +SIGNAL \inst2|counter[23]~70_combout\ : std_logic; +SIGNAL \inst2|LessThan0~9_combout\ : std_logic; +SIGNAL \inst2|LessThan0~2_combout\ : std_logic; +SIGNAL \inst2|LessThan0~3_combout\ : std_logic; +SIGNAL \inst2|LessThan0~0_combout\ : std_logic; +SIGNAL \inst2|LessThan0~1_combout\ : std_logic; +SIGNAL \inst2|LessThan0~4_combout\ : std_logic; +SIGNAL \inst2|LessThan0~6_combout\ : std_logic; +SIGNAL \inst2|LessThan0~10_combout\ : std_logic; SIGNAL \inst2|counter[0]~25\ : std_logic; SIGNAL \inst2|counter[1]~26_combout\ : std_logic; SIGNAL \inst2|counter[1]~27\ : std_logic; @@ -143,153 +257,69 @@ SIGNAL \inst2|counter[11]~47\ : std_logic; SIGNAL \inst2|counter[12]~48_combout\ : std_logic; SIGNAL \inst2|counter[12]~49\ : std_logic; SIGNAL \inst2|counter[13]~50_combout\ : std_logic; -SIGNAL \inst2|counter[13]~51\ : std_logic; -SIGNAL \inst2|counter[14]~52_combout\ : std_logic; -SIGNAL \inst2|counter[14]~53\ : std_logic; -SIGNAL \inst2|counter[15]~54_combout\ : std_logic; -SIGNAL \inst2|counter[15]~55\ : std_logic; -SIGNAL \inst2|counter[16]~56_combout\ : std_logic; -SIGNAL \inst2|counter[16]~57\ : std_logic; -SIGNAL \inst2|counter[17]~58_combout\ : std_logic; -SIGNAL \inst2|LessThan0~0_combout\ : std_logic; -SIGNAL \inst2|counter[17]~59\ : std_logic; -SIGNAL \inst2|counter[18]~60_combout\ : std_logic; -SIGNAL \inst2|counter[18]~61\ : std_logic; -SIGNAL \inst2|counter[19]~62_combout\ : std_logic; -SIGNAL \inst2|counter[19]~63\ : std_logic; -SIGNAL \inst2|counter[20]~64_combout\ : std_logic; -SIGNAL \inst2|counter[20]~65\ : std_logic; -SIGNAL \inst2|counter[21]~66_combout\ : std_logic; -SIGNAL \inst2|counter[21]~67\ : std_logic; -SIGNAL \inst2|counter[22]~68_combout\ : std_logic; -SIGNAL \inst2|counter[22]~69\ : std_logic; -SIGNAL \inst2|counter[23]~70_combout\ : std_logic; -SIGNAL \inst2|LessThan0~1_combout\ : std_logic; -SIGNAL \inst2|LessThan0~2_combout\ : std_logic; SIGNAL \inst2|LessThan0~5_combout\ : std_logic; -SIGNAL \inst2|LessThan0~3_combout\ : std_logic; -SIGNAL \inst2|LessThan0~4_combout\ : std_logic; -SIGNAL \inst2|LessThan0~6_combout\ : std_logic; SIGNAL \inst2|LessThan0~7_combout\ : std_logic; -SIGNAL \inst2|LessThan0~8_combout\ : std_logic; SIGNAL \inst2|ledBuf~0_combout\ : std_logic; SIGNAL \inst2|ledBuf~q\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_fbout\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\ : std_logic; +SIGNAL \inst3|addr\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0_bypass\ : std_logic_vector(0 TO 24); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk\ : std_logic_vector(4 DOWNTO 0); SIGNAL \inst2|counter\ : std_logic_vector(23 DOWNTO 0); -SIGNAL \inst2|ALT_INV_LessThan0~8_combout\ : std_logic; +SIGNAL \inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\ : std_logic; +SIGNAL \inst3|ALT_INV_stateMM0.Waiting~q\ : std_logic; SIGNAL \inst2|ALT_INV_ledBuf~q\ : std_logic; BEGIN FPGA_LED_1 <= ww_FPGA_LED_1; ww_FPGA_CLK <= FPGA_CLK; -ww_Address <= Address; -ww_nOE <= nOE; +FPGA_LED_2 <= ww_FPGA_LED_2; +FPGA_LED_3 <= ww_FPGA_LED_3; ww_nWE <= nWE; +ww_nOE <= nOE; ww_nCE <= nCE; +ww_Address <= Address; ww_devoe <= devoe; ww_devclrn <= devclrn; ww_devpor <= devpor; +\inst|altpll_component|auto_generated|pll1_INCLK_bus\ <= (gnd & \FPGA_CLK~input_o\); + +\inst|altpll_component|auto_generated|wire_pll1_clk\(0) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(0); +\inst|altpll_component|auto_generated|wire_pll1_clk\(1) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(1); +\inst|altpll_component|auto_generated|wire_pll1_clk\(2) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(2); +\inst|altpll_component|auto_generated|wire_pll1_clk\(3) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(3); +\inst|altpll_component|auto_generated|wire_pll1_clk\(4) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(4); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & \Data[7]~input_o\ +& \Data[6]~input_o\ & \Data[5]~input_o\ & \Data[4]~input_o\ & \Data[3]~input_o\ & \Data[2]~input_o\ & \Data[1]~input_o\ & \Data[0]~input_o\); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\inst3|addr\(7) & \inst3|addr\(6) & \inst3|addr\(5) & \inst3|addr\(4) & \inst3|addr\(3) & \inst3|addr\(2) & \inst3|addr\(1) & \inst3|addr\(0)); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\inst3|addr~7_combout\ & \inst3|addr~6_combout\ & \inst3|addr~5_combout\ & \inst3|addr~4_combout\ & \inst3|addr~3_combout\ & \inst3|addr~2_combout\ & \inst3|addr~1_combout\ & +\inst3|addr~0_combout\); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\inst3|memory_rtl_0|auto_generated|ram_block1a1\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); +\inst3|memory_rtl_0|auto_generated|ram_block1a2\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2); +\inst3|memory_rtl_0|auto_generated|ram_block1a3\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3); +\inst3|memory_rtl_0|auto_generated|ram_block1a4\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4); +\inst3|memory_rtl_0|auto_generated|ram_block1a5\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5); +\inst3|memory_rtl_0|auto_generated|ram_block1a6\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6); +\inst3|memory_rtl_0|auto_generated|ram_block1a7\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7); + +\inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|altpll_component|auto_generated|wire_pll1_clk\(1)); + +\inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|altpll_component|auto_generated|wire_pll1_clk\(0)); + \FPGA_CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \FPGA_CLK~input_o\); -\inst2|ALT_INV_LessThan0~8_combout\ <= NOT \inst2|LessThan0~8_combout\; +\inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\ <= NOT \inst3|stateMM0.Waiting~_wirecell_combout\; +\inst3|ALT_INV_stateMM0.Waiting~q\ <= NOT \inst3|stateMM0.Waiting~q\; \inst2|ALT_INV_ledBuf~q\ <= NOT \inst2|ledBuf~q\; --- Location: IOOBUF_X18_Y34_N2 -\Data[7]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[7]~output_o\); - --- Location: IOOBUF_X18_Y34_N23 -\Data[6]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[6]~output_o\); - --- Location: IOOBUF_X16_Y34_N2 -\Data[5]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[5]~output_o\); - --- Location: IOOBUF_X16_Y34_N16 -\Data[4]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[4]~output_o\); - --- Location: IOOBUF_X45_Y34_N9 -\Data[3]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[3]~output_o\); - --- Location: IOOBUF_X45_Y34_N16 -\Data[2]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[2]~output_o\); - --- Location: IOOBUF_X45_Y34_N23 -\Data[1]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[1]~output_o\); - --- Location: IOOBUF_X40_Y34_N9 -\Data[0]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[0]~output_o\); - -- Location: IOOBUF_X53_Y22_N2 \FPGA_LED_1~output\ : cycloneiii_io_obuf -- pragma translate_off @@ -300,7 +330,135 @@ GENERIC MAP ( PORT MAP ( i => \inst2|ALT_INV_ledBuf~q\, devoe => ww_devoe, - o => \FPGA_LED_1~output_o\); + o => ww_FPGA_LED_1); + +-- Location: IOOBUF_X53_Y23_N23 +\FPGA_LED_2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\, + devoe => ww_devoe, + o => ww_FPGA_LED_2); + +-- Location: IOOBUF_X53_Y23_N16 +\FPGA_LED_3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\, + devoe => ww_devoe, + o => ww_FPGA_LED_3); + +-- Location: IOOBUF_X18_Y34_N2 +\Data[7]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[7]~reg0_q\, + oe => \inst3|data0[7]~en_q\, + devoe => ww_devoe, + o => Data(7)); + +-- Location: IOOBUF_X18_Y34_N23 +\Data[6]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[6]~reg0_q\, + oe => \inst3|data0[6]~en_q\, + devoe => ww_devoe, + o => Data(6)); + +-- Location: IOOBUF_X16_Y34_N2 +\Data[5]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[5]~reg0_q\, + oe => \inst3|data0[5]~en_q\, + devoe => ww_devoe, + o => Data(5)); + +-- Location: IOOBUF_X16_Y34_N16 +\Data[4]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[4]~reg0_q\, + oe => \inst3|data0[4]~en_q\, + devoe => ww_devoe, + o => Data(4)); + +-- Location: IOOBUF_X45_Y34_N9 +\Data[3]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[3]~reg0_q\, + oe => \inst3|data0[3]~en_q\, + devoe => ww_devoe, + o => Data(3)); + +-- Location: IOOBUF_X45_Y34_N16 +\Data[2]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[2]~reg0_q\, + oe => \inst3|data0[2]~en_q\, + devoe => ww_devoe, + o => Data(2)); + +-- Location: IOOBUF_X45_Y34_N23 +\Data[1]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[1]~reg0_q\, + oe => \inst3|data0[1]~en_q\, + devoe => ww_devoe, + o => Data(1)); + +-- Location: IOOBUF_X40_Y34_N9 +\Data[0]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[0]~reg0_q\, + oe => \inst3|data0[0]~en_q\, + devoe => ww_devoe, + o => Data(0)); -- Location: IOIBUF_X0_Y16_N1 \FPGA_CLK~input\ : cycloneiii_io_ibuf @@ -313,7 +471,7 @@ PORT MAP ( i => ww_FPGA_CLK, o => \FPGA_CLK~input_o\); --- Location: CLKCTRL_G4 +-- Location: CLKCTRL_G2 \FPGA_CLK~inputclkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( @@ -326,7 +484,1858 @@ PORT MAP ( devpor => ww_devpor, outclk => \FPGA_CLK~inputclkctrl_outclk\); --- Location: LCCOMB_X51_Y14_N8 +-- Location: IOIBUF_X20_Y34_N15 +\nCE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nCE, + o => \nCE~input_o\); + +-- Location: IOIBUF_X7_Y34_N15 +\Address[5]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(5), + o => \Address[5]~input_o\); + +-- Location: FF_X27_Y29_N31 +\inst3|ce0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nCE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|ce0Prev~q\); + +-- Location: LCCOMB_X34_Y24_N26 +\inst3|addr~5\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~5_combout\ = (!\nCE~input_o\ & (\Address[5]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[5]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~5_combout\); + +-- Location: LCCOMB_X32_Y23_N12 +\inst3|memory_rtl_0_bypass[12]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[12]~feeder_combout\ = \inst3|addr~5_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~5_combout\, + combout => \inst3|memory_rtl_0_bypass[12]~feeder_combout\); + +-- Location: IOIBUF_X20_Y34_N8 +\nWE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nWE, + o => \nWE~input_o\); + +-- Location: FF_X27_Y29_N21 +\inst3|we0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nWE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|we0Prev~q\); + +-- Location: IOIBUF_X20_Y34_N1 +\nOE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nOE, + o => \nOE~input_o\); + +-- Location: LCCOMB_X27_Y29_N14 +\inst3|Selector3~3\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~3_combout\ = (\nOE~input_o\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\ & !\inst3|stateMM0.Waiting~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector3~3_combout\); + +-- Location: LCCOMB_X27_Y29_N30 +\inst3|Selector3~2\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~2_combout\ = (\inst3|stateMM0.Waiting~q\ & (((\inst3|Selector3~1_combout\)))) # (!\inst3|stateMM0.Waiting~q\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011101000010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|stateMM0.Waiting~q\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|Selector3~1_combout\, + combout => \inst3|Selector3~2_combout\); + +-- Location: FF_X27_Y29_N15 +\inst3|stateMM0.Writing\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector3~3_combout\, + ena => \inst3|Selector3~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Writing~q\); + +-- Location: LCCOMB_X27_Y29_N20 +\inst3|memory~48\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~48_combout\ = (!\nWE~input_o\ & (\inst3|we0Prev~q\ & \inst3|stateMM0.Writing~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nWE~input_o\, + datac => \inst3|we0Prev~q\, + datad => \inst3|stateMM0.Writing~q\, + combout => \inst3|memory~48_combout\); + +-- Location: FF_X27_Y29_N25 +\inst3|oe0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nOE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|oe0Prev~q\); + +-- Location: LCCOMB_X27_Y29_N24 +\inst3|Selector3~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~0_combout\ = (\nOE~input_o\ & (!\inst3|oe0Prev~q\ & !\inst3|stateMM0.Writing~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datac => \inst3|oe0Prev~q\, + datad => \inst3|stateMM0.Writing~q\, + combout => \inst3|Selector3~0_combout\); + +-- Location: LCCOMB_X27_Y29_N2 +\inst3|Selector3~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~1_combout\ = (\inst3|memory~48_combout\) # ((\nCE~input_o\) # (\inst3|Selector3~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111101110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory~48_combout\, + datab => \nCE~input_o\, + datad => \inst3|Selector3~0_combout\, + combout => \inst3|Selector3~1_combout\); + +-- Location: LCCOMB_X27_Y29_N8 +\inst3|Selector2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector2~0_combout\ = (\inst3|stateMM0.Waiting~q\ & (((!\inst3|Selector3~1_combout\)))) # (!\inst3|stateMM0.Waiting~q\ & (\inst3|ce0Prev~q\ & (!\nCE~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000001011110010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datac => \inst3|stateMM0.Waiting~q\, + datad => \inst3|Selector3~1_combout\, + combout => \inst3|Selector2~0_combout\); + +-- Location: FF_X27_Y29_N9 +\inst3|stateMM0.Waiting\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Waiting~q\); + +-- Location: FF_X32_Y23_N13 +\inst3|memory_rtl_0_bypass[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[12]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(12)); + +-- Location: FF_X34_Y24_N27 +\inst3|addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~5_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(5)); + +-- Location: LCCOMB_X32_Y23_N2 +\inst3|memory_rtl_0_bypass[11]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[11]~feeder_combout\ = \inst3|addr\(5) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr\(5), + combout => \inst3|memory_rtl_0_bypass[11]~feeder_combout\); + +-- Location: FF_X32_Y23_N3 +\inst3|memory_rtl_0_bypass[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[11]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(11)); + +-- Location: IOIBUF_X14_Y34_N22 +\Address[4]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(4), + o => \Address[4]~input_o\); + +-- Location: LCCOMB_X34_Y24_N0 +\inst3|addr~4\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~4_combout\ = (!\nCE~input_o\ & (\Address[4]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[4]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~4_combout\); + +-- Location: FF_X32_Y23_N7 +\inst3|memory_rtl_0_bypass[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~4_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(10)); + +-- Location: FF_X34_Y24_N1 +\inst3|addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~4_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(4)); + +-- Location: FF_X32_Y23_N1 +\inst3|memory_rtl_0_bypass[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(4), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(9)); + +-- Location: LCCOMB_X32_Y23_N6 +\inst3|memory~37\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~37_combout\ = (\inst3|memory_rtl_0_bypass\(12) & (\inst3|memory_rtl_0_bypass\(11) & (\inst3|memory_rtl_0_bypass\(10) $ (!\inst3|memory_rtl_0_bypass\(9))))) # (!\inst3|memory_rtl_0_bypass\(12) & (!\inst3|memory_rtl_0_bypass\(11) & +-- (\inst3|memory_rtl_0_bypass\(10) $ (!\inst3|memory_rtl_0_bypass\(9))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001000000001001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(12), + datab => \inst3|memory_rtl_0_bypass\(11), + datac => \inst3|memory_rtl_0_bypass\(10), + datad => \inst3|memory_rtl_0_bypass\(9), + combout => \inst3|memory~37_combout\); + +-- Location: IOIBUF_X7_Y34_N8 +\Address[2]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(2), + o => \Address[2]~input_o\); + +-- Location: LCCOMB_X34_Y24_N12 +\inst3|addr~2\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~2_combout\ = (!\nCE~input_o\ & (\Address[2]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[2]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~2_combout\); + +-- Location: LCCOMB_X34_Y24_N14 +\inst3|memory_rtl_0_bypass[6]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[6]~feeder_combout\ = \inst3|addr~2_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~2_combout\, + combout => \inst3|memory_rtl_0_bypass[6]~feeder_combout\); + +-- Location: FF_X34_Y24_N15 +\inst3|memory_rtl_0_bypass[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[6]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(6)); + +-- Location: IOIBUF_X7_Y34_N1 +\Address[3]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(3), + o => \Address[3]~input_o\); + +-- Location: LCCOMB_X34_Y24_N30 +\inst3|addr~3\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~3_combout\ = (\inst3|ce0Prev~q\ & (\Address[3]~input_o\ & !\nCE~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \Address[3]~input_o\, + datad => \nCE~input_o\, + combout => \inst3|addr~3_combout\); + +-- Location: FF_X34_Y24_N31 +\inst3|addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~3_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(3)); + +-- Location: FF_X27_Y29_N1 +\inst3|memory_rtl_0_bypass[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(3), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(7)); + +-- Location: FF_X34_Y24_N13 +\inst3|addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~2_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(2)); + +-- Location: FF_X27_Y29_N23 +\inst3|memory_rtl_0_bypass[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(2), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(5)); + +-- Location: FF_X34_Y24_N5 +\inst3|memory_rtl_0_bypass[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~3_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(8)); + +-- Location: LCCOMB_X27_Y29_N22 +\inst3|memory~35\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~35_combout\ = (\inst3|memory_rtl_0_bypass\(6) & (\inst3|memory_rtl_0_bypass\(5) & (\inst3|memory_rtl_0_bypass\(7) $ (!\inst3|memory_rtl_0_bypass\(8))))) # (!\inst3|memory_rtl_0_bypass\(6) & (!\inst3|memory_rtl_0_bypass\(5) & +-- (\inst3|memory_rtl_0_bypass\(7) $ (!\inst3|memory_rtl_0_bypass\(8))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(6), + datab => \inst3|memory_rtl_0_bypass\(7), + datac => \inst3|memory_rtl_0_bypass\(5), + datad => \inst3|memory_rtl_0_bypass\(8), + combout => \inst3|memory~35_combout\); + +-- Location: IOIBUF_X38_Y34_N15 +\Address[0]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(0), + o => \Address[0]~input_o\); + +-- Location: LCCOMB_X34_Y24_N24 +\inst3|addr~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~0_combout\ = (\inst3|ce0Prev~q\ & (!\nCE~input_o\ & \Address[0]~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datac => \Address[0]~input_o\, + combout => \inst3|addr~0_combout\); + +-- Location: LCCOMB_X34_Y24_N18 +\inst3|memory_rtl_0_bypass[2]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[2]~feeder_combout\ = \inst3|addr~0_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~0_combout\, + combout => \inst3|memory_rtl_0_bypass[2]~feeder_combout\); + +-- Location: FF_X34_Y24_N19 +\inst3|memory_rtl_0_bypass[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[2]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(2)); + +-- Location: IOIBUF_X14_Y34_N15 +\Address[1]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(1), + o => \Address[1]~input_o\); + +-- Location: LCCOMB_X34_Y24_N2 +\inst3|addr~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~1_combout\ = (\Address[1]~input_o\ & (!\nCE~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \Address[1]~input_o\, + datab => \nCE~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~1_combout\); + +-- Location: FF_X34_Y24_N3 +\inst3|addr[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~1_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(1)); + +-- Location: FF_X27_Y29_N29 +\inst3|memory_rtl_0_bypass[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(1), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(3)); + +-- Location: FF_X34_Y24_N25 +\inst3|addr[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~0_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(0)); + +-- Location: FF_X27_Y29_N11 +\inst3|memory_rtl_0_bypass[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(0), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(1)); + +-- Location: LCCOMB_X34_Y24_N16 +\inst3|memory_rtl_0_bypass[4]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[4]~feeder_combout\ = \inst3|addr~1_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~1_combout\, + combout => \inst3|memory_rtl_0_bypass[4]~feeder_combout\); + +-- Location: FF_X34_Y24_N17 +\inst3|memory_rtl_0_bypass[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[4]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(4)); + +-- Location: LCCOMB_X27_Y29_N10 +\inst3|memory~34\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~34_combout\ = (\inst3|memory_rtl_0_bypass\(2) & (\inst3|memory_rtl_0_bypass\(1) & (\inst3|memory_rtl_0_bypass\(3) $ (!\inst3|memory_rtl_0_bypass\(4))))) # (!\inst3|memory_rtl_0_bypass\(2) & (!\inst3|memory_rtl_0_bypass\(1) & +-- (\inst3|memory_rtl_0_bypass\(3) $ (!\inst3|memory_rtl_0_bypass\(4))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(2), + datab => \inst3|memory_rtl_0_bypass\(3), + datac => \inst3|memory_rtl_0_bypass\(1), + datad => \inst3|memory_rtl_0_bypass\(4), + combout => \inst3|memory~34_combout\); + +-- Location: LCCOMB_X27_Y29_N18 +\inst3|memory~36\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~36_combout\ = (\inst3|memory~35_combout\ & \inst3|memory~34_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datac => \inst3|memory~35_combout\, + datad => \inst3|memory~34_combout\, + combout => \inst3|memory~36_combout\); + +-- Location: FF_X27_Y29_N17 +\inst3|memory_rtl_0_bypass[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|memory~48_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(0)); + +-- Location: IOIBUF_X38_Y34_N1 +\Address[7]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(7), + o => \Address[7]~input_o\); + +-- Location: LCCOMB_X34_Y24_N22 +\inst3|addr~7\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~7_combout\ = (\inst3|ce0Prev~q\ & (!\nCE~input_o\ & \Address[7]~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datad => \Address[7]~input_o\, + combout => \inst3|addr~7_combout\); + +-- Location: FF_X34_Y24_N23 +\inst3|addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~7_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(7)); + +-- Location: FF_X34_Y24_N11 +\inst3|memory_rtl_0_bypass[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(7), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(15)); + +-- Location: IOIBUF_X14_Y34_N8 +\Address[6]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(6), + o => \Address[6]~input_o\); + +-- Location: LCCOMB_X34_Y24_N20 +\inst3|addr~6\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~6_combout\ = (\Address[6]~input_o\ & (!\nCE~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \Address[6]~input_o\, + datab => \nCE~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~6_combout\); + +-- Location: FF_X34_Y24_N21 +\inst3|addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~6_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(6)); + +-- Location: LCCOMB_X34_Y24_N8 +\inst3|memory_rtl_0_bypass[13]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[13]~feeder_combout\ = \inst3|addr\(6) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr\(6), + combout => \inst3|memory_rtl_0_bypass[13]~feeder_combout\); + +-- Location: FF_X34_Y24_N9 +\inst3|memory_rtl_0_bypass[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[13]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(13)); + +-- Location: FF_X34_Y24_N7 +\inst3|memory_rtl_0_bypass[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~6_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(14)); + +-- Location: LCCOMB_X34_Y24_N28 +\inst3|memory_rtl_0_bypass[16]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[16]~feeder_combout\ = \inst3|addr~7_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~7_combout\, + combout => \inst3|memory_rtl_0_bypass[16]~feeder_combout\); + +-- Location: FF_X34_Y24_N29 +\inst3|memory_rtl_0_bypass[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[16]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(16)); + +-- Location: LCCOMB_X34_Y24_N6 +\inst3|memory~38\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~38_combout\ = (\inst3|memory_rtl_0_bypass\(15) & (\inst3|memory_rtl_0_bypass\(16) & (\inst3|memory_rtl_0_bypass\(13) $ (!\inst3|memory_rtl_0_bypass\(14))))) # (!\inst3|memory_rtl_0_bypass\(15) & (!\inst3|memory_rtl_0_bypass\(16) & +-- (\inst3|memory_rtl_0_bypass\(13) $ (!\inst3|memory_rtl_0_bypass\(14))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000001001000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(15), + datab => \inst3|memory_rtl_0_bypass\(13), + datac => \inst3|memory_rtl_0_bypass\(14), + datad => \inst3|memory_rtl_0_bypass\(16), + combout => \inst3|memory~38_combout\); + +-- Location: LCCOMB_X27_Y29_N16 +\inst3|memory~39\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~39_combout\ = (\inst3|memory~37_combout\ & (\inst3|memory~36_combout\ & (\inst3|memory_rtl_0_bypass\(0) & \inst3|memory~38_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory~37_combout\, + datab => \inst3|memory~36_combout\, + datac => \inst3|memory_rtl_0_bypass\(0), + datad => \inst3|memory~38_combout\, + combout => \inst3|memory~39_combout\); + +-- Location: LCCOMB_X35_Y33_N24 +\inst3|stateMM0.Waiting~_wirecell\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|stateMM0.Waiting~_wirecell_combout\ = !\inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000011111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|stateMM0.Waiting~_wirecell_combout\); + +-- Location: IOIBUF_X40_Y34_N8 +\Data[0]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(0), + o => \Data[0]~input_o\); + +-- Location: IOIBUF_X45_Y34_N22 +\Data[1]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(1), + o => \Data[1]~input_o\); + +-- Location: IOIBUF_X45_Y34_N15 +\Data[2]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(2), + o => \Data[2]~input_o\); + +-- Location: IOIBUF_X45_Y34_N8 +\Data[3]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(3), + o => \Data[3]~input_o\); + +-- Location: IOIBUF_X16_Y34_N15 +\Data[4]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(4), + o => \Data[4]~input_o\); + +-- Location: IOIBUF_X16_Y34_N1 +\Data[5]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(5), + o => \Data[5]~input_o\); + +-- Location: IOIBUF_X18_Y34_N22 +\Data[6]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(6), + o => \Data[6]~input_o\); + +-- Location: IOIBUF_X18_Y34_N1 +\Data[7]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(7), + o => \Data[7]~input_o\); + +-- Location: M9K_X33_Y29_N0 +\inst3|memory_rtl_0|auto_generated|ram_block1a0\ : cycloneiii_ram_block +-- pragma translate_off +GENERIC MAP ( + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + logical_ram_name => "RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 8, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 36, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 255, + port_a_logical_ram_depth => 256, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_with_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 8, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 36, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 255, + port_b_logical_ram_depth => 256, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_with_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M9K") +-- pragma translate_on +PORT MAP ( + portawe => \inst3|memory~48_combout\, + portbre => VCC, + portbaddrstall => \inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\, + clk0 => \FPGA_CLK~inputclkctrl_outclk\, + portadatain => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LCCOMB_X35_Y29_N24 +\inst3|memory_rtl_0_bypass[24]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[24]~feeder_combout\ = \Data[7]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[7]~input_o\, + combout => \inst3|memory_rtl_0_bypass[24]~feeder_combout\); + +-- Location: FF_X35_Y29_N25 +\inst3|memory_rtl_0_bypass[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[24]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(24)); + +-- Location: LCCOMB_X35_Y29_N0 +\inst3|memory~40\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~40_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(24)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a7\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a7\, + datad => \inst3|memory_rtl_0_bypass\(24), + combout => \inst3|memory~40_combout\); + +-- Location: LCCOMB_X27_Y29_N12 +\inst3|Selector4~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector4~0_combout\ = (!\nOE~input_o\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\ & !\inst3|stateMM0.Waiting~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector4~0_combout\); + +-- Location: FF_X27_Y29_N13 +\inst3|stateMM0.Reading\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector4~0_combout\, + ena => \inst3|Selector3~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Reading~q\); + +-- Location: LCCOMB_X27_Y29_N26 +\inst3|Selector74~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector74~0_combout\ = (\inst3|stateMM0.Reading~q\) # ((!\inst3|stateMM0.Waiting~q\ & ((\nCE~input_o\) # (!\inst3|ce0Prev~q\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010101011101111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|stateMM0.Reading~q\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector74~0_combout\); + +-- Location: FF_X35_Y29_N1 +\inst3|data0[7]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~40_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[7]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N16 +\inst3|data0[7]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[7]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[7]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N17 +\inst3|data0[7]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[7]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[7]~en_q\); + +-- Location: LCCOMB_X35_Y29_N26 +\inst3|memory_rtl_0_bypass[23]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[23]~feeder_combout\ = \Data[6]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[6]~input_o\, + combout => \inst3|memory_rtl_0_bypass[23]~feeder_combout\); + +-- Location: FF_X35_Y29_N27 +\inst3|memory_rtl_0_bypass[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[23]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(23)); + +-- Location: LCCOMB_X35_Y29_N18 +\inst3|memory~41\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~41_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(23))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a6\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011100010111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(23), + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a6\, + combout => \inst3|memory~41_combout\); + +-- Location: FF_X35_Y29_N19 +\inst3|data0[6]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~41_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[6]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N18 +\inst3|data0[6]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[6]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[6]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N19 +\inst3|data0[6]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[6]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[6]~en_q\); + +-- Location: LCCOMB_X35_Y29_N28 +\inst3|memory_rtl_0_bypass[22]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[22]~feeder_combout\ = \Data[5]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[5]~input_o\, + combout => \inst3|memory_rtl_0_bypass[22]~feeder_combout\); + +-- Location: FF_X35_Y29_N29 +\inst3|memory_rtl_0_bypass[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[22]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(22)); + +-- Location: LCCOMB_X35_Y29_N20 +\inst3|memory~42\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~42_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(22)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a5\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101000001010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0|auto_generated|ram_block1a5\, + datac => \inst3|memory~39_combout\, + datad => \inst3|memory_rtl_0_bypass\(22), + combout => \inst3|memory~42_combout\); + +-- Location: FF_X35_Y29_N21 +\inst3|data0[5]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~42_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[5]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N4 +\inst3|data0[5]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[5]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[5]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N5 +\inst3|data0[5]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[5]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[5]~en_q\); + +-- Location: LCCOMB_X35_Y29_N14 +\inst3|memory_rtl_0_bypass[21]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[21]~feeder_combout\ = \Data[4]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[4]~input_o\, + combout => \inst3|memory_rtl_0_bypass[21]~feeder_combout\); + +-- Location: FF_X35_Y29_N15 +\inst3|memory_rtl_0_bypass[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[21]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(21)); + +-- Location: LCCOMB_X35_Y29_N30 +\inst3|memory~43\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~43_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(21)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a4\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110001011100010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0|auto_generated|ram_block1a4\, + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0_bypass\(21), + combout => \inst3|memory~43_combout\); + +-- Location: FF_X35_Y29_N31 +\inst3|data0[4]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~43_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[4]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N6 +\inst3|data0[4]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[4]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[4]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N7 +\inst3|data0[4]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[4]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[4]~en_q\); + +-- Location: FF_X35_Y29_N9 +\inst3|memory_rtl_0_bypass[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[3]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(20)); + +-- Location: LCCOMB_X35_Y29_N16 +\inst3|memory~44\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~44_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(20))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a3\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111001111000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0_bypass\(20), + datad => \inst3|memory_rtl_0|auto_generated|ram_block1a3\, + combout => \inst3|memory~44_combout\); + +-- Location: FF_X35_Y29_N17 +\inst3|data0[3]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~44_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[3]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N8 +\inst3|data0[3]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[3]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[3]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N9 +\inst3|data0[3]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[3]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[3]~en_q\); + +-- Location: FF_X35_Y29_N11 +\inst3|memory_rtl_0_bypass[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[2]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(19)); + +-- Location: LCCOMB_X35_Y29_N2 +\inst3|memory~45\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~45_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(19)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a2\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a2\, + datad => \inst3|memory_rtl_0_bypass\(19), + combout => \inst3|memory~45_combout\); + +-- Location: FF_X35_Y29_N3 +\inst3|data0[2]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~45_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[2]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N2 +\inst3|data0[2]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[2]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[2]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N3 +\inst3|data0[2]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[2]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[2]~en_q\); + +-- Location: FF_X35_Y29_N13 +\inst3|memory_rtl_0_bypass[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[1]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(18)); + +-- Location: LCCOMB_X35_Y29_N4 +\inst3|memory~46\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~46_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(18)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a1\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a1\, + datad => \inst3|memory_rtl_0_bypass\(18), + combout => \inst3|memory~46_combout\); + +-- Location: FF_X35_Y29_N5 +\inst3|data0[1]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~46_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[1]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N20 +\inst3|data0[1]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[1]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[1]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N21 +\inst3|data0[1]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[1]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[1]~en_q\); + +-- Location: FF_X35_Y29_N23 +\inst3|memory_rtl_0_bypass[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[0]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(17)); + +-- Location: LCCOMB_X35_Y29_N6 +\inst3|memory~47\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~47_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(17))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011100010111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(17), + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\, + combout => \inst3|memory~47_combout\); + +-- Location: FF_X35_Y29_N7 +\inst3|data0[0]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~47_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[0]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N22 +\inst3|data0[0]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[0]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[0]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N23 +\inst3|data0[0]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[0]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[0]~en_q\); + +-- Location: LCCOMB_X26_Y29_N8 \inst2|counter[0]~24\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[0]~24_combout\ = \inst2|counter\(0) $ (VCC) @@ -334,427 +2343,16 @@ PORT MAP ( -- pragma translate_off GENERIC MAP ( - lut_mask => "0101010110101010", + lut_mask => "0011001111001100", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(0), + datab => \inst2|counter\(0), datad => VCC, combout => \inst2|counter[0]~24_combout\, cout => \inst2|counter[0]~25\); --- Location: FF_X51_Y14_N9 -\inst2|counter[0]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[0]~24_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(0)); - --- Location: LCCOMB_X51_Y14_N10 -\inst2|counter[1]~26\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND))) --- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(1), - datad => VCC, - cin => \inst2|counter[0]~25\, - combout => \inst2|counter[1]~26_combout\, - cout => \inst2|counter[1]~27\); - --- Location: FF_X51_Y14_N11 -\inst2|counter[1]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[1]~26_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(1)); - --- Location: LCCOMB_X51_Y14_N12 -\inst2|counter[2]~28\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC)) --- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(2), - datad => VCC, - cin => \inst2|counter[1]~27\, - combout => \inst2|counter[2]~28_combout\, - cout => \inst2|counter[2]~29\); - --- Location: FF_X51_Y14_N13 -\inst2|counter[2]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[2]~28_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(2)); - --- Location: LCCOMB_X51_Y14_N14 -\inst2|counter[3]~30\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND))) --- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(3), - datad => VCC, - cin => \inst2|counter[2]~29\, - combout => \inst2|counter[3]~30_combout\, - cout => \inst2|counter[3]~31\); - --- Location: FF_X51_Y14_N15 -\inst2|counter[3]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[3]~30_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(3)); - --- Location: LCCOMB_X51_Y14_N16 -\inst2|counter[4]~32\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC)) --- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1010010100001010", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(4), - datad => VCC, - cin => \inst2|counter[3]~31\, - combout => \inst2|counter[4]~32_combout\, - cout => \inst2|counter[4]~33\); - --- Location: FF_X51_Y14_N17 -\inst2|counter[4]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[4]~32_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(4)); - --- Location: LCCOMB_X51_Y14_N18 -\inst2|counter[5]~34\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND))) --- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(5), - datad => VCC, - cin => \inst2|counter[4]~33\, - combout => \inst2|counter[5]~34_combout\, - cout => \inst2|counter[5]~35\); - --- Location: FF_X51_Y14_N19 -\inst2|counter[5]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[5]~34_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(5)); - --- Location: LCCOMB_X51_Y14_N20 -\inst2|counter[6]~36\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC)) --- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(6), - datad => VCC, - cin => \inst2|counter[5]~35\, - combout => \inst2|counter[6]~36_combout\, - cout => \inst2|counter[6]~37\); - --- Location: FF_X51_Y14_N21 -\inst2|counter[6]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[6]~36_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(6)); - --- Location: LCCOMB_X51_Y14_N22 -\inst2|counter[7]~38\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND))) --- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(7), - datad => VCC, - cin => \inst2|counter[6]~37\, - combout => \inst2|counter[7]~38_combout\, - cout => \inst2|counter[7]~39\); - --- Location: FF_X51_Y14_N23 -\inst2|counter[7]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[7]~38_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(7)); - --- Location: LCCOMB_X51_Y14_N24 -\inst2|counter[8]~40\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC)) --- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(8), - datad => VCC, - cin => \inst2|counter[7]~39\, - combout => \inst2|counter[8]~40_combout\, - cout => \inst2|counter[8]~41\); - --- Location: FF_X51_Y14_N25 -\inst2|counter[8]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[8]~40_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(8)); - --- Location: LCCOMB_X51_Y14_N26 -\inst2|counter[9]~42\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND))) --- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0101101001011111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(9), - datad => VCC, - cin => \inst2|counter[8]~41\, - combout => \inst2|counter[9]~42_combout\, - cout => \inst2|counter[9]~43\); - --- Location: FF_X51_Y14_N27 -\inst2|counter[9]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[9]~42_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(9)); - --- Location: LCCOMB_X51_Y14_N28 -\inst2|counter[10]~44\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC)) --- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(10), - datad => VCC, - cin => \inst2|counter[9]~43\, - combout => \inst2|counter[10]~44_combout\, - cout => \inst2|counter[10]~45\); - --- Location: FF_X51_Y14_N29 -\inst2|counter[10]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[10]~44_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(10)); - --- Location: LCCOMB_X51_Y14_N30 -\inst2|counter[11]~46\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND))) --- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0101101001011111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(11), - datad => VCC, - cin => \inst2|counter[10]~45\, - combout => \inst2|counter[11]~46_combout\, - cout => \inst2|counter[11]~47\); - --- Location: FF_X51_Y14_N31 -\inst2|counter[11]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[11]~46_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(11)); - --- Location: LCCOMB_X51_Y13_N0 -\inst2|counter[12]~48\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC)) --- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(12), - datad => VCC, - cin => \inst2|counter[11]~47\, - combout => \inst2|counter[12]~48_combout\, - cout => \inst2|counter[12]~49\); - --- Location: FF_X51_Y13_N1 -\inst2|counter[12]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[12]~48_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(12)); - --- Location: LCCOMB_X51_Y13_N2 +-- Location: LCCOMB_X26_Y28_N2 \inst2|counter[13]~50\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[13]~50_combout\ = (\inst2|counter\(13) & (!\inst2|counter[12]~49\)) # (!\inst2|counter\(13) & ((\inst2|counter[12]~49\) # (GND))) @@ -772,22 +2370,7 @@ PORT MAP ( combout => \inst2|counter[13]~50_combout\, cout => \inst2|counter[13]~51\); --- Location: FF_X51_Y13_N3 -\inst2|counter[13]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[13]~50_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(13)); - --- Location: LCCOMB_X51_Y13_N4 +-- Location: LCCOMB_X26_Y28_N4 \inst2|counter[14]~52\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[14]~52_combout\ = (\inst2|counter\(14) & (\inst2|counter[13]~51\ $ (GND))) # (!\inst2|counter\(14) & (!\inst2|counter[13]~51\ & VCC)) @@ -805,7 +2388,7 @@ PORT MAP ( combout => \inst2|counter[14]~52_combout\, cout => \inst2|counter[14]~53\); --- Location: FF_X51_Y13_N5 +-- Location: FF_X26_Y28_N5 \inst2|counter[14]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -815,12 +2398,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[14]~52_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(14)); --- Location: LCCOMB_X51_Y13_N6 +-- Location: LCCOMB_X26_Y28_N6 \inst2|counter[15]~54\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[15]~54_combout\ = (\inst2|counter\(15) & (!\inst2|counter[14]~53\)) # (!\inst2|counter\(15) & ((\inst2|counter[14]~53\) # (GND))) @@ -838,7 +2421,7 @@ PORT MAP ( combout => \inst2|counter[15]~54_combout\, cout => \inst2|counter[15]~55\); --- Location: FF_X51_Y13_N7 +-- Location: FF_X26_Y28_N7 \inst2|counter[15]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -848,12 +2431,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[15]~54_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(15)); --- Location: LCCOMB_X51_Y13_N8 +-- Location: LCCOMB_X26_Y28_N8 \inst2|counter[16]~56\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[16]~56_combout\ = (\inst2|counter\(16) & (\inst2|counter[15]~55\ $ (GND))) # (!\inst2|counter\(16) & (!\inst2|counter[15]~55\ & VCC)) @@ -871,7 +2454,7 @@ PORT MAP ( combout => \inst2|counter[16]~56_combout\, cout => \inst2|counter[16]~57\); --- Location: FF_X51_Y13_N9 +-- Location: FF_X26_Y28_N9 \inst2|counter[16]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -881,12 +2464,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[16]~56_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(16)); --- Location: LCCOMB_X51_Y13_N10 +-- Location: LCCOMB_X26_Y28_N10 \inst2|counter[17]~58\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[17]~58_combout\ = (\inst2|counter\(17) & (!\inst2|counter[16]~57\)) # (!\inst2|counter\(17) & ((\inst2|counter[16]~57\) # (GND))) @@ -904,7 +2487,7 @@ PORT MAP ( combout => \inst2|counter[17]~58_combout\, cout => \inst2|counter[17]~59\); --- Location: FF_X51_Y13_N11 +-- Location: FF_X26_Y28_N11 \inst2|counter[17]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -914,29 +2497,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[17]~58_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(17)); --- Location: LCCOMB_X50_Y13_N20 -\inst2|LessThan0~0\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~0_combout\ = ((!\inst2|counter\(15) & (!\inst2|counter\(16) & !\inst2|counter\(14)))) # (!\inst2|counter\(17)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0000111100011111", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(15), - datab => \inst2|counter\(16), - datac => \inst2|counter\(17), - datad => \inst2|counter\(14), - combout => \inst2|LessThan0~0_combout\); - --- Location: LCCOMB_X51_Y13_N12 +-- Location: LCCOMB_X26_Y28_N12 \inst2|counter[18]~60\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[18]~60_combout\ = (\inst2|counter\(18) & (\inst2|counter[17]~59\ $ (GND))) # (!\inst2|counter\(18) & (!\inst2|counter[17]~59\ & VCC)) @@ -954,7 +2520,7 @@ PORT MAP ( combout => \inst2|counter[18]~60_combout\, cout => \inst2|counter[18]~61\); --- Location: FF_X51_Y13_N13 +-- Location: FF_X26_Y28_N13 \inst2|counter[18]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -964,12 +2530,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[18]~60_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(18)); --- Location: LCCOMB_X51_Y13_N14 +-- Location: LCCOMB_X26_Y28_N14 \inst2|counter[19]~62\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[19]~62_combout\ = (\inst2|counter\(19) & (!\inst2|counter[18]~61\)) # (!\inst2|counter\(19) & ((\inst2|counter[18]~61\) # (GND))) @@ -987,7 +2553,7 @@ PORT MAP ( combout => \inst2|counter[19]~62_combout\, cout => \inst2|counter[19]~63\); --- Location: FF_X51_Y13_N15 +-- Location: FF_X26_Y28_N15 \inst2|counter[19]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -997,12 +2563,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[19]~62_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(19)); --- Location: LCCOMB_X51_Y13_N16 +-- Location: LCCOMB_X26_Y28_N16 \inst2|counter[20]~64\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[20]~64_combout\ = (\inst2|counter\(20) & (\inst2|counter[19]~63\ $ (GND))) # (!\inst2|counter\(20) & (!\inst2|counter[19]~63\ & VCC)) @@ -1020,7 +2586,7 @@ PORT MAP ( combout => \inst2|counter[20]~64_combout\, cout => \inst2|counter[20]~65\); --- Location: FF_X51_Y13_N17 +-- Location: FF_X26_Y28_N17 \inst2|counter[20]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1030,12 +2596,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[20]~64_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(20)); --- Location: LCCOMB_X51_Y13_N18 +-- Location: LCCOMB_X26_Y28_N18 \inst2|counter[21]~66\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[21]~66_combout\ = (\inst2|counter\(21) & (!\inst2|counter[20]~65\)) # (!\inst2|counter\(21) & ((\inst2|counter[20]~65\) # (GND))) @@ -1053,7 +2619,7 @@ PORT MAP ( combout => \inst2|counter[21]~66_combout\, cout => \inst2|counter[21]~67\); --- Location: FF_X51_Y13_N19 +-- Location: FF_X26_Y28_N19 \inst2|counter[21]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1063,12 +2629,29 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[21]~66_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(21)); --- Location: LCCOMB_X51_Y13_N20 +-- Location: LCCOMB_X26_Y28_N26 +\inst2|LessThan0~8\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~8_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0111111111111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(18), + datab => \inst2|counter\(20), + datac => \inst2|counter\(19), + datad => \inst2|counter\(21), + combout => \inst2|LessThan0~8_combout\); + +-- Location: LCCOMB_X26_Y28_N20 \inst2|counter[22]~68\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[22]~68_combout\ = (\inst2|counter\(22) & (\inst2|counter[21]~67\ $ (GND))) # (!\inst2|counter\(22) & (!\inst2|counter[21]~67\ & VCC)) @@ -1086,7 +2669,7 @@ PORT MAP ( combout => \inst2|counter[22]~68_combout\, cout => \inst2|counter[22]~69\); --- Location: FF_X51_Y13_N21 +-- Location: FF_X26_Y28_N21 \inst2|counter[22]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1096,12 +2679,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[22]~68_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(22)); --- Location: LCCOMB_X51_Y13_N22 +-- Location: LCCOMB_X26_Y28_N22 \inst2|counter[23]~70\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[23]~70_combout\ = \inst2|counter\(23) $ (\inst2|counter[22]~69\) @@ -1116,7 +2699,7 @@ PORT MAP ( cin => \inst2|counter[22]~69\, combout => \inst2|counter[23]~70_combout\); --- Location: FF_X51_Y13_N23 +-- Location: FF_X26_Y28_N23 \inst2|counter[23]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1126,48 +2709,31 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[23]~70_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(23)); --- Location: LCCOMB_X51_Y13_N24 -\inst2|LessThan0~1\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y28_N28 +\inst2|LessThan0~9\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~1_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18)) +-- \inst2|LessThan0~9_combout\ = (\inst2|LessThan0~8_combout\) # ((!\inst2|counter\(22)) # (!\inst2|counter\(23))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0111111111111111", + lut_mask => "1010111111111111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(18), - datab => \inst2|counter\(20), - datac => \inst2|counter\(19), - datad => \inst2|counter\(21), - combout => \inst2|LessThan0~1_combout\); + dataa => \inst2|LessThan0~8_combout\, + datac => \inst2|counter\(23), + datad => \inst2|counter\(22), + combout => \inst2|LessThan0~9_combout\); --- Location: LCCOMB_X51_Y13_N30 +-- Location: LCCOMB_X25_Y23_N18 \inst2|LessThan0~2\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~2_combout\ = ((\inst2|LessThan0~1_combout\) # (!\inst2|counter\(23))) # (!\inst2|counter\(22)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1111111100111111", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(22), - datac => \inst2|counter\(23), - datad => \inst2|LessThan0~1_combout\, - combout => \inst2|LessThan0~2_combout\); - --- Location: LCCOMB_X51_Y14_N4 -\inst2|LessThan0~5\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(9) & (!\inst2|counter\(8) & (!\inst2|counter\(7) & !\inst2|counter\(10)))) +-- \inst2|LessThan0~2_combout\ = (!\inst2|counter\(13) & (!\inst2|counter\(16) & (!\inst2|counter\(15) & !\inst2|counter\(6)))) -- pragma translate_off GENERIC MAP ( @@ -1175,113 +2741,590 @@ GENERIC MAP ( sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(9), - datab => \inst2|counter\(8), - datac => \inst2|counter\(7), - datad => \inst2|counter\(10), - combout => \inst2|LessThan0~5_combout\); + dataa => \inst2|counter\(13), + datab => \inst2|counter\(16), + datac => \inst2|counter\(15), + datad => \inst2|counter\(6), + combout => \inst2|LessThan0~2_combout\); --- Location: LCCOMB_X51_Y14_N0 +-- Location: LCCOMB_X26_Y29_N4 \inst2|LessThan0~3\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(2) & (!\inst2|counter\(4) & ((!\inst2|counter\(1)) # (!\inst2|counter\(0))))) +-- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(7) & (!\inst2|counter\(10) & (!\inst2|counter\(9) & !\inst2|counter\(8)))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000000100010001", + lut_mask => "0000000000000001", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(2), - datab => \inst2|counter\(4), - datac => \inst2|counter\(0), - datad => \inst2|counter\(1), + dataa => \inst2|counter\(7), + datab => \inst2|counter\(10), + datac => \inst2|counter\(9), + datad => \inst2|counter\(8), combout => \inst2|LessThan0~3_combout\); --- Location: LCCOMB_X51_Y14_N6 -\inst2|LessThan0~4\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y29_N0 +\inst2|LessThan0~0\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~4_combout\ = ((\inst2|LessThan0~3_combout\) # ((!\inst2|counter\(4) & !\inst2|counter\(3)))) # (!\inst2|counter\(5)) +-- \inst2|LessThan0~0_combout\ = (!\inst2|counter\(4) & (!\inst2|counter\(2) & ((!\inst2|counter\(0)) # (!\inst2|counter\(1))))) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111111100110111", + lut_mask => "0000000000010011", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(1), + datab => \inst2|counter\(4), + datac => \inst2|counter\(0), + datad => \inst2|counter\(2), + combout => \inst2|LessThan0~0_combout\); + +-- Location: LCCOMB_X26_Y29_N2 +\inst2|LessThan0~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~1_combout\ = (\inst2|LessThan0~0_combout\) # (((!\inst2|counter\(4) & !\inst2|counter\(3))) # (!\inst2|counter\(5))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100110111111111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( dataa => \inst2|counter\(4), - datab => \inst2|counter\(5), + datab => \inst2|LessThan0~0_combout\, datac => \inst2|counter\(3), - datad => \inst2|LessThan0~3_combout\, - combout => \inst2|LessThan0~4_combout\); + datad => \inst2|counter\(5), + combout => \inst2|LessThan0~1_combout\); --- Location: LCCOMB_X51_Y14_N2 -\inst2|LessThan0~6\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y29_N6 +\inst2|LessThan0~4\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~6_combout\ = (!\inst2|counter\(11) & (!\inst2|counter\(6) & (\inst2|LessThan0~5_combout\ & \inst2|LessThan0~4_combout\))) +-- \inst2|LessThan0~4_combout\ = (!\inst2|counter\(11) & (\inst2|LessThan0~2_combout\ & (\inst2|LessThan0~3_combout\ & \inst2|LessThan0~1_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0001000000000000", + lut_mask => "0100000000000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( dataa => \inst2|counter\(11), - datab => \inst2|counter\(6), - datac => \inst2|LessThan0~5_combout\, - datad => \inst2|LessThan0~4_combout\, - combout => \inst2|LessThan0~6_combout\); + datab => \inst2|LessThan0~2_combout\, + datac => \inst2|LessThan0~3_combout\, + datad => \inst2|LessThan0~1_combout\, + combout => \inst2|LessThan0~4_combout\); --- Location: LCCOMB_X51_Y13_N28 -\inst2|LessThan0~7\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y28_N24 +\inst2|LessThan0~6\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~7_combout\ = (\inst2|counter\(16)) # ((\inst2|counter\(13)) # ((\inst2|counter\(12) & !\inst2|LessThan0~6_combout\))) +-- \inst2|LessThan0~6_combout\ = ((!\inst2|counter\(14) & (!\inst2|counter\(16) & !\inst2|counter\(15)))) # (!\inst2|counter\(17)) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111101011111110", + lut_mask => "0101010101010111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(16), + dataa => \inst2|counter\(17), + datab => \inst2|counter\(14), + datac => \inst2|counter\(16), + datad => \inst2|counter\(15), + combout => \inst2|LessThan0~6_combout\); + +-- Location: LCCOMB_X26_Y28_N30 +\inst2|LessThan0~10\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~10_combout\ = (!\inst2|LessThan0~5_combout\ & (!\inst2|LessThan0~9_combout\ & (!\inst2|LessThan0~4_combout\ & !\inst2|LessThan0~6_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|LessThan0~5_combout\, + datab => \inst2|LessThan0~9_combout\, + datac => \inst2|LessThan0~4_combout\, + datad => \inst2|LessThan0~6_combout\, + combout => \inst2|LessThan0~10_combout\); + +-- Location: FF_X26_Y29_N9 +\inst2|counter[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[0]~24_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(0)); + +-- Location: LCCOMB_X26_Y29_N10 +\inst2|counter[1]~26\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND))) +-- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(1), + datad => VCC, + cin => \inst2|counter[0]~25\, + combout => \inst2|counter[1]~26_combout\, + cout => \inst2|counter[1]~27\); + +-- Location: FF_X26_Y29_N11 +\inst2|counter[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[1]~26_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(1)); + +-- Location: LCCOMB_X26_Y29_N12 +\inst2|counter[2]~28\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC)) +-- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010100001010", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(2), + datad => VCC, + cin => \inst2|counter[1]~27\, + combout => \inst2|counter[2]~28_combout\, + cout => \inst2|counter[2]~29\); + +-- Location: FF_X26_Y29_N13 +\inst2|counter[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[2]~28_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(2)); + +-- Location: LCCOMB_X26_Y29_N14 +\inst2|counter[3]~30\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND))) +-- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(3), + datad => VCC, + cin => \inst2|counter[2]~29\, + combout => \inst2|counter[3]~30_combout\, + cout => \inst2|counter[3]~31\); + +-- Location: FF_X26_Y29_N15 +\inst2|counter[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[3]~30_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(3)); + +-- Location: LCCOMB_X26_Y29_N16 +\inst2|counter[4]~32\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC)) +-- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(4), + datad => VCC, + cin => \inst2|counter[3]~31\, + combout => \inst2|counter[4]~32_combout\, + cout => \inst2|counter[4]~33\); + +-- Location: FF_X26_Y29_N17 +\inst2|counter[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[4]~32_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(4)); + +-- Location: LCCOMB_X26_Y29_N18 +\inst2|counter[5]~34\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND))) +-- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(5), + datad => VCC, + cin => \inst2|counter[4]~33\, + combout => \inst2|counter[5]~34_combout\, + cout => \inst2|counter[5]~35\); + +-- Location: FF_X26_Y29_N19 +\inst2|counter[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[5]~34_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(5)); + +-- Location: LCCOMB_X26_Y29_N20 +\inst2|counter[6]~36\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC)) +-- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(6), + datad => VCC, + cin => \inst2|counter[5]~35\, + combout => \inst2|counter[6]~36_combout\, + cout => \inst2|counter[6]~37\); + +-- Location: FF_X26_Y29_N21 +\inst2|counter[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[6]~36_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(6)); + +-- Location: LCCOMB_X26_Y29_N22 +\inst2|counter[7]~38\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND))) +-- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(7), + datad => VCC, + cin => \inst2|counter[6]~37\, + combout => \inst2|counter[7]~38_combout\, + cout => \inst2|counter[7]~39\); + +-- Location: FF_X26_Y29_N23 +\inst2|counter[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[7]~38_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(7)); + +-- Location: LCCOMB_X26_Y29_N24 +\inst2|counter[8]~40\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC)) +-- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(8), + datad => VCC, + cin => \inst2|counter[7]~39\, + combout => \inst2|counter[8]~40_combout\, + cout => \inst2|counter[8]~41\); + +-- Location: FF_X26_Y29_N25 +\inst2|counter[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[8]~40_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(8)); + +-- Location: LCCOMB_X26_Y29_N26 +\inst2|counter[9]~42\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND))) +-- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(9), + datad => VCC, + cin => \inst2|counter[8]~41\, + combout => \inst2|counter[9]~42_combout\, + cout => \inst2|counter[9]~43\); + +-- Location: FF_X26_Y29_N27 +\inst2|counter[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[9]~42_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(9)); + +-- Location: LCCOMB_X26_Y29_N28 +\inst2|counter[10]~44\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC)) +-- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(10), + datad => VCC, + cin => \inst2|counter[9]~43\, + combout => \inst2|counter[10]~44_combout\, + cout => \inst2|counter[10]~45\); + +-- Location: FF_X26_Y29_N29 +\inst2|counter[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[10]~44_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(10)); + +-- Location: LCCOMB_X26_Y29_N30 +\inst2|counter[11]~46\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND))) +-- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(11), + datad => VCC, + cin => \inst2|counter[10]~45\, + combout => \inst2|counter[11]~46_combout\, + cout => \inst2|counter[11]~47\); + +-- Location: FF_X26_Y29_N31 +\inst2|counter[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[11]~46_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(11)); + +-- Location: LCCOMB_X26_Y28_N0 +\inst2|counter[12]~48\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC)) +-- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( datab => \inst2|counter\(12), - datac => \inst2|counter\(13), + datad => VCC, + cin => \inst2|counter[11]~47\, + combout => \inst2|counter[12]~48_combout\, + cout => \inst2|counter[12]~49\); + +-- Location: FF_X26_Y28_N1 +\inst2|counter[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[12]~48_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(12)); + +-- Location: FF_X26_Y28_N3 +\inst2|counter[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[13]~50_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(13)); + +-- Location: LCCOMB_X25_Y23_N4 +\inst2|LessThan0~5\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(13) & (!\inst2|counter\(15) & (!\inst2|counter\(12) & !\inst2|counter\(16)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(13), + datab => \inst2|counter\(15), + datac => \inst2|counter\(12), + datad => \inst2|counter\(16), + combout => \inst2|LessThan0~5_combout\); + +-- Location: LCCOMB_X25_Y23_N6 +\inst2|LessThan0~7\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~7_combout\ = (\inst2|LessThan0~5_combout\) # (\inst2|LessThan0~6_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datac => \inst2|LessThan0~5_combout\, datad => \inst2|LessThan0~6_combout\, combout => \inst2|LessThan0~7_combout\); --- Location: LCCOMB_X51_Y13_N26 -\inst2|LessThan0~8\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~8_combout\ = (\inst2|LessThan0~0_combout\) # ((\inst2|LessThan0~2_combout\) # ((!\inst2|counter\(15) & !\inst2|LessThan0~7_combout\))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1111110011111101", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(15), - datab => \inst2|LessThan0~0_combout\, - datac => \inst2|LessThan0~2_combout\, - datad => \inst2|LessThan0~7_combout\, - combout => \inst2|LessThan0~8_combout\); - --- Location: LCCOMB_X52_Y13_N0 +-- Location: LCCOMB_X25_Y23_N8 \inst2|ledBuf~0\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (!\inst2|LessThan0~8_combout\) +-- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (((!\inst2|LessThan0~7_combout\ & (!\inst2|LessThan0~9_combout\ & !\inst2|LessThan0~4_combout\)))) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111000000001111", + lut_mask => "1111000011100001", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( + dataa => \inst2|LessThan0~7_combout\, + datab => \inst2|LessThan0~9_combout\, datac => \inst2|ledBuf~q\, - datad => \inst2|LessThan0~8_combout\, + datad => \inst2|LessThan0~4_combout\, combout => \inst2|ledBuf~0_combout\); --- Location: FF_X52_Y13_N1 +-- Location: FF_X25_Y23_N9 \inst2|ledBuf\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1295,232 +3338,124 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|ledBuf~q\); --- Location: IOIBUF_X38_Y34_N1 -\Address[7]~input\ : cycloneiii_io_ibuf +-- Location: PLL_1 +\inst|altpll_component|auto_generated|pll1\ : cycloneiii_pll -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + auto_settings => "false", + bandwidth_type => "medium", + c0_high => 3, + c0_initial => 1, + c0_low => 3, + c0_mode => "even", + c0_ph => 0, + c1_high => 2, + c1_initial => 1, + c1_low => 1, + c1_mode => "odd", + c1_ph => 0, + c1_use_casc_in => "off", + c2_high => 0, + c2_initial => 0, + c2_low => 0, + c2_mode => "bypass", + c2_ph => 0, + c2_use_casc_in => "off", + c3_high => 0, + c3_initial => 0, + c3_low => 0, + c3_mode => "bypass", + c3_ph => 0, + c3_use_casc_in => "off", + c4_high => 0, + c4_initial => 0, + c4_low => 0, + c4_mode => "bypass", + c4_ph => 0, + c4_use_casc_in => "off", + charge_pump_current_bits => 1, + clk0_counter => "c0", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 4, + clk0_phase_shift => "0", + clk1_counter => "c1", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 8, + clk1_phase_shift => "0", + clk2_counter => "unused", + clk2_divide_by => 0, + clk2_duty_cycle => 50, + clk2_multiply_by => 0, + clk2_phase_shift => "0", + clk3_counter => "unused", + clk3_divide_by => 0, + clk3_duty_cycle => 50, + clk3_multiply_by => 0, + clk3_phase_shift => "0", + clk4_counter => "unused", + clk4_divide_by => 0, + clk4_duty_cycle => 50, + clk4_multiply_by => 0, + clk4_phase_shift => "0", + compensate_clock => "clock0", + inclk0_input_frequency => 40000, + inclk1_input_frequency => 0, + loop_filter_c_bits => 0, + loop_filter_r_bits => 24, + m => 24, + m_initial => 1, + m_ph => 0, + n => 1, + operation_mode => "normal", + pfd_max => 200000, + pfd_min => 3076, + pll_compensation_delay => 7057, + self_reset_on_loss_lock => "off", + simulation_type => "timing", + switch_over_type => "auto", + vco_center => 1538, + vco_divide_by => 0, + vco_frequency_control => "auto", + vco_max => 3333, + vco_min => 1538, + vco_multiply_by => 0, + vco_phase_shift_step => 208, + vco_post_scale => 2) -- pragma translate_on PORT MAP ( - i => ww_Address(7), - o => \Address[7]~input_o\); + areset => GND, + fbin => \inst|altpll_component|auto_generated|wire_pll1_fbout\, + inclk => \inst|altpll_component|auto_generated|pll1_INCLK_bus\, + fbout => \inst|altpll_component|auto_generated|wire_pll1_fbout\, + clk => \inst|altpll_component|auto_generated|pll1_CLK_bus\); --- Location: IOIBUF_X14_Y34_N8 -\Address[6]~input\ : cycloneiii_io_ibuf +-- Location: CLKCTRL_G3 +\inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + clock_type => "global clock", + ena_register_mode => "none") -- pragma translate_on PORT MAP ( - i => ww_Address(6), - o => \Address[6]~input_o\); + inclk => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\); --- Location: IOIBUF_X7_Y34_N15 -\Address[5]~input\ : cycloneiii_io_ibuf +-- Location: CLKCTRL_G4 +\inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + clock_type => "global clock", + ena_register_mode => "none") -- pragma translate_on PORT MAP ( - i => ww_Address(5), - o => \Address[5]~input_o\); - --- Location: IOIBUF_X14_Y34_N22 -\Address[4]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(4), - o => \Address[4]~input_o\); - --- Location: IOIBUF_X7_Y34_N1 -\Address[3]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(3), - o => \Address[3]~input_o\); - --- Location: IOIBUF_X7_Y34_N8 -\Address[2]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(2), - o => \Address[2]~input_o\); - --- Location: IOIBUF_X14_Y34_N15 -\Address[1]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(1), - o => \Address[1]~input_o\); - --- Location: IOIBUF_X38_Y34_N15 -\Address[0]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(0), - o => \Address[0]~input_o\); - --- Location: IOIBUF_X20_Y34_N1 -\nOE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nOE, - o => \nOE~input_o\); - --- Location: IOIBUF_X20_Y34_N8 -\nWE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nWE, - o => \nWE~input_o\); - --- Location: IOIBUF_X20_Y34_N15 -\nCE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nCE, - o => \nCE~input_o\); - --- Location: IOIBUF_X18_Y34_N1 -\Data[7]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(7), - o => \Data[7]~input_o\); - --- Location: IOIBUF_X18_Y34_N22 -\Data[6]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(6), - o => \Data[6]~input_o\); - --- Location: IOIBUF_X16_Y34_N1 -\Data[5]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(5), - o => \Data[5]~input_o\); - --- Location: IOIBUF_X16_Y34_N15 -\Data[4]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(4), - o => \Data[4]~input_o\); - --- Location: IOIBUF_X45_Y34_N8 -\Data[3]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(3), - o => \Data[3]~input_o\); - --- Location: IOIBUF_X45_Y34_N15 -\Data[2]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(2), - o => \Data[2]~input_o\); - --- Location: IOIBUF_X45_Y34_N22 -\Data[1]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(1), - o => \Data[1]~input_o\); - --- Location: IOIBUF_X40_Y34_N8 -\Data[0]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(0), - o => \Data[0]~input_o\); - -ww_FPGA_LED_1 <= \FPGA_LED_1~output_o\; - -Data(7) <= \Data[7]~output_o\; - -Data(6) <= \Data[6]~output_o\; - -Data(5) <= \Data[5]~output_o\; - -Data(4) <= \Data[4]~output_o\; - -Data(3) <= \Data[3]~output_o\; - -Data(2) <= \Data[2]~output_o\; - -Data(1) <= \Data[1]~output_o\; - -Data(0) <= \Data[0]~output_o\; + inclk => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\); END structure; diff --git a/MainController/simulation/modelsim/MainController_8_1200mv_0c_slow.vho b/MainController/simulation/modelsim/MainController_8_1200mv_0c_slow.vho index d2c6f05..0695c7d 100644 --- a/MainController/simulation/modelsim/MainController_8_1200mv_0c_slow.vho +++ b/MainController/simulation/modelsim/MainController_8_1200mv_0c_slow.vho @@ -16,7 +16,7 @@ -- PROGRAM "Quartus II 64-Bit" -- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" --- DATE "03/12/2024 16:24:29" +-- DATE "03/12/2024 17:46:57" -- -- Device: Altera EP3C25Q240C8 Package PQFP240 @@ -37,27 +37,20 @@ ENTITY MainController IS PORT ( FPGA_LED_1 : OUT std_logic; FPGA_CLK : IN std_logic; + FPGA_LED_2 : OUT std_logic; + FPGA_LED_3 : OUT std_logic; Data : INOUT std_logic_vector(7 DOWNTO 0); - Address : IN std_logic_vector(7 DOWNTO 0); - nOE : IN std_logic; nWE : IN std_logic; - nCE : IN std_logic + nOE : IN std_logic; + nCE : IN std_logic; + Address : IN std_logic_vector(7 DOWNTO 0) ); END MainController; -- Design Ports Information -- FPGA_LED_1 => Location: PIN_166, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA --- Address[7] => Location: PIN_195, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[6] => Location: PIN_230, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[5] => Location: PIN_235, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[4] => Location: PIN_232, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[3] => Location: PIN_233, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[2] => Location: PIN_234, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[1] => Location: PIN_231, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[0] => Location: PIN_196, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nOE => Location: PIN_217, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nWE => Location: PIN_218, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nCE => Location: PIN_219, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- FPGA_LED_2 => Location: PIN_167, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +-- FPGA_LED_3 => Location: PIN_168, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[7] => Location: PIN_221, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[6] => Location: PIN_223, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[5] => Location: PIN_224, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -67,6 +60,17 @@ END MainController; -- Data[1] => Location: PIN_189, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[0] => Location: PIN_194, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- FPGA_CLK => Location: PIN_31, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nCE => Location: PIN_219, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nWE => Location: PIN_218, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[0] => Location: PIN_196, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[1] => Location: PIN_231, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[2] => Location: PIN_234, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[3] => Location: PIN_233, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[4] => Location: PIN_232, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[5] => Location: PIN_235, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[6] => Location: PIN_230, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[7] => Location: PIN_195, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nOE => Location: PIN_217, I/O Standard: 3.3-V LVTTL, Current Strength: Default ARCHITECTURE structure OF MainController IS @@ -81,42 +85,152 @@ SIGNAL ww_devclrn : std_logic; SIGNAL ww_devpor : std_logic; SIGNAL ww_FPGA_LED_1 : std_logic; SIGNAL ww_FPGA_CLK : std_logic; -SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0); -SIGNAL ww_nOE : std_logic; +SIGNAL ww_FPGA_LED_2 : std_logic; +SIGNAL ww_FPGA_LED_3 : std_logic; SIGNAL ww_nWE : std_logic; +SIGNAL ww_nOE : std_logic; SIGNAL ww_nCE : std_logic; +SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|pll1_INCLK_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|pll1_CLK_bus\ : std_logic_vector(4 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(35 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(35 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); SIGNAL \FPGA_CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); -SIGNAL \Address[7]~input_o\ : std_logic; -SIGNAL \Address[6]~input_o\ : std_logic; -SIGNAL \Address[5]~input_o\ : std_logic; -SIGNAL \Address[4]~input_o\ : std_logic; -SIGNAL \Address[3]~input_o\ : std_logic; -SIGNAL \Address[2]~input_o\ : std_logic; -SIGNAL \Address[1]~input_o\ : std_logic; -SIGNAL \Address[0]~input_o\ : std_logic; -SIGNAL \nOE~input_o\ : std_logic; -SIGNAL \nWE~input_o\ : std_logic; -SIGNAL \nCE~input_o\ : std_logic; -SIGNAL \Data[7]~input_o\ : std_logic; -SIGNAL \Data[6]~input_o\ : std_logic; -SIGNAL \Data[5]~input_o\ : std_logic; -SIGNAL \Data[4]~input_o\ : std_logic; -SIGNAL \Data[3]~input_o\ : std_logic; -SIGNAL \Data[2]~input_o\ : std_logic; -SIGNAL \Data[1]~input_o\ : std_logic; -SIGNAL \Data[0]~input_o\ : std_logic; -SIGNAL \Data[7]~output_o\ : std_logic; -SIGNAL \Data[6]~output_o\ : std_logic; -SIGNAL \Data[5]~output_o\ : std_logic; -SIGNAL \Data[4]~output_o\ : std_logic; -SIGNAL \Data[3]~output_o\ : std_logic; -SIGNAL \Data[2]~output_o\ : std_logic; -SIGNAL \Data[1]~output_o\ : std_logic; -SIGNAL \Data[0]~output_o\ : std_logic; -SIGNAL \FPGA_LED_1~output_o\ : std_logic; SIGNAL \FPGA_CLK~input_o\ : std_logic; SIGNAL \FPGA_CLK~inputclkctrl_outclk\ : std_logic; +SIGNAL \nCE~input_o\ : std_logic; +SIGNAL \Address[5]~input_o\ : std_logic; +SIGNAL \inst3|ce0Prev~q\ : std_logic; +SIGNAL \inst3|addr~5_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[12]~feeder_combout\ : std_logic; +SIGNAL \nWE~input_o\ : std_logic; +SIGNAL \inst3|we0Prev~q\ : std_logic; +SIGNAL \nOE~input_o\ : std_logic; +SIGNAL \inst3|Selector3~3_combout\ : std_logic; +SIGNAL \inst3|Selector3~2_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Writing~q\ : std_logic; +SIGNAL \inst3|memory~48_combout\ : std_logic; +SIGNAL \inst3|oe0Prev~q\ : std_logic; +SIGNAL \inst3|Selector3~0_combout\ : std_logic; +SIGNAL \inst3|Selector3~1_combout\ : std_logic; +SIGNAL \inst3|Selector2~0_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Waiting~q\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[11]~feeder_combout\ : std_logic; +SIGNAL \Address[4]~input_o\ : std_logic; +SIGNAL \inst3|addr~4_combout\ : std_logic; +SIGNAL \inst3|memory~37_combout\ : std_logic; +SIGNAL \Address[2]~input_o\ : std_logic; +SIGNAL \inst3|addr~2_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[6]~feeder_combout\ : std_logic; +SIGNAL \Address[3]~input_o\ : std_logic; +SIGNAL \inst3|addr~3_combout\ : std_logic; +SIGNAL \inst3|memory~35_combout\ : std_logic; +SIGNAL \Address[0]~input_o\ : std_logic; +SIGNAL \inst3|addr~0_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[2]~feeder_combout\ : std_logic; +SIGNAL \Address[1]~input_o\ : std_logic; +SIGNAL \inst3|addr~1_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[4]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~34_combout\ : std_logic; +SIGNAL \inst3|memory~36_combout\ : std_logic; +SIGNAL \Address[7]~input_o\ : std_logic; +SIGNAL \inst3|addr~7_combout\ : std_logic; +SIGNAL \Address[6]~input_o\ : std_logic; +SIGNAL \inst3|addr~6_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[13]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[16]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~38_combout\ : std_logic; +SIGNAL \inst3|memory~39_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Waiting~_wirecell_combout\ : std_logic; +SIGNAL \Data[0]~input_o\ : std_logic; +SIGNAL \Data[1]~input_o\ : std_logic; +SIGNAL \Data[2]~input_o\ : std_logic; +SIGNAL \Data[3]~input_o\ : std_logic; +SIGNAL \Data[4]~input_o\ : std_logic; +SIGNAL \Data[5]~input_o\ : std_logic; +SIGNAL \Data[6]~input_o\ : std_logic; +SIGNAL \Data[7]~input_o\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[24]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~40_combout\ : std_logic; +SIGNAL \inst3|Selector4~0_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Reading~q\ : std_logic; +SIGNAL \inst3|Selector74~0_combout\ : std_logic; +SIGNAL \inst3|data0[7]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[7]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[7]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[23]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a6\ : std_logic; +SIGNAL \inst3|memory~41_combout\ : std_logic; +SIGNAL \inst3|data0[6]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[6]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[6]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[22]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~42_combout\ : std_logic; +SIGNAL \inst3|data0[5]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[5]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[5]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a4\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[21]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~43_combout\ : std_logic; +SIGNAL \inst3|data0[4]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[4]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[4]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \inst3|memory~44_combout\ : std_logic; +SIGNAL \inst3|data0[3]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[3]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[3]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a2\ : std_logic; +SIGNAL \inst3|memory~45_combout\ : std_logic; +SIGNAL \inst3|data0[2]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[2]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[2]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \inst3|memory~46_combout\ : std_logic; +SIGNAL \inst3|data0[1]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[1]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[1]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \inst3|memory~47_combout\ : std_logic; +SIGNAL \inst3|data0[0]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[0]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[0]~en_q\ : std_logic; SIGNAL \inst2|counter[0]~24_combout\ : std_logic; +SIGNAL \inst2|counter[13]~51\ : std_logic; +SIGNAL \inst2|counter[14]~52_combout\ : std_logic; +SIGNAL \inst2|counter[14]~53\ : std_logic; +SIGNAL \inst2|counter[15]~54_combout\ : std_logic; +SIGNAL \inst2|counter[15]~55\ : std_logic; +SIGNAL \inst2|counter[16]~56_combout\ : std_logic; +SIGNAL \inst2|counter[16]~57\ : std_logic; +SIGNAL \inst2|counter[17]~58_combout\ : std_logic; +SIGNAL \inst2|counter[17]~59\ : std_logic; +SIGNAL \inst2|counter[18]~60_combout\ : std_logic; +SIGNAL \inst2|counter[18]~61\ : std_logic; +SIGNAL \inst2|counter[19]~62_combout\ : std_logic; +SIGNAL \inst2|counter[19]~63\ : std_logic; +SIGNAL \inst2|counter[20]~64_combout\ : std_logic; +SIGNAL \inst2|counter[20]~65\ : std_logic; +SIGNAL \inst2|counter[21]~66_combout\ : std_logic; +SIGNAL \inst2|LessThan0~8_combout\ : std_logic; +SIGNAL \inst2|counter[21]~67\ : std_logic; +SIGNAL \inst2|counter[22]~68_combout\ : std_logic; +SIGNAL \inst2|counter[22]~69\ : std_logic; +SIGNAL \inst2|counter[23]~70_combout\ : std_logic; +SIGNAL \inst2|LessThan0~9_combout\ : std_logic; +SIGNAL \inst2|LessThan0~2_combout\ : std_logic; +SIGNAL \inst2|LessThan0~3_combout\ : std_logic; +SIGNAL \inst2|LessThan0~0_combout\ : std_logic; +SIGNAL \inst2|LessThan0~1_combout\ : std_logic; +SIGNAL \inst2|LessThan0~4_combout\ : std_logic; +SIGNAL \inst2|LessThan0~6_combout\ : std_logic; +SIGNAL \inst2|LessThan0~10_combout\ : std_logic; SIGNAL \inst2|counter[0]~25\ : std_logic; SIGNAL \inst2|counter[1]~26_combout\ : std_logic; SIGNAL \inst2|counter[1]~27\ : std_logic; @@ -143,153 +257,69 @@ SIGNAL \inst2|counter[11]~47\ : std_logic; SIGNAL \inst2|counter[12]~48_combout\ : std_logic; SIGNAL \inst2|counter[12]~49\ : std_logic; SIGNAL \inst2|counter[13]~50_combout\ : std_logic; -SIGNAL \inst2|counter[13]~51\ : std_logic; -SIGNAL \inst2|counter[14]~52_combout\ : std_logic; -SIGNAL \inst2|counter[14]~53\ : std_logic; -SIGNAL \inst2|counter[15]~54_combout\ : std_logic; -SIGNAL \inst2|counter[15]~55\ : std_logic; -SIGNAL \inst2|counter[16]~56_combout\ : std_logic; -SIGNAL \inst2|counter[16]~57\ : std_logic; -SIGNAL \inst2|counter[17]~58_combout\ : std_logic; -SIGNAL \inst2|LessThan0~0_combout\ : std_logic; -SIGNAL \inst2|counter[17]~59\ : std_logic; -SIGNAL \inst2|counter[18]~60_combout\ : std_logic; -SIGNAL \inst2|counter[18]~61\ : std_logic; -SIGNAL \inst2|counter[19]~62_combout\ : std_logic; -SIGNAL \inst2|counter[19]~63\ : std_logic; -SIGNAL \inst2|counter[20]~64_combout\ : std_logic; -SIGNAL \inst2|counter[20]~65\ : std_logic; -SIGNAL \inst2|counter[21]~66_combout\ : std_logic; -SIGNAL \inst2|counter[21]~67\ : std_logic; -SIGNAL \inst2|counter[22]~68_combout\ : std_logic; -SIGNAL \inst2|counter[22]~69\ : std_logic; -SIGNAL \inst2|counter[23]~70_combout\ : std_logic; -SIGNAL \inst2|LessThan0~1_combout\ : std_logic; -SIGNAL \inst2|LessThan0~2_combout\ : std_logic; SIGNAL \inst2|LessThan0~5_combout\ : std_logic; -SIGNAL \inst2|LessThan0~3_combout\ : std_logic; -SIGNAL \inst2|LessThan0~4_combout\ : std_logic; -SIGNAL \inst2|LessThan0~6_combout\ : std_logic; SIGNAL \inst2|LessThan0~7_combout\ : std_logic; -SIGNAL \inst2|LessThan0~8_combout\ : std_logic; SIGNAL \inst2|ledBuf~0_combout\ : std_logic; SIGNAL \inst2|ledBuf~q\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_fbout\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\ : std_logic; +SIGNAL \inst3|addr\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0_bypass\ : std_logic_vector(0 TO 24); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk\ : std_logic_vector(4 DOWNTO 0); SIGNAL \inst2|counter\ : std_logic_vector(23 DOWNTO 0); -SIGNAL \inst2|ALT_INV_LessThan0~8_combout\ : std_logic; +SIGNAL \inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\ : std_logic; +SIGNAL \inst3|ALT_INV_stateMM0.Waiting~q\ : std_logic; SIGNAL \inst2|ALT_INV_ledBuf~q\ : std_logic; BEGIN FPGA_LED_1 <= ww_FPGA_LED_1; ww_FPGA_CLK <= FPGA_CLK; -ww_Address <= Address; -ww_nOE <= nOE; +FPGA_LED_2 <= ww_FPGA_LED_2; +FPGA_LED_3 <= ww_FPGA_LED_3; ww_nWE <= nWE; +ww_nOE <= nOE; ww_nCE <= nCE; +ww_Address <= Address; ww_devoe <= devoe; ww_devclrn <= devclrn; ww_devpor <= devpor; +\inst|altpll_component|auto_generated|pll1_INCLK_bus\ <= (gnd & \FPGA_CLK~input_o\); + +\inst|altpll_component|auto_generated|wire_pll1_clk\(0) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(0); +\inst|altpll_component|auto_generated|wire_pll1_clk\(1) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(1); +\inst|altpll_component|auto_generated|wire_pll1_clk\(2) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(2); +\inst|altpll_component|auto_generated|wire_pll1_clk\(3) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(3); +\inst|altpll_component|auto_generated|wire_pll1_clk\(4) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(4); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & \Data[7]~input_o\ +& \Data[6]~input_o\ & \Data[5]~input_o\ & \Data[4]~input_o\ & \Data[3]~input_o\ & \Data[2]~input_o\ & \Data[1]~input_o\ & \Data[0]~input_o\); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\inst3|addr\(7) & \inst3|addr\(6) & \inst3|addr\(5) & \inst3|addr\(4) & \inst3|addr\(3) & \inst3|addr\(2) & \inst3|addr\(1) & \inst3|addr\(0)); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\inst3|addr~7_combout\ & \inst3|addr~6_combout\ & \inst3|addr~5_combout\ & \inst3|addr~4_combout\ & \inst3|addr~3_combout\ & \inst3|addr~2_combout\ & \inst3|addr~1_combout\ & +\inst3|addr~0_combout\); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\inst3|memory_rtl_0|auto_generated|ram_block1a1\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); +\inst3|memory_rtl_0|auto_generated|ram_block1a2\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2); +\inst3|memory_rtl_0|auto_generated|ram_block1a3\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3); +\inst3|memory_rtl_0|auto_generated|ram_block1a4\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4); +\inst3|memory_rtl_0|auto_generated|ram_block1a5\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5); +\inst3|memory_rtl_0|auto_generated|ram_block1a6\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6); +\inst3|memory_rtl_0|auto_generated|ram_block1a7\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7); + +\inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|altpll_component|auto_generated|wire_pll1_clk\(1)); + +\inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|altpll_component|auto_generated|wire_pll1_clk\(0)); + \FPGA_CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \FPGA_CLK~input_o\); -\inst2|ALT_INV_LessThan0~8_combout\ <= NOT \inst2|LessThan0~8_combout\; +\inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\ <= NOT \inst3|stateMM0.Waiting~_wirecell_combout\; +\inst3|ALT_INV_stateMM0.Waiting~q\ <= NOT \inst3|stateMM0.Waiting~q\; \inst2|ALT_INV_ledBuf~q\ <= NOT \inst2|ledBuf~q\; --- Location: IOOBUF_X18_Y34_N2 -\Data[7]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[7]~output_o\); - --- Location: IOOBUF_X18_Y34_N23 -\Data[6]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[6]~output_o\); - --- Location: IOOBUF_X16_Y34_N2 -\Data[5]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[5]~output_o\); - --- Location: IOOBUF_X16_Y34_N16 -\Data[4]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[4]~output_o\); - --- Location: IOOBUF_X45_Y34_N9 -\Data[3]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[3]~output_o\); - --- Location: IOOBUF_X45_Y34_N16 -\Data[2]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[2]~output_o\); - --- Location: IOOBUF_X45_Y34_N23 -\Data[1]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[1]~output_o\); - --- Location: IOOBUF_X40_Y34_N9 -\Data[0]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[0]~output_o\); - -- Location: IOOBUF_X53_Y22_N2 \FPGA_LED_1~output\ : cycloneiii_io_obuf -- pragma translate_off @@ -300,7 +330,135 @@ GENERIC MAP ( PORT MAP ( i => \inst2|ALT_INV_ledBuf~q\, devoe => ww_devoe, - o => \FPGA_LED_1~output_o\); + o => ww_FPGA_LED_1); + +-- Location: IOOBUF_X53_Y23_N23 +\FPGA_LED_2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\, + devoe => ww_devoe, + o => ww_FPGA_LED_2); + +-- Location: IOOBUF_X53_Y23_N16 +\FPGA_LED_3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\, + devoe => ww_devoe, + o => ww_FPGA_LED_3); + +-- Location: IOOBUF_X18_Y34_N2 +\Data[7]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[7]~reg0_q\, + oe => \inst3|data0[7]~en_q\, + devoe => ww_devoe, + o => Data(7)); + +-- Location: IOOBUF_X18_Y34_N23 +\Data[6]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[6]~reg0_q\, + oe => \inst3|data0[6]~en_q\, + devoe => ww_devoe, + o => Data(6)); + +-- Location: IOOBUF_X16_Y34_N2 +\Data[5]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[5]~reg0_q\, + oe => \inst3|data0[5]~en_q\, + devoe => ww_devoe, + o => Data(5)); + +-- Location: IOOBUF_X16_Y34_N16 +\Data[4]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[4]~reg0_q\, + oe => \inst3|data0[4]~en_q\, + devoe => ww_devoe, + o => Data(4)); + +-- Location: IOOBUF_X45_Y34_N9 +\Data[3]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[3]~reg0_q\, + oe => \inst3|data0[3]~en_q\, + devoe => ww_devoe, + o => Data(3)); + +-- Location: IOOBUF_X45_Y34_N16 +\Data[2]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[2]~reg0_q\, + oe => \inst3|data0[2]~en_q\, + devoe => ww_devoe, + o => Data(2)); + +-- Location: IOOBUF_X45_Y34_N23 +\Data[1]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[1]~reg0_q\, + oe => \inst3|data0[1]~en_q\, + devoe => ww_devoe, + o => Data(1)); + +-- Location: IOOBUF_X40_Y34_N9 +\Data[0]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[0]~reg0_q\, + oe => \inst3|data0[0]~en_q\, + devoe => ww_devoe, + o => Data(0)); -- Location: IOIBUF_X0_Y16_N1 \FPGA_CLK~input\ : cycloneiii_io_ibuf @@ -313,7 +471,7 @@ PORT MAP ( i => ww_FPGA_CLK, o => \FPGA_CLK~input_o\); --- Location: CLKCTRL_G4 +-- Location: CLKCTRL_G2 \FPGA_CLK~inputclkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( @@ -326,7 +484,1858 @@ PORT MAP ( devpor => ww_devpor, outclk => \FPGA_CLK~inputclkctrl_outclk\); --- Location: LCCOMB_X51_Y14_N8 +-- Location: IOIBUF_X20_Y34_N15 +\nCE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nCE, + o => \nCE~input_o\); + +-- Location: IOIBUF_X7_Y34_N15 +\Address[5]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(5), + o => \Address[5]~input_o\); + +-- Location: FF_X27_Y29_N31 +\inst3|ce0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nCE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|ce0Prev~q\); + +-- Location: LCCOMB_X34_Y24_N26 +\inst3|addr~5\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~5_combout\ = (!\nCE~input_o\ & (\Address[5]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[5]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~5_combout\); + +-- Location: LCCOMB_X32_Y23_N12 +\inst3|memory_rtl_0_bypass[12]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[12]~feeder_combout\ = \inst3|addr~5_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~5_combout\, + combout => \inst3|memory_rtl_0_bypass[12]~feeder_combout\); + +-- Location: IOIBUF_X20_Y34_N8 +\nWE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nWE, + o => \nWE~input_o\); + +-- Location: FF_X27_Y29_N21 +\inst3|we0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nWE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|we0Prev~q\); + +-- Location: IOIBUF_X20_Y34_N1 +\nOE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nOE, + o => \nOE~input_o\); + +-- Location: LCCOMB_X27_Y29_N14 +\inst3|Selector3~3\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~3_combout\ = (\nOE~input_o\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\ & !\inst3|stateMM0.Waiting~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector3~3_combout\); + +-- Location: LCCOMB_X27_Y29_N30 +\inst3|Selector3~2\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~2_combout\ = (\inst3|stateMM0.Waiting~q\ & (((\inst3|Selector3~1_combout\)))) # (!\inst3|stateMM0.Waiting~q\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011101000010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|stateMM0.Waiting~q\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|Selector3~1_combout\, + combout => \inst3|Selector3~2_combout\); + +-- Location: FF_X27_Y29_N15 +\inst3|stateMM0.Writing\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector3~3_combout\, + ena => \inst3|Selector3~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Writing~q\); + +-- Location: LCCOMB_X27_Y29_N20 +\inst3|memory~48\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~48_combout\ = (!\nWE~input_o\ & (\inst3|we0Prev~q\ & \inst3|stateMM0.Writing~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nWE~input_o\, + datac => \inst3|we0Prev~q\, + datad => \inst3|stateMM0.Writing~q\, + combout => \inst3|memory~48_combout\); + +-- Location: FF_X27_Y29_N25 +\inst3|oe0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nOE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|oe0Prev~q\); + +-- Location: LCCOMB_X27_Y29_N24 +\inst3|Selector3~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~0_combout\ = (\nOE~input_o\ & (!\inst3|oe0Prev~q\ & !\inst3|stateMM0.Writing~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datac => \inst3|oe0Prev~q\, + datad => \inst3|stateMM0.Writing~q\, + combout => \inst3|Selector3~0_combout\); + +-- Location: LCCOMB_X27_Y29_N2 +\inst3|Selector3~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~1_combout\ = (\inst3|memory~48_combout\) # ((\nCE~input_o\) # (\inst3|Selector3~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111101110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory~48_combout\, + datab => \nCE~input_o\, + datad => \inst3|Selector3~0_combout\, + combout => \inst3|Selector3~1_combout\); + +-- Location: LCCOMB_X27_Y29_N8 +\inst3|Selector2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector2~0_combout\ = (\inst3|stateMM0.Waiting~q\ & (((!\inst3|Selector3~1_combout\)))) # (!\inst3|stateMM0.Waiting~q\ & (\inst3|ce0Prev~q\ & (!\nCE~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000001011110010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datac => \inst3|stateMM0.Waiting~q\, + datad => \inst3|Selector3~1_combout\, + combout => \inst3|Selector2~0_combout\); + +-- Location: FF_X27_Y29_N9 +\inst3|stateMM0.Waiting\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Waiting~q\); + +-- Location: FF_X32_Y23_N13 +\inst3|memory_rtl_0_bypass[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[12]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(12)); + +-- Location: FF_X34_Y24_N27 +\inst3|addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~5_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(5)); + +-- Location: LCCOMB_X32_Y23_N2 +\inst3|memory_rtl_0_bypass[11]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[11]~feeder_combout\ = \inst3|addr\(5) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr\(5), + combout => \inst3|memory_rtl_0_bypass[11]~feeder_combout\); + +-- Location: FF_X32_Y23_N3 +\inst3|memory_rtl_0_bypass[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[11]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(11)); + +-- Location: IOIBUF_X14_Y34_N22 +\Address[4]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(4), + o => \Address[4]~input_o\); + +-- Location: LCCOMB_X34_Y24_N0 +\inst3|addr~4\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~4_combout\ = (!\nCE~input_o\ & (\Address[4]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[4]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~4_combout\); + +-- Location: FF_X32_Y23_N7 +\inst3|memory_rtl_0_bypass[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~4_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(10)); + +-- Location: FF_X34_Y24_N1 +\inst3|addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~4_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(4)); + +-- Location: FF_X32_Y23_N1 +\inst3|memory_rtl_0_bypass[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(4), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(9)); + +-- Location: LCCOMB_X32_Y23_N6 +\inst3|memory~37\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~37_combout\ = (\inst3|memory_rtl_0_bypass\(12) & (\inst3|memory_rtl_0_bypass\(11) & (\inst3|memory_rtl_0_bypass\(10) $ (!\inst3|memory_rtl_0_bypass\(9))))) # (!\inst3|memory_rtl_0_bypass\(12) & (!\inst3|memory_rtl_0_bypass\(11) & +-- (\inst3|memory_rtl_0_bypass\(10) $ (!\inst3|memory_rtl_0_bypass\(9))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001000000001001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(12), + datab => \inst3|memory_rtl_0_bypass\(11), + datac => \inst3|memory_rtl_0_bypass\(10), + datad => \inst3|memory_rtl_0_bypass\(9), + combout => \inst3|memory~37_combout\); + +-- Location: IOIBUF_X7_Y34_N8 +\Address[2]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(2), + o => \Address[2]~input_o\); + +-- Location: LCCOMB_X34_Y24_N12 +\inst3|addr~2\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~2_combout\ = (!\nCE~input_o\ & (\Address[2]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[2]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~2_combout\); + +-- Location: LCCOMB_X34_Y24_N14 +\inst3|memory_rtl_0_bypass[6]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[6]~feeder_combout\ = \inst3|addr~2_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~2_combout\, + combout => \inst3|memory_rtl_0_bypass[6]~feeder_combout\); + +-- Location: FF_X34_Y24_N15 +\inst3|memory_rtl_0_bypass[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[6]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(6)); + +-- Location: IOIBUF_X7_Y34_N1 +\Address[3]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(3), + o => \Address[3]~input_o\); + +-- Location: LCCOMB_X34_Y24_N30 +\inst3|addr~3\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~3_combout\ = (\inst3|ce0Prev~q\ & (\Address[3]~input_o\ & !\nCE~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \Address[3]~input_o\, + datad => \nCE~input_o\, + combout => \inst3|addr~3_combout\); + +-- Location: FF_X34_Y24_N31 +\inst3|addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~3_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(3)); + +-- Location: FF_X27_Y29_N1 +\inst3|memory_rtl_0_bypass[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(3), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(7)); + +-- Location: FF_X34_Y24_N13 +\inst3|addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~2_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(2)); + +-- Location: FF_X27_Y29_N23 +\inst3|memory_rtl_0_bypass[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(2), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(5)); + +-- Location: FF_X34_Y24_N5 +\inst3|memory_rtl_0_bypass[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~3_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(8)); + +-- Location: LCCOMB_X27_Y29_N22 +\inst3|memory~35\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~35_combout\ = (\inst3|memory_rtl_0_bypass\(6) & (\inst3|memory_rtl_0_bypass\(5) & (\inst3|memory_rtl_0_bypass\(7) $ (!\inst3|memory_rtl_0_bypass\(8))))) # (!\inst3|memory_rtl_0_bypass\(6) & (!\inst3|memory_rtl_0_bypass\(5) & +-- (\inst3|memory_rtl_0_bypass\(7) $ (!\inst3|memory_rtl_0_bypass\(8))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(6), + datab => \inst3|memory_rtl_0_bypass\(7), + datac => \inst3|memory_rtl_0_bypass\(5), + datad => \inst3|memory_rtl_0_bypass\(8), + combout => \inst3|memory~35_combout\); + +-- Location: IOIBUF_X38_Y34_N15 +\Address[0]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(0), + o => \Address[0]~input_o\); + +-- Location: LCCOMB_X34_Y24_N24 +\inst3|addr~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~0_combout\ = (\inst3|ce0Prev~q\ & (!\nCE~input_o\ & \Address[0]~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datac => \Address[0]~input_o\, + combout => \inst3|addr~0_combout\); + +-- Location: LCCOMB_X34_Y24_N18 +\inst3|memory_rtl_0_bypass[2]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[2]~feeder_combout\ = \inst3|addr~0_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~0_combout\, + combout => \inst3|memory_rtl_0_bypass[2]~feeder_combout\); + +-- Location: FF_X34_Y24_N19 +\inst3|memory_rtl_0_bypass[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[2]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(2)); + +-- Location: IOIBUF_X14_Y34_N15 +\Address[1]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(1), + o => \Address[1]~input_o\); + +-- Location: LCCOMB_X34_Y24_N2 +\inst3|addr~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~1_combout\ = (\Address[1]~input_o\ & (!\nCE~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \Address[1]~input_o\, + datab => \nCE~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~1_combout\); + +-- Location: FF_X34_Y24_N3 +\inst3|addr[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~1_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(1)); + +-- Location: FF_X27_Y29_N29 +\inst3|memory_rtl_0_bypass[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(1), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(3)); + +-- Location: FF_X34_Y24_N25 +\inst3|addr[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~0_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(0)); + +-- Location: FF_X27_Y29_N11 +\inst3|memory_rtl_0_bypass[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(0), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(1)); + +-- Location: LCCOMB_X34_Y24_N16 +\inst3|memory_rtl_0_bypass[4]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[4]~feeder_combout\ = \inst3|addr~1_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~1_combout\, + combout => \inst3|memory_rtl_0_bypass[4]~feeder_combout\); + +-- Location: FF_X34_Y24_N17 +\inst3|memory_rtl_0_bypass[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[4]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(4)); + +-- Location: LCCOMB_X27_Y29_N10 +\inst3|memory~34\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~34_combout\ = (\inst3|memory_rtl_0_bypass\(2) & (\inst3|memory_rtl_0_bypass\(1) & (\inst3|memory_rtl_0_bypass\(3) $ (!\inst3|memory_rtl_0_bypass\(4))))) # (!\inst3|memory_rtl_0_bypass\(2) & (!\inst3|memory_rtl_0_bypass\(1) & +-- (\inst3|memory_rtl_0_bypass\(3) $ (!\inst3|memory_rtl_0_bypass\(4))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(2), + datab => \inst3|memory_rtl_0_bypass\(3), + datac => \inst3|memory_rtl_0_bypass\(1), + datad => \inst3|memory_rtl_0_bypass\(4), + combout => \inst3|memory~34_combout\); + +-- Location: LCCOMB_X27_Y29_N18 +\inst3|memory~36\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~36_combout\ = (\inst3|memory~35_combout\ & \inst3|memory~34_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datac => \inst3|memory~35_combout\, + datad => \inst3|memory~34_combout\, + combout => \inst3|memory~36_combout\); + +-- Location: FF_X27_Y29_N17 +\inst3|memory_rtl_0_bypass[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|memory~48_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(0)); + +-- Location: IOIBUF_X38_Y34_N1 +\Address[7]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(7), + o => \Address[7]~input_o\); + +-- Location: LCCOMB_X34_Y24_N22 +\inst3|addr~7\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~7_combout\ = (\inst3|ce0Prev~q\ & (!\nCE~input_o\ & \Address[7]~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datad => \Address[7]~input_o\, + combout => \inst3|addr~7_combout\); + +-- Location: FF_X34_Y24_N23 +\inst3|addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~7_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(7)); + +-- Location: FF_X34_Y24_N11 +\inst3|memory_rtl_0_bypass[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(7), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(15)); + +-- Location: IOIBUF_X14_Y34_N8 +\Address[6]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(6), + o => \Address[6]~input_o\); + +-- Location: LCCOMB_X34_Y24_N20 +\inst3|addr~6\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~6_combout\ = (\Address[6]~input_o\ & (!\nCE~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \Address[6]~input_o\, + datab => \nCE~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~6_combout\); + +-- Location: FF_X34_Y24_N21 +\inst3|addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~6_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(6)); + +-- Location: LCCOMB_X34_Y24_N8 +\inst3|memory_rtl_0_bypass[13]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[13]~feeder_combout\ = \inst3|addr\(6) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr\(6), + combout => \inst3|memory_rtl_0_bypass[13]~feeder_combout\); + +-- Location: FF_X34_Y24_N9 +\inst3|memory_rtl_0_bypass[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[13]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(13)); + +-- Location: FF_X34_Y24_N7 +\inst3|memory_rtl_0_bypass[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~6_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(14)); + +-- Location: LCCOMB_X34_Y24_N28 +\inst3|memory_rtl_0_bypass[16]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[16]~feeder_combout\ = \inst3|addr~7_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~7_combout\, + combout => \inst3|memory_rtl_0_bypass[16]~feeder_combout\); + +-- Location: FF_X34_Y24_N29 +\inst3|memory_rtl_0_bypass[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[16]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(16)); + +-- Location: LCCOMB_X34_Y24_N6 +\inst3|memory~38\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~38_combout\ = (\inst3|memory_rtl_0_bypass\(15) & (\inst3|memory_rtl_0_bypass\(16) & (\inst3|memory_rtl_0_bypass\(13) $ (!\inst3|memory_rtl_0_bypass\(14))))) # (!\inst3|memory_rtl_0_bypass\(15) & (!\inst3|memory_rtl_0_bypass\(16) & +-- (\inst3|memory_rtl_0_bypass\(13) $ (!\inst3|memory_rtl_0_bypass\(14))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000001001000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(15), + datab => \inst3|memory_rtl_0_bypass\(13), + datac => \inst3|memory_rtl_0_bypass\(14), + datad => \inst3|memory_rtl_0_bypass\(16), + combout => \inst3|memory~38_combout\); + +-- Location: LCCOMB_X27_Y29_N16 +\inst3|memory~39\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~39_combout\ = (\inst3|memory~37_combout\ & (\inst3|memory~36_combout\ & (\inst3|memory_rtl_0_bypass\(0) & \inst3|memory~38_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory~37_combout\, + datab => \inst3|memory~36_combout\, + datac => \inst3|memory_rtl_0_bypass\(0), + datad => \inst3|memory~38_combout\, + combout => \inst3|memory~39_combout\); + +-- Location: LCCOMB_X35_Y33_N24 +\inst3|stateMM0.Waiting~_wirecell\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|stateMM0.Waiting~_wirecell_combout\ = !\inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000011111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|stateMM0.Waiting~_wirecell_combout\); + +-- Location: IOIBUF_X40_Y34_N8 +\Data[0]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(0), + o => \Data[0]~input_o\); + +-- Location: IOIBUF_X45_Y34_N22 +\Data[1]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(1), + o => \Data[1]~input_o\); + +-- Location: IOIBUF_X45_Y34_N15 +\Data[2]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(2), + o => \Data[2]~input_o\); + +-- Location: IOIBUF_X45_Y34_N8 +\Data[3]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(3), + o => \Data[3]~input_o\); + +-- Location: IOIBUF_X16_Y34_N15 +\Data[4]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(4), + o => \Data[4]~input_o\); + +-- Location: IOIBUF_X16_Y34_N1 +\Data[5]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(5), + o => \Data[5]~input_o\); + +-- Location: IOIBUF_X18_Y34_N22 +\Data[6]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(6), + o => \Data[6]~input_o\); + +-- Location: IOIBUF_X18_Y34_N1 +\Data[7]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(7), + o => \Data[7]~input_o\); + +-- Location: M9K_X33_Y29_N0 +\inst3|memory_rtl_0|auto_generated|ram_block1a0\ : cycloneiii_ram_block +-- pragma translate_off +GENERIC MAP ( + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + logical_ram_name => "RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 8, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 36, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 255, + port_a_logical_ram_depth => 256, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_with_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 8, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 36, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 255, + port_b_logical_ram_depth => 256, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_with_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M9K") +-- pragma translate_on +PORT MAP ( + portawe => \inst3|memory~48_combout\, + portbre => VCC, + portbaddrstall => \inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\, + clk0 => \FPGA_CLK~inputclkctrl_outclk\, + portadatain => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LCCOMB_X35_Y29_N24 +\inst3|memory_rtl_0_bypass[24]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[24]~feeder_combout\ = \Data[7]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[7]~input_o\, + combout => \inst3|memory_rtl_0_bypass[24]~feeder_combout\); + +-- Location: FF_X35_Y29_N25 +\inst3|memory_rtl_0_bypass[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[24]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(24)); + +-- Location: LCCOMB_X35_Y29_N0 +\inst3|memory~40\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~40_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(24)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a7\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a7\, + datad => \inst3|memory_rtl_0_bypass\(24), + combout => \inst3|memory~40_combout\); + +-- Location: LCCOMB_X27_Y29_N12 +\inst3|Selector4~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector4~0_combout\ = (!\nOE~input_o\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\ & !\inst3|stateMM0.Waiting~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector4~0_combout\); + +-- Location: FF_X27_Y29_N13 +\inst3|stateMM0.Reading\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector4~0_combout\, + ena => \inst3|Selector3~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Reading~q\); + +-- Location: LCCOMB_X27_Y29_N26 +\inst3|Selector74~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector74~0_combout\ = (\inst3|stateMM0.Reading~q\) # ((!\inst3|stateMM0.Waiting~q\ & ((\nCE~input_o\) # (!\inst3|ce0Prev~q\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010101011101111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|stateMM0.Reading~q\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector74~0_combout\); + +-- Location: FF_X35_Y29_N1 +\inst3|data0[7]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~40_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[7]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N16 +\inst3|data0[7]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[7]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[7]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N17 +\inst3|data0[7]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[7]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[7]~en_q\); + +-- Location: LCCOMB_X35_Y29_N26 +\inst3|memory_rtl_0_bypass[23]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[23]~feeder_combout\ = \Data[6]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[6]~input_o\, + combout => \inst3|memory_rtl_0_bypass[23]~feeder_combout\); + +-- Location: FF_X35_Y29_N27 +\inst3|memory_rtl_0_bypass[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[23]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(23)); + +-- Location: LCCOMB_X35_Y29_N18 +\inst3|memory~41\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~41_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(23))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a6\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011100010111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(23), + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a6\, + combout => \inst3|memory~41_combout\); + +-- Location: FF_X35_Y29_N19 +\inst3|data0[6]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~41_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[6]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N18 +\inst3|data0[6]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[6]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[6]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N19 +\inst3|data0[6]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[6]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[6]~en_q\); + +-- Location: LCCOMB_X35_Y29_N28 +\inst3|memory_rtl_0_bypass[22]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[22]~feeder_combout\ = \Data[5]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[5]~input_o\, + combout => \inst3|memory_rtl_0_bypass[22]~feeder_combout\); + +-- Location: FF_X35_Y29_N29 +\inst3|memory_rtl_0_bypass[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[22]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(22)); + +-- Location: LCCOMB_X35_Y29_N20 +\inst3|memory~42\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~42_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(22)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a5\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101000001010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0|auto_generated|ram_block1a5\, + datac => \inst3|memory~39_combout\, + datad => \inst3|memory_rtl_0_bypass\(22), + combout => \inst3|memory~42_combout\); + +-- Location: FF_X35_Y29_N21 +\inst3|data0[5]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~42_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[5]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N4 +\inst3|data0[5]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[5]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[5]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N5 +\inst3|data0[5]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[5]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[5]~en_q\); + +-- Location: LCCOMB_X35_Y29_N14 +\inst3|memory_rtl_0_bypass[21]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[21]~feeder_combout\ = \Data[4]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[4]~input_o\, + combout => \inst3|memory_rtl_0_bypass[21]~feeder_combout\); + +-- Location: FF_X35_Y29_N15 +\inst3|memory_rtl_0_bypass[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[21]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(21)); + +-- Location: LCCOMB_X35_Y29_N30 +\inst3|memory~43\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~43_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(21)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a4\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110001011100010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0|auto_generated|ram_block1a4\, + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0_bypass\(21), + combout => \inst3|memory~43_combout\); + +-- Location: FF_X35_Y29_N31 +\inst3|data0[4]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~43_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[4]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N6 +\inst3|data0[4]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[4]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[4]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N7 +\inst3|data0[4]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[4]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[4]~en_q\); + +-- Location: FF_X35_Y29_N9 +\inst3|memory_rtl_0_bypass[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[3]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(20)); + +-- Location: LCCOMB_X35_Y29_N16 +\inst3|memory~44\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~44_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(20))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a3\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111001111000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0_bypass\(20), + datad => \inst3|memory_rtl_0|auto_generated|ram_block1a3\, + combout => \inst3|memory~44_combout\); + +-- Location: FF_X35_Y29_N17 +\inst3|data0[3]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~44_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[3]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N8 +\inst3|data0[3]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[3]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[3]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N9 +\inst3|data0[3]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[3]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[3]~en_q\); + +-- Location: FF_X35_Y29_N11 +\inst3|memory_rtl_0_bypass[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[2]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(19)); + +-- Location: LCCOMB_X35_Y29_N2 +\inst3|memory~45\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~45_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(19)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a2\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a2\, + datad => \inst3|memory_rtl_0_bypass\(19), + combout => \inst3|memory~45_combout\); + +-- Location: FF_X35_Y29_N3 +\inst3|data0[2]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~45_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[2]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N2 +\inst3|data0[2]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[2]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[2]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N3 +\inst3|data0[2]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[2]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[2]~en_q\); + +-- Location: FF_X35_Y29_N13 +\inst3|memory_rtl_0_bypass[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[1]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(18)); + +-- Location: LCCOMB_X35_Y29_N4 +\inst3|memory~46\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~46_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(18)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a1\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a1\, + datad => \inst3|memory_rtl_0_bypass\(18), + combout => \inst3|memory~46_combout\); + +-- Location: FF_X35_Y29_N5 +\inst3|data0[1]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~46_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[1]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N20 +\inst3|data0[1]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[1]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[1]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N21 +\inst3|data0[1]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[1]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[1]~en_q\); + +-- Location: FF_X35_Y29_N23 +\inst3|memory_rtl_0_bypass[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[0]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(17)); + +-- Location: LCCOMB_X35_Y29_N6 +\inst3|memory~47\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~47_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(17))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011100010111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(17), + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\, + combout => \inst3|memory~47_combout\); + +-- Location: FF_X35_Y29_N7 +\inst3|data0[0]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~47_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[0]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N22 +\inst3|data0[0]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[0]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[0]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N23 +\inst3|data0[0]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[0]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[0]~en_q\); + +-- Location: LCCOMB_X26_Y29_N8 \inst2|counter[0]~24\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[0]~24_combout\ = \inst2|counter\(0) $ (VCC) @@ -334,427 +2343,16 @@ PORT MAP ( -- pragma translate_off GENERIC MAP ( - lut_mask => "0101010110101010", + lut_mask => "0011001111001100", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(0), + datab => \inst2|counter\(0), datad => VCC, combout => \inst2|counter[0]~24_combout\, cout => \inst2|counter[0]~25\); --- Location: FF_X51_Y14_N9 -\inst2|counter[0]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[0]~24_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(0)); - --- Location: LCCOMB_X51_Y14_N10 -\inst2|counter[1]~26\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND))) --- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(1), - datad => VCC, - cin => \inst2|counter[0]~25\, - combout => \inst2|counter[1]~26_combout\, - cout => \inst2|counter[1]~27\); - --- Location: FF_X51_Y14_N11 -\inst2|counter[1]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[1]~26_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(1)); - --- Location: LCCOMB_X51_Y14_N12 -\inst2|counter[2]~28\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC)) --- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(2), - datad => VCC, - cin => \inst2|counter[1]~27\, - combout => \inst2|counter[2]~28_combout\, - cout => \inst2|counter[2]~29\); - --- Location: FF_X51_Y14_N13 -\inst2|counter[2]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[2]~28_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(2)); - --- Location: LCCOMB_X51_Y14_N14 -\inst2|counter[3]~30\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND))) --- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(3), - datad => VCC, - cin => \inst2|counter[2]~29\, - combout => \inst2|counter[3]~30_combout\, - cout => \inst2|counter[3]~31\); - --- Location: FF_X51_Y14_N15 -\inst2|counter[3]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[3]~30_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(3)); - --- Location: LCCOMB_X51_Y14_N16 -\inst2|counter[4]~32\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC)) --- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1010010100001010", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(4), - datad => VCC, - cin => \inst2|counter[3]~31\, - combout => \inst2|counter[4]~32_combout\, - cout => \inst2|counter[4]~33\); - --- Location: FF_X51_Y14_N17 -\inst2|counter[4]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[4]~32_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(4)); - --- Location: LCCOMB_X51_Y14_N18 -\inst2|counter[5]~34\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND))) --- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(5), - datad => VCC, - cin => \inst2|counter[4]~33\, - combout => \inst2|counter[5]~34_combout\, - cout => \inst2|counter[5]~35\); - --- Location: FF_X51_Y14_N19 -\inst2|counter[5]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[5]~34_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(5)); - --- Location: LCCOMB_X51_Y14_N20 -\inst2|counter[6]~36\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC)) --- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(6), - datad => VCC, - cin => \inst2|counter[5]~35\, - combout => \inst2|counter[6]~36_combout\, - cout => \inst2|counter[6]~37\); - --- Location: FF_X51_Y14_N21 -\inst2|counter[6]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[6]~36_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(6)); - --- Location: LCCOMB_X51_Y14_N22 -\inst2|counter[7]~38\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND))) --- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(7), - datad => VCC, - cin => \inst2|counter[6]~37\, - combout => \inst2|counter[7]~38_combout\, - cout => \inst2|counter[7]~39\); - --- Location: FF_X51_Y14_N23 -\inst2|counter[7]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[7]~38_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(7)); - --- Location: LCCOMB_X51_Y14_N24 -\inst2|counter[8]~40\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC)) --- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(8), - datad => VCC, - cin => \inst2|counter[7]~39\, - combout => \inst2|counter[8]~40_combout\, - cout => \inst2|counter[8]~41\); - --- Location: FF_X51_Y14_N25 -\inst2|counter[8]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[8]~40_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(8)); - --- Location: LCCOMB_X51_Y14_N26 -\inst2|counter[9]~42\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND))) --- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0101101001011111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(9), - datad => VCC, - cin => \inst2|counter[8]~41\, - combout => \inst2|counter[9]~42_combout\, - cout => \inst2|counter[9]~43\); - --- Location: FF_X51_Y14_N27 -\inst2|counter[9]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[9]~42_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(9)); - --- Location: LCCOMB_X51_Y14_N28 -\inst2|counter[10]~44\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC)) --- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(10), - datad => VCC, - cin => \inst2|counter[9]~43\, - combout => \inst2|counter[10]~44_combout\, - cout => \inst2|counter[10]~45\); - --- Location: FF_X51_Y14_N29 -\inst2|counter[10]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[10]~44_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(10)); - --- Location: LCCOMB_X51_Y14_N30 -\inst2|counter[11]~46\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND))) --- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0101101001011111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(11), - datad => VCC, - cin => \inst2|counter[10]~45\, - combout => \inst2|counter[11]~46_combout\, - cout => \inst2|counter[11]~47\); - --- Location: FF_X51_Y14_N31 -\inst2|counter[11]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[11]~46_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(11)); - --- Location: LCCOMB_X51_Y13_N0 -\inst2|counter[12]~48\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC)) --- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(12), - datad => VCC, - cin => \inst2|counter[11]~47\, - combout => \inst2|counter[12]~48_combout\, - cout => \inst2|counter[12]~49\); - --- Location: FF_X51_Y13_N1 -\inst2|counter[12]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[12]~48_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(12)); - --- Location: LCCOMB_X51_Y13_N2 +-- Location: LCCOMB_X26_Y28_N2 \inst2|counter[13]~50\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[13]~50_combout\ = (\inst2|counter\(13) & (!\inst2|counter[12]~49\)) # (!\inst2|counter\(13) & ((\inst2|counter[12]~49\) # (GND))) @@ -772,22 +2370,7 @@ PORT MAP ( combout => \inst2|counter[13]~50_combout\, cout => \inst2|counter[13]~51\); --- Location: FF_X51_Y13_N3 -\inst2|counter[13]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[13]~50_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(13)); - --- Location: LCCOMB_X51_Y13_N4 +-- Location: LCCOMB_X26_Y28_N4 \inst2|counter[14]~52\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[14]~52_combout\ = (\inst2|counter\(14) & (\inst2|counter[13]~51\ $ (GND))) # (!\inst2|counter\(14) & (!\inst2|counter[13]~51\ & VCC)) @@ -805,7 +2388,7 @@ PORT MAP ( combout => \inst2|counter[14]~52_combout\, cout => \inst2|counter[14]~53\); --- Location: FF_X51_Y13_N5 +-- Location: FF_X26_Y28_N5 \inst2|counter[14]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -815,12 +2398,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[14]~52_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(14)); --- Location: LCCOMB_X51_Y13_N6 +-- Location: LCCOMB_X26_Y28_N6 \inst2|counter[15]~54\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[15]~54_combout\ = (\inst2|counter\(15) & (!\inst2|counter[14]~53\)) # (!\inst2|counter\(15) & ((\inst2|counter[14]~53\) # (GND))) @@ -838,7 +2421,7 @@ PORT MAP ( combout => \inst2|counter[15]~54_combout\, cout => \inst2|counter[15]~55\); --- Location: FF_X51_Y13_N7 +-- Location: FF_X26_Y28_N7 \inst2|counter[15]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -848,12 +2431,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[15]~54_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(15)); --- Location: LCCOMB_X51_Y13_N8 +-- Location: LCCOMB_X26_Y28_N8 \inst2|counter[16]~56\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[16]~56_combout\ = (\inst2|counter\(16) & (\inst2|counter[15]~55\ $ (GND))) # (!\inst2|counter\(16) & (!\inst2|counter[15]~55\ & VCC)) @@ -871,7 +2454,7 @@ PORT MAP ( combout => \inst2|counter[16]~56_combout\, cout => \inst2|counter[16]~57\); --- Location: FF_X51_Y13_N9 +-- Location: FF_X26_Y28_N9 \inst2|counter[16]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -881,12 +2464,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[16]~56_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(16)); --- Location: LCCOMB_X51_Y13_N10 +-- Location: LCCOMB_X26_Y28_N10 \inst2|counter[17]~58\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[17]~58_combout\ = (\inst2|counter\(17) & (!\inst2|counter[16]~57\)) # (!\inst2|counter\(17) & ((\inst2|counter[16]~57\) # (GND))) @@ -904,7 +2487,7 @@ PORT MAP ( combout => \inst2|counter[17]~58_combout\, cout => \inst2|counter[17]~59\); --- Location: FF_X51_Y13_N11 +-- Location: FF_X26_Y28_N11 \inst2|counter[17]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -914,29 +2497,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[17]~58_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(17)); --- Location: LCCOMB_X50_Y13_N20 -\inst2|LessThan0~0\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~0_combout\ = ((!\inst2|counter\(15) & (!\inst2|counter\(16) & !\inst2|counter\(14)))) # (!\inst2|counter\(17)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0000111100011111", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(15), - datab => \inst2|counter\(16), - datac => \inst2|counter\(17), - datad => \inst2|counter\(14), - combout => \inst2|LessThan0~0_combout\); - --- Location: LCCOMB_X51_Y13_N12 +-- Location: LCCOMB_X26_Y28_N12 \inst2|counter[18]~60\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[18]~60_combout\ = (\inst2|counter\(18) & (\inst2|counter[17]~59\ $ (GND))) # (!\inst2|counter\(18) & (!\inst2|counter[17]~59\ & VCC)) @@ -954,7 +2520,7 @@ PORT MAP ( combout => \inst2|counter[18]~60_combout\, cout => \inst2|counter[18]~61\); --- Location: FF_X51_Y13_N13 +-- Location: FF_X26_Y28_N13 \inst2|counter[18]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -964,12 +2530,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[18]~60_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(18)); --- Location: LCCOMB_X51_Y13_N14 +-- Location: LCCOMB_X26_Y28_N14 \inst2|counter[19]~62\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[19]~62_combout\ = (\inst2|counter\(19) & (!\inst2|counter[18]~61\)) # (!\inst2|counter\(19) & ((\inst2|counter[18]~61\) # (GND))) @@ -987,7 +2553,7 @@ PORT MAP ( combout => \inst2|counter[19]~62_combout\, cout => \inst2|counter[19]~63\); --- Location: FF_X51_Y13_N15 +-- Location: FF_X26_Y28_N15 \inst2|counter[19]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -997,12 +2563,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[19]~62_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(19)); --- Location: LCCOMB_X51_Y13_N16 +-- Location: LCCOMB_X26_Y28_N16 \inst2|counter[20]~64\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[20]~64_combout\ = (\inst2|counter\(20) & (\inst2|counter[19]~63\ $ (GND))) # (!\inst2|counter\(20) & (!\inst2|counter[19]~63\ & VCC)) @@ -1020,7 +2586,7 @@ PORT MAP ( combout => \inst2|counter[20]~64_combout\, cout => \inst2|counter[20]~65\); --- Location: FF_X51_Y13_N17 +-- Location: FF_X26_Y28_N17 \inst2|counter[20]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1030,12 +2596,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[20]~64_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(20)); --- Location: LCCOMB_X51_Y13_N18 +-- Location: LCCOMB_X26_Y28_N18 \inst2|counter[21]~66\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[21]~66_combout\ = (\inst2|counter\(21) & (!\inst2|counter[20]~65\)) # (!\inst2|counter\(21) & ((\inst2|counter[20]~65\) # (GND))) @@ -1053,7 +2619,7 @@ PORT MAP ( combout => \inst2|counter[21]~66_combout\, cout => \inst2|counter[21]~67\); --- Location: FF_X51_Y13_N19 +-- Location: FF_X26_Y28_N19 \inst2|counter[21]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1063,12 +2629,29 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[21]~66_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(21)); --- Location: LCCOMB_X51_Y13_N20 +-- Location: LCCOMB_X26_Y28_N26 +\inst2|LessThan0~8\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~8_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0111111111111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(18), + datab => \inst2|counter\(20), + datac => \inst2|counter\(19), + datad => \inst2|counter\(21), + combout => \inst2|LessThan0~8_combout\); + +-- Location: LCCOMB_X26_Y28_N20 \inst2|counter[22]~68\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[22]~68_combout\ = (\inst2|counter\(22) & (\inst2|counter[21]~67\ $ (GND))) # (!\inst2|counter\(22) & (!\inst2|counter[21]~67\ & VCC)) @@ -1086,7 +2669,7 @@ PORT MAP ( combout => \inst2|counter[22]~68_combout\, cout => \inst2|counter[22]~69\); --- Location: FF_X51_Y13_N21 +-- Location: FF_X26_Y28_N21 \inst2|counter[22]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1096,12 +2679,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[22]~68_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(22)); --- Location: LCCOMB_X51_Y13_N22 +-- Location: LCCOMB_X26_Y28_N22 \inst2|counter[23]~70\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[23]~70_combout\ = \inst2|counter\(23) $ (\inst2|counter[22]~69\) @@ -1116,7 +2699,7 @@ PORT MAP ( cin => \inst2|counter[22]~69\, combout => \inst2|counter[23]~70_combout\); --- Location: FF_X51_Y13_N23 +-- Location: FF_X26_Y28_N23 \inst2|counter[23]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1126,48 +2709,31 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[23]~70_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(23)); --- Location: LCCOMB_X51_Y13_N24 -\inst2|LessThan0~1\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y28_N28 +\inst2|LessThan0~9\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~1_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18)) +-- \inst2|LessThan0~9_combout\ = (\inst2|LessThan0~8_combout\) # ((!\inst2|counter\(22)) # (!\inst2|counter\(23))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0111111111111111", + lut_mask => "1010111111111111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(18), - datab => \inst2|counter\(20), - datac => \inst2|counter\(19), - datad => \inst2|counter\(21), - combout => \inst2|LessThan0~1_combout\); + dataa => \inst2|LessThan0~8_combout\, + datac => \inst2|counter\(23), + datad => \inst2|counter\(22), + combout => \inst2|LessThan0~9_combout\); --- Location: LCCOMB_X51_Y13_N30 +-- Location: LCCOMB_X25_Y23_N18 \inst2|LessThan0~2\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~2_combout\ = ((\inst2|LessThan0~1_combout\) # (!\inst2|counter\(23))) # (!\inst2|counter\(22)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1111111100111111", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(22), - datac => \inst2|counter\(23), - datad => \inst2|LessThan0~1_combout\, - combout => \inst2|LessThan0~2_combout\); - --- Location: LCCOMB_X51_Y14_N4 -\inst2|LessThan0~5\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(9) & (!\inst2|counter\(8) & (!\inst2|counter\(7) & !\inst2|counter\(10)))) +-- \inst2|LessThan0~2_combout\ = (!\inst2|counter\(13) & (!\inst2|counter\(16) & (!\inst2|counter\(15) & !\inst2|counter\(6)))) -- pragma translate_off GENERIC MAP ( @@ -1175,113 +2741,590 @@ GENERIC MAP ( sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(9), - datab => \inst2|counter\(8), - datac => \inst2|counter\(7), - datad => \inst2|counter\(10), - combout => \inst2|LessThan0~5_combout\); + dataa => \inst2|counter\(13), + datab => \inst2|counter\(16), + datac => \inst2|counter\(15), + datad => \inst2|counter\(6), + combout => \inst2|LessThan0~2_combout\); --- Location: LCCOMB_X51_Y14_N0 +-- Location: LCCOMB_X26_Y29_N4 \inst2|LessThan0~3\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(2) & (!\inst2|counter\(4) & ((!\inst2|counter\(1)) # (!\inst2|counter\(0))))) +-- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(7) & (!\inst2|counter\(10) & (!\inst2|counter\(9) & !\inst2|counter\(8)))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000000100010001", + lut_mask => "0000000000000001", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(2), - datab => \inst2|counter\(4), - datac => \inst2|counter\(0), - datad => \inst2|counter\(1), + dataa => \inst2|counter\(7), + datab => \inst2|counter\(10), + datac => \inst2|counter\(9), + datad => \inst2|counter\(8), combout => \inst2|LessThan0~3_combout\); --- Location: LCCOMB_X51_Y14_N6 -\inst2|LessThan0~4\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y29_N0 +\inst2|LessThan0~0\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~4_combout\ = ((\inst2|LessThan0~3_combout\) # ((!\inst2|counter\(4) & !\inst2|counter\(3)))) # (!\inst2|counter\(5)) +-- \inst2|LessThan0~0_combout\ = (!\inst2|counter\(4) & (!\inst2|counter\(2) & ((!\inst2|counter\(0)) # (!\inst2|counter\(1))))) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111111100110111", + lut_mask => "0000000000010011", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(1), + datab => \inst2|counter\(4), + datac => \inst2|counter\(0), + datad => \inst2|counter\(2), + combout => \inst2|LessThan0~0_combout\); + +-- Location: LCCOMB_X26_Y29_N2 +\inst2|LessThan0~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~1_combout\ = (\inst2|LessThan0~0_combout\) # (((!\inst2|counter\(4) & !\inst2|counter\(3))) # (!\inst2|counter\(5))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100110111111111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( dataa => \inst2|counter\(4), - datab => \inst2|counter\(5), + datab => \inst2|LessThan0~0_combout\, datac => \inst2|counter\(3), - datad => \inst2|LessThan0~3_combout\, - combout => \inst2|LessThan0~4_combout\); + datad => \inst2|counter\(5), + combout => \inst2|LessThan0~1_combout\); --- Location: LCCOMB_X51_Y14_N2 -\inst2|LessThan0~6\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y29_N6 +\inst2|LessThan0~4\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~6_combout\ = (!\inst2|counter\(11) & (!\inst2|counter\(6) & (\inst2|LessThan0~5_combout\ & \inst2|LessThan0~4_combout\))) +-- \inst2|LessThan0~4_combout\ = (!\inst2|counter\(11) & (\inst2|LessThan0~2_combout\ & (\inst2|LessThan0~3_combout\ & \inst2|LessThan0~1_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0001000000000000", + lut_mask => "0100000000000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( dataa => \inst2|counter\(11), - datab => \inst2|counter\(6), - datac => \inst2|LessThan0~5_combout\, - datad => \inst2|LessThan0~4_combout\, - combout => \inst2|LessThan0~6_combout\); + datab => \inst2|LessThan0~2_combout\, + datac => \inst2|LessThan0~3_combout\, + datad => \inst2|LessThan0~1_combout\, + combout => \inst2|LessThan0~4_combout\); --- Location: LCCOMB_X51_Y13_N28 -\inst2|LessThan0~7\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y28_N24 +\inst2|LessThan0~6\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~7_combout\ = (\inst2|counter\(16)) # ((\inst2|counter\(13)) # ((\inst2|counter\(12) & !\inst2|LessThan0~6_combout\))) +-- \inst2|LessThan0~6_combout\ = ((!\inst2|counter\(14) & (!\inst2|counter\(16) & !\inst2|counter\(15)))) # (!\inst2|counter\(17)) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111101011111110", + lut_mask => "0101010101010111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(16), + dataa => \inst2|counter\(17), + datab => \inst2|counter\(14), + datac => \inst2|counter\(16), + datad => \inst2|counter\(15), + combout => \inst2|LessThan0~6_combout\); + +-- Location: LCCOMB_X26_Y28_N30 +\inst2|LessThan0~10\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~10_combout\ = (!\inst2|LessThan0~5_combout\ & (!\inst2|LessThan0~9_combout\ & (!\inst2|LessThan0~4_combout\ & !\inst2|LessThan0~6_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|LessThan0~5_combout\, + datab => \inst2|LessThan0~9_combout\, + datac => \inst2|LessThan0~4_combout\, + datad => \inst2|LessThan0~6_combout\, + combout => \inst2|LessThan0~10_combout\); + +-- Location: FF_X26_Y29_N9 +\inst2|counter[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[0]~24_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(0)); + +-- Location: LCCOMB_X26_Y29_N10 +\inst2|counter[1]~26\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND))) +-- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(1), + datad => VCC, + cin => \inst2|counter[0]~25\, + combout => \inst2|counter[1]~26_combout\, + cout => \inst2|counter[1]~27\); + +-- Location: FF_X26_Y29_N11 +\inst2|counter[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[1]~26_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(1)); + +-- Location: LCCOMB_X26_Y29_N12 +\inst2|counter[2]~28\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC)) +-- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010100001010", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(2), + datad => VCC, + cin => \inst2|counter[1]~27\, + combout => \inst2|counter[2]~28_combout\, + cout => \inst2|counter[2]~29\); + +-- Location: FF_X26_Y29_N13 +\inst2|counter[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[2]~28_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(2)); + +-- Location: LCCOMB_X26_Y29_N14 +\inst2|counter[3]~30\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND))) +-- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(3), + datad => VCC, + cin => \inst2|counter[2]~29\, + combout => \inst2|counter[3]~30_combout\, + cout => \inst2|counter[3]~31\); + +-- Location: FF_X26_Y29_N15 +\inst2|counter[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[3]~30_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(3)); + +-- Location: LCCOMB_X26_Y29_N16 +\inst2|counter[4]~32\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC)) +-- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(4), + datad => VCC, + cin => \inst2|counter[3]~31\, + combout => \inst2|counter[4]~32_combout\, + cout => \inst2|counter[4]~33\); + +-- Location: FF_X26_Y29_N17 +\inst2|counter[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[4]~32_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(4)); + +-- Location: LCCOMB_X26_Y29_N18 +\inst2|counter[5]~34\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND))) +-- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(5), + datad => VCC, + cin => \inst2|counter[4]~33\, + combout => \inst2|counter[5]~34_combout\, + cout => \inst2|counter[5]~35\); + +-- Location: FF_X26_Y29_N19 +\inst2|counter[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[5]~34_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(5)); + +-- Location: LCCOMB_X26_Y29_N20 +\inst2|counter[6]~36\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC)) +-- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(6), + datad => VCC, + cin => \inst2|counter[5]~35\, + combout => \inst2|counter[6]~36_combout\, + cout => \inst2|counter[6]~37\); + +-- Location: FF_X26_Y29_N21 +\inst2|counter[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[6]~36_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(6)); + +-- Location: LCCOMB_X26_Y29_N22 +\inst2|counter[7]~38\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND))) +-- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(7), + datad => VCC, + cin => \inst2|counter[6]~37\, + combout => \inst2|counter[7]~38_combout\, + cout => \inst2|counter[7]~39\); + +-- Location: FF_X26_Y29_N23 +\inst2|counter[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[7]~38_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(7)); + +-- Location: LCCOMB_X26_Y29_N24 +\inst2|counter[8]~40\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC)) +-- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(8), + datad => VCC, + cin => \inst2|counter[7]~39\, + combout => \inst2|counter[8]~40_combout\, + cout => \inst2|counter[8]~41\); + +-- Location: FF_X26_Y29_N25 +\inst2|counter[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[8]~40_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(8)); + +-- Location: LCCOMB_X26_Y29_N26 +\inst2|counter[9]~42\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND))) +-- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(9), + datad => VCC, + cin => \inst2|counter[8]~41\, + combout => \inst2|counter[9]~42_combout\, + cout => \inst2|counter[9]~43\); + +-- Location: FF_X26_Y29_N27 +\inst2|counter[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[9]~42_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(9)); + +-- Location: LCCOMB_X26_Y29_N28 +\inst2|counter[10]~44\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC)) +-- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(10), + datad => VCC, + cin => \inst2|counter[9]~43\, + combout => \inst2|counter[10]~44_combout\, + cout => \inst2|counter[10]~45\); + +-- Location: FF_X26_Y29_N29 +\inst2|counter[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[10]~44_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(10)); + +-- Location: LCCOMB_X26_Y29_N30 +\inst2|counter[11]~46\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND))) +-- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(11), + datad => VCC, + cin => \inst2|counter[10]~45\, + combout => \inst2|counter[11]~46_combout\, + cout => \inst2|counter[11]~47\); + +-- Location: FF_X26_Y29_N31 +\inst2|counter[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[11]~46_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(11)); + +-- Location: LCCOMB_X26_Y28_N0 +\inst2|counter[12]~48\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC)) +-- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( datab => \inst2|counter\(12), - datac => \inst2|counter\(13), + datad => VCC, + cin => \inst2|counter[11]~47\, + combout => \inst2|counter[12]~48_combout\, + cout => \inst2|counter[12]~49\); + +-- Location: FF_X26_Y28_N1 +\inst2|counter[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[12]~48_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(12)); + +-- Location: FF_X26_Y28_N3 +\inst2|counter[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[13]~50_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(13)); + +-- Location: LCCOMB_X25_Y23_N4 +\inst2|LessThan0~5\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(13) & (!\inst2|counter\(15) & (!\inst2|counter\(12) & !\inst2|counter\(16)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(13), + datab => \inst2|counter\(15), + datac => \inst2|counter\(12), + datad => \inst2|counter\(16), + combout => \inst2|LessThan0~5_combout\); + +-- Location: LCCOMB_X25_Y23_N6 +\inst2|LessThan0~7\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~7_combout\ = (\inst2|LessThan0~5_combout\) # (\inst2|LessThan0~6_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datac => \inst2|LessThan0~5_combout\, datad => \inst2|LessThan0~6_combout\, combout => \inst2|LessThan0~7_combout\); --- Location: LCCOMB_X51_Y13_N26 -\inst2|LessThan0~8\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~8_combout\ = (\inst2|LessThan0~0_combout\) # ((\inst2|LessThan0~2_combout\) # ((!\inst2|counter\(15) & !\inst2|LessThan0~7_combout\))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1111110011111101", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(15), - datab => \inst2|LessThan0~0_combout\, - datac => \inst2|LessThan0~2_combout\, - datad => \inst2|LessThan0~7_combout\, - combout => \inst2|LessThan0~8_combout\); - --- Location: LCCOMB_X52_Y13_N0 +-- Location: LCCOMB_X25_Y23_N8 \inst2|ledBuf~0\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (!\inst2|LessThan0~8_combout\) +-- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (((!\inst2|LessThan0~7_combout\ & (!\inst2|LessThan0~9_combout\ & !\inst2|LessThan0~4_combout\)))) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111000000001111", + lut_mask => "1111000011100001", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( + dataa => \inst2|LessThan0~7_combout\, + datab => \inst2|LessThan0~9_combout\, datac => \inst2|ledBuf~q\, - datad => \inst2|LessThan0~8_combout\, + datad => \inst2|LessThan0~4_combout\, combout => \inst2|ledBuf~0_combout\); --- Location: FF_X52_Y13_N1 +-- Location: FF_X25_Y23_N9 \inst2|ledBuf\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1295,232 +3338,124 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|ledBuf~q\); --- Location: IOIBUF_X38_Y34_N1 -\Address[7]~input\ : cycloneiii_io_ibuf +-- Location: PLL_1 +\inst|altpll_component|auto_generated|pll1\ : cycloneiii_pll -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + auto_settings => "false", + bandwidth_type => "medium", + c0_high => 3, + c0_initial => 1, + c0_low => 3, + c0_mode => "even", + c0_ph => 0, + c1_high => 2, + c1_initial => 1, + c1_low => 1, + c1_mode => "odd", + c1_ph => 0, + c1_use_casc_in => "off", + c2_high => 0, + c2_initial => 0, + c2_low => 0, + c2_mode => "bypass", + c2_ph => 0, + c2_use_casc_in => "off", + c3_high => 0, + c3_initial => 0, + c3_low => 0, + c3_mode => "bypass", + c3_ph => 0, + c3_use_casc_in => "off", + c4_high => 0, + c4_initial => 0, + c4_low => 0, + c4_mode => "bypass", + c4_ph => 0, + c4_use_casc_in => "off", + charge_pump_current_bits => 1, + clk0_counter => "c0", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 4, + clk0_phase_shift => "0", + clk1_counter => "c1", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 8, + clk1_phase_shift => "0", + clk2_counter => "unused", + clk2_divide_by => 0, + clk2_duty_cycle => 50, + clk2_multiply_by => 0, + clk2_phase_shift => "0", + clk3_counter => "unused", + clk3_divide_by => 0, + clk3_duty_cycle => 50, + clk3_multiply_by => 0, + clk3_phase_shift => "0", + clk4_counter => "unused", + clk4_divide_by => 0, + clk4_duty_cycle => 50, + clk4_multiply_by => 0, + clk4_phase_shift => "0", + compensate_clock => "clock0", + inclk0_input_frequency => 40000, + inclk1_input_frequency => 0, + loop_filter_c_bits => 0, + loop_filter_r_bits => 24, + m => 24, + m_initial => 1, + m_ph => 0, + n => 1, + operation_mode => "normal", + pfd_max => 200000, + pfd_min => 3076, + pll_compensation_delay => 6129, + self_reset_on_loss_lock => "off", + simulation_type => "timing", + switch_over_type => "auto", + vco_center => 1538, + vco_divide_by => 0, + vco_frequency_control => "auto", + vco_max => 3333, + vco_min => 1538, + vco_multiply_by => 0, + vco_phase_shift_step => 208, + vco_post_scale => 2) -- pragma translate_on PORT MAP ( - i => ww_Address(7), - o => \Address[7]~input_o\); + areset => GND, + fbin => \inst|altpll_component|auto_generated|wire_pll1_fbout\, + inclk => \inst|altpll_component|auto_generated|pll1_INCLK_bus\, + fbout => \inst|altpll_component|auto_generated|wire_pll1_fbout\, + clk => \inst|altpll_component|auto_generated|pll1_CLK_bus\); --- Location: IOIBUF_X14_Y34_N8 -\Address[6]~input\ : cycloneiii_io_ibuf +-- Location: CLKCTRL_G3 +\inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + clock_type => "global clock", + ena_register_mode => "none") -- pragma translate_on PORT MAP ( - i => ww_Address(6), - o => \Address[6]~input_o\); + inclk => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\); --- Location: IOIBUF_X7_Y34_N15 -\Address[5]~input\ : cycloneiii_io_ibuf +-- Location: CLKCTRL_G4 +\inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + clock_type => "global clock", + ena_register_mode => "none") -- pragma translate_on PORT MAP ( - i => ww_Address(5), - o => \Address[5]~input_o\); - --- Location: IOIBUF_X14_Y34_N22 -\Address[4]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(4), - o => \Address[4]~input_o\); - --- Location: IOIBUF_X7_Y34_N1 -\Address[3]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(3), - o => \Address[3]~input_o\); - --- Location: IOIBUF_X7_Y34_N8 -\Address[2]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(2), - o => \Address[2]~input_o\); - --- Location: IOIBUF_X14_Y34_N15 -\Address[1]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(1), - o => \Address[1]~input_o\); - --- Location: IOIBUF_X38_Y34_N15 -\Address[0]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(0), - o => \Address[0]~input_o\); - --- Location: IOIBUF_X20_Y34_N1 -\nOE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nOE, - o => \nOE~input_o\); - --- Location: IOIBUF_X20_Y34_N8 -\nWE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nWE, - o => \nWE~input_o\); - --- Location: IOIBUF_X20_Y34_N15 -\nCE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nCE, - o => \nCE~input_o\); - --- Location: IOIBUF_X18_Y34_N1 -\Data[7]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(7), - o => \Data[7]~input_o\); - --- Location: IOIBUF_X18_Y34_N22 -\Data[6]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(6), - o => \Data[6]~input_o\); - --- Location: IOIBUF_X16_Y34_N1 -\Data[5]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(5), - o => \Data[5]~input_o\); - --- Location: IOIBUF_X16_Y34_N15 -\Data[4]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(4), - o => \Data[4]~input_o\); - --- Location: IOIBUF_X45_Y34_N8 -\Data[3]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(3), - o => \Data[3]~input_o\); - --- Location: IOIBUF_X45_Y34_N15 -\Data[2]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(2), - o => \Data[2]~input_o\); - --- Location: IOIBUF_X45_Y34_N22 -\Data[1]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(1), - o => \Data[1]~input_o\); - --- Location: IOIBUF_X40_Y34_N8 -\Data[0]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(0), - o => \Data[0]~input_o\); - -ww_FPGA_LED_1 <= \FPGA_LED_1~output_o\; - -Data(7) <= \Data[7]~output_o\; - -Data(6) <= \Data[6]~output_o\; - -Data(5) <= \Data[5]~output_o\; - -Data(4) <= \Data[4]~output_o\; - -Data(3) <= \Data[3]~output_o\; - -Data(2) <= \Data[2]~output_o\; - -Data(1) <= \Data[1]~output_o\; - -Data(0) <= \Data[0]~output_o\; + inclk => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\); END structure; diff --git a/MainController/simulation/modelsim/MainController_8_1200mv_0c_vhd_slow.sdo b/MainController/simulation/modelsim/MainController_8_1200mv_0c_vhd_slow.sdo index afb55df..2a82c12 100644 --- a/MainController/simulation/modelsim/MainController_8_1200mv_0c_vhd_slow.sdo +++ b/MainController/simulation/modelsim/MainController_8_1200mv_0c_vhd_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "MainController") - (DATE "03/12/2024 16:24:29") + (DATE "03/12/2024 17:46:57") (VENDOR "Altera") (PROGRAM "Quartus II 64-Bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version") @@ -41,11 +41,127 @@ (INSTANCE \\FPGA_LED_1\~output\\) (DELAY (ABSOLUTE - (PORT i (1277:1277:1277) (1446:1446:1446)) + (PORT i (1813:1813:1813) (2116:2116:2116)) (IOPATH i o (2195:2195:2195) (2297:2297:2297)) ) ) ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\FPGA_LED_2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1429:1429:1429) (1399:1399:1399)) + (IOPATH i o (2466:2466:2466) (2351:2351:2351)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\FPGA_LED_3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1429:1429:1429) (1399:1399:1399)) + (IOPATH i o (2466:2466:2466) (2351:2351:2351)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[7\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1852:1852:1852) (1666:1666:1666)) + (PORT oe (1980:1980:1980) (1625:1625:1625)) + (IOPATH i o (2337:2337:2337) (2218:2218:2218)) + (IOPATH oe o (2197:2197:2197) (2197:2197:2197)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[6\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1574:1574:1574) (1414:1414:1414)) + (PORT oe (1838:1838:1838) (1606:1606:1606)) + (IOPATH i o (4562:4562:4562) (4088:4088:4088)) + (IOPATH oe o (2197:2197:2197) (2197:2197:2197)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[5\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (2546:2546:2546) (2186:2186:2186)) + (PORT oe (2196:2196:2196) (1899:1899:1899)) + (IOPATH i o (2337:2337:2337) (2218:2218:2218)) + (IOPATH oe o (2197:2197:2197) (2197:2197:2197)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[4\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (2656:2656:2656) (2351:2351:2351)) + (PORT oe (2170:2170:2170) (1879:1879:1879)) + (IOPATH i o (2337:2337:2337) (2218:2218:2218)) + (IOPATH oe o (2197:2197:2197) (2197:2197:2197)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[3\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1636:1636:1636) (1329:1329:1329)) + (PORT oe (1574:1574:1574) (1245:1245:1245)) + (IOPATH i o (2357:2357:2357) (2238:2238:2238)) + (IOPATH oe o (2217:2217:2217) (2217:2217:2217)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[2\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1700:1700:1700) (1459:1459:1459)) + (PORT oe (1536:1536:1536) (1223:1223:1223)) + (IOPATH i o (2357:2357:2357) (2238:2238:2238)) + (IOPATH oe o (2217:2217:2217) (2217:2217:2217)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[1\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1609:1609:1609) (1312:1312:1312)) + (PORT oe (1589:1589:1589) (1256:1256:1256)) + (IOPATH i o (2357:2357:2357) (2238:2238:2238)) + (IOPATH oe o (2217:2217:2217) (2217:2217:2217)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[0\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1344:1344:1344) (1119:1119:1119)) + (PORT oe (1245:1245:1245) (1023:1023:1023)) + (IOPATH i o (2347:2347:2347) (2228:2228:2228)) + (IOPATH oe o (2207:2207:2207) (2207:2207:2207)) + ) + ) + ) (CELL (CELLTYPE "cycloneiii_io_ibuf") (INSTANCE \\FPGA_CLK\~input\\) @@ -64,394 +180,1818 @@ ) ) ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nCE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (895:895:895) (1014:1014:1014)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[5\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|ce0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (1726:1726:1726) (1746:1746:1746)) + (PORT asdata (4497:4497:4497) (4521:4521:4521)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~5\\) + (DELAY + (ABSOLUTE + (PORT datab (3823:3823:3823) (3934:3934:3934)) + (PORT datac (4040:4040:4040) (4076:4076:4076)) + (PORT datad (1857:1857:1857) (1648:1648:1648)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[12\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1148:1148:1148) (956:956:956)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nWE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (895:895:895) (1014:1014:1014)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|we0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (1726:1726:1726) (1746:1746:1746)) + (PORT asdata (3980:3980:3980) (3991:3991:3991)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nOE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (895:895:895) (1014:1014:1014)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~3\\) + (DELAY + (ABSOLUTE + (PORT dataa (3718:3718:3718) (3764:3764:3764)) + (PORT datab (4120:4120:4120) (4131:4131:4131)) + (PORT datac (326:326:326) (399:399:399)) + (PORT datad (583:583:583) (580:580:580)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~2\\) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (625:625:625)) + (PORT datab (4127:4127:4127) (4134:4134:4134)) + (PORT datad (237:237:237) (247:247:247)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Writing\\) + (DELAY + (ABSOLUTE + (PORT clk (1726:1726:1726) (1746:1746:1746)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1547:1547:1547) (1365:1365:1365)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~48\\) + (DELAY + (ABSOLUTE + (PORT datab (3601:3601:3601) (3604:3604:3604)) + (PORT datad (542:542:542) (530:530:530)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|oe0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (1726:1726:1726) (1746:1746:1746)) + (PORT asdata (4570:4570:4570) (4590:4590:4590)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (4205:4205:4205) (4211:4211:4211)) + (PORT datad (543:543:543) (528:528:528)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (506:506:506)) + (PORT datab (4121:4121:4121) (4127:4127:4127)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (439:439:439)) + (PORT datab (4118:4118:4118) (4128:4128:4128)) + (PORT datad (233:233:233) (244:244:244)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Waiting\\) + (DELAY + (ABSOLUTE + (PORT clk (1726:1726:1726) (1746:1746:1746)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[12\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1719:1719:1719) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (3553:3553:3553) (3934:3934:3934)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[11\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1242:1242:1242) (1088:1088:1088)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[11\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1719:1719:1719) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[4\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~4\\) + (DELAY + (ABSOLUTE + (PORT datab (3827:3827:3827) (3940:3940:3940)) + (PORT datac (3771:3771:3771) (3877:3877:3877)) + (PORT datad (1850:1850:1850) (1640:1640:1640)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[10\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1719:1719:1719) (1736:1736:1736)) + (PORT asdata (1598:1598:1598) (1407:1407:1407)) + (PORT ena (3553:3553:3553) (3934:3934:3934)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[9\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1719:1719:1719) (1736:1736:1736)) + (PORT asdata (1658:1658:1658) (1504:1504:1504)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~37\\) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (377:377:377)) + (PORT datab (315:315:315) (369:369:369)) + (PORT datad (274:274:274) (329:329:329)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[2\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~2\\) + (DELAY + (ABSOLUTE + (PORT datab (3823:3823:3823) (3941:3941:3941)) + (PORT datac (4078:4078:4078) (4143:4143:4143)) + (PORT datad (1850:1850:1850) (1646:1646:1646)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[6\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (250:250:250) (258:258:258)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[6\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[3\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~3\\) + (DELAY + (ABSOLUTE + (PORT dataa (1900:1900:1900) (1694:1694:1694)) + (PORT datab (4063:4063:4063) (4087:4087:4087)) + (PORT datad (3761:3761:3761) (3892:3892:3892)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[7\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1726:1726:1726) (1746:1746:1746)) + (PORT asdata (2412:2412:2412) (2118:2118:2118)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1726:1726:1726) (1746:1746:1746)) + (PORT asdata (2361:2361:2361) (2083:2083:2083)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[8\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT asdata (675:675:675) (688:688:688)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~35\\) + (DELAY + (ABSOLUTE + (PORT dataa (2014:2014:2014) (1722:1722:1722)) + (PORT datab (318:318:318) (373:373:373)) + (PORT datad (1870:1870:1870) (1620:1620:1620)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[0\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1898:1898:1898) (1691:1691:1691)) + (PORT datab (3823:3823:3823) (3936:3936:3936)) + (PORT datac (3665:3665:3665) (3660:3660:3660)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[2\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (249:249:249) (257:257:257)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[1\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (915:915:915) (1034:1034:1034)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (3835:3835:3835) (3919:3919:3919)) + (PORT datab (3827:3827:3827) (3940:3940:3940)) + (PORT datad (1850:1850:1850) (1639:1639:1639)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1726:1726:1726) (1746:1746:1746)) + (PORT asdata (2391:2391:2391) (2239:2239:2239)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1726:1726:1726) (1746:1746:1746)) + (PORT asdata (2287:2287:2287) (2027:2027:2027)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[4\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (251:251:251) (259:259:259)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~34\\) + (DELAY + (ABSOLUTE + (PORT dataa (1884:1884:1884) (1615:1615:1615)) + (PORT datab (318:318:318) (373:373:373)) + (PORT datad (1823:1823:1823) (1581:1581:1581)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~36\\) + (DELAY + (ABSOLUTE + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1726:1726:1726) (1746:1746:1746)) + (PORT asdata (940:940:940) (890:890:890)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[7\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~7\\) + (DELAY + (ABSOLUTE + (PORT dataa (1898:1898:1898) (1691:1691:1691)) + (PORT datab (3823:3823:3823) (3936:3936:3936)) + (PORT datad (3641:3641:3641) (3690:3690:3690)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[7\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[15\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT asdata (725:725:725) (786:786:786)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[6\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (915:915:915) (1034:1034:1034)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~6\\) + (DELAY + (ABSOLUTE + (PORT dataa (3784:3784:3784) (3886:3886:3886)) + (PORT datab (3823:3823:3823) (3938:3938:3938)) + (PORT datad (1855:1855:1855) (1649:1649:1649)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[6\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[13\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (301:301:301) (356:356:356)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[13\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[14\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT asdata (876:876:876) (810:810:810)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[16\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (441:441:441) (378:378:378)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[16\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2989:2989:2989) (3250:3250:3250)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~38\\) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (377:377:377)) + (PORT datab (315:315:315) (370:370:370)) + (PORT datad (276:276:276) (331:331:331)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~39\\) + (DELAY + (ABSOLUTE + (PORT dataa (1519:1519:1519) (1281:1281:1281)) + (PORT datab (268:268:268) (274:274:274)) + (PORT datad (1809:1809:1809) (1515:1515:1515)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|stateMM0\.Waiting\~_wirecell\\) + (DELAY + (ABSOLUTE + (PORT datad (1545:1545:1545) (1374:1374:1374)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[0\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (915:915:915) (1034:1034:1034)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[1\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[2\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[3\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[4\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[5\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[6\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[7\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3669:3669:3669) (3685:3685:3685)) + (PORT d[1] (3787:3787:3787) (3874:3874:3874)) + (PORT d[2] (4101:4101:4101) (4129:4129:4129)) + (PORT d[3] (4054:4054:4054) (4109:4109:4109)) + (PORT d[4] (3756:3756:3756) (3849:3849:3849)) + (PORT d[5] (3766:3766:3766) (3893:3893:3893)) + (PORT d[6] (3756:3756:3756) (3861:3861:3861)) + (PORT d[7] (4076:4076:4076) (4094:4094:4094)) + (PORT clk (2088:2088:2088) (2131:2131:2131)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2012:2012:2012) (1793:1793:1793)) + (PORT d[1] (2061:2061:2061) (1826:1826:1826)) + (PORT d[2] (1588:1588:1588) (1407:1407:1407)) + (PORT d[3] (2062:2062:2062) (1847:1847:1847)) + (PORT d[4] (1516:1516:1516) (1340:1340:1340)) + (PORT d[5] (1361:1361:1361) (1263:1263:1263)) + (PORT d[6] (1960:1960:1960) (1727:1727:1727)) + (PORT d[7] (1647:1647:1647) (1460:1460:1460)) + (PORT clk (2085:2085:2085) (2127:2127:2127)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1465:1465:1465) (1233:1233:1233)) + (PORT clk (2085:2085:2085) (2127:2127:2127)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2088:2088:2088) (2131:2131:2131)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (3799:3799:3799) (3842:3842:3842)) + (IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2132:2132:2132)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2132:2132:2132)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2132:2132:2132)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1268:1268:1268) (1115:1115:1115)) + (PORT d[1] (1320:1320:1320) (1172:1172:1172)) + (PORT d[2] (1311:1311:1311) (1144:1144:1144)) + (PORT d[3] (1297:1297:1297) (1150:1150:1150)) + (PORT d[4] (1251:1251:1251) (1078:1078:1078)) + (PORT d[5] (1591:1591:1591) (1390:1390:1390)) + (PORT d[6] (1256:1256:1256) (1106:1106:1106)) + (PORT d[7] (1230:1230:1230) (1097:1097:1097)) + (PORT clk (2087:2087:2087) (2129:2129:2129)) + (PORT stall (1385:1385:1385) (1619:1619:1619)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + (HOLD stall (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2087:2087:2087) (2129:2129:2129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2088:2088:2088) (2130:2130:2130)) + (IOPATH (posedge clk) pulse (0:0:0) (2957:2957:2957)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2088:2088:2088) (2130:2130:2130)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2088:2088:2088) (2130:2130:2130)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[24\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (3670:3670:3670) (3740:3740:3740)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[24\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~40\\) + (DELAY + (ABSOLUTE + (PORT datab (1217:1217:1217) (1005:1005:1005)) + (PORT datac (818:818:818) (644:644:644)) + (PORT datad (279:279:279) (336:336:336)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector4\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (3717:3717:3717) (3764:3764:3764)) + (PORT datab (4119:4119:4119) (4133:4133:4133)) + (PORT datac (328:328:328) (402:402:402)) + (PORT datad (583:583:583) (580:580:580)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Reading\\) + (DELAY + (ABSOLUTE + (PORT clk (1726:1726:1726) (1746:1746:1746)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1547:1547:1547) (1365:1365:1365)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector74\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (380:380:380)) + (PORT datab (4126:4126:4126) (4133:4133:4133)) + (PORT datac (322:322:322) (394:394:394)) + (PORT datad (582:582:582) (580:580:580)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[7\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (3567:3567:3567) (3164:3164:3164)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[7\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1545:1545:1545) (1377:1377:1377)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[7\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1724:1724:1724) (1744:1744:1744)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2861:2861:2861) (2583:2583:2583)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[23\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (3625:3625:3625) (3730:3730:3730)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[23\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~41\\) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (383:383:383)) + (PORT datab (1217:1217:1217) (1009:1009:1009)) + (PORT datac (724:724:724) (581:581:581)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[6\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (3567:3567:3567) (3164:3164:3164)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[6\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1544:1544:1544) (1377:1377:1377)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[6\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1724:1724:1724) (1744:1744:1744)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2861:2861:2861) (2583:2583:2583)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[22\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (3685:3685:3685) (3796:3796:3796)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[22\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~42\\) + (DELAY + (ABSOLUTE + (PORT dataa (1458:1458:1458) (1144:1144:1144)) + (PORT datac (1170:1170:1170) (974:974:974)) + (PORT datad (277:277:277) (333:333:333)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[5\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (3567:3567:3567) (3164:3164:3164)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[5\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1541:1541:1541) (1368:1368:1368)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[5\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1724:1724:1724) (1744:1744:1744)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2861:2861:2861) (2583:2583:2583)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[21\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (3693:3693:3693) (3776:3776:3776)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[21\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~43\\) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (693:693:693)) + (PORT datab (1218:1218:1218) (1009:1009:1009)) + (PORT datac (278:278:278) (342:342:342)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[4\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (3567:3567:3567) (3164:3164:3164)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[4\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1541:1541:1541) (1369:1369:1369)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[4\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1724:1724:1724) (1744:1744:1744)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2861:2861:2861) (2583:2583:2583)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[20\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT asdata (4111:4111:4111) (4181:4181:4181)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~44\\) + (DELAY + (ABSOLUTE + (PORT datab (1217:1217:1217) (1006:1006:1006)) + (PORT datac (278:278:278) (341:341:341)) + (PORT datad (789:789:789) (625:625:625)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[3\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (3567:3567:3567) (3164:3164:3164)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[3\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1542:1542:1542) (1370:1370:1370)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[3\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1724:1724:1724) (1744:1744:1744)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2861:2861:2861) (2583:2583:2583)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[19\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT asdata (4104:4104:4104) (4180:4180:4180)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~45\\) + (DELAY + (ABSOLUTE + (PORT datab (1217:1217:1217) (1005:1005:1005)) + (PORT datac (728:728:728) (584:584:584)) + (PORT datad (277:277:277) (333:333:333)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[2\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (3567:3567:3567) (3164:3164:3164)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[2\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1541:1541:1541) (1370:1370:1370)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[2\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1724:1724:1724) (1744:1744:1744)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2861:2861:2861) (2583:2583:2583)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[18\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT asdata (4137:4137:4137) (4204:4204:4204)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~46\\) + (DELAY + (ABSOLUTE + (PORT datab (1216:1216:1216) (1005:1005:1005)) + (PORT datac (719:719:719) (572:572:572)) + (PORT datad (277:277:277) (332:332:332)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[1\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (3567:3567:3567) (3164:3164:3164)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[1\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1543:1543:1543) (1377:1377:1377)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[1\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1724:1724:1724) (1744:1744:1744)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2861:2861:2861) (2583:2583:2583)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[17\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT asdata (3925:3925:3925) (3929:3929:3929)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~47\\) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (383:383:383)) + (PORT datab (1215:1215:1215) (1005:1005:1005)) + (PORT datac (765:765:765) (608:608:608)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[0\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1721:1721:1721) (1741:1741:1741)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (3567:3567:3567) (3164:3164:3164)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[0\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1545:1545:1545) (1374:1374:1374)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[0\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1724:1724:1724) (1744:1744:1744)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2861:2861:2861) (2583:2583:2583)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[0\]\~24\\) (DELAY (ABSOLUTE - (PORT dataa (553:553:553) (536:536:536)) - (IOPATH dataa combout (435:435:435) (425:425:425)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[0\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1712:1712:1712) (1732:1732:1732)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[1\]\~26\\) - (DELAY - (ABSOLUTE - (PORT datab (558:558:558) (530:530:530)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[1\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1712:1712:1712) (1732:1732:1732)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[2\]\~28\\) - (DELAY - (ABSOLUTE - (PORT datab (548:548:548) (534:534:534)) + (PORT datab (326:326:326) (382:382:382)) (IOPATH datab combout (437:437:437) (425:425:425)) (IOPATH datab cout (497:497:497) (381:381:381)) (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[2\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1712:1712:1712) (1732:1732:1732)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[3\]\~30\\) - (DELAY - (ABSOLUTE - (PORT datab (326:326:326) (383:383:383)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[3\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2182:2182:2182) (2152:2152:2152)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[4\]\~32\\) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (551:551:551)) - (IOPATH dataa combout (435:435:435) (425:425:425)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[4\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1712:1712:1712) (1732:1732:1732)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[5\]\~34\\) - (DELAY - (ABSOLUTE - (PORT datab (326:326:326) (383:383:383)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[5\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1712:1712:1712) (1732:1732:1732)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[6\]\~36\\) - (DELAY - (ABSOLUTE - (PORT datab (326:326:326) (384:384:384)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[6\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2182:2182:2182) (2152:2152:2152)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[7\]\~38\\) - (DELAY - (ABSOLUTE - (PORT datab (548:548:548) (530:530:530)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[7\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1712:1712:1712) (1732:1732:1732)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[8\]\~40\\) - (DELAY - (ABSOLUTE - (PORT datab (325:325:325) (382:382:382)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[8\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1712:1712:1712) (1732:1732:1732)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[9\]\~42\\) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (392:392:392)) - (IOPATH dataa combout (414:414:414) (444:444:444)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[9\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1712:1712:1712) (1732:1732:1732)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[10\]\~44\\) - (DELAY - (ABSOLUTE - (PORT datab (324:324:324) (381:381:381)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[10\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2182:2182:2182) (2152:2152:2152)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[11\]\~46\\) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (392:392:392)) - (IOPATH dataa combout (414:414:414) (444:444:444)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[11\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2182:2182:2182) (2152:2152:2152)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (1344:1344:1344) (1536:1536:1536)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[12\]\~48\\) - (DELAY - (ABSOLUTE - (PORT datab (323:323:323) (381:381:381)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[12\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2183:2183:2183) (2153:2153:2153)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[13\]\~50\\) @@ -466,28 +2006,12 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[13\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2183:2183:2183) (2153:2153:2153)) - (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[14\]\~52\\) (DELAY (ABSOLUTE - (PORT datab (339:339:339) (393:393:393)) + (PORT datab (325:325:325) (382:382:382)) (IOPATH datab combout (437:437:437) (425:425:425)) (IOPATH datab cout (497:497:497) (381:381:381)) (IOPATH datad combout (167:167:167) (143:143:143)) @@ -501,9 +2025,9 @@ (INSTANCE \\inst2\|counter\[14\]\\) (DELAY (ABSOLUTE - (PORT clk (2183:2183:2183) (2153:2153:2153)) + (PORT clk (1713:1713:1713) (1732:1732:1732)) (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) + (PORT sclr (873:873:873) (934:934:934)) (IOPATH (posedge clk) q (240:240:240) (240:240:240)) ) ) @@ -517,7 +2041,7 @@ (INSTANCE \\inst2\|counter\[15\]\~54\\) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (414:414:414)) + (PORT dataa (349:349:349) (411:411:411)) (IOPATH dataa combout (414:414:414) (444:444:444)) (IOPATH dataa cout (486:486:486) (375:375:375)) (IOPATH datad combout (167:167:167) (143:143:143)) @@ -531,9 +2055,9 @@ (INSTANCE \\inst2\|counter\[15\]\\) (DELAY (ABSOLUTE - (PORT clk (1711:1711:1711) (1731:1731:1731)) + (PORT clk (1713:1713:1713) (1732:1732:1732)) (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) + (PORT sclr (873:873:873) (934:934:934)) (IOPATH (posedge clk) q (240:240:240) (240:240:240)) ) ) @@ -547,7 +2071,7 @@ (INSTANCE \\inst2\|counter\[16\]\~56\\) (DELAY (ABSOLUTE - (PORT datab (340:340:340) (394:394:394)) + (PORT datab (348:348:348) (405:405:405)) (IOPATH datab combout (437:437:437) (425:425:425)) (IOPATH datab cout (497:497:497) (381:381:381)) (IOPATH datad combout (167:167:167) (143:143:143)) @@ -561,9 +2085,9 @@ (INSTANCE \\inst2\|counter\[16\]\\) (DELAY (ABSOLUTE - (PORT clk (1711:1711:1711) (1731:1731:1731)) + (PORT clk (1713:1713:1713) (1732:1732:1732)) (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) + (PORT sclr (873:873:873) (934:934:934)) (IOPATH (posedge clk) q (240:240:240) (240:240:240)) ) ) @@ -577,7 +2101,7 @@ (INSTANCE \\inst2\|counter\[17\]\~58\\) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (403:403:403)) + (PORT dataa (330:330:330) (394:394:394)) (IOPATH dataa combout (414:414:414) (444:444:444)) (IOPATH dataa cout (486:486:486) (375:375:375)) (IOPATH datad combout (167:167:167) (143:143:143)) @@ -591,9 +2115,9 @@ (INSTANCE \\inst2\|counter\[17\]\\) (DELAY (ABSOLUTE - (PORT clk (1711:1711:1711) (1731:1731:1731)) + (PORT clk (1713:1713:1713) (1732:1732:1732)) (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) + (PORT sclr (873:873:873) (934:934:934)) (IOPATH (posedge clk) q (240:240:240) (240:240:240)) ) ) @@ -602,22 +2126,6 @@ (HOLD sclr (posedge clk) (195:195:195)) ) ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~0\\) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (761:761:761)) - (PORT datab (618:618:618) (575:575:575)) - (PORT datac (513:513:513) (507:507:507)) - (PORT datad (552:552:552) (524:524:524)) - (IOPATH dataa combout (392:392:392) (419:419:419)) - (IOPATH datab combout (393:393:393) (431:431:431)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[18\]\~60\\) @@ -637,9 +2145,9 @@ (INSTANCE \\inst2\|counter\[18\]\\) (DELAY (ABSOLUTE - (PORT clk (1711:1711:1711) (1731:1731:1731)) + (PORT clk (1713:1713:1713) (1732:1732:1732)) (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) + (PORT sclr (873:873:873) (934:934:934)) (IOPATH (posedge clk) q (240:240:240) (240:240:240)) ) ) @@ -667,9 +2175,9 @@ (INSTANCE \\inst2\|counter\[19\]\\) (DELAY (ABSOLUTE - (PORT clk (2183:2183:2183) (2153:2153:2153)) + (PORT clk (1713:1713:1713) (1732:1732:1732)) (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) + (PORT sclr (873:873:873) (934:934:934)) (IOPATH (posedge clk) q (240:240:240) (240:240:240)) ) ) @@ -697,9 +2205,9 @@ (INSTANCE \\inst2\|counter\[20\]\\) (DELAY (ABSOLUTE - (PORT clk (2183:2183:2183) (2153:2153:2153)) + (PORT clk (1713:1713:1713) (1732:1732:1732)) (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) + (PORT sclr (873:873:873) (934:934:934)) (IOPATH (posedge clk) q (240:240:240) (240:240:240)) ) ) @@ -727,9 +2235,9 @@ (INSTANCE \\inst2\|counter\[21\]\\) (DELAY (ABSOLUTE - (PORT clk (2183:2183:2183) (2153:2153:2153)) + (PORT clk (1713:1713:1713) (1732:1732:1732)) (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) + (PORT sclr (873:873:873) (934:934:934)) (IOPATH (posedge clk) q (240:240:240) (240:240:240)) ) ) @@ -738,12 +2246,28 @@ (HOLD sclr (posedge clk) (195:195:195)) ) ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~8\\) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (394:394:394)) + (PORT datab (326:326:326) (384:384:384)) + (PORT datac (284:284:284) (350:350:350)) + (PORT datad (284:284:284) (343:343:343)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[22\]\~68\\) (DELAY (ABSOLUTE - (PORT datab (328:328:328) (386:386:386)) + (PORT datab (327:327:327) (384:384:384)) (IOPATH datab combout (437:437:437) (425:425:425)) (IOPATH datab cout (497:497:497) (381:381:381)) (IOPATH datad combout (167:167:167) (143:143:143)) @@ -757,9 +2281,9 @@ (INSTANCE \\inst2\|counter\[22\]\\) (DELAY (ABSOLUTE - (PORT clk (2183:2183:2183) (2153:2153:2153)) + (PORT clk (1713:1713:1713) (1732:1732:1732)) (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) + (PORT sclr (873:873:873) (934:934:934)) (IOPATH (posedge clk) q (240:240:240) (240:240:240)) ) ) @@ -773,7 +2297,7 @@ (INSTANCE \\inst2\|counter\[23\]\~70\\) (DELAY (ABSOLUTE - (PORT dataa (808:808:808) (716:716:716)) + (PORT dataa (331:331:331) (393:393:393)) (IOPATH dataa combout (435:435:435) (444:444:444)) (IOPATH cin combout (549:549:549) (519:519:519)) ) @@ -784,9 +2308,9 @@ (INSTANCE \\inst2\|counter\[23\]\\) (DELAY (ABSOLUTE - (PORT clk (2183:2183:2183) (2153:2153:2153)) + (PORT clk (1713:1713:1713) (1732:1732:1732)) (PORT d (90:90:90) (101:101:101)) - (PORT sclr (884:884:884) (924:924:924)) + (PORT sclr (873:873:873) (934:934:934)) (IOPATH (posedge clk) q (240:240:240) (240:240:240)) ) ) @@ -797,15 +2321,13 @@ ) (CELL (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~1\\) + (INSTANCE \\inst2\|LessThan0\~9\\) (DELAY (ABSOLUTE - (PORT dataa (329:329:329) (393:393:393)) - (PORT datab (326:326:326) (383:383:383)) - (PORT datac (283:283:283) (349:349:349)) - (PORT datad (284:284:284) (342:342:342)) - (IOPATH dataa combout (374:374:374) (392:392:392)) - (IOPATH datab combout (384:384:384) (398:398:398)) + (PORT dataa (269:269:269) (281:281:281)) + (PORT datac (284:284:284) (352:352:352)) + (PORT datad (284:284:284) (344:344:344)) + (IOPATH dataa combout (377:377:377) (371:371:371)) (IOPATH datac combout (301:301:301) (283:283:283)) (IOPATH datad combout (167:167:167) (143:143:143)) ) @@ -816,24 +2338,10 @@ (INSTANCE \\inst2\|LessThan0\~2\\) (DELAY (ABSOLUTE - (PORT datab (327:327:327) (384:384:384)) - (PORT datac (761:761:761) (676:676:676)) - (PORT datad (225:225:225) (233:233:233)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~5\\) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (392:392:392)) - (PORT datab (325:325:325) (382:382:382)) - (PORT datac (297:297:297) (359:359:359)) - (PORT datad (284:284:284) (343:343:343)) + (PORT dataa (1301:1301:1301) (1193:1193:1193)) + (PORT datab (1305:1305:1305) (1176:1176:1176)) + (PORT datac (1297:1297:1297) (1163:1163:1163)) + (PORT datad (1266:1266:1266) (1160:1160:1160)) (IOPATH dataa combout (404:404:404) (450:450:450)) (IOPATH datab combout (406:406:406) (453:453:453)) (IOPATH datac combout (301:301:301) (283:283:283)) @@ -846,10 +2354,10 @@ (INSTANCE \\inst2\|LessThan0\~3\\) (DELAY (ABSOLUTE - (PORT dataa (341:341:341) (401:401:401)) - (PORT datab (339:339:339) (394:394:394)) - (PORT datac (296:296:296) (359:359:359)) - (PORT datad (297:297:297) (353:353:353)) + (PORT dataa (328:328:328) (392:392:392)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (283:283:283) (351:351:351)) + (PORT datad (284:284:284) (343:343:343)) (IOPATH dataa combout (404:404:404) (450:450:450)) (IOPATH datab combout (406:406:406) (453:453:453)) (IOPATH datac combout (301:301:301) (283:283:283)) @@ -857,18 +2365,50 @@ ) ) ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (394:394:394)) + (PORT datab (349:349:349) (406:406:406)) + (PORT datac (283:283:283) (350:350:350)) + (PORT datad (285:285:285) (346:346:346)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (538:538:538)) + (PORT datab (266:266:266) (272:272:272)) + (PORT datac (283:283:283) (350:350:350)) + (PORT datad (285:285:285) (344:344:344)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|LessThan0\~4\\) (DELAY (ABSOLUTE - (PORT dataa (570:570:570) (549:549:549)) - (PORT datab (326:326:326) (382:382:382)) - (PORT datac (283:283:283) (348:348:348)) - (PORT datad (225:225:225) (232:232:232)) - (IOPATH dataa combout (428:428:428) (449:449:449)) - (IOPATH datab combout (438:438:438) (455:455:455)) - (IOPATH datac combout (301:301:301) (283:283:283)) + (PORT dataa (330:330:330) (393:393:393)) + (PORT datab (1202:1202:1202) (1035:1035:1035)) + (PORT datac (225:225:225) (239:239:239)) + (PORT datad (225:225:225) (233:233:233)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) (IOPATH datad combout (167:167:167) (143:143:143)) ) ) @@ -878,13 +2418,437 @@ (INSTANCE \\inst2\|LessThan0\~6\\) (DELAY (ABSOLUTE - (PORT dataa (332:332:332) (396:396:396)) - (PORT datab (328:328:328) (385:385:385)) - (PORT datac (224:224:224) (239:239:239)) - (PORT datad (225:225:225) (233:233:233)) - (IOPATH dataa combout (350:350:350) (371:371:371)) - (IOPATH datab combout (354:354:354) (380:380:380)) - (IOPATH datac combout (301:301:301) (285:285:285)) + (PORT dataa (329:329:329) (392:392:392)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (306:306:306) (371:371:371)) + (PORT datad (308:308:308) (367:367:367)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~10\\) + (DELAY + (ABSOLUTE + (PORT dataa (1247:1247:1247) (1079:1079:1079)) + (PORT datab (289:289:289) (296:296:296)) + (PORT datac (829:829:829) (690:690:690)) + (PORT datad (249:249:249) (257:257:257)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[1\]\~26\\) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (394:394:394)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[2\]\~28\\) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (390:390:390)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[3\]\~30\\) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[4\]\~32\\) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (406:406:406)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[5\]\~34\\) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[6\]\~36\\) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[6\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[7\]\~38\\) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (392:392:392)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[7\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[8\]\~40\\) + (DELAY + (ABSOLUTE + (PORT datab (324:324:324) (380:380:380)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[8\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[9\]\~42\\) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (389:389:389)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[9\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[10\]\~44\\) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[10\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[11\]\~46\\) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (392:392:392)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[11\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1715:1715:1715) (1736:1736:1736)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (1447:1447:1447) (1362:1362:1362)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[12\]\~48\\) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (391:391:391)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[12\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1713:1713:1713) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (873:873:873) (934:934:934)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[13\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1713:1713:1713) (1732:1732:1732)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (873:873:873) (934:934:934)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~5\\) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1190:1190:1190)) + (PORT datab (1349:1349:1349) (1194:1194:1194)) + (PORT datac (1281:1281:1281) (1153:1153:1153)) + (PORT datad (1248:1248:1248) (1135:1135:1135)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) (IOPATH datad combout (167:167:167) (143:143:143)) ) ) @@ -894,29 +2858,9 @@ (INSTANCE \\inst2\|LessThan0\~7\\) (DELAY (ABSOLUTE - (PORT dataa (563:563:563) (549:549:549)) - (PORT datab (329:329:329) (387:387:387)) - (PORT datac (522:522:522) (502:502:502)) - (PORT datad (799:799:799) (654:654:654)) - (IOPATH dataa combout (435:435:435) (407:407:407)) - (IOPATH datab combout (437:437:437) (407:407:407)) - (IOPATH datac combout (305:305:305) (285:285:285)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~8\\) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (418:418:418)) - (PORT datab (529:529:529) (432:432:432)) - (PORT datac (224:224:224) (239:239:239)) - (PORT datad (224:224:224) (232:232:232)) - (IOPATH dataa combout (404:404:404) (450:450:450)) - (IOPATH datab combout (415:415:415) (425:425:425)) - (IOPATH datac combout (305:305:305) (285:285:285)) + (PORT datac (248:248:248) (262:262:262)) + (PORT datad (1220:1220:1220) (1045:1045:1045)) + (IOPATH datac combout (305:305:305) (283:283:283)) (IOPATH datad combout (167:167:167) (143:143:143)) ) ) @@ -926,7 +2870,11 @@ (INSTANCE \\inst2\|ledBuf\~0\\) (DELAY (ABSOLUTE - (PORT datad (737:737:737) (601:601:601)) + (PORT dataa (270:270:270) (281:281:281)) + (PORT datab (1233:1233:1233) (1070:1070:1070)) + (PORT datad (1183:1183:1183) (1026:1026:1026)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) (IOPATH datac combout (415:415:415) (429:429:429)) (IOPATH datad combout (167:167:167) (143:143:143)) ) @@ -937,7 +2885,7 @@ (INSTANCE \\inst2\|ledBuf\\) (DELAY (ABSOLUTE - (PORT clk (2183:2183:2183) (2153:2153:2153)) + (PORT clk (1709:1709:1709) (1727:1727:1727)) (PORT d (90:90:90) (101:101:101)) (IOPATH (posedge clk) q (240:240:240) (240:240:240)) ) @@ -946,4 +2894,31 @@ (HOLD d (posedge clk) (195:195:195)) ) ) + (CELL + (CELLTYPE "cycloneiii_pll") + (INSTANCE \\inst\|altpll_component\|auto_generated\|pll1\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2075:2075:2075) (2075:2075:2075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_clkctrl") + (INSTANCE \\inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2065:2065:2065) (2030:2030:2030)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_clkctrl") + (INSTANCE \\inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2065:2065:2065) (2030:2030:2030)) + ) + ) + ) ) diff --git a/MainController/simulation/modelsim/MainController_8_1200mv_85c_slow.vho b/MainController/simulation/modelsim/MainController_8_1200mv_85c_slow.vho index d2c6f05..e2557e0 100644 --- a/MainController/simulation/modelsim/MainController_8_1200mv_85c_slow.vho +++ b/MainController/simulation/modelsim/MainController_8_1200mv_85c_slow.vho @@ -16,7 +16,7 @@ -- PROGRAM "Quartus II 64-Bit" -- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" --- DATE "03/12/2024 16:24:29" +-- DATE "03/12/2024 17:46:57" -- -- Device: Altera EP3C25Q240C8 Package PQFP240 @@ -37,27 +37,20 @@ ENTITY MainController IS PORT ( FPGA_LED_1 : OUT std_logic; FPGA_CLK : IN std_logic; + FPGA_LED_2 : OUT std_logic; + FPGA_LED_3 : OUT std_logic; Data : INOUT std_logic_vector(7 DOWNTO 0); - Address : IN std_logic_vector(7 DOWNTO 0); - nOE : IN std_logic; nWE : IN std_logic; - nCE : IN std_logic + nOE : IN std_logic; + nCE : IN std_logic; + Address : IN std_logic_vector(7 DOWNTO 0) ); END MainController; -- Design Ports Information -- FPGA_LED_1 => Location: PIN_166, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA --- Address[7] => Location: PIN_195, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[6] => Location: PIN_230, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[5] => Location: PIN_235, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[4] => Location: PIN_232, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[3] => Location: PIN_233, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[2] => Location: PIN_234, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[1] => Location: PIN_231, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[0] => Location: PIN_196, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nOE => Location: PIN_217, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nWE => Location: PIN_218, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nCE => Location: PIN_219, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- FPGA_LED_2 => Location: PIN_167, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +-- FPGA_LED_3 => Location: PIN_168, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[7] => Location: PIN_221, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[6] => Location: PIN_223, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[5] => Location: PIN_224, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -67,6 +60,17 @@ END MainController; -- Data[1] => Location: PIN_189, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[0] => Location: PIN_194, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- FPGA_CLK => Location: PIN_31, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nCE => Location: PIN_219, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nWE => Location: PIN_218, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[0] => Location: PIN_196, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[1] => Location: PIN_231, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[2] => Location: PIN_234, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[3] => Location: PIN_233, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[4] => Location: PIN_232, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[5] => Location: PIN_235, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[6] => Location: PIN_230, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[7] => Location: PIN_195, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nOE => Location: PIN_217, I/O Standard: 3.3-V LVTTL, Current Strength: Default ARCHITECTURE structure OF MainController IS @@ -81,42 +85,152 @@ SIGNAL ww_devclrn : std_logic; SIGNAL ww_devpor : std_logic; SIGNAL ww_FPGA_LED_1 : std_logic; SIGNAL ww_FPGA_CLK : std_logic; -SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0); -SIGNAL ww_nOE : std_logic; +SIGNAL ww_FPGA_LED_2 : std_logic; +SIGNAL ww_FPGA_LED_3 : std_logic; SIGNAL ww_nWE : std_logic; +SIGNAL ww_nOE : std_logic; SIGNAL ww_nCE : std_logic; +SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|pll1_INCLK_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|pll1_CLK_bus\ : std_logic_vector(4 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(35 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(35 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); SIGNAL \FPGA_CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); -SIGNAL \Address[7]~input_o\ : std_logic; -SIGNAL \Address[6]~input_o\ : std_logic; -SIGNAL \Address[5]~input_o\ : std_logic; -SIGNAL \Address[4]~input_o\ : std_logic; -SIGNAL \Address[3]~input_o\ : std_logic; -SIGNAL \Address[2]~input_o\ : std_logic; -SIGNAL \Address[1]~input_o\ : std_logic; -SIGNAL \Address[0]~input_o\ : std_logic; -SIGNAL \nOE~input_o\ : std_logic; -SIGNAL \nWE~input_o\ : std_logic; -SIGNAL \nCE~input_o\ : std_logic; -SIGNAL \Data[7]~input_o\ : std_logic; -SIGNAL \Data[6]~input_o\ : std_logic; -SIGNAL \Data[5]~input_o\ : std_logic; -SIGNAL \Data[4]~input_o\ : std_logic; -SIGNAL \Data[3]~input_o\ : std_logic; -SIGNAL \Data[2]~input_o\ : std_logic; -SIGNAL \Data[1]~input_o\ : std_logic; -SIGNAL \Data[0]~input_o\ : std_logic; -SIGNAL \Data[7]~output_o\ : std_logic; -SIGNAL \Data[6]~output_o\ : std_logic; -SIGNAL \Data[5]~output_o\ : std_logic; -SIGNAL \Data[4]~output_o\ : std_logic; -SIGNAL \Data[3]~output_o\ : std_logic; -SIGNAL \Data[2]~output_o\ : std_logic; -SIGNAL \Data[1]~output_o\ : std_logic; -SIGNAL \Data[0]~output_o\ : std_logic; -SIGNAL \FPGA_LED_1~output_o\ : std_logic; SIGNAL \FPGA_CLK~input_o\ : std_logic; SIGNAL \FPGA_CLK~inputclkctrl_outclk\ : std_logic; +SIGNAL \nCE~input_o\ : std_logic; +SIGNAL \Address[5]~input_o\ : std_logic; +SIGNAL \inst3|ce0Prev~q\ : std_logic; +SIGNAL \inst3|addr~5_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[12]~feeder_combout\ : std_logic; +SIGNAL \nWE~input_o\ : std_logic; +SIGNAL \inst3|we0Prev~q\ : std_logic; +SIGNAL \nOE~input_o\ : std_logic; +SIGNAL \inst3|Selector3~3_combout\ : std_logic; +SIGNAL \inst3|Selector3~2_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Writing~q\ : std_logic; +SIGNAL \inst3|memory~48_combout\ : std_logic; +SIGNAL \inst3|oe0Prev~q\ : std_logic; +SIGNAL \inst3|Selector3~0_combout\ : std_logic; +SIGNAL \inst3|Selector3~1_combout\ : std_logic; +SIGNAL \inst3|Selector2~0_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Waiting~q\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[11]~feeder_combout\ : std_logic; +SIGNAL \Address[4]~input_o\ : std_logic; +SIGNAL \inst3|addr~4_combout\ : std_logic; +SIGNAL \inst3|memory~37_combout\ : std_logic; +SIGNAL \Address[2]~input_o\ : std_logic; +SIGNAL \inst3|addr~2_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[6]~feeder_combout\ : std_logic; +SIGNAL \Address[3]~input_o\ : std_logic; +SIGNAL \inst3|addr~3_combout\ : std_logic; +SIGNAL \inst3|memory~35_combout\ : std_logic; +SIGNAL \Address[0]~input_o\ : std_logic; +SIGNAL \inst3|addr~0_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[2]~feeder_combout\ : std_logic; +SIGNAL \Address[1]~input_o\ : std_logic; +SIGNAL \inst3|addr~1_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[4]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~34_combout\ : std_logic; +SIGNAL \inst3|memory~36_combout\ : std_logic; +SIGNAL \Address[7]~input_o\ : std_logic; +SIGNAL \inst3|addr~7_combout\ : std_logic; +SIGNAL \Address[6]~input_o\ : std_logic; +SIGNAL \inst3|addr~6_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[13]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[16]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~38_combout\ : std_logic; +SIGNAL \inst3|memory~39_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Waiting~_wirecell_combout\ : std_logic; +SIGNAL \Data[0]~input_o\ : std_logic; +SIGNAL \Data[1]~input_o\ : std_logic; +SIGNAL \Data[2]~input_o\ : std_logic; +SIGNAL \Data[3]~input_o\ : std_logic; +SIGNAL \Data[4]~input_o\ : std_logic; +SIGNAL \Data[5]~input_o\ : std_logic; +SIGNAL \Data[6]~input_o\ : std_logic; +SIGNAL \Data[7]~input_o\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[24]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~40_combout\ : std_logic; +SIGNAL \inst3|Selector4~0_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Reading~q\ : std_logic; +SIGNAL \inst3|Selector74~0_combout\ : std_logic; +SIGNAL \inst3|data0[7]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[7]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[7]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[23]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a6\ : std_logic; +SIGNAL \inst3|memory~41_combout\ : std_logic; +SIGNAL \inst3|data0[6]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[6]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[6]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[22]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~42_combout\ : std_logic; +SIGNAL \inst3|data0[5]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[5]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[5]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a4\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[21]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~43_combout\ : std_logic; +SIGNAL \inst3|data0[4]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[4]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[4]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \inst3|memory~44_combout\ : std_logic; +SIGNAL \inst3|data0[3]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[3]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[3]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a2\ : std_logic; +SIGNAL \inst3|memory~45_combout\ : std_logic; +SIGNAL \inst3|data0[2]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[2]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[2]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \inst3|memory~46_combout\ : std_logic; +SIGNAL \inst3|data0[1]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[1]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[1]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \inst3|memory~47_combout\ : std_logic; +SIGNAL \inst3|data0[0]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[0]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[0]~en_q\ : std_logic; SIGNAL \inst2|counter[0]~24_combout\ : std_logic; +SIGNAL \inst2|counter[13]~51\ : std_logic; +SIGNAL \inst2|counter[14]~52_combout\ : std_logic; +SIGNAL \inst2|counter[14]~53\ : std_logic; +SIGNAL \inst2|counter[15]~54_combout\ : std_logic; +SIGNAL \inst2|counter[15]~55\ : std_logic; +SIGNAL \inst2|counter[16]~56_combout\ : std_logic; +SIGNAL \inst2|counter[16]~57\ : std_logic; +SIGNAL \inst2|counter[17]~58_combout\ : std_logic; +SIGNAL \inst2|counter[17]~59\ : std_logic; +SIGNAL \inst2|counter[18]~60_combout\ : std_logic; +SIGNAL \inst2|counter[18]~61\ : std_logic; +SIGNAL \inst2|counter[19]~62_combout\ : std_logic; +SIGNAL \inst2|counter[19]~63\ : std_logic; +SIGNAL \inst2|counter[20]~64_combout\ : std_logic; +SIGNAL \inst2|counter[20]~65\ : std_logic; +SIGNAL \inst2|counter[21]~66_combout\ : std_logic; +SIGNAL \inst2|LessThan0~8_combout\ : std_logic; +SIGNAL \inst2|counter[21]~67\ : std_logic; +SIGNAL \inst2|counter[22]~68_combout\ : std_logic; +SIGNAL \inst2|counter[22]~69\ : std_logic; +SIGNAL \inst2|counter[23]~70_combout\ : std_logic; +SIGNAL \inst2|LessThan0~9_combout\ : std_logic; +SIGNAL \inst2|LessThan0~2_combout\ : std_logic; +SIGNAL \inst2|LessThan0~3_combout\ : std_logic; +SIGNAL \inst2|LessThan0~0_combout\ : std_logic; +SIGNAL \inst2|LessThan0~1_combout\ : std_logic; +SIGNAL \inst2|LessThan0~4_combout\ : std_logic; +SIGNAL \inst2|LessThan0~6_combout\ : std_logic; +SIGNAL \inst2|LessThan0~10_combout\ : std_logic; SIGNAL \inst2|counter[0]~25\ : std_logic; SIGNAL \inst2|counter[1]~26_combout\ : std_logic; SIGNAL \inst2|counter[1]~27\ : std_logic; @@ -143,153 +257,69 @@ SIGNAL \inst2|counter[11]~47\ : std_logic; SIGNAL \inst2|counter[12]~48_combout\ : std_logic; SIGNAL \inst2|counter[12]~49\ : std_logic; SIGNAL \inst2|counter[13]~50_combout\ : std_logic; -SIGNAL \inst2|counter[13]~51\ : std_logic; -SIGNAL \inst2|counter[14]~52_combout\ : std_logic; -SIGNAL \inst2|counter[14]~53\ : std_logic; -SIGNAL \inst2|counter[15]~54_combout\ : std_logic; -SIGNAL \inst2|counter[15]~55\ : std_logic; -SIGNAL \inst2|counter[16]~56_combout\ : std_logic; -SIGNAL \inst2|counter[16]~57\ : std_logic; -SIGNAL \inst2|counter[17]~58_combout\ : std_logic; -SIGNAL \inst2|LessThan0~0_combout\ : std_logic; -SIGNAL \inst2|counter[17]~59\ : std_logic; -SIGNAL \inst2|counter[18]~60_combout\ : std_logic; -SIGNAL \inst2|counter[18]~61\ : std_logic; -SIGNAL \inst2|counter[19]~62_combout\ : std_logic; -SIGNAL \inst2|counter[19]~63\ : std_logic; -SIGNAL \inst2|counter[20]~64_combout\ : std_logic; -SIGNAL \inst2|counter[20]~65\ : std_logic; -SIGNAL \inst2|counter[21]~66_combout\ : std_logic; -SIGNAL \inst2|counter[21]~67\ : std_logic; -SIGNAL \inst2|counter[22]~68_combout\ : std_logic; -SIGNAL \inst2|counter[22]~69\ : std_logic; -SIGNAL \inst2|counter[23]~70_combout\ : std_logic; -SIGNAL \inst2|LessThan0~1_combout\ : std_logic; -SIGNAL \inst2|LessThan0~2_combout\ : std_logic; SIGNAL \inst2|LessThan0~5_combout\ : std_logic; -SIGNAL \inst2|LessThan0~3_combout\ : std_logic; -SIGNAL \inst2|LessThan0~4_combout\ : std_logic; -SIGNAL \inst2|LessThan0~6_combout\ : std_logic; SIGNAL \inst2|LessThan0~7_combout\ : std_logic; -SIGNAL \inst2|LessThan0~8_combout\ : std_logic; SIGNAL \inst2|ledBuf~0_combout\ : std_logic; SIGNAL \inst2|ledBuf~q\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_fbout\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\ : std_logic; +SIGNAL \inst3|addr\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0_bypass\ : std_logic_vector(0 TO 24); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk\ : std_logic_vector(4 DOWNTO 0); SIGNAL \inst2|counter\ : std_logic_vector(23 DOWNTO 0); -SIGNAL \inst2|ALT_INV_LessThan0~8_combout\ : std_logic; +SIGNAL \inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\ : std_logic; +SIGNAL \inst3|ALT_INV_stateMM0.Waiting~q\ : std_logic; SIGNAL \inst2|ALT_INV_ledBuf~q\ : std_logic; BEGIN FPGA_LED_1 <= ww_FPGA_LED_1; ww_FPGA_CLK <= FPGA_CLK; -ww_Address <= Address; -ww_nOE <= nOE; +FPGA_LED_2 <= ww_FPGA_LED_2; +FPGA_LED_3 <= ww_FPGA_LED_3; ww_nWE <= nWE; +ww_nOE <= nOE; ww_nCE <= nCE; +ww_Address <= Address; ww_devoe <= devoe; ww_devclrn <= devclrn; ww_devpor <= devpor; +\inst|altpll_component|auto_generated|pll1_INCLK_bus\ <= (gnd & \FPGA_CLK~input_o\); + +\inst|altpll_component|auto_generated|wire_pll1_clk\(0) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(0); +\inst|altpll_component|auto_generated|wire_pll1_clk\(1) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(1); +\inst|altpll_component|auto_generated|wire_pll1_clk\(2) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(2); +\inst|altpll_component|auto_generated|wire_pll1_clk\(3) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(3); +\inst|altpll_component|auto_generated|wire_pll1_clk\(4) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(4); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & \Data[7]~input_o\ +& \Data[6]~input_o\ & \Data[5]~input_o\ & \Data[4]~input_o\ & \Data[3]~input_o\ & \Data[2]~input_o\ & \Data[1]~input_o\ & \Data[0]~input_o\); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\inst3|addr\(7) & \inst3|addr\(6) & \inst3|addr\(5) & \inst3|addr\(4) & \inst3|addr\(3) & \inst3|addr\(2) & \inst3|addr\(1) & \inst3|addr\(0)); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\inst3|addr~7_combout\ & \inst3|addr~6_combout\ & \inst3|addr~5_combout\ & \inst3|addr~4_combout\ & \inst3|addr~3_combout\ & \inst3|addr~2_combout\ & \inst3|addr~1_combout\ & +\inst3|addr~0_combout\); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\inst3|memory_rtl_0|auto_generated|ram_block1a1\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); +\inst3|memory_rtl_0|auto_generated|ram_block1a2\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2); +\inst3|memory_rtl_0|auto_generated|ram_block1a3\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3); +\inst3|memory_rtl_0|auto_generated|ram_block1a4\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4); +\inst3|memory_rtl_0|auto_generated|ram_block1a5\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5); +\inst3|memory_rtl_0|auto_generated|ram_block1a6\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6); +\inst3|memory_rtl_0|auto_generated|ram_block1a7\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7); + +\inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|altpll_component|auto_generated|wire_pll1_clk\(1)); + +\inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|altpll_component|auto_generated|wire_pll1_clk\(0)); + \FPGA_CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \FPGA_CLK~input_o\); -\inst2|ALT_INV_LessThan0~8_combout\ <= NOT \inst2|LessThan0~8_combout\; +\inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\ <= NOT \inst3|stateMM0.Waiting~_wirecell_combout\; +\inst3|ALT_INV_stateMM0.Waiting~q\ <= NOT \inst3|stateMM0.Waiting~q\; \inst2|ALT_INV_ledBuf~q\ <= NOT \inst2|ledBuf~q\; --- Location: IOOBUF_X18_Y34_N2 -\Data[7]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[7]~output_o\); - --- Location: IOOBUF_X18_Y34_N23 -\Data[6]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[6]~output_o\); - --- Location: IOOBUF_X16_Y34_N2 -\Data[5]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[5]~output_o\); - --- Location: IOOBUF_X16_Y34_N16 -\Data[4]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[4]~output_o\); - --- Location: IOOBUF_X45_Y34_N9 -\Data[3]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[3]~output_o\); - --- Location: IOOBUF_X45_Y34_N16 -\Data[2]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[2]~output_o\); - --- Location: IOOBUF_X45_Y34_N23 -\Data[1]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[1]~output_o\); - --- Location: IOOBUF_X40_Y34_N9 -\Data[0]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[0]~output_o\); - -- Location: IOOBUF_X53_Y22_N2 \FPGA_LED_1~output\ : cycloneiii_io_obuf -- pragma translate_off @@ -300,7 +330,135 @@ GENERIC MAP ( PORT MAP ( i => \inst2|ALT_INV_ledBuf~q\, devoe => ww_devoe, - o => \FPGA_LED_1~output_o\); + o => ww_FPGA_LED_1); + +-- Location: IOOBUF_X53_Y23_N23 +\FPGA_LED_2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\, + devoe => ww_devoe, + o => ww_FPGA_LED_2); + +-- Location: IOOBUF_X53_Y23_N16 +\FPGA_LED_3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\, + devoe => ww_devoe, + o => ww_FPGA_LED_3); + +-- Location: IOOBUF_X18_Y34_N2 +\Data[7]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[7]~reg0_q\, + oe => \inst3|data0[7]~en_q\, + devoe => ww_devoe, + o => Data(7)); + +-- Location: IOOBUF_X18_Y34_N23 +\Data[6]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[6]~reg0_q\, + oe => \inst3|data0[6]~en_q\, + devoe => ww_devoe, + o => Data(6)); + +-- Location: IOOBUF_X16_Y34_N2 +\Data[5]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[5]~reg0_q\, + oe => \inst3|data0[5]~en_q\, + devoe => ww_devoe, + o => Data(5)); + +-- Location: IOOBUF_X16_Y34_N16 +\Data[4]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[4]~reg0_q\, + oe => \inst3|data0[4]~en_q\, + devoe => ww_devoe, + o => Data(4)); + +-- Location: IOOBUF_X45_Y34_N9 +\Data[3]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[3]~reg0_q\, + oe => \inst3|data0[3]~en_q\, + devoe => ww_devoe, + o => Data(3)); + +-- Location: IOOBUF_X45_Y34_N16 +\Data[2]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[2]~reg0_q\, + oe => \inst3|data0[2]~en_q\, + devoe => ww_devoe, + o => Data(2)); + +-- Location: IOOBUF_X45_Y34_N23 +\Data[1]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[1]~reg0_q\, + oe => \inst3|data0[1]~en_q\, + devoe => ww_devoe, + o => Data(1)); + +-- Location: IOOBUF_X40_Y34_N9 +\Data[0]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[0]~reg0_q\, + oe => \inst3|data0[0]~en_q\, + devoe => ww_devoe, + o => Data(0)); -- Location: IOIBUF_X0_Y16_N1 \FPGA_CLK~input\ : cycloneiii_io_ibuf @@ -313,7 +471,7 @@ PORT MAP ( i => ww_FPGA_CLK, o => \FPGA_CLK~input_o\); --- Location: CLKCTRL_G4 +-- Location: CLKCTRL_G2 \FPGA_CLK~inputclkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( @@ -326,7 +484,1858 @@ PORT MAP ( devpor => ww_devpor, outclk => \FPGA_CLK~inputclkctrl_outclk\); --- Location: LCCOMB_X51_Y14_N8 +-- Location: IOIBUF_X20_Y34_N15 +\nCE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nCE, + o => \nCE~input_o\); + +-- Location: IOIBUF_X7_Y34_N15 +\Address[5]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(5), + o => \Address[5]~input_o\); + +-- Location: FF_X27_Y29_N31 +\inst3|ce0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nCE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|ce0Prev~q\); + +-- Location: LCCOMB_X34_Y24_N26 +\inst3|addr~5\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~5_combout\ = (!\nCE~input_o\ & (\Address[5]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[5]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~5_combout\); + +-- Location: LCCOMB_X32_Y23_N12 +\inst3|memory_rtl_0_bypass[12]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[12]~feeder_combout\ = \inst3|addr~5_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~5_combout\, + combout => \inst3|memory_rtl_0_bypass[12]~feeder_combout\); + +-- Location: IOIBUF_X20_Y34_N8 +\nWE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nWE, + o => \nWE~input_o\); + +-- Location: FF_X27_Y29_N21 +\inst3|we0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nWE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|we0Prev~q\); + +-- Location: IOIBUF_X20_Y34_N1 +\nOE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nOE, + o => \nOE~input_o\); + +-- Location: LCCOMB_X27_Y29_N14 +\inst3|Selector3~3\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~3_combout\ = (\nOE~input_o\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\ & !\inst3|stateMM0.Waiting~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector3~3_combout\); + +-- Location: LCCOMB_X27_Y29_N30 +\inst3|Selector3~2\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~2_combout\ = (\inst3|stateMM0.Waiting~q\ & (((\inst3|Selector3~1_combout\)))) # (!\inst3|stateMM0.Waiting~q\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011101000010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|stateMM0.Waiting~q\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|Selector3~1_combout\, + combout => \inst3|Selector3~2_combout\); + +-- Location: FF_X27_Y29_N15 +\inst3|stateMM0.Writing\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector3~3_combout\, + ena => \inst3|Selector3~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Writing~q\); + +-- Location: LCCOMB_X27_Y29_N20 +\inst3|memory~48\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~48_combout\ = (!\nWE~input_o\ & (\inst3|we0Prev~q\ & \inst3|stateMM0.Writing~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nWE~input_o\, + datac => \inst3|we0Prev~q\, + datad => \inst3|stateMM0.Writing~q\, + combout => \inst3|memory~48_combout\); + +-- Location: FF_X27_Y29_N25 +\inst3|oe0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nOE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|oe0Prev~q\); + +-- Location: LCCOMB_X27_Y29_N24 +\inst3|Selector3~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~0_combout\ = (\nOE~input_o\ & (!\inst3|oe0Prev~q\ & !\inst3|stateMM0.Writing~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datac => \inst3|oe0Prev~q\, + datad => \inst3|stateMM0.Writing~q\, + combout => \inst3|Selector3~0_combout\); + +-- Location: LCCOMB_X27_Y29_N2 +\inst3|Selector3~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~1_combout\ = (\inst3|memory~48_combout\) # ((\nCE~input_o\) # (\inst3|Selector3~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111101110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory~48_combout\, + datab => \nCE~input_o\, + datad => \inst3|Selector3~0_combout\, + combout => \inst3|Selector3~1_combout\); + +-- Location: LCCOMB_X27_Y29_N8 +\inst3|Selector2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector2~0_combout\ = (\inst3|stateMM0.Waiting~q\ & (((!\inst3|Selector3~1_combout\)))) # (!\inst3|stateMM0.Waiting~q\ & (\inst3|ce0Prev~q\ & (!\nCE~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000001011110010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datac => \inst3|stateMM0.Waiting~q\, + datad => \inst3|Selector3~1_combout\, + combout => \inst3|Selector2~0_combout\); + +-- Location: FF_X27_Y29_N9 +\inst3|stateMM0.Waiting\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Waiting~q\); + +-- Location: FF_X32_Y23_N13 +\inst3|memory_rtl_0_bypass[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[12]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(12)); + +-- Location: FF_X34_Y24_N27 +\inst3|addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~5_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(5)); + +-- Location: LCCOMB_X32_Y23_N2 +\inst3|memory_rtl_0_bypass[11]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[11]~feeder_combout\ = \inst3|addr\(5) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr\(5), + combout => \inst3|memory_rtl_0_bypass[11]~feeder_combout\); + +-- Location: FF_X32_Y23_N3 +\inst3|memory_rtl_0_bypass[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[11]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(11)); + +-- Location: IOIBUF_X14_Y34_N22 +\Address[4]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(4), + o => \Address[4]~input_o\); + +-- Location: LCCOMB_X34_Y24_N0 +\inst3|addr~4\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~4_combout\ = (!\nCE~input_o\ & (\Address[4]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[4]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~4_combout\); + +-- Location: FF_X32_Y23_N7 +\inst3|memory_rtl_0_bypass[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~4_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(10)); + +-- Location: FF_X34_Y24_N1 +\inst3|addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~4_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(4)); + +-- Location: FF_X32_Y23_N1 +\inst3|memory_rtl_0_bypass[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(4), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(9)); + +-- Location: LCCOMB_X32_Y23_N6 +\inst3|memory~37\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~37_combout\ = (\inst3|memory_rtl_0_bypass\(12) & (\inst3|memory_rtl_0_bypass\(11) & (\inst3|memory_rtl_0_bypass\(10) $ (!\inst3|memory_rtl_0_bypass\(9))))) # (!\inst3|memory_rtl_0_bypass\(12) & (!\inst3|memory_rtl_0_bypass\(11) & +-- (\inst3|memory_rtl_0_bypass\(10) $ (!\inst3|memory_rtl_0_bypass\(9))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001000000001001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(12), + datab => \inst3|memory_rtl_0_bypass\(11), + datac => \inst3|memory_rtl_0_bypass\(10), + datad => \inst3|memory_rtl_0_bypass\(9), + combout => \inst3|memory~37_combout\); + +-- Location: IOIBUF_X7_Y34_N8 +\Address[2]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(2), + o => \Address[2]~input_o\); + +-- Location: LCCOMB_X34_Y24_N12 +\inst3|addr~2\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~2_combout\ = (!\nCE~input_o\ & (\Address[2]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[2]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~2_combout\); + +-- Location: LCCOMB_X34_Y24_N14 +\inst3|memory_rtl_0_bypass[6]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[6]~feeder_combout\ = \inst3|addr~2_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~2_combout\, + combout => \inst3|memory_rtl_0_bypass[6]~feeder_combout\); + +-- Location: FF_X34_Y24_N15 +\inst3|memory_rtl_0_bypass[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[6]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(6)); + +-- Location: IOIBUF_X7_Y34_N1 +\Address[3]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(3), + o => \Address[3]~input_o\); + +-- Location: LCCOMB_X34_Y24_N30 +\inst3|addr~3\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~3_combout\ = (\inst3|ce0Prev~q\ & (\Address[3]~input_o\ & !\nCE~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \Address[3]~input_o\, + datad => \nCE~input_o\, + combout => \inst3|addr~3_combout\); + +-- Location: FF_X34_Y24_N31 +\inst3|addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~3_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(3)); + +-- Location: FF_X27_Y29_N1 +\inst3|memory_rtl_0_bypass[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(3), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(7)); + +-- Location: FF_X34_Y24_N13 +\inst3|addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~2_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(2)); + +-- Location: FF_X27_Y29_N23 +\inst3|memory_rtl_0_bypass[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(2), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(5)); + +-- Location: FF_X34_Y24_N5 +\inst3|memory_rtl_0_bypass[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~3_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(8)); + +-- Location: LCCOMB_X27_Y29_N22 +\inst3|memory~35\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~35_combout\ = (\inst3|memory_rtl_0_bypass\(6) & (\inst3|memory_rtl_0_bypass\(5) & (\inst3|memory_rtl_0_bypass\(7) $ (!\inst3|memory_rtl_0_bypass\(8))))) # (!\inst3|memory_rtl_0_bypass\(6) & (!\inst3|memory_rtl_0_bypass\(5) & +-- (\inst3|memory_rtl_0_bypass\(7) $ (!\inst3|memory_rtl_0_bypass\(8))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(6), + datab => \inst3|memory_rtl_0_bypass\(7), + datac => \inst3|memory_rtl_0_bypass\(5), + datad => \inst3|memory_rtl_0_bypass\(8), + combout => \inst3|memory~35_combout\); + +-- Location: IOIBUF_X38_Y34_N15 +\Address[0]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(0), + o => \Address[0]~input_o\); + +-- Location: LCCOMB_X34_Y24_N24 +\inst3|addr~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~0_combout\ = (\inst3|ce0Prev~q\ & (!\nCE~input_o\ & \Address[0]~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datac => \Address[0]~input_o\, + combout => \inst3|addr~0_combout\); + +-- Location: LCCOMB_X34_Y24_N18 +\inst3|memory_rtl_0_bypass[2]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[2]~feeder_combout\ = \inst3|addr~0_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~0_combout\, + combout => \inst3|memory_rtl_0_bypass[2]~feeder_combout\); + +-- Location: FF_X34_Y24_N19 +\inst3|memory_rtl_0_bypass[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[2]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(2)); + +-- Location: IOIBUF_X14_Y34_N15 +\Address[1]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(1), + o => \Address[1]~input_o\); + +-- Location: LCCOMB_X34_Y24_N2 +\inst3|addr~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~1_combout\ = (\Address[1]~input_o\ & (!\nCE~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \Address[1]~input_o\, + datab => \nCE~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~1_combout\); + +-- Location: FF_X34_Y24_N3 +\inst3|addr[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~1_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(1)); + +-- Location: FF_X27_Y29_N29 +\inst3|memory_rtl_0_bypass[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(1), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(3)); + +-- Location: FF_X34_Y24_N25 +\inst3|addr[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~0_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(0)); + +-- Location: FF_X27_Y29_N11 +\inst3|memory_rtl_0_bypass[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(0), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(1)); + +-- Location: LCCOMB_X34_Y24_N16 +\inst3|memory_rtl_0_bypass[4]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[4]~feeder_combout\ = \inst3|addr~1_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~1_combout\, + combout => \inst3|memory_rtl_0_bypass[4]~feeder_combout\); + +-- Location: FF_X34_Y24_N17 +\inst3|memory_rtl_0_bypass[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[4]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(4)); + +-- Location: LCCOMB_X27_Y29_N10 +\inst3|memory~34\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~34_combout\ = (\inst3|memory_rtl_0_bypass\(2) & (\inst3|memory_rtl_0_bypass\(1) & (\inst3|memory_rtl_0_bypass\(3) $ (!\inst3|memory_rtl_0_bypass\(4))))) # (!\inst3|memory_rtl_0_bypass\(2) & (!\inst3|memory_rtl_0_bypass\(1) & +-- (\inst3|memory_rtl_0_bypass\(3) $ (!\inst3|memory_rtl_0_bypass\(4))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(2), + datab => \inst3|memory_rtl_0_bypass\(3), + datac => \inst3|memory_rtl_0_bypass\(1), + datad => \inst3|memory_rtl_0_bypass\(4), + combout => \inst3|memory~34_combout\); + +-- Location: LCCOMB_X27_Y29_N18 +\inst3|memory~36\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~36_combout\ = (\inst3|memory~35_combout\ & \inst3|memory~34_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datac => \inst3|memory~35_combout\, + datad => \inst3|memory~34_combout\, + combout => \inst3|memory~36_combout\); + +-- Location: FF_X27_Y29_N17 +\inst3|memory_rtl_0_bypass[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|memory~48_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(0)); + +-- Location: IOIBUF_X38_Y34_N1 +\Address[7]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(7), + o => \Address[7]~input_o\); + +-- Location: LCCOMB_X34_Y24_N22 +\inst3|addr~7\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~7_combout\ = (\inst3|ce0Prev~q\ & (!\nCE~input_o\ & \Address[7]~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datad => \Address[7]~input_o\, + combout => \inst3|addr~7_combout\); + +-- Location: FF_X34_Y24_N23 +\inst3|addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~7_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(7)); + +-- Location: FF_X34_Y24_N11 +\inst3|memory_rtl_0_bypass[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(7), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(15)); + +-- Location: IOIBUF_X14_Y34_N8 +\Address[6]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(6), + o => \Address[6]~input_o\); + +-- Location: LCCOMB_X34_Y24_N20 +\inst3|addr~6\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~6_combout\ = (\Address[6]~input_o\ & (!\nCE~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \Address[6]~input_o\, + datab => \nCE~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~6_combout\); + +-- Location: FF_X34_Y24_N21 +\inst3|addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~6_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(6)); + +-- Location: LCCOMB_X34_Y24_N8 +\inst3|memory_rtl_0_bypass[13]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[13]~feeder_combout\ = \inst3|addr\(6) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr\(6), + combout => \inst3|memory_rtl_0_bypass[13]~feeder_combout\); + +-- Location: FF_X34_Y24_N9 +\inst3|memory_rtl_0_bypass[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[13]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(13)); + +-- Location: FF_X34_Y24_N7 +\inst3|memory_rtl_0_bypass[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~6_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(14)); + +-- Location: LCCOMB_X34_Y24_N28 +\inst3|memory_rtl_0_bypass[16]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[16]~feeder_combout\ = \inst3|addr~7_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~7_combout\, + combout => \inst3|memory_rtl_0_bypass[16]~feeder_combout\); + +-- Location: FF_X34_Y24_N29 +\inst3|memory_rtl_0_bypass[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[16]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(16)); + +-- Location: LCCOMB_X34_Y24_N6 +\inst3|memory~38\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~38_combout\ = (\inst3|memory_rtl_0_bypass\(15) & (\inst3|memory_rtl_0_bypass\(16) & (\inst3|memory_rtl_0_bypass\(13) $ (!\inst3|memory_rtl_0_bypass\(14))))) # (!\inst3|memory_rtl_0_bypass\(15) & (!\inst3|memory_rtl_0_bypass\(16) & +-- (\inst3|memory_rtl_0_bypass\(13) $ (!\inst3|memory_rtl_0_bypass\(14))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000001001000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(15), + datab => \inst3|memory_rtl_0_bypass\(13), + datac => \inst3|memory_rtl_0_bypass\(14), + datad => \inst3|memory_rtl_0_bypass\(16), + combout => \inst3|memory~38_combout\); + +-- Location: LCCOMB_X27_Y29_N16 +\inst3|memory~39\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~39_combout\ = (\inst3|memory~37_combout\ & (\inst3|memory~36_combout\ & (\inst3|memory_rtl_0_bypass\(0) & \inst3|memory~38_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory~37_combout\, + datab => \inst3|memory~36_combout\, + datac => \inst3|memory_rtl_0_bypass\(0), + datad => \inst3|memory~38_combout\, + combout => \inst3|memory~39_combout\); + +-- Location: LCCOMB_X35_Y33_N24 +\inst3|stateMM0.Waiting~_wirecell\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|stateMM0.Waiting~_wirecell_combout\ = !\inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000011111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|stateMM0.Waiting~_wirecell_combout\); + +-- Location: IOIBUF_X40_Y34_N8 +\Data[0]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(0), + o => \Data[0]~input_o\); + +-- Location: IOIBUF_X45_Y34_N22 +\Data[1]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(1), + o => \Data[1]~input_o\); + +-- Location: IOIBUF_X45_Y34_N15 +\Data[2]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(2), + o => \Data[2]~input_o\); + +-- Location: IOIBUF_X45_Y34_N8 +\Data[3]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(3), + o => \Data[3]~input_o\); + +-- Location: IOIBUF_X16_Y34_N15 +\Data[4]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(4), + o => \Data[4]~input_o\); + +-- Location: IOIBUF_X16_Y34_N1 +\Data[5]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(5), + o => \Data[5]~input_o\); + +-- Location: IOIBUF_X18_Y34_N22 +\Data[6]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(6), + o => \Data[6]~input_o\); + +-- Location: IOIBUF_X18_Y34_N1 +\Data[7]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(7), + o => \Data[7]~input_o\); + +-- Location: M9K_X33_Y29_N0 +\inst3|memory_rtl_0|auto_generated|ram_block1a0\ : cycloneiii_ram_block +-- pragma translate_off +GENERIC MAP ( + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + logical_ram_name => "RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 8, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 36, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 255, + port_a_logical_ram_depth => 256, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_with_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 8, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 36, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 255, + port_b_logical_ram_depth => 256, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_with_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M9K") +-- pragma translate_on +PORT MAP ( + portawe => \inst3|memory~48_combout\, + portbre => VCC, + portbaddrstall => \inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\, + clk0 => \FPGA_CLK~inputclkctrl_outclk\, + portadatain => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LCCOMB_X35_Y29_N24 +\inst3|memory_rtl_0_bypass[24]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[24]~feeder_combout\ = \Data[7]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[7]~input_o\, + combout => \inst3|memory_rtl_0_bypass[24]~feeder_combout\); + +-- Location: FF_X35_Y29_N25 +\inst3|memory_rtl_0_bypass[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[24]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(24)); + +-- Location: LCCOMB_X35_Y29_N0 +\inst3|memory~40\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~40_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(24)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a7\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a7\, + datad => \inst3|memory_rtl_0_bypass\(24), + combout => \inst3|memory~40_combout\); + +-- Location: LCCOMB_X27_Y29_N12 +\inst3|Selector4~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector4~0_combout\ = (!\nOE~input_o\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\ & !\inst3|stateMM0.Waiting~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector4~0_combout\); + +-- Location: FF_X27_Y29_N13 +\inst3|stateMM0.Reading\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector4~0_combout\, + ena => \inst3|Selector3~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Reading~q\); + +-- Location: LCCOMB_X27_Y29_N26 +\inst3|Selector74~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector74~0_combout\ = (\inst3|stateMM0.Reading~q\) # ((!\inst3|stateMM0.Waiting~q\ & ((\nCE~input_o\) # (!\inst3|ce0Prev~q\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010101011101111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|stateMM0.Reading~q\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector74~0_combout\); + +-- Location: FF_X35_Y29_N1 +\inst3|data0[7]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~40_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[7]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N16 +\inst3|data0[7]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[7]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[7]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N17 +\inst3|data0[7]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[7]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[7]~en_q\); + +-- Location: LCCOMB_X35_Y29_N26 +\inst3|memory_rtl_0_bypass[23]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[23]~feeder_combout\ = \Data[6]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[6]~input_o\, + combout => \inst3|memory_rtl_0_bypass[23]~feeder_combout\); + +-- Location: FF_X35_Y29_N27 +\inst3|memory_rtl_0_bypass[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[23]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(23)); + +-- Location: LCCOMB_X35_Y29_N18 +\inst3|memory~41\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~41_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(23))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a6\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011100010111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(23), + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a6\, + combout => \inst3|memory~41_combout\); + +-- Location: FF_X35_Y29_N19 +\inst3|data0[6]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~41_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[6]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N18 +\inst3|data0[6]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[6]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[6]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N19 +\inst3|data0[6]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[6]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[6]~en_q\); + +-- Location: LCCOMB_X35_Y29_N28 +\inst3|memory_rtl_0_bypass[22]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[22]~feeder_combout\ = \Data[5]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[5]~input_o\, + combout => \inst3|memory_rtl_0_bypass[22]~feeder_combout\); + +-- Location: FF_X35_Y29_N29 +\inst3|memory_rtl_0_bypass[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[22]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(22)); + +-- Location: LCCOMB_X35_Y29_N20 +\inst3|memory~42\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~42_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(22)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a5\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101000001010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0|auto_generated|ram_block1a5\, + datac => \inst3|memory~39_combout\, + datad => \inst3|memory_rtl_0_bypass\(22), + combout => \inst3|memory~42_combout\); + +-- Location: FF_X35_Y29_N21 +\inst3|data0[5]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~42_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[5]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N4 +\inst3|data0[5]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[5]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[5]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N5 +\inst3|data0[5]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[5]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[5]~en_q\); + +-- Location: LCCOMB_X35_Y29_N14 +\inst3|memory_rtl_0_bypass[21]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[21]~feeder_combout\ = \Data[4]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[4]~input_o\, + combout => \inst3|memory_rtl_0_bypass[21]~feeder_combout\); + +-- Location: FF_X35_Y29_N15 +\inst3|memory_rtl_0_bypass[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[21]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(21)); + +-- Location: LCCOMB_X35_Y29_N30 +\inst3|memory~43\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~43_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(21)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a4\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110001011100010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0|auto_generated|ram_block1a4\, + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0_bypass\(21), + combout => \inst3|memory~43_combout\); + +-- Location: FF_X35_Y29_N31 +\inst3|data0[4]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~43_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[4]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N6 +\inst3|data0[4]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[4]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[4]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N7 +\inst3|data0[4]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[4]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[4]~en_q\); + +-- Location: FF_X35_Y29_N9 +\inst3|memory_rtl_0_bypass[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[3]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(20)); + +-- Location: LCCOMB_X35_Y29_N16 +\inst3|memory~44\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~44_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(20))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a3\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111001111000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0_bypass\(20), + datad => \inst3|memory_rtl_0|auto_generated|ram_block1a3\, + combout => \inst3|memory~44_combout\); + +-- Location: FF_X35_Y29_N17 +\inst3|data0[3]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~44_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[3]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N8 +\inst3|data0[3]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[3]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[3]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N9 +\inst3|data0[3]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[3]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[3]~en_q\); + +-- Location: FF_X35_Y29_N11 +\inst3|memory_rtl_0_bypass[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[2]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(19)); + +-- Location: LCCOMB_X35_Y29_N2 +\inst3|memory~45\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~45_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(19)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a2\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a2\, + datad => \inst3|memory_rtl_0_bypass\(19), + combout => \inst3|memory~45_combout\); + +-- Location: FF_X35_Y29_N3 +\inst3|data0[2]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~45_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[2]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N2 +\inst3|data0[2]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[2]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[2]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N3 +\inst3|data0[2]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[2]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[2]~en_q\); + +-- Location: FF_X35_Y29_N13 +\inst3|memory_rtl_0_bypass[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[1]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(18)); + +-- Location: LCCOMB_X35_Y29_N4 +\inst3|memory~46\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~46_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(18)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a1\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a1\, + datad => \inst3|memory_rtl_0_bypass\(18), + combout => \inst3|memory~46_combout\); + +-- Location: FF_X35_Y29_N5 +\inst3|data0[1]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~46_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[1]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N20 +\inst3|data0[1]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[1]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[1]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N21 +\inst3|data0[1]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[1]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[1]~en_q\); + +-- Location: FF_X35_Y29_N23 +\inst3|memory_rtl_0_bypass[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[0]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(17)); + +-- Location: LCCOMB_X35_Y29_N6 +\inst3|memory~47\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~47_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(17))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011100010111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(17), + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\, + combout => \inst3|memory~47_combout\); + +-- Location: FF_X35_Y29_N7 +\inst3|data0[0]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~47_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[0]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N22 +\inst3|data0[0]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[0]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[0]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N23 +\inst3|data0[0]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[0]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[0]~en_q\); + +-- Location: LCCOMB_X26_Y29_N8 \inst2|counter[0]~24\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[0]~24_combout\ = \inst2|counter\(0) $ (VCC) @@ -334,427 +2343,16 @@ PORT MAP ( -- pragma translate_off GENERIC MAP ( - lut_mask => "0101010110101010", + lut_mask => "0011001111001100", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(0), + datab => \inst2|counter\(0), datad => VCC, combout => \inst2|counter[0]~24_combout\, cout => \inst2|counter[0]~25\); --- Location: FF_X51_Y14_N9 -\inst2|counter[0]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[0]~24_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(0)); - --- Location: LCCOMB_X51_Y14_N10 -\inst2|counter[1]~26\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND))) --- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(1), - datad => VCC, - cin => \inst2|counter[0]~25\, - combout => \inst2|counter[1]~26_combout\, - cout => \inst2|counter[1]~27\); - --- Location: FF_X51_Y14_N11 -\inst2|counter[1]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[1]~26_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(1)); - --- Location: LCCOMB_X51_Y14_N12 -\inst2|counter[2]~28\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC)) --- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(2), - datad => VCC, - cin => \inst2|counter[1]~27\, - combout => \inst2|counter[2]~28_combout\, - cout => \inst2|counter[2]~29\); - --- Location: FF_X51_Y14_N13 -\inst2|counter[2]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[2]~28_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(2)); - --- Location: LCCOMB_X51_Y14_N14 -\inst2|counter[3]~30\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND))) --- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(3), - datad => VCC, - cin => \inst2|counter[2]~29\, - combout => \inst2|counter[3]~30_combout\, - cout => \inst2|counter[3]~31\); - --- Location: FF_X51_Y14_N15 -\inst2|counter[3]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[3]~30_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(3)); - --- Location: LCCOMB_X51_Y14_N16 -\inst2|counter[4]~32\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC)) --- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1010010100001010", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(4), - datad => VCC, - cin => \inst2|counter[3]~31\, - combout => \inst2|counter[4]~32_combout\, - cout => \inst2|counter[4]~33\); - --- Location: FF_X51_Y14_N17 -\inst2|counter[4]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[4]~32_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(4)); - --- Location: LCCOMB_X51_Y14_N18 -\inst2|counter[5]~34\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND))) --- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(5), - datad => VCC, - cin => \inst2|counter[4]~33\, - combout => \inst2|counter[5]~34_combout\, - cout => \inst2|counter[5]~35\); - --- Location: FF_X51_Y14_N19 -\inst2|counter[5]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[5]~34_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(5)); - --- Location: LCCOMB_X51_Y14_N20 -\inst2|counter[6]~36\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC)) --- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(6), - datad => VCC, - cin => \inst2|counter[5]~35\, - combout => \inst2|counter[6]~36_combout\, - cout => \inst2|counter[6]~37\); - --- Location: FF_X51_Y14_N21 -\inst2|counter[6]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[6]~36_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(6)); - --- Location: LCCOMB_X51_Y14_N22 -\inst2|counter[7]~38\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND))) --- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(7), - datad => VCC, - cin => \inst2|counter[6]~37\, - combout => \inst2|counter[7]~38_combout\, - cout => \inst2|counter[7]~39\); - --- Location: FF_X51_Y14_N23 -\inst2|counter[7]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[7]~38_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(7)); - --- Location: LCCOMB_X51_Y14_N24 -\inst2|counter[8]~40\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC)) --- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(8), - datad => VCC, - cin => \inst2|counter[7]~39\, - combout => \inst2|counter[8]~40_combout\, - cout => \inst2|counter[8]~41\); - --- Location: FF_X51_Y14_N25 -\inst2|counter[8]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[8]~40_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(8)); - --- Location: LCCOMB_X51_Y14_N26 -\inst2|counter[9]~42\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND))) --- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0101101001011111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(9), - datad => VCC, - cin => \inst2|counter[8]~41\, - combout => \inst2|counter[9]~42_combout\, - cout => \inst2|counter[9]~43\); - --- Location: FF_X51_Y14_N27 -\inst2|counter[9]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[9]~42_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(9)); - --- Location: LCCOMB_X51_Y14_N28 -\inst2|counter[10]~44\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC)) --- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(10), - datad => VCC, - cin => \inst2|counter[9]~43\, - combout => \inst2|counter[10]~44_combout\, - cout => \inst2|counter[10]~45\); - --- Location: FF_X51_Y14_N29 -\inst2|counter[10]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[10]~44_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(10)); - --- Location: LCCOMB_X51_Y14_N30 -\inst2|counter[11]~46\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND))) --- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0101101001011111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(11), - datad => VCC, - cin => \inst2|counter[10]~45\, - combout => \inst2|counter[11]~46_combout\, - cout => \inst2|counter[11]~47\); - --- Location: FF_X51_Y14_N31 -\inst2|counter[11]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[11]~46_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(11)); - --- Location: LCCOMB_X51_Y13_N0 -\inst2|counter[12]~48\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC)) --- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(12), - datad => VCC, - cin => \inst2|counter[11]~47\, - combout => \inst2|counter[12]~48_combout\, - cout => \inst2|counter[12]~49\); - --- Location: FF_X51_Y13_N1 -\inst2|counter[12]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[12]~48_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(12)); - --- Location: LCCOMB_X51_Y13_N2 +-- Location: LCCOMB_X26_Y28_N2 \inst2|counter[13]~50\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[13]~50_combout\ = (\inst2|counter\(13) & (!\inst2|counter[12]~49\)) # (!\inst2|counter\(13) & ((\inst2|counter[12]~49\) # (GND))) @@ -772,22 +2370,7 @@ PORT MAP ( combout => \inst2|counter[13]~50_combout\, cout => \inst2|counter[13]~51\); --- Location: FF_X51_Y13_N3 -\inst2|counter[13]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[13]~50_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(13)); - --- Location: LCCOMB_X51_Y13_N4 +-- Location: LCCOMB_X26_Y28_N4 \inst2|counter[14]~52\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[14]~52_combout\ = (\inst2|counter\(14) & (\inst2|counter[13]~51\ $ (GND))) # (!\inst2|counter\(14) & (!\inst2|counter[13]~51\ & VCC)) @@ -805,7 +2388,7 @@ PORT MAP ( combout => \inst2|counter[14]~52_combout\, cout => \inst2|counter[14]~53\); --- Location: FF_X51_Y13_N5 +-- Location: FF_X26_Y28_N5 \inst2|counter[14]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -815,12 +2398,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[14]~52_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(14)); --- Location: LCCOMB_X51_Y13_N6 +-- Location: LCCOMB_X26_Y28_N6 \inst2|counter[15]~54\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[15]~54_combout\ = (\inst2|counter\(15) & (!\inst2|counter[14]~53\)) # (!\inst2|counter\(15) & ((\inst2|counter[14]~53\) # (GND))) @@ -838,7 +2421,7 @@ PORT MAP ( combout => \inst2|counter[15]~54_combout\, cout => \inst2|counter[15]~55\); --- Location: FF_X51_Y13_N7 +-- Location: FF_X26_Y28_N7 \inst2|counter[15]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -848,12 +2431,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[15]~54_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(15)); --- Location: LCCOMB_X51_Y13_N8 +-- Location: LCCOMB_X26_Y28_N8 \inst2|counter[16]~56\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[16]~56_combout\ = (\inst2|counter\(16) & (\inst2|counter[15]~55\ $ (GND))) # (!\inst2|counter\(16) & (!\inst2|counter[15]~55\ & VCC)) @@ -871,7 +2454,7 @@ PORT MAP ( combout => \inst2|counter[16]~56_combout\, cout => \inst2|counter[16]~57\); --- Location: FF_X51_Y13_N9 +-- Location: FF_X26_Y28_N9 \inst2|counter[16]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -881,12 +2464,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[16]~56_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(16)); --- Location: LCCOMB_X51_Y13_N10 +-- Location: LCCOMB_X26_Y28_N10 \inst2|counter[17]~58\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[17]~58_combout\ = (\inst2|counter\(17) & (!\inst2|counter[16]~57\)) # (!\inst2|counter\(17) & ((\inst2|counter[16]~57\) # (GND))) @@ -904,7 +2487,7 @@ PORT MAP ( combout => \inst2|counter[17]~58_combout\, cout => \inst2|counter[17]~59\); --- Location: FF_X51_Y13_N11 +-- Location: FF_X26_Y28_N11 \inst2|counter[17]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -914,29 +2497,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[17]~58_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(17)); --- Location: LCCOMB_X50_Y13_N20 -\inst2|LessThan0~0\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~0_combout\ = ((!\inst2|counter\(15) & (!\inst2|counter\(16) & !\inst2|counter\(14)))) # (!\inst2|counter\(17)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0000111100011111", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(15), - datab => \inst2|counter\(16), - datac => \inst2|counter\(17), - datad => \inst2|counter\(14), - combout => \inst2|LessThan0~0_combout\); - --- Location: LCCOMB_X51_Y13_N12 +-- Location: LCCOMB_X26_Y28_N12 \inst2|counter[18]~60\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[18]~60_combout\ = (\inst2|counter\(18) & (\inst2|counter[17]~59\ $ (GND))) # (!\inst2|counter\(18) & (!\inst2|counter[17]~59\ & VCC)) @@ -954,7 +2520,7 @@ PORT MAP ( combout => \inst2|counter[18]~60_combout\, cout => \inst2|counter[18]~61\); --- Location: FF_X51_Y13_N13 +-- Location: FF_X26_Y28_N13 \inst2|counter[18]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -964,12 +2530,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[18]~60_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(18)); --- Location: LCCOMB_X51_Y13_N14 +-- Location: LCCOMB_X26_Y28_N14 \inst2|counter[19]~62\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[19]~62_combout\ = (\inst2|counter\(19) & (!\inst2|counter[18]~61\)) # (!\inst2|counter\(19) & ((\inst2|counter[18]~61\) # (GND))) @@ -987,7 +2553,7 @@ PORT MAP ( combout => \inst2|counter[19]~62_combout\, cout => \inst2|counter[19]~63\); --- Location: FF_X51_Y13_N15 +-- Location: FF_X26_Y28_N15 \inst2|counter[19]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -997,12 +2563,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[19]~62_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(19)); --- Location: LCCOMB_X51_Y13_N16 +-- Location: LCCOMB_X26_Y28_N16 \inst2|counter[20]~64\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[20]~64_combout\ = (\inst2|counter\(20) & (\inst2|counter[19]~63\ $ (GND))) # (!\inst2|counter\(20) & (!\inst2|counter[19]~63\ & VCC)) @@ -1020,7 +2586,7 @@ PORT MAP ( combout => \inst2|counter[20]~64_combout\, cout => \inst2|counter[20]~65\); --- Location: FF_X51_Y13_N17 +-- Location: FF_X26_Y28_N17 \inst2|counter[20]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1030,12 +2596,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[20]~64_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(20)); --- Location: LCCOMB_X51_Y13_N18 +-- Location: LCCOMB_X26_Y28_N18 \inst2|counter[21]~66\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[21]~66_combout\ = (\inst2|counter\(21) & (!\inst2|counter[20]~65\)) # (!\inst2|counter\(21) & ((\inst2|counter[20]~65\) # (GND))) @@ -1053,7 +2619,7 @@ PORT MAP ( combout => \inst2|counter[21]~66_combout\, cout => \inst2|counter[21]~67\); --- Location: FF_X51_Y13_N19 +-- Location: FF_X26_Y28_N19 \inst2|counter[21]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1063,12 +2629,29 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[21]~66_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(21)); --- Location: LCCOMB_X51_Y13_N20 +-- Location: LCCOMB_X26_Y28_N26 +\inst2|LessThan0~8\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~8_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0111111111111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(18), + datab => \inst2|counter\(20), + datac => \inst2|counter\(19), + datad => \inst2|counter\(21), + combout => \inst2|LessThan0~8_combout\); + +-- Location: LCCOMB_X26_Y28_N20 \inst2|counter[22]~68\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[22]~68_combout\ = (\inst2|counter\(22) & (\inst2|counter[21]~67\ $ (GND))) # (!\inst2|counter\(22) & (!\inst2|counter[21]~67\ & VCC)) @@ -1086,7 +2669,7 @@ PORT MAP ( combout => \inst2|counter[22]~68_combout\, cout => \inst2|counter[22]~69\); --- Location: FF_X51_Y13_N21 +-- Location: FF_X26_Y28_N21 \inst2|counter[22]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1096,12 +2679,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[22]~68_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(22)); --- Location: LCCOMB_X51_Y13_N22 +-- Location: LCCOMB_X26_Y28_N22 \inst2|counter[23]~70\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[23]~70_combout\ = \inst2|counter\(23) $ (\inst2|counter[22]~69\) @@ -1116,7 +2699,7 @@ PORT MAP ( cin => \inst2|counter[22]~69\, combout => \inst2|counter[23]~70_combout\); --- Location: FF_X51_Y13_N23 +-- Location: FF_X26_Y28_N23 \inst2|counter[23]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1126,48 +2709,31 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[23]~70_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(23)); --- Location: LCCOMB_X51_Y13_N24 -\inst2|LessThan0~1\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y28_N28 +\inst2|LessThan0~9\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~1_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18)) +-- \inst2|LessThan0~9_combout\ = (\inst2|LessThan0~8_combout\) # ((!\inst2|counter\(22)) # (!\inst2|counter\(23))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0111111111111111", + lut_mask => "1010111111111111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(18), - datab => \inst2|counter\(20), - datac => \inst2|counter\(19), - datad => \inst2|counter\(21), - combout => \inst2|LessThan0~1_combout\); + dataa => \inst2|LessThan0~8_combout\, + datac => \inst2|counter\(23), + datad => \inst2|counter\(22), + combout => \inst2|LessThan0~9_combout\); --- Location: LCCOMB_X51_Y13_N30 +-- Location: LCCOMB_X25_Y23_N18 \inst2|LessThan0~2\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~2_combout\ = ((\inst2|LessThan0~1_combout\) # (!\inst2|counter\(23))) # (!\inst2|counter\(22)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1111111100111111", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(22), - datac => \inst2|counter\(23), - datad => \inst2|LessThan0~1_combout\, - combout => \inst2|LessThan0~2_combout\); - --- Location: LCCOMB_X51_Y14_N4 -\inst2|LessThan0~5\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(9) & (!\inst2|counter\(8) & (!\inst2|counter\(7) & !\inst2|counter\(10)))) +-- \inst2|LessThan0~2_combout\ = (!\inst2|counter\(13) & (!\inst2|counter\(16) & (!\inst2|counter\(15) & !\inst2|counter\(6)))) -- pragma translate_off GENERIC MAP ( @@ -1175,113 +2741,590 @@ GENERIC MAP ( sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(9), - datab => \inst2|counter\(8), - datac => \inst2|counter\(7), - datad => \inst2|counter\(10), - combout => \inst2|LessThan0~5_combout\); + dataa => \inst2|counter\(13), + datab => \inst2|counter\(16), + datac => \inst2|counter\(15), + datad => \inst2|counter\(6), + combout => \inst2|LessThan0~2_combout\); --- Location: LCCOMB_X51_Y14_N0 +-- Location: LCCOMB_X26_Y29_N4 \inst2|LessThan0~3\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(2) & (!\inst2|counter\(4) & ((!\inst2|counter\(1)) # (!\inst2|counter\(0))))) +-- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(7) & (!\inst2|counter\(10) & (!\inst2|counter\(9) & !\inst2|counter\(8)))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000000100010001", + lut_mask => "0000000000000001", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(2), - datab => \inst2|counter\(4), - datac => \inst2|counter\(0), - datad => \inst2|counter\(1), + dataa => \inst2|counter\(7), + datab => \inst2|counter\(10), + datac => \inst2|counter\(9), + datad => \inst2|counter\(8), combout => \inst2|LessThan0~3_combout\); --- Location: LCCOMB_X51_Y14_N6 -\inst2|LessThan0~4\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y29_N0 +\inst2|LessThan0~0\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~4_combout\ = ((\inst2|LessThan0~3_combout\) # ((!\inst2|counter\(4) & !\inst2|counter\(3)))) # (!\inst2|counter\(5)) +-- \inst2|LessThan0~0_combout\ = (!\inst2|counter\(4) & (!\inst2|counter\(2) & ((!\inst2|counter\(0)) # (!\inst2|counter\(1))))) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111111100110111", + lut_mask => "0000000000010011", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(1), + datab => \inst2|counter\(4), + datac => \inst2|counter\(0), + datad => \inst2|counter\(2), + combout => \inst2|LessThan0~0_combout\); + +-- Location: LCCOMB_X26_Y29_N2 +\inst2|LessThan0~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~1_combout\ = (\inst2|LessThan0~0_combout\) # (((!\inst2|counter\(4) & !\inst2|counter\(3))) # (!\inst2|counter\(5))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100110111111111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( dataa => \inst2|counter\(4), - datab => \inst2|counter\(5), + datab => \inst2|LessThan0~0_combout\, datac => \inst2|counter\(3), - datad => \inst2|LessThan0~3_combout\, - combout => \inst2|LessThan0~4_combout\); + datad => \inst2|counter\(5), + combout => \inst2|LessThan0~1_combout\); --- Location: LCCOMB_X51_Y14_N2 -\inst2|LessThan0~6\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y29_N6 +\inst2|LessThan0~4\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~6_combout\ = (!\inst2|counter\(11) & (!\inst2|counter\(6) & (\inst2|LessThan0~5_combout\ & \inst2|LessThan0~4_combout\))) +-- \inst2|LessThan0~4_combout\ = (!\inst2|counter\(11) & (\inst2|LessThan0~2_combout\ & (\inst2|LessThan0~3_combout\ & \inst2|LessThan0~1_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0001000000000000", + lut_mask => "0100000000000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( dataa => \inst2|counter\(11), - datab => \inst2|counter\(6), - datac => \inst2|LessThan0~5_combout\, - datad => \inst2|LessThan0~4_combout\, - combout => \inst2|LessThan0~6_combout\); + datab => \inst2|LessThan0~2_combout\, + datac => \inst2|LessThan0~3_combout\, + datad => \inst2|LessThan0~1_combout\, + combout => \inst2|LessThan0~4_combout\); --- Location: LCCOMB_X51_Y13_N28 -\inst2|LessThan0~7\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y28_N24 +\inst2|LessThan0~6\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~7_combout\ = (\inst2|counter\(16)) # ((\inst2|counter\(13)) # ((\inst2|counter\(12) & !\inst2|LessThan0~6_combout\))) +-- \inst2|LessThan0~6_combout\ = ((!\inst2|counter\(14) & (!\inst2|counter\(16) & !\inst2|counter\(15)))) # (!\inst2|counter\(17)) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111101011111110", + lut_mask => "0101010101010111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(16), + dataa => \inst2|counter\(17), + datab => \inst2|counter\(14), + datac => \inst2|counter\(16), + datad => \inst2|counter\(15), + combout => \inst2|LessThan0~6_combout\); + +-- Location: LCCOMB_X26_Y28_N30 +\inst2|LessThan0~10\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~10_combout\ = (!\inst2|LessThan0~5_combout\ & (!\inst2|LessThan0~9_combout\ & (!\inst2|LessThan0~4_combout\ & !\inst2|LessThan0~6_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|LessThan0~5_combout\, + datab => \inst2|LessThan0~9_combout\, + datac => \inst2|LessThan0~4_combout\, + datad => \inst2|LessThan0~6_combout\, + combout => \inst2|LessThan0~10_combout\); + +-- Location: FF_X26_Y29_N9 +\inst2|counter[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[0]~24_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(0)); + +-- Location: LCCOMB_X26_Y29_N10 +\inst2|counter[1]~26\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND))) +-- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(1), + datad => VCC, + cin => \inst2|counter[0]~25\, + combout => \inst2|counter[1]~26_combout\, + cout => \inst2|counter[1]~27\); + +-- Location: FF_X26_Y29_N11 +\inst2|counter[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[1]~26_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(1)); + +-- Location: LCCOMB_X26_Y29_N12 +\inst2|counter[2]~28\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC)) +-- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010100001010", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(2), + datad => VCC, + cin => \inst2|counter[1]~27\, + combout => \inst2|counter[2]~28_combout\, + cout => \inst2|counter[2]~29\); + +-- Location: FF_X26_Y29_N13 +\inst2|counter[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[2]~28_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(2)); + +-- Location: LCCOMB_X26_Y29_N14 +\inst2|counter[3]~30\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND))) +-- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(3), + datad => VCC, + cin => \inst2|counter[2]~29\, + combout => \inst2|counter[3]~30_combout\, + cout => \inst2|counter[3]~31\); + +-- Location: FF_X26_Y29_N15 +\inst2|counter[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[3]~30_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(3)); + +-- Location: LCCOMB_X26_Y29_N16 +\inst2|counter[4]~32\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC)) +-- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(4), + datad => VCC, + cin => \inst2|counter[3]~31\, + combout => \inst2|counter[4]~32_combout\, + cout => \inst2|counter[4]~33\); + +-- Location: FF_X26_Y29_N17 +\inst2|counter[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[4]~32_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(4)); + +-- Location: LCCOMB_X26_Y29_N18 +\inst2|counter[5]~34\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND))) +-- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(5), + datad => VCC, + cin => \inst2|counter[4]~33\, + combout => \inst2|counter[5]~34_combout\, + cout => \inst2|counter[5]~35\); + +-- Location: FF_X26_Y29_N19 +\inst2|counter[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[5]~34_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(5)); + +-- Location: LCCOMB_X26_Y29_N20 +\inst2|counter[6]~36\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC)) +-- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(6), + datad => VCC, + cin => \inst2|counter[5]~35\, + combout => \inst2|counter[6]~36_combout\, + cout => \inst2|counter[6]~37\); + +-- Location: FF_X26_Y29_N21 +\inst2|counter[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[6]~36_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(6)); + +-- Location: LCCOMB_X26_Y29_N22 +\inst2|counter[7]~38\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND))) +-- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(7), + datad => VCC, + cin => \inst2|counter[6]~37\, + combout => \inst2|counter[7]~38_combout\, + cout => \inst2|counter[7]~39\); + +-- Location: FF_X26_Y29_N23 +\inst2|counter[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[7]~38_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(7)); + +-- Location: LCCOMB_X26_Y29_N24 +\inst2|counter[8]~40\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC)) +-- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(8), + datad => VCC, + cin => \inst2|counter[7]~39\, + combout => \inst2|counter[8]~40_combout\, + cout => \inst2|counter[8]~41\); + +-- Location: FF_X26_Y29_N25 +\inst2|counter[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[8]~40_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(8)); + +-- Location: LCCOMB_X26_Y29_N26 +\inst2|counter[9]~42\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND))) +-- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(9), + datad => VCC, + cin => \inst2|counter[8]~41\, + combout => \inst2|counter[9]~42_combout\, + cout => \inst2|counter[9]~43\); + +-- Location: FF_X26_Y29_N27 +\inst2|counter[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[9]~42_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(9)); + +-- Location: LCCOMB_X26_Y29_N28 +\inst2|counter[10]~44\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC)) +-- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(10), + datad => VCC, + cin => \inst2|counter[9]~43\, + combout => \inst2|counter[10]~44_combout\, + cout => \inst2|counter[10]~45\); + +-- Location: FF_X26_Y29_N29 +\inst2|counter[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[10]~44_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(10)); + +-- Location: LCCOMB_X26_Y29_N30 +\inst2|counter[11]~46\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND))) +-- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(11), + datad => VCC, + cin => \inst2|counter[10]~45\, + combout => \inst2|counter[11]~46_combout\, + cout => \inst2|counter[11]~47\); + +-- Location: FF_X26_Y29_N31 +\inst2|counter[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[11]~46_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(11)); + +-- Location: LCCOMB_X26_Y28_N0 +\inst2|counter[12]~48\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC)) +-- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( datab => \inst2|counter\(12), - datac => \inst2|counter\(13), + datad => VCC, + cin => \inst2|counter[11]~47\, + combout => \inst2|counter[12]~48_combout\, + cout => \inst2|counter[12]~49\); + +-- Location: FF_X26_Y28_N1 +\inst2|counter[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[12]~48_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(12)); + +-- Location: FF_X26_Y28_N3 +\inst2|counter[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[13]~50_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(13)); + +-- Location: LCCOMB_X25_Y23_N4 +\inst2|LessThan0~5\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(13) & (!\inst2|counter\(15) & (!\inst2|counter\(12) & !\inst2|counter\(16)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(13), + datab => \inst2|counter\(15), + datac => \inst2|counter\(12), + datad => \inst2|counter\(16), + combout => \inst2|LessThan0~5_combout\); + +-- Location: LCCOMB_X25_Y23_N6 +\inst2|LessThan0~7\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~7_combout\ = (\inst2|LessThan0~5_combout\) # (\inst2|LessThan0~6_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datac => \inst2|LessThan0~5_combout\, datad => \inst2|LessThan0~6_combout\, combout => \inst2|LessThan0~7_combout\); --- Location: LCCOMB_X51_Y13_N26 -\inst2|LessThan0~8\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~8_combout\ = (\inst2|LessThan0~0_combout\) # ((\inst2|LessThan0~2_combout\) # ((!\inst2|counter\(15) & !\inst2|LessThan0~7_combout\))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1111110011111101", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(15), - datab => \inst2|LessThan0~0_combout\, - datac => \inst2|LessThan0~2_combout\, - datad => \inst2|LessThan0~7_combout\, - combout => \inst2|LessThan0~8_combout\); - --- Location: LCCOMB_X52_Y13_N0 +-- Location: LCCOMB_X25_Y23_N8 \inst2|ledBuf~0\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (!\inst2|LessThan0~8_combout\) +-- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (((!\inst2|LessThan0~7_combout\ & (!\inst2|LessThan0~9_combout\ & !\inst2|LessThan0~4_combout\)))) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111000000001111", + lut_mask => "1111000011100001", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( + dataa => \inst2|LessThan0~7_combout\, + datab => \inst2|LessThan0~9_combout\, datac => \inst2|ledBuf~q\, - datad => \inst2|LessThan0~8_combout\, + datad => \inst2|LessThan0~4_combout\, combout => \inst2|ledBuf~0_combout\); --- Location: FF_X52_Y13_N1 +-- Location: FF_X25_Y23_N9 \inst2|ledBuf\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1295,232 +3338,124 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|ledBuf~q\); --- Location: IOIBUF_X38_Y34_N1 -\Address[7]~input\ : cycloneiii_io_ibuf +-- Location: PLL_1 +\inst|altpll_component|auto_generated|pll1\ : cycloneiii_pll -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + auto_settings => "false", + bandwidth_type => "medium", + c0_high => 3, + c0_initial => 1, + c0_low => 3, + c0_mode => "even", + c0_ph => 0, + c1_high => 2, + c1_initial => 1, + c1_low => 1, + c1_mode => "odd", + c1_ph => 0, + c1_use_casc_in => "off", + c2_high => 0, + c2_initial => 0, + c2_low => 0, + c2_mode => "bypass", + c2_ph => 0, + c2_use_casc_in => "off", + c3_high => 0, + c3_initial => 0, + c3_low => 0, + c3_mode => "bypass", + c3_ph => 0, + c3_use_casc_in => "off", + c4_high => 0, + c4_initial => 0, + c4_low => 0, + c4_mode => "bypass", + c4_ph => 0, + c4_use_casc_in => "off", + charge_pump_current_bits => 1, + clk0_counter => "c0", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 4, + clk0_phase_shift => "0", + clk1_counter => "c1", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 8, + clk1_phase_shift => "0", + clk2_counter => "unused", + clk2_divide_by => 0, + clk2_duty_cycle => 50, + clk2_multiply_by => 0, + clk2_phase_shift => "0", + clk3_counter => "unused", + clk3_divide_by => 0, + clk3_duty_cycle => 50, + clk3_multiply_by => 0, + clk3_phase_shift => "0", + clk4_counter => "unused", + clk4_divide_by => 0, + clk4_duty_cycle => 50, + clk4_multiply_by => 0, + clk4_phase_shift => "0", + compensate_clock => "clock0", + inclk0_input_frequency => 40000, + inclk1_input_frequency => 0, + loop_filter_c_bits => 0, + loop_filter_r_bits => 24, + m => 24, + m_initial => 1, + m_ph => 0, + n => 1, + operation_mode => "normal", + pfd_max => 200000, + pfd_min => 3076, + pll_compensation_delay => 7057, + self_reset_on_loss_lock => "off", + simulation_type => "timing", + switch_over_type => "auto", + vco_center => 1538, + vco_divide_by => 0, + vco_frequency_control => "auto", + vco_max => 3333, + vco_min => 1538, + vco_multiply_by => 0, + vco_phase_shift_step => 208, + vco_post_scale => 2) -- pragma translate_on PORT MAP ( - i => ww_Address(7), - o => \Address[7]~input_o\); + areset => GND, + fbin => \inst|altpll_component|auto_generated|wire_pll1_fbout\, + inclk => \inst|altpll_component|auto_generated|pll1_INCLK_bus\, + fbout => \inst|altpll_component|auto_generated|wire_pll1_fbout\, + clk => \inst|altpll_component|auto_generated|pll1_CLK_bus\); --- Location: IOIBUF_X14_Y34_N8 -\Address[6]~input\ : cycloneiii_io_ibuf +-- Location: CLKCTRL_G3 +\inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + clock_type => "global clock", + ena_register_mode => "none") -- pragma translate_on PORT MAP ( - i => ww_Address(6), - o => \Address[6]~input_o\); + inclk => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\); --- Location: IOIBUF_X7_Y34_N15 -\Address[5]~input\ : cycloneiii_io_ibuf +-- Location: CLKCTRL_G4 +\inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + clock_type => "global clock", + ena_register_mode => "none") -- pragma translate_on PORT MAP ( - i => ww_Address(5), - o => \Address[5]~input_o\); - --- Location: IOIBUF_X14_Y34_N22 -\Address[4]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(4), - o => \Address[4]~input_o\); - --- Location: IOIBUF_X7_Y34_N1 -\Address[3]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(3), - o => \Address[3]~input_o\); - --- Location: IOIBUF_X7_Y34_N8 -\Address[2]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(2), - o => \Address[2]~input_o\); - --- Location: IOIBUF_X14_Y34_N15 -\Address[1]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(1), - o => \Address[1]~input_o\); - --- Location: IOIBUF_X38_Y34_N15 -\Address[0]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(0), - o => \Address[0]~input_o\); - --- Location: IOIBUF_X20_Y34_N1 -\nOE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nOE, - o => \nOE~input_o\); - --- Location: IOIBUF_X20_Y34_N8 -\nWE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nWE, - o => \nWE~input_o\); - --- Location: IOIBUF_X20_Y34_N15 -\nCE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nCE, - o => \nCE~input_o\); - --- Location: IOIBUF_X18_Y34_N1 -\Data[7]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(7), - o => \Data[7]~input_o\); - --- Location: IOIBUF_X18_Y34_N22 -\Data[6]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(6), - o => \Data[6]~input_o\); - --- Location: IOIBUF_X16_Y34_N1 -\Data[5]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(5), - o => \Data[5]~input_o\); - --- Location: IOIBUF_X16_Y34_N15 -\Data[4]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(4), - o => \Data[4]~input_o\); - --- Location: IOIBUF_X45_Y34_N8 -\Data[3]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(3), - o => \Data[3]~input_o\); - --- Location: IOIBUF_X45_Y34_N15 -\Data[2]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(2), - o => \Data[2]~input_o\); - --- Location: IOIBUF_X45_Y34_N22 -\Data[1]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(1), - o => \Data[1]~input_o\); - --- Location: IOIBUF_X40_Y34_N8 -\Data[0]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(0), - o => \Data[0]~input_o\); - -ww_FPGA_LED_1 <= \FPGA_LED_1~output_o\; - -Data(7) <= \Data[7]~output_o\; - -Data(6) <= \Data[6]~output_o\; - -Data(5) <= \Data[5]~output_o\; - -Data(4) <= \Data[4]~output_o\; - -Data(3) <= \Data[3]~output_o\; - -Data(2) <= \Data[2]~output_o\; - -Data(1) <= \Data[1]~output_o\; - -Data(0) <= \Data[0]~output_o\; + inclk => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\); END structure; diff --git a/MainController/simulation/modelsim/MainController_8_1200mv_85c_vhd_slow.sdo b/MainController/simulation/modelsim/MainController_8_1200mv_85c_vhd_slow.sdo index 7a8f05c..a6b5c76 100644 --- a/MainController/simulation/modelsim/MainController_8_1200mv_85c_vhd_slow.sdo +++ b/MainController/simulation/modelsim/MainController_8_1200mv_85c_vhd_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "MainController") - (DATE "03/12/2024 16:24:29") + (DATE "03/12/2024 17:46:57") (VENDOR "Altera") (PROGRAM "Quartus II 64-Bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version") @@ -41,11 +41,127 @@ (INSTANCE \\FPGA_LED_1\~output\\) (DELAY (ABSOLUTE - (PORT i (1403:1403:1403) (1502:1502:1502)) + (PORT i (2032:2032:2032) (2189:2189:2189)) (IOPATH i o (2195:2195:2195) (2297:2297:2297)) ) ) ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\FPGA_LED_2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1600:1600:1600) (1590:1590:1590)) + (IOPATH i o (2466:2466:2466) (2351:2351:2351)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\FPGA_LED_3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1599:1599:1599) (1589:1589:1589)) + (IOPATH i o (2466:2466:2466) (2351:2351:2351)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[7\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1926:1926:1926) (1856:1856:1856)) + (PORT oe (2010:2010:2010) (1825:1825:1825)) + (IOPATH i o (2337:2337:2337) (2218:2218:2218)) + (IOPATH oe o (2571:2571:2571) (2571:2571:2571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[6\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1625:1625:1625) (1582:1582:1582)) + (PORT oe (1891:1891:1891) (1792:1792:1792)) + (IOPATH i o (4562:4562:4562) (4088:4088:4088)) + (IOPATH oe o (2571:2571:2571) (2571:2571:2571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[5\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (2637:2637:2637) (2438:2438:2438)) + (PORT oe (2269:2269:2269) (2130:2130:2130)) + (IOPATH i o (2337:2337:2337) (2218:2218:2218)) + (IOPATH oe o (2571:2571:2571) (2571:2571:2571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[4\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (2755:2755:2755) (2596:2596:2596)) + (PORT oe (2242:2242:2242) (2111:2111:2111)) + (IOPATH i o (2337:2337:2337) (2218:2218:2218)) + (IOPATH oe o (2571:2571:2571) (2571:2571:2571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[3\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1679:1679:1679) (1497:1497:1497)) + (PORT oe (1608:1608:1608) (1396:1396:1396)) + (IOPATH i o (2357:2357:2357) (2238:2238:2238)) + (IOPATH oe o (2591:2591:2591) (2591:2591:2591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[2\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1761:1761:1761) (1621:1621:1621)) + (PORT oe (1565:1565:1565) (1376:1376:1376)) + (IOPATH i o (2357:2357:2357) (2238:2238:2238)) + (IOPATH oe o (2591:2591:2591) (2591:2591:2591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[1\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1646:1646:1646) (1479:1479:1479)) + (PORT oe (1622:1622:1622) (1415:1415:1415)) + (IOPATH i o (2357:2357:2357) (2238:2238:2238)) + (IOPATH oe o (2591:2591:2591) (2591:2591:2591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[0\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1382:1382:1382) (1258:1258:1258)) + (PORT oe (1275:1275:1275) (1149:1149:1149)) + (IOPATH i o (2347:2347:2347) (2228:2228:2228)) + (IOPATH oe o (2581:2581:2581) (2581:2581:2581)) + ) + ) + ) (CELL (CELLTYPE "cycloneiii_io_ibuf") (INSTANCE \\FPGA_CLK\~input\\) @@ -64,394 +180,1818 @@ ) ) ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nCE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (895:895:895) (1014:1014:1014)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[5\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|ce0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT asdata (4980:4980:4980) (5188:5188:5188)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~5\\) + (DELAY + (ABSOLUTE + (PORT datab (4266:4266:4266) (4538:4538:4538)) + (PORT datac (4497:4497:4497) (4683:4683:4683)) + (PORT datad (1924:1924:1924) (1827:1827:1827)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[12\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1184:1184:1184) (1079:1079:1079)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nWE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (895:895:895) (1014:1014:1014)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|we0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT asdata (4449:4449:4449) (4593:4593:4593)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nOE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (895:895:895) (1014:1014:1014)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~3\\) + (DELAY + (ABSOLUTE + (PORT dataa (4145:4145:4145) (4366:4366:4366)) + (PORT datab (4567:4567:4567) (4770:4770:4770)) + (PORT datac (347:347:347) (442:442:442)) + (PORT datad (609:609:609) (649:649:649)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~2\\) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (703:703:703)) + (PORT datab (4569:4569:4569) (4772:4772:4772)) + (PORT datad (250:250:250) (271:271:271)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Writing\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1614:1614:1614) (1508:1508:1508)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~48\\) + (DELAY + (ABSOLUTE + (PORT datab (4026:4026:4026) (4176:4176:4176)) + (PORT datad (566:566:566) (590:590:590)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|oe0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT asdata (5065:5065:5065) (5258:5258:5258)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (4662:4662:4662) (4851:4851:4851)) + (PORT datad (567:567:567) (588:588:588)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (566:566:566)) + (PORT datab (4564:4564:4564) (4766:4766:4766)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (490:490:490)) + (PORT datab (4564:4564:4564) (4767:4767:4767)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Waiting\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[12\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1927:1927:1927) (1935:1935:1935)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3893:3893:3893) (4125:4125:4125)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[11\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1285:1285:1285) (1219:1219:1219)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[11\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1927:1927:1927) (1935:1935:1935)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[4\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~4\\) + (DELAY + (ABSOLUTE + (PORT datab (4267:4267:4267) (4544:4544:4544)) + (PORT datac (4204:4204:4204) (4476:4476:4476)) + (PORT datad (1918:1918:1918) (1819:1819:1819)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[10\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1927:1927:1927) (1935:1935:1935)) + (PORT asdata (1674:1674:1674) (1561:1561:1561)) + (PORT ena (3893:3893:3893) (4125:4125:4125)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[9\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1927:1927:1927) (1935:1935:1935)) + (PORT asdata (1746:1746:1746) (1673:1673:1673)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~37\\) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (418:418:418)) + (PORT datab (332:332:332) (408:408:408)) + (PORT datad (293:293:293) (362:362:362)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[2\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~2\\) + (DELAY + (ABSOLUTE + (PORT datab (4266:4266:4266) (4543:4543:4543)) + (PORT datac (4524:4524:4524) (4768:4768:4768)) + (PORT datad (1921:1921:1921) (1825:1825:1825)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[6\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (265:265:265) (283:283:283)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[6\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[3\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~3\\) + (DELAY + (ABSOLUTE + (PORT dataa (1969:1969:1969) (1882:1882:1882)) + (PORT datab (4509:4509:4509) (4715:4715:4715)) + (PORT datad (4204:4204:4204) (4488:4488:4488)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[7\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT asdata (2506:2506:2506) (2334:2334:2334)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT asdata (2463:2463:2463) (2297:2297:2297)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL 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(1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1968:1968:1968) (1879:1879:1879)) + (PORT datab (4265:4265:4265) (4539:4539:4539)) + (PORT datac (4087:4087:4087) (4222:4222:4222)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[2\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (264:264:264) (282:282:282)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[1\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (915:915:915) (1034:1034:1034)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (4274:4274:4274) (4526:4526:4526)) + (PORT datab (4267:4267:4267) (4543:4543:4543)) + (PORT datad (1917:1917:1917) (1819:1819:1819)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT asdata (2520:2520:2520) (2469:2469:2469)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT asdata (2392:2392:2392) (2243:2243:2243)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[4\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (265:265:265) (284:284:284)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~34\\) + (DELAY + (ABSOLUTE + (PORT dataa (1936:1936:1936) (1804:1804:1804)) + (PORT datab (333:333:333) (411:411:411)) + (PORT datad (1885:1885:1885) (1755:1755:1755)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~36\\) + (DELAY + (ABSOLUTE + (PORT datac (236:236:236) (263:263:263)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT asdata (1001:1001:1001) (976:976:976)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[7\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~7\\) + (DELAY + (ABSOLUTE + (PORT dataa (1967:1967:1967) (1879:1879:1879)) + (PORT datab (4265:4265:4265) (4540:4540:4540)) + (PORT datad (4059:4059:4059) (4281:4281:4281)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[7\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[15\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT asdata (786:786:786) (858:858:858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[6\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (915:915:915) (1034:1034:1034)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~6\\) + (DELAY + (ABSOLUTE + (PORT dataa (4227:4227:4227) (4475:4475:4475)) + (PORT datab (4266:4266:4266) (4544:4544:4544)) + (PORT datad (1923:1923:1923) (1827:1827:1827)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[6\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[13\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (323:323:323) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[13\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[14\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT asdata (924:924:924) (889:889:889)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[16\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (446:446:446) (423:423:423)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[16\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~38\\) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (418:418:418)) + (PORT datab (331:331:331) (408:408:408)) + (PORT datad (296:296:296) (364:364:364)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~39\\) + (DELAY + (ABSOLUTE + (PORT dataa (1551:1551:1551) (1402:1402:1402)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datad (1872:1872:1872) (1686:1686:1686)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|stateMM0\.Waiting\~_wirecell\\) + (DELAY + (ABSOLUTE + (PORT datad (1604:1604:1604) (1529:1529:1529)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[0\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (915:915:915) (1034:1034:1034)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[1\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[2\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[3\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[4\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[5\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[6\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[7\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4089:4089:4089) (4246:4246:4246)) + (PORT d[1] (4233:4233:4233) (4465:4465:4465)) + (PORT d[2] (4554:4554:4554) (4747:4747:4747)) + (PORT d[3] (4519:4519:4519) (4714:4714:4714)) + (PORT d[4] (4201:4201:4201) (4435:4435:4435)) + (PORT d[5] (4207:4207:4207) (4456:4456:4456)) + (PORT d[6] (4201:4201:4201) (4436:4436:4436)) + (PORT d[7] (4528:4528:4528) (4710:4710:4710)) + (PORT clk (2347:2347:2347) (2373:2373:2373)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2095:2095:2095) (1969:1969:1969)) + (PORT d[1] (2159:2159:2159) (2022:2022:2022)) + (PORT d[2] (1656:1656:1656) (1566:1566:1566)) + (PORT d[3] (2146:2146:2146) (2029:2029:2029)) + (PORT d[4] (1569:1569:1569) (1474:1474:1474)) + (PORT d[5] (1426:1426:1426) (1386:1386:1386)) + (PORT d[6] (2045:2045:2045) (1899:1899:1899)) + (PORT d[7] (1718:1718:1718) (1611:1611:1611)) + (PORT clk (2343:2343:2343) (2368:2368:2368)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1544:1544:1544) (1368:1368:1368)) + (PORT clk (2343:2343:2343) (2368:2368:2368)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2347:2347:2347) (2373:2373:2373)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (3798:3798:3798) (3824:3824:3824)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2348:2348:2348) (2374:2374:2374)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2348:2348:2348) (2374:2374:2374)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2348:2348:2348) (2374:2374:2374)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1324:1324:1324) (1224:1224:1224)) + (PORT d[1] (1379:1379:1379) (1286:1286:1286)) + (PORT d[2] (1363:1363:1363) (1259:1259:1259)) + (PORT d[3] (1357:1357:1357) (1262:1262:1262)) + (PORT d[4] (1286:1286:1286) (1179:1179:1179)) + (PORT d[5] (1660:1660:1660) (1537:1537:1537)) + (PORT d[6] (1311:1311:1311) (1215:1215:1215)) + (PORT d[7] (1278:1278:1278) (1189:1189:1189)) + (PORT clk (2345:2345:2345) (2370:2370:2370)) + (PORT stall (1538:1538:1538) (1703:1703:1703)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2345:2345:2345) (2370:2370:2370)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2346:2346:2346) (2371:2371:2371)) + (IOPATH (posedge clk) pulse (0:0:0) (3251:3251:3251)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2346:2346:2346) (2371:2371:2371)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2346:2346:2346) (2371:2371:2371)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[24\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (4102:4102:4102) (4331:4331:4331)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[24\]\\) + (DELAY + (ABSOLUTE + (PORT clk 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(IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Reading\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1614:1614:1614) (1508:1508:1508)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector74\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (421:421:421)) + (PORT datab (4568:4568:4568) (4771:4771:4771)) + (PORT datac (342:342:342) (437:437:437)) + (PORT datad (607:607:607) (647:647:647)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[7\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[7\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1605:1605:1605) (1529:1529:1529)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[7\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1943:1943:1943)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3021:3021:3021) (2829:2829:2829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) 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\\inst3\|memory_rtl_0_bypass\[20\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT asdata (4587:4587:4587) (4803:4803:4803)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~44\\) + (DELAY + (ABSOLUTE + (PORT datab (1230:1230:1230) (1140:1140:1140)) + (PORT datac (296:296:296) (375:375:375)) + (PORT datad (809:809:809) (714:714:714)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[3\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD 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(212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~45\\) + (DELAY + (ABSOLUTE + (PORT datab (1229:1229:1229) (1140:1140:1140)) + (PORT datac (747:747:747) (664:664:664)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[2\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[2\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1600:1600:1600) (1522:1522:1522)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[2\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1943:1943:1943)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3021:3021:3021) (2829:2829:2829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[18\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT asdata (4618:4618:4618) (4837:4837:4837)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~46\\) + (DELAY + (ABSOLUTE + (PORT datab (1229:1229:1229) (1138:1138:1138)) + (PORT datac (736:736:736) (653:653:653)) + (PORT datad (296:296:296) (365:365:365)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[1\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[1\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1603:1603:1603) (1532:1532:1532)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[1\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1943:1943:1943)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3021:3021:3021) (2829:2829:2829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[17\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT asdata (4384:4384:4384) (4529:4529:4529)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~47\\) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datab (1228:1228:1228) (1139:1139:1139)) + (PORT datac (781:781:781) (698:698:698)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[0\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[0\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1605:1605:1605) (1530:1530:1530)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[0\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1943:1943:1943)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3021:3021:3021) (2829:2829:2829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[0\]\~24\\) (DELAY (ABSOLUTE - (PORT dataa (567:567:567) (600:600:600)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[0\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[1\]\~26\\) - (DELAY - (ABSOLUTE - (PORT datab (576:576:576) (592:592:592)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[1\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[2\]\~28\\) - (DELAY - (ABSOLUTE - (PORT datab (566:566:566) (594:594:594)) + (PORT datab (341:341:341) (422:422:422)) (IOPATH datab combout (472:472:472) (473:473:473)) (IOPATH datab cout (565:565:565) (421:421:421)) (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[2\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[3\]\~30\\) - (DELAY - (ABSOLUTE - (PORT datab (343:343:343) (423:423:423)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[3\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2413:2413:2413)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[4\]\~32\\) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (615:615:615)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[4\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[5\]\~34\\) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (425:425:425)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[5\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[6\]\~36\\) - (DELAY - (ABSOLUTE - (PORT datab (341:341:341) (425:425:425)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[6\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2413:2413:2413)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[7\]\~38\\) - (DELAY - (ABSOLUTE - (PORT datab (561:561:561) (592:592:592)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[7\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[8\]\~40\\) - (DELAY - (ABSOLUTE - (PORT datab (341:341:341) (423:423:423)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[8\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[9\]\~42\\) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (434:434:434)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[9\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[10\]\~44\\) - (DELAY - (ABSOLUTE - (PORT datab (341:341:341) (421:421:421)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[10\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2413:2413:2413)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[11\]\~46\\) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (434:434:434)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[11\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2413:2413:2413)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[12\]\~48\\) - (DELAY - (ABSOLUTE - (PORT datab (340:340:340) (422:422:422)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[12\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[13\]\~50\\) @@ -466,28 +2006,12 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[13\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[14\]\~52\\) (DELAY (ABSOLUTE - (PORT datab (358:358:358) (435:435:435)) + (PORT datab (341:341:341) (423:423:423)) (IOPATH datab combout (472:472:472) (473:473:473)) (IOPATH datab cout (565:565:565) (421:421:421)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -501,9 +2025,9 @@ (INSTANCE \\inst2\|counter\[14\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -517,7 +2041,7 @@ (INSTANCE \\inst2\|counter\[15\]\~54\\) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (460:460:460)) + (PORT dataa (370:370:370) (457:457:457)) (IOPATH dataa combout (461:461:461) (481:481:481)) (IOPATH dataa cout (552:552:552) (416:416:416)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -531,9 +2055,9 @@ (INSTANCE \\inst2\|counter\[15\]\\) (DELAY (ABSOLUTE - (PORT clk (1919:1919:1919) (1929:1929:1929)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -547,7 +2071,7 @@ (INSTANCE \\inst2\|counter\[16\]\~56\\) (DELAY (ABSOLUTE - (PORT datab (359:359:359) (436:436:436)) + (PORT datab (368:368:368) (449:449:449)) (IOPATH datab combout (472:472:472) (473:473:473)) (IOPATH datab cout (565:565:565) (421:421:421)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -561,9 +2085,9 @@ (INSTANCE \\inst2\|counter\[16\]\\) (DELAY (ABSOLUTE - (PORT clk (1919:1919:1919) (1929:1929:1929)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -577,7 +2101,7 @@ (INSTANCE \\inst2\|counter\[17\]\~58\\) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (447:447:447)) + (PORT dataa (345:345:345) (436:436:436)) (IOPATH dataa combout (461:461:461) (481:481:481)) (IOPATH dataa cout (552:552:552) (416:416:416)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -591,9 +2115,9 @@ (INSTANCE \\inst2\|counter\[17\]\\) (DELAY (ABSOLUTE - (PORT clk (1919:1919:1919) (1929:1929:1929)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -602,28 +2126,12 @@ (HOLD sclr (posedge clk) (212:212:212)) ) ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~0\\) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (866:866:866)) - (PORT datab (635:635:635) (645:645:645)) - (PORT datac (534:534:534) (562:562:562)) - (PORT datad (572:572:572) (584:584:584)) - (IOPATH dataa combout (438:438:438) (448:448:448)) - (IOPATH datab combout (440:440:440) (462:462:462)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[18\]\~60\\) (DELAY (ABSOLUTE - (PORT dataa (346:346:346) (436:436:436)) + (PORT dataa (345:345:345) (436:436:436)) (IOPATH dataa combout (471:471:471) (472:472:472)) (IOPATH dataa cout (552:552:552) (416:416:416)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -637,9 +2145,9 @@ (INSTANCE \\inst2\|counter\[18\]\\) (DELAY (ABSOLUTE - (PORT clk (1919:1919:1919) (1929:1929:1929)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -667,9 +2175,9 @@ (INSTANCE \\inst2\|counter\[19\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -697,9 +2205,9 @@ (INSTANCE \\inst2\|counter\[20\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -727,9 +2235,9 @@ (INSTANCE \\inst2\|counter\[21\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -738,12 +2246,28 @@ (HOLD sclr (posedge clk) (212:212:212)) ) ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~8\\) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (437:437:437)) + (PORT datab (342:342:342) (426:426:426)) + (PORT datac (302:302:302) (387:387:387)) + (PORT datad (302:302:302) (379:379:379)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[22\]\~68\\) (DELAY (ABSOLUTE - (PORT datab (343:343:343) (428:428:428)) + (PORT datab (344:344:344) (425:425:425)) (IOPATH datab combout (472:472:472) (473:473:473)) (IOPATH datab cout (565:565:565) (421:421:421)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -757,9 +2281,9 @@ (INSTANCE \\inst2\|counter\[22\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -773,7 +2297,7 @@ (INSTANCE \\inst2\|counter\[23\]\~70\\) (DELAY (ABSOLUTE - (PORT dataa (821:821:821) (810:810:810)) + (PORT dataa (347:347:347) (436:436:436)) (IOPATH dataa combout (471:471:471) (481:481:481)) (IOPATH cin combout (607:607:607) (577:577:577)) ) @@ -784,9 +2308,9 @@ (INSTANCE \\inst2\|counter\[23\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -797,15 +2321,13 @@ ) (CELL (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~1\\) + (INSTANCE \\inst2\|LessThan0\~9\\) (DELAY (ABSOLUTE - (PORT dataa (346:346:346) (435:435:435)) - (PORT datab (342:342:342) (425:425:425)) - (PORT datac (302:302:302) (385:385:385)) - (PORT datad (302:302:302) (378:378:378)) - (IOPATH dataa combout (420:420:420) (428:428:428)) - (IOPATH datab combout (432:432:432) (433:433:433)) + (PORT dataa (279:279:279) (312:312:312)) + (PORT datac (302:302:302) (387:387:387)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (405:405:405) (398:398:398)) (IOPATH datac combout (324:324:324) (315:315:315)) (IOPATH datad combout (177:177:177) (155:155:155)) ) @@ -816,24 +2338,10 @@ (INSTANCE \\inst2\|LessThan0\~2\\) (DELAY (ABSOLUTE - (PORT datab (343:343:343) (427:427:427)) - (PORT datac (776:776:776) (761:761:761)) - (PORT datad (237:237:237) (256:256:256)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~5\\) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (434:434:434)) - (PORT datab (343:343:343) (424:424:424)) - (PORT datac (319:319:319) (396:396:396)) - (PORT datad (304:304:304) (379:379:379)) + (PORT dataa (1357:1357:1357) (1326:1326:1326)) + (PORT datab (1359:1359:1359) (1293:1293:1293)) + (PORT datac (1347:1347:1347) (1289:1289:1289)) + (PORT datad (1321:1321:1321) (1266:1266:1266)) (IOPATH dataa combout (456:456:456) (486:486:486)) (IOPATH datab combout (457:457:457) (489:489:489)) (IOPATH datac combout (324:324:324) (315:315:315)) @@ -846,10 +2354,10 @@ (INSTANCE \\inst2\|LessThan0\~3\\) (DELAY (ABSOLUTE - (PORT dataa (361:361:361) (445:445:445)) - (PORT datab (359:359:359) (437:437:437)) - (PORT datac (318:318:318) (396:396:396)) - (PORT datad (319:319:319) (389:389:389)) + (PORT dataa (346:346:346) (434:434:434)) + (PORT datab (344:344:344) (424:424:424)) + (PORT datac (303:303:303) (385:385:385)) + (PORT datad (304:304:304) (378:378:378)) (IOPATH dataa combout (456:456:456) (486:486:486)) (IOPATH datab combout (457:457:457) (489:489:489)) (IOPATH datac combout (324:324:324) (315:315:315)) @@ -857,18 +2365,50 @@ ) ) ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (436:436:436)) + (PORT datab (368:368:368) (452:452:452)) + (PORT datac (301:301:301) (386:386:386)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (601:601:601)) + (PORT datab (275:275:275) (300:300:300)) + (PORT datac (301:301:301) (387:387:387)) + (PORT datad (304:304:304) (380:380:380)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|LessThan0\~4\\) (DELAY (ABSOLUTE - (PORT dataa (583:583:583) (613:613:613)) - (PORT datab (342:342:342) (424:424:424)) - (PORT datac (301:301:301) (385:385:385)) + (PORT dataa (347:347:347) (436:436:436)) + (PORT datab (1246:1246:1246) (1139:1139:1139)) + (PORT datac (236:236:236) (262:262:262)) (PORT datad (237:237:237) (255:255:255)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) (IOPATH datad combout (177:177:177) (155:155:155)) ) ) @@ -878,13 +2418,437 @@ (INSTANCE \\inst2\|LessThan0\~6\\) (DELAY (ABSOLUTE - (PORT dataa (348:348:348) (438:438:438)) - (PORT datab (344:344:344) (427:427:427)) - (PORT datac (235:235:235) (262:262:262)) - (PORT datad (237:237:237) (255:255:255)) - (IOPATH dataa combout (393:393:393) (398:398:398)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datac combout (324:324:324) (316:316:316)) + (PORT dataa (346:346:346) (435:435:435)) + (PORT datab (344:344:344) (425:425:425)) + (PORT datac (328:328:328) (411:411:411)) + (PORT datad (330:330:330) (405:405:405)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~10\\) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1201:1201:1201)) + (PORT datab (302:302:302) (328:328:328)) + (PORT datac (849:849:849) (776:776:776)) + (PORT datad (264:264:264) (282:282:282)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[1\]\~26\\) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (436:436:436)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[2\]\~28\\) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[3\]\~30\\) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[4\]\~32\\) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (451:451:451)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[5\]\~34\\) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[6\]\~36\\) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[6\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[7\]\~38\\) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[7\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[8\]\~40\\) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (421:421:421)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[8\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[9\]\~42\\) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[9\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[10\]\~44\\) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (424:424:424)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[10\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[11\]\~46\\) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[11\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[12\]\~48\\) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (433:433:433)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[12\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1920:1920:1920) (1931:1931:1931)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (935:935:935) (1004:1004:1004)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[13\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1920:1920:1920) (1931:1931:1931)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (935:935:935) (1004:1004:1004)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~5\\) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1323:1323:1323)) + (PORT datab (1398:1398:1398) (1325:1325:1325)) + (PORT datac (1336:1336:1336) (1278:1278:1278)) + (PORT datad (1301:1301:1301) (1245:1245:1245)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) (IOPATH datad combout (177:177:177) (155:155:155)) ) ) @@ -894,29 +2858,9 @@ (INSTANCE \\inst2\|LessThan0\~7\\) (DELAY (ABSOLUTE - (PORT dataa (579:579:579) (617:617:617)) - (PORT datab (345:345:345) (429:429:429)) - (PORT datac (541:541:541) (559:559:559)) - (PORT datad (816:816:816) (741:741:741)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (472:472:472) (452:452:452)) - (IOPATH datac combout (327:327:327) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~8\\) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (464:464:464)) - (PORT datab (531:531:531) (492:492:492)) - (PORT datac (235:235:235) (262:262:262)) - (PORT datad (236:236:236) (255:255:255)) - (IOPATH dataa combout (456:456:456) (486:486:486)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datac combout (327:327:327) (316:316:316)) + (PORT datac (262:262:262) (288:288:288)) + (PORT datad (1268:1268:1268) (1163:1163:1163)) + (IOPATH datac combout (327:327:327) (315:315:315)) (IOPATH datad combout (177:177:177) (155:155:155)) ) ) @@ -926,7 +2870,11 @@ (INSTANCE \\inst2\|ledBuf\~0\\) (DELAY (ABSOLUTE - (PORT datad (747:747:747) (674:674:674)) + (PORT dataa (279:279:279) (312:312:312)) + (PORT datab (1281:1281:1281) (1188:1188:1188)) + (PORT datad (1223:1223:1223) (1126:1126:1126)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) (IOPATH datac combout (462:462:462) (482:482:482)) (IOPATH datad combout (177:177:177) (155:155:155)) ) @@ -937,7 +2885,7 @@ (INSTANCE \\inst2\|ledBuf\\) (DELAY (ABSOLUTE - (PORT clk (2411:2411:2411) (2414:2414:2414)) + (PORT clk (1917:1917:1917) (1925:1925:1925)) (PORT d (99:99:99) (115:115:115)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) @@ -946,4 +2894,31 @@ (HOLD d (posedge clk) (212:212:212)) ) ) + (CELL + (CELLTYPE "cycloneiii_pll") + (INSTANCE \\inst\|altpll_component\|auto_generated\|pll1\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2357:2357:2357) (2357:2357:2357)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_clkctrl") + (INSTANCE \\inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2365:2365:2365) (2331:2331:2331)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_clkctrl") + (INSTANCE \\inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2365:2365:2365) (2331:2331:2331)) + ) + ) + ) ) diff --git a/MainController/simulation/modelsim/MainController_min_1200mv_0c_fast.vho b/MainController/simulation/modelsim/MainController_min_1200mv_0c_fast.vho index d2c6f05..68aef67 100644 --- a/MainController/simulation/modelsim/MainController_min_1200mv_0c_fast.vho +++ b/MainController/simulation/modelsim/MainController_min_1200mv_0c_fast.vho @@ -16,7 +16,7 @@ -- PROGRAM "Quartus II 64-Bit" -- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" --- DATE "03/12/2024 16:24:29" +-- DATE "03/12/2024 17:46:57" -- -- Device: Altera EP3C25Q240C8 Package PQFP240 @@ -37,27 +37,20 @@ ENTITY MainController IS PORT ( FPGA_LED_1 : OUT std_logic; FPGA_CLK : IN std_logic; + FPGA_LED_2 : OUT std_logic; + FPGA_LED_3 : OUT std_logic; Data : INOUT std_logic_vector(7 DOWNTO 0); - Address : IN std_logic_vector(7 DOWNTO 0); - nOE : IN std_logic; nWE : IN std_logic; - nCE : IN std_logic + nOE : IN std_logic; + nCE : IN std_logic; + Address : IN std_logic_vector(7 DOWNTO 0) ); END MainController; -- Design Ports Information -- FPGA_LED_1 => Location: PIN_166, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA --- Address[7] => Location: PIN_195, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[6] => Location: PIN_230, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[5] => Location: PIN_235, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[4] => Location: PIN_232, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[3] => Location: PIN_233, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[2] => Location: PIN_234, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[1] => Location: PIN_231, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- Address[0] => Location: PIN_196, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nOE => Location: PIN_217, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nWE => Location: PIN_218, I/O Standard: 3.3-V LVTTL, Current Strength: Default --- nCE => Location: PIN_219, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- FPGA_LED_2 => Location: PIN_167, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +-- FPGA_LED_3 => Location: PIN_168, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[7] => Location: PIN_221, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[6] => Location: PIN_223, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[5] => Location: PIN_224, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA @@ -67,6 +60,17 @@ END MainController; -- Data[1] => Location: PIN_189, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- Data[0] => Location: PIN_194, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA -- FPGA_CLK => Location: PIN_31, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nCE => Location: PIN_219, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nWE => Location: PIN_218, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[0] => Location: PIN_196, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[1] => Location: PIN_231, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[2] => Location: PIN_234, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[3] => Location: PIN_233, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[4] => Location: PIN_232, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[5] => Location: PIN_235, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[6] => Location: PIN_230, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- Address[7] => Location: PIN_195, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- nOE => Location: PIN_217, I/O Standard: 3.3-V LVTTL, Current Strength: Default ARCHITECTURE structure OF MainController IS @@ -81,42 +85,152 @@ SIGNAL ww_devclrn : std_logic; SIGNAL ww_devpor : std_logic; SIGNAL ww_FPGA_LED_1 : std_logic; SIGNAL ww_FPGA_CLK : std_logic; -SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0); -SIGNAL ww_nOE : std_logic; +SIGNAL ww_FPGA_LED_2 : std_logic; +SIGNAL ww_FPGA_LED_3 : std_logic; SIGNAL ww_nWE : std_logic; +SIGNAL ww_nOE : std_logic; SIGNAL ww_nCE : std_logic; +SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|pll1_INCLK_bus\ : std_logic_vector(1 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|pll1_CLK_bus\ : std_logic_vector(4 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(35 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(35 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); SIGNAL \FPGA_CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); -SIGNAL \Address[7]~input_o\ : std_logic; -SIGNAL \Address[6]~input_o\ : std_logic; -SIGNAL \Address[5]~input_o\ : std_logic; -SIGNAL \Address[4]~input_o\ : std_logic; -SIGNAL \Address[3]~input_o\ : std_logic; -SIGNAL \Address[2]~input_o\ : std_logic; -SIGNAL \Address[1]~input_o\ : std_logic; -SIGNAL \Address[0]~input_o\ : std_logic; -SIGNAL \nOE~input_o\ : std_logic; -SIGNAL \nWE~input_o\ : std_logic; -SIGNAL \nCE~input_o\ : std_logic; -SIGNAL \Data[7]~input_o\ : std_logic; -SIGNAL \Data[6]~input_o\ : std_logic; -SIGNAL \Data[5]~input_o\ : std_logic; -SIGNAL \Data[4]~input_o\ : std_logic; -SIGNAL \Data[3]~input_o\ : std_logic; -SIGNAL \Data[2]~input_o\ : std_logic; -SIGNAL \Data[1]~input_o\ : std_logic; -SIGNAL \Data[0]~input_o\ : std_logic; -SIGNAL \Data[7]~output_o\ : std_logic; -SIGNAL \Data[6]~output_o\ : std_logic; -SIGNAL \Data[5]~output_o\ : std_logic; -SIGNAL \Data[4]~output_o\ : std_logic; -SIGNAL \Data[3]~output_o\ : std_logic; -SIGNAL \Data[2]~output_o\ : std_logic; -SIGNAL \Data[1]~output_o\ : std_logic; -SIGNAL \Data[0]~output_o\ : std_logic; -SIGNAL \FPGA_LED_1~output_o\ : std_logic; SIGNAL \FPGA_CLK~input_o\ : std_logic; SIGNAL \FPGA_CLK~inputclkctrl_outclk\ : std_logic; +SIGNAL \nCE~input_o\ : std_logic; +SIGNAL \Address[5]~input_o\ : std_logic; +SIGNAL \inst3|ce0Prev~q\ : std_logic; +SIGNAL \inst3|addr~5_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[12]~feeder_combout\ : std_logic; +SIGNAL \nWE~input_o\ : std_logic; +SIGNAL \inst3|we0Prev~q\ : std_logic; +SIGNAL \nOE~input_o\ : std_logic; +SIGNAL \inst3|Selector3~3_combout\ : std_logic; +SIGNAL \inst3|Selector3~2_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Writing~q\ : std_logic; +SIGNAL \inst3|memory~48_combout\ : std_logic; +SIGNAL \inst3|oe0Prev~q\ : std_logic; +SIGNAL \inst3|Selector3~0_combout\ : std_logic; +SIGNAL \inst3|Selector3~1_combout\ : std_logic; +SIGNAL \inst3|Selector2~0_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Waiting~q\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[11]~feeder_combout\ : std_logic; +SIGNAL \Address[4]~input_o\ : std_logic; +SIGNAL \inst3|addr~4_combout\ : std_logic; +SIGNAL \inst3|memory~37_combout\ : std_logic; +SIGNAL \Address[2]~input_o\ : std_logic; +SIGNAL \inst3|addr~2_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[6]~feeder_combout\ : std_logic; +SIGNAL \Address[3]~input_o\ : std_logic; +SIGNAL \inst3|addr~3_combout\ : std_logic; +SIGNAL \inst3|memory~35_combout\ : std_logic; +SIGNAL \Address[0]~input_o\ : std_logic; +SIGNAL \inst3|addr~0_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[2]~feeder_combout\ : std_logic; +SIGNAL \Address[1]~input_o\ : std_logic; +SIGNAL \inst3|addr~1_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[4]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~34_combout\ : std_logic; +SIGNAL \inst3|memory~36_combout\ : std_logic; +SIGNAL \Address[7]~input_o\ : std_logic; +SIGNAL \inst3|addr~7_combout\ : std_logic; +SIGNAL \Address[6]~input_o\ : std_logic; +SIGNAL \inst3|addr~6_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[13]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[16]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~38_combout\ : std_logic; +SIGNAL \inst3|memory~39_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Waiting~_wirecell_combout\ : std_logic; +SIGNAL \Data[0]~input_o\ : std_logic; +SIGNAL \Data[1]~input_o\ : std_logic; +SIGNAL \Data[2]~input_o\ : std_logic; +SIGNAL \Data[3]~input_o\ : std_logic; +SIGNAL \Data[4]~input_o\ : std_logic; +SIGNAL \Data[5]~input_o\ : std_logic; +SIGNAL \Data[6]~input_o\ : std_logic; +SIGNAL \Data[7]~input_o\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a7\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[24]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~40_combout\ : std_logic; +SIGNAL \inst3|Selector4~0_combout\ : std_logic; +SIGNAL \inst3|stateMM0.Reading~q\ : std_logic; +SIGNAL \inst3|Selector74~0_combout\ : std_logic; +SIGNAL \inst3|data0[7]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[7]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[7]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[23]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a6\ : std_logic; +SIGNAL \inst3|memory~41_combout\ : std_logic; +SIGNAL \inst3|data0[6]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[6]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[6]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a5\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[22]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~42_combout\ : std_logic; +SIGNAL \inst3|data0[5]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[5]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[5]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a4\ : std_logic; +SIGNAL \inst3|memory_rtl_0_bypass[21]~feeder_combout\ : std_logic; +SIGNAL \inst3|memory~43_combout\ : std_logic; +SIGNAL \inst3|data0[4]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[4]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[4]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a3\ : std_logic; +SIGNAL \inst3|memory~44_combout\ : std_logic; +SIGNAL \inst3|data0[3]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[3]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[3]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a2\ : std_logic; +SIGNAL \inst3|memory~45_combout\ : std_logic; +SIGNAL \inst3|data0[2]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[2]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[2]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a1\ : std_logic; +SIGNAL \inst3|memory~46_combout\ : std_logic; +SIGNAL \inst3|data0[1]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[1]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[1]~en_q\ : std_logic; +SIGNAL \inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic; +SIGNAL \inst3|memory~47_combout\ : std_logic; +SIGNAL \inst3|data0[0]~reg0_q\ : std_logic; +SIGNAL \inst3|data0[0]~enfeeder_combout\ : std_logic; +SIGNAL \inst3|data0[0]~en_q\ : std_logic; SIGNAL \inst2|counter[0]~24_combout\ : std_logic; +SIGNAL \inst2|counter[13]~51\ : std_logic; +SIGNAL \inst2|counter[14]~52_combout\ : std_logic; +SIGNAL \inst2|counter[14]~53\ : std_logic; +SIGNAL \inst2|counter[15]~54_combout\ : std_logic; +SIGNAL \inst2|counter[15]~55\ : std_logic; +SIGNAL \inst2|counter[16]~56_combout\ : std_logic; +SIGNAL \inst2|counter[16]~57\ : std_logic; +SIGNAL \inst2|counter[17]~58_combout\ : std_logic; +SIGNAL \inst2|counter[17]~59\ : std_logic; +SIGNAL \inst2|counter[18]~60_combout\ : std_logic; +SIGNAL \inst2|counter[18]~61\ : std_logic; +SIGNAL \inst2|counter[19]~62_combout\ : std_logic; +SIGNAL \inst2|counter[19]~63\ : std_logic; +SIGNAL \inst2|counter[20]~64_combout\ : std_logic; +SIGNAL \inst2|counter[20]~65\ : std_logic; +SIGNAL \inst2|counter[21]~66_combout\ : std_logic; +SIGNAL \inst2|LessThan0~8_combout\ : std_logic; +SIGNAL \inst2|counter[21]~67\ : std_logic; +SIGNAL \inst2|counter[22]~68_combout\ : std_logic; +SIGNAL \inst2|counter[22]~69\ : std_logic; +SIGNAL \inst2|counter[23]~70_combout\ : std_logic; +SIGNAL \inst2|LessThan0~9_combout\ : std_logic; +SIGNAL \inst2|LessThan0~2_combout\ : std_logic; +SIGNAL \inst2|LessThan0~3_combout\ : std_logic; +SIGNAL \inst2|LessThan0~0_combout\ : std_logic; +SIGNAL \inst2|LessThan0~1_combout\ : std_logic; +SIGNAL \inst2|LessThan0~4_combout\ : std_logic; +SIGNAL \inst2|LessThan0~6_combout\ : std_logic; +SIGNAL \inst2|LessThan0~10_combout\ : std_logic; SIGNAL \inst2|counter[0]~25\ : std_logic; SIGNAL \inst2|counter[1]~26_combout\ : std_logic; SIGNAL \inst2|counter[1]~27\ : std_logic; @@ -143,153 +257,69 @@ SIGNAL \inst2|counter[11]~47\ : std_logic; SIGNAL \inst2|counter[12]~48_combout\ : std_logic; SIGNAL \inst2|counter[12]~49\ : std_logic; SIGNAL \inst2|counter[13]~50_combout\ : std_logic; -SIGNAL \inst2|counter[13]~51\ : std_logic; -SIGNAL \inst2|counter[14]~52_combout\ : std_logic; -SIGNAL \inst2|counter[14]~53\ : std_logic; -SIGNAL \inst2|counter[15]~54_combout\ : std_logic; -SIGNAL \inst2|counter[15]~55\ : std_logic; -SIGNAL \inst2|counter[16]~56_combout\ : std_logic; -SIGNAL \inst2|counter[16]~57\ : std_logic; -SIGNAL \inst2|counter[17]~58_combout\ : std_logic; -SIGNAL \inst2|LessThan0~0_combout\ : std_logic; -SIGNAL \inst2|counter[17]~59\ : std_logic; -SIGNAL \inst2|counter[18]~60_combout\ : std_logic; -SIGNAL \inst2|counter[18]~61\ : std_logic; -SIGNAL \inst2|counter[19]~62_combout\ : std_logic; -SIGNAL \inst2|counter[19]~63\ : std_logic; -SIGNAL \inst2|counter[20]~64_combout\ : std_logic; -SIGNAL \inst2|counter[20]~65\ : std_logic; -SIGNAL \inst2|counter[21]~66_combout\ : std_logic; -SIGNAL \inst2|counter[21]~67\ : std_logic; -SIGNAL \inst2|counter[22]~68_combout\ : std_logic; -SIGNAL \inst2|counter[22]~69\ : std_logic; -SIGNAL \inst2|counter[23]~70_combout\ : std_logic; -SIGNAL \inst2|LessThan0~1_combout\ : std_logic; -SIGNAL \inst2|LessThan0~2_combout\ : std_logic; SIGNAL \inst2|LessThan0~5_combout\ : std_logic; -SIGNAL \inst2|LessThan0~3_combout\ : std_logic; -SIGNAL \inst2|LessThan0~4_combout\ : std_logic; -SIGNAL \inst2|LessThan0~6_combout\ : std_logic; SIGNAL \inst2|LessThan0~7_combout\ : std_logic; -SIGNAL \inst2|LessThan0~8_combout\ : std_logic; SIGNAL \inst2|ledBuf~0_combout\ : std_logic; SIGNAL \inst2|ledBuf~q\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_fbout\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\ : std_logic; +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\ : std_logic; +SIGNAL \inst3|addr\ : std_logic_vector(7 DOWNTO 0); +SIGNAL \inst3|memory_rtl_0_bypass\ : std_logic_vector(0 TO 24); +SIGNAL \inst|altpll_component|auto_generated|wire_pll1_clk\ : std_logic_vector(4 DOWNTO 0); SIGNAL \inst2|counter\ : std_logic_vector(23 DOWNTO 0); -SIGNAL \inst2|ALT_INV_LessThan0~8_combout\ : std_logic; +SIGNAL \inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\ : std_logic; +SIGNAL \inst3|ALT_INV_stateMM0.Waiting~q\ : std_logic; SIGNAL \inst2|ALT_INV_ledBuf~q\ : std_logic; BEGIN FPGA_LED_1 <= ww_FPGA_LED_1; ww_FPGA_CLK <= FPGA_CLK; -ww_Address <= Address; -ww_nOE <= nOE; +FPGA_LED_2 <= ww_FPGA_LED_2; +FPGA_LED_3 <= ww_FPGA_LED_3; ww_nWE <= nWE; +ww_nOE <= nOE; ww_nCE <= nCE; +ww_Address <= Address; ww_devoe <= devoe; ww_devclrn <= devclrn; ww_devpor <= devpor; +\inst|altpll_component|auto_generated|pll1_INCLK_bus\ <= (gnd & \FPGA_CLK~input_o\); + +\inst|altpll_component|auto_generated|wire_pll1_clk\(0) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(0); +\inst|altpll_component|auto_generated|wire_pll1_clk\(1) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(1); +\inst|altpll_component|auto_generated|wire_pll1_clk\(2) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(2); +\inst|altpll_component|auto_generated|wire_pll1_clk\(3) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(3); +\inst|altpll_component|auto_generated|wire_pll1_clk\(4) <= \inst|altpll_component|auto_generated|pll1_CLK_bus\(4); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & \Data[7]~input_o\ +& \Data[6]~input_o\ & \Data[5]~input_o\ & \Data[4]~input_o\ & \Data[3]~input_o\ & \Data[2]~input_o\ & \Data[1]~input_o\ & \Data[0]~input_o\); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\inst3|addr\(7) & \inst3|addr\(6) & \inst3|addr\(5) & \inst3|addr\(4) & \inst3|addr\(3) & \inst3|addr\(2) & \inst3|addr\(1) & \inst3|addr\(0)); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\inst3|addr~7_combout\ & \inst3|addr~6_combout\ & \inst3|addr~5_combout\ & \inst3|addr~4_combout\ & \inst3|addr~3_combout\ & \inst3|addr~2_combout\ & \inst3|addr~1_combout\ & +\inst3|addr~0_combout\); + +\inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0); +\inst3|memory_rtl_0|auto_generated|ram_block1a1\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1); +\inst3|memory_rtl_0|auto_generated|ram_block1a2\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2); +\inst3|memory_rtl_0|auto_generated|ram_block1a3\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3); +\inst3|memory_rtl_0|auto_generated|ram_block1a4\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4); +\inst3|memory_rtl_0|auto_generated|ram_block1a5\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5); +\inst3|memory_rtl_0|auto_generated|ram_block1a6\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6); +\inst3|memory_rtl_0|auto_generated|ram_block1a7\ <= \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7); + +\inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|altpll_component|auto_generated|wire_pll1_clk\(1)); + +\inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \inst|altpll_component|auto_generated|wire_pll1_clk\(0)); + \FPGA_CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \FPGA_CLK~input_o\); -\inst2|ALT_INV_LessThan0~8_combout\ <= NOT \inst2|LessThan0~8_combout\; +\inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\ <= NOT \inst3|stateMM0.Waiting~_wirecell_combout\; +\inst3|ALT_INV_stateMM0.Waiting~q\ <= NOT \inst3|stateMM0.Waiting~q\; \inst2|ALT_INV_ledBuf~q\ <= NOT \inst2|ledBuf~q\; --- Location: IOOBUF_X18_Y34_N2 -\Data[7]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[7]~output_o\); - --- Location: IOOBUF_X18_Y34_N23 -\Data[6]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[6]~output_o\); - --- Location: IOOBUF_X16_Y34_N2 -\Data[5]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[5]~output_o\); - --- Location: IOOBUF_X16_Y34_N16 -\Data[4]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[4]~output_o\); - --- Location: IOOBUF_X45_Y34_N9 -\Data[3]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[3]~output_o\); - --- Location: IOOBUF_X45_Y34_N16 -\Data[2]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[2]~output_o\); - --- Location: IOOBUF_X45_Y34_N23 -\Data[1]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[1]~output_o\); - --- Location: IOOBUF_X40_Y34_N9 -\Data[0]~output\ : cycloneiii_io_obuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - open_drain_output => "true") --- pragma translate_on -PORT MAP ( - i => VCC, - devoe => ww_devoe, - o => \Data[0]~output_o\); - -- Location: IOOBUF_X53_Y22_N2 \FPGA_LED_1~output\ : cycloneiii_io_obuf -- pragma translate_off @@ -300,7 +330,135 @@ GENERIC MAP ( PORT MAP ( i => \inst2|ALT_INV_ledBuf~q\, devoe => ww_devoe, - o => \FPGA_LED_1~output_o\); + o => ww_FPGA_LED_1); + +-- Location: IOOBUF_X53_Y23_N23 +\FPGA_LED_2~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\, + devoe => ww_devoe, + o => ww_FPGA_LED_2); + +-- Location: IOOBUF_X53_Y23_N16 +\FPGA_LED_3~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\, + devoe => ww_devoe, + o => ww_FPGA_LED_3); + +-- Location: IOOBUF_X18_Y34_N2 +\Data[7]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[7]~reg0_q\, + oe => \inst3|data0[7]~en_q\, + devoe => ww_devoe, + o => Data(7)); + +-- Location: IOOBUF_X18_Y34_N23 +\Data[6]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[6]~reg0_q\, + oe => \inst3|data0[6]~en_q\, + devoe => ww_devoe, + o => Data(6)); + +-- Location: IOOBUF_X16_Y34_N2 +\Data[5]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[5]~reg0_q\, + oe => \inst3|data0[5]~en_q\, + devoe => ww_devoe, + o => Data(5)); + +-- Location: IOOBUF_X16_Y34_N16 +\Data[4]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[4]~reg0_q\, + oe => \inst3|data0[4]~en_q\, + devoe => ww_devoe, + o => Data(4)); + +-- Location: IOOBUF_X45_Y34_N9 +\Data[3]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[3]~reg0_q\, + oe => \inst3|data0[3]~en_q\, + devoe => ww_devoe, + o => Data(3)); + +-- Location: IOOBUF_X45_Y34_N16 +\Data[2]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[2]~reg0_q\, + oe => \inst3|data0[2]~en_q\, + devoe => ww_devoe, + o => Data(2)); + +-- Location: IOOBUF_X45_Y34_N23 +\Data[1]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[1]~reg0_q\, + oe => \inst3|data0[1]~en_q\, + devoe => ww_devoe, + o => Data(1)); + +-- Location: IOOBUF_X40_Y34_N9 +\Data[0]~output\ : cycloneiii_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3|data0[0]~reg0_q\, + oe => \inst3|data0[0]~en_q\, + devoe => ww_devoe, + o => Data(0)); -- Location: IOIBUF_X0_Y16_N1 \FPGA_CLK~input\ : cycloneiii_io_ibuf @@ -313,7 +471,7 @@ PORT MAP ( i => ww_FPGA_CLK, o => \FPGA_CLK~input_o\); --- Location: CLKCTRL_G4 +-- Location: CLKCTRL_G2 \FPGA_CLK~inputclkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( @@ -326,7 +484,1858 @@ PORT MAP ( devpor => ww_devpor, outclk => \FPGA_CLK~inputclkctrl_outclk\); --- Location: LCCOMB_X51_Y14_N8 +-- Location: IOIBUF_X20_Y34_N15 +\nCE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nCE, + o => \nCE~input_o\); + +-- Location: IOIBUF_X7_Y34_N15 +\Address[5]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(5), + o => \Address[5]~input_o\); + +-- Location: FF_X27_Y29_N31 +\inst3|ce0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nCE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|ce0Prev~q\); + +-- Location: LCCOMB_X34_Y24_N26 +\inst3|addr~5\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~5_combout\ = (!\nCE~input_o\ & (\Address[5]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[5]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~5_combout\); + +-- Location: LCCOMB_X32_Y23_N12 +\inst3|memory_rtl_0_bypass[12]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[12]~feeder_combout\ = \inst3|addr~5_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~5_combout\, + combout => \inst3|memory_rtl_0_bypass[12]~feeder_combout\); + +-- Location: IOIBUF_X20_Y34_N8 +\nWE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nWE, + o => \nWE~input_o\); + +-- Location: FF_X27_Y29_N21 +\inst3|we0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nWE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|we0Prev~q\); + +-- Location: IOIBUF_X20_Y34_N1 +\nOE~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_nOE, + o => \nOE~input_o\); + +-- Location: LCCOMB_X27_Y29_N14 +\inst3|Selector3~3\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~3_combout\ = (\nOE~input_o\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\ & !\inst3|stateMM0.Waiting~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector3~3_combout\); + +-- Location: LCCOMB_X27_Y29_N30 +\inst3|Selector3~2\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~2_combout\ = (\inst3|stateMM0.Waiting~q\ & (((\inst3|Selector3~1_combout\)))) # (!\inst3|stateMM0.Waiting~q\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011101000010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|stateMM0.Waiting~q\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|Selector3~1_combout\, + combout => \inst3|Selector3~2_combout\); + +-- Location: FF_X27_Y29_N15 +\inst3|stateMM0.Writing\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector3~3_combout\, + ena => \inst3|Selector3~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Writing~q\); + +-- Location: LCCOMB_X27_Y29_N20 +\inst3|memory~48\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~48_combout\ = (!\nWE~input_o\ & (\inst3|we0Prev~q\ & \inst3|stateMM0.Writing~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nWE~input_o\, + datac => \inst3|we0Prev~q\, + datad => \inst3|stateMM0.Writing~q\, + combout => \inst3|memory~48_combout\); + +-- Location: FF_X27_Y29_N25 +\inst3|oe0Prev\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \nOE~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|oe0Prev~q\); + +-- Location: LCCOMB_X27_Y29_N24 +\inst3|Selector3~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~0_combout\ = (\nOE~input_o\ & (!\inst3|oe0Prev~q\ & !\inst3|stateMM0.Writing~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datac => \inst3|oe0Prev~q\, + datad => \inst3|stateMM0.Writing~q\, + combout => \inst3|Selector3~0_combout\); + +-- Location: LCCOMB_X27_Y29_N2 +\inst3|Selector3~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector3~1_combout\ = (\inst3|memory~48_combout\) # ((\nCE~input_o\) # (\inst3|Selector3~0_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111101110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory~48_combout\, + datab => \nCE~input_o\, + datad => \inst3|Selector3~0_combout\, + combout => \inst3|Selector3~1_combout\); + +-- Location: LCCOMB_X27_Y29_N8 +\inst3|Selector2~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector2~0_combout\ = (\inst3|stateMM0.Waiting~q\ & (((!\inst3|Selector3~1_combout\)))) # (!\inst3|stateMM0.Waiting~q\ & (\inst3|ce0Prev~q\ & (!\nCE~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000001011110010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datac => \inst3|stateMM0.Waiting~q\, + datad => \inst3|Selector3~1_combout\, + combout => \inst3|Selector2~0_combout\); + +-- Location: FF_X27_Y29_N9 +\inst3|stateMM0.Waiting\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector2~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Waiting~q\); + +-- Location: FF_X32_Y23_N13 +\inst3|memory_rtl_0_bypass[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[12]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(12)); + +-- Location: FF_X34_Y24_N27 +\inst3|addr[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~5_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(5)); + +-- Location: LCCOMB_X32_Y23_N2 +\inst3|memory_rtl_0_bypass[11]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[11]~feeder_combout\ = \inst3|addr\(5) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr\(5), + combout => \inst3|memory_rtl_0_bypass[11]~feeder_combout\); + +-- Location: FF_X32_Y23_N3 +\inst3|memory_rtl_0_bypass[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[11]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(11)); + +-- Location: IOIBUF_X14_Y34_N22 +\Address[4]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(4), + o => \Address[4]~input_o\); + +-- Location: LCCOMB_X34_Y24_N0 +\inst3|addr~4\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~4_combout\ = (!\nCE~input_o\ & (\Address[4]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[4]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~4_combout\); + +-- Location: FF_X32_Y23_N7 +\inst3|memory_rtl_0_bypass[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~4_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(10)); + +-- Location: FF_X34_Y24_N1 +\inst3|addr[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~4_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(4)); + +-- Location: FF_X32_Y23_N1 +\inst3|memory_rtl_0_bypass[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(4), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(9)); + +-- Location: LCCOMB_X32_Y23_N6 +\inst3|memory~37\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~37_combout\ = (\inst3|memory_rtl_0_bypass\(12) & (\inst3|memory_rtl_0_bypass\(11) & (\inst3|memory_rtl_0_bypass\(10) $ (!\inst3|memory_rtl_0_bypass\(9))))) # (!\inst3|memory_rtl_0_bypass\(12) & (!\inst3|memory_rtl_0_bypass\(11) & +-- (\inst3|memory_rtl_0_bypass\(10) $ (!\inst3|memory_rtl_0_bypass\(9))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001000000001001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(12), + datab => \inst3|memory_rtl_0_bypass\(11), + datac => \inst3|memory_rtl_0_bypass\(10), + datad => \inst3|memory_rtl_0_bypass\(9), + combout => \inst3|memory~37_combout\); + +-- Location: IOIBUF_X7_Y34_N8 +\Address[2]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(2), + o => \Address[2]~input_o\); + +-- Location: LCCOMB_X34_Y24_N12 +\inst3|addr~2\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~2_combout\ = (!\nCE~input_o\ & (\Address[2]~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \nCE~input_o\, + datac => \Address[2]~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~2_combout\); + +-- Location: LCCOMB_X34_Y24_N14 +\inst3|memory_rtl_0_bypass[6]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[6]~feeder_combout\ = \inst3|addr~2_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~2_combout\, + combout => \inst3|memory_rtl_0_bypass[6]~feeder_combout\); + +-- Location: FF_X34_Y24_N15 +\inst3|memory_rtl_0_bypass[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[6]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(6)); + +-- Location: IOIBUF_X7_Y34_N1 +\Address[3]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(3), + o => \Address[3]~input_o\); + +-- Location: LCCOMB_X34_Y24_N30 +\inst3|addr~3\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~3_combout\ = (\inst3|ce0Prev~q\ & (\Address[3]~input_o\ & !\nCE~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \Address[3]~input_o\, + datad => \nCE~input_o\, + combout => \inst3|addr~3_combout\); + +-- Location: FF_X34_Y24_N31 +\inst3|addr[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~3_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(3)); + +-- Location: FF_X27_Y29_N1 +\inst3|memory_rtl_0_bypass[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(3), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(7)); + +-- Location: FF_X34_Y24_N13 +\inst3|addr[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~2_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(2)); + +-- Location: FF_X27_Y29_N23 +\inst3|memory_rtl_0_bypass[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(2), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(5)); + +-- Location: FF_X34_Y24_N5 +\inst3|memory_rtl_0_bypass[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~3_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(8)); + +-- Location: LCCOMB_X27_Y29_N22 +\inst3|memory~35\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~35_combout\ = (\inst3|memory_rtl_0_bypass\(6) & (\inst3|memory_rtl_0_bypass\(5) & (\inst3|memory_rtl_0_bypass\(7) $ (!\inst3|memory_rtl_0_bypass\(8))))) # (!\inst3|memory_rtl_0_bypass\(6) & (!\inst3|memory_rtl_0_bypass\(5) & +-- (\inst3|memory_rtl_0_bypass\(7) $ (!\inst3|memory_rtl_0_bypass\(8))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(6), + datab => \inst3|memory_rtl_0_bypass\(7), + datac => \inst3|memory_rtl_0_bypass\(5), + datad => \inst3|memory_rtl_0_bypass\(8), + combout => \inst3|memory~35_combout\); + +-- Location: IOIBUF_X38_Y34_N15 +\Address[0]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(0), + o => \Address[0]~input_o\); + +-- Location: LCCOMB_X34_Y24_N24 +\inst3|addr~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~0_combout\ = (\inst3|ce0Prev~q\ & (!\nCE~input_o\ & \Address[0]~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datac => \Address[0]~input_o\, + combout => \inst3|addr~0_combout\); + +-- Location: LCCOMB_X34_Y24_N18 +\inst3|memory_rtl_0_bypass[2]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[2]~feeder_combout\ = \inst3|addr~0_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~0_combout\, + combout => \inst3|memory_rtl_0_bypass[2]~feeder_combout\); + +-- Location: FF_X34_Y24_N19 +\inst3|memory_rtl_0_bypass[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[2]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(2)); + +-- Location: IOIBUF_X14_Y34_N15 +\Address[1]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(1), + o => \Address[1]~input_o\); + +-- Location: LCCOMB_X34_Y24_N2 +\inst3|addr~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~1_combout\ = (\Address[1]~input_o\ & (!\nCE~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \Address[1]~input_o\, + datab => \nCE~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~1_combout\); + +-- Location: FF_X34_Y24_N3 +\inst3|addr[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~1_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(1)); + +-- Location: FF_X27_Y29_N29 +\inst3|memory_rtl_0_bypass[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(1), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(3)); + +-- Location: FF_X34_Y24_N25 +\inst3|addr[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~0_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(0)); + +-- Location: FF_X27_Y29_N11 +\inst3|memory_rtl_0_bypass[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(0), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(1)); + +-- Location: LCCOMB_X34_Y24_N16 +\inst3|memory_rtl_0_bypass[4]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[4]~feeder_combout\ = \inst3|addr~1_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~1_combout\, + combout => \inst3|memory_rtl_0_bypass[4]~feeder_combout\); + +-- Location: FF_X34_Y24_N17 +\inst3|memory_rtl_0_bypass[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[4]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(4)); + +-- Location: LCCOMB_X27_Y29_N10 +\inst3|memory~34\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~34_combout\ = (\inst3|memory_rtl_0_bypass\(2) & (\inst3|memory_rtl_0_bypass\(1) & (\inst3|memory_rtl_0_bypass\(3) $ (!\inst3|memory_rtl_0_bypass\(4))))) # (!\inst3|memory_rtl_0_bypass\(2) & (!\inst3|memory_rtl_0_bypass\(1) & +-- (\inst3|memory_rtl_0_bypass\(3) $ (!\inst3|memory_rtl_0_bypass\(4))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(2), + datab => \inst3|memory_rtl_0_bypass\(3), + datac => \inst3|memory_rtl_0_bypass\(1), + datad => \inst3|memory_rtl_0_bypass\(4), + combout => \inst3|memory~34_combout\); + +-- Location: LCCOMB_X27_Y29_N18 +\inst3|memory~36\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~36_combout\ = (\inst3|memory~35_combout\ & \inst3|memory~34_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datac => \inst3|memory~35_combout\, + datad => \inst3|memory~34_combout\, + combout => \inst3|memory~36_combout\); + +-- Location: FF_X27_Y29_N17 +\inst3|memory_rtl_0_bypass[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|memory~48_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(0)); + +-- Location: IOIBUF_X38_Y34_N1 +\Address[7]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(7), + o => \Address[7]~input_o\); + +-- Location: LCCOMB_X34_Y24_N22 +\inst3|addr~7\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~7_combout\ = (\inst3|ce0Prev~q\ & (!\nCE~input_o\ & \Address[7]~input_o\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|ce0Prev~q\, + datab => \nCE~input_o\, + datad => \Address[7]~input_o\, + combout => \inst3|addr~7_combout\); + +-- Location: FF_X34_Y24_N23 +\inst3|addr[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~7_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(7)); + +-- Location: FF_X34_Y24_N11 +\inst3|memory_rtl_0_bypass[15]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr\(7), + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(15)); + +-- Location: IOIBUF_X14_Y34_N8 +\Address[6]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_Address(6), + o => \Address[6]~input_o\); + +-- Location: LCCOMB_X34_Y24_N20 +\inst3|addr~6\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|addr~6_combout\ = (\Address[6]~input_o\ & (!\nCE~input_o\ & \inst3|ce0Prev~q\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0010001000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \Address[6]~input_o\, + datab => \nCE~input_o\, + datad => \inst3|ce0Prev~q\, + combout => \inst3|addr~6_combout\); + +-- Location: FF_X34_Y24_N21 +\inst3|addr[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|addr~6_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|addr\(6)); + +-- Location: LCCOMB_X34_Y24_N8 +\inst3|memory_rtl_0_bypass[13]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[13]~feeder_combout\ = \inst3|addr\(6) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr\(6), + combout => \inst3|memory_rtl_0_bypass[13]~feeder_combout\); + +-- Location: FF_X34_Y24_N9 +\inst3|memory_rtl_0_bypass[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[13]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(13)); + +-- Location: FF_X34_Y24_N7 +\inst3|memory_rtl_0_bypass[14]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \inst3|addr~6_combout\, + sload => VCC, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(14)); + +-- Location: LCCOMB_X34_Y24_N28 +\inst3|memory_rtl_0_bypass[16]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[16]~feeder_combout\ = \inst3|addr~7_combout\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|addr~7_combout\, + combout => \inst3|memory_rtl_0_bypass[16]~feeder_combout\); + +-- Location: FF_X34_Y24_N29 +\inst3|memory_rtl_0_bypass[16]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[16]~feeder_combout\, + ena => \inst3|ALT_INV_stateMM0.Waiting~q\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(16)); + +-- Location: LCCOMB_X34_Y24_N6 +\inst3|memory~38\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~38_combout\ = (\inst3|memory_rtl_0_bypass\(15) & (\inst3|memory_rtl_0_bypass\(16) & (\inst3|memory_rtl_0_bypass\(13) $ (!\inst3|memory_rtl_0_bypass\(14))))) # (!\inst3|memory_rtl_0_bypass\(15) & (!\inst3|memory_rtl_0_bypass\(16) & +-- (\inst3|memory_rtl_0_bypass\(13) $ (!\inst3|memory_rtl_0_bypass\(14))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000001001000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(15), + datab => \inst3|memory_rtl_0_bypass\(13), + datac => \inst3|memory_rtl_0_bypass\(14), + datad => \inst3|memory_rtl_0_bypass\(16), + combout => \inst3|memory~38_combout\); + +-- Location: LCCOMB_X27_Y29_N16 +\inst3|memory~39\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~39_combout\ = (\inst3|memory~37_combout\ & (\inst3|memory~36_combout\ & (\inst3|memory_rtl_0_bypass\(0) & \inst3|memory~38_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory~37_combout\, + datab => \inst3|memory~36_combout\, + datac => \inst3|memory_rtl_0_bypass\(0), + datad => \inst3|memory~38_combout\, + combout => \inst3|memory~39_combout\); + +-- Location: LCCOMB_X35_Y33_N24 +\inst3|stateMM0.Waiting~_wirecell\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|stateMM0.Waiting~_wirecell_combout\ = !\inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000011111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|stateMM0.Waiting~_wirecell_combout\); + +-- Location: IOIBUF_X40_Y34_N8 +\Data[0]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(0), + o => \Data[0]~input_o\); + +-- Location: IOIBUF_X45_Y34_N22 +\Data[1]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(1), + o => \Data[1]~input_o\); + +-- Location: IOIBUF_X45_Y34_N15 +\Data[2]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(2), + o => \Data[2]~input_o\); + +-- Location: IOIBUF_X45_Y34_N8 +\Data[3]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(3), + o => \Data[3]~input_o\); + +-- Location: IOIBUF_X16_Y34_N15 +\Data[4]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(4), + o => \Data[4]~input_o\); + +-- Location: IOIBUF_X16_Y34_N1 +\Data[5]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(5), + o => \Data[5]~input_o\); + +-- Location: IOIBUF_X18_Y34_N22 +\Data[6]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(6), + o => \Data[6]~input_o\); + +-- Location: IOIBUF_X18_Y34_N1 +\Data[7]~input\ : cycloneiii_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => Data(7), + o => \Data[7]~input_o\); + +-- Location: M9K_X33_Y29_N0 +\inst3|memory_rtl_0|auto_generated|ram_block1a0\ : cycloneiii_ram_block +-- pragma translate_off +GENERIC MAP ( + data_interleave_offset_in_bits => 1, + data_interleave_width_in_bits => 1, + logical_ram_name => "RAM:inst3|altsyncram:memory_rtl_0|altsyncram_8bi1:auto_generated|ALTSYNCRAM", + mixed_port_feed_through_mode => "old", + operation_mode => "dual_port", + port_a_address_clear => "none", + port_a_address_width => 8, + port_a_byte_enable_clock => "none", + port_a_data_out_clear => "none", + port_a_data_out_clock => "none", + port_a_data_width => 36, + port_a_first_address => 0, + port_a_first_bit_number => 0, + port_a_last_address => 255, + port_a_logical_ram_depth => 256, + port_a_logical_ram_width => 8, + port_a_read_during_write_mode => "new_data_with_nbe_read", + port_b_address_clear => "none", + port_b_address_clock => "clock0", + port_b_address_width => 8, + port_b_data_out_clear => "none", + port_b_data_out_clock => "none", + port_b_data_width => 36, + port_b_first_address => 0, + port_b_first_bit_number => 0, + port_b_last_address => 255, + port_b_logical_ram_depth => 256, + port_b_logical_ram_width => 8, + port_b_read_during_write_mode => "new_data_with_nbe_read", + port_b_read_enable_clock => "clock0", + ram_block_type => "M9K") +-- pragma translate_on +PORT MAP ( + portawe => \inst3|memory~48_combout\, + portbre => VCC, + portbaddrstall => \inst3|ALT_INV_stateMM0.Waiting~_wirecell_combout\, + clk0 => \FPGA_CLK~inputclkctrl_outclk\, + portadatain => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\, + portaaddr => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\, + portbaddr => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + portbdataout => \inst3|memory_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\); + +-- Location: LCCOMB_X35_Y29_N24 +\inst3|memory_rtl_0_bypass[24]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[24]~feeder_combout\ = \Data[7]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[7]~input_o\, + combout => \inst3|memory_rtl_0_bypass[24]~feeder_combout\); + +-- Location: FF_X35_Y29_N25 +\inst3|memory_rtl_0_bypass[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[24]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(24)); + +-- Location: LCCOMB_X35_Y29_N0 +\inst3|memory~40\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~40_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(24)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a7\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a7\, + datad => \inst3|memory_rtl_0_bypass\(24), + combout => \inst3|memory~40_combout\); + +-- Location: LCCOMB_X27_Y29_N12 +\inst3|Selector4~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector4~0_combout\ = (!\nOE~input_o\ & (!\nCE~input_o\ & (\inst3|ce0Prev~q\ & !\inst3|stateMM0.Waiting~q\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000010000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \nOE~input_o\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector4~0_combout\); + +-- Location: FF_X27_Y29_N13 +\inst3|stateMM0.Reading\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|Selector4~0_combout\, + ena => \inst3|Selector3~2_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|stateMM0.Reading~q\); + +-- Location: LCCOMB_X27_Y29_N26 +\inst3|Selector74~0\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|Selector74~0_combout\ = (\inst3|stateMM0.Reading~q\) # ((!\inst3|stateMM0.Waiting~q\ & ((\nCE~input_o\) # (!\inst3|ce0Prev~q\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010101011101111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|stateMM0.Reading~q\, + datab => \nCE~input_o\, + datac => \inst3|ce0Prev~q\, + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|Selector74~0_combout\); + +-- Location: FF_X35_Y29_N1 +\inst3|data0[7]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~40_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[7]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N16 +\inst3|data0[7]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[7]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[7]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N17 +\inst3|data0[7]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[7]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[7]~en_q\); + +-- Location: LCCOMB_X35_Y29_N26 +\inst3|memory_rtl_0_bypass[23]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[23]~feeder_combout\ = \Data[6]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[6]~input_o\, + combout => \inst3|memory_rtl_0_bypass[23]~feeder_combout\); + +-- Location: FF_X35_Y29_N27 +\inst3|memory_rtl_0_bypass[23]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[23]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(23)); + +-- Location: LCCOMB_X35_Y29_N18 +\inst3|memory~41\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~41_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(23))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a6\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011100010111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(23), + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a6\, + combout => \inst3|memory~41_combout\); + +-- Location: FF_X35_Y29_N19 +\inst3|data0[6]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~41_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[6]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N18 +\inst3|data0[6]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[6]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[6]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N19 +\inst3|data0[6]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[6]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[6]~en_q\); + +-- Location: LCCOMB_X35_Y29_N28 +\inst3|memory_rtl_0_bypass[22]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[22]~feeder_combout\ = \Data[5]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[5]~input_o\, + combout => \inst3|memory_rtl_0_bypass[22]~feeder_combout\); + +-- Location: FF_X35_Y29_N29 +\inst3|memory_rtl_0_bypass[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[22]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(22)); + +-- Location: LCCOMB_X35_Y29_N20 +\inst3|memory~42\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~42_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(22)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a5\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101000001010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0|auto_generated|ram_block1a5\, + datac => \inst3|memory~39_combout\, + datad => \inst3|memory_rtl_0_bypass\(22), + combout => \inst3|memory~42_combout\); + +-- Location: FF_X35_Y29_N21 +\inst3|data0[5]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~42_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[5]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N4 +\inst3|data0[5]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[5]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[5]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N5 +\inst3|data0[5]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[5]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[5]~en_q\); + +-- Location: LCCOMB_X35_Y29_N14 +\inst3|memory_rtl_0_bypass[21]~feeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory_rtl_0_bypass[21]~feeder_combout\ = \Data[4]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \Data[4]~input_o\, + combout => \inst3|memory_rtl_0_bypass[21]~feeder_combout\); + +-- Location: FF_X35_Y29_N15 +\inst3|memory_rtl_0_bypass[21]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory_rtl_0_bypass[21]~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(21)); + +-- Location: LCCOMB_X35_Y29_N30 +\inst3|memory~43\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~43_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(21)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a4\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110001011100010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0|auto_generated|ram_block1a4\, + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0_bypass\(21), + combout => \inst3|memory~43_combout\); + +-- Location: FF_X35_Y29_N31 +\inst3|data0[4]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~43_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[4]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N6 +\inst3|data0[4]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[4]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[4]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N7 +\inst3|data0[4]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[4]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[4]~en_q\); + +-- Location: FF_X35_Y29_N9 +\inst3|memory_rtl_0_bypass[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[3]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(20)); + +-- Location: LCCOMB_X35_Y29_N16 +\inst3|memory~44\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~44_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(20))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a3\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111001111000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0_bypass\(20), + datad => \inst3|memory_rtl_0|auto_generated|ram_block1a3\, + combout => \inst3|memory~44_combout\); + +-- Location: FF_X35_Y29_N17 +\inst3|data0[3]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~44_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[3]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N8 +\inst3|data0[3]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[3]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[3]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N9 +\inst3|data0[3]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[3]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[3]~en_q\); + +-- Location: FF_X35_Y29_N11 +\inst3|memory_rtl_0_bypass[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[2]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(19)); + +-- Location: LCCOMB_X35_Y29_N2 +\inst3|memory~45\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~45_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(19)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a2\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a2\, + datad => \inst3|memory_rtl_0_bypass\(19), + combout => \inst3|memory~45_combout\); + +-- Location: FF_X35_Y29_N3 +\inst3|data0[2]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~45_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[2]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N2 +\inst3|data0[2]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[2]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[2]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N3 +\inst3|data0[2]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[2]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[2]~en_q\); + +-- Location: FF_X35_Y29_N13 +\inst3|memory_rtl_0_bypass[18]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[1]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(18)); + +-- Location: LCCOMB_X35_Y29_N4 +\inst3|memory~46\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~46_combout\ = (\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0_bypass\(18)))) # (!\inst3|memory~39_combout\ & (\inst3|memory_rtl_0|auto_generated|ram_block1a1\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110000110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a1\, + datad => \inst3|memory_rtl_0_bypass\(18), + combout => \inst3|memory~46_combout\); + +-- Location: FF_X35_Y29_N5 +\inst3|data0[1]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~46_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[1]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N20 +\inst3|data0[1]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[1]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[1]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N21 +\inst3|data0[1]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[1]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[1]~en_q\); + +-- Location: FF_X35_Y29_N23 +\inst3|memory_rtl_0_bypass[17]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + asdata => \Data[0]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|memory_rtl_0_bypass\(17)); + +-- Location: LCCOMB_X35_Y29_N6 +\inst3|memory~47\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|memory~47_combout\ = (\inst3|memory~39_combout\ & (\inst3|memory_rtl_0_bypass\(17))) # (!\inst3|memory~39_combout\ & ((\inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1011100010111000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst3|memory_rtl_0_bypass\(17), + datab => \inst3|memory~39_combout\, + datac => \inst3|memory_rtl_0|auto_generated|ram_block1a0~portbdataout\, + combout => \inst3|memory~47_combout\); + +-- Location: FF_X35_Y29_N7 +\inst3|data0[0]~reg0\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|memory~47_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[0]~reg0_q\); + +-- Location: LCCOMB_X35_Y33_N22 +\inst3|data0[0]~enfeeder\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst3|data0[0]~enfeeder_combout\ = \inst3|stateMM0.Waiting~q\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \inst3|stateMM0.Waiting~q\, + combout => \inst3|data0[0]~enfeeder_combout\); + +-- Location: FF_X35_Y33_N23 +\inst3|data0[0]~en\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst3|data0[0]~enfeeder_combout\, + ena => \inst3|Selector74~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3|data0[0]~en_q\); + +-- Location: LCCOMB_X26_Y29_N8 \inst2|counter[0]~24\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[0]~24_combout\ = \inst2|counter\(0) $ (VCC) @@ -334,427 +2343,16 @@ PORT MAP ( -- pragma translate_off GENERIC MAP ( - lut_mask => "0101010110101010", + lut_mask => "0011001111001100", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(0), + datab => \inst2|counter\(0), datad => VCC, combout => \inst2|counter[0]~24_combout\, cout => \inst2|counter[0]~25\); --- Location: FF_X51_Y14_N9 -\inst2|counter[0]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[0]~24_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(0)); - --- Location: LCCOMB_X51_Y14_N10 -\inst2|counter[1]~26\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND))) --- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(1), - datad => VCC, - cin => \inst2|counter[0]~25\, - combout => \inst2|counter[1]~26_combout\, - cout => \inst2|counter[1]~27\); - --- Location: FF_X51_Y14_N11 -\inst2|counter[1]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[1]~26_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(1)); - --- Location: LCCOMB_X51_Y14_N12 -\inst2|counter[2]~28\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC)) --- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(2), - datad => VCC, - cin => \inst2|counter[1]~27\, - combout => \inst2|counter[2]~28_combout\, - cout => \inst2|counter[2]~29\); - --- Location: FF_X51_Y14_N13 -\inst2|counter[2]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[2]~28_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(2)); - --- Location: LCCOMB_X51_Y14_N14 -\inst2|counter[3]~30\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND))) --- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(3), - datad => VCC, - cin => \inst2|counter[2]~29\, - combout => \inst2|counter[3]~30_combout\, - cout => \inst2|counter[3]~31\); - --- Location: FF_X51_Y14_N15 -\inst2|counter[3]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[3]~30_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(3)); - --- Location: LCCOMB_X51_Y14_N16 -\inst2|counter[4]~32\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC)) --- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1010010100001010", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(4), - datad => VCC, - cin => \inst2|counter[3]~31\, - combout => \inst2|counter[4]~32_combout\, - cout => \inst2|counter[4]~33\); - --- Location: FF_X51_Y14_N17 -\inst2|counter[4]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[4]~32_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(4)); - --- Location: LCCOMB_X51_Y14_N18 -\inst2|counter[5]~34\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND))) --- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(5), - datad => VCC, - cin => \inst2|counter[4]~33\, - combout => \inst2|counter[5]~34_combout\, - cout => \inst2|counter[5]~35\); - --- Location: FF_X51_Y14_N19 -\inst2|counter[5]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[5]~34_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(5)); - --- Location: LCCOMB_X51_Y14_N20 -\inst2|counter[6]~36\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC)) --- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(6), - datad => VCC, - cin => \inst2|counter[5]~35\, - combout => \inst2|counter[6]~36_combout\, - cout => \inst2|counter[6]~37\); - --- Location: FF_X51_Y14_N21 -\inst2|counter[6]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[6]~36_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(6)); - --- Location: LCCOMB_X51_Y14_N22 -\inst2|counter[7]~38\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND))) --- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(7), - datad => VCC, - cin => \inst2|counter[6]~37\, - combout => \inst2|counter[7]~38_combout\, - cout => \inst2|counter[7]~39\); - --- Location: FF_X51_Y14_N23 -\inst2|counter[7]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[7]~38_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(7)); - --- Location: LCCOMB_X51_Y14_N24 -\inst2|counter[8]~40\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC)) --- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(8), - datad => VCC, - cin => \inst2|counter[7]~39\, - combout => \inst2|counter[8]~40_combout\, - cout => \inst2|counter[8]~41\); - --- Location: FF_X51_Y14_N25 -\inst2|counter[8]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[8]~40_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(8)); - --- Location: LCCOMB_X51_Y14_N26 -\inst2|counter[9]~42\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND))) --- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0101101001011111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(9), - datad => VCC, - cin => \inst2|counter[8]~41\, - combout => \inst2|counter[9]~42_combout\, - cout => \inst2|counter[9]~43\); - --- Location: FF_X51_Y14_N27 -\inst2|counter[9]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[9]~42_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(9)); - --- Location: LCCOMB_X51_Y14_N28 -\inst2|counter[10]~44\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC)) --- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(10), - datad => VCC, - cin => \inst2|counter[9]~43\, - combout => \inst2|counter[10]~44_combout\, - cout => \inst2|counter[10]~45\); - --- Location: FF_X51_Y14_N29 -\inst2|counter[10]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[10]~44_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(10)); - --- Location: LCCOMB_X51_Y14_N30 -\inst2|counter[11]~46\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND))) --- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0101101001011111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(11), - datad => VCC, - cin => \inst2|counter[10]~45\, - combout => \inst2|counter[11]~46_combout\, - cout => \inst2|counter[11]~47\); - --- Location: FF_X51_Y14_N31 -\inst2|counter[11]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[11]~46_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(11)); - --- Location: LCCOMB_X51_Y13_N0 -\inst2|counter[12]~48\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC)) --- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(12), - datad => VCC, - cin => \inst2|counter[11]~47\, - combout => \inst2|counter[12]~48_combout\, - cout => \inst2|counter[12]~49\); - --- Location: FF_X51_Y13_N1 -\inst2|counter[12]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[12]~48_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(12)); - --- Location: LCCOMB_X51_Y13_N2 +-- Location: LCCOMB_X26_Y28_N2 \inst2|counter[13]~50\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[13]~50_combout\ = (\inst2|counter\(13) & (!\inst2|counter[12]~49\)) # (!\inst2|counter\(13) & ((\inst2|counter[12]~49\) # (GND))) @@ -772,22 +2370,7 @@ PORT MAP ( combout => \inst2|counter[13]~50_combout\, cout => \inst2|counter[13]~51\); --- Location: FF_X51_Y13_N3 -\inst2|counter[13]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \FPGA_CLK~inputclkctrl_outclk\, - d => \inst2|counter[13]~50_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|counter\(13)); - --- Location: LCCOMB_X51_Y13_N4 +-- Location: LCCOMB_X26_Y28_N4 \inst2|counter[14]~52\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[14]~52_combout\ = (\inst2|counter\(14) & (\inst2|counter[13]~51\ $ (GND))) # (!\inst2|counter\(14) & (!\inst2|counter[13]~51\ & VCC)) @@ -805,7 +2388,7 @@ PORT MAP ( combout => \inst2|counter[14]~52_combout\, cout => \inst2|counter[14]~53\); --- Location: FF_X51_Y13_N5 +-- Location: FF_X26_Y28_N5 \inst2|counter[14]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -815,12 +2398,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[14]~52_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(14)); --- Location: LCCOMB_X51_Y13_N6 +-- Location: LCCOMB_X26_Y28_N6 \inst2|counter[15]~54\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[15]~54_combout\ = (\inst2|counter\(15) & (!\inst2|counter[14]~53\)) # (!\inst2|counter\(15) & ((\inst2|counter[14]~53\) # (GND))) @@ -838,7 +2421,7 @@ PORT MAP ( combout => \inst2|counter[15]~54_combout\, cout => \inst2|counter[15]~55\); --- Location: FF_X51_Y13_N7 +-- Location: FF_X26_Y28_N7 \inst2|counter[15]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -848,12 +2431,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[15]~54_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(15)); --- Location: LCCOMB_X51_Y13_N8 +-- Location: LCCOMB_X26_Y28_N8 \inst2|counter[16]~56\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[16]~56_combout\ = (\inst2|counter\(16) & (\inst2|counter[15]~55\ $ (GND))) # (!\inst2|counter\(16) & (!\inst2|counter[15]~55\ & VCC)) @@ -871,7 +2454,7 @@ PORT MAP ( combout => \inst2|counter[16]~56_combout\, cout => \inst2|counter[16]~57\); --- Location: FF_X51_Y13_N9 +-- Location: FF_X26_Y28_N9 \inst2|counter[16]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -881,12 +2464,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[16]~56_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(16)); --- Location: LCCOMB_X51_Y13_N10 +-- Location: LCCOMB_X26_Y28_N10 \inst2|counter[17]~58\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[17]~58_combout\ = (\inst2|counter\(17) & (!\inst2|counter[16]~57\)) # (!\inst2|counter\(17) & ((\inst2|counter[16]~57\) # (GND))) @@ -904,7 +2487,7 @@ PORT MAP ( combout => \inst2|counter[17]~58_combout\, cout => \inst2|counter[17]~59\); --- Location: FF_X51_Y13_N11 +-- Location: FF_X26_Y28_N11 \inst2|counter[17]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -914,29 +2497,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[17]~58_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(17)); --- Location: LCCOMB_X50_Y13_N20 -\inst2|LessThan0~0\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~0_combout\ = ((!\inst2|counter\(15) & (!\inst2|counter\(16) & !\inst2|counter\(14)))) # (!\inst2|counter\(17)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0000111100011111", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(15), - datab => \inst2|counter\(16), - datac => \inst2|counter\(17), - datad => \inst2|counter\(14), - combout => \inst2|LessThan0~0_combout\); - --- Location: LCCOMB_X51_Y13_N12 +-- Location: LCCOMB_X26_Y28_N12 \inst2|counter[18]~60\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[18]~60_combout\ = (\inst2|counter\(18) & (\inst2|counter[17]~59\ $ (GND))) # (!\inst2|counter\(18) & (!\inst2|counter[17]~59\ & VCC)) @@ -954,7 +2520,7 @@ PORT MAP ( combout => \inst2|counter[18]~60_combout\, cout => \inst2|counter[18]~61\); --- Location: FF_X51_Y13_N13 +-- Location: FF_X26_Y28_N13 \inst2|counter[18]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -964,12 +2530,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[18]~60_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(18)); --- Location: LCCOMB_X51_Y13_N14 +-- Location: LCCOMB_X26_Y28_N14 \inst2|counter[19]~62\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[19]~62_combout\ = (\inst2|counter\(19) & (!\inst2|counter[18]~61\)) # (!\inst2|counter\(19) & ((\inst2|counter[18]~61\) # (GND))) @@ -987,7 +2553,7 @@ PORT MAP ( combout => \inst2|counter[19]~62_combout\, cout => \inst2|counter[19]~63\); --- Location: FF_X51_Y13_N15 +-- Location: FF_X26_Y28_N15 \inst2|counter[19]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -997,12 +2563,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[19]~62_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(19)); --- Location: LCCOMB_X51_Y13_N16 +-- Location: LCCOMB_X26_Y28_N16 \inst2|counter[20]~64\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[20]~64_combout\ = (\inst2|counter\(20) & (\inst2|counter[19]~63\ $ (GND))) # (!\inst2|counter\(20) & (!\inst2|counter[19]~63\ & VCC)) @@ -1020,7 +2586,7 @@ PORT MAP ( combout => \inst2|counter[20]~64_combout\, cout => \inst2|counter[20]~65\); --- Location: FF_X51_Y13_N17 +-- Location: FF_X26_Y28_N17 \inst2|counter[20]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1030,12 +2596,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[20]~64_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(20)); --- Location: LCCOMB_X51_Y13_N18 +-- Location: LCCOMB_X26_Y28_N18 \inst2|counter[21]~66\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[21]~66_combout\ = (\inst2|counter\(21) & (!\inst2|counter[20]~65\)) # (!\inst2|counter\(21) & ((\inst2|counter[20]~65\) # (GND))) @@ -1053,7 +2619,7 @@ PORT MAP ( combout => \inst2|counter[21]~66_combout\, cout => \inst2|counter[21]~67\); --- Location: FF_X51_Y13_N19 +-- Location: FF_X26_Y28_N19 \inst2|counter[21]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1063,12 +2629,29 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[21]~66_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(21)); --- Location: LCCOMB_X51_Y13_N20 +-- Location: LCCOMB_X26_Y28_N26 +\inst2|LessThan0~8\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~8_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0111111111111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(18), + datab => \inst2|counter\(20), + datac => \inst2|counter\(19), + datad => \inst2|counter\(21), + combout => \inst2|LessThan0~8_combout\); + +-- Location: LCCOMB_X26_Y28_N20 \inst2|counter[22]~68\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[22]~68_combout\ = (\inst2|counter\(22) & (\inst2|counter[21]~67\ $ (GND))) # (!\inst2|counter\(22) & (!\inst2|counter[21]~67\ & VCC)) @@ -1086,7 +2669,7 @@ PORT MAP ( combout => \inst2|counter[22]~68_combout\, cout => \inst2|counter[22]~69\); --- Location: FF_X51_Y13_N21 +-- Location: FF_X26_Y28_N21 \inst2|counter[22]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1096,12 +2679,12 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[22]~68_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(22)); --- Location: LCCOMB_X51_Y13_N22 +-- Location: LCCOMB_X26_Y28_N22 \inst2|counter[23]~70\ : cycloneiii_lcell_comb -- Equation(s): -- \inst2|counter[23]~70_combout\ = \inst2|counter\(23) $ (\inst2|counter[22]~69\) @@ -1116,7 +2699,7 @@ PORT MAP ( cin => \inst2|counter[22]~69\, combout => \inst2|counter[23]~70_combout\); --- Location: FF_X51_Y13_N23 +-- Location: FF_X26_Y28_N23 \inst2|counter[23]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1126,48 +2709,31 @@ GENERIC MAP ( PORT MAP ( clk => \FPGA_CLK~inputclkctrl_outclk\, d => \inst2|counter[23]~70_combout\, - sclr => \inst2|ALT_INV_LessThan0~8_combout\, + sclr => \inst2|LessThan0~10_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|counter\(23)); --- Location: LCCOMB_X51_Y13_N24 -\inst2|LessThan0~1\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y28_N28 +\inst2|LessThan0~9\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~1_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18)) +-- \inst2|LessThan0~9_combout\ = (\inst2|LessThan0~8_combout\) # ((!\inst2|counter\(22)) # (!\inst2|counter\(23))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0111111111111111", + lut_mask => "1010111111111111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(18), - datab => \inst2|counter\(20), - datac => \inst2|counter\(19), - datad => \inst2|counter\(21), - combout => \inst2|LessThan0~1_combout\); + dataa => \inst2|LessThan0~8_combout\, + datac => \inst2|counter\(23), + datad => \inst2|counter\(22), + combout => \inst2|LessThan0~9_combout\); --- Location: LCCOMB_X51_Y13_N30 +-- Location: LCCOMB_X25_Y23_N18 \inst2|LessThan0~2\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~2_combout\ = ((\inst2|LessThan0~1_combout\) # (!\inst2|counter\(23))) # (!\inst2|counter\(22)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1111111100111111", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - datab => \inst2|counter\(22), - datac => \inst2|counter\(23), - datad => \inst2|LessThan0~1_combout\, - combout => \inst2|LessThan0~2_combout\); - --- Location: LCCOMB_X51_Y14_N4 -\inst2|LessThan0~5\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(9) & (!\inst2|counter\(8) & (!\inst2|counter\(7) & !\inst2|counter\(10)))) +-- \inst2|LessThan0~2_combout\ = (!\inst2|counter\(13) & (!\inst2|counter\(16) & (!\inst2|counter\(15) & !\inst2|counter\(6)))) -- pragma translate_off GENERIC MAP ( @@ -1175,113 +2741,590 @@ GENERIC MAP ( sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(9), - datab => \inst2|counter\(8), - datac => \inst2|counter\(7), - datad => \inst2|counter\(10), - combout => \inst2|LessThan0~5_combout\); + dataa => \inst2|counter\(13), + datab => \inst2|counter\(16), + datac => \inst2|counter\(15), + datad => \inst2|counter\(6), + combout => \inst2|LessThan0~2_combout\); --- Location: LCCOMB_X51_Y14_N0 +-- Location: LCCOMB_X26_Y29_N4 \inst2|LessThan0~3\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(2) & (!\inst2|counter\(4) & ((!\inst2|counter\(1)) # (!\inst2|counter\(0))))) +-- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(7) & (!\inst2|counter\(10) & (!\inst2|counter\(9) & !\inst2|counter\(8)))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000000100010001", + lut_mask => "0000000000000001", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(2), - datab => \inst2|counter\(4), - datac => \inst2|counter\(0), - datad => \inst2|counter\(1), + dataa => \inst2|counter\(7), + datab => \inst2|counter\(10), + datac => \inst2|counter\(9), + datad => \inst2|counter\(8), combout => \inst2|LessThan0~3_combout\); --- Location: LCCOMB_X51_Y14_N6 -\inst2|LessThan0~4\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y29_N0 +\inst2|LessThan0~0\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~4_combout\ = ((\inst2|LessThan0~3_combout\) # ((!\inst2|counter\(4) & !\inst2|counter\(3)))) # (!\inst2|counter\(5)) +-- \inst2|LessThan0~0_combout\ = (!\inst2|counter\(4) & (!\inst2|counter\(2) & ((!\inst2|counter\(0)) # (!\inst2|counter\(1))))) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111111100110111", + lut_mask => "0000000000010011", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(1), + datab => \inst2|counter\(4), + datac => \inst2|counter\(0), + datad => \inst2|counter\(2), + combout => \inst2|LessThan0~0_combout\); + +-- Location: LCCOMB_X26_Y29_N2 +\inst2|LessThan0~1\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~1_combout\ = (\inst2|LessThan0~0_combout\) # (((!\inst2|counter\(4) & !\inst2|counter\(3))) # (!\inst2|counter\(5))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100110111111111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( dataa => \inst2|counter\(4), - datab => \inst2|counter\(5), + datab => \inst2|LessThan0~0_combout\, datac => \inst2|counter\(3), - datad => \inst2|LessThan0~3_combout\, - combout => \inst2|LessThan0~4_combout\); + datad => \inst2|counter\(5), + combout => \inst2|LessThan0~1_combout\); --- Location: LCCOMB_X51_Y14_N2 -\inst2|LessThan0~6\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y29_N6 +\inst2|LessThan0~4\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~6_combout\ = (!\inst2|counter\(11) & (!\inst2|counter\(6) & (\inst2|LessThan0~5_combout\ & \inst2|LessThan0~4_combout\))) +-- \inst2|LessThan0~4_combout\ = (!\inst2|counter\(11) & (\inst2|LessThan0~2_combout\ & (\inst2|LessThan0~3_combout\ & \inst2|LessThan0~1_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0001000000000000", + lut_mask => "0100000000000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( dataa => \inst2|counter\(11), - datab => \inst2|counter\(6), - datac => \inst2|LessThan0~5_combout\, - datad => \inst2|LessThan0~4_combout\, - combout => \inst2|LessThan0~6_combout\); + datab => \inst2|LessThan0~2_combout\, + datac => \inst2|LessThan0~3_combout\, + datad => \inst2|LessThan0~1_combout\, + combout => \inst2|LessThan0~4_combout\); --- Location: LCCOMB_X51_Y13_N28 -\inst2|LessThan0~7\ : cycloneiii_lcell_comb +-- Location: LCCOMB_X26_Y28_N24 +\inst2|LessThan0~6\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|LessThan0~7_combout\ = (\inst2|counter\(16)) # ((\inst2|counter\(13)) # ((\inst2|counter\(12) & !\inst2|LessThan0~6_combout\))) +-- \inst2|LessThan0~6_combout\ = ((!\inst2|counter\(14) & (!\inst2|counter\(16) & !\inst2|counter\(15)))) # (!\inst2|counter\(17)) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111101011111110", + lut_mask => "0101010101010111", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|counter\(16), + dataa => \inst2|counter\(17), + datab => \inst2|counter\(14), + datac => \inst2|counter\(16), + datad => \inst2|counter\(15), + combout => \inst2|LessThan0~6_combout\); + +-- Location: LCCOMB_X26_Y28_N30 +\inst2|LessThan0~10\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~10_combout\ = (!\inst2|LessThan0~5_combout\ & (!\inst2|LessThan0~9_combout\ & (!\inst2|LessThan0~4_combout\ & !\inst2|LessThan0~6_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|LessThan0~5_combout\, + datab => \inst2|LessThan0~9_combout\, + datac => \inst2|LessThan0~4_combout\, + datad => \inst2|LessThan0~6_combout\, + combout => \inst2|LessThan0~10_combout\); + +-- Location: FF_X26_Y29_N9 +\inst2|counter[0]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[0]~24_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(0)); + +-- Location: LCCOMB_X26_Y29_N10 +\inst2|counter[1]~26\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND))) +-- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(1), + datad => VCC, + cin => \inst2|counter[0]~25\, + combout => \inst2|counter[1]~26_combout\, + cout => \inst2|counter[1]~27\); + +-- Location: FF_X26_Y29_N11 +\inst2|counter[1]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[1]~26_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(1)); + +-- Location: LCCOMB_X26_Y29_N12 +\inst2|counter[2]~28\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC)) +-- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010010100001010", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(2), + datad => VCC, + cin => \inst2|counter[1]~27\, + combout => \inst2|counter[2]~28_combout\, + cout => \inst2|counter[2]~29\); + +-- Location: FF_X26_Y29_N13 +\inst2|counter[2]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[2]~28_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(2)); + +-- Location: LCCOMB_X26_Y29_N14 +\inst2|counter[3]~30\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND))) +-- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(3), + datad => VCC, + cin => \inst2|counter[2]~29\, + combout => \inst2|counter[3]~30_combout\, + cout => \inst2|counter[3]~31\); + +-- Location: FF_X26_Y29_N15 +\inst2|counter[3]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[3]~30_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(3)); + +-- Location: LCCOMB_X26_Y29_N16 +\inst2|counter[4]~32\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC)) +-- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(4), + datad => VCC, + cin => \inst2|counter[3]~31\, + combout => \inst2|counter[4]~32_combout\, + cout => \inst2|counter[4]~33\); + +-- Location: FF_X26_Y29_N17 +\inst2|counter[4]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[4]~32_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(4)); + +-- Location: LCCOMB_X26_Y29_N18 +\inst2|counter[5]~34\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND))) +-- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011110000111111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(5), + datad => VCC, + cin => \inst2|counter[4]~33\, + combout => \inst2|counter[5]~34_combout\, + cout => \inst2|counter[5]~35\); + +-- Location: FF_X26_Y29_N19 +\inst2|counter[5]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[5]~34_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(5)); + +-- Location: LCCOMB_X26_Y29_N20 +\inst2|counter[6]~36\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC)) +-- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(6), + datad => VCC, + cin => \inst2|counter[5]~35\, + combout => \inst2|counter[6]~36_combout\, + cout => \inst2|counter[6]~37\); + +-- Location: FF_X26_Y29_N21 +\inst2|counter[6]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[6]~36_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(6)); + +-- Location: LCCOMB_X26_Y29_N22 +\inst2|counter[7]~38\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND))) +-- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(7), + datad => VCC, + cin => \inst2|counter[6]~37\, + combout => \inst2|counter[7]~38_combout\, + cout => \inst2|counter[7]~39\); + +-- Location: FF_X26_Y29_N23 +\inst2|counter[7]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[7]~38_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(7)); + +-- Location: LCCOMB_X26_Y29_N24 +\inst2|counter[8]~40\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC)) +-- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(8), + datad => VCC, + cin => \inst2|counter[7]~39\, + combout => \inst2|counter[8]~40_combout\, + cout => \inst2|counter[8]~41\); + +-- Location: FF_X26_Y29_N25 +\inst2|counter[8]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[8]~40_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(8)); + +-- Location: LCCOMB_X26_Y29_N26 +\inst2|counter[9]~42\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND))) +-- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(9), + datad => VCC, + cin => \inst2|counter[8]~41\, + combout => \inst2|counter[9]~42_combout\, + cout => \inst2|counter[9]~43\); + +-- Location: FF_X26_Y29_N27 +\inst2|counter[9]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[9]~42_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(9)); + +-- Location: LCCOMB_X26_Y29_N28 +\inst2|counter[10]~44\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC)) +-- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|counter\(10), + datad => VCC, + cin => \inst2|counter[9]~43\, + combout => \inst2|counter[10]~44_combout\, + cout => \inst2|counter[10]~45\); + +-- Location: FF_X26_Y29_N29 +\inst2|counter[10]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[10]~44_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(10)); + +-- Location: LCCOMB_X26_Y29_N30 +\inst2|counter[11]~46\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND))) +-- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(11), + datad => VCC, + cin => \inst2|counter[10]~45\, + combout => \inst2|counter[11]~46_combout\, + cout => \inst2|counter[11]~47\); + +-- Location: FF_X26_Y29_N31 +\inst2|counter[11]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[11]~46_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(11)); + +-- Location: LCCOMB_X26_Y28_N0 +\inst2|counter[12]~48\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC)) +-- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( datab => \inst2|counter\(12), - datac => \inst2|counter\(13), + datad => VCC, + cin => \inst2|counter[11]~47\, + combout => \inst2|counter[12]~48_combout\, + cout => \inst2|counter[12]~49\); + +-- Location: FF_X26_Y28_N1 +\inst2|counter[12]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[12]~48_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(12)); + +-- Location: FF_X26_Y28_N3 +\inst2|counter[13]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \FPGA_CLK~inputclkctrl_outclk\, + d => \inst2|counter[13]~50_combout\, + sclr => \inst2|LessThan0~10_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|counter\(13)); + +-- Location: LCCOMB_X25_Y23_N4 +\inst2|LessThan0~5\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(13) & (!\inst2|counter\(15) & (!\inst2|counter\(12) & !\inst2|counter\(16)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|counter\(13), + datab => \inst2|counter\(15), + datac => \inst2|counter\(12), + datad => \inst2|counter\(16), + combout => \inst2|LessThan0~5_combout\); + +-- Location: LCCOMB_X25_Y23_N6 +\inst2|LessThan0~7\ : cycloneiii_lcell_comb +-- Equation(s): +-- \inst2|LessThan0~7_combout\ = (\inst2|LessThan0~5_combout\) # (\inst2|LessThan0~6_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datac => \inst2|LessThan0~5_combout\, datad => \inst2|LessThan0~6_combout\, combout => \inst2|LessThan0~7_combout\); --- Location: LCCOMB_X51_Y13_N26 -\inst2|LessThan0~8\ : cycloneiii_lcell_comb --- Equation(s): --- \inst2|LessThan0~8_combout\ = (\inst2|LessThan0~0_combout\) # ((\inst2|LessThan0~2_combout\) # ((!\inst2|counter\(15) & !\inst2|LessThan0~7_combout\))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1111110011111101", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|counter\(15), - datab => \inst2|LessThan0~0_combout\, - datac => \inst2|LessThan0~2_combout\, - datad => \inst2|LessThan0~7_combout\, - combout => \inst2|LessThan0~8_combout\); - --- Location: LCCOMB_X52_Y13_N0 +-- Location: LCCOMB_X25_Y23_N8 \inst2|ledBuf~0\ : cycloneiii_lcell_comb -- Equation(s): --- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (!\inst2|LessThan0~8_combout\) +-- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (((!\inst2|LessThan0~7_combout\ & (!\inst2|LessThan0~9_combout\ & !\inst2|LessThan0~4_combout\)))) -- pragma translate_off GENERIC MAP ( - lut_mask => "1111000000001111", + lut_mask => "1111000011100001", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( + dataa => \inst2|LessThan0~7_combout\, + datab => \inst2|LessThan0~9_combout\, datac => \inst2|ledBuf~q\, - datad => \inst2|LessThan0~8_combout\, + datad => \inst2|LessThan0~4_combout\, combout => \inst2|ledBuf~0_combout\); --- Location: FF_X52_Y13_N1 +-- Location: FF_X25_Y23_N9 \inst2|ledBuf\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1295,232 +3338,124 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|ledBuf~q\); --- Location: IOIBUF_X38_Y34_N1 -\Address[7]~input\ : cycloneiii_io_ibuf +-- Location: PLL_1 +\inst|altpll_component|auto_generated|pll1\ : cycloneiii_pll -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + auto_settings => "false", + bandwidth_type => "medium", + c0_high => 3, + c0_initial => 1, + c0_low => 3, + c0_mode => "even", + c0_ph => 0, + c1_high => 2, + c1_initial => 1, + c1_low => 1, + c1_mode => "odd", + c1_ph => 0, + c1_use_casc_in => "off", + c2_high => 0, + c2_initial => 0, + c2_low => 0, + c2_mode => "bypass", + c2_ph => 0, + c2_use_casc_in => "off", + c3_high => 0, + c3_initial => 0, + c3_low => 0, + c3_mode => "bypass", + c3_ph => 0, + c3_use_casc_in => "off", + c4_high => 0, + c4_initial => 0, + c4_low => 0, + c4_mode => "bypass", + c4_ph => 0, + c4_use_casc_in => "off", + charge_pump_current_bits => 1, + clk0_counter => "c0", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 4, + clk0_phase_shift => "0", + clk1_counter => "c1", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 8, + clk1_phase_shift => "0", + clk2_counter => "unused", + clk2_divide_by => 0, + clk2_duty_cycle => 50, + clk2_multiply_by => 0, + clk2_phase_shift => "0", + clk3_counter => "unused", + clk3_divide_by => 0, + clk3_duty_cycle => 50, + clk3_multiply_by => 0, + clk3_phase_shift => "0", + clk4_counter => "unused", + clk4_divide_by => 0, + clk4_duty_cycle => 50, + clk4_multiply_by => 0, + clk4_phase_shift => "0", + compensate_clock => "clock0", + inclk0_input_frequency => 40000, + inclk1_input_frequency => 0, + loop_filter_c_bits => 0, + loop_filter_r_bits => 24, + m => 24, + m_initial => 1, + m_ph => 0, + n => 1, + operation_mode => "normal", + pfd_max => 200000, + pfd_min => 3076, + pll_compensation_delay => 3418, + self_reset_on_loss_lock => "off", + simulation_type => "timing", + switch_over_type => "auto", + vco_center => 1538, + vco_divide_by => 0, + vco_frequency_control => "auto", + vco_max => 3333, + vco_min => 1538, + vco_multiply_by => 0, + vco_phase_shift_step => 208, + vco_post_scale => 2) -- pragma translate_on PORT MAP ( - i => ww_Address(7), - o => \Address[7]~input_o\); + areset => GND, + fbin => \inst|altpll_component|auto_generated|wire_pll1_fbout\, + inclk => \inst|altpll_component|auto_generated|pll1_INCLK_bus\, + fbout => \inst|altpll_component|auto_generated|wire_pll1_fbout\, + clk => \inst|altpll_component|auto_generated|pll1_CLK_bus\); --- Location: IOIBUF_X14_Y34_N8 -\Address[6]~input\ : cycloneiii_io_ibuf +-- Location: CLKCTRL_G3 +\inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + clock_type => "global clock", + ena_register_mode => "none") -- pragma translate_on PORT MAP ( - i => ww_Address(6), - o => \Address[6]~input_o\); + inclk => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk\); --- Location: IOIBUF_X7_Y34_N15 -\Address[5]~input\ : cycloneiii_io_ibuf +-- Location: CLKCTRL_G4 +\inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl\ : cycloneiii_clkctrl -- pragma translate_off GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") + clock_type => "global clock", + ena_register_mode => "none") -- pragma translate_on PORT MAP ( - i => ww_Address(5), - o => \Address[5]~input_o\); - --- Location: IOIBUF_X14_Y34_N22 -\Address[4]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(4), - o => \Address[4]~input_o\); - --- Location: IOIBUF_X7_Y34_N1 -\Address[3]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(3), - o => \Address[3]~input_o\); - --- Location: IOIBUF_X7_Y34_N8 -\Address[2]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(2), - o => \Address[2]~input_o\); - --- Location: IOIBUF_X14_Y34_N15 -\Address[1]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(1), - o => \Address[1]~input_o\); - --- Location: IOIBUF_X38_Y34_N15 -\Address[0]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_Address(0), - o => \Address[0]~input_o\); - --- Location: IOIBUF_X20_Y34_N1 -\nOE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nOE, - o => \nOE~input_o\); - --- Location: IOIBUF_X20_Y34_N8 -\nWE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nWE, - o => \nWE~input_o\); - --- Location: IOIBUF_X20_Y34_N15 -\nCE~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => ww_nCE, - o => \nCE~input_o\); - --- Location: IOIBUF_X18_Y34_N1 -\Data[7]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(7), - o => \Data[7]~input_o\); - --- Location: IOIBUF_X18_Y34_N22 -\Data[6]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(6), - o => \Data[6]~input_o\); - --- Location: IOIBUF_X16_Y34_N1 -\Data[5]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(5), - o => \Data[5]~input_o\); - --- Location: IOIBUF_X16_Y34_N15 -\Data[4]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(4), - o => \Data[4]~input_o\); - --- Location: IOIBUF_X45_Y34_N8 -\Data[3]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(3), - o => \Data[3]~input_o\); - --- Location: IOIBUF_X45_Y34_N15 -\Data[2]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(2), - o => \Data[2]~input_o\); - --- Location: IOIBUF_X45_Y34_N22 -\Data[1]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(1), - o => \Data[1]~input_o\); - --- Location: IOIBUF_X40_Y34_N8 -\Data[0]~input\ : cycloneiii_io_ibuf --- pragma translate_off -GENERIC MAP ( - bus_hold => "false", - simulate_z_as => "z") --- pragma translate_on -PORT MAP ( - i => Data(0), - o => \Data[0]~input_o\); - -ww_FPGA_LED_1 <= \FPGA_LED_1~output_o\; - -Data(7) <= \Data[7]~output_o\; - -Data(6) <= \Data[6]~output_o\; - -Data(5) <= \Data[5]~output_o\; - -Data(4) <= \Data[4]~output_o\; - -Data(3) <= \Data[3]~output_o\; - -Data(2) <= \Data[2]~output_o\; - -Data(1) <= \Data[1]~output_o\; - -Data(0) <= \Data[0]~output_o\; + inclk => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk\); END structure; diff --git a/MainController/simulation/modelsim/MainController_min_1200mv_0c_vhd_fast.sdo b/MainController/simulation/modelsim/MainController_min_1200mv_0c_vhd_fast.sdo index ac15010..311eaa2 100644 --- a/MainController/simulation/modelsim/MainController_min_1200mv_0c_vhd_fast.sdo +++ b/MainController/simulation/modelsim/MainController_min_1200mv_0c_vhd_fast.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "MainController") - (DATE "03/12/2024 16:24:29") + (DATE "03/12/2024 17:46:57") (VENDOR "Altera") (PROGRAM "Quartus II 64-Bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version") @@ -41,11 +41,127 @@ (INSTANCE \\FPGA_LED_1\~output\\) (DELAY (ABSOLUTE - (PORT i (677:677:677) (604:604:604)) + (PORT i (999:999:999) (882:882:882)) (IOPATH i o (1309:1309:1309) (1354:1354:1354)) ) ) ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\FPGA_LED_2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (767:767:767) (796:796:796)) + (IOPATH i o (1442:1442:1442) (1378:1378:1378)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\FPGA_LED_3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (766:766:766) (796:796:796)) + (IOPATH i o (1442:1442:1442) (1378:1378:1378)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[7\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (800:800:800) (917:917:917)) + (PORT oe (800:800:800) (910:910:910)) + (IOPATH i o (1377:1377:1377) (1324:1324:1324)) + (IOPATH oe o (2177:2177:2177) (2158:2158:2158)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[6\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (673:673:673) (784:784:784)) + (PORT oe (756:756:756) (893:893:893)) + (IOPATH i o (2906:2906:2906) (2614:2614:2614)) + (IOPATH oe o (2177:2177:2177) (2158:2158:2158)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[5\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1051:1051:1051) (1197:1197:1197)) + (PORT oe (911:911:911) (1044:1044:1044)) + (IOPATH i o (1377:1377:1377) (1324:1324:1324)) + (IOPATH oe o (2177:2177:2177) (2158:2158:2158)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[4\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1155:1155:1155) (1330:1330:1330)) + (PORT oe (904:904:904) (1046:1046:1046)) + (IOPATH i o (1377:1377:1377) (1324:1324:1324)) + (IOPATH oe o (2177:2177:2177) (2158:2158:2158)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[3\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (657:657:657) (730:730:730)) + (PORT oe (604:604:604) (680:680:680)) + (IOPATH i o (1397:1397:1397) (1344:1344:1344)) + (IOPATH oe o (2197:2197:2197) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[2\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (691:691:691) (778:778:778)) + (PORT oe (581:581:581) (658:658:658)) + (IOPATH i o (1397:1397:1397) (1344:1344:1344)) + (IOPATH oe o (2197:2197:2197) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[1\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (636:636:636) (708:708:708)) + (PORT oe (613:613:613) (686:686:686)) + (IOPATH i o (1397:1397:1397) (1344:1344:1344)) + (IOPATH oe o (2197:2197:2197) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[0\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (525:525:525) (594:594:594)) + (PORT oe (482:482:482) (538:538:538)) + (IOPATH i o (1387:1387:1387) (1334:1334:1334)) + (IOPATH oe o (2187:2187:2187) (2168:2168:2168)) + ) + ) + ) (CELL (CELLTYPE "cycloneiii_io_ibuf") (INSTANCE \\FPGA_CLK\~input\\) @@ -64,394 +180,1818 @@ ) ) ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nCE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (323:323:323) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[5\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (353:353:353) (912:912:912)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|ce0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (933:933:933)) + (PORT asdata (2271:2271:2271) (2568:2568:2568)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~5\\) + (DELAY + (ABSOLUTE + (PORT datab (2024:2024:2024) (2305:2305:2305)) + (PORT datac (2107:2107:2107) (2388:2388:2388)) + (PORT datad (794:794:794) (904:904:904)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[12\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (463:463:463) (532:532:532)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nWE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (323:323:323) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|we0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (933:933:933)) + (PORT asdata (2053:2053:2053) (2275:2275:2275)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nOE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (323:323:323) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~3\\) + (DELAY + (ABSOLUTE + (PORT dataa (1939:1939:1939) (2201:2201:2201)) + (PORT datab (2108:2108:2108) (2408:2408:2408)) + (PORT datac (143:143:143) (192:192:192)) + (PORT datad (241:241:241) (296:296:296)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~2\\) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (326:326:326)) + (PORT datab (2113:2113:2113) (2414:2414:2414)) + (PORT datad (98:98:98) (117:117:117)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Writing\\) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (933:933:933)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (608:608:608) (661:661:661)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~48\\) + (DELAY + (ABSOLUTE + (PORT datab (1890:1890:1890) (2122:2122:2122)) + (PORT datad (220:220:220) (269:269:269)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|oe0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (933:933:933)) + (PORT asdata (2295:2295:2295) (2597:2597:2597)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2140:2140:2140) (2446:2446:2446)) + (PORT datad (220:220:220) (268:268:268)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (266:266:266)) + (PORT datab (2106:2106:2106) (2406:2406:2406)) + (PORT datad (93:93:93) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (162:162:162) (217:217:217)) + (PORT datab (2107:2107:2107) (2407:2407:2407)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Waiting\\) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (933:933:933)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[12\]\\) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (926:926:926)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1867:1867:1867) (1696:1696:1696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[11\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (506:506:506) (589:589:589)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[11\]\\) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (926:926:926)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[4\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (353:353:353) (912:912:912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~4\\) + (DELAY + (ABSOLUTE + (PORT datab (2028:2028:2028) (2310:2310:2310)) + (PORT datac (2004:2004:2004) (2289:2289:2289)) + (PORT datad (787:787:787) (896:896:896)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[10\]\\) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (926:926:926)) + (PORT asdata (653:653:653) (726:726:726)) + (PORT ena (1867:1867:1867) (1696:1696:1696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[9\]\\) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (926:926:926)) + (PORT asdata (688:688:688) (775:775:775)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~37\\) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[2\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (353:353:353) (912:912:912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~2\\) + (DELAY + (ABSOLUTE + (PORT datab (2025:2025:2025) (2308:2308:2308)) + (PORT datac (2129:2129:2129) (2414:2414:2414)) + (PORT datad (788:788:788) (897:897:897)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[6\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (103:103:103) (120:120:120)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[6\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[3\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (353:353:353) (912:912:912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~3\\) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (932:932:932)) + (PORT datab (2119:2119:2119) (2404:2404:2404)) + (PORT datad (2005:2005:2005) (2280:2280:2280)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[7\]\\) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (933:933:933)) + (PORT asdata (978:978:978) (1122:1122:1122)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (933:933:933)) + (PORT asdata (977:977:977) (1101:1101:1101)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[8\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT asdata (282:282:282) (301:301:301)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~35\\) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (961:961:961)) + (PORT datab (132:132:132) (181:181:181)) + (PORT datad (772:772:772) (902:902:902)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[0\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (333:333:333) (892:892:892)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (929:929:929)) + (PORT datab (2024:2024:2024) (2306:2306:2306)) + (PORT datac (1900:1900:1900) (2136:2136:2136)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[2\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (103:103:103) (121:121:121)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[1\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (343:343:343) (902:902:902)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2026:2026:2026) (2308:2308:2308)) + (PORT datab (2027:2027:2027) (2310:2310:2310)) + (PORT datad (787:787:787) (896:896:896)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (933:933:933)) + (PORT asdata (1015:1015:1015) (1167:1167:1167)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (933:933:933)) + (PORT asdata (952:952:952) (1075:1075:1075)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[4\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (105:105:105) (122:122:122)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~34\\) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (893:893:893)) + (PORT datab (131:131:131) (180:180:180)) + (PORT datad (768:768:768) (877:877:877)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~36\\) + (DELAY + (ABSOLUTE + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (933:933:933)) + (PORT asdata (383:383:383) (414:414:414)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[7\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (333:333:333) (892:892:892)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~7\\) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (929:929:929)) + (PORT datab (2025:2025:2025) (2307:2307:2307)) + (PORT datad (1906:1906:1906) (2152:2152:2152)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[7\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[15\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT asdata (307:307:307) (346:346:346)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[6\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (343:343:343) (902:902:902)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~6\\) + (DELAY + (ABSOLUTE + (PORT dataa (2002:2002:2002) (2268:2268:2268)) + (PORT datab (2025:2025:2025) (2306:2306:2306)) + (PORT datad (793:793:793) (903:903:903)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[6\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[13\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (130:130:130) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[13\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[14\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT asdata (344:344:344) (370:370:370)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[16\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (163:163:163) (190:190:190)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[16\]\\) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1557:1557:1557) (1425:1425:1425)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~38\\) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~39\\) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (707:707:707)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datad (750:750:750) (848:848:848)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|stateMM0\.Waiting\~_wirecell\\) + (DELAY + (ABSOLUTE + (PORT datad (655:655:655) (750:750:750)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[0\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (343:343:343) (902:902:902)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[1\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (353:353:353) (912:912:912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[2\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (353:353:353) (912:912:912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[3\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (353:353:353) (912:912:912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[4\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (333:333:333) (892:892:892)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[5\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (333:333:333) (892:892:892)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[6\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (333:333:333) (892:892:892)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[7\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (333:333:333) (892:892:892)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1910:1910:1910) (2155:2155:2155)) + (PORT d[1] (1999:1999:1999) (2265:2265:2265)) + (PORT d[2] (2121:2121:2121) (2408:2408:2408)) + (PORT d[3] (2111:2111:2111) (2384:2384:2384)) + (PORT d[4] (1990:1990:1990) (2257:2257:2257)) + (PORT d[5] (2029:2029:2029) (2297:2297:2297)) + (PORT d[6] (1996:1996:1996) (2244:2244:2244)) + (PORT d[7] (2132:2132:2132) (2400:2400:2400)) + (PORT clk (1111:1111:1111) (1130:1130:1130)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (883:883:883) (1003:1003:1003)) + (PORT d[1] (872:872:872) (1006:1006:1006)) + (PORT d[2] (662:662:662) (768:768:768)) + (PORT d[3] (884:884:884) (1027:1027:1027)) + (PORT d[4] (621:621:621) (705:705:705)) + (PORT d[5] (588:588:588) (690:690:690)) + (PORT d[6] (839:839:839) (955:955:955)) + (PORT d[7] (692:692:692) (798:798:798)) + (PORT clk (1109:1109:1109) (1128:1128:1128)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (623:623:623) (641:641:641)) + (PORT clk (1109:1109:1109) (1128:1128:1128)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1111:1111:1111) (1130:1130:1130)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2124:2124:2124) (2143:2143:2143)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1112:1112:1112) (1131:1131:1131)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1112:1112:1112) (1131:1131:1131)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1112:1112:1112) (1131:1131:1131)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (535:535:535) (611:611:611)) + (PORT d[1] (565:565:565) (644:644:644)) + (PORT d[2] (550:550:550) (628:628:628)) + (PORT d[3] (555:555:555) (634:634:634)) + (PORT d[4] (504:504:504) (577:577:577)) + (PORT d[5] (682:682:682) (780:780:780)) + (PORT d[6] (529:529:529) (611:611:611)) + (PORT d[7] (532:532:532) (602:602:602)) + (PORT clk (1111:1111:1111) (1130:1130:1130)) + (PORT stall (753:753:753) (713:713:713)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + (HOLD stall (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1111:1111:1111) (1130:1130:1130)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1112:1112:1112) (1131:1131:1131)) + (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1112:1112:1112) (1131:1131:1131)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1112:1112:1112) (1131:1131:1131)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[24\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1949:1949:1949) (2197:2197:2197)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[24\]\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~40\\) + (DELAY + (ABSOLUTE + (PORT datab (481:481:481) (554:554:554)) + (PORT datac (309:309:309) (352:352:352)) + (PORT datad (120:120:120) (157:157:157)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector4\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (1938:1938:1938) (2200:2200:2200)) + (PORT datab (2107:2107:2107) (2407:2407:2407)) + (PORT datac (144:144:144) (195:195:195)) + (PORT datad (240:240:240) (293:293:293)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Reading\\) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (933:933:933)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (608:608:608) (661:661:661)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector74\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (183:183:183)) + (PORT datab (2112:2112:2112) (2412:2412:2412)) + (PORT datac (140:140:140) (188:188:188)) + (PORT datad (244:244:244) (298:298:298)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[7\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1564:1564:1564) (1724:1724:1724)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[7\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (654:654:654) (749:749:749)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[7\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (932:932:932)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1277:1277:1277) (1403:1403:1403)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[23\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1939:1939:1939) (2184:2184:2184)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[23\]\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~41\\) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (183:183:183)) + (PORT datab (480:480:480) (558:558:558)) + (PORT datac (284:284:284) (317:317:317)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[6\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1564:1564:1564) (1724:1724:1724)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[6\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (653:653:653) (748:748:748)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[6\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (932:932:932)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1277:1277:1277) (1403:1403:1403)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[22\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1989:1989:1989) (2247:2247:2247)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[22\]\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~42\\) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (636:636:636)) + (PORT datac (464:464:464) (536:536:536)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[5\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1564:1564:1564) (1724:1724:1724)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[5\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (650:650:650) (740:740:740)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[5\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (932:932:932)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1277:1277:1277) (1403:1403:1403)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[21\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1962:1962:1962) (2223:2223:2223)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[21\]\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~43\\) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (382:382:382)) + (PORT datab (481:481:481) (555:555:555)) + (PORT datac (117:117:117) (160:160:160)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[4\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1564:1564:1564) (1724:1724:1724)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[4\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (651:651:651) (742:742:742)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[4\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (932:932:932)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1277:1277:1277) (1403:1403:1403)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[20\]\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT asdata (2106:2106:2106) (2356:2356:2356)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~44\\) + (DELAY + (ABSOLUTE + (PORT datab (480:480:480) (555:555:555)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (303:303:303) (341:341:341)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[3\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1564:1564:1564) (1724:1724:1724)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[3\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (652:652:652) (742:742:742)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[3\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (932:932:932)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1277:1277:1277) (1403:1403:1403)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[19\]\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT asdata (2109:2109:2109) (2370:2370:2370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~45\\) + (DELAY + (ABSOLUTE + (PORT datab (481:481:481) (553:553:553)) + (PORT datac (287:287:287) (321:321:321)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[2\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1564:1564:1564) (1724:1724:1724)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[2\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (649:649:649) (744:744:744)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[2\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (932:932:932)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1277:1277:1277) (1403:1403:1403)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[18\]\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT asdata (2125:2125:2125) (2388:2388:2388)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~46\\) + (DELAY + (ABSOLUTE + (PORT datab (479:479:479) (553:553:553)) + (PORT datac (280:280:280) (312:312:312)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[1\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1564:1564:1564) (1724:1724:1724)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[1\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (654:654:654) (749:749:749)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[1\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (932:932:932)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1277:1277:1277) (1403:1403:1403)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[17\]\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT asdata (2002:2002:2002) (2212:2212:2212)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~47\\) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (183:183:183)) + (PORT datab (479:479:479) (553:553:553)) + (PORT datac (297:297:297) (336:336:336)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[0\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1564:1564:1564) (1724:1724:1724)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[0\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (655:655:655) (751:751:751)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[0\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (927:927:927) (932:932:932)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1277:1277:1277) (1403:1403:1403)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[0\]\~24\\) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (266:266:266)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[0\]\\) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[1\]\~26\\) - (DELAY - (ABSOLUTE - (PORT datab (212:212:212) (265:265:265)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (135:135:135) (183:183:183)) + (IOPATH datab combout (192:192:192) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[1\]\\) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[2\]\~28\\) - (DELAY - (ABSOLUTE - (PORT datab (209:209:209) (265:265:265)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[2\]\\) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[3\]\~30\\) - (DELAY - (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[3\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1115:1115:1115) (1150:1150:1150)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[4\]\~32\\) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (273:273:273)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[4\]\\) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[5\]\~34\\) - (DELAY - (ABSOLUTE - (PORT datab (134:134:134) (185:185:185)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[5\]\\) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[6\]\~36\\) - (DELAY - (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[6\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1115:1115:1115) (1150:1150:1150)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[7\]\~38\\) - (DELAY - (ABSOLUTE - (PORT datab (211:211:211) (265:265:265)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[7\]\\) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[8\]\~40\\) - (DELAY - (ABSOLUTE - (PORT datab (134:134:134) (183:183:183)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[8\]\\) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[9\]\~42\\) - (DELAY - (ABSOLUTE - (PORT dataa (135:135:135) (187:187:187)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[9\]\\) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[10\]\~44\\) - (DELAY - (ABSOLUTE - (PORT datab (133:133:133) (182:182:182)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[10\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1115:1115:1115) (1150:1150:1150)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[11\]\~46\\) - (DELAY - (ABSOLUTE - (PORT dataa (134:134:134) (187:187:187)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[11\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1115:1115:1115) (1150:1150:1150)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (612:612:612) (611:611:611)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[12\]\~48\\) - (DELAY - (ABSOLUTE - (PORT datab (133:133:133) (183:183:183)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[12\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1115:1115:1115) (1151:1151:1151)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[13\]\~50\\) @@ -466,28 +2006,12 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[13\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1115:1115:1115) (1151:1151:1151)) - (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[14\]\~52\\) (DELAY (ABSOLUTE - (PORT datab (141:141:141) (189:189:189)) + (PORT datab (134:134:134) (184:184:184)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -501,9 +2025,9 @@ (INSTANCE \\inst2\|counter\[14\]\\) (DELAY (ABSOLUTE - (PORT clk (1115:1115:1115) (1151:1151:1151)) + (PORT clk (920:920:920) (926:926:926)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) + (PORT sclr (334:334:334) (387:387:387)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -517,7 +2041,7 @@ (INSTANCE \\inst2\|counter\[15\]\~54\\) (DELAY (ABSOLUTE - (PORT dataa (147:147:147) (199:199:199)) + (PORT dataa (146:146:146) (198:198:198)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -531,9 +2055,9 @@ (INSTANCE \\inst2\|counter\[15\]\\) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) + (PORT clk (920:920:920) (926:926:926)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) + (PORT sclr (334:334:334) (387:387:387)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -547,7 +2071,7 @@ (INSTANCE \\inst2\|counter\[16\]\~56\\) (DELAY (ABSOLUTE - (PORT datab (142:142:142) (189:189:189)) + (PORT datab (147:147:147) (196:196:196)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -561,9 +2085,9 @@ (INSTANCE \\inst2\|counter\[16\]\\) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) + (PORT clk (920:920:920) (926:926:926)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) + (PORT sclr (334:334:334) (387:387:387)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -577,7 +2101,7 @@ (INSTANCE \\inst2\|counter\[17\]\~58\\) (DELAY (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) + (PORT dataa (136:136:136) (189:189:189)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -591,9 +2115,9 @@ (INSTANCE \\inst2\|counter\[17\]\\) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) + (PORT clk (920:920:920) (926:926:926)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) + (PORT sclr (334:334:334) (387:387:387)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -602,22 +2126,6 @@ (HOLD sclr (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~0\\) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (397:397:397)) - (PORT datab (233:233:233) (291:291:291)) - (PORT datac (200:200:200) (249:249:249)) - (PORT datad (212:212:212) (260:260:260)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[18\]\~60\\) @@ -637,9 +2145,9 @@ (INSTANCE \\inst2\|counter\[18\]\\) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (925:925:925)) + (PORT clk (920:920:920) (926:926:926)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) + (PORT sclr (334:334:334) (387:387:387)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -667,9 +2175,9 @@ (INSTANCE \\inst2\|counter\[19\]\\) (DELAY (ABSOLUTE - (PORT clk (1115:1115:1115) (1151:1151:1151)) + (PORT clk (920:920:920) (926:926:926)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) + (PORT sclr (334:334:334) (387:387:387)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -697,9 +2205,9 @@ (INSTANCE \\inst2\|counter\[20\]\\) (DELAY (ABSOLUTE - (PORT clk (1115:1115:1115) (1151:1151:1151)) + (PORT clk (920:920:920) (926:926:926)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) + (PORT sclr (334:334:334) (387:387:387)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -727,9 +2235,9 @@ (INSTANCE \\inst2\|counter\[21\]\\) (DELAY (ABSOLUTE - (PORT clk (1115:1115:1115) (1151:1151:1151)) + (PORT clk (920:920:920) (926:926:926)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) + (PORT sclr (334:334:334) (387:387:387)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -738,12 +2246,28 @@ (HOLD sclr (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~8\\) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (191:191:191)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (122:122:122) (166:166:166)) + (PORT datad (122:122:122) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[22\]\~68\\) (DELAY (ABSOLUTE - (PORT datab (135:135:135) (186:186:186)) + (PORT datab (135:135:135) (185:185:185)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -757,9 +2281,9 @@ (INSTANCE \\inst2\|counter\[22\]\\) (DELAY (ABSOLUTE - (PORT clk (1115:1115:1115) (1151:1151:1151)) + (PORT clk (920:920:920) (926:926:926)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) + (PORT sclr (334:334:334) (387:387:387)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -773,7 +2297,7 @@ (INSTANCE \\inst2\|counter\[23\]\~70\\) (DELAY (ABSOLUTE - (PORT dataa (303:303:303) (368:368:368)) + (PORT dataa (136:136:136) (188:188:188)) (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -784,9 +2308,9 @@ (INSTANCE \\inst2\|counter\[23\]\\) (DELAY (ABSOLUTE - (PORT clk (1115:1115:1115) (1151:1151:1151)) + (PORT clk (920:920:920) (926:926:926)) (PORT d (37:37:37) (50:50:50)) - (PORT sclr (348:348:348) (372:372:372)) + (PORT sclr (334:334:334) (387:387:387)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -797,15 +2321,13 @@ ) (CELL (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~1\\) + (INSTANCE \\inst2\|LessThan0\~9\\) (DELAY (ABSOLUTE - (PORT dataa (138:138:138) (190:190:190)) - (PORT datab (135:135:135) (184:184:184)) + (PORT dataa (103:103:103) (134:134:134)) (PORT datac (122:122:122) (164:164:164)) - (PORT datad (122:122:122) (160:160:160)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -816,24 +2338,10 @@ (INSTANCE \\inst2\|LessThan0\~2\\) (DELAY (ABSOLUTE - (PORT datab (135:135:135) (184:184:184)) - (PORT datac (289:289:289) (344:344:344)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~5\\) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (190:190:190)) - (PORT datab (137:137:137) (186:186:186)) - (PORT datac (130:130:130) (170:170:170)) - (PORT datad (124:124:124) (162:162:162)) + (PORT dataa (545:545:545) (652:652:652)) + (PORT datab (545:545:545) (636:636:636)) + (PORT datac (535:535:535) (630:630:630)) + (PORT datad (531:531:531) (619:619:619)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -846,12 +2354,44 @@ (INSTANCE \\inst2\|LessThan0\~3\\) (DELAY (ABSOLUTE - (PORT dataa (143:143:143) (193:193:193)) - (PORT datab (143:143:143) (192:192:192)) - (PORT datac (128:128:128) (168:168:168)) - (PORT datad (129:129:129) (165:165:165)) + (PORT dataa (138:138:138) (190:190:190)) + (PORT datab (138:138:138) (187:187:187)) + (PORT datac (124:124:124) (166:166:166)) + (PORT datad (124:124:124) (162:162:162)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (149:149:149) (199:199:199)) + (PORT datac (121:121:121) (163:163:163)) + (PORT datad (123:123:123) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (268:268:268)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (124:124:124) (163:163:163)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -862,13 +2402,13 @@ (INSTANCE \\inst2\|LessThan0\~4\\) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (274:274:274)) - (PORT datab (135:135:135) (185:185:185)) - (PORT datac (121:121:121) (164:164:164)) + (PORT dataa (139:139:139) (191:191:191)) + (PORT datab (502:502:502) (584:584:584)) + (PORT datac (89:89:89) (110:110:110)) (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -878,13 +2418,437 @@ (INSTANCE \\inst2\|LessThan0\~6\\) (DELAY (ABSOLUTE - (PORT dataa (139:139:139) (193:193:193)) - (PORT datab (137:137:137) (188:188:188)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (90:90:90) (106:106:106)) + (PORT dataa (136:136:136) (190:190:190)) + (PORT datab (137:137:137) (186:186:186)) + (PORT datac (135:135:135) (177:177:177)) + (PORT datad (136:136:136) (174:174:174)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~10\\) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (594:594:594)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (324:324:324) (368:368:368)) + (PORT datad (103:103:103) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[1\]\~26\\) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[2\]\~28\\) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (187:187:187)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[3\]\~30\\) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[4\]\~32\\) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (195:195:195)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[5\]\~34\\) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[6\]\~36\\) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[6\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[7\]\~38\\) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[7\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[8\]\~40\\) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (182:182:182)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[8\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[9\]\~42\\) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[9\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[10\]\~44\\) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[10\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[11\]\~46\\) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[11\]\\) + (DELAY + (ABSOLUTE + (PORT clk (922:922:922) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (556:556:556) (636:636:636)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[12\]\~48\\) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (188:188:188)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[12\]\\) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (926:926:926)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (334:334:334) (387:387:387)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[13\]\\) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (926:926:926)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (334:334:334) (387:387:387)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~5\\) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (649:649:649)) + (PORT datab (550:550:550) (648:648:648)) + (PORT datac (528:528:528) (625:625:625)) + (PORT datad (530:530:530) (613:613:613)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -894,28 +2858,8 @@ (INSTANCE \\inst2\|LessThan0\~7\\) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (278:278:278)) - (PORT datab (138:138:138) (189:189:189)) - (PORT datac (203:203:203) (249:249:249)) - (PORT datad (301:301:301) (355:355:355)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~8\\) - (DELAY - (ABSOLUTE - (PORT dataa (151:151:151) (205:205:205)) - (PORT datab (185:185:185) (222:222:222)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (102:102:102) (122:122:122)) + (PORT datad (503:503:503) (574:574:574)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -926,7 +2870,11 @@ (INSTANCE \\inst2\|ledBuf\~0\\) (DELAY (ABSOLUTE - (PORT datad (274:274:274) (308:308:308)) + (PORT dataa (104:104:104) (134:134:134)) + (PORT datab (511:511:511) (592:592:592)) + (PORT datad (495:495:495) (564:564:564)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -937,7 +2885,7 @@ (INSTANCE \\inst2\|ledBuf\\) (DELAY (ABSOLUTE - (PORT clk (1115:1115:1115) (1152:1152:1152)) + (PORT clk (916:916:916) (922:922:922)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -946,4 +2894,31 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneiii_pll") + (INSTANCE \\inst\|altpll_component\|auto_generated\|pll1\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1115:1115:1115) (1115:1115:1115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_clkctrl") + (INSTANCE \\inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1137:1137:1137) (1133:1133:1133)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_clkctrl") + (INSTANCE \\inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1137:1137:1137) (1133:1133:1133)) + ) + ) + ) ) diff --git a/MainController/simulation/modelsim/MainController_modelsim.xrf b/MainController/simulation/modelsim/MainController_modelsim.xrf index bb35dbd..c6190f1 100644 --- a/MainController/simulation/modelsim/MainController_modelsim.xrf +++ b/MainController/simulation/modelsim/MainController_modelsim.xrf @@ -16,7 +16,20 @@ source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratixii_pll source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cbx.lst source_file = 1, D:/GITEA/altera/MainController/db/alterapll_altpll.v +source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altsyncram.tdf +source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc +source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/lpm_mux.inc +source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/lpm_decode.inc +source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/a_rdenreg.inc +source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altrom.inc +source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altram.inc +source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altdpram.inc +source_file = 1, D:/GITEA/altera/MainController/db/altsyncram_lkc1.tdf +source_file = 1, D:/GITEA/altera/MainController/db/altsyncram_8bi1.tdf design_name = MainController +instance = comp, \FPGA_LED_1~output\, FPGA_LED_1~output, MainController, 1 +instance = comp, \FPGA_LED_2~output\, FPGA_LED_2~output, MainController, 1 +instance = comp, \FPGA_LED_3~output\, FPGA_LED_3~output, MainController, 1 instance = comp, \Data[7]~output\, Data[7]~output, MainController, 1 instance = comp, \Data[6]~output\, Data[6]~output, MainController, 1 instance = comp, \Data[5]~output\, Data[5]~output, MainController, 1 @@ -25,10 +38,164 @@ instance = comp, \Data[3]~output\, Data[3]~output, MainController, 1 instance = comp, \Data[2]~output\, Data[2]~output, MainController, 1 instance = comp, \Data[1]~output\, Data[1]~output, MainController, 1 instance = comp, \Data[0]~output\, Data[0]~output, MainController, 1 -instance = comp, \FPGA_LED_1~output\, FPGA_LED_1~output, MainController, 1 instance = comp, \FPGA_CLK~input\, FPGA_CLK~input, MainController, 1 instance = comp, \FPGA_CLK~inputclkctrl\, FPGA_CLK~inputclkctrl, MainController, 1 +instance = comp, \nCE~input\, nCE~input, MainController, 1 +instance = comp, \Address[5]~input\, Address[5]~input, MainController, 1 +instance = comp, \inst3|ce0Prev\, inst3|ce0Prev, MainController, 1 +instance = comp, \inst3|addr~5\, inst3|addr~5, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[12]~feeder\, inst3|memory_rtl_0_bypass[12]~feeder, MainController, 1 +instance = comp, \nWE~input\, nWE~input, MainController, 1 +instance = comp, \inst3|we0Prev\, inst3|we0Prev, MainController, 1 +instance = comp, \nOE~input\, nOE~input, MainController, 1 +instance = comp, \inst3|Selector3~3\, inst3|Selector3~3, MainController, 1 +instance = comp, \inst3|Selector3~2\, inst3|Selector3~2, MainController, 1 +instance = comp, \inst3|stateMM0.Writing\, inst3|stateMM0.Writing, MainController, 1 +instance = comp, \inst3|memory~48\, inst3|memory~48, MainController, 1 +instance = comp, \inst3|oe0Prev\, inst3|oe0Prev, MainController, 1 +instance = comp, \inst3|Selector3~0\, inst3|Selector3~0, MainController, 1 +instance = comp, \inst3|Selector3~1\, inst3|Selector3~1, MainController, 1 +instance = comp, \inst3|Selector2~0\, inst3|Selector2~0, MainController, 1 +instance = comp, \inst3|stateMM0.Waiting\, inst3|stateMM0.Waiting, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[12]\, inst3|memory_rtl_0_bypass[12], MainController, 1 +instance = comp, \inst3|addr[5]\, inst3|addr[5], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[11]~feeder\, inst3|memory_rtl_0_bypass[11]~feeder, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[11]\, inst3|memory_rtl_0_bypass[11], MainController, 1 +instance = comp, \Address[4]~input\, Address[4]~input, MainController, 1 +instance = comp, \inst3|addr~4\, inst3|addr~4, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[10]\, inst3|memory_rtl_0_bypass[10], MainController, 1 +instance = comp, \inst3|addr[4]\, inst3|addr[4], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[9]\, inst3|memory_rtl_0_bypass[9], MainController, 1 +instance = comp, \inst3|memory~37\, inst3|memory~37, MainController, 1 +instance = comp, \Address[2]~input\, Address[2]~input, MainController, 1 +instance = comp, \inst3|addr~2\, inst3|addr~2, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[6]~feeder\, inst3|memory_rtl_0_bypass[6]~feeder, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[6]\, inst3|memory_rtl_0_bypass[6], MainController, 1 +instance = comp, \Address[3]~input\, Address[3]~input, MainController, 1 +instance = comp, \inst3|addr~3\, inst3|addr~3, MainController, 1 +instance = comp, \inst3|addr[3]\, inst3|addr[3], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[7]\, inst3|memory_rtl_0_bypass[7], MainController, 1 +instance = comp, \inst3|addr[2]\, inst3|addr[2], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[5]\, inst3|memory_rtl_0_bypass[5], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[8]\, inst3|memory_rtl_0_bypass[8], MainController, 1 +instance = comp, \inst3|memory~35\, inst3|memory~35, MainController, 1 +instance = comp, \Address[0]~input\, Address[0]~input, MainController, 1 +instance = comp, \inst3|addr~0\, inst3|addr~0, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[2]~feeder\, inst3|memory_rtl_0_bypass[2]~feeder, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[2]\, inst3|memory_rtl_0_bypass[2], MainController, 1 +instance = comp, \Address[1]~input\, Address[1]~input, MainController, 1 +instance = comp, \inst3|addr~1\, inst3|addr~1, MainController, 1 +instance = comp, \inst3|addr[1]\, inst3|addr[1], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[3]\, inst3|memory_rtl_0_bypass[3], MainController, 1 +instance = comp, \inst3|addr[0]\, inst3|addr[0], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[1]\, inst3|memory_rtl_0_bypass[1], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[4]~feeder\, inst3|memory_rtl_0_bypass[4]~feeder, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[4]\, inst3|memory_rtl_0_bypass[4], MainController, 1 +instance = comp, \inst3|memory~34\, inst3|memory~34, MainController, 1 +instance = comp, \inst3|memory~36\, inst3|memory~36, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[0]\, inst3|memory_rtl_0_bypass[0], MainController, 1 +instance = comp, \Address[7]~input\, Address[7]~input, MainController, 1 +instance = comp, \inst3|addr~7\, inst3|addr~7, MainController, 1 +instance = comp, \inst3|addr[7]\, inst3|addr[7], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[15]\, inst3|memory_rtl_0_bypass[15], MainController, 1 +instance = comp, \Address[6]~input\, Address[6]~input, MainController, 1 +instance = comp, \inst3|addr~6\, inst3|addr~6, MainController, 1 +instance = comp, \inst3|addr[6]\, inst3|addr[6], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[13]~feeder\, inst3|memory_rtl_0_bypass[13]~feeder, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[13]\, inst3|memory_rtl_0_bypass[13], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[14]\, inst3|memory_rtl_0_bypass[14], MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[16]~feeder\, inst3|memory_rtl_0_bypass[16]~feeder, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[16]\, inst3|memory_rtl_0_bypass[16], MainController, 1 +instance = comp, \inst3|memory~38\, inst3|memory~38, MainController, 1 +instance = comp, \inst3|memory~39\, inst3|memory~39, MainController, 1 +instance = comp, \inst3|stateMM0.Waiting~_wirecell\, inst3|stateMM0.Waiting~_wirecell, MainController, 1 +instance = comp, \Data[0]~input\, Data[0]~input, MainController, 1 +instance = comp, \Data[1]~input\, Data[1]~input, MainController, 1 +instance = comp, \Data[2]~input\, Data[2]~input, MainController, 1 +instance = comp, \Data[3]~input\, Data[3]~input, MainController, 1 +instance = comp, \Data[4]~input\, Data[4]~input, MainController, 1 +instance = comp, \Data[5]~input\, Data[5]~input, MainController, 1 +instance = comp, \Data[6]~input\, Data[6]~input, MainController, 1 +instance = comp, \Data[7]~input\, Data[7]~input, MainController, 1 +instance = comp, \inst3|memory_rtl_0|auto_generated|ram_block1a0\, inst3|memory_rtl_0|auto_generated|ram_block1a0, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[24]~feeder\, inst3|memory_rtl_0_bypass[24]~feeder, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[24]\, inst3|memory_rtl_0_bypass[24], MainController, 1 +instance = comp, \inst3|memory~40\, inst3|memory~40, MainController, 1 +instance = comp, \inst3|Selector4~0\, inst3|Selector4~0, MainController, 1 +instance = comp, \inst3|stateMM0.Reading\, inst3|stateMM0.Reading, MainController, 1 +instance = comp, \inst3|Selector74~0\, inst3|Selector74~0, MainController, 1 +instance = comp, \inst3|data0[7]~reg0\, inst3|data0[7]~reg0, MainController, 1 +instance = comp, \inst3|data0[7]~enfeeder\, inst3|data0[7]~enfeeder, MainController, 1 +instance = comp, \inst3|data0[7]~en\, inst3|data0[7]~en, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[23]~feeder\, inst3|memory_rtl_0_bypass[23]~feeder, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[23]\, inst3|memory_rtl_0_bypass[23], MainController, 1 +instance = comp, \inst3|memory~41\, inst3|memory~41, MainController, 1 +instance = comp, \inst3|data0[6]~reg0\, inst3|data0[6]~reg0, MainController, 1 +instance = comp, \inst3|data0[6]~enfeeder\, inst3|data0[6]~enfeeder, MainController, 1 +instance = comp, \inst3|data0[6]~en\, inst3|data0[6]~en, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[22]~feeder\, inst3|memory_rtl_0_bypass[22]~feeder, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[22]\, inst3|memory_rtl_0_bypass[22], MainController, 1 +instance = comp, \inst3|memory~42\, inst3|memory~42, MainController, 1 +instance = comp, \inst3|data0[5]~reg0\, inst3|data0[5]~reg0, MainController, 1 +instance = comp, \inst3|data0[5]~enfeeder\, inst3|data0[5]~enfeeder, MainController, 1 +instance = comp, \inst3|data0[5]~en\, inst3|data0[5]~en, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[21]~feeder\, inst3|memory_rtl_0_bypass[21]~feeder, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[21]\, inst3|memory_rtl_0_bypass[21], MainController, 1 +instance = comp, \inst3|memory~43\, inst3|memory~43, MainController, 1 +instance = comp, \inst3|data0[4]~reg0\, inst3|data0[4]~reg0, MainController, 1 +instance = comp, \inst3|data0[4]~enfeeder\, inst3|data0[4]~enfeeder, MainController, 1 +instance = comp, \inst3|data0[4]~en\, inst3|data0[4]~en, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[20]\, inst3|memory_rtl_0_bypass[20], MainController, 1 +instance = comp, \inst3|memory~44\, inst3|memory~44, MainController, 1 +instance = comp, \inst3|data0[3]~reg0\, inst3|data0[3]~reg0, MainController, 1 +instance = comp, \inst3|data0[3]~enfeeder\, inst3|data0[3]~enfeeder, MainController, 1 +instance = comp, \inst3|data0[3]~en\, inst3|data0[3]~en, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[19]\, inst3|memory_rtl_0_bypass[19], MainController, 1 +instance = comp, \inst3|memory~45\, inst3|memory~45, MainController, 1 +instance = comp, \inst3|data0[2]~reg0\, inst3|data0[2]~reg0, MainController, 1 +instance = comp, \inst3|data0[2]~enfeeder\, inst3|data0[2]~enfeeder, MainController, 1 +instance = comp, \inst3|data0[2]~en\, inst3|data0[2]~en, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[18]\, inst3|memory_rtl_0_bypass[18], MainController, 1 +instance = comp, \inst3|memory~46\, inst3|memory~46, MainController, 1 +instance = comp, \inst3|data0[1]~reg0\, inst3|data0[1]~reg0, MainController, 1 +instance = comp, \inst3|data0[1]~enfeeder\, inst3|data0[1]~enfeeder, MainController, 1 +instance = comp, \inst3|data0[1]~en\, inst3|data0[1]~en, MainController, 1 +instance = comp, \inst3|memory_rtl_0_bypass[17]\, inst3|memory_rtl_0_bypass[17], MainController, 1 +instance = comp, \inst3|memory~47\, inst3|memory~47, MainController, 1 +instance = comp, \inst3|data0[0]~reg0\, inst3|data0[0]~reg0, MainController, 1 +instance = comp, \inst3|data0[0]~enfeeder\, inst3|data0[0]~enfeeder, MainController, 1 +instance = comp, \inst3|data0[0]~en\, inst3|data0[0]~en, MainController, 1 instance = comp, \inst2|counter[0]~24\, inst2|counter[0]~24, MainController, 1 +instance = comp, \inst2|counter[13]~50\, inst2|counter[13]~50, MainController, 1 +instance = comp, \inst2|counter[14]~52\, inst2|counter[14]~52, MainController, 1 +instance = comp, \inst2|counter[14]\, inst2|counter[14], MainController, 1 +instance = comp, \inst2|counter[15]~54\, inst2|counter[15]~54, MainController, 1 +instance = comp, \inst2|counter[15]\, inst2|counter[15], MainController, 1 +instance = comp, \inst2|counter[16]~56\, inst2|counter[16]~56, MainController, 1 +instance = comp, \inst2|counter[16]\, inst2|counter[16], MainController, 1 +instance = comp, \inst2|counter[17]~58\, inst2|counter[17]~58, MainController, 1 +instance = comp, \inst2|counter[17]\, inst2|counter[17], MainController, 1 +instance = comp, \inst2|counter[18]~60\, inst2|counter[18]~60, MainController, 1 +instance = comp, \inst2|counter[18]\, inst2|counter[18], MainController, 1 +instance = comp, \inst2|counter[19]~62\, inst2|counter[19]~62, MainController, 1 +instance = comp, \inst2|counter[19]\, inst2|counter[19], MainController, 1 +instance = comp, \inst2|counter[20]~64\, inst2|counter[20]~64, MainController, 1 +instance = comp, \inst2|counter[20]\, inst2|counter[20], MainController, 1 +instance = comp, \inst2|counter[21]~66\, inst2|counter[21]~66, MainController, 1 +instance = comp, \inst2|counter[21]\, inst2|counter[21], MainController, 1 +instance = comp, \inst2|LessThan0~8\, inst2|LessThan0~8, MainController, 1 +instance = comp, \inst2|counter[22]~68\, inst2|counter[22]~68, MainController, 1 +instance = comp, \inst2|counter[22]\, inst2|counter[22], MainController, 1 +instance = comp, \inst2|counter[23]~70\, inst2|counter[23]~70, MainController, 1 +instance = comp, \inst2|counter[23]\, inst2|counter[23], MainController, 1 +instance = comp, \inst2|LessThan0~9\, inst2|LessThan0~9, MainController, 1 +instance = comp, \inst2|LessThan0~2\, inst2|LessThan0~2, MainController, 1 +instance = comp, \inst2|LessThan0~3\, inst2|LessThan0~3, MainController, 1 +instance = comp, \inst2|LessThan0~0\, inst2|LessThan0~0, MainController, 1 +instance = comp, \inst2|LessThan0~1\, inst2|LessThan0~1, MainController, 1 +instance = comp, \inst2|LessThan0~4\, inst2|LessThan0~4, MainController, 1 +instance = comp, \inst2|LessThan0~6\, inst2|LessThan0~6, MainController, 1 +instance = comp, \inst2|LessThan0~10\, inst2|LessThan0~10, MainController, 1 instance = comp, \inst2|counter[0]\, inst2|counter[0], MainController, 1 instance = comp, \inst2|counter[1]~26\, inst2|counter[1]~26, MainController, 1 instance = comp, \inst2|counter[1]\, inst2|counter[1], MainController, 1 @@ -54,55 +221,11 @@ instance = comp, \inst2|counter[11]~46\, inst2|counter[11]~46, MainController, 1 instance = comp, \inst2|counter[11]\, inst2|counter[11], MainController, 1 instance = comp, \inst2|counter[12]~48\, inst2|counter[12]~48, MainController, 1 instance = comp, \inst2|counter[12]\, inst2|counter[12], MainController, 1 -instance = comp, \inst2|counter[13]~50\, inst2|counter[13]~50, MainController, 1 instance = comp, \inst2|counter[13]\, inst2|counter[13], MainController, 1 -instance = comp, \inst2|counter[14]~52\, inst2|counter[14]~52, MainController, 1 -instance = comp, \inst2|counter[14]\, inst2|counter[14], MainController, 1 -instance = comp, \inst2|counter[15]~54\, inst2|counter[15]~54, MainController, 1 -instance = comp, \inst2|counter[15]\, inst2|counter[15], MainController, 1 -instance = comp, \inst2|counter[16]~56\, inst2|counter[16]~56, MainController, 1 -instance = comp, \inst2|counter[16]\, inst2|counter[16], MainController, 1 -instance = comp, \inst2|counter[17]~58\, inst2|counter[17]~58, MainController, 1 -instance = comp, \inst2|counter[17]\, inst2|counter[17], MainController, 1 -instance = comp, \inst2|LessThan0~0\, inst2|LessThan0~0, MainController, 1 -instance = comp, \inst2|counter[18]~60\, inst2|counter[18]~60, MainController, 1 -instance = comp, \inst2|counter[18]\, inst2|counter[18], MainController, 1 -instance = comp, \inst2|counter[19]~62\, inst2|counter[19]~62, MainController, 1 -instance = comp, \inst2|counter[19]\, inst2|counter[19], MainController, 1 -instance = comp, \inst2|counter[20]~64\, inst2|counter[20]~64, MainController, 1 -instance = comp, \inst2|counter[20]\, inst2|counter[20], MainController, 1 -instance = comp, \inst2|counter[21]~66\, inst2|counter[21]~66, MainController, 1 -instance = comp, \inst2|counter[21]\, inst2|counter[21], MainController, 1 -instance = comp, \inst2|counter[22]~68\, inst2|counter[22]~68, MainController, 1 -instance = comp, \inst2|counter[22]\, inst2|counter[22], MainController, 1 -instance = comp, \inst2|counter[23]~70\, inst2|counter[23]~70, MainController, 1 -instance = comp, \inst2|counter[23]\, inst2|counter[23], MainController, 1 -instance = comp, \inst2|LessThan0~1\, inst2|LessThan0~1, MainController, 1 -instance = comp, \inst2|LessThan0~2\, inst2|LessThan0~2, MainController, 1 instance = comp, \inst2|LessThan0~5\, inst2|LessThan0~5, MainController, 1 -instance = comp, \inst2|LessThan0~3\, inst2|LessThan0~3, MainController, 1 -instance = comp, \inst2|LessThan0~4\, inst2|LessThan0~4, MainController, 1 -instance = comp, \inst2|LessThan0~6\, inst2|LessThan0~6, MainController, 1 instance = comp, \inst2|LessThan0~7\, inst2|LessThan0~7, MainController, 1 -instance = comp, \inst2|LessThan0~8\, inst2|LessThan0~8, MainController, 1 instance = comp, \inst2|ledBuf~0\, inst2|ledBuf~0, MainController, 1 instance = comp, \inst2|ledBuf\, inst2|ledBuf, MainController, 1 -instance = comp, \Address[7]~input\, Address[7]~input, MainController, 1 -instance = comp, \Address[6]~input\, Address[6]~input, MainController, 1 -instance = comp, \Address[5]~input\, Address[5]~input, MainController, 1 -instance = comp, \Address[4]~input\, Address[4]~input, MainController, 1 -instance = comp, \Address[3]~input\, Address[3]~input, MainController, 1 -instance = comp, \Address[2]~input\, Address[2]~input, MainController, 1 -instance = comp, \Address[1]~input\, Address[1]~input, MainController, 1 -instance = comp, \Address[0]~input\, Address[0]~input, MainController, 1 -instance = comp, \nOE~input\, nOE~input, MainController, 1 -instance = comp, \nWE~input\, nWE~input, MainController, 1 -instance = comp, \nCE~input\, nCE~input, MainController, 1 -instance = comp, \Data[7]~input\, Data[7]~input, MainController, 1 -instance = comp, \Data[6]~input\, Data[6]~input, MainController, 1 -instance = comp, \Data[5]~input\, Data[5]~input, MainController, 1 -instance = comp, \Data[4]~input\, Data[4]~input, MainController, 1 -instance = comp, \Data[3]~input\, Data[3]~input, MainController, 1 -instance = comp, \Data[2]~input\, Data[2]~input, MainController, 1 -instance = comp, \Data[1]~input\, Data[1]~input, MainController, 1 -instance = comp, \Data[0]~input\, Data[0]~input, MainController, 1 +instance = comp, \inst|altpll_component|auto_generated|pll1\, inst|altpll_component|auto_generated|pll1, MainController, 1 +instance = comp, \inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl\, inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, MainController, 1 +instance = comp, \inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl\, inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl, MainController, 1 diff --git a/MainController/simulation/modelsim/MainController_vhd.sdo b/MainController/simulation/modelsim/MainController_vhd.sdo index 7a8f05c..a6b5c76 100644 --- a/MainController/simulation/modelsim/MainController_vhd.sdo +++ b/MainController/simulation/modelsim/MainController_vhd.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "MainController") - (DATE "03/12/2024 16:24:29") + (DATE "03/12/2024 17:46:57") (VENDOR "Altera") (PROGRAM "Quartus II 64-Bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version") @@ -41,11 +41,127 @@ (INSTANCE \\FPGA_LED_1\~output\\) (DELAY (ABSOLUTE - (PORT i (1403:1403:1403) (1502:1502:1502)) + (PORT i (2032:2032:2032) (2189:2189:2189)) (IOPATH i o (2195:2195:2195) (2297:2297:2297)) ) ) ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\FPGA_LED_2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1600:1600:1600) (1590:1590:1590)) + (IOPATH i o (2466:2466:2466) (2351:2351:2351)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\FPGA_LED_3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1599:1599:1599) (1589:1589:1589)) + (IOPATH i o (2466:2466:2466) (2351:2351:2351)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[7\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1926:1926:1926) (1856:1856:1856)) + (PORT oe (2010:2010:2010) (1825:1825:1825)) + (IOPATH i o (2337:2337:2337) (2218:2218:2218)) + (IOPATH oe o (2571:2571:2571) (2571:2571:2571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[6\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1625:1625:1625) (1582:1582:1582)) + (PORT oe (1891:1891:1891) (1792:1792:1792)) + (IOPATH i o (4562:4562:4562) (4088:4088:4088)) + (IOPATH oe o (2571:2571:2571) (2571:2571:2571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[5\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (2637:2637:2637) (2438:2438:2438)) + (PORT oe (2269:2269:2269) (2130:2130:2130)) + (IOPATH i o (2337:2337:2337) (2218:2218:2218)) + (IOPATH oe o (2571:2571:2571) (2571:2571:2571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[4\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (2755:2755:2755) (2596:2596:2596)) + (PORT oe (2242:2242:2242) (2111:2111:2111)) + (IOPATH i o (2337:2337:2337) (2218:2218:2218)) + (IOPATH oe o (2571:2571:2571) (2571:2571:2571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[3\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1679:1679:1679) (1497:1497:1497)) + (PORT oe (1608:1608:1608) (1396:1396:1396)) + (IOPATH i o (2357:2357:2357) (2238:2238:2238)) + (IOPATH oe o (2591:2591:2591) (2591:2591:2591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[2\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1761:1761:1761) (1621:1621:1621)) + (PORT oe (1565:1565:1565) (1376:1376:1376)) + (IOPATH i o (2357:2357:2357) (2238:2238:2238)) + (IOPATH oe o (2591:2591:2591) (2591:2591:2591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[1\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1646:1646:1646) (1479:1479:1479)) + (PORT oe (1622:1622:1622) (1415:1415:1415)) + (IOPATH i o (2357:2357:2357) (2238:2238:2238)) + (IOPATH oe o (2591:2591:2591) (2591:2591:2591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\Data\[0\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1382:1382:1382) (1258:1258:1258)) + (PORT oe (1275:1275:1275) (1149:1149:1149)) + (IOPATH i o (2347:2347:2347) (2228:2228:2228)) + (IOPATH oe o (2581:2581:2581) (2581:2581:2581)) + ) + ) + ) (CELL (CELLTYPE "cycloneiii_io_ibuf") (INSTANCE \\FPGA_CLK\~input\\) @@ -64,394 +180,1818 @@ ) ) ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nCE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (895:895:895) (1014:1014:1014)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[5\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|ce0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT asdata (4980:4980:4980) (5188:5188:5188)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~5\\) + (DELAY + (ABSOLUTE + (PORT datab (4266:4266:4266) (4538:4538:4538)) + (PORT datac (4497:4497:4497) (4683:4683:4683)) + (PORT datad (1924:1924:1924) (1827:1827:1827)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[12\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1184:1184:1184) (1079:1079:1079)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nWE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (895:895:895) (1014:1014:1014)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|we0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT asdata (4449:4449:4449) (4593:4593:4593)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\nOE\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (895:895:895) (1014:1014:1014)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~3\\) + (DELAY + (ABSOLUTE + (PORT dataa (4145:4145:4145) (4366:4366:4366)) + (PORT datab (4567:4567:4567) (4770:4770:4770)) + (PORT datac (347:347:347) (442:442:442)) + (PORT datad (609:609:609) (649:649:649)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~2\\) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (703:703:703)) + (PORT datab (4569:4569:4569) (4772:4772:4772)) + (PORT datad (250:250:250) (271:271:271)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Writing\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1614:1614:1614) (1508:1508:1508)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~48\\) + (DELAY + (ABSOLUTE + (PORT datab (4026:4026:4026) (4176:4176:4176)) + (PORT datad (566:566:566) (590:590:590)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|oe0Prev\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT asdata (5065:5065:5065) (5258:5258:5258)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (4662:4662:4662) (4851:4851:4851)) + (PORT datad (567:567:567) (588:588:588)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector3\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (566:566:566)) + (PORT datab (4564:4564:4564) (4766:4766:4766)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (490:490:490)) + (PORT datab (4564:4564:4564) (4767:4767:4767)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Waiting\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT d 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) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Address\[6\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (915:915:915) (1034:1034:1034)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|addr\~6\\) + (DELAY + (ABSOLUTE + (PORT dataa (4227:4227:4227) (4475:4475:4475)) + (PORT datab (4266:4266:4266) (4544:4544:4544)) + (PORT datad (1923:1923:1923) (1827:1827:1827)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|addr\[6\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE 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\\inst3\|memory_rtl_0_bypass\[16\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (446:446:446) (423:423:423)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[16\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1922:1922:1922) (1930:1930:1930)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3257:3257:3257) (3417:3417:3417)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~38\\) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (418:418:418)) + (PORT datab (331:331:331) (408:408:408)) + (PORT datad (296:296:296) (364:364:364)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~39\\) + (DELAY + (ABSOLUTE + (PORT dataa (1551:1551:1551) (1402:1402:1402)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datad (1872:1872:1872) (1686:1686:1686)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|stateMM0\.Waiting\~_wirecell\\) + (DELAY + (ABSOLUTE + (PORT datad (1604:1604:1604) (1529:1529:1529)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[0\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (915:915:915) (1034:1034:1034)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[1\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[2\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[3\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (925:925:925) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[4\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[5\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[6\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\Data\[7\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (905:905:905) (1024:1024:1024)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4089:4089:4089) (4246:4246:4246)) + (PORT d[1] (4233:4233:4233) (4465:4465:4465)) + (PORT d[2] (4554:4554:4554) (4747:4747:4747)) + (PORT d[3] (4519:4519:4519) (4714:4714:4714)) + (PORT d[4] (4201:4201:4201) (4435:4435:4435)) + (PORT d[5] (4207:4207:4207) (4456:4456:4456)) + (PORT d[6] (4201:4201:4201) (4436:4436:4436)) + (PORT d[7] (4528:4528:4528) (4710:4710:4710)) + (PORT clk (2347:2347:2347) (2373:2373:2373)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2095:2095:2095) (1969:1969:1969)) + (PORT d[1] (2159:2159:2159) (2022:2022:2022)) + (PORT d[2] (1656:1656:1656) (1566:1566:1566)) + (PORT d[3] (2146:2146:2146) (2029:2029:2029)) + (PORT d[4] (1569:1569:1569) (1474:1474:1474)) + (PORT d[5] (1426:1426:1426) (1386:1386:1386)) + (PORT d[6] (2045:2045:2045) (1899:1899:1899)) + (PORT d[7] (1718:1718:1718) (1611:1611:1611)) + (PORT clk (2343:2343:2343) (2368:2368:2368)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1544:1544:1544) (1368:1368:1368)) + (PORT clk (2343:2343:2343) (2368:2368:2368)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2347:2347:2347) (2373:2373:2373)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (3798:3798:3798) (3824:3824:3824)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2348:2348:2348) (2374:2374:2374)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2348:2348:2348) (2374:2374:2374)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2348:2348:2348) (2374:2374:2374)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1324:1324:1324) (1224:1224:1224)) + (PORT d[1] (1379:1379:1379) (1286:1286:1286)) + (PORT d[2] (1363:1363:1363) (1259:1259:1259)) + (PORT d[3] (1357:1357:1357) (1262:1262:1262)) + (PORT d[4] (1286:1286:1286) (1179:1179:1179)) + (PORT d[5] (1660:1660:1660) (1537:1537:1537)) + (PORT d[6] (1311:1311:1311) (1215:1215:1215)) + (PORT d[7] (1278:1278:1278) (1189:1189:1189)) + (PORT clk (2345:2345:2345) (2370:2370:2370)) + (PORT stall (1538:1538:1538) (1703:1703:1703)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_register") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2345:2345:2345) (2370:2370:2370)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2346:2346:2346) (2371:2371:2371)) + (IOPATH (posedge clk) pulse (0:0:0) (3251:3251:3251)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2346:2346:2346) (2371:2371:2371)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_ram_pulse_generator") + (INSTANCE \\inst3\|memory_rtl_0\|auto_generated\|ram_block1a0\\.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2346:2346:2346) (2371:2371:2371)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[24\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (4102:4102:4102) (4331:4331:4331)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[24\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~40\\) + (DELAY + (ABSOLUTE + (PORT datab (1230:1230:1230) (1141:1141:1141)) + (PORT datac (832:832:832) (737:737:737)) + (PORT datad (298:298:298) (369:369:369)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector4\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (4145:4145:4145) (4366:4366:4366)) + (PORT datab (4566:4566:4566) (4772:4772:4772)) + (PORT datac (347:347:347) (444:444:444)) + (PORT datad (608:608:608) (648:648:648)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|stateMM0\.Reading\\) + (DELAY + (ABSOLUTE + (PORT clk (1935:1935:1935) (1944:1944:1944)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1614:1614:1614) (1508:1508:1508)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|Selector74\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (421:421:421)) + (PORT datab (4568:4568:4568) (4771:4771:4771)) + (PORT datac (342:342:342) (437:437:437)) + (PORT datad (607:607:607) (647:647:647)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE 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\\inst3\|data0\[6\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[6\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1604:1604:1604) (1531:1531:1531)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[6\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1943:1943:1943)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3021:3021:3021) (2829:2829:2829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE 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\\inst3\|data0\[5\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[5\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1600:1600:1600) (1523:1523:1523)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[5\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1943:1943:1943)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3021:3021:3021) (2829:2829:2829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[21\]\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (4135:4135:4135) (4375:4375:4375)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[21\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~43\\) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (792:792:792)) + (PORT datab (1231:1231:1231) (1143:1143:1143)) + (PORT datac (297:297:297) (376:376:376)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[4\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[4\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1599:1599:1599) (1524:1524:1524)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[4\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1943:1943:1943)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3021:3021:3021) (2829:2829:2829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[20\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT asdata (4587:4587:4587) (4803:4803:4803)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~44\\) + (DELAY + (ABSOLUTE + (PORT datab (1230:1230:1230) (1140:1140:1140)) + (PORT datac (296:296:296) (375:375:375)) + (PORT datad (809:809:809) (714:714:714)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[3\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[3\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1602:1602:1602) (1525:1525:1525)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[3\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1943:1943:1943)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3021:3021:3021) (2829:2829:2829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[19\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT asdata (4583:4583:4583) (4813:4813:4813)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~45\\) + (DELAY + (ABSOLUTE + (PORT datab (1229:1229:1229) (1140:1140:1140)) + (PORT datac (747:747:747) (664:664:664)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[2\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[2\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1600:1600:1600) (1522:1522:1522)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[2\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1943:1943:1943)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3021:3021:3021) (2829:2829:2829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[18\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT asdata (4618:4618:4618) (4837:4837:4837)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~46\\) + (DELAY + (ABSOLUTE + (PORT datab (1229:1229:1229) (1138:1138:1138)) + (PORT datac (736:736:736) (653:653:653)) + (PORT datad (296:296:296) (365:365:365)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[1\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[1\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1603:1603:1603) (1532:1532:1532)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[1\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1943:1943:1943)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3021:3021:3021) (2829:2829:2829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|memory_rtl_0_bypass\[17\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT asdata (4384:4384:4384) (4529:4529:4529)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|memory\~47\\) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datab (1228:1228:1228) (1139:1139:1139)) + (PORT datac (781:781:781) (698:698:698)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[0\]\~reg0\\) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1939:1939:1939)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3753:3753:3753) (3465:3465:3465)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst3\|data0\[0\]\~enfeeder\\) + (DELAY + (ABSOLUTE + (PORT datad (1605:1605:1605) (1530:1530:1530)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst3\|data0\[0\]\~en\\) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1943:1943:1943)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (3021:3021:3021) (2829:2829:2829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[0\]\~24\\) (DELAY (ABSOLUTE - (PORT dataa (567:567:567) (600:600:600)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[0\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[1\]\~26\\) - (DELAY - (ABSOLUTE - (PORT datab (576:576:576) (592:592:592)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[1\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[2\]\~28\\) - (DELAY - (ABSOLUTE - (PORT datab (566:566:566) (594:594:594)) + (PORT datab (341:341:341) (422:422:422)) (IOPATH datab combout (472:472:472) (473:473:473)) (IOPATH datab cout (565:565:565) (421:421:421)) (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[2\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[3\]\~30\\) - (DELAY - (ABSOLUTE - (PORT datab (343:343:343) (423:423:423)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[3\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2413:2413:2413)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[4\]\~32\\) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (615:615:615)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[4\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[5\]\~34\\) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (425:425:425)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[5\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[6\]\~36\\) - (DELAY - (ABSOLUTE - (PORT datab (341:341:341) (425:425:425)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[6\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2413:2413:2413)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[7\]\~38\\) - (DELAY - (ABSOLUTE - (PORT datab (561:561:561) (592:592:592)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[7\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[8\]\~40\\) - (DELAY - (ABSOLUTE - (PORT datab (341:341:341) (423:423:423)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[8\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[9\]\~42\\) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (434:434:434)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[9\]\\) - (DELAY - (ABSOLUTE - (PORT clk (1920:1920:1920) (1930:1930:1930)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[10\]\~44\\) - (DELAY - (ABSOLUTE - (PORT datab (341:341:341) (421:421:421)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[10\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2413:2413:2413)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[11\]\~46\\) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (434:434:434)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[11\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2413:2413:2413)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (1472:1472:1472) (1612:1612:1612)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|counter\[12\]\~48\\) - (DELAY - (ABSOLUTE - (PORT datab (340:340:340) (422:422:422)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[12\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[13\]\~50\\) @@ -466,28 +2006,12 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE \\inst2\|counter\[13\]\\) - (DELAY - (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) - (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[14\]\~52\\) (DELAY (ABSOLUTE - (PORT datab (358:358:358) (435:435:435)) + (PORT datab (341:341:341) (423:423:423)) (IOPATH datab combout (472:472:472) (473:473:473)) (IOPATH datab cout (565:565:565) (421:421:421)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -501,9 +2025,9 @@ (INSTANCE \\inst2\|counter\[14\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -517,7 +2041,7 @@ (INSTANCE \\inst2\|counter\[15\]\~54\\) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (460:460:460)) + (PORT dataa (370:370:370) (457:457:457)) (IOPATH dataa combout (461:461:461) (481:481:481)) (IOPATH dataa cout (552:552:552) (416:416:416)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -531,9 +2055,9 @@ (INSTANCE \\inst2\|counter\[15\]\\) (DELAY (ABSOLUTE - (PORT clk (1919:1919:1919) (1929:1929:1929)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -547,7 +2071,7 @@ (INSTANCE \\inst2\|counter\[16\]\~56\\) (DELAY (ABSOLUTE - (PORT datab (359:359:359) (436:436:436)) + (PORT datab (368:368:368) (449:449:449)) (IOPATH datab combout (472:472:472) (473:473:473)) (IOPATH datab cout (565:565:565) (421:421:421)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -561,9 +2085,9 @@ (INSTANCE \\inst2\|counter\[16\]\\) (DELAY (ABSOLUTE - (PORT clk (1919:1919:1919) (1929:1929:1929)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -577,7 +2101,7 @@ (INSTANCE \\inst2\|counter\[17\]\~58\\) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (447:447:447)) + (PORT dataa (345:345:345) (436:436:436)) (IOPATH dataa combout (461:461:461) (481:481:481)) (IOPATH dataa cout (552:552:552) (416:416:416)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -591,9 +2115,9 @@ (INSTANCE \\inst2\|counter\[17\]\\) (DELAY (ABSOLUTE - (PORT clk (1919:1919:1919) (1929:1929:1929)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -602,28 +2126,12 @@ (HOLD sclr (posedge clk) (212:212:212)) ) ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~0\\) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (866:866:866)) - (PORT datab (635:635:635) (645:645:645)) - (PORT datac (534:534:534) (562:562:562)) - (PORT datad (572:572:572) (584:584:584)) - (IOPATH dataa combout (438:438:438) (448:448:448)) - (IOPATH datab combout (440:440:440) (462:462:462)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[18\]\~60\\) (DELAY (ABSOLUTE - (PORT dataa (346:346:346) (436:436:436)) + (PORT dataa (345:345:345) (436:436:436)) (IOPATH dataa combout (471:471:471) (472:472:472)) (IOPATH dataa cout (552:552:552) (416:416:416)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -637,9 +2145,9 @@ (INSTANCE \\inst2\|counter\[18\]\\) (DELAY (ABSOLUTE - (PORT clk (1919:1919:1919) (1929:1929:1929)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -667,9 +2175,9 @@ (INSTANCE \\inst2\|counter\[19\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -697,9 +2205,9 @@ (INSTANCE \\inst2\|counter\[20\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -727,9 +2235,9 @@ (INSTANCE \\inst2\|counter\[21\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -738,12 +2246,28 @@ (HOLD sclr (posedge clk) (212:212:212)) ) ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~8\\) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (437:437:437)) + (PORT datab (342:342:342) (426:426:426)) + (PORT datac (302:302:302) (387:387:387)) + (PORT datad (302:302:302) (379:379:379)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|counter\[22\]\~68\\) (DELAY (ABSOLUTE - (PORT datab (343:343:343) (428:428:428)) + (PORT datab (344:344:344) (425:425:425)) (IOPATH datab combout (472:472:472) (473:473:473)) (IOPATH datab cout (565:565:565) (421:421:421)) (IOPATH datad combout (177:177:177) (155:155:155)) @@ -757,9 +2281,9 @@ (INSTANCE \\inst2\|counter\[22\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -773,7 +2297,7 @@ (INSTANCE \\inst2\|counter\[23\]\~70\\) (DELAY (ABSOLUTE - (PORT dataa (821:821:821) (810:810:810)) + (PORT dataa (347:347:347) (436:436:436)) (IOPATH dataa combout (471:471:471) (481:481:481)) (IOPATH cin combout (607:607:607) (577:577:577)) ) @@ -784,9 +2308,9 @@ (INSTANCE \\inst2\|counter\[23\]\\) (DELAY (ABSOLUTE - (PORT clk (2410:2410:2410) (2414:2414:2414)) + (PORT clk (1920:1920:1920) (1931:1931:1931)) (PORT d (99:99:99) (115:115:115)) - (PORT sclr (951:951:951) (989:989:989)) + (PORT sclr (935:935:935) (1004:1004:1004)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) ) @@ -797,15 +2321,13 @@ ) (CELL (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~1\\) + (INSTANCE \\inst2\|LessThan0\~9\\) (DELAY (ABSOLUTE - (PORT dataa (346:346:346) (435:435:435)) - (PORT datab (342:342:342) (425:425:425)) - (PORT datac (302:302:302) (385:385:385)) - (PORT datad (302:302:302) (378:378:378)) - (IOPATH dataa combout (420:420:420) (428:428:428)) - (IOPATH datab combout (432:432:432) (433:433:433)) + (PORT dataa (279:279:279) (312:312:312)) + (PORT datac (302:302:302) (387:387:387)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (405:405:405) (398:398:398)) (IOPATH datac combout (324:324:324) (315:315:315)) (IOPATH datad combout (177:177:177) (155:155:155)) ) @@ -816,24 +2338,10 @@ (INSTANCE \\inst2\|LessThan0\~2\\) (DELAY (ABSOLUTE - (PORT datab (343:343:343) (427:427:427)) - (PORT datac (776:776:776) (761:761:761)) - (PORT datad (237:237:237) (256:256:256)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~5\\) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (434:434:434)) - (PORT datab (343:343:343) (424:424:424)) - (PORT datac (319:319:319) (396:396:396)) - (PORT datad (304:304:304) (379:379:379)) + (PORT dataa (1357:1357:1357) (1326:1326:1326)) + (PORT datab (1359:1359:1359) (1293:1293:1293)) + (PORT datac (1347:1347:1347) (1289:1289:1289)) + (PORT datad (1321:1321:1321) (1266:1266:1266)) (IOPATH dataa combout (456:456:456) (486:486:486)) (IOPATH datab combout (457:457:457) (489:489:489)) (IOPATH datac combout (324:324:324) (315:315:315)) @@ -846,10 +2354,10 @@ (INSTANCE \\inst2\|LessThan0\~3\\) (DELAY (ABSOLUTE - (PORT dataa (361:361:361) (445:445:445)) - (PORT datab (359:359:359) (437:437:437)) - (PORT datac (318:318:318) (396:396:396)) - (PORT datad (319:319:319) (389:389:389)) + (PORT dataa (346:346:346) (434:434:434)) + (PORT datab (344:344:344) (424:424:424)) + (PORT datac (303:303:303) (385:385:385)) + (PORT datad (304:304:304) (378:378:378)) (IOPATH dataa combout (456:456:456) (486:486:486)) (IOPATH datab combout (457:457:457) (489:489:489)) (IOPATH datac combout (324:324:324) (315:315:315)) @@ -857,18 +2365,50 @@ ) ) ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (436:436:436)) + (PORT datab (368:368:368) (452:452:452)) + (PORT datac (301:301:301) (386:386:386)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (601:601:601)) + (PORT datab (275:275:275) (300:300:300)) + (PORT datac (301:301:301) (387:387:387)) + (PORT datad (304:304:304) (380:380:380)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) (CELL (CELLTYPE "cycloneiii_lcell_comb") (INSTANCE \\inst2\|LessThan0\~4\\) (DELAY (ABSOLUTE - (PORT dataa (583:583:583) (613:613:613)) - (PORT datab (342:342:342) (424:424:424)) - (PORT datac (301:301:301) (385:385:385)) + (PORT dataa (347:347:347) (436:436:436)) + (PORT datab (1246:1246:1246) (1139:1139:1139)) + (PORT datac (236:236:236) (262:262:262)) (PORT datad (237:237:237) (255:255:255)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) (IOPATH datad combout (177:177:177) (155:155:155)) ) ) @@ -878,13 +2418,437 @@ (INSTANCE \\inst2\|LessThan0\~6\\) (DELAY (ABSOLUTE - (PORT dataa (348:348:348) (438:438:438)) - (PORT datab (344:344:344) (427:427:427)) - (PORT datac (235:235:235) (262:262:262)) - (PORT datad (237:237:237) (255:255:255)) - (IOPATH dataa combout (393:393:393) (398:398:398)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datac combout (324:324:324) (316:316:316)) + (PORT dataa (346:346:346) (435:435:435)) + (PORT datab (344:344:344) (425:425:425)) + (PORT datac (328:328:328) (411:411:411)) + (PORT datad (330:330:330) (405:405:405)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~10\\) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1201:1201:1201)) + (PORT datab (302:302:302) (328:328:328)) + (PORT datac (849:849:849) (776:776:776)) + (PORT datad (264:264:264) (282:282:282)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[1\]\~26\\) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (436:436:436)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[2\]\~28\\) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[3\]\~30\\) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[4\]\~32\\) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (451:451:451)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[5\]\~34\\) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[6\]\~36\\) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[6\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[7\]\~38\\) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[7\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[8\]\~40\\) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (421:421:421)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[8\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[9\]\~42\\) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[9\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[10\]\~44\\) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (424:424:424)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[10\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[11\]\~46\\) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[11\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1923:1923:1923) (1933:1933:1933)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1520:1520:1520) (1491:1491:1491)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|counter\[12\]\~48\\) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (433:433:433)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[12\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1920:1920:1920) (1931:1931:1931)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (935:935:935) (1004:1004:1004)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE \\inst2\|counter\[13\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1920:1920:1920) (1931:1931:1931)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (935:935:935) (1004:1004:1004)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\|LessThan0\~5\\) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1323:1323:1323)) + (PORT datab (1398:1398:1398) (1325:1325:1325)) + (PORT datac (1336:1336:1336) (1278:1278:1278)) + (PORT datad (1301:1301:1301) (1245:1245:1245)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) (IOPATH datad combout (177:177:177) (155:155:155)) ) ) @@ -894,29 +2858,9 @@ (INSTANCE \\inst2\|LessThan0\~7\\) (DELAY (ABSOLUTE - (PORT dataa (579:579:579) (617:617:617)) - (PORT datab (345:345:345) (429:429:429)) - (PORT datac (541:541:541) (559:559:559)) - (PORT datad (816:816:816) (741:741:741)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (472:472:472) (452:452:452)) - (IOPATH datac combout (327:327:327) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneiii_lcell_comb") - (INSTANCE \\inst2\|LessThan0\~8\\) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (464:464:464)) - (PORT datab (531:531:531) (492:492:492)) - (PORT datac (235:235:235) (262:262:262)) - (PORT datad (236:236:236) (255:255:255)) - (IOPATH dataa combout (456:456:456) (486:486:486)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datac combout (327:327:327) (316:316:316)) + (PORT datac (262:262:262) (288:288:288)) + (PORT datad (1268:1268:1268) (1163:1163:1163)) + (IOPATH datac combout (327:327:327) (315:315:315)) (IOPATH datad combout (177:177:177) (155:155:155)) ) ) @@ -926,7 +2870,11 @@ (INSTANCE \\inst2\|ledBuf\~0\\) (DELAY (ABSOLUTE - (PORT datad (747:747:747) (674:674:674)) + (PORT dataa (279:279:279) (312:312:312)) + (PORT datab (1281:1281:1281) (1188:1188:1188)) + (PORT datad (1223:1223:1223) (1126:1126:1126)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) (IOPATH datac combout (462:462:462) (482:482:482)) (IOPATH datad combout (177:177:177) (155:155:155)) ) @@ -937,7 +2885,7 @@ (INSTANCE \\inst2\|ledBuf\\) (DELAY (ABSOLUTE - (PORT clk (2411:2411:2411) (2414:2414:2414)) + (PORT clk (1917:1917:1917) (1925:1925:1925)) (PORT d (99:99:99) (115:115:115)) (IOPATH (posedge clk) q (261:261:261) (261:261:261)) ) @@ -946,4 +2894,31 @@ (HOLD d (posedge clk) (212:212:212)) ) ) + (CELL + (CELLTYPE "cycloneiii_pll") + (INSTANCE \\inst\|altpll_component\|auto_generated\|pll1\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2357:2357:2357) (2357:2357:2357)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_clkctrl") + (INSTANCE \\inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2365:2365:2365) (2331:2331:2331)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_clkctrl") + (INSTANCE \\inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2365:2365:2365) (2331:2331:2331)) + ) + ) + ) )