From 51ae2e64a4b0622dfd3aa5119eeb60eb087d77df Mon Sep 17 00:00:00 2001 From: sokolovstanislav Date: Tue, 2 Apr 2024 18:08:20 +0300 Subject: [PATCH] =?UTF-8?q?=D0=94=D0=BE=D0=B1=D0=B0=D0=B2=D0=B8=D0=BB=20?= =?UTF-8?q?=D0=B2=20=D0=BF=D1=80=D0=BE=D0=B5=D0=BA=D1=82=20LedController.?= =?UTF-8?q?=20=D0=9D=D0=B0=D1=87=D0=B0=D0=BB=20=D1=80=D0=B5=D0=B0=D0=BB?= =?UTF-8?q?=D0=B8=D0=B7=D0=B0=D1=86=D0=B8=D1=8E=20=D0=B7=D0=B0=D0=B3=D1=80?= =?UTF-8?q?=D1=83=D0=B7=D1=87=D0=B8=D0=BA=D0=B0.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- MainController/MainController.bdf | 407 ++++++++++++++++++------ MainController/MainController.qsf | 6 +- MainController/RAM9X8_LedController.bsf | 130 ++++++++ MainController/RAM9X8_LedController.vhd | 291 +++++++++++++++++ 4 files changed, 743 insertions(+), 91 deletions(-) create mode 100644 MainController/RAM9X8_LedController.bsf create mode 100644 MainController/RAM9X8_LedController.vhd diff --git a/MainController/MainController.bdf b/MainController/MainController.bdf index 7b2f187..6d750cc 100644 --- a/MainController/MainController.bdf +++ b/MainController/MainController.bdf @@ -159,7 +159,7 @@ applicable agreement for further details. (input) (rect 368 1520 536 1536) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) - (text "PWM[5..0]" (rect 5 0 57 12)(font "Arial" )) + (text "PWM[5..0]" (rect 5 0 56 12)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -462,8 +462,40 @@ applicable agreement for further details. (annotation_block (location)(rect 2096 984 2144 1440)) ) (pin - (bidir) + (output) (rect 1840 280 2016 296) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "AsyncLine" (rect 90 0 141 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 1840 296 2016 312) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "DivClk" (rect 90 0 124 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (bidir) + (rect 1848 1664 2024 1680) (text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "Data[7..0]" (rect 122 0 171 12)(font "Arial" )) (pt 0 8) @@ -477,7 +509,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2024 168 2080 280)) + (annotation_block (location)(rect 2032 1552 2088 1664)) ) (pin (bidir) @@ -691,60 +723,6 @@ applicable agreement for further details. ) (annotation_block (parameter)(rect 1040 416 1360 544)) ) -(symbol - (rect 1040 256 1368 368) - (text "RAM" (rect 5 0 28 12)(font "Arial" )) - (text "inst1" (rect 8 96 31 108)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "address[address_bus_width-1..0]" (rect 0 0 161 12)(font "Arial" )) - (text "address[address_bus_width-1..0]" (rect 21 27 182 39)(font "Arial" )) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "we" (rect 0 0 12 12)(font "Arial" )) - (text "we" (rect 21 43 33 55)(font "Arial" )) - (line (pt 0 48)(pt 16 48)) - ) - (port - (pt 0 64) - (input) - (text "oe" (rect 0 0 11 12)(font "Arial" )) - (text "oe" (rect 21 59 32 71)(font "Arial" )) - (line (pt 0 64)(pt 16 64)) - ) - (port - (pt 0 80) - (input) - (text "ce" (rect 0 0 11 12)(font "Arial" )) - (text "ce" (rect 21 75 32 87)(font "Arial" )) - (line (pt 0 80)(pt 16 80)) - ) - (port - (pt 328 32) - (bidir) - (text "data[data_bus_width-1..0]" (rect 0 0 126 12)(font "Arial" )) - (text "data[data_bus_width-1..0]" (rect 208 27 334 39)(font "Arial" )) - (line (pt 328 32)(pt 312 32)(line_width 3)) - ) - (parameter - "DATA_BUS_WIDTH" - "8" - "" - (type "PARAMETER_SIGNED_DEC") ) - (parameter - "ADDRESS_BUS_WIDTH" - "9" - "" - (type "PARAMETER_SIGNED_DEC") ) - (drawing - (rectangle (rect 16 16 312 96)) - ) - (annotation_block (parameter)(rect 1040 208 1280 256)) -) (symbol (rect 1040 864 1368 1008) (text "RAM9X8_ParallelBusMaster" (rect 5 0 139 12)(font "Arial" )) @@ -1005,7 +983,7 @@ applicable agreement for further details. ) ) (symbol - (rect 1552 408 1584 424) + (rect 1552 400 1584 416) (text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6))) (text "inst13" (rect 3 5 32 17)(font "Arial" )(invisible)) (port @@ -1264,14 +1242,14 @@ applicable agreement for further details. (pt 328 48) (output) (text "tk[31..0]" (rect 0 0 41 12)(font "Arial" )) - (text "tk[31..0]" (rect 273 43 307 55)(font "Arial" )) + (text "tk[31..0]" (rect 273 43 314 55)(font "Arial" )) (line (pt 328 48)(pt 312 48)(line_width 3)) ) (port (pt 328 64) (output) (text "interrupt" (rect 0 0 40 12)(font "Arial" )) - (text "interrupt" (rect 274 59 307 71)(font "Arial" )) + (text "interrupt" (rect 274 59 314 71)(font "Arial" )) (line (pt 328 64)(pt 312 64)) ) (port @@ -1416,6 +1394,184 @@ applicable agreement for further details. ) (annotation_block (parameter)(rect 1024 1016 1400 1400)) ) +(symbol + (rect 1040 240 1368 384) + (text "RAM9X8_LedController" (rect 5 0 117 12)(font "Arial" )) + (text "inst19" (rect 8 128 37 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 14 12)(font "Arial" )) + (text "clk" (rect 21 27 35 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "address[address_bus_width-1..0]" (rect 0 0 161 12)(font "Arial" )) + (text "address[address_bus_width-1..0]" (rect 21 43 182 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "we" (rect 0 0 12 12)(font "Arial" )) + (text "we" (rect 21 59 33 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 0 80) + (input) + (text "oe" (rect 0 0 11 12)(font "Arial" )) + (text "oe" (rect 21 75 32 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)) + ) + (port + (pt 0 96) + (input) + (text "ce" (rect 0 0 11 12)(font "Arial" )) + (text "ce" (rect 21 91 32 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)) + ) + (port + (pt 0 112) + (input) + (text "error" (rect 0 0 22 12)(font "Arial" )) + (text "error" (rect 21 107 43 119)(font "Arial" )) + (line (pt 0 112)(pt 16 112)) + ) + (port + (pt 328 48) + (output) + (text "asyncline" (rect 0 0 47 12)(font "Arial" )) + (text "asyncline" (rect 268 43 315 55)(font "Arial" )) + (line (pt 328 48)(pt 312 48)) + ) + (port + (pt 328 64) + (output) + (text "divclk" (rect 0 0 29 12)(font "Arial" )) + (text "divclk" (rect 283 59 312 71)(font "Arial" )) + (line (pt 328 64)(pt 312 64)) + ) + (port + (pt 328 80) + (output) + (text "init" (rect 0 0 14 12)(font "Arial" )) + (text "init" (rect 296 75 310 87)(font "Arial" )) + (line (pt 328 80)(pt 312 80)) + ) + (port + (pt 328 32) + (bidir) + (text "data[data_bus_width-1..0]" (rect 0 0 126 12)(font "Arial" )) + (text "data[data_bus_width-1..0]" (rect 208 27 334 39)(font "Arial" )) + (line (pt 328 32)(pt 312 32)(line_width 3)) + ) + (parameter + "REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE" + "38" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE" + "39" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "REG_ADDR_TEST_UPPER_BYTE" + "40" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "REG_ADDR_TEST_LOWER_BYTE" + "41" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "DATA_BUS_WIDTH" + "8" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "ADDRESS_BUS_WIDTH" + "9" + "" + (type "PARAMETER_SIGNED_DEC") ) + (drawing + (rectangle (rect 16 16 312 128)) + ) + (annotation_block (parameter)(rect 1024 136 1376 240)) +) +(symbol + (rect 536 320 568 336) + (text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6))) + (text "inst20" (rect 3 5 32 17)(font "Arial" )(invisible)) + (port + (pt 16 16) + (output) + (text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible)) + (text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible)) + (line (pt 16 16)(pt 16 8)) + ) + (drawing + (line (pt 8 8)(pt 24 8)) + ) +) +(symbol + (rect 1048 1640 1376 1752) + (text "RAM" (rect 5 0 28 12)(font "Arial" )) + (text "inst21" (rect 8 96 37 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "address[address_bus_width-1..0]" (rect 0 0 161 12)(font "Arial" )) + (text "address[address_bus_width-1..0]" (rect 21 27 182 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "we" (rect 0 0 12 12)(font "Arial" )) + (text "we" (rect 21 43 33 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "oe" (rect 0 0 11 12)(font "Arial" )) + (text "oe" (rect 21 59 32 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 0 80) + (input) + (text "ce" (rect 0 0 11 12)(font "Arial" )) + (text "ce" (rect 21 75 32 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)) + ) + (port + (pt 328 32) + (bidir) + (text "data[data_bus_width-1..0]" (rect 0 0 126 12)(font "Arial" )) + (text "data[data_bus_width-1..0]" (rect 208 27 334 39)(font "Arial" )) + (line (pt 328 32)(pt 312 32)(line_width 3)) + ) + (parameter + "DATA_BUS_WIDTH" + "8" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "ADDRESS_BUS_WIDTH" + "9" + "" + (type "PARAMETER_SIGNED_DEC") ) + (drawing + (rectangle (rect 16 16 312 96)) + ) + (annotation_block (parameter)(rect 1040 1592 1280 1640)) +) (connector (pt 488 136) (pt 488 120) @@ -1528,11 +1684,6 @@ applicable agreement for further details. (pt 824 32) (pt 1840 32) ) -(connector - (pt 1840 288) - (pt 1368 288) - (bus) -) (connector (pt 704 256) (pt 544 256) @@ -1557,14 +1708,6 @@ applicable agreement for further details. (pt 1592 624) (pt 1568 624) ) -(connector - (pt 1568 424) - (pt 1568 504) -) -(connector - (pt 1568 504) - (pt 1568 624) -) (connector (pt 1592 592) (pt 1544 592) @@ -1585,10 +1728,6 @@ applicable agreement for further details. (pt 608 408) (pt 1544 408) ) -(connector - (pt 608 136) - (pt 608 408) -) (connector (pt 608 408) (pt 608 576) @@ -1828,35 +1967,118 @@ applicable agreement for further details. (pt 1000 912) (bus) ) -(connector - (pt 1000 912) - (pt 1000 1448) - (bus) -) (connector (pt 984 608) (pt 984 928) ) -(connector - (pt 984 928) - (pt 984 1464) -) (connector (pt 968 624) (pt 968 944) ) -(connector - (pt 968 944) - (pt 968 1480) -) (connector (pt 952 640) (pt 952 960) ) +(connector + (pt 1568 504) + (pt 1568 624) +) +(connector + (pt 1568 416) + (pt 1568 504) +) +(connector + (pt 1040 352) + (pt 552 352) +) +(connector + (pt 552 352) + (pt 552 336) +) +(connector + (pt 1040 272) + (pt 1016 272) +) +(connector + (pt 1016 272) + (pt 1016 368) +) +(connector + (pt 1016 368) + (pt 608 368) +) +(connector + (pt 608 136) + (pt 608 368) +) +(connector + (pt 608 368) + (pt 608 408) +) +(connector + (pt 1048 1672) + (pt 1000 1672) + (bus) +) +(connector + (pt 1000 912) + (pt 1000 1448) + (bus) +) +(connector + (pt 1000 1448) + (pt 1000 1672) + (bus) +) +(connector + (pt 1048 1688) + (pt 984 1688) +) +(connector + (pt 984 928) + (pt 984 1464) +) +(connector + (pt 984 1464) + (pt 984 1688) +) +(connector + (pt 1048 1704) + (pt 968 1704) +) +(connector + (pt 968 944) + (pt 968 1480) +) +(connector + (pt 968 1480) + (pt 968 1704) +) +(connector + (pt 1048 1720) + (pt 952 1720) +) (connector (pt 952 960) (pt 952 1496) ) +(connector + (pt 952 1496) + (pt 952 1720) +) +(connector + (pt 1848 1672) + (pt 1376 1672) + (bus) +) +(connector + (pt 1368 288) + (pt 1840 288) +) +(connector + (pt 1368 304) + (pt 1840 304) +) (junction (pt 608 32)) (junction (pt 1000 288)) (junction (pt 984 304)) @@ -1881,3 +2103,8 @@ applicable agreement for further details. (junction (pt 968 944)) (junction (pt 952 960)) (junction (pt 608 1432)) +(junction (pt 608 368)) +(junction (pt 1000 1448)) +(junction (pt 984 1464)) +(junction (pt 968 1480)) +(junction (pt 952 1496)) diff --git a/MainController/MainController.qsf b/MainController/MainController.qsf index 74f4caf..1dcaea5 100644 --- a/MainController/MainController.qsf +++ b/MainController/MainController.qsf @@ -208,7 +208,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[9] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TK[14] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Error set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Interrupt set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM[0] @@ -280,4 +279,9 @@ set_location_assignment PIN_119 -to TK[29] set_location_assignment PIN_113 -to TK[30] set_location_assignment PIN_118 -to TK[31] set_global_assignment -name BDF_FILE DigitalFilterBlock6.bdf +set_global_assignment -name VHDL_FILE RAM9X8_LedController.vhd +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AsyncLine +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DivClk +set_location_assignment PIN_70 -to DivClk +set_location_assignment PIN_69 -to AsyncLine set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/MainController/RAM9X8_LedController.bsf b/MainController/RAM9X8_LedController.bsf new file mode 100644 index 0000000..9977c9b --- /dev/null +++ b/MainController/RAM9X8_LedController.bsf @@ -0,0 +1,130 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 344 160) + (text "RAM9X8_LedController" (rect 5 0 104 12)(font "Arial" )) + (text "inst" (rect 8 128 20 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" )) + (text "address[address_bus_width-1..0]" (rect 21 43 150 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "we" (rect 0 0 10 12)(font "Arial" )) + (text "we" (rect 21 59 31 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "oe" (rect 0 0 9 12)(font "Arial" )) + (text "oe" (rect 21 75 30 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "ce" (rect 0 0 9 12)(font "Arial" )) + (text "ce" (rect 21 91 30 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "error" (rect 0 0 20 12)(font "Arial" )) + (text "error" (rect 21 107 41 119)(font "Arial" )) + (line (pt 0 112)(pt 16 112)(line_width 1)) + ) + (port + (pt 328 48) + (output) + (text "asyncline" (rect 0 0 36 12)(font "Arial" )) + (text "asyncline" (rect 271 43 307 55)(font "Arial" )) + (line (pt 328 48)(pt 312 48)(line_width 1)) + ) + (port + (pt 328 64) + (output) + (text "divclk" (rect 0 0 22 12)(font "Arial" )) + (text "divclk" (rect 285 59 307 71)(font "Arial" )) + (line (pt 328 64)(pt 312 64)(line_width 1)) + ) + (port + (pt 328 80) + (output) + (text "init" (rect 0 0 9 12)(font "Arial" )) + (text "init" (rect 298 75 307 87)(font "Arial" )) + (line (pt 328 80)(pt 312 80)(line_width 1)) + ) + (port + (pt 328 32) + (bidir) + (text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" )) + (text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" )) + (line (pt 328 32)(pt 312 32)(line_width 3)) + ) + (parameter + "REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE" + "38" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE" + "39" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "REG_ADDR_TEST_UPPER_BYTE" + "40" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "REG_ADDR_TEST_LOWER_BYTE" + "41" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "DATA_BUS_WIDTH" + "8" + "" + (type "PARAMETER_SIGNED_DEC") ) + (parameter + "ADDRESS_BUS_WIDTH" + "9" + "" + (type "PARAMETER_SIGNED_DEC") ) + (drawing + (rectangle (rect 16 16 312 128)(line_width 1)) + ) + (annotation_block (parameter)(rect 344 -64 444 16)) +) diff --git a/MainController/RAM9X8_LedController.vhd b/MainController/RAM9X8_LedController.vhd new file mode 100644 index 0000000..7c2ae8a --- /dev/null +++ b/MainController/RAM9X8_LedController.vhd @@ -0,0 +1,291 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity RAM9X8_LedController is + generic( + REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE : integer := 38; + REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE : integer := 39; + REG_ADDR_TEST_UPPER_BYTE : integer := 40; + REG_ADDR_TEST_LOWER_BYTE : integer := 41; + + DATA_BUS_WIDTH : integer := 8; + ADDRESS_BUS_WIDTH : integer := 9 + ); + + port( + clk : in std_logic; + + data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0); + address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0); + we : in std_logic; + oe : in std_logic; + ce : in std_logic; + + asyncline : out std_logic := '1'; + divclk : out std_logic := '1'; + error : in std_logic; + init : out std_logic := '0' + ); +end entity; + +architecture behavorial of RAM9X8_LedController is + +signal activeDeviceBuf : std_logic_vector(15 downto 0) := (others => '0'); +signal testBuf : std_logic_vector(15 downto 0) := (others => '0'); + +signal initBuf : std_logic := '0'; +signal divClkBuf : std_logic := '0'; +signal divClkBufPWM : std_logic := '0'; + +signal addrBuf : std_logic_vector(3 downto 0) := (others => '0'); +signal ledBuf : std_logic := '0'; + +signal LedState : std_logic_vector(1 downto 0) := (others => '0'); + +type BusSt is (Waiting, A3, A2, A1, A0, Dt, Finish); +signal BusState : BusSt := Waiting; + +signal countBuf : std_logic_vector(3 downto 0) := (others => '0'); +signal countBufPWM : std_logic_vector(3 downto 0) := (others => '0'); + +begin + + process (we, oe, ce) + variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0; + begin + if (ce = '0') then -- Если микросхема выбрана + addr := conv_integer(address); + if (addr = REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE or addr = REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE + or addr = REG_ADDR_TEST_UPPER_BYTE or addr = REG_ADDR_TEST_LOWER_BYTE) then + if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет + case addr is + when REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE => + data <= activeDeviceBuf(15 downto 8); + when REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE => + data <= activeDeviceBuf(7 downto 0); + when REG_ADDR_TEST_UPPER_BYTE => + data <= not testBuf(15 downto 8); + when REG_ADDR_TEST_LOWER_BYTE => + data <= not testBuf(7 downto 0); + when others => + data <= (others => 'Z'); -- Запретить запись на шину + end case; + elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет + case addr is + when REG_ADDR_ACTIVE_DEVICE_UPPER_BYTE => + activeDeviceBuf(15 downto 8) <= data; + when REG_ADDR_ACTIVE_DEVICE_LOWER_BYTE => + activeDeviceBuf(7 downto 0) <= data; + when REG_ADDR_TEST_UPPER_BYTE => + testBuf(15 downto 8) <= data; + when REG_ADDR_TEST_LOWER_BYTE => + testBuf(7 downto 0) <= data; + when others => + data <= (others => 'Z'); -- Запретить запись на шину + end case; + else + data <= (others => 'Z'); -- Запретить запись на шину + end if; + else + data <= (others => 'Z'); -- Запретить запись на шину + end if; + else + data <= (others => 'Z'); -- Запретить запись на шину + end if; + end process; + + process(clk) is + begin + if rising_edge(clk) then + if testBuf = x"5AA5" then + initBuf <= '1'; + end if; + end if; + end process; + + init <= initBuf; + + process(clk) is + variable count50000 : integer range 0 to 50000 := 0; + variable count50 : integer range 0 to 50 := 0; + begin + if rising_edge(clk) then + if count50000 < 50000 then + count50000 := count50000 + 1; + else + divClkBufPWM <= not divClkBufPWM; + count50000 := 0; + if count50 < 50 then + count50 := count50 + 1; + else + count50 := 0; + divClkBuf <= not divClkBuf; + end if; + end if; + end if; + end process; + + process(divClkBufPWM) is + begin + if conv_integer(countBufPWM) < 15 then + countBufPWM <= conv_std_logic_vector(conv_integer(countBufPWM) + 1, 4); + else + countBufPWM <= (others => '0'); + end if; + end process; + + process(divClkBuf) is + variable direction : integer range 0 to 1 := 0; + begin + if direction = 0 then + if conv_integer(countBuf) < 15 then + countBuf <= conv_std_logic_vector(conv_integer(countBuf) + 1, 4); + else + direction := 1; + end if; + else + if conv_integer(countBuf) > 0 then + countBuf <= conv_std_logic_vector(conv_integer(countBuf) - 1, 4); + else + direction := 0; + end if; + end if; + end process; + + process(divClkBuf) is + variable count15 : integer range 0 to 15 := 0; + begin + case LedState is + when b"00" => + if count15 < 15 then + count15 := count15 + 1; + else + count15 := 0; + LedState <= b"01"; + end if; + divclk <= '0'; + when b"01" => + if count15 < 7 then + count15 := count15 + 1; + else + count15 := 0; + LedState <= b"10"; + end if; + divclk <= '1'; + when b"10" => + if count15 < 15 then + count15 := count15 + 1; + else + count15 := 0; + LedState <= b"11"; + end if; + divclk <= '0'; + when b"11" => + if count15 < 4 then + count15 := count15 + 1; + else + count15 := 0; + LedState <= b"00"; + end if; + divclk <= '1'; + when others => + LedState <= b"00"; + end case; + end process; + + process(clk) is + variable count50 : integer range 0 to 50 := 0; + variable count15 : integer range 0 to 15 := 15; + begin + if rising_edge(clk) then + if initBuf = '0' then + case BusState is + when Waiting => + if count50 < 38 then + count50 := count50 + 1; + else + if count15 < 15 then + count15 := count15 + 1; + else + count15 := 0; + end if; + if activeDeviceBuf(count15) = '1' then + addrBuf <= conv_std_logic_vector(count15, 4); + asyncline <= '0'; + count50 := 0; + BusState <= A3; + end if; + end if; + when A3 => + if count50 < 18 then + count50 := count50 + 1; + else + count50 := 0; + asyncline <= addrBuf(3); + BusState <= A2; + end if; + when A2 => + if count50 < 38 then + count50 := count50 + 1; + else + count50 := 0; + asyncline <= addrBuf(2); + BusState <= A1; + end if; + when A1 => + if count50 < 38 then + count50 := count50 + 1; + else + count50 := 0; + asyncline <= addrBuf(1); + BusState <= A0; + end if; + when A0 => + if count50 < 38 then + count50 := count50 + 1; + else + count50 := 0; + asyncline <= addrBuf(0); + BusState <= Dt; + end if; + when Dt => + if count50 < 38 then + count50 := count50 + 1; + else + count50 := 0; + asyncline <= divClkBuf; + BusState <= Finish; + end if; + when Finish => + if count50 < 38 then + count50 := count50 + 1; + else + count50 := 0; + asyncline <= '1'; + BusState <= Finish; + end if; + when others => + BusState <= Waiting; + count50 := 0; + count15 :=15; + end case; + else + BusState <= Waiting; + count50 := 0; + count15 := 15; + if error = '0' then + if countBuf < countBufPWM then + asyncline <= '1'; + else + asyncline <= '0'; + end if; + else + asyncline <= '1'; + end if; + end if; + end if; + end process; + +end behavorial; \ No newline at end of file