diff --git a/MainController/RAM9X8_SerialBusMaster.vhd b/MainController/RAM9X8_SerialBusMaster.vhd
index 0055778..673d80c 100644
--- a/MainController/RAM9X8_SerialBusMaster.vhd
+++ b/MainController/RAM9X8_SerialBusMaster.vhd
@@ -44,7 +44,7 @@ signal dataToTransmit : std_logic_vector(15 downto 0) := x"0000";
 signal dataFromDevices : std_logic_vector(15 downto 0) := x"0000";
     
 type   CommunicationState_start  is (Waiting, TransmitAddress, TransmitData, TransmitCRC, TransmitCheck, ReceiveData, ReceiveCRC, ReceiveCheck, Timeout);  
-signal CommunicationState  : CommunicationState_start := Waiting ;
+signal CommunicationState  : CommunicationState_start := Waiting;
 	
 signal resetCRC : std_logic := '1';
 signal CRC : std_logic_vector(3 downto 0) := x"0";
@@ -111,6 +111,7 @@ begin
 	process(clk) is
 		variable count : integer range 0 to 255 := 0;
 		variable halfPeriod : integer range 0 to 255 := 50;
+		variable countPause : integer range 0 to 255 := 0;
 		variable pause : integer range 0 to 255 := 200;
 		variable state : integer range 0 to 1 := 1;
 		variable bitCnt : integer range -1 to 31 := 0;
@@ -123,6 +124,7 @@ begin
 					bitCnt := 8;
 					latch := 0;
 					resetCRC <= '1';
+					count := 0;
 					sbdataout <= '0';									
 					state := 1;
 					if start = '1' and  startPrev = '0' then                               
@@ -132,32 +134,18 @@ begin
                   dataCRC(23 downto 16) <= cmdBuf(7 downto 0);
                   dataToTransmit <= dataBufIn;
                   dataCRC(15 downto 0) <= dataBufIn;              
-                  controlBuf(15 downto 2) <= (others => '0');
-						controlBuf(1) <= '1';
-						controlBuf(0) <= '0';
-						if count < pause then
-							CommunicationState <= Timeout;
-							count := count + 1;
-						else 	
-							CommunicationState <= TransmitAddress;
-							count:= 0;
-						end if;	
-					else 
-						if count < pause then
-							count := count + 1;
-							controlBuf(1) <= '1';
-						else 
-							controlBuf(1) <= '0';	
-						end if;	
+                  controlBuf(15 downto 0) <= (others => '0');	
+						CommunicationState <= TransmitAddress;
                end if;
 				when Timeout =>
 					if count < pause then
+						sbclk <= '0';
 						count := count + 1;
 					else 	
-						CommunicationState <= TransmitAddress;
-						count:= 0;
+						controlBuf(1) <= '0';
+						CommunicationState <= Waiting;
 					end if;
-				when TransmitAddress =>	 
+				when TransmitAddress =>		
 					if bitCnt = -1 then
 						if direction = '1' then
 							CommunicationState <= TransmitData;
@@ -171,6 +159,7 @@ begin
 							if count = 0 then
 								if latch = 0 then 
 									sbdataout <= direction;
+									controlBuf(1) <= '1';
 								else 
 									sbdataout <= addressToTransmit(bitCnt);
 								end if;                           
@@ -242,9 +231,10 @@ begin
 								bitCnt := bitCnt - 1;
 							end if; 
 						end if;    		
-					else
-						count := 0;	
-						CommunicationState <= Waiting;
+					else	
+						--CommunicationState <= Waiting;
+						count := 0;
+						CommunicationState <= Timeout;
 						controlBuf(15) <= '1';
 					end if; 
 			   when TransmitCheck =>
@@ -255,13 +245,14 @@ begin
 						count := count + 1;
 					else	                   
 						count := 0;
-						state := 0;
 						if sbdatain = '0' then                           
 							controlBuf(0) <= '1';
 						else
 							controlBuf(14) <= '1';
 						end if;
-						CommunicationState <= Waiting;
+						--CommunicationState <= Waiting;
+						count := 0;
+						CommunicationState <= Timeout;
 					end if;    
 			   when ReceiveData =>
 					if bitCnt = -1 then
@@ -329,11 +320,10 @@ begin
 					else 
 						controlBuf(12) <= '1';    
 					end if;
+					--CommunicationState <= Waiting;
 					count := 0;
-					CommunicationState <= Waiting;     
+					CommunicationState <= Timeout;					
 				when others =>
-					count := 0;
-					CommunicationState <= Waiting;
 			end case;
       startPrev <= start;
 		end if;