208 lines
8.3 KiB
VHDL
208 lines
8.3 KiB
VHDL
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entity RAM9X8_PWM is
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generic(
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REG_ADDR_MODE_CONTROL_UPPER_BYTE : integer := 14;
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REG_ADDR_MODE_CONTROL_LOWER_BYTE : integer := 15;
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REG_ADDR_MASK_2_UPPER_BYTE : integer := 16;
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REG_ADDR_MASK_2_LOWER_BYTE : integer := 17;
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REG_ADDR_MASK_1_UPPER_BYTE : integer := 18;
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REG_ADDR_MASK_1_LOWER_BYTE : integer := 19;
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REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE : integer := 20;
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REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE : integer := 21;
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REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE : integer := 22;
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REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE : integer := 23;
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REG_ADDR_PERIOD_UPPER_BYTE : integer := 24;
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REG_ADDR_PERIOD_LOWER_BYTE : integer := 25;
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REG_ADDR_DIRECTION_UPPER_BYTE : integer := 26;
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REG_ADDR_DIRECTION_LOWER_BYTE : integer := 27;
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REG_ADDR_CHANNEL_UPPER_BYTE : integer := 28;
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REG_ADDR_CHANNEL_LOWER_BYTE : integer := 29;
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REG_ADDR_TIMING_UPPER_BYTE : integer := 30;
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REG_ADDR_TIMING_LOWER_BYTE : integer := 31;
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REG_ADDR_CMD_UPPER_BYTE : integer := 32;
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REG_ADDR_CMD_LOWER_BYTE : integer := 33;
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REG_ADDR_CONTROL_UPPER_BYTE : integer := 34;
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REG_ADDR_CONTROL_LOWER_BYTE : integer := 35;
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DATA_BUS_WIDTH : integer := 8;
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ADDRESS_BUS_WIDTH : integer := 9
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);
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port(
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clk : in std_logic;
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data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
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address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
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we : in std_logic;
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oe : in std_logic;
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ce : in std_logic;
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tk : out std_logic_vector(31 downto 0) := (others => '1');
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interrupt : out std_logic := '1';
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pwm : in std_logic_vector(5 downto 0)
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);
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end entity;
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architecture behavorial of RAM9X8_PWM is
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signal modeBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal maskBuf : std_logic_vector(31 downto 0) := (others => '1');
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signal directControlBuf : std_logic_vector(31 downto 0) := (others => '1');
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signal periodBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal directionBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal channelBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal cmdBuf : std_logic_vector(15 downto 0) := (others => '0');
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signal controlBuf : std_logic_vector(15 downto 0) := (others => '0');
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type mem is array (15 downto 0) of std_logic_vector(15 downto 0);
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signal memory : mem;
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signal lineBusy : std_logic := '1';
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signal start : std_logic := '0';
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signal startPrev : std_logic := '0';
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begin
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process (we, oe, ce)
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variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
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variable position : integer range 0 to ARRAY_LENGTH - 1 := 0;
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begin
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if (ce = '0') then -- Если микросхема выбрана
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addr := conv_integer(address);
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if (addr = REG_ADDR_MODE_CONTROL_UPPER_BYTE or addr = REG_ADDR_MODE_CONTROL_LOWER_BYTE
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or addr = REG_ADDR_MASK_2_UPPER_BYTE or addr = REG_ADDR_MASK_2_LOWER_BYTE or addr = REG_ADDR_MASK_1_UPPER_BYTE or addr = REG_ADDR_MASK_1_LOWER_BYTE
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or addr = REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE or addr = REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE or addr = REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE or addr = REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE
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or addr = REG_ADDR_PERIOD_UPPER_BYTE or addr = REG_ADDR_PERIOD_LOWER_BYTE or addr = REG_ADDR_DIRECTION_UPPER_BYTE or addr = REG_ADDR_DIRECTION_LOWER_BYTE
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or addr = REG_ADDR_CHANNEL_UPPER_BYTE or addr = REG_ADDR_CHANNEL_LOWER_BYTE or addr = REG_ADDR_TIMING_UPPER_BYTE or addr = REG_ADDR_TIMING_LOWER_BYTE
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or addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE or addr = REG_ADDR_CONTROL_UPPER_BYTE or addr = REG_ADDR_CONTROL_LOWER_BYTE) then
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if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
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case addr is
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when REG_ADDR_MODE_CONTROL_UPPER_BYTE =>
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data <= modeBuf(15 downto 8);
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when REG_ADDR_MODE_CONTROL_LOWER_BYTE =>
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data <= modeBuf(7 downto 0);
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when REG_ADDR_MASK_2_UPPER_BYTE =>
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data <= maskBuf(31 downto 24);
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when REG_ADDR_MASK_2_LOWER_BYTE =>
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data <= maskBuf(23 downto 16);
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when REG_ADDR_MASK_1_UPPER_BYTE =>
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data <= maskBuf(15 downto 8);
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when REG_ADDR_MASK_1_LOWER_BYTE =>
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data <= maskBuf(7 downto 0);
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when REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE =>
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data <= directControlBuf(31 downto 24);
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when REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE =>
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data <= directControlBuf(23 downto 16);
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when REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE =>
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data <= directControlBuf(15 downto 8);
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when REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE =>
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data <= directControlBuf(7 downto 0);
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when REG_ADDR_PERIOD_UPPER_BYTE =>
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data <= periodBuf(15 downto 8);
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when REG_ADDR_PERIOD_LOWER_BYTE =>
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data <= periodBuf(7 downto 0);
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when REG_ADDR_DIRECTION_UPPER_BYTEE =>
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data <= directionBuf(15 downto 8);
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when REG_ADDR_DIRECTION_LOWER_BYTE =>
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data <= directionBuf(7 downto 0);
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when REG_ADDR_CHANNEL_UPPER_BYTE =>
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data <= channelBuf(15 downto 8);
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when REG_ADDR_CHANNEL_LOWER_BYTE =>
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data <= channelBuf(7 downto 0);
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when REG_ADDR_TIMING_UPPER_BYTE =>
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data <= memory(conv_integer(channelBuf)(15 downto 8));
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when REG_ADDR_TIMING_LOWER_BYTE =>
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data <= memory(conv_integer(channelBuf)(7 downto 0);
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when REG_ADDR_CMD_UPPER_BYTE =>
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data <= cmdBuf(15 downto 8);
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when REG_ADDR_CMD_LOWER_BYTE =>
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data <= cmdBuf(7 downto 0);
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when REG_ADDR_CONTROL_UPPER_BYTE =>
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data <= controlBuf(15 downto 8);
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when REG_ADDR_CONTROL_LOWER_BYTE =>
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data <= controlBuf(7 downto 0);
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
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case addr is
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when REG_ADDR_MODE_CONTROL_UPPER_BYTE =>
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modeBuf(15 downto 8) <= data;
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when REG_ADDR_MODE_CONTROL_LOWER_BYTE =>
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modeBuf(7 downto 0) <= data;
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when REG_ADDR_MASK_2_UPPER_BYTE =>
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maskBuf(31 downto 24) <= data;
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when REG_ADDR_MASK_2_LOWER_BYTE =>
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maskBuf(23 downto 16) <= data;
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when REG_ADDR_MASK_1_UPPER_BYTE =>
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maskBuf(15 downto 8) <= data;
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when REG_ADDR_MASK_1_LOWER_BYTE =>
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maskBuf(7 downto 0) <= data;
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when REG_ADDR_DIRECT_CONTROL_2_UPPER_BYTE =>
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directControlBuf(31 downto 24) <= data;
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when REG_ADDR_DIRECT_CONTROL_2_LOWER_BYTE =>
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directControlBuf(23 downto 16) <= data;
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when REG_ADDR_DIRECT_CONTROL_1_UPPER_BYTE =>
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directControlBuf(15 downto 8) <= data;
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when REG_ADDR_DIRECT_CONTROL_1_LOWER_BYTE =>
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directControlBuf(7 downto 0) <= data;
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when REG_ADDR_PERIOD_UPPER_BYTE =>
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periodBuf(15 downto 8) <= data;
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when REG_ADDR_PERIOD_LOWER_BYTE =>
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periodBuf(7 downto 0) <= data;
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when REG_ADDR_DIRECTION_UPPER_BYTEE =>
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directionBuf(15 downto 8) <= data;
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when REG_ADDR_DIRECTION_LOWER_BYTE =>
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directionBuf(7 downto 0) <= data;
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when REG_ADDR_CHANNEL_UPPER_BYTE =>
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channelBuf(15 downto 8) <= data;
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when REG_ADDR_CHANNEL_LOWER_BYTE =>
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channelBuf(7 downto 0) <= data;
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when REG_ADDR_TIMING_UPPER_BYTE =>
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memory(conv_integer(channelBuf)(15 downto 8)) <= data;
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when REG_ADDR_TIMING_LOWER_BYTE =>
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memory(conv_integer(channelBuf)(7 downto 0) <= data;
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when REG_ADDR_CMD_UPPER_BYTE =>
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cmdBuf(15 downto 8) <= data;
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when REG_ADDR_CMD_LOWER_BYTE =>
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cmdBuf(7 downto 0) <= data;
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when REG_ADDR_CONTROL_UPPER_BYTE =>
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controlBuf(15 downto 8) <= data;
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when REG_ADDR_CONTROL_LOWER_BYTE =>
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controlBuf(7 downto 0) <= data;
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when others =>
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data <= (others => 'Z'); -- Запретить запись на шину
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end case;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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else
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data <= (others => 'Z'); -- Запретить запись на шину
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end if;
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end process;
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process(clk) is
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variable counter : integer range 0 to 65666 := 0;
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begin
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if(rising_edge clk) then
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if(conv_integer(memory(0)) > counter) then
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if(directionBuf(0) = '0') then
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pwm3level(0) <= '0';
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else
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pwm3level(0) <= '1';
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end if;
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else
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if(directionBuf(0) = '0') then
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pwm3level(0) <= '1';
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else
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pwm3level(0) <= '0';
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end if;
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end if;
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end process;
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end behavorial;
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