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stm32f407xx_matlab_memory.h
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/**
**************************************************************************
* @file stm32f407xx_matlab_memory.h
* @brief Заголовочный файл для определения памяти МК STM32F4xx.
**************************************************************************
@details
В данном файле переопределяются дефайны памяти STM32 таким образом, чтобы
к ним можно было обратиться в MATLAB.
Конкретно, создается структуруа имитирующая память, и далее дефайны определяются
так, чтобы обращаться к этой структуре, а не по абсолютному адресу.
**************************************************************************/
/**
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE_SHIFT (0x0000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE_SHIFT (0x00000000UL) /*!< ITM Base Address */
#define DWT_BASE_SHIFT (0x00001000UL) /*!< DWT Base Address */
#define TPI_BASE_SHIFT (0x00040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE_SHIFT (0x0000EDF0UL) /*!< Core Debug Base Address */
typedef struct _cortex_memory
{
uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000];
}MCU_CortexMemoryTypeDef;
extern MCU_CortexMemoryTypeDef MCU_CORTEX_MEM;
#define SCS_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< System Control Space Base Address */
#define ITM_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< ITM Base Address */
#define DWT_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< DWT Base Address */
#define TPI_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< TPI Base Address */
#define CoreDebug_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
/**
* @}
*/
/** @ingroup CMSIS_core_base
* @addtogroup Peripheral_memory_map Peripheral Memory Map
* @{
*/
#define FLASH_BASE_SHIFT 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
#define FLASH_END_SHIFT 0x080FFFFFUL /*!< FLASH end address */
#define CCMDATARAM_BASE_SHIFT 0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define CCMDATARAM_END_SHIFT 0x1000FFFFUL /*!< CCM data RAM end address */
#define FLASH_OTP_BASE_SHIFT 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
#define FLASH_OTP_END_SHIFT 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
#define SRAM1_BASE_SHIFT 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE_SHIFT 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */
#define SRAM1_BB_BASE_SHIFT 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */
#define SRAM2_BB_BASE_SHIFT 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BASE_SHIFT 0x40000000UL /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE_SHIFT 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */
#define PERIPH_BB_BASE_SHIFT 0x42000000UL /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE_SHIFT 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FSMC_R_BASE_SHIFT 0xA0000000UL /*!< FSMC registers base address */
#define MCU_MEM_END 0xA0000FFFUL /*!< CCM data RAM end address */
#define CCMDATARAM_SIZE 0x10000UL /* (64 KB) */
#define SRAM1_SIZE 0x1C000UL /* (112 KB) */
#define SRAM2_SIZE 0x4000UL /* (16 KB) */
#define BKPSRAM_SIZE 0x1000UL /* (4 KB) */
#define FLASH_SIZE (CCMDATARAM_BASE_SHIFT - FLASH_BASE_SHIFT)
//#define CCMDATARAM_SIZE (FLASH_OTP_BASE_SHIFT - CCMDATARAM_BASE_SHIFT)
#define FLASH_OTP_SIZE (SRAM1_BASE_SHIFT - FLASH_OTP_BASE_SHIFT)
//#define SRAM1_SIZE (SRAM2_BASE_SHIFT - SRAM1_BASE_SHIFT)
//#define SRAM2_SIZE (SRAM1_BB_BASE_SHIFT - SRAM2_BASE_SHIFT)
#define SRAM1_BB_SIZE (SRAM2_BB_BASE_SHIFT - SRAM1_BB_BASE_SHIFT)
#define SRAM2_BB_SIZE (PERIPH_BASE_SHIFT - SRAM2_BB_BASE_SHIFT)
#define PERIPH_SIZE (BKPSRAM_BASE_SHIFT - PERIPH_BASE_SHIFT)
//#define BKPSRAM_SIZE (PERIPH_BB_BASE_SHIFT - BKPSRAM_BASE_SHIFT)
#define PERIPH_BB_SIZE (BKPSRAM_BB_BASE_SHIFT - PERIPH_BB_BASE_SHIFT)
//#define BKPSRAM_BB_SIZE (FSMC_R_BASE_SHIFT - BKPSRAM_BB_BASE_SHIFT)
#define FSMC_R_SIZE (MCU_MEM_END - FSMC_R_BASE_SHIFT)
#define DEBUG_MCU_SIZE (2)
typedef struct _memory
{
//uint8_t RESERVED[FLASH_BASE_SHIFT];
uint8_t FLASH_BASE[FLASH_SIZE];
uint8_t CCMDATARAM_BASE[CCMDATARAM_SIZE];
uint8_t FLASH_OTP_BASE[FLASH_OTP_SIZE];
uint8_t SRAM1_BASE[SRAM1_SIZE];
uint8_t SRAM2_BASE[SRAM2_SIZE];
uint8_t SRAM1_BB_BASE[SRAM1_SIZE];
uint8_t SRAM2_BB_BASE[SRAM2_SIZE];
uint8_t PERIPH_BASE[PERIPH_SIZE];
uint8_t BKPSRAM_BASE[BKPSRAM_SIZE];
uint8_t PERIPH_BB_BASE[PERIPH_BB_SIZE];
uint8_t BKPSRAM_BB_BASE[BKPSRAM_SIZE];
uint8_t FSMC_R_BASE[FSMC_R_SIZE];
uint8_t DEBUG_MCU_BASE[DEBUG_MCU_SIZE];
}MCU_MemoryTypeDef;
extern MCU_MemoryTypeDef MCU_MEM;
#define FLASH_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< FLASH(up to 1 MB) base address in the alias region */
#define CCMDATARAM_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE (MCU_MEM.SRAM1_BASE) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE (MCU_MEM.SRAM2_BASE) /*!< SRAM2(16 KB) base address in the alias region */
#define PERIPH_BASE (MCU_MEM.PERIPH_BASE) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE (MCU_MEM.BKPSRAM_BASE) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE (MCU_MEM.FSMC_R_BASE) /*!< FSMC registers base address */
#define SRAM1_BB_BASE (MCU_MEM.SRAM1_BB_BASE) /*!< SRAM1(112 KB) base address in the bit-band region */
#define SRAM2_BB_BASE (MCU_MEM.SRAM2_BB_BASE) /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE (MCU_MEM.PERIPH_BB_BASE) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE (MCU_MEM.BKPSRAM_BB_BASE) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END (MCU_MEM.FLASH_END) /*!< FLASH end address */
#define FLASH_OTP_BASE (MCU_MEM.FLASH_OTP_BASE) /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
#define FLASH_OTP_END (MCU_MEM.FLASH_OTP_END) /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
#define CCMDATARAM_END (MCU_MEM.CCMDATARAM_END) /*!< CCM data RAM end address */
/*!< Debug MCU registers base address */
#define DBGMCU_BASE (MCU_MEM.DEBUG_MCU_BASE)
/**
* @}
*/
MCU_CortexMemoryTypeDef
struct _cortex_memory MCU_CortexMemoryTypeDef
MCU_CORTEX_MEM
MCU_CortexMemoryTypeDef MCU_CORTEX_MEM
Definition stm32f4xx_matlab_conf.c:14
PERIPH_BB_SIZE
#define PERIPH_BB_SIZE
Definition stm32f407xx_matlab_memory.h:100
MCU_MemoryTypeDef
struct _memory MCU_MemoryTypeDef
FSMC_R_SIZE
#define FSMC_R_SIZE
Definition stm32f407xx_matlab_memory.h:102
DEBUG_MCU_SIZE
#define DEBUG_MCU_SIZE
Definition stm32f407xx_matlab_memory.h:103
CCMDATARAM_SIZE
#define CCMDATARAM_SIZE
Definition stm32f407xx_matlab_memory.h:86
FLASH_OTP_SIZE
#define FLASH_OTP_SIZE
Definition stm32f407xx_matlab_memory.h:93
SRAM1_SIZE
#define SRAM1_SIZE
Definition stm32f407xx_matlab_memory.h:87
SRAM2_SIZE
#define SRAM2_SIZE
Definition stm32f407xx_matlab_memory.h:88
FLASH_SIZE
#define FLASH_SIZE
Definition stm32f407xx_matlab_memory.h:91
MCU_MEM
MCU_MemoryTypeDef MCU_MEM
Definition stm32f4xx_matlab_conf.c:13
PERIPH_SIZE
#define PERIPH_SIZE
Definition stm32f407xx_matlab_memory.h:98
BKPSRAM_SIZE
#define BKPSRAM_SIZE
Definition stm32f407xx_matlab_memory.h:89
_cortex_memory
Definition stm32f407xx_matlab_memory.h:27
_cortex_memory::CORTEX_PERIPH_BASE
uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000]
Definition stm32f407xx_matlab_memory.h:28
_memory
Definition stm32f407xx_matlab_memory.h:107
_memory::DEBUG_MCU_BASE
uint8_t DEBUG_MCU_BASE[DEBUG_MCU_SIZE]
Definition stm32f407xx_matlab_memory.h:122
_memory::PERIPH_BASE
uint8_t PERIPH_BASE[PERIPH_SIZE]
Definition stm32f407xx_matlab_memory.h:117
_memory::SRAM2_BASE
uint8_t SRAM2_BASE[SRAM2_SIZE]
Definition stm32f407xx_matlab_memory.h:114
_memory::SRAM2_BB_BASE
uint8_t SRAM2_BB_BASE[SRAM2_SIZE]
Definition stm32f407xx_matlab_memory.h:116
_memory::FLASH_BASE
uint8_t FLASH_BASE[FLASH_SIZE]
Definition stm32f407xx_matlab_memory.h:110
_memory::BKPSRAM_BB_BASE
uint8_t BKPSRAM_BB_BASE[BKPSRAM_SIZE]
Definition stm32f407xx_matlab_memory.h:120
_memory::PERIPH_BB_BASE
uint8_t PERIPH_BB_BASE[PERIPH_BB_SIZE]
Definition stm32f407xx_matlab_memory.h:119
_memory::SRAM1_BASE
uint8_t SRAM1_BASE[SRAM1_SIZE]
Definition stm32f407xx_matlab_memory.h:113
_memory::SRAM1_BB_BASE
uint8_t SRAM1_BB_BASE[SRAM1_SIZE]
Definition stm32f407xx_matlab_memory.h:115
_memory::CCMDATARAM_BASE
uint8_t CCMDATARAM_BASE[CCMDATARAM_SIZE]
Definition stm32f407xx_matlab_memory.h:111
_memory::FLASH_OTP_BASE
uint8_t FLASH_OTP_BASE[FLASH_OTP_SIZE]
Definition stm32f407xx_matlab_memory.h:112
_memory::BKPSRAM_BASE
uint8_t BKPSRAM_BASE[BKPSRAM_SIZE]
Definition stm32f407xx_matlab_memory.h:118
_memory::FSMC_R_BASE
uint8_t FSMC_R_BASE[FSMC_R_SIZE]
Definition stm32f407xx_matlab_memory.h:121