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Here is a list of all variables with links to the structures/unions they belong to:

### - b -

- BKPSRAM_BASE : _memory
- BKPSRAM_BB_BASE : _memory

### - c -

- CCMDATARAM_BASE : _memory
- Channels : TIM_Sim
- CORTEX_PERIPH_BASE : _cortex_memory

### - d -

- DEBUG_MCU_BASE : _memory

### - f -

- FLASH_BASE : _memory
- FLASH_OTP_BASE : _memory
- fMCU_Stop : SIM__MCUHandleTypeDef
- FSMC_R_BASE : _memory

### - h -

- hMCUThread : SIM__MCUHandleTypeDef

### - i -

- idMCUThread : SIM__MCUHandleTypeDef

### - o -

- OC1_GPIOx : Channels_Sim
- OC1_PIN_SHIFT : Channels_Sim
- OC1REF : Channels_Sim
- OC2_GPIOx : Channels_Sim
- OC2_PIN_SHIFT : Channels_Sim
- OC2REF : Channels_Sim
- OC3_GPIOx : Channels_Sim
- OC3_PIN_SHIFT : Channels_Sim
- OC3REF : Channels_Sim
- OC4_GPIOx : Channels_Sim
- OC4_PIN_SHIFT : Channels_Sim
- OC4REF : Channels_Sim

### - p -

- PERIPH_BASE : _memory
- PERIPH_BB_BASE : _memory

### - r -

- RELOAD : TIM_Sim

### - s -

- SIM_Sample_Time : SIM__MCUHandleTypeDef
- SRAM1_BASE : _memory
- SRAM1_BB_BASE : _memory
- SRAM2_BASE : _memory
- SRAM2_BB_BASE : _memory

### - t -

- TIM1_TRGO : SlaveChannels
- TIM2_TRGO : SlaveChannels
- TIM3_TRGO : SlaveChannels
- TIM4_TRGO : SlaveChannels
- TIM5_TRGO : SlaveChannels
- TIM6_TRGO : SlaveChannels
- TIM7_TRGO : SlaveChannels
- TIM8_TRGO : SlaveChannels
- tx_cnt : TIM_Sim
- tx_step : TIM_Sim