/*
 * detect_error_3_phase.h
 *
 *  Created on: 7 дек. 2020 г.
 *      Author: star
 */

#ifndef SRC_MAIN_DETECT_ERROR_3_PHASE_H_
#define SRC_MAIN_DETECT_ERROR_3_PHASE_H_

#include <detect_phase_break.h>

typedef struct {
    _iq iqVal_module_max;
    _iq iqVal_U_max;
    _iq iqVal_V_max;
    _iq iqVal_W_max;
    _iq iqNominal_plus10;
    _iq iqNominal_plus20;
    _iq iqNominal_minus10;

    _iq iqNominal_minus20;
    _iq iqAsymmetry_delta;
} PROTECT_LEVELS_3_PHASE;

#define PROTECT_LEVELS_3_PHASE_DEFAULTS {0,0,0,0,0,0,0, 0,0}

typedef struct {
    PROTECT_LEVELS_3_PHASE levels;
    union {
        unsigned int all;
        struct {
            unsigned int phase_U :1;
            unsigned int phase_V :1;
            unsigned int phase_W :1;
            unsigned int module :1;

            unsigned int detect_minus_10 :1;
            unsigned int detect_minus_20 :1;
            unsigned int detect_plus_10 :1;
            unsigned int detect_plus_20 :1;

            unsigned int system_asymmetry_by_summ :1; //Сумма 3-х составляющих равна 0
            unsigned int system_asymmetry_by_delta :1; //Действующие значения 3-х составляющих равны между собой
            unsigned int break_phase :1;
            unsigned int reserved :5;
        } bits;
    } use;
    unsigned int timers_inited;
} SETUP_3_PHASE_PROTECT;

#define SETUP_3_PHASE_PROTECT_DEFAULTS {PROTECT_LEVELS_3_PHASE_DEFAULTS, {0}, 0}

typedef struct {
    //In values
    _iq iqVal_U;
    _iq iqVal_V;
    _iq iqVal_W;
    _iq iqVal_mod;
    _iq iqTeta; //Нужен для определения обрыва фазы

    unsigned int timer_low_minus_10;
    unsigned int timer_low_minus_20;
    unsigned int timer_high_plus_10;
    unsigned int timer_high_plus_20;

    //Break phase I state values
    BREAK_PHASE_I *break_phase;

    //Out values
    union {
        unsigned int all;
        struct {
            unsigned int phase_U_max :1;
            unsigned int phase_V_max :1;
            unsigned int phase_W_max :1;
            unsigned int module_max :1;
            unsigned int module_10_percent_hi :1;
            unsigned int module_20_percent_hi :1;
            unsigned int module_10_percent_low :1;
            unsigned int module_20_percent_low :1;

            unsigned int system_asymmetry :1;
            unsigned int break_phase :1;
            unsigned int break_phase_U :1;
            unsigned int break_phase_V :1;
            unsigned int break_phase_W :1;
            unsigned int reserved :3;

        } bits;
    } errors;
    union {
        unsigned int all;
        struct {
            unsigned int phase_U_max :1;
            unsigned int phase_V_max :1;
            unsigned int phase_W_max :1;
            unsigned int module_max :1;
            unsigned int module_10_percent_hi :1;
            unsigned int module_20_percent_hi :1;
            unsigned int module_10_percent_low :1;
            unsigned int module_20_percent_low :1;

            unsigned int system_asymmetry_by_summ :1;
            unsigned int break_phase :1;
            unsigned int break_phase_U :1;
            unsigned int break_phase_V :1;
            unsigned int break_phase_W :1;
            unsigned int reserved :3;

        } bits;
    } over_limit;
    unsigned int new_timer_low_minus_10;
    unsigned int new_timer_low_minus_20;
    unsigned int new_timer_high_plus_10;
    unsigned int new_timer_high_plus_20;

    //Setup
    SETUP_3_PHASE_PROTECT setup;

    int (*calc_detect_error_3_phase)();

} DETECT_PROTECT_3_PHASE;

#define DETECT_PROTECT_3_PHASE_DEFAULTS {0,0,0,0,0, 0,0,0,0, 0, {0},{0}, 0,0,0,0,\
                        SETUP_3_PHASE_PROTECT_DEFAULTS,  \
                        detect_error_3_phase}


#define ADC_PROTECT_LEVELS_DEFAULT {0,0,0,0, 0,0,0,0, 0}

#define PAUSE_VAL_MINIS_10_S  10000
#define PAUSE_VAL_MINIS_20_S  1000
#define PAUSE_VAL_PLUS_10_S   10000
#define PAUSE_VAL_PLUS_20_S   1000

#define PLUS_10_PERCENT 1.1
#define PLUS_20_PERCENT 1.2
#define MINUS_10_PERCENT 0.9
#define MINUS_20_PERCENT 0.8
#define ASYMMETRY_DELTA_PERCENTS 0.2

int detect_error_3_phase(DETECT_PROTECT_3_PHASE *v);




#endif /* SRC_MAIN_DETECT_ERROR_3_PHASE_H_ */
