

#define ADC_usDELAY  8000L
#define ADC_usDELAY2 20L





// Determine when the shift to right justify the data takes place
// Only one of these should be defined as 1.  
// The other two should be defined as 0.
#define POST_SHIFT   0  // Shift results after the entire sample table is full
#define INLINE_SHIFT 1  // Shift results as the data is taken from the results regsiter
#define NO_SHIFT     0  // Do not shift the results 
  
// ADC start parameters
#define ADC_MODCLK 0x3   // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3)     = 25MHz
#define ADC_CKPS   0x0   // ADC module clock = HSPCLK/1      = 25MHz/(1)     = 25MHz
#define ADC_SHCLK  0x1   // S/H width in ADC module periods                  = 2 ADC cycle
#define AVG        1000  // Average sample limit
#define ZOFFSET    0x00  // Average Zero offset
#define BUF_SIZE   100  // Sample buffer size



#define FREQ_ADC 15000.0//26.08.2009//73000.0 


#define read_ADC(c) (*(&AdcRegs.ADCRESULT0+c)>>4)

#define SDVIG_K_FILTER_S 2 //1//(27.08.2009) //3

