1622 lines
74 KiB
C
1622 lines
74 KiB
C
/**************************************************************************
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Description: Ïîñëå çàãðóçêè ïðîöåññîðà ôóíêöèÿ âûçûâàåòñÿ îäèí ðàç
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è èíèöèàëèçèðóåò óïðàâëÿþùèå ðåãèñòðû ïðîöåññîðà
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TMS320F28335/TMS320F28379D.
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Àâòîð: Óëèòîâñêèé Ä.È.
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Äàòà ïîñëåäíåãî îáíîâëåíèÿ: 2021.10.04
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**************************************************************************/
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#include "def.h"
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#include "init28335.h"
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#ifndef ML
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extern void InitPll(Uint16 val, Uint16 divsel);
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extern void InitPieCtrl(void);
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extern void InitPieVectTable(void);
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extern void ADC_cal(void);
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extern void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
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extern void InitFlash(void);
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extern short CsmUnlock(void);
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void InitPeripheralClocks(void);
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void SetupGpio(void);
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extern interrupt void isr(void);
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#endif //ML
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void SetupAdc(void);
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void SetupEpwm(void);
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void SetupEqep(void);
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void init28335(void) {
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#ifndef ML
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// Global Disable all Interrupts
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DINT;
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// Disable CPU interrupts
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IER = 0x0000;
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// Clear all CPU interrupt flags
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IFR = 0x0000;
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// Initialize the PLL control: PLLCR[DIV] and PLLSTS[DIVSEL]
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InitPll(PLLCR_DIV, PLLSTS_DIVSEL);
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// Initialize interrupt controller and Vector Table
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// to defaults for now. Application ISR mapping done later.
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InitPieCtrl();
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InitPieVectTable();
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// Initialize the peripheral clocks
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InitPeripheralClocks();
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// Ulock the CSM
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csmSuccess = CsmUnlock();
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/* Copy time critical code and Flash setup code to RAM
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(the RamfuncsLoadStart, RamfuncsLoadEnd, RamfuncsRunStart,
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RamfuncsLoadStart2, RamfuncsLoadEnd2 and RamfuncsRunStart2
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symbols are created by the linker) */
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MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
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MemCopy(&RamfuncsLoadStart2, &RamfuncsLoadEnd2, &RamfuncsRunStart2);
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/* Copy the .switch section */
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// (the SwitchLoadStart, SwitchLoadEnd and SwitchRunStart
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// symbols are created by the linker)
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MemCopy(&SwitchLoadStart, &SwitchLoadEnd, &SwitchRunStart);
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/* Copy the .econst section */
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// (the EconstLoadStart, EconstLoadEnd and EconstRunStart
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// symbols are created by the linker)
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MemCopy(&EconstLoadStart, &EconstLoadEnd, &EconstRunStart);
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// Call Flash Initialization to setup flash waitstates
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// (this function must reside in RAM)
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InitFlash();
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#endif //ML
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// Setup ePWM
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SetupEpwm();
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// Setup ADC
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SetupAdc();
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// Setup eQEP
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SetupEqep();
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#ifndef ML
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// Setup GPIO
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SetupGpio();
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// Reassign ISR
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EALLOW;
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PieVectTable.ADCINT = &isr;
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EDIS;
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#endif //ML
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} //void init28335(void)
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#ifndef ML
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/* This function initializes the clocks to the peripheral modules.
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First the high and low clock prescalers are set
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Second the clocks are enabled to each peripheral.
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To reduce power, leave clocks to unused peripherals disabled
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Note: If a peripherals clock is not enabled then you cannot
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read or write to the registers for that peripheral */
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void InitPeripheralClocks(void) {
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EALLOW;
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// HISPCP/LOSPCP prescale register settings, normally it will be set
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// to default values
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// High speed clock = FSYSCLKOUT/2
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SysCtrlRegs.HISPCP.all = 0x0001;
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// Low speed clock = FSYSCLKOUT/4
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SysCtrlRegs.LOSPCP.all = 0x0002;
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/* Peripheral clock enables set for the selected peripherals.
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If you are not using a peripheral leave the clock off
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to save on power.
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This function is not written to be an example of efficient code */
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SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
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/* IMPORTANT
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The ADC_cal function, which copies the ADC calibration values from
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TI reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs
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automatically in the Boot ROM. If the boot ROM code is bypassed
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during the debug process, the following function MUST be called for
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the ADC to function according to specification. The clocks to the
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ADC MUST be enabled before calling this function.
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See the device data manual and/or the ADC Reference
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Manual for more information */
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ADC_cal();
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SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 0; // I2C
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SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 0; // SCI-A
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SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 0; // SCI-B
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SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 0; // SCI-C
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SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 0; // SPI-A
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SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 0;// McBSP-A
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SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 0;// McBSP-B
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SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 0; // eCAN-A
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SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 0; // eCAN-B
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
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SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
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SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
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SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
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SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
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SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
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SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
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SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 0; // eCAP3
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SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 0; // eCAP4
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SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 0; // eCAP5
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SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 0; // eCAP6
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SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 0; // eCAP1
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SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 0; // eCAP2
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SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 0; // eQEP1
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SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
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SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 0; // CPU Timer 0
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SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 0; // CPU Timer 1
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SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 0; // CPU Timer 2
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SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 0; // DMA Clock
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SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
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SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
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EDIS;
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} //void InitPeripheralClocks(void)
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// Íàñòðàèâàåò GPIO
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void SetupGpio(void) {
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EALLOW;
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// GPIO and Peripheral Multiplexing
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// GPIO0 ... GPIO15
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GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;//EPWM1A (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;//EPWM1B (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;//EPWM2A (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;//EPWM2B (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;//EPWM3A (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;//EPWM3B (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1;//EPWM4A (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1;//EPWM4B (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1;//EPWM5A (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1;//EPWM5B (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1;//EPWM6A (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;//EPWM6B (INU)
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GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0;//DI
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GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0;//DO
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GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0;//DI
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GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0;//DO
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// GPIO16 ... GPIO31
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GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0;//DI
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GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 0;//DO
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GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0;//DI
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GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0;//DO
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GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0;//DO
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GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0;//DI
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GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3;//SCITXDB
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GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3;//SCIRXDB
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GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2;//EQEP2A
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GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2;//EQEP2B
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GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2;//EQEP2I
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GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0;//DI
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GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1;//SCIRXDA
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GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1;//SCITXDA
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GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 0;//DO
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GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3;//XA17
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// GPIO32 ... GPIO47
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GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2;//EPWMSYNCI
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GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2;//EPWMSYNCO
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GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;//DO
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GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0;//DO
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GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3;//XZCS0
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GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3;//XZCS7
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GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3;//XWE0
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GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3;//XA16
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GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3;//XA0/XWE1
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GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3;//XA1
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GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3;//XA2
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GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3;//XA3
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GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3;//XA4
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GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3;//XA5
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GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3;//XA6
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GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3;//XA7
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// GPIO48 ... GPIO63
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GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 0;//DO
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GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 0;//DO
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GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 0;//DI (íåèñïðàâíîñòü èñòî÷íèêà ïèòàíèÿ +24 Â)
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GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 0;//DI
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GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 0;//DI
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GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 0;//DI
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GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1;//SPISIMOA
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GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1;//SPISOMIA
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GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1;//SPICLKA
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GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 0;//DO
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GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0;//DO
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GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 0;//DO (çåëåíûé ñâåòîäèîä "Ãîòîâíîñòü")
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GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 0;//DO (çåëåíûé ñâåòîäèîä "Ðàáîòà")
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GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0;//DO (êðàñíûé ñâåòîäèîä "Àâàðèÿ")
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GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1;//SCIRXDC
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GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1;//SCITXDC
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// GPIO64 ... GPIO79
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GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3;//XD15
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GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3;//XD14
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GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3;//XD13
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GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3;//XD12
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GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3;//XD11
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GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3;//XD10
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GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3;//XD9
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GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3;//XD8
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GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3;//XD7
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GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3;//XD6
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GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3;//XD5
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GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3;//XD4
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GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3;//XD3
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GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3;//XD2
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GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3;//XD1
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GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3;//XD0
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// GPIO80 ... GPIO87
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GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3;//XA8
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GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3;//XA9
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GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3;//XA10
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GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3;//XA11
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GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3;//XA12
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GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3;//XA13
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GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3;//XA14
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GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3;//XA15
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// âûáèðàåì ñîñòîÿíèå öèôðîâûõ âûõîäîâ
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DO_GPIO019_CLEAR;
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DO_GPIO020_CLEAR;
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DO_GPIO022_CLEAR;
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// ... ñâåòîäèîäû âûêëþ÷àåì
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LED_GREEN1_OFF;
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LED_GREEN2_OFF;
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LED_RED_OFF;
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DO_GPIO63_CLEAR;
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// Select the direction of the GPIO pins
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// GPIO0 ... GPIO31
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GpioCtrlRegs.GPADIR.bit.GPIO0 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO1 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO2 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO3 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO4 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO5 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO6 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO7 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO8 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO9 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO10 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO11 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO12 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO13 = 1;
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GpioCtrlRegs.GPADIR.bit.GPIO14 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO15 = 1;
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GpioCtrlRegs.GPADIR.bit.GPIO16 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO17 = 1;
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GpioCtrlRegs.GPADIR.bit.GPIO18 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO19 = 1;
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GpioCtrlRegs.GPADIR.bit.GPIO20 = 1;
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GpioCtrlRegs.GPADIR.bit.GPIO21 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO22 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO23 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO24 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO25 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO26 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO27 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO28 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO29 = 0;
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GpioCtrlRegs.GPADIR.bit.GPIO30 = 1;
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GpioCtrlRegs.GPADIR.bit.GPIO31 = 0;
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// GPIO32 ... GPIO63
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GpioCtrlRegs.GPBDIR.bit.GPIO32 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO33 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
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GpioCtrlRegs.GPBDIR.bit.GPIO35 = 1;
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GpioCtrlRegs.GPBDIR.bit.GPIO36 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO37 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO38 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO40 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO41 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO42 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO43 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO44 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO45 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1;
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GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1;
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GpioCtrlRegs.GPBDIR.bit.GPIO50 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO52 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO53 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO55 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1;
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GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1;
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GpioCtrlRegs.GPBDIR.bit.GPIO59 = 1;
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GpioCtrlRegs.GPBDIR.bit.GPIO60 = 1;
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GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1;
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GpioCtrlRegs.GPBDIR.bit.GPIO62 = 0;
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GpioCtrlRegs.GPBDIR.bit.GPIO63 = 1;
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// GPIO64 ... GPIO87
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GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0;
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GpioCtrlRegs.GPCDIR.bit.GPIO65 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO68 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO69 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO70 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO71 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO72 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO73 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO74 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO75 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO76 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO77 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO78 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO79 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO80 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO81 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO82 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO83 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO84 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO85 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO86 = 0;
|
|
GpioCtrlRegs.GPCDIR.bit.GPIO87 = 0;
|
|
|
|
// Each input can have different qualification:
|
|
// 0 - Synchronize to FSYSCLKOUT only;
|
|
// 1 - Qualification using 3 samples;
|
|
// 2 - Qualification using 6 samples;
|
|
// 3 - Asynchronous.
|
|
// GPIO0 ... GPIO15
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO4 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 2;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 2;
|
|
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 0;
|
|
// GPIO16 ... GPIO31
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 2;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 0;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 2;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 0;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 2;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 2;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 0;
|
|
GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 0;
|
|
// GPIO32 ... GPIO47
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO36 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO38 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO39 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO40 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO41 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO42 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO43 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO44 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO45 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO46 = 0;
|
|
GpioCtrlRegs.GPBQSEL1.bit.GPIO47 = 0;
|
|
// GPIO48 ... GPIO63
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 2;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 2;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 2;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 2;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 0;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 0;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 0;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 0;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 2;
|
|
GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0;
|
|
|
|
// Qualification Control (sampling period = (1/FSYSCLKOUT)*QUALPRDx*2)
|
|
// ( (1/150e6)*255*2 = 3.4 ìêñ )
|
|
// Port A
|
|
GpioCtrlRegs.GPACTRL.bit.QUALPRD0 = 255;//GPIO0 ... GPIO7
|
|
GpioCtrlRegs.GPACTRL.bit.QUALPRD1 = 255;//GPIO8 ... GPIO15
|
|
GpioCtrlRegs.GPACTRL.bit.QUALPRD2 = 255;//GPIO16 ... GPIO23
|
|
GpioCtrlRegs.GPACTRL.bit.QUALPRD3 = 255;//GPIO24 ... GPIO31
|
|
// Port B
|
|
GpioCtrlRegs.GPBCTRL.bit.QUALPRD0 = 255;//GPIO32 ... GPIO39
|
|
GpioCtrlRegs.GPBCTRL.bit.QUALPRD1 = 255;//GPIO40 ... GPIO47
|
|
GpioCtrlRegs.GPBCTRL.bit.QUALPRD2 = 255;//GPIO48 ... GPIO55
|
|
GpioCtrlRegs.GPBCTRL.bit.QUALPRD3 = 255;//GPIO56 ... GPIO63
|
|
|
|
// Pull-ups (the internal pullup çàïðåù¸í äëÿ ØÈÌ-âûõîäîâ)
|
|
// GPIO0 ... GPIO31
|
|
GpioCtrlRegs.GPAPUD.all = 0x00000FFF;
|
|
// GPIO32 ... GPIO63
|
|
GpioCtrlRegs.GPBPUD.all = 0x00000000;
|
|
// GPIO64 ... GPIO87
|
|
GpioCtrlRegs.GPCPUD.all = 0x00000000;
|
|
EDIS;
|
|
} //void SetupGpio(void)
|
|
#endif //ML
|
|
|
|
|
|
|
|
// Íàñòðàèâàåò ePWM
|
|
void SetupEpwm(void) {
|
|
// ePWM1
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm1Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm1Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm1Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;//TBCTR==0 -> EPWMxSYNCO
|
|
EPwm1Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm1Regs.TBCTL.bit.PHSEN = 0;//do not load TBCTR from TBPHS
|
|
EPwm1Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm1Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm1Regs.TBPHS.half.TBPHS = 0;
|
|
// Time-Base Counter Register
|
|
EPwm1Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm1Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm1Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;//active CMPB load from shadow - load on CTR = Zero
|
|
EPwm1Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm1Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm1Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm1Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
|
EPwm1Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
|
EPwm1Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm1Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm1Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm1Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm1Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm1Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm1Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm1Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm1Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm1Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm1Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm1Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm1Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm1Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm1Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm1Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm1Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm1Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm1Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm1Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm1Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm1Regs.ETSEL.bit.SOCBEN = 1;//enable EPWMxSOCB pulse
|
|
EPwm1Regs.ETSEL.bit.SOCBSEL = 1;//EPWMxSOCB selection - enable event CTR == 0
|
|
EPwm1Regs.ETSEL.bit.SOCAEN = 1;//enable EPWMxSOCA pulse
|
|
EPwm1Regs.ETSEL.bit.SOCASEL = 2;//EPWMxSOCA selection - enable event CTR == PRD
|
|
EPwm1Regs.ETSEL.bit.INTEN = 0;//disable EPWMx_INT generation
|
|
EPwm1Regs.ETSEL.bit.INTSEL = 0;//reserved
|
|
// Event-Trigger Prescale Register
|
|
EPwm1Regs.ETPS.bit.SOCBPRD = 1;//generate the EPWMxSOCB pulse on the first event
|
|
EPwm1Regs.ETPS.bit.SOCAPRD = 1;//generate the EPWMxSOCA pulse on the first event
|
|
EPwm1Regs.ETPS.bit.INTPRD = 0;//disable the interrupt event counter (no interrupt will be generated)
|
|
|
|
// ePWM2
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm2Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm2Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm2Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
|
EPwm2Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm2Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
|
EPwm2Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm2Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm2Regs.TBPHS.half.TBPHS = 2;
|
|
// Time-Base Counter Register
|
|
EPwm2Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm2Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm2Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
|
EPwm2Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm2Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm2Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm2Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
|
EPwm2Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
|
EPwm2Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm2Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm2Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm2Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm2Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm2Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm2Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm2Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm2Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm2Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm2Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm2Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm2Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm2Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm2Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm2Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm2Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm2Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm2Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm2Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm2Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm2Regs.ETSEL.all = 0;
|
|
// Event-Trigger Prescale Register
|
|
EPwm2Regs.ETPS.all = 0;
|
|
|
|
// ePWM3
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm3Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm3Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm3Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
|
EPwm3Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm3Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
|
EPwm3Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm3Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm3Regs.TBPHS.half.TBPHS = 2;
|
|
// Time-Base Counter Register
|
|
EPwm3Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm3Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm3Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
|
EPwm3Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm3Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm3Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm3Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
|
EPwm3Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
|
EPwm3Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm3Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm3Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm3Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm3Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm3Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm3Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm3Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm3Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm3Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm3Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm3Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm3Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm3Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm3Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm3Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm3Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm3Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm3Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm3Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm3Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm3Regs.ETSEL.all = 0;
|
|
// Event-Trigger Prescale Register
|
|
EPwm3Regs.ETPS.all = 0;
|
|
|
|
// ePWM4
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm4Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm4Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm4Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm4Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
|
EPwm4Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm4Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
|
EPwm4Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm4Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm4Regs.TBPHS.half.TBPHS = 2;
|
|
// Time-Base Counter Register
|
|
EPwm4Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm4Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm4Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm4Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
|
EPwm4Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm4Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm4Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm4Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
|
EPwm4Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
|
EPwm4Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm4Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm4Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm4Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm4Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm4Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm4Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm4Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm4Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm4Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm4Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm4Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm4Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm4Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm4Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm4Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm4Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm4Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm4Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm4Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm4Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm4Regs.ETSEL.all = 0;
|
|
// Event-Trigger Prescale Register
|
|
EPwm4Regs.ETPS.all = 0;
|
|
|
|
// ePWM5
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm5Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm5Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm5Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm5Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm5Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
|
EPwm5Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm5Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
|
EPwm5Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm5Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm5Regs.TBPHS.half.TBPHS = 2;
|
|
// Time-Base Counter Register
|
|
EPwm5Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm5Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm5Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm5Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
|
EPwm5Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm5Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm5Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm5Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
|
EPwm5Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
|
EPwm5Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm5Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm5Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm5Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm5Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm5Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm5Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm5Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm5Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm5Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm5Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm5Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm5Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm5Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm5Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm5Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm5Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm5Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm5Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm5Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm5Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm5Regs.ETSEL.all = 0;
|
|
// Event-Trigger Prescale Register
|
|
EPwm5Regs.ETPS.all = 0;
|
|
|
|
// ePWM6
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm6Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm6Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm6Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm6Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
|
EPwm6Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm6Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
|
EPwm6Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm6Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm6Regs.TBPHS.half.TBPHS = 2;
|
|
// Time-Base Counter Register
|
|
EPwm6Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm6Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm6Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm6Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
|
EPwm6Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm6Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm6Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm6Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
|
EPwm6Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
|
EPwm6Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm6Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm6Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm6Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm6Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm6Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm6Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm6Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm6Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm6Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm6Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm6Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm6Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm6Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm6Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm6Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm6Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm6Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm6Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm6Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm6Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm6Regs.ETSEL.all = 0;
|
|
// Event-Trigger Prescale Register
|
|
EPwm6Regs.ETPS.all = 0;
|
|
|
|
#ifdef ML
|
|
// ePWM7
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm7Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm7Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm7Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm7Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm7Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
|
EPwm7Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm7Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
|
EPwm7Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm7Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm7Regs.TBPHS.half.TBPHS = 2;
|
|
// Time-Base Counter Register
|
|
EPwm7Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm7Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm7Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm7Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm7Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm7Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
|
EPwm7Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm7Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm7Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm7Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
|
EPwm7Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
|
EPwm7Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm7Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm7Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm7Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm7Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm7Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm7Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm7Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm7Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm7Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm7Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm7Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm7Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm7Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm7Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm7Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm7Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm7Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm7Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm7Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm7Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm7Regs.ETSEL.all = 0;
|
|
// Event-Trigger Prescale Register
|
|
EPwm7Regs.ETPS.all = 0;
|
|
|
|
// ePWM8
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm8Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm8Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm8Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm8Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm8Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
|
EPwm8Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm8Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
|
EPwm8Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm8Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm8Regs.TBPHS.half.TBPHS = 2;
|
|
// Time-Base Counter Register
|
|
EPwm8Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm8Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm8Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm8Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm8Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm8Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
|
EPwm8Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm8Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm8Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm8Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
|
EPwm8Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
|
EPwm8Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm8Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm8Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm8Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm8Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm8Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm8Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm8Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm8Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm8Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm8Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm8Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm8Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm8Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm8Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm8Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm8Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm8Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm8Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm8Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm8Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm8Regs.ETSEL.all = 0;
|
|
// Event-Trigger Prescale Register
|
|
EPwm8Regs.ETPS.all = 0;
|
|
|
|
// ePWM9
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm9Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm9Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm9Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm9Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm9Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
|
EPwm9Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm9Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
|
EPwm9Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm9Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm9Regs.TBPHS.half.TBPHS = 2;
|
|
// Time-Base Counter Register
|
|
EPwm9Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm9Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm9Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm9Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm9Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm9Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
|
EPwm9Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm9Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm9Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm9Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
|
EPwm9Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
|
EPwm9Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm9Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm9Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm9Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm9Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm9Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm9Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm9Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm9Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm9Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm9Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm9Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm9Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm9Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm9Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm9Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm9Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm9Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm9Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm9Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm9Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm9Regs.ETSEL.all = 0;
|
|
// Event-Trigger Prescale Register
|
|
EPwm9Regs.ETPS.all = 0;
|
|
|
|
// ePWM10
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm10Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm10Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm10Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm10Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm10Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
|
EPwm10Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm10Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
|
EPwm10Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm10Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm10Regs.TBPHS.half.TBPHS = 2;
|
|
// Time-Base Counter Register
|
|
EPwm10Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm10Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm10Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm10Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm10Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm10Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
|
EPwm10Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm10Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm10Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm10Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
|
EPwm10Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
|
EPwm10Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm10Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm10Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm10Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm10Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm10Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm10Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm10Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm10Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm10Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm10Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm10Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm10Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm10Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm10Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm10Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm10Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm10Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm10Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm10Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm10Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm10Regs.ETSEL.all = 0;
|
|
// Event-Trigger Prescale Register
|
|
EPwm10Regs.ETPS.all = 0;
|
|
|
|
// ePWM11
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm11Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm11Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm11Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm11Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm11Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
|
EPwm11Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm11Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
|
EPwm11Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm11Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm11Regs.TBPHS.half.TBPHS = 2;
|
|
// Time-Base Counter Register
|
|
EPwm11Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm11Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm11Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm11Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm11Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm11Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
|
EPwm11Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm11Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm11Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm11Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
|
EPwm11Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
|
EPwm11Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm11Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm11Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm11Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm11Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm11Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm11Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm11Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm11Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm11Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm11Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm11Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm11Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm11Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm11Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm11Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm11Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm11Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm11Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm11Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm11Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm11Regs.ETSEL.all = 0;
|
|
// Event-Trigger Prescale Register
|
|
EPwm11Regs.ETPS.all = 0;
|
|
|
|
// ePWM12
|
|
// ####################################################################
|
|
// Time-Base (TB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Time-Base Control Register
|
|
EPwm12Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
|
EPwm12Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
|
EPwm12Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm12Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
|
EPwm12Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
|
EPwm12Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
|
EPwm12Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
|
EPwm12Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
|
// Time-Base Period Register
|
|
EPwm12Regs.TBPRD = (unsigned short)T1_PRD;
|
|
// Time-Base Phase Register
|
|
EPwm12Regs.TBPHS.half.TBPHS = 2;
|
|
// Time-Base Counter Register
|
|
EPwm12Regs.TBCTR = 1;
|
|
// Counter-Compare (CC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Counter-Compare A Register
|
|
EPwm12Regs.CMPA.half.CMPA = 0;
|
|
// Counter-Compare B Register
|
|
EPwm12Regs.CMPB = 0;
|
|
// Counter-Compare Control Register
|
|
EPwm12Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
|
EPwm12Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
|
EPwm12Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
|
EPwm12Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
|
// Action-Qualifier (AQ) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Action-Qualifier Output A Control Register
|
|
EPwm12Regs.AQCTLA.bit.CBD = 0;//do nothing
|
|
EPwm12Regs.AQCTLA.bit.CBU = 0;//do nothing
|
|
EPwm12Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
|
EPwm12Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
|
EPwm12Regs.AQCTLA.bit.PRD = 0;//do nothing
|
|
EPwm12Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Output B Control Register
|
|
EPwm12Regs.AQCTLB.bit.CBD = 0;//do nothing
|
|
EPwm12Regs.AQCTLB.bit.CBU = 0;//do nothing
|
|
EPwm12Regs.AQCTLB.bit.CAD = 0;//do nothing
|
|
EPwm12Regs.AQCTLB.bit.CAU = 0;//do nothing
|
|
EPwm12Regs.AQCTLB.bit.PRD = 0;//do nothing
|
|
EPwm12Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
|
// Action-Qualifier Software Force Register
|
|
EPwm12Regs.AQSFRC.all = 0;
|
|
// Action-Qualifier Continuous Software Force Register
|
|
EPwm12Regs.AQCSFRC.all = 0;
|
|
// Dead-Band Generator (DB) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Dead-Band Generator Control Register
|
|
EPwm12Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
|
EPwm12Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
|
EPwm12Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
|
// Dead-Band Generator Rising Edge Delay Register
|
|
EPwm12Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
|
// Dead-Band Generator Falling Edge Delay Register
|
|
EPwm12Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
|
// PWM-Chopper (PC) Submodule
|
|
// --------------------------------------------------------------------
|
|
// PWM-Chopper Control Register
|
|
EPwm12Regs.PCCTL.all = 0;
|
|
// Trip-Zone (TZ) Submodule
|
|
// --------------------------------------------------------------------
|
|
EALLOW;
|
|
// Trip-Zone Select Register
|
|
EPwm12Regs.TZSEL.all = 0;
|
|
// Trip-Zone Control Register
|
|
EPwm12Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
|
EPwm12Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
|
// Trip-Zone Enable Interrupt Register
|
|
EPwm12Regs.TZEINT.all = 0;
|
|
// Trip-Zone Force Register
|
|
EPwm12Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
|
EDIS;
|
|
// Event-Trigger (ET) Submodule
|
|
// --------------------------------------------------------------------
|
|
// Event-Trigger Selection Register
|
|
EPwm12Regs.ETSEL.all = 0;
|
|
// Event-Trigger Prescale Register
|
|
EPwm12Regs.ETPS.all = 0;
|
|
#endif //ML
|
|
} //void SetupEpwm(void)
|
|
|
|
|
|
|
|
// Íàñòðàèâàåò ADC
|
|
void SetupAdc(void) {
|
|
#ifndef ML
|
|
unsigned short i;
|
|
|
|
// ADC Control Register 1
|
|
AdcRegs.ADCTRL1.bit.SUSMOD = 0;//emulation suspend is ignored
|
|
AdcRegs.ADCTRL1.bit.ACQ_PS = 3;//width of SOC pulse is (ACQ_PS+1) times the ADCLK period
|
|
AdcRegs.ADCTRL1.bit.CPS = 0;//ADCCLK = HSPCLK/(2*ADCCLKPS*(CPS+1))
|
|
AdcRegs.ADCTRL1.bit.CONT_RUN = 0;//start-stop mode
|
|
AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0;//sequencer override disabled
|
|
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;//cascaded mode
|
|
|
|
// ADC Control Register 2
|
|
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ = 1;//allows SEQ to be started by ePWMx SOCB trigger
|
|
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0;//clears a pending SOC trigger
|
|
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;//interrupt request by INT_SEQ1 is enabled
|
|
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0;//INT_SEQ1 is set at the end of every SEQ1 sequence
|
|
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;//allows SEQ1/SEQ to be started by ePWMx SOCA trigger
|
|
AdcRegs.ADCTRL2.bit.EXT_SOC_SEQ1 = 0;//disables an ADC autoconversion sequence to be started by a signal from a GPIO Port A pin
|
|
AdcRegs.ADCTRL2.bit.SOC_SEQ2 = 0;//clears a pending SOC trigger
|
|
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ2 = 0;//interrupt request by INT_SEQ2 is disabled
|
|
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ2 = 0;//INT_SEQ2 is set at the end of every SEQ2 sequence
|
|
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ2 = 0;//SEQ2 cannot be started by ePWMx SOCB trigger
|
|
|
|
/* The ADC resets to the ADC off state. When powering up the ADC, use
|
|
the following sequence:
|
|
1. If external reference is desired, enable this mode using bits
|
|
15-14 in the ADCREFSEL Register. This mode must be enabled before
|
|
band gap is powered;
|
|
2. Power up the reference, bandgap, and analog circuits together by
|
|
setting bits 7-5 (ADCBGRFDN[1:0], ADCPWDN) in the ADCTRL3 register;
|
|
3. Before performing the first conversion, a delay of 5 ms is required */
|
|
|
|
// ADC Reference Select Register
|
|
AdcRegs.ADCREFSEL.bit.REF_SEL = 1;//external reference, 2.048 V on ADCREFIN
|
|
|
|
// ADC Control Register 3
|
|
AdcRegs.ADCTRL3.all = 0x00E0;//power up the reference, bandgap, and analog circuits together
|
|
AdcRegs.ADCTRL3.bit.ADCCLKPS = 5;//ADCCLK = HSPCLK/(2*ADCCLKPS*(CPS+1)) -> ADCCLK = 75e6/(2*5*(0+1)) = 7.5e6 Ãö
|
|
AdcRegs.ADCTRL3.bit.SMODE_SEL = 1;//simultaneous sampling mode
|
|
|
|
// Delay before converting ADC channels
|
|
for ( i = 0; i < 65500; i++ )
|
|
;
|
|
#endif //ML
|
|
|
|
// Maximum Conversion Channels Register
|
|
AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 5;//6 double conv's (12 total)
|
|
// ADC Input Channel Select Sequencing Control Registers
|
|
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0;
|
|
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 1;
|
|
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 2;
|
|
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 3;
|
|
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 4;
|
|
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 5;
|
|
AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 6;
|
|
AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 7;
|
|
AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0;
|
|
AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0;
|
|
AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0;
|
|
AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0;
|
|
AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0;
|
|
AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0;
|
|
AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0;
|
|
AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0;
|
|
} //void SetupAdc(void)
|
|
|
|
|
|
|
|
// Íàñòðàèâàåò eQEP
|
|
void SetupEqep(void) {
|
|
// eQEP Decoder Control Register
|
|
EQep2Regs.QDECCTL.bit.QSRC = 0;//Position-counter source selection: Quadrature count mode (QCLK = iCLK, QDIR = iDIR)
|
|
EQep2Regs.QDECCTL.bit.SOEN = 0;//Sync output-enable: Disable position-compare sync output
|
|
EQep2Regs.QDECCTL.bit.SPSEL = 0;//Sync output pin selection: Index pin is used for sync output
|
|
EQep2Regs.QDECCTL.bit.XCR = 0;//External clock rate: 2x resolution: Count the rising/falling edge
|
|
EQep2Regs.QDECCTL.bit.SWAP = 0;//Swap quadrature clock inputs: Quadrature-clock inputs are not swapped
|
|
EQep2Regs.QDECCTL.bit.IGATE = 0;//Index pulse gating option: Disable gating of Index pulse
|
|
EQep2Regs.QDECCTL.bit.QAP = 0;//QEPA input polarity: No effect
|
|
EQep2Regs.QDECCTL.bit.QBP = 0;//QEPB input polarity: No effect
|
|
EQep2Regs.QDECCTL.bit.QIP = 0;//QEPI input polarity: No effect
|
|
EQep2Regs.QDECCTL.bit.QSP = 0;//QEPS input polarity: No effect
|
|
// eQEP Control Register
|
|
EQep2Regs.QEPCTL.bit.FREE_SOFT = 0;//Emulation Control Bits: all stops immediately
|
|
EQep2Regs.QEPCTL.bit.PCRM = 1;//Position counter reset mode: position counter reset on the maximum position
|
|
EQep2Regs.QEPCTL.bit.SEI = 0;//Strobe event initialization of position counter: does nothing (action disabled)
|
|
EQep2Regs.QEPCTL.bit.IEI = 0;//Index event initialization of position counter: do nothing (action disabled)
|
|
EQep2Regs.QEPCTL.bit.SWI = 0;//Software initialization of position counter: do nothing (action disabled)
|
|
EQep2Regs.QEPCTL.bit.SEL = 0;//Strobe event latch of position counter: the position counter is latched on the rising edge of QEPS strobe
|
|
EQep2Regs.QEPCTL.bit.IEL = 1;//Index event latch of position counter (software index marker): latches position counter on rising edge of the index signal
|
|
EQep2Regs.QEPCTL.bit.QPEN = 1;//Quadrature position counter enable/software reset: eQEP position counter is enabled
|
|
EQep2Regs.QEPCTL.bit.QCLM = 0;//eQEP capture latch mode: latch on position counter read by CPU
|
|
EQep2Regs.QEPCTL.bit.UTE = 1;//eQEP unit timer enable: Enable unit timer
|
|
EQep2Regs.QEPCTL.bit.WDE = 0;//eQEP watchdog enable: disable the eQEP watchdog timer
|
|
// eQEP Position-compare Control Register
|
|
EQep2Regs.QPOSCTL.bit.PCSHDW = 0;//Position-compare shadow enable: Shadow disabled, load Immediate
|
|
EQep2Regs.QPOSCTL.bit.PCLOAD = 0;//Position-compare shadow load mode: Load on QPOSCNT = 0
|
|
EQep2Regs.QPOSCTL.bit.PCPOL = 0;//Polarity of sync output: Active HIGH pulse output
|
|
EQep2Regs.QPOSCTL.bit.PCE = 0;//Position-compare enable/disable: Disable position compare unit
|
|
EQep2Regs.QPOSCTL.bit.PCSPW = 0;//Select-position-compare sync output pulse width: 1 * 4 * SYSCLKOUT cycles
|
|
// eQEP Capture Control Register
|
|
EQep2Regs.QCAPCTL.bit.CEN = 1;//Enable eQEP capture: eQEP capture unit is enabled
|
|
EQep2Regs.QCAPCTL.bit.CCPS = 2;//eQEP capture timer clock prescaler: CAPCLK = SYSCLKOUT/4
|
|
EQep2Regs.QCAPCTL.bit.UPPS = 0;//Unit position event prescaler: UPEVNT = QCLK/1
|
|
// eQEP Position Counter Register
|
|
EQep2Regs.QPOSCNT = 0x00000000;
|
|
// eQEP Maximum Position Count Register Register
|
|
EQep2Regs.QPOSMAX = 0x7FFF;
|
|
// eQEP Position-compare Register
|
|
EQep2Regs.QPOSCMP = 0x00000000;
|
|
// eQEP Unit Timer Register
|
|
EQep2Regs.QUTMR = 0x00000000;
|
|
// eQEP Register Unit Period Register
|
|
EQep2Regs.QUPRD = 0x00000000;
|
|
// eQEP Watchdog Timer Register
|
|
EQep2Regs.QWDTMR = 0x0000;
|
|
// eQEP Watchdog Period Register
|
|
EQep2Regs.QWDPRD = 0x0000;
|
|
// eQEP Interrupt Enable Register
|
|
EQep2Regs.QEINT.all = 0x0000;
|
|
// eQEP Capture Timer Register
|
|
EQep2Regs.QCTMR = 0x0000;
|
|
// eQEP Capture Period Register
|
|
EQep2Regs.QCPRD = 0x0000;
|
|
} //void SetupEqep(void)
|