34 lines
1017 B
C
34 lines
1017 B
C
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#define ADC_usDELAY 8000L
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#define ADC_usDELAY2 20L
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// Determine when the shift to right justify the data takes place
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// Only one of these should be defined as 1.
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// The other two should be defined as 0.
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#define POST_SHIFT 0 // Shift results after the entire sample table is full
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#define INLINE_SHIFT 1 // Shift results as the data is taken from the results regsiter
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#define NO_SHIFT 0 // Do not shift the results
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// ADC start parameters
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#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25MHz
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#define ADC_CKPS 0x0 // ADC module clock = HSPCLK/1 = 25MHz/(1) = 25MHz
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#define ADC_SHCLK 0x1 // S/H width in ADC module periods = 2 ADC cycle
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#define AVG 1000 // Average sample limit
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#define ZOFFSET 0x00 // Average Zero offset
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#define BUF_SIZE 100 // Sample buffer size
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#define FREQ_ADC 15000.0//26.08.2009//73000.0
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#define read_ADC(c) (*(&AdcRegs.ADCRESULT0+c)>>4)
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#define SDVIG_K_FILTER_S 2 //1//(27.08.2009) //3
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