149 lines
4.1 KiB
C
149 lines
4.1 KiB
C
/*
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* detect_error_3_phase.h
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*
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* Created on: 7 äåê. 2020 ã.
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* Author: star
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*/
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#ifndef SRC_MAIN_DETECT_ERROR_3_PHASE_H_
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#define SRC_MAIN_DETECT_ERROR_3_PHASE_H_
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#include <detect_phase_break.h>
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typedef struct {
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_iq iqVal_module_max;
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_iq iqVal_U_max;
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_iq iqVal_V_max;
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_iq iqVal_W_max;
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_iq iqNominal_plus10;
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_iq iqNominal_plus20;
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_iq iqNominal_minus10;
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_iq iqNominal_minus20;
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_iq iqAsymmetry_delta;
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} PROTECT_LEVELS_3_PHASE;
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#define PROTECT_LEVELS_3_PHASE_DEFAULTS {0,0,0,0,0,0,0, 0,0}
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typedef struct {
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PROTECT_LEVELS_3_PHASE levels;
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union {
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unsigned int all;
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struct {
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unsigned int phase_U :1;
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unsigned int phase_V :1;
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unsigned int phase_W :1;
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unsigned int module :1;
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unsigned int detect_minus_10 :1;
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unsigned int detect_minus_20 :1;
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unsigned int detect_plus_10 :1;
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unsigned int detect_plus_20 :1;
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unsigned int system_asymmetry_by_summ :1; //Ñóììà 3-õ ñîñòàâëÿþùèõ ðàâíà 0
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unsigned int system_asymmetry_by_delta :1; //Äåéñòâóþùèå çíà÷åíèÿ 3-õ ñîñòàâëÿþùèõ ðàâíû ìåæäó ñîáîé
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unsigned int break_phase :1;
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unsigned int reserved :5;
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} bits;
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} use;
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unsigned int timers_inited;
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} SETUP_3_PHASE_PROTECT;
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#define SETUP_3_PHASE_PROTECT_DEFAULTS {PROTECT_LEVELS_3_PHASE_DEFAULTS, {0}, 0}
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typedef struct {
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//In values
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_iq iqVal_U;
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_iq iqVal_V;
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_iq iqVal_W;
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_iq iqVal_mod;
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_iq iqTeta; //Íóæåí äëÿ îïðåäåëåíèÿ îáðûâà ôàçû
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unsigned int timer_low_minus_10;
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unsigned int timer_low_minus_20;
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unsigned int timer_high_plus_10;
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unsigned int timer_high_plus_20;
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//Break phase I state values
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BREAK_PHASE_I *break_phase;
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//Out values
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union {
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unsigned int all;
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struct {
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unsigned int phase_U_max :1;
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unsigned int phase_V_max :1;
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unsigned int phase_W_max :1;
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unsigned int module_max :1;
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unsigned int module_10_percent_hi :1;
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unsigned int module_20_percent_hi :1;
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unsigned int module_10_percent_low :1;
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unsigned int module_20_percent_low :1;
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unsigned int system_asymmetry :1;
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unsigned int break_phase :1;
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unsigned int break_phase_U :1;
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unsigned int break_phase_V :1;
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unsigned int break_phase_W :1;
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unsigned int reserved :3;
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} bits;
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} errors;
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union {
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unsigned int all;
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struct {
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unsigned int phase_U_max :1;
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unsigned int phase_V_max :1;
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unsigned int phase_W_max :1;
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unsigned int module_max :1;
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unsigned int module_10_percent_hi :1;
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unsigned int module_20_percent_hi :1;
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unsigned int module_10_percent_low :1;
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unsigned int module_20_percent_low :1;
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unsigned int system_asymmetry_by_summ :1;
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unsigned int break_phase :1;
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unsigned int break_phase_U :1;
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unsigned int break_phase_V :1;
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unsigned int break_phase_W :1;
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unsigned int reserved :3;
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} bits;
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} over_limit;
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unsigned int new_timer_low_minus_10;
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unsigned int new_timer_low_minus_20;
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unsigned int new_timer_high_plus_10;
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unsigned int new_timer_high_plus_20;
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//Setup
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SETUP_3_PHASE_PROTECT setup;
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int (*calc_detect_error_3_phase)();
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} DETECT_PROTECT_3_PHASE;
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#define DETECT_PROTECT_3_PHASE_DEFAULTS {0,0,0,0,0, 0,0,0,0, 0, {0},{0}, 0,0,0,0,\
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SETUP_3_PHASE_PROTECT_DEFAULTS, \
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detect_error_3_phase}
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#define ADC_PROTECT_LEVELS_DEFAULT {0,0,0,0, 0,0,0,0, 0}
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#define PAUSE_VAL_MINIS_10_S 10000
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#define PAUSE_VAL_MINIS_20_S 1000
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#define PAUSE_VAL_PLUS_10_S 10000
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#define PAUSE_VAL_PLUS_20_S 1000
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#define PLUS_10_PERCENT 1.1
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#define PLUS_20_PERCENT 1.2
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#define MINUS_10_PERCENT 0.9
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#define MINUS_20_PERCENT 0.8
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#define ASYMMETRY_DELTA_PERCENTS 0.2
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int detect_error_3_phase(DETECT_PROTECT_3_PHASE *v);
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#endif /* SRC_MAIN_DETECT_ERROR_3_PHASE_H_ */
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