2024-12-27 10:50:32 +03:00
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#include <adc_tools.h>
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#include <detect_errors_adc.h>
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#include <edrk_main.h>
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#include <math.h>
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#include <message_modbus.h>
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#include <modbus_hmi.h>
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#include <modbus_hmi_read.h>
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#include <modbus_hmi_update.h>
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#include <optical_bus.h>
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#include <params.h>
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#include <params_norma.h>
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#include <project.h>
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#include <protect_levels.h>
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#include <pump_control.h>
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#include <v_rotor.h>
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#include <vector.h>
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#include "edrk_main.h"
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#include "global_time.h"
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#include "control_station.h"
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#include "CAN_Setup.h"
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#include "global_time.h"
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#include "RS_Functions.h"
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#include "mathlib.h"
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/*
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#include "mathlib.h"
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#include <math.h>
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#include "IQmathLib.h"
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*/
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int hmi_watch_dog = 0;
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int prev_kvitir = 0;
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int prev_sbor = 0;
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int kvitir1 = 0;
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int sbor1 = 0;
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int razbor1 = 0;
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//30001 ResetErrors command to controller to reset errors 1-reset
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//30002 SchemeAssemble Command to change scheme state 0-scheme dissasemble 1- assemble
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//30003 IsPowerSetMode 0-control enigine by turnovers, 1- by power
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//30004 SpecifiedPower Power set by user
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//30005 SpecifiedTurnovers Turnovers set by user
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//30006 UserValueUpdated command to controller to update set value 1-ative
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//30007 ReportGet Command to get report 1-get 0- nothinhg
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//30008 ReportArraySaved Sets to 1 when HMI is ready to get array(part of report)
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//30009 PumpsControlMode Pumps Control mode. 0 = auto, 1= pump 1, 2= pump 2
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//30010 MotoHoursPanel <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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//30011 MotoHoursFan1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1 (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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//30012 MotoHoursFan2 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2 (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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//30013 MotoHoursPump1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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//30014 MotoHoursPump2 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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//30015 MotoHoursInvertorCharged <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ""<22><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"" (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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//30016 MotoHoursInvertorGo <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ""<22><><EFBFBD>"" (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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//30017 MotoHoursInvertorGoFault <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ""<22><><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"" (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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//30018 MotoHoursInvertorAlarm <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ""<22><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"" (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
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2025-01-15 13:39:33 +03:00
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#define COUNT_ANALOG_DATA_FROM_INGETEAM 200 //(18+1)
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2024-12-27 10:50:32 +03:00
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///////////////////////////////////////////////////
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///
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///////////////////////////////////////////////////
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void func_unpack_answer_from_Ingeteam(unsigned int cc)
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{
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>y <20><><EFBFBD><EFBFBD><EFBFBD>
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unsigned int DataOut;
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int Data, Data1, Data2, DataAnalog1, DataAnalog2, DataAnalog3, DataAnalog4, i;
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unsigned int h;
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volatile unsigned char *pByte;
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// static int vs11,vs12,vs1;
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// static int DataCnt=0;
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// int GoT,Assemble_scheme;
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// static int prev_temp_Rele1=0, temp_Rele1=0, prev_temp_Rele2=0, temp_Rele2=0;
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static int flag_prev_turn_on = 0;
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static int flag_prev_turn_off = 0;
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static int prev_byte01_bit4 = 0;
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static int prev_byte01_bit1 = 0;
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static int flag_wait_revers_sbor = 1;
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static int flag_wait_revers_go = 1;
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static unsigned int count_transmited = 0;
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>y <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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// <20><><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
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if (COUNT_ANALOG_DATA_FROM_INGETEAM > CONTROL_STATION_MAX_RAW_DATA)
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xerror(main_er_ID(2),(void *)0);
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for (h=1;h<COUNT_ANALOG_DATA_FROM_INGETEAM;h++)
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control_station.raw_array_data[cc][h].all = modbus_table_analog_in[h].all;
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}
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///////////////////////////////////////////////////
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///
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///////////////////////////////////////////////////
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void get_command_HMI(void)
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{
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2025-01-15 13:39:33 +03:00
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if (modbus_table_analog_in[1].all == 1)
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2024-12-27 10:50:32 +03:00
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{
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if (prev_kvitir==0)
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kvitir1 = 1;
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}
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else
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kvitir1 = 0;
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// edrk.KvitirDISPLAY = kvitir1;
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// edrk.from_display.bits.KVITIR = kvitir1;
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control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_CHECKBACK] = kvitir1;
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2025-01-15 13:39:33 +03:00
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prev_kvitir = modbus_table_analog_in[1].all;
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2024-12-27 10:50:32 +03:00
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2025-01-15 13:39:33 +03:00
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/////////////////
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if (modbus_table_analog_in[2].all == 1)
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2024-12-27 10:50:32 +03:00
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{
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if (prev_sbor==0)
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{
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sbor1 = 1;
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}
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razbor1 = 0;
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}
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else
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{
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if (prev_sbor==1)
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{
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razbor1 = 1;
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}
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sbor1 = 0;
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}
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edrk.from_display.bits.SBOR_SHEMA = sbor1;
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2025-01-15 13:39:33 +03:00
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// edrk.from_display.bits.RAZBOR_SHEMA = razbor1;
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2024-12-27 10:50:32 +03:00
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2025-01-15 13:39:33 +03:00
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prev_sbor = modbus_table_analog_in[2].all;
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2024-12-27 10:50:32 +03:00
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2025-01-15 13:39:33 +03:00
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log_to_HMI.send_log = modbus_table_analog_in[7].all;
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2024-12-27 10:50:32 +03:00
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2025-01-15 13:39:33 +03:00
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control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_MODE_PUMP] = modbus_table_analog_in[9].all;
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// mode_pump = modbus_table_analog_in[9].all;
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// 0 - auto on - rand pump
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// 1 - auto on 1 pump
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// 2 - auto on 2 pump
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// 3 - manual on 1 pump
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// 4 - manual on 2 pump
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//////////////////////
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pumps.pump1_engine_minutes = modbus_table_analog_in[13].all;
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pumps.pump2_engine_minutes = modbus_table_analog_in[14].all;
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2024-12-27 10:50:32 +03:00
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2025-01-15 13:39:33 +03:00
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/*
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control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = modbus_table_analog_in[188].all;
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control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_QTV] = modbus_table_analog_in[189].all;
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control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_UMP] = modbus_table_analog_in[190].all;
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control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = modbus_table_analog_in[191].all;
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control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_MANUAL_DISCHARGE] = modbus_table_analog_in[180].all;
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control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_GO] = !modbus_table_analog_in[192].all;
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*/
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2024-12-27 10:50:32 +03:00
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// control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_] = modbus_table_analog_in[188].all;
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parse_protect_levels_HMI();
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}
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///////////////////////////////////////////////////
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///
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///////////////////////////////////////////////////
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int update_progress_load_hmi(int proc_load)
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{
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static unsigned int old_time_5 = 0;
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volatile int perc_load=0, final_code = 0, c_l = 0;
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// return 0;
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update_tables_HMI_on_inited(proc_load);
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old_time_5 = global_time.miliseconds;
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do
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{
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if (final_code >= 4)
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{
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return 1;
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}
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// if (control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485]==0)
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// final_code = modbusNetworkSharing(0);
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// else
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final_code = modbusNetworkSharing(1);
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// RS232_WorkingWith(0,1,0);
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}
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while (detect_pause_milisec(1500, &old_time_5)==0);//(100,&old_time));
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return 0;
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}
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///////////////////////////////////////////////////
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///
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///////////////////////////////////////////////////
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void update_tables_HMI_on_inited(int perc_load)
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{
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Inverter_state state;
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static int nn=0, ss=0;
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static int prev_edrk_KVITIR=0;
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int i,status;
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2025-01-15 13:39:33 +03:00
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log_to_HMI.send_log = modbus_table_analog_in[7].all;
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2024-12-27 10:50:32 +03:00
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//setRegisterDiscreteOutput(log_to_HMI.flag_log_array_ready_sent, 310);
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// LoadMode Read 00544 00544 <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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setRegisterDiscreteOutput(0, 544);//
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// Loading ReadWrite 30088 40088 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0-10
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modbus_table_analog_out[88].all = perc_load;
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// <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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modbus_table_analog_out[4].all++;
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}
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///////////////////////////////////////////////////
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///
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///////////////////////////////////////////////////
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void update_tables_HMI_discrete(void)
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{
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// <20><><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>!!!
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// if (edrk.from_display.bits.KVITIR)
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// setRegisterDiscreteOutput(edrk.from_display.bits.KVITIR, 301);
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setRegisterDiscreteOutput(control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_CHECKBACK], 513);
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|
|
// prev_edrk_KVITIR = edrk.from_display.bits.KVITIR;
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|
|
/////
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|
//setRegisterDiscreteOutput(edrk.RemouteFromDISPLAY, 302);
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|
|
setRegisterDiscreteOutput(control_station.active_control_station[CONTROL_STATION_INGETEAM_PULT_RS485], 514);
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|
|
setRegisterDiscreteOutput(hmi_watch_dog, 515);
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|
|
setRegisterDiscreteOutput(edrk.StatusFunAll, 516);
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|
setRegisterDiscreteOutput(edrk.StatusFunAll, 517);
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|
setRegisterDiscreteOutput(edrk.StatusPump0, 518);
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|
setRegisterDiscreteOutput(edrk.StatusPump1, 519);
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|
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>_<EFBFBD><5F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>_<EFBFBD><5F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>_<EFBFBD><5F> Read 00523
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>_<EFBFBD><5F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>_<EFBFBD><5F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>_<EFBFBD><5F><EFBFBD> Read 00524
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|
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>_<EFBFBD><5F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>_<EFBFBD><5F><EFBFBD><EFBFBD><EFBFBD> Read 00525
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setRegisterDiscreteOutput(edrk.from_ing1.bits.OHLAD_UTE4KA_WATER, 526);//
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|
setRegisterDiscreteOutput(edrk.from_ing1.bits.NASOS_NORMA, 527);//
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|
setRegisterDiscreteOutput(edrk.from_ing1.bits.OP_PIT_NORMA, 528);//
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|
setRegisterDiscreteOutput(edrk.from_ing1.bits.UPC_24V_NORMA, 529);//
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|
setRegisterDiscreteOutput(edrk.from_ing1.bits.ALL_KNOPKA_AVARIA, 530);//
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|
setRegisterDiscreteOutput(edrk.SumSbor, 531);//
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|
setRegisterDiscreteOutput(edrk.from_ing1.bits.ZARYAD_ON, 532);//
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|
setRegisterDiscreteOutput(edrk.from_ing1.bits.VIPR_PREDOHR_NORMA, 533);//
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|
setRegisterDiscreteOutput(!edrk.temper_limit_koeffs.code_status, 534);//
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|
// setRegisterDiscreteOutput(1, 331);//
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|
setRegisterDiscreteOutput(edrk.from_ing1.bits.ZAZEML_ON, 535);//
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|
setRegisterDiscreteOutput(edrk.from_ing1.bits.NAGREV_ON, 536);//
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|
setRegisterDiscreteOutput(edrk.from_ing1.bits.BLOCK_IZOL_NORMA, 537);//
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|
|
setRegisterDiscreteOutput(edrk.from_ing1.bits.BLOCK_IZOL_AVARIA, 538);//
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|
//////////////
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|
// schemeStateOnController ReadWrite 00539 00539 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0 - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, 1-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
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|
// StateAnotherPowerChannel Read 00540 00540 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: 0 - <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, 1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
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|
// InterfaceOpticalBus Read 00541 00541 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>: 0 - <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, 1 - <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>
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|
// StateDriver Read 00542 00542 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: 0 - <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>, 1 - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>
|
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|
|
// NumberPowerChannel Read 00543 00543 <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: 0 - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, 1 - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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|
|
setRegisterDiscreteOutput(edrk.Status_Ready.bits.ready_final, 539);
|
|
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|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.ANOTHER_BS_ALARM, 540);
|
|
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|
|
setRegisterDiscreteOutput(optical_read_data.status == 1 && optical_write_data.status == 1 ? 1 : 0, 541);
|
|
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|
|
setRegisterDiscreteOutput(edrk.Status_Rascepitel_Ok, 542);
|
|
|
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|
|
|
|
|
|
if (edrk.flag_second_PCH==0)
|
|
|
|
|
setRegisterDiscreteOutput(0, 543);
|
|
|
|
|
else
|
|
|
|
|
setRegisterDiscreteOutput(1, 543);
|
|
|
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|
|
// LoadMode Read 00544 00544 <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
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|
|
setRegisterDiscreteOutput(1, 544); //
|
|
|
|
|
|
|
|
|
|
// Loading ReadWrite 30088 40088 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0-10
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(control_station.active_array_cmd[CONTROL_STATION_CMD_BLOCK_BS]
|
|
|
|
|
|| edrk.from_shema.bits.SVU_BLOCK_QTV, 545);
|
|
|
|
|
//////////////
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk0_ack, 17);//
|
|
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|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk1_ack, 18);//
|
|
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|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk2_ack, 19);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk3_ack, 20);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk4_ack, 21);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk5_ack, 22);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk6_ack, 23);//
|
|
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|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk7_ack, 24);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk0_ack, 25);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk1_ack, 26);//
|
|
|
|
|
/////////////////////
|
|
|
|
|
if (edrk.flag_second_PCH==0)
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e4.bits.ANOTHER_BS_POWER_OFF, 27);
|
|
|
|
|
else
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e4.bits.ANOTHER_BS_POWER_OFF, 28);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk0_current, 33);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk1_current, 34);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk2_current, 35);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk3_current, 36);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk4_current, 37);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk5_current, 38);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk6_current, 39);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk7_current, 40);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk0_current, 41);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk1_current, 42);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk2_current, 43);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk3_current, 44);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk4_current, 45);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk5_current, 46);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk6_current, 47);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk7_current, 48);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk0_current, 49);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk1_current, 50);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk2_current, 51);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk3_current, 52);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk4_current, 53);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk5_current, 54);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk6_current, 55);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk7_current, 56);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk0_current, 57);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk1_current, 58);//
|
|
|
|
|
//////////////////////////
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 65);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 66);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 67);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 68);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 69);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 70);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 71);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 72);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 73);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 74);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 75);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 76);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 77);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 78);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 79);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 80);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 81);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 82);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 83);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 84);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 85);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 86);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 87);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 88);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 89);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 90);//
|
|
|
|
|
|
|
|
|
|
/////////////////
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_TK_0, 97);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_TK_1, 98);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_TK_2, 99);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_TK_3, 100);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_IN_0, 101);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_IN_1, 102);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_OUT_0, 103);//
|
|
|
|
|
// setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_OUT_1, 105);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_ADC_0, 104);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_HWP_0, 105);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_ADC_1, 106);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_CONTR, 107);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
///////////////////
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.KEY_AVARIA, 113);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER, 114);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.SVU_BLOCK_ON_QTV
|
|
|
|
|
|| control_station.active_array_cmd[CONTROL_STATION_CMD_BLOCK_BS], 115);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.UMP_NOT_ANSWER, 116);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.UMP_NOT_READY, 117);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e6.bits.RASCEPITEL_ERROR_NOT_ANSWER, 118);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.ANOTHER_RASCEPITEL_ON, 119);
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.AUTO_SET_MASTER, 120);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.ANOTHER_PCH_NOT_ANSWER, 121);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.WDOG_OPTICAL_BUS, 122);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.ERROR_RAZBOR_SHEMA, 123);
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.NO_CONFIRM_ON_RASCEPITEL, 124);
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.ANOTHER_BS_NOT_ON_RASCEPITEL, 125);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.ANOTHER_BS_VERY_LONG_WAIT, 126);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.VERY_LONG_BOTH_READY2, 127);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.BOTH_KEYS_CHARGE_DISCHARGE, 128);
|
|
|
|
|
|
|
|
|
|
// setRegisterDiscreteOutput(edrk.errors.e5.bits.OP_PIT, 115);//
|
|
|
|
|
// setRegisterDiscreteOutput(edrk.errors.e5.bits.POWER_UPC, 116);//
|
|
|
|
|
///////////////////
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(!control_station.alive_control_station[CONTROL_STATION_ZADATCHIK_CAN], 129);
|
|
|
|
|
setRegisterDiscreteOutput(!control_station.alive_control_station[CONTROL_STATION_MPU_SVU_CAN], 130);
|
|
|
|
|
// setRegisterDiscreteOutput(CAN_timeout[get_real_in_mbox(UNITS_TYPE_BOX,UMU_CAN_DEVICE)], 131); <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD>
|
2025-01-15 13:39:33 +03:00
|
|
|
|
setRegisterDiscreteOutput(CAN_timeout[get_real_in_mbox(UNITS_TYPE_BOX,BKSSD_CAN_DEVICE)], 132);
|
|
|
|
|
setRegisterDiscreteOutput(CAN_timeout[get_real_in_mbox(UNITS_TYPE_BOX,VPU_CAN)], 133);
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(CAN_timeout[get_real_in_mbox(UNITS_TYPE_BOX,ANOTHER_BSU1_CAN_DEVICE)], 134);
|
2024-12-27 10:50:32 +03:00
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.CAN2CAN_BS, 135);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if (edrk.flag_second_PCH==0)
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e4.bits.ANOTHER_BS_POWER_OFF, 137);
|
|
|
|
|
else
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e4.bits.ANOTHER_BS_POWER_OFF, 136);
|
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e4.bits.FAST_OPTICAL_ALARM, 138);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e4.bits.FAST_OPTICAL_ALARM, 139);
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
///
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk0_ack, 145);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk1_ack, 146);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk2_ack, 147);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk3_ack, 148);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk4_ack, 149);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk5_ack, 150);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk6_ack, 151);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk7_ack, 152);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk0_ack, 153);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk1_ack, 154);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk2_ack, 155);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk3_ack, 156);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk4_ack, 157);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk5_ack, 158);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk6_ack, 159);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk7_ack, 160);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// setRegisterDiscreteOutput(edrk.errors.e5.bits.KEY_AVARIA, 243);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.OP_PIT, 161);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.UTE4KA_WATER, 162);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.BLOCK_DOOR, 163);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_PRE_CHARGE_ON, 164);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.FAN, 165);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.PUMP_1, 166);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.PRE_READY_PUMP, 167);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_HEAT, 168);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_PRED_VIPR, 170);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_ISOLATE, 171);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.POWER_UPC, 172);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_GROUND_NET, 173);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.PUMP_2, 174);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e5.bits.ERROR_ISOLATE, 175);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e5.bits.PRE_READY_PUMP, 176);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
///////////////////
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_1_MAX, 177);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_2_MAX, 178);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_1_MIN, 179);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_2_MIN, 180);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_A1B1_MAX, 181);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_A2B2_MAX, 182);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_B1C1_MAX, 183);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_B2C2_MAX, 184);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_A1B1_MIN, 185);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_A2B2_MIN, 186);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_B1C1_MIN, 187);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_B2C2_MIN, 188);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_IN_MAX, 189);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e0.bits.U_IN_MIN, 190);//
|
|
|
|
|
|
|
|
|
|
// setRegisterDiscreteOutput(edrk.errors.e0.bits.I_1_MAX, 191);//
|
|
|
|
|
// setRegisterDiscreteOutput(edrk.errors.e0.bits.I_2_MAX, 192);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//////////////
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO2_MAX, 193);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO3_MAX, 194);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO4_MAX, 195);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO5_MAX, 196);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO6_MAX, 197);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO7_MAX, 198);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.I_BREAK_1_MAX, 199);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.I_BREAK_2_MAX, 200);//
|
|
|
|
|
|
|
|
|
|
// setRegisterDiscreteOutput(edrk.errors.e1.bits.HWP_ERROR, 201);//
|
|
|
|
|
////////////////////
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_AIR0_MAX, 203);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_AIR1_MAX, 204);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_AIR2_MAX, 205);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_AIR3_MAX, 206);//
|
|
|
|
|
|
|
|
|
|
////////////////////
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_PRE_CHARGE_ON, 209);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.ERROR_SBOR_SHEMA, 210);//
|
|
|
|
|
|
|
|
|
|
/////////////////////
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch0, 225);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch1, 226);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch2, 227);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch3, 228);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch4, 229);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch5, 230);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch6, 231);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch7, 232);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch8, 234);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch10, 235);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch11, 236);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch12, 237);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch13, 238);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch14, 239);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch15, 240);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
////////////////////
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.LINE_ERR0, 241);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.LINE_HWP, 242);//
|
|
|
|
|
////////////////////
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch2, 243);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch3, 244);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch4, 245);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch5, 246);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch6, 247);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch7, 248);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch8, 250);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch10, 251);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch11, 252);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch12, 253);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch13, 254);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch14, 255);//
|
|
|
|
|
setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch15, 256);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
////////////////////
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_INPUT_A1B1, 257);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_INPUT_B1C1, 258);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_INPUT_A2B2, 259);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_INPUT_B2C2, 260);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.LOW_FREQ_50HZ, 261);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e8.bits.LOW_FREQ_50HZ, 262);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.READ_OPTBUS || edrk.errors.e7.bits.WRITE_OPTBUS, 263);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.MASTER_SLAVE_SYNC, 264); //
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e6.bits.ERR_SBUS, 265);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e6.bits.ERR_PBUS, 266);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e6.bits.ER_DISBAL_BATT, 267);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e6.bits.QTV_ERROR_NOT_U, 268);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e6.bits.ERROR_PRE_CHARGE_U, 269);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.U_IN_20_PROCENTS_HIGH, 270);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.U_IN_10_PROCENTS_LOW, 271);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.U_IN_20_PROCENTS_LOW, 272);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
////////////////
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.err_power, 273);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.err_power, 274);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.err_power, 275);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.lock_status_error.bit.err_power, 276);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_in[0].read.sbus.lock_status_error.bit.err_power, 277);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_in[1].read.sbus.lock_status_error.bit.err_power, 278);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_out[0].read.sbus.lock_status_error.bit.err_power, 279);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.NOT_VALID_CONTROL_STATION, 280);//
|
|
|
|
|
|
|
|
|
|
////////////////
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_U1, 281);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_V1, 282);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_W1, 283);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_U2, 284);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_V2, 285);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_W2, 286);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e8.bits.DISBALANCE_IM1_IM2, 287);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.VERY_FAST_GO_0to1, 288);//
|
|
|
|
|
|
|
|
|
|
////////////////
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.err_switch, 289);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.err_switch, 290);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.err_switch, 291);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.lock_status_error.bit.err_switch, 292);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_in[0].read.sbus.lock_status_error.bit.err_switch, 293);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_in[1].read.sbus.lock_status_error.bit.err_switch, 294);//
|
|
|
|
|
setRegisterDiscreteOutput(project.cds_out[0].read.sbus.lock_status_error.bit.err_switch, 295);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(project.adc[0].read.sbus.lock_status_error.bit.err_switch, 296);//
|
|
|
|
|
setRegisterDiscreteOutput(project.adc[1].read.sbus.lock_status_error.bit.err_switch, 298);//
|
|
|
|
|
|
|
|
|
|
////////////////
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO1_MAX, 305);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO2_MAX, 306);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO3_MAX, 307);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO4_MAX, 308);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO5_MAX, 309);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO6_MAX, 310);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO7_MAX, 311);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO1_MAX, 312);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO2_MAX, 313);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO3_MAX, 314);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO4_MAX, 315);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO5_MAX, 316);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO6_MAX, 317);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO7_MAX, 318);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/////////////////////
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e7.bits.READ_OPTBUS || edrk.warnings.e7.bits.WRITE_OPTBUS, 321);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e7.bits.MASTER_SLAVE_SYNC, 322);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e6.bits.ERROR_PRE_CHARGE_ANSWER, 323);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e1.bits.NO_INPUT_SYNC_SIGNAL, 324);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e1.bits.NO_INPUT_SYNC_SIGNAL, 325);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e3.bits.ERR_INT_PWM_LONG
|
|
|
|
|
|| edrk.errors.e9.bits.ERR_PWM_WDOG
|
|
|
|
|
|| edrk.errors.e9.bits.ERR_INT_PWM_VERY_LONG, 326);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e5.bits.T_VIPR_MAX, 336);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_AIR0_MAX, 337);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_AIR1_MAX, 338);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_AIR2_MAX, 339);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_AIR3_MAX, 340);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_BSU_Sensor_BK1, 341);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e10.bits.T_BSU_Sensor_BK1, 342);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_BSU_Sensor_BK2, 343);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e10.bits.T_BSU_Sensor_BK2, 344);
|
|
|
|
|
//////
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_WATER_EXT_MAX, 345);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.T_WATER_INT_MAX, 346);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_WATER_EXT_MAX, 347);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_WATER_INT_MAX, 348);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e7.bits.T_ACDRIVE_BEAR_MAX_DNE, 349);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e9.bits.T_ACDRIVE_BEAR_MAX_NE, 350);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e7.bits.T_ACDRIVE_BEAR_MAX_DNE, 351);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e9.bits.T_ACDRIVE_BEAR_MAX_NE, 352);//
|
|
|
|
|
|
|
|
|
|
//////////////
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_U1, 353);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_V1, 354);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_W1, 355);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_U2, 356);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_V2, 357);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_W2, 358);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1, 359);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V1, 360);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W1, 361);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U2, 362);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V2, 363);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W2, 364);//
|
|
|
|
|
|
|
|
|
|
////////////////////
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.P_WATER_INT_MAX, 369);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.errors.e2.bits.P_WATER_INT_MIN, 370);//
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.P_WATER_INT_MAX, 371);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e2.bits.P_WATER_INT_MIN, 372);//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
////
|
2025-01-15 13:39:33 +03:00
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_PUMP_ON_SBOR, 385);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_RESTART_PUMP_1_ON_SBOR, 386);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_RESTART_PUMP_2_ON_SBOR, 387);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_RESTART_PUMP_ALL_ON_SBOR, 388);
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_PRED_ZARYAD, 389);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_PRED_ZARYAD_AFTER, 390);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_READY_UMP_BEFORE_QTV, 391);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_STATUS_QTV, 392);
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_UMP_ON_AFTER, 393);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_UMP_NOT_ON, 394);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_UMP_NOT_OFF, 395);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_RASCEPITEL_WAIT_CMD, 396);
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_RASCEPITEL_ON_AFTER, 397);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_DISABLE_SBOR, 398);
|
|
|
|
|
setRegisterDiscreteOutput(edrk.warnings.e11.bits.ERROR_VERY_LONG_SBOR, 399);
|
|
|
|
|
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
//////////////////
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER ||
|
|
|
|
|
edrk.Mode_ScalarVectorUFConst == ALG_MODE_SCALAR_POWER) {
|
|
|
|
|
setRegisterDiscreteOutput(1, 520);
|
|
|
|
|
} else {
|
|
|
|
|
setRegisterDiscreteOutput(0, 520);
|
|
|
|
|
}
|
|
|
|
|
// setRegisterDiscreteOutput(TODO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>, 546);//
|
|
|
|
|
setRegisterDiscreteOutput(!edrk.from_ing1.bits.UPC_24V_NORMA, 546);//
|
|
|
|
|
setRegisterDiscreteOutput(edrk.from_ing2.bits.SOST_ZAMKA, 547);//
|
2025-01-15 13:39:33 +03:00
|
|
|
|
setRegisterDiscreteOutput(edrk.from_shema.bits.READY_UMP, 548);//
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
////////////////
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void update_tables_HMI_analog(void)
|
|
|
|
|
{
|
|
|
|
|
Inverter_state state;
|
|
|
|
|
static int nn=0, ss=0, pl = 0;
|
|
|
|
|
// static int prev_edrk_KVITIR=0;
|
|
|
|
|
int i,status;
|
|
|
|
|
// static int check = 0;
|
|
|
|
|
|
|
|
|
|
hmi_watch_dog = !hmi_watch_dog; //was transmitted, need to change
|
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
log_to_HMI.send_log = modbus_table_analog_in[7].all;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
//setRegisterDiscreteOutput(log_to_HMI.flag_log_array_ready_sent, 310);
|
|
|
|
|
|
|
|
|
|
// setRegisterDiscreteOutput(ss, nn);
|
|
|
|
|
|
|
|
|
|
// <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
modbus_table_analog_out[4].all++;// = ++check;
|
|
|
|
|
// test
|
|
|
|
|
// setRegisterDiscreteOutput(1, 293);
|
|
|
|
|
// setRegisterDiscreteOutput(1, 294);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
state = f.Stop ? state_accident :
|
|
|
|
|
f.fault ? state_fault :
|
|
|
|
|
edrk.Go ? state_go :
|
|
|
|
|
f.Ready2 ? state_ready2 :
|
|
|
|
|
f.Assemble ? state_assemble :
|
|
|
|
|
f.Ready1 ? state_ready1 :
|
|
|
|
|
state_not_init;
|
|
|
|
|
*/
|
|
|
|
|
// setStateHMI(state);
|
|
|
|
|
// setElementsColorsHMI(state);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
f.Assemble = modbus_table_analog_in[2].all;
|
|
|
|
|
f.Mode = modbus_table_analog_in[3].all == 0 ? 1 : //turnovers
|
|
|
|
|
modbus_table_analog_in[3].all == 1 ? 2 : 0; //power
|
|
|
|
|
|
|
|
|
|
setRegisterDiscreteOutput(f.Mode == 2 ? 1 : 0, 308);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if (modbus_table_analog_in[6].all == 1){
|
|
|
|
|
f.p_zad = ((float)modbus_table_analog_in[4].all) * 1000.0; //convert to Watts
|
|
|
|
|
f.iq_p_zad = _IQ(f.p_zad / (float)NORMA_ACP / (float)NORMA_ACP);
|
|
|
|
|
f.fzad = (float)modbus_table_analog_in[5].all / 60.0;
|
|
|
|
|
f.iq_fzad = _IQ(f.fzad / NORMA_FROTOR);
|
|
|
|
|
setRegisterDiscreteOutput(1, 309); //Acknoledge to HMI
|
|
|
|
|
} else {
|
|
|
|
|
setRegisterDiscreteOutput(0, 309);
|
|
|
|
|
}
|
|
|
|
|
modbus_table_analog_out[46].all = _IQtoF((f.iq_p_zad)) * NORMA_ACP * NORMA_ACP / 1000.0;
|
|
|
|
|
modbus_table_analog_out[47].all = _IQtoF((f.iq_fzad)) * NORMA_FROTOR * 60;
|
|
|
|
|
// modbus_table_analog_out[48].all = _IQtoF((analog.iqW1 + analog.iqW2)) * NORMA_ACP * NORMA_ACP / 1000;
|
|
|
|
|
modbus_table_analog_out[49].all = _IQtoF((rotor.iqFout) * NORMA_FROTOR) * 60;
|
|
|
|
|
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
// modbus_table_analog_out[49].all = edrk.W_Ing;
|
|
|
|
|
|
|
|
|
|
|
2024-12-27 10:50:32 +03:00
|
|
|
|
if (edrk.summ_errors)
|
|
|
|
|
{
|
|
|
|
|
modbus_table_analog_out[1].all = 6; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
modbus_table_analog_out[2].all = 3; // red
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[2].all = 1; // green
|
|
|
|
|
|
|
|
|
|
if (edrk.SumSbor)
|
2024-12-27 10:50:32 +03:00
|
|
|
|
{
|
|
|
|
|
if (edrk.Status_Ready.bits.ready_final)
|
|
|
|
|
{
|
|
|
|
|
if (edrk.Go)
|
|
|
|
|
{
|
|
|
|
|
modbus_table_analog_out[1].all = 3; // <20><><EFBFBD>
|
|
|
|
|
if (edrk.Provorot)
|
|
|
|
|
modbus_table_analog_out[1].all = 12; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> = 11
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[1].all = 2; // ready2
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[1].all = 4; // building
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (edrk.Status_Ready.bits.ready1)
|
|
|
|
|
modbus_table_analog_out[1].all = 1; // ready1
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[1].all = 0; // waiting
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (edrk.RazborNotFinish)
|
|
|
|
|
modbus_table_analog_out[1].all = 11; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
|
|
|
|
if (edrk.Status_Perehod_Rascepitel==1 && edrk.cmd_to_rascepitel==1)
|
|
|
|
|
modbus_table_analog_out[1].all = 7; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
|
|
|
|
if (edrk.Status_Perehod_Rascepitel==1 && edrk.cmd_to_rascepitel==0)
|
|
|
|
|
modbus_table_analog_out[1].all = 8; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
|
|
|
|
if (edrk.RunZahvatRascepitel)
|
|
|
|
|
modbus_table_analog_out[1].all = 9; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> = 9
|
|
|
|
|
if (edrk.RunUnZahvatRascepitel)
|
|
|
|
|
modbus_table_analog_out[1].all = 10; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> = 10
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
//modbus_table_analog_out[1].all = 5; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if (edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER || edrk.errors.e6.bits.QTV_ERROR_NOT_U)
|
|
|
|
|
{
|
|
|
|
|
modbus_table_analog_out[10].all = 3;
|
|
|
|
|
modbus_table_analog_out[11].all = 3;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2025-01-15 13:39:33 +03:00
|
|
|
|
if (edrk.from_shema.bits.QTV_ON_OFF)
|
2024-12-27 10:50:32 +03:00
|
|
|
|
{
|
|
|
|
|
modbus_table_analog_out[10].all = 1;
|
|
|
|
|
modbus_table_analog_out[11].all = 1;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
modbus_table_analog_out[10].all = 0;
|
|
|
|
|
modbus_table_analog_out[11].all = 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if (edrk.from_ing1.bits.VIPR_PREDOHR_NORMA==1)
|
|
|
|
|
{
|
2025-01-15 13:39:33 +03:00
|
|
|
|
if (edrk.from_shema.bits.QTV_ON_OFF==1)
|
2024-12-27 10:50:32 +03:00
|
|
|
|
modbus_table_analog_out[12].all = 1;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[12].all = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[12].all = 3;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if (edrk.errors.e6.bits.UO1_KEYS || edrk.errors.e1.bits.I_BREAK_1_MAX || edrk.errors.e1.bits.I_BREAK_2_MAX || edrk.errors.e2.bits.T_UO1_MAX)
|
|
|
|
|
modbus_table_analog_out[13].all = 3;
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e2.bits.T_UO1_MAX)
|
|
|
|
|
modbus_table_analog_out[13].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[13].all = 1;
|
|
|
|
|
|
|
|
|
|
if (edrk.errors.e6.bits.UO2_KEYS || edrk.errors.e1.bits.I_UO2_MAX || edrk.errors.e2.bits.T_UO2_MAX)
|
|
|
|
|
modbus_table_analog_out[14].all = 3;
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e2.bits.T_UO2_MAX)
|
|
|
|
|
modbus_table_analog_out[14].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[14].all = 1;
|
|
|
|
|
|
|
|
|
|
if (edrk.errors.e6.bits.UO3_KEYS || edrk.errors.e1.bits.I_UO3_MAX || edrk.errors.e2.bits.T_UO3_MAX)
|
|
|
|
|
modbus_table_analog_out[15].all = 3;
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e2.bits.T_UO3_MAX)
|
|
|
|
|
modbus_table_analog_out[15].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[15].all = 1;
|
|
|
|
|
|
|
|
|
|
if (edrk.errors.e6.bits.UO4_KEYS || edrk.errors.e1.bits.I_UO4_MAX || edrk.errors.e2.bits.T_UO4_MAX)
|
|
|
|
|
modbus_table_analog_out[16].all = 3;
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e2.bits.T_UO4_MAX)
|
|
|
|
|
modbus_table_analog_out[16].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[16].all = 1;
|
|
|
|
|
|
|
|
|
|
if (edrk.errors.e6.bits.UO5_KEYS || edrk.errors.e1.bits.I_UO5_MAX || edrk.errors.e2.bits.T_UO5_MAX)
|
|
|
|
|
modbus_table_analog_out[17].all = 3;
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e2.bits.T_UO5_MAX)
|
|
|
|
|
modbus_table_analog_out[17].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[17].all = 1;
|
|
|
|
|
|
|
|
|
|
if (edrk.errors.e6.bits.UO6_KEYS || edrk.errors.e1.bits.I_UO6_MAX || edrk.errors.e2.bits.T_UO6_MAX)
|
|
|
|
|
modbus_table_analog_out[18].all = 3;
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e2.bits.T_UO6_MAX)
|
|
|
|
|
modbus_table_analog_out[18].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[18].all = 1;
|
|
|
|
|
|
|
|
|
|
if (edrk.errors.e6.bits.UO7_KEYS || edrk.errors.e1.bits.I_UO7_MAX || edrk.errors.e2.bits.T_UO7_MAX)
|
|
|
|
|
modbus_table_analog_out[19].all = 3;
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e2.bits.T_UO7_MAX)
|
|
|
|
|
modbus_table_analog_out[19].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[19].all = 1;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// motor_state
|
|
|
|
|
if (edrk.errors.e10.bits.T_ACDRIVE_WINDING_U1 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_V1 ||
|
|
|
|
|
edrk.errors.e10.bits.T_ACDRIVE_WINDING_W1 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_U2 ||
|
|
|
|
|
edrk.errors.e10.bits.T_ACDRIVE_WINDING_V2 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_W2 ||
|
2025-01-15 13:39:33 +03:00
|
|
|
|
edrk.errors.e10.bits.T_ACDRIVE_WINDING_U1 || edrk.errors.e9.bits.T_ACDRIVE_BEAR_MAX_NE) {
|
2024-12-27 10:50:32 +03:00
|
|
|
|
modbus_table_analog_out[20].all = 3;
|
|
|
|
|
} else if (edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V1 ||
|
|
|
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W1 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U2 ||
|
|
|
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V2 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W2 ||
|
2025-01-15 13:39:33 +03:00
|
|
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1 || edrk.warnings.e9.bits.T_ACDRIVE_BEAR_MAX_NE) {
|
2024-12-27 10:50:32 +03:00
|
|
|
|
modbus_table_analog_out[20].all = 2;
|
|
|
|
|
} else {
|
|
|
|
|
modbus_table_analog_out[20].all = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// ump state
|
2025-01-15 13:39:33 +03:00
|
|
|
|
if (edrk.from_ing1.bits.ZARYAD_ON || edrk.from_shema.bits.UMP_ON_OFF)
|
|
|
|
|
modbus_table_analog_out[21].all = 1;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (edrk.errors.e7.bits.ERROR_SBOR_SHEMA || edrk.errors.e5.bits.ERROR_PRE_CHARGE_ON ||
|
|
|
|
|
edrk.errors.e6.bits.ERROR_PRE_CHARGE_ANSWER || edrk.errors.e6.bits.ERROR_PRE_CHARGE_U || edrk.errors.e7.bits.UMP_NOT_READY)
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[21].all = 3;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
else
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[21].all = 0;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[30].all = fast_round(_IQtoF(filter.iqUin_m1)*NORMA_ACP/1.41);
|
|
|
|
|
modbus_table_analog_out[31].all = fast_round(_IQtoF(filter.iqUin_m2)*NORMA_ACP/1.41);
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
// if (edrk.Status_Ready.bits.ready_final==0)
|
|
|
|
|
// {
|
|
|
|
|
// modbus_table_analog_out[32].all = edrk.Stage_Sbor;
|
|
|
|
|
// modbus_table_analog_out[33].all = edrk.Sbor_Mode;//_IQtoF(analog.iqIin_1)*NORMA_ACP;
|
|
|
|
|
// }
|
|
|
|
|
// else
|
|
|
|
|
// {
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[32].all = fast_round(_IQtoF(analog.iqIin_1)*NORMA_ACP);
|
|
|
|
|
modbus_table_analog_out[33].all = fast_round(_IQtoF(analog.iqIin_2)*NORMA_ACP);
|
2024-12-27 10:50:32 +03:00
|
|
|
|
// }
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// modbus_table_analog_out[34].all = _IQtoF(filter.iqU_1_long)*NORMA_ACP;
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[35].all = fast_round(_IQtoF(filter.iqU_2_long)*NORMA_ACP);
|
|
|
|
|
modbus_table_analog_out[34].all = fast_round(_IQtoF(filter.iqU_1_long)*NORMA_ACP);
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[36].all = fast_round(_IQtoF(analog.iqIbreak_1)*NORMA_ACP + _IQtoF(analog.iqIbreak_2)*NORMA_ACP);//Ibreak
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// modbus_table_analog_out[37].all = fast_round(_IQtoF(analog.iqIu_1_rms)*NORMA_ACP);
|
|
|
|
|
// modbus_table_analog_out[38].all = fast_round(_IQtoF(analog.iqIv_1_rms)*NORMA_ACP);
|
|
|
|
|
// modbus_table_analog_out[39].all = fast_round(_IQtoF(analog.iqIw_1_rms)*NORMA_ACP);
|
|
|
|
|
//
|
|
|
|
|
// modbus_table_analog_out[40].all = fast_round(_IQtoF(analog.iqIu_2_rms)*NORMA_ACP);
|
|
|
|
|
// modbus_table_analog_out[41].all = fast_round(_IQtoF(analog.iqIv_2_rms)*NORMA_ACP);
|
|
|
|
|
// modbus_table_analog_out[42].all = fast_round(_IQtoF(analog.iqIw_2_rms)*NORMA_ACP);
|
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[37].all = fast_round(_IQtoF(filter.iqIm_1)*NORMA_ACP);
|
|
|
|
|
modbus_table_analog_out[38].all = fast_round(_IQtoF(filter.iqIm_1)*NORMA_ACP);
|
|
|
|
|
modbus_table_analog_out[39].all = fast_round(_IQtoF(filter.iqIm_1)*NORMA_ACP);
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[40].all = fast_round(_IQtoF(filter.iqIm_2)*NORMA_ACP);
|
|
|
|
|
modbus_table_analog_out[41].all = fast_round(_IQtoF(filter.iqIm_2)*NORMA_ACP);
|
|
|
|
|
modbus_table_analog_out[42].all = fast_round(_IQtoF(filter.iqIm_2)*NORMA_ACP);
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
if (edrk.flag_second_PCH == 0) {
|
|
|
|
|
modbus_table_analog_out[43].all = fast_round(_IQtoF(filter.iqIm_1 + filter.iqIm_2)*NORMA_ACP);
|
|
|
|
|
modbus_table_analog_out[44].all = fast_round(_IQtoF(filter.iqIm_1 + filter.iqIm_2)*NORMA_ACP);
|
|
|
|
|
} else {
|
|
|
|
|
modbus_table_analog_out[43].all = fast_round(_IQtoF(filter.iqIm_1 + filter.iqIm_2)*NORMA_ACP);
|
|
|
|
|
modbus_table_analog_out[44].all = fast_round(_IQtoF(filter.iqIm_1 + filter.iqIm_2)*NORMA_ACP);
|
|
|
|
|
}
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
modbus_table_analog_out[45].all = 0; //edrk.I_zad_vozbud_exp;
|
|
|
|
|
|
|
|
|
|
// modbus_table_analog_out[4].all = control_station.active_array_cmd[CONTROL_STATION_CMD_SET_ROTOR];
|
|
|
|
|
// modbus_table_analog_out[5].all = control_station.active_array_cmd[CONTROL_STATION_CMD_SET_POWER];
|
|
|
|
|
|
|
|
|
|
if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_UF_CONST) // UFCONST
|
|
|
|
|
{
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[47].all = fast_round(edrk.zadanie.fzad*100.0); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
2024-12-27 10:50:32 +03:00
|
|
|
|
modbus_table_analog_out[46].all = 0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_SCALAR_OBOROTS) // scalar oborots
|
|
|
|
|
{
|
|
|
|
|
modbus_table_analog_out[47].all = edrk.zadanie.oborots_zad; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[46].all = 0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_SCALAR_POWER) // scalar power
|
|
|
|
|
{
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[47].all = 0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
2024-12-27 10:50:32 +03:00
|
|
|
|
modbus_table_analog_out[46].all = edrk.zadanie.power_zad; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_FOC_OBOROTS) // foc oborots
|
|
|
|
|
{
|
|
|
|
|
modbus_table_analog_out[47].all = edrk.zadanie.oborots_zad; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[46].all = 0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_FOC_POWER) // foc power
|
|
|
|
|
{
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[47].all = 0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
2024-12-27 10:50:32 +03:00
|
|
|
|
modbus_table_analog_out[46].all = edrk.zadanie.power_zad; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[46].all = -1; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
modbus_table_analog_out[47].all = -1; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
2024-12-27 10:50:32 +03:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[48].all = edrk.power_kw; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_UF_CONST) // UFCONST
|
|
|
|
|
{
|
|
|
|
|
modbus_table_analog_out[49].all = fast_round(_IQtoF(edrk.f_stator)*NORMA_FROTOR*100.0);
|
|
|
|
|
// modbus_table_analog_out[48].all = fast_round(_IQtoF((filter.Power) * NORMA_ACP * NORMA_ACP) / 1000.0); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>
|
|
|
|
|
//fast_round(_IQtoF(edrk.k_stator1)*10000.0); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
modbus_table_analog_out[49].all = edrk.oborots;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
// modbus_table_analog_out[48].all = fast_round(_IQtoF((filter.Power) * NORMA_ACP * NORMA_ACP) / 1000.0); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>
|
2025-01-15 13:39:33 +03:00
|
|
|
|
}
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[50].all = edrk.temper_edrk.real_int_temper_water[0]/10;
|
|
|
|
|
modbus_table_analog_out[51].all = edrk.temper_edrk.real_int_temper_water[1]/10;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[52].all = edrk.p_water_edrk.filter_real_int_p_water[0]/10;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[53].all = edrk.temper_edrk.real_int_temper_u[1]/10;
|
|
|
|
|
modbus_table_analog_out[54].all = edrk.temper_edrk.real_int_temper_u[2]/10;
|
|
|
|
|
modbus_table_analog_out[55].all = edrk.temper_edrk.real_int_temper_u[3]/10;
|
|
|
|
|
modbus_table_analog_out[56].all = edrk.temper_edrk.real_int_temper_u[4]/10;
|
|
|
|
|
modbus_table_analog_out[57].all = edrk.temper_edrk.real_int_temper_u[5]/10;
|
|
|
|
|
modbus_table_analog_out[58].all = edrk.temper_edrk.real_int_temper_u[6]/10;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[59].all = edrk.temper_edrk.real_int_temper_u[0]/10;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[60].all = edrk.temper_edrk.real_int_temper_air[0]/10;
|
|
|
|
|
modbus_table_analog_out[61].all = edrk.temper_edrk.real_int_temper_air[1]/10;
|
|
|
|
|
modbus_table_analog_out[62].all = edrk.temper_edrk.real_int_temper_air[2]/10;
|
|
|
|
|
modbus_table_analog_out[63].all = edrk.temper_edrk.real_int_temper_air[3]/10;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
if (edrk.errors.e2.bits.T_AIR0_MAX)
|
|
|
|
|
modbus_table_analog_out[64].all = 3;
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e2.bits.T_AIR0_MAX)
|
|
|
|
|
modbus_table_analog_out[64].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[64].all = 1;
|
|
|
|
|
|
|
|
|
|
if (edrk.errors.e2.bits.T_AIR1_MAX)
|
|
|
|
|
modbus_table_analog_out[65].all = 3;
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e2.bits.T_AIR1_MAX)
|
|
|
|
|
modbus_table_analog_out[65].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[65].all = 1;
|
|
|
|
|
|
|
|
|
|
if (edrk.errors.e2.bits.T_AIR2_MAX)
|
|
|
|
|
modbus_table_analog_out[66].all = 3;
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e2.bits.T_AIR2_MAX)
|
|
|
|
|
modbus_table_analog_out[66].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[66].all = 1;
|
|
|
|
|
|
|
|
|
|
if (edrk.errors.e2.bits.T_AIR3_MAX)
|
|
|
|
|
modbus_table_analog_out[67].all = 3;
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e2.bits.T_AIR3_MAX)
|
|
|
|
|
modbus_table_analog_out[67].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[67].all = 1;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if (edrk.auto_master_slave.local.bits.master)
|
|
|
|
|
modbus_table_analog_out[68].all = 0; // master salve
|
|
|
|
|
else
|
|
|
|
|
if (edrk.auto_master_slave.local.bits.slave)
|
|
|
|
|
modbus_table_analog_out[68].all = 1; // master salve
|
|
|
|
|
else
|
|
|
|
|
if (edrk.auto_master_slave.local.bits.try_master)
|
|
|
|
|
modbus_table_analog_out[68].all = 3; // master salve
|
|
|
|
|
else
|
|
|
|
|
if (edrk.errors.e7.bits.AUTO_SET_MASTER)
|
|
|
|
|
modbus_table_analog_out[68].all = 4; // master salve
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[68].all = 2; // master salve
|
|
|
|
|
|
|
|
|
|
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[69].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[0]);
|
|
|
|
|
modbus_table_analog_out[70].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[1]);
|
|
|
|
|
modbus_table_analog_out[71].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[2]);
|
|
|
|
|
modbus_table_analog_out[72].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[3]);
|
|
|
|
|
modbus_table_analog_out[73].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[4]);
|
|
|
|
|
modbus_table_analog_out[74].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[5]);
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
modbus_table_analog_out[75].all = fast_round(edrk.temper_acdrive.bear.filter_real_temper[0]);
|
|
|
|
|
modbus_table_analog_out[76].all = fast_round(edrk.temper_acdrive.bear.filter_real_temper[1]);
|
|
|
|
|
|
|
|
|
|
for (i=0;i<6;i++)
|
|
|
|
|
{
|
|
|
|
|
status = get_status_temper_acdrive_winding(i);
|
|
|
|
|
if (status==4)
|
|
|
|
|
modbus_table_analog_out[77+i].all = 3;
|
|
|
|
|
if (status==2)
|
|
|
|
|
modbus_table_analog_out[77+i].all = 2;
|
|
|
|
|
if (status==1)
|
|
|
|
|
modbus_table_analog_out[77+i].all = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i=0;i<2;i++)
|
|
|
|
|
{
|
|
|
|
|
status = get_status_temper_acdrive_bear(i);
|
|
|
|
|
if (status==4)
|
|
|
|
|
modbus_table_analog_out[83+i].all = 3;
|
|
|
|
|
if (status==2)
|
|
|
|
|
modbus_table_analog_out[83+i].all = 2;
|
|
|
|
|
if (status==1)
|
|
|
|
|
modbus_table_analog_out[83+i].all = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//UOM
|
|
|
|
|
modbus_table_analog_out[85].all = edrk.from_uom.level_value;
|
|
|
|
|
|
|
|
|
|
if (edrk.from_uom.ready==1)
|
|
|
|
|
{
|
|
|
|
|
if (edrk.from_uom.error)
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[86].all = 1;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
else
|
|
|
|
|
{
|
2025-01-15 13:39:33 +03:00
|
|
|
|
if (edrk.from_uom.level_value==100)
|
|
|
|
|
modbus_table_analog_out[86].all = 2;
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[86].all = 3;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[86].all = 0;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// active control station
|
|
|
|
|
// CONTROL_STATION_TERMINAL_RS232 = 0, -
|
|
|
|
|
// CONTROL_STATION_TERMINAL_CAN, -
|
|
|
|
|
//
|
|
|
|
|
// CONTROL_STATION_INGETEAM_PULT_RS485, -
|
|
|
|
|
// CONTROL_STATION_MPU_SVU_CAN,
|
|
|
|
|
// CONTROL_STATION_MPU_KEY_CAN,
|
|
|
|
|
// CONTROL_STATION_MPU_SVU_RS485,
|
|
|
|
|
// CONTROL_STATION_MPU_KEY_RS485,
|
|
|
|
|
// CONTROL_STATION_ZADATCHIK_CAN,
|
|
|
|
|
// CONTROL_STATION_VPU_CAN,
|
|
|
|
|
|
|
|
|
|
modbus_table_analog_out[87].all = edrk.active_post_upravl;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// load procents
|
|
|
|
|
modbus_table_analog_out[88].all = 0; //error
|
|
|
|
|
|
|
|
|
|
// 0- <20><><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>. [87].
|
|
|
|
|
if (modbus_table_analog_out[87].all == 10)
|
|
|
|
|
modbus_table_analog_out[89].all = 3; //red
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[89].all = 1; //no error
|
|
|
|
|
|
|
|
|
|
/////////////////////////////
|
|
|
|
|
/////////////////////////////
|
|
|
|
|
if (edrk.warnings.e7.bits.READ_OPTBUS
|
|
|
|
|
&& edrk.warnings.e7.bits.WRITE_OPTBUS
|
|
|
|
|
&& edrk.warnings.e7.bits.MASTER_SLAVE_SYNC)
|
|
|
|
|
modbus_table_analog_out[90].all = 2; //warning
|
|
|
|
|
else
|
|
|
|
|
if (edrk.errors.e7.bits.READ_OPTBUS
|
|
|
|
|
|| edrk.errors.e7.bits.WRITE_OPTBUS
|
|
|
|
|
|| edrk.errors.e7.bits.MASTER_SLAVE_SYNC
|
|
|
|
|
|| edrk.errors.e1.bits.NO_INPUT_SYNC_SIGNAL)
|
|
|
|
|
modbus_table_analog_out[90].all = 3; //error
|
|
|
|
|
else
|
|
|
|
|
if (edrk.warnings.e7.bits.READ_OPTBUS
|
|
|
|
|
|| edrk.warnings.e7.bits.WRITE_OPTBUS
|
|
|
|
|
|| edrk.warnings.e7.bits.MASTER_SLAVE_SYNC
|
|
|
|
|
|| edrk.warnings.e1.bits.NO_INPUT_SYNC_SIGNAL)
|
|
|
|
|
modbus_table_analog_out[90].all = 5; //warning
|
|
|
|
|
else
|
|
|
|
|
if (edrk.ms.ready1==0)
|
|
|
|
|
modbus_table_analog_out[90].all = 1; //find
|
|
|
|
|
else
|
|
|
|
|
modbus_table_analog_out[90].all = 0; //ok
|
|
|
|
|
|
|
|
|
|
modbus_table_analog_out[91].all = protect_levels.abnormal_temper_acdrive_winding_U1 / 10;
|
|
|
|
|
modbus_table_analog_out[92].all = protect_levels.abnormal_temper_acdrive_winding_V1 / 10;
|
|
|
|
|
modbus_table_analog_out[93].all = protect_levels.abnormal_temper_acdrive_winding_W1 / 10;
|
|
|
|
|
modbus_table_analog_out[94].all = protect_levels.abnormal_temper_acdrive_winding_U2 / 10;
|
|
|
|
|
modbus_table_analog_out[95].all = protect_levels.abnormal_temper_acdrive_winding_V2 / 10;
|
|
|
|
|
modbus_table_analog_out[96].all = protect_levels.abnormal_temper_acdrive_winding_W2 / 10;
|
|
|
|
|
modbus_table_analog_out[97].all = protect_levels.abnormal_temper_acdrive_bear_DNE / 10;
|
|
|
|
|
modbus_table_analog_out[98].all = protect_levels.abnormal_temper_acdrive_bear_NE / 10;
|
|
|
|
|
|
|
|
|
|
modbus_table_analog_out[99].all = protect_levels.alarm_temper_acdrive_winding_U1 / 10;
|
|
|
|
|
modbus_table_analog_out[100].all = protect_levels.alarm_temper_acdrive_winding_V1 / 10;
|
|
|
|
|
modbus_table_analog_out[101].all = protect_levels.alarm_temper_acdrive_winding_W1 / 10;
|
|
|
|
|
modbus_table_analog_out[102].all = protect_levels.alarm_temper_acdrive_winding_U2 / 10;
|
|
|
|
|
modbus_table_analog_out[103].all = protect_levels.alarm_temper_acdrive_winding_V2 / 10;
|
|
|
|
|
modbus_table_analog_out[104].all = protect_levels.alarm_temper_acdrive_winding_W2 / 10;
|
|
|
|
|
modbus_table_analog_out[105].all = protect_levels.alarm_temper_acdrive_bear_DNE / 10;
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|
|
|
|
modbus_table_analog_out[106].all = protect_levels.alarm_temper_acdrive_bear_NE / 10;
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|
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|
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modbus_table_analog_out[107].all = protect_levels.abnormal_temper_u_01 / 10;
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|
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modbus_table_analog_out[108].all = protect_levels.abnormal_temper_u_02 / 10;
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modbus_table_analog_out[109].all = protect_levels.abnormal_temper_u_03 / 10;
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modbus_table_analog_out[110].all = protect_levels.abnormal_temper_u_04 / 10;
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modbus_table_analog_out[111].all = protect_levels.abnormal_temper_u_05 / 10;
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modbus_table_analog_out[112].all = protect_levels.abnormal_temper_u_06 / 10;
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|
modbus_table_analog_out[113].all = protect_levels.abnormal_temper_u_07 / 10;
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|
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modbus_table_analog_out[114].all = protect_levels.alarm_temper_u_01 / 10;
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|
modbus_table_analog_out[115].all = protect_levels.alarm_temper_u_02 / 10;
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modbus_table_analog_out[116].all = protect_levels.alarm_temper_u_03 / 10;
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modbus_table_analog_out[117].all = protect_levels.alarm_temper_u_04 / 10;
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modbus_table_analog_out[118].all = protect_levels.alarm_temper_u_05 / 10;
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modbus_table_analog_out[119].all = protect_levels.alarm_temper_u_06 / 10;
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modbus_table_analog_out[120].all = protect_levels.alarm_temper_u_07 / 10;
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modbus_table_analog_out[123].all = protect_levels.abnormal_temper_water_int / 10;
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modbus_table_analog_out[124].all = protect_levels.abnormal_temper_water_ext / 10;
|
2025-01-15 13:39:33 +03:00
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modbus_table_analog_out[125].all = protect_levels.alarm_p_water_min_int / 100;
|
2024-12-27 10:50:32 +03:00
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modbus_table_analog_out[126].all = protect_levels.alarm_temper_water_int / 10;
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|
modbus_table_analog_out[127].all = protect_levels.alarm_temper_water_ext / 10;
|
2025-01-15 13:39:33 +03:00
|
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|
modbus_table_analog_out[128].all = protect_levels.alarm_p_water_max_int / 100;
|
2024-12-27 10:50:32 +03:00
|
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|
modbus_table_analog_out[129].all = protect_levels.abnormal_temper_air_int_01 / 10;
|
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|
modbus_table_analog_out[130].all = protect_levels.abnormal_temper_air_int_02 / 10;
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|
modbus_table_analog_out[131].all = protect_levels.abnormal_temper_air_int_03 / 10;
|
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|
|
|
modbus_table_analog_out[132].all = protect_levels.abnormal_temper_air_int_04 / 10;
|
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|
|
|
modbus_table_analog_out[133].all = protect_levels.alarm_temper_air_int_01 / 10;
|
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|
|
|
modbus_table_analog_out[134].all = protect_levels.alarm_temper_air_int_02 / 10;
|
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|
|
|
modbus_table_analog_out[135].all = protect_levels.alarm_temper_air_int_03 / 10;
|
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|
|
|
modbus_table_analog_out[136].all = protect_levels.alarm_temper_air_int_04 / 10;
|
|
|
|
|
|
|
|
|
|
modbus_table_analog_out[137].all = _IQtoF(analog_protect.in_voltage[0].setup.levels.iqNominal_minus20) * NORMA_ACP;//_IQtoF(edrk.iqMIN_U_IN) * NORMA_ACP;
|
|
|
|
|
modbus_table_analog_out[138].all = _IQtoF(analog_protect.in_voltage[1].setup.levels.iqNominal_minus20) * NORMA_ACP;
|
2025-01-15 13:39:33 +03:00
|
|
|
|
modbus_table_analog_out[139].all = _IQtoF(analog_protect.in_voltage[0].setup.levels.iqNominal_plus20) * NORMA_ACP;
|
|
|
|
|
modbus_table_analog_out[140].all = _IQtoF(analog_protect.in_voltage[1].setup.levels.iqNominal_plus20) * NORMA_ACP;
|
|
|
|
|
modbus_table_analog_out[141].all = _IQtoF(edrk.iqMAX_U_IN) * NORMA_ACP;
|
|
|
|
|
modbus_table_analog_out[140].all = _IQtoF(edrk.iqMAX_U_IN) * NORMA_ACP;
|
2024-12-27 10:50:32 +03:00
|
|
|
|
modbus_table_analog_out[144].all = _IQtoF(edrk.iqMAX_U_ZPT) * NORMA_ACP;
|
|
|
|
|
modbus_table_analog_out[145].all = _IQtoF(edrk.iqMAX_U_ZPT) * NORMA_ACP;
|
|
|
|
|
|
|
|
|
|
modbus_table_analog_out[146].all = protect_levels.alarm_Izpt_max;
|
|
|
|
|
|
|
|
|
|
modbus_table_analog_out[155].all = protect_levels.alarm_Imax_U01;
|
|
|
|
|
modbus_table_analog_out[156].all = protect_levels.alarm_Imax_U02;
|
|
|
|
|
modbus_table_analog_out[157].all = protect_levels.alarm_Imax_U03;
|
|
|
|
|
modbus_table_analog_out[158].all = protect_levels.alarm_Imax_U04;
|
|
|
|
|
modbus_table_analog_out[159].all = protect_levels.alarm_Imax_U05;
|
|
|
|
|
modbus_table_analog_out[160].all = protect_levels.alarm_Imax_U06;
|
|
|
|
|
modbus_table_analog_out[161].all = protect_levels.alarm_Imax_U07;
|
|
|
|
|
modbus_table_analog_out[162].all = protect_levels.alarm_Iged_max;
|
|
|
|
|
|
|
|
|
|
}
|
2025-01-15 13:39:33 +03:00
|
|
|
|
///////////////////////////////////////////////////
|
|
|
|
|
///
|
|
|
|
|
///////////////////////////////////////////////////
|
2024-12-27 10:50:32 +03:00
|
|
|
|
|
|
|
|
|
void update_tables_HMI(void)
|
|
|
|
|
{
|
|
|
|
|
update_tables_HMI_analog();
|
|
|
|
|
update_tables_HMI_discrete();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void setStateHMI(Inverter_state state) {
|
|
|
|
|
switch (state) {
|
|
|
|
|
case state_ready1:
|
|
|
|
|
modbus_table_analog_out[1].all = 1;
|
|
|
|
|
modbus_table_analog_out[2].all = 1;
|
|
|
|
|
break;
|
|
|
|
|
case state_ready2:
|
|
|
|
|
modbus_table_analog_out[1].all = 2;
|
|
|
|
|
modbus_table_analog_out[2].all = 1;
|
|
|
|
|
break;
|
|
|
|
|
case state_go:
|
|
|
|
|
modbus_table_analog_out[1].all = 3;
|
|
|
|
|
modbus_table_analog_out[2].all = 1;
|
|
|
|
|
break;
|
|
|
|
|
case state_assemble:
|
|
|
|
|
modbus_table_analog_out[1].all = 4;
|
|
|
|
|
modbus_table_analog_out[2].all = 1;
|
|
|
|
|
break;
|
|
|
|
|
case state_fault:
|
|
|
|
|
modbus_table_analog_out[1].all = 5;
|
|
|
|
|
modbus_table_analog_out[2].all = 2;
|
|
|
|
|
break;
|
|
|
|
|
case state_accident:
|
|
|
|
|
modbus_table_analog_out[1].all = 6;
|
|
|
|
|
modbus_table_analog_out[2].all = 3;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
modbus_table_analog_out[1].all = 0;
|
|
|
|
|
modbus_table_analog_out[2].all = 0;
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
}
|
|
|
|
|
///////////////////////////////////////////////////
|
|
|
|
|
///
|
|
|
|
|
///////////////////////////////////////////////////
|
|
|
|
|
|
|
|
|
|
void setElementsColorsHMI(Inverter_state state) {
|
|
|
|
|
int i = 10;
|
|
|
|
|
if ((state == state_not_init) || (state == state_ready1)) {
|
|
|
|
|
//All grey
|
|
|
|
|
for (i = 10; i <= 22; ++i) {
|
|
|
|
|
modbus_table_analog_out[i].all = 0;
|
|
|
|
|
}
|
|
|
|
|
} else if (state == state_assemble) {
|
|
|
|
|
//UMP
|
|
|
|
|
for (i = 10; i <= 22; ++i) {
|
|
|
|
|
modbus_table_analog_out[i].all = 0;
|
|
|
|
|
}
|
|
|
|
|
modbus_table_analog_out[21].all = 1;
|
|
|
|
|
} else if (state == state_ready2) {
|
|
|
|
|
//All green
|
|
|
|
|
for (i = 10; i <= 22; ++i) {
|
|
|
|
|
modbus_table_analog_out[i].all = 0;
|
|
|
|
|
}
|
|
|
|
|
modbus_table_analog_out[10].all = 1;
|
|
|
|
|
modbus_table_analog_out[11].all = 1;
|
|
|
|
|
modbus_table_analog_out[12].all = 1;
|
|
|
|
|
} else if (state == state_go) {
|
|
|
|
|
//Almost all
|
|
|
|
|
for (i = 10; i <= 22; ++i) {
|
|
|
|
|
modbus_table_analog_out[i].all = 1;
|
|
|
|
|
}
|
|
|
|
|
modbus_table_analog_out[21].all = 0;
|
|
|
|
|
} else if (state == state_fault) {
|
|
|
|
|
for (i = 10; i <= 22; ++i) {
|
|
|
|
|
modbus_table_analog_out[i].all = 2;
|
|
|
|
|
}
|
|
|
|
|
} else if (state == state_accident) {
|
|
|
|
|
for (i = 10; i <= 22; ++i) {
|
|
|
|
|
modbus_table_analog_out[i].all = 3;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
///////////////////////////////////////////////////
|
|
|
|
|
///
|
|
|
|
|
///////////////////////////////////////////////////
|
|
|
|
|
|