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andrey
2025-06-26 21:04:59 +03:00
parent c5ea733074
commit a27b6bcb50
30 changed files with 26216 additions and 115 deletions
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38
john103C6T6/.mxproject
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52
john103C6T6/Core/Inc/can.h Normal file
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@@ -0,0 +1,52 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file can.h
* @brief This file contains all the function prototypes for
* the can.c file
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __CAN_H__
#define __CAN_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern CAN_HandleTypeDef hcan;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_CAN_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __CAN_H__ */

52
john103C6T6/Core/Inc/i2c.h Normal file
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@@ -0,0 +1,52 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file i2c.h
* @brief This file contains all the function prototypes for
* the i2c.c file
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __I2C_H__
#define __I2C_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern I2C_HandleTypeDef hi2c1;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_I2C1_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __I2C_H__ */

7
john103C6T6/Core/Inc/main.h
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@@ -63,6 +63,11 @@ typedef struct
/* USER CODE BEGIN ET */
#define reset_blink_delay 50
#define rest_iter 10
#define GPIOB11_valve MB_DATA.Coils.coils.state_val_bit.state_val_01
extern void handle_command(char* cmd);
typedef void (*FunctionPointer)(void);
@@ -91,8 +96,6 @@ void Error_Handler(void);
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define One_wire_Pin GPIO_PIN_1
#define One_wire_GPIO_Port GPIOA
/* USER CODE BEGIN Private defines */

4
john103C6T6/Core/Inc/ow_port.h
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@@ -23,14 +23,14 @@
* @brief Порт вывода для шины 1-Wire.
* @details Указывает порт GPIO, к которому подключена линия данных 1-Wire (например, для DS18B20).
*/
#define OW_GPIO_Port GPIOB
#define OW_GPIO_Port GPIOA
/**
* @def OW_Pin_Numb
* @brief Номер пина в порту OW_GPIO_Port.
* @details Используется для формирования маски пина и настройки ввода/вывода.
*/
#define OW_Pin_Numb 9
#define OW_Pin_Numb 15
/**
* @def OW_Pin

52
john103C6T6/Core/Inc/rtc.h Normal file
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@@ -0,0 +1,52 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file rtc.h
* @brief This file contains all the function prototypes for
* the rtc.c file
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __RTC_H__
#define __RTC_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern RTC_HandleTypeDef hrtc;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_RTC_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __RTC_H__ */

52
john103C6T6/Core/Inc/spi.h Normal file
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@@ -0,0 +1,52 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file spi.h
* @brief This file contains all the function prototypes for
* the spi.c file
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SPI_H__
#define __SPI_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern SPI_HandleTypeDef hspi1;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_SPI1_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __SPI_H__ */

8
john103C6T6/Core/Inc/stm32f1xx_hal_conf.h
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@@ -36,7 +36,7 @@
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
#define HAL_CAN_MODULE_ENABLED
/*#define HAL_CAN_LEGACY_MODULE_ENABLED */
/*#define HAL_CEC_MODULE_ENABLED */
/*#define HAL_CORTEX_MODULE_ENABLED */
@@ -46,7 +46,7 @@
/*#define HAL_ETH_MODULE_ENABLED */
/*#define HAL_FLASH_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
/*#define HAL_I2C_MODULE_ENABLED */
#define HAL_I2C_MODULE_ENABLED
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
@@ -57,12 +57,12 @@
/*#define HAL_HCD_MODULE_ENABLED */
/*#define HAL_PWR_MODULE_ENABLED */
/*#define HAL_RCC_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/*#define HAL_SD_MODULE_ENABLED */
/*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_SDRAM_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED
/*#define HAL_SRAM_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED

120
john103C6T6/Core/Src/can.c Normal file
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@@ -0,0 +1,120 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file can.c
* @brief This file provides code for the configuration
* of the CAN instances.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "can.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
CAN_HandleTypeDef hcan;
/* CAN init function */
void MX_CAN_Init(void)
{
/* USER CODE BEGIN CAN_Init 0 */
/* USER CODE END CAN_Init 0 */
/* USER CODE BEGIN CAN_Init 1 */
/* USER CODE END CAN_Init 1 */
hcan.Instance = CAN1;
hcan.Init.Prescaler = 16;
hcan.Init.Mode = CAN_MODE_NORMAL;
hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;
hcan.Init.TimeSeg1 = CAN_BS1_1TQ;
hcan.Init.TimeSeg2 = CAN_BS2_1TQ;
hcan.Init.TimeTriggeredMode = DISABLE;
hcan.Init.AutoBusOff = DISABLE;
hcan.Init.AutoWakeUp = DISABLE;
hcan.Init.AutoRetransmission = DISABLE;
hcan.Init.ReceiveFifoLocked = DISABLE;
hcan.Init.TransmitFifoPriority = DISABLE;
if (HAL_CAN_Init(&hcan) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN CAN_Init 2 */
/* USER CODE END CAN_Init 2 */
}
void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(canHandle->Instance==CAN1)
{
/* USER CODE BEGIN CAN1_MspInit 0 */
/* USER CODE END CAN1_MspInit 0 */
/* CAN1 clock enable */
__HAL_RCC_CAN1_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**CAN GPIO Configuration
PA11 ------> CAN_RX
PA12 ------> CAN_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN CAN1_MspInit 1 */
/* USER CODE END CAN1_MspInit 1 */
}
}
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle)
{
if(canHandle->Instance==CAN1)
{
/* USER CODE BEGIN CAN1_MspDeInit 0 */
/* USER CODE END CAN1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_CAN1_CLK_DISABLE();
/**CAN GPIO Configuration
PA11 ------> CAN_RX
PA12 ------> CAN_TX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
/* USER CODE BEGIN CAN1_MspDeInit 1 */
/* USER CODE END CAN1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

31
john103C6T6/Core/Src/gpio.c
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@@ -51,10 +51,7 @@ void MX_GPIO_Init(void)
__HAL_RCC_GPIOB_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, One_wire_Pin|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4
|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8
|GPIO_PIN_9|GPIO_PIN_10, GPIO_PIN_RESET);
@@ -63,32 +60,18 @@ void MX_GPIO_Init(void)
|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
|GPIO_PIN_15, GPIO_PIN_RESET);
/*Configure GPIO pin : PC13 */
GPIO_InitStruct.Pin = GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/*Configure GPIO pin : PA0 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = One_wire_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(One_wire_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : PA2 PA3 PA4 PA5
PA6 PA7 PA8 PA9
PA10 */
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5
|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9
|GPIO_PIN_10;
/*Configure GPIO pins : PA1 PA2 PA3 PA4
PA5 PA6 PA7 PA8
PA9 PA10 */
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4
|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8
|GPIO_PIN_9|GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;

117
john103C6T6/Core/Src/i2c.c Normal file
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@@ -0,0 +1,117 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file i2c.c
* @brief This file provides code for the configuration
* of the I2C instances.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "i2c.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
I2C_HandleTypeDef hi2c1;
/* I2C1 init function */
void MX_I2C1_Init(void)
{
/* USER CODE BEGIN I2C1_Init 0 */
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
hi2c1.Init.ClockSpeed = 100000;
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
hi2c1.Init.OwnAddress1 = 0;
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
hi2c1.Init.OwnAddress2 = 0;
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(i2cHandle->Instance==I2C1)
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
/**I2C1 GPIO Configuration
PB8 ------> I2C1_SCL
PB9 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
__HAL_AFIO_REMAP_I2C1_ENABLE();
/* I2C1 clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
}
}
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle)
{
if(i2cHandle->Instance==I2C1)
{
/* USER CODE BEGIN I2C1_MspDeInit 0 */
/* USER CODE END I2C1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_I2C1_CLK_DISABLE();
/**I2C1 GPIO Configuration
PB8 ------> I2C1_SCL
PB9 ------> I2C1_SDA
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9);
/* USER CODE BEGIN I2C1_MspDeInit 1 */
/* USER CODE END I2C1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

27
john103C6T6/Core/Src/main.c
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@@ -19,6 +19,10 @@
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "adc.h"
#include "can.h"
#include "i2c.h"
#include "rtc.h"
#include "spi.h"
#include "tim.h"
#include "usart.h"
#include "gpio.h"
@@ -118,7 +122,11 @@ int main(void)
MX_USART1_UART_Init();
MX_TIM2_Init();
MX_ADC1_Init();
/* USER CODE BEGIN 2 */
MX_CAN_Init();
MX_I2C1_Init();
MX_RTC_Init();
MX_SPI1_Init();
/* USER CODE BEGIN 2 */
led_blink(GPIOC,13,rest_iter,reset_blink_delay);
MODBUS_FirstInit();
@@ -189,8 +197,17 @@ int main(void)
{
MB_DATA.Coils.coils.all&=~(1<<i);
}
if(GPIOB11_valve)
{
GPIOB->ODR|=1<<11;
}
else
{
GPIOB->ODR&=~(1<<11);
}
}
@@ -219,10 +236,11 @@ void SystemClock_Config(void)
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
@@ -244,7 +262,8 @@ void SystemClock_Config(void)
{
Error_Handler();
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC;
PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{

130
john103C6T6/Core/Src/rtc.c Normal file
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@@ -0,0 +1,130 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file rtc.c
* @brief This file provides code for the configuration
* of the RTC instances.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "rtc.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
RTC_HandleTypeDef hrtc;
/* RTC init function */
void MX_RTC_Init(void)
{
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
RTC_TimeTypeDef sTime = {0};
RTC_DateTypeDef DateToUpdate = {0};
RTC_TamperTypeDef sTamper = {0};
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/** Initialize RTC Only
*/
hrtc.Instance = RTC;
hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
hrtc.Init.OutPut = RTC_OUTPUTSOURCE_NONE;
if (HAL_RTC_Init(&hrtc) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN Check_RTC_BKUP */
/* USER CODE END Check_RTC_BKUP */
/** Initialize RTC and set the Time and Date
*/
sTime.Hours = 0x0;
sTime.Minutes = 0x0;
sTime.Seconds = 0x0;
if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK)
{
Error_Handler();
}
DateToUpdate.WeekDay = RTC_WEEKDAY_MONDAY;
DateToUpdate.Month = RTC_MONTH_JANUARY;
DateToUpdate.Date = 0x1;
DateToUpdate.Year = 0x0;
if (HAL_RTC_SetDate(&hrtc, &DateToUpdate, RTC_FORMAT_BCD) != HAL_OK)
{
Error_Handler();
}
/** Enable the RTC Tamper
*/
sTamper.Tamper = RTC_TAMPER_1;
sTamper.Trigger = RTC_TAMPERTRIGGER_LOWLEVEL;
if (HAL_RTCEx_SetTamper(&hrtc, &sTamper) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle)
{
if(rtcHandle->Instance==RTC)
{
/* USER CODE BEGIN RTC_MspInit 0 */
/* USER CODE END RTC_MspInit 0 */
HAL_PWR_EnableBkUpAccess();
/* Enable BKP CLK enable for backup registers */
__HAL_RCC_BKP_CLK_ENABLE();
/* RTC clock enable */
__HAL_RCC_RTC_ENABLE();
/* USER CODE BEGIN RTC_MspInit 1 */
/* USER CODE END RTC_MspInit 1 */
}
}
void HAL_RTC_MspDeInit(RTC_HandleTypeDef* rtcHandle)
{
if(rtcHandle->Instance==RTC)
{
/* USER CODE BEGIN RTC_MspDeInit 0 */
/* USER CODE END RTC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_RTC_DISABLE();
/* USER CODE BEGIN RTC_MspDeInit 1 */
/* USER CODE END RTC_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

124
john103C6T6/Core/Src/spi.c Normal file
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@@ -0,0 +1,124 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file spi.c
* @brief This file provides code for the configuration
* of the SPI instances.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "spi.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
SPI_HandleTypeDef hspi1;
/* SPI1 init function */
void MX_SPI1_Init(void)
{
/* USER CODE BEGIN SPI1_Init 0 */
/* USER CODE END SPI1_Init 0 */
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
hspi1.Instance = SPI1;
hspi1.Init.Mode = SPI_MODE_MASTER;
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi1.Init.NSS = SPI_NSS_SOFT;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi1.Init.CRCPolynomial = 10;
if (HAL_SPI_Init(&hspi1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(spiHandle->Instance==SPI1)
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* SPI1 clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**SPI1 GPIO Configuration
PB3 ------> SPI1_SCK
PB4 ------> SPI1_MISO
PB5 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_4;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
__HAL_AFIO_REMAP_SPI1_ENABLE();
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
}
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
{
if(spiHandle->Instance==SPI1)
{
/* USER CODE BEGIN SPI1_MspDeInit 0 */
/* USER CODE END SPI1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SPI1_CLK_DISABLE();
/**SPI1 GPIO Configuration
PB3 ------> SPI1_SCK
PB4 ------> SPI1_MISO
PB5 ------> SPI1_MOSI
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5);
/* USER CODE BEGIN SPI1_MspDeInit 1 */
/* USER CODE END SPI1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_can.h
* @author MCD Application Team
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_CAN_H
#define STM32F1xx_HAL_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#if defined (CAN1)
/** @addtogroup CAN
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CAN_Exported_Types CAN Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */
HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */
HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */
HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */
} HAL_CAN_StateTypeDef;
/**
* @brief CAN init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
uint32_t Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of @ref CAN_operating_mode */
uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
is allowed to lengthen or shorten a bit to perform resynchronization.
This parameter can be a value of @ref CAN_synchronisation_jump_width */
uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
This parameter can be set to ENABLE or DISABLE. */
} CAN_InitTypeDef;
/**
* @brief CAN filter configuration structure definition
*/
typedef struct
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter must be a number between
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
For single CAN instance(14 dedicated filter banks),
this parameter must be a number between Min_Data = 0 and Max_Data = 13.
For dual CAN instances(28 filter banks shared),
this parameter must be a number between Min_Data = 0 and Max_Data = 27. */
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint32_t FilterScale; /*!< Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be a value of @ref CAN_filter_activation */
uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
For single CAN instances, this parameter is meaningless.
For dual CAN instances, all filter banks with lower index are assigned to master
CAN instance, whereas all filter banks with greater index are assigned to slave
CAN instance.
This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
} CAN_FilterTypeDef;
/**
* @brief CAN Tx message header structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
@note: Time Triggered Communication Mode must be enabled.
@note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
This parameter can be set to ENABLE or DISABLE. */
} CAN_TxHeaderTypeDef;
/**
* @brief CAN Rx message header structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
@note: Time Triggered Communication Mode must be enabled.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
} CAN_RxHeaderTypeDef;
/**
* @brief CAN handle Structure definition
*/
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
typedef struct __CAN_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
{
CAN_TypeDef *Instance; /*!< Register base address */
CAN_InitTypeDef Init; /*!< CAN required parameters */
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
__IO uint32_t ErrorCode; /*!< CAN Error code.
This parameter can be a value of @ref CAN_Error_Code */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */
void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */
void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */
void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */
void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */
void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */
void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */
void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */
void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */
void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */
void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */
void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */
void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */
void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */
void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
} CAN_HandleTypeDef;
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/**
* @brief HAL CAN common Callback ID enumeration definition
*/
typedef enum
{
HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */
HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */
HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */
HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */
HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */
HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */
HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */
HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */
} HAL_CAN_CallbackIDTypeDef;
/**
* @brief HAL CAN Callback pointer definition
*/
typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
/**
* @}
*/
/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
/**
* @}
*/
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with
silent mode */
/**
* @}
*/
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{
*/
#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{
*/
#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
* @{
*/
#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
/**
* @}
*/
/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */
/**
* @}
*/
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */
/**
* @}
*/
/** @defgroup CAN_filter_activation CAN Filter Activation
* @{
*/
#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */
#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */
/**
* @}
*/
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
/** @defgroup CAN_identifier_type CAN Identifier Type
* @{
*/
#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
/**
* @}
*/
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
/**
* @}
*/
/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
* @{
*/
#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
/**
* @}
*/
/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
* @{
*/
#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
/**
* @}
*/
/** @defgroup CAN_flags CAN Flags
* @{
*/
/* Transmit Flags */
#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */
#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */
#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */
#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */
#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */
#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */
#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */
#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */
#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */
#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */
#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */
#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */
#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */
#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */
#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */
#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */
#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */
/* Receive Flags */
#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */
#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */
#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */
#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */
/* Operating Mode Flags */
#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */
#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */
/* Error Flags */
#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
/**
* @}
*/
/** @defgroup CAN_Interrupts CAN Interrupts
* @{
*/
/* Transmit Interrupt */
#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
/* Operating Mode Interrupts */
#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
/* Error Interrupts */
#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CAN_Exported_Macros CAN Exported Macros
* @{
*/
/** @brief Reset CAN handle state
* @param __HANDLE__ CAN handle.
* @retval None
*/
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_CAN_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @brief Enable the specified CAN interrupts.
* @param __HANDLE__ CAN handle.
* @param __INTERRUPT__ CAN Interrupt sources to enable.
* This parameter can be any combination of @arg CAN_Interrupts
* @retval None
*/
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable the specified CAN interrupts.
* @param __HANDLE__ CAN handle.
* @param __INTERRUPT__ CAN Interrupt sources to disable.
* This parameter can be any combination of @arg CAN_Interrupts
* @retval None
*/
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the CAN Handle.
* @param __INTERRUPT__ specifies the CAN interrupt source to check.
* This parameter can be a value of @arg CAN_Interrupts
* @retval The state of __IT__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
/** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__ specifies the CAN Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of @arg CAN_flags
* @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/** @brief Clear the specified CAN pending flag.
* @param __HANDLE__ specifies the CAN Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
* @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
* @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
* @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
* @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
* @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
* @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
* @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
* @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
* @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag
* @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag
* @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag
* @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag
* @arg CAN_FLAG_WKUI: Wake up Interrupt Flag
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
* @retval None
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID,
void (* pCallback)(CAN_HandleTypeDef *_hcan));
HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group3 Control functions
* @brief Control functions
* @{
*/
/* Control functions **********************************************************/
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
const uint8_t aData[], uint32_t *pTxMailbox);
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan);
uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
* @brief Interrupts management
* @{
*/
/* Interrupts management ******************************************************/
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
* @brief Callback functions
* @{
*/
/* Callbacks functions ********************************************************/
void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
* @brief CAN Peripheral State functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan);
uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CAN_Private_Types CAN Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CAN_Private_Variables CAN Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
#define CAN_FLAG_MASK (0x000000FFU)
/**
* @}
*/
/* Private Macros -----------------------------------------------------------*/
/** @defgroup CAN_Private_Macros CAN Private Macros
* @{
*/
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
((MODE) == CAN_MODE_LOOPBACK)|| \
((MODE) == CAN_MODE_SILENT) || \
((MODE) == CAN_MODE_SILENT_LOOPBACK))
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
#if defined(CAN2)
#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
#endif
#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT))
#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
((ACTIVATION) == CAN_FILTER_ENABLE))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \
CAN_TX_MAILBOX2))
#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \
CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \
CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \
CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \
CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \
CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \
CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR))
/**
* @}
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
#endif /* CAN1 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_CAN_H */

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john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h Normal file
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@@ -0,0 +1,738 @@
/**
******************************************************************************
* @file stm32f1xx_hal_i2c.h
* @author MCD Application Team
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_I2C_H
#define __STM32F1xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t ClockSpeed; /*!< Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */
uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_addressing_mode */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_dual_addressing_mode */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_general_call_addressing_mode */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_nostretch_mode */
} I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : Abort (Abort user request on going)
* 10 : Timeout
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
* b4 (not used)
* x : Should be set to 0
* b3
* 0 : Ready or Busy (No Listen mode ongoing)
* 1 : Listen (Peripheral in Address Listen Mode)
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
} HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */
#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
typedef struct __I2C_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint32_t XferOptions; /*!< I2C transfer options */
__IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
context for internal usage */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t Devaddress; /*!< I2C Target device address */
__IO uint32_t Memaddress; /*!< I2C Target memory address */
__IO uint32_t MemaddSize; /*!< I2C Target memory address size */
__IO uint32_t EventCount; /*!< I2C Event counter */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
} HAL_I2C_CallbackIDTypeDef;
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
* @{
*/
#define I2C_DUTYCYCLE_2 0x00000000U
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
/**
* @}
*/
/** @defgroup I2C_addressing_mode I2C addressing mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT 0x00004000U
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
/**
* @}
*/
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE 0x00000000U
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
/**
* @}
*/
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
* @{
*/
#define I2C_GENERALCALL_DISABLE 0x00000000U
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
/**
* @}
*/
/** @defgroup I2C_nostretch_mode I2C nostretch mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE 0x00000000U
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT 0x00000001U
#define I2C_MEMADD_SIZE_16BIT 0x00000010U
/**
* @}
*/
/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
* @{
*/
#define I2C_DIRECTION_RECEIVE 0x00000000U
#define I2C_DIRECTION_TRANSMIT 0x00000001U
/**
* @}
*/
/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
* @{
*/
#define I2C_FIRST_FRAME 0x00000001U
#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U
#define I2C_NEXT_FRAME 0x00000004U
#define I2C_FIRST_AND_LAST_FRAME 0x00000008U
#define I2C_LAST_FRAME_NO_STOP 0x00000010U
#define I2C_LAST_FRAME 0x00000020U
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x00AA0000U)
#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U)
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_BUF I2C_CR2_ITBUFEN
#define I2C_IT_EVT I2C_CR2_ITEVTEN
#define I2C_IT_ERR I2C_CR2_ITERREN
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_OVR 0x00010800U
#define I2C_FLAG_AF 0x00010400U
#define I2C_FLAG_ARLO 0x00010200U
#define I2C_FLAG_BERR 0x00010100U
#define I2C_FLAG_TXE 0x00010080U
#define I2C_FLAG_RXNE 0x00010040U
#define I2C_FLAG_STOPF 0x00010010U
#define I2C_FLAG_ADD10 0x00010008U
#define I2C_FLAG_BTF 0x00010004U
#define I2C_FLAG_ADDR 0x00010002U
#define I2C_FLAG_SB 0x00010001U
#define I2C_FLAG_DUALF 0x00100080U
#define I2C_FLAG_GENCALL 0x00100010U
#define I2C_FLAG_TRA 0x00100004U
#define I2C_FLAG_BUSY 0x00100002U
#define I2C_FLAG_MSL 0x00100001U
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif
/** @brief Enable or disable the specified I2C interrupts.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2C_IT_BUF: Buffer interrupt enable
* @arg I2C_IT_EVT: Event interrupt enable
* @arg I2C_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg I2C_IT_BUF: Buffer interrupt enable
* @arg I2C_IT_EVT: Event interrupt enable
* @arg I2C_IT_ERR: Error interrupt enable
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2C_FLAG_OVR: Overrun/Underrun flag
* @arg I2C_FLAG_AF: Acknowledge failure flag
* @arg I2C_FLAG_ARLO: Arbitration lost flag
* @arg I2C_FLAG_BERR: Bus error flag
* @arg I2C_FLAG_TXE: Data register empty flag
* @arg I2C_FLAG_RXNE: Data register not empty flag
* @arg I2C_FLAG_STOPF: Stop detection flag
* @arg I2C_FLAG_ADD10: 10-bit header sent flag
* @arg I2C_FLAG_BTF: Byte transfer finished flag
* @arg I2C_FLAG_ADDR: Address sent flag
* Address matched flag
* @arg I2C_FLAG_SB: Start bit flag
* @arg I2C_FLAG_DUALF: Dual flag
* @arg I2C_FLAG_GENCALL: General call header flag
* @arg I2C_FLAG_TRA: Transmitter/Receiver flag
* @arg I2C_FLAG_BUSY: Bus busy flag
* @arg I2C_FLAG_MSL: Master/Slave flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \
(((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \
(((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
* @arg I2C_FLAG_AF: Acknowledge failure flag
* @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
* @arg I2C_FLAG_BERR: Bus error flag
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
/** @brief Clears the I2C ADDR pending flag.
* @param __HANDLE__ specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR1; \
tmpreg = (__HANDLE__)->Instance->SR2; \
UNUSED(tmpreg); \
} while(0)
/** @brief Clears the I2C STOPF pending flag.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR1; \
SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \
UNUSED(tmpreg); \
} while(0)
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
#define I2C_FLAG_MASK 0x0000FFFFU
#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */
#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macros I2C Private Macros
* @{
*/
#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
* @{
*/
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
((CYCLE) == I2C_DUTYCYCLE_16_9))
#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_I2C_H */

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/**
******************************************************************************
* @file stm32f1xx_hal_rtc.h
* @author MCD Application Team
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_RTC_H
#define __STM32F1xx_HAL_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup RTC
* @{
*/
/** @addtogroup RTC_Private_Macros
* @{
*/
#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \
((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \
((__OUTPUT__) == RTC_OUTPUTSOURCE_ALARM) || \
((__OUTPUT__) == RTC_OUTPUTSOURCE_SECOND))
/**
* @}
*/
/** @addtogroup RTC_Private_Constants
* @{
*/
/** @defgroup RTC_Timeout_Value Default Timeout Value
* @{
*/
#define RTC_TIMEOUT_VALUE 1000U
/**
* @}
*/
/** @defgroup RTC_EXTI_Line_Event RTC EXTI Line event
* @{
*/
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
/**
* @}
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint8_t Hours; /*!< Specifies the RTC Time Hour.
This parameter must be a number between Min_Data = 0 and Max_Data = 23 */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
} RTC_TimeTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
uint32_t Alarm; /*!< Specifies the alarm ID (only 1 alarm ID for STM32F1).
This parameter can be a value of @ref RTC_Alarms_Definitions */
} RTC_AlarmTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
} HAL_RTCStateTypeDef;
/**
* @brief RTC Configuration Structure definition
*/
typedef struct
{
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF or RTC_AUTO_1_SECOND
If RTC_AUTO_1_SECOND is selected, AsynchPrediv will be set automatically to get 1sec timebase */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC Tamper pin.
This parameter can be a value of @ref RTC_output_source_to_output_on_the_Tamper_pin */
} RTC_InitTypeDef;
/**
* @brief RTC Date structure definition
*/
typedef struct
{
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay (not necessary for HAL_RTC_SetDate).
This parameter can be a value of @ref RTC_WeekDay_Definitions */
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
This parameter can be a value of @ref RTC_Month_Date_Definitions */
uint8_t Date; /*!< Specifies the RTC Date.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
uint8_t Year; /*!< Specifies the RTC Date Year.
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
} RTC_DateTypeDef;
/**
* @brief Time Handle Structure definition
*/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
typedef struct __RTC_HandleTypeDef
#else
typedef struct
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
{
RTC_TypeDef *Instance; /*!< Register base address */
RTC_InitTypeDef Init; /*!< RTC required parameters */
RTC_DateTypeDef DateToUpdate; /*!< Current date set by user and updated automatically */
HAL_LockTypeDef Lock; /*!< RTC locking object */
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
} RTC_HandleTypeDef;
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL RTC Callback ID enumeration definition
*/
typedef enum
{
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */
HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */
HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */
} HAL_RTC_CallbackIDTypeDef;
/**
* @brief HAL RTC Callback pointer definition
*/
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
/** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase
* @{
*/
#define RTC_AUTO_1_SECOND 0xFFFFFFFFU
/**
* @}
*/
/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
* @{
*/
#define RTC_FORMAT_BIN 0x000000000U
#define RTC_FORMAT_BCD 0x000000001U
/**
* @}
*/
/** @defgroup RTC_Month_Date_Definitions Month Definitions
* @{
*/
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define RTC_MONTH_MARCH ((uint8_t)0x03)
#define RTC_MONTH_APRIL ((uint8_t)0x04)
#define RTC_MONTH_MAY ((uint8_t)0x05)
#define RTC_MONTH_JUNE ((uint8_t)0x06)
#define RTC_MONTH_JULY ((uint8_t)0x07)
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
/**
* @}
*/
/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions
* @{
*/
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup RTC_Alarms_Definitions Alarms Definitions
* @{
*/
#define RTC_ALARM_A 0U /*!< Specify alarm ID (mainly for legacy purposes) */
/**
* @}
*/
/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin Output source to output on the Tamper pin
* @{
*/
#define RTC_OUTPUTSOURCE_NONE 0x00000000U /*!< No output on the TAMPER pin */
#define RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO /*!< RTC clock with a frequency divided by 64 on the TAMPER pin */
#define RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE /*!< Alarm pulse signal on the TAMPER pin */
#define RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin */
/**
* @}
*/
/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions
* @{
*/
#define RTC_IT_OW RTC_CRH_OWIE /*!< Overflow interrupt */
#define RTC_IT_ALRA RTC_CRH_ALRIE /*!< Alarm interrupt */
#define RTC_IT_SEC RTC_CRH_SECIE /*!< Second interrupt */
#define RTC_IT_TAMP1 BKP_CSR_TPIE /*!< TAMPER Pin interrupt enable */
/**
* @}
*/
/** @defgroup RTC_Flags_Definitions Flags Definitions
* @{
*/
#define RTC_FLAG_RTOFF RTC_CRL_RTOFF /*!< RTC Operation OFF flag */
#define RTC_FLAG_RSF RTC_CRL_RSF /*!< Registers Synchronized flag */
#define RTC_FLAG_OW RTC_CRL_OWF /*!< Overflow flag */
#define RTC_FLAG_ALRAF RTC_CRL_ALRF /*!< Alarm flag */
#define RTC_FLAG_SEC RTC_CRL_SECF /*!< Second flag */
#define RTC_FLAG_TAMP1F BKP_CSR_TEF /*!< Tamper Interrupt Flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RTC_Exported_macros RTC Exported Macros
* @{
*/
/** @brief Reset RTC handle state
* @param __HANDLE__: RTC handle.
* @retval None
*/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
(__HANDLE__)->State = HAL_RTC_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL;\
(__HANDLE__)->MspDeInitCallback = NULL;\
}while(0u)
#else
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @brief Disable the write protection for RTC registers.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
/**
* @brief Enable the write protection for RTC registers.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
/**
* @brief Enable the RTC Alarm interrupt.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
/**
* @brief Disable the RTC Alarm interrupt.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be checked
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
/**
* @brief Get the selected RTC Alarm's flag status.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @retval None
*/
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
/**
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET)
/**
* @brief Clear the RTC Alarm's pending flags.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @retval None
*/
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) &= ~(__FLAG__)
/**
* @brief Enable interrupt on ALARM Exti Line 17.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable interrupt on ALARM Exti Line 17.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Enable event on ALARM Exti Line 17.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable event on ALARM Exti Line 17.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief ALARM EXTI line configuration: set falling edge trigger.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable the ALARM Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief ALARM EXTI line configuration: set rising edge trigger.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable the ALARM Extended Interrupt Rising Trigger.
* This parameter can be:
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief ALARM EXTI line configuration: set rising & falling edge trigger.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() \
do{ \
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
} while(0U)
/**
* @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger.
* This parameter can be:
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() \
do{ \
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
} while(0U)
/**
* @brief Check whether the specified ALARM EXTI interrupt flag is set or not.
* @retval EXTI ALARM Line Status.
*/
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Clear the ALARM EXTI flag.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT)
/**
* @}
*/
/* Include RTC HAL Extension module */
#include "stm32f1xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RTC_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/** @addtogroup RTC_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @}
*/
/* RTC Time and Date functions ************************************************/
/** @addtogroup RTC_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
/**
* @}
*/
/* RTC Alarm functions ********************************************************/
/** @addtogroup RTC_Exported_Functions_Group3
* @{
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/* Peripheral State functions *************************************************/
/** @addtogroup RTC_Exported_Functions_Group4
* @{
*/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/* Peripheral Control functions ***********************************************/
/** @addtogroup RTC_Exported_Functions_Group5
* @{
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_RTC_H */

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/**
******************************************************************************
* @file stm32f1xx_hal_rtc_ex.h
* @author MCD Application Team
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_RTC_EX_H
#define __STM32F1xx_HAL_RTC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup RTCEx
* @{
*/
/** @addtogroup RTCEx_Private_Macros
* @{
*/
/** @defgroup RTCEx_Alias_For_Legacy Alias define maintained for legacy
* @{
*/
#define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler
/**
* @}
*/
/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
* @{
*/
#define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1)
#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
#if RTC_BKP_NUMBER > 10U
#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t)RTC_BKP_DR10) || (((BKP) >= (uint32_t)RTC_BKP_DR11) && ((BKP) <= (uint32_t)RTC_BKP_DR42)))
#else
#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t)RTC_BKP_NUMBER)
#endif
#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU)
/**
* @}
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
* @{
*/
/**
* @brief RTC Tamper structure definition
*/
typedef struct
{
uint32_t Tamper; /*!< Specifies the Tamper Pin.
This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
} RTC_TamperTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
* @{
*/
/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions
* @{
*/
#define RTC_TAMPER_1 BKP_CR_TPE /*!< Select tamper to be enabled (mainly for legacy purposes) */
/**
* @}
*/
/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions
* @{
*/
#define RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
/**
* @}
*/
/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions
* @{
*/
#if RTC_BKP_NUMBER > 0U
#define RTC_BKP_DR1 0x00000001U
#define RTC_BKP_DR2 0x00000002U
#define RTC_BKP_DR3 0x00000003U
#define RTC_BKP_DR4 0x00000004U
#define RTC_BKP_DR5 0x00000005U
#define RTC_BKP_DR6 0x00000006U
#define RTC_BKP_DR7 0x00000007U
#define RTC_BKP_DR8 0x00000008U
#define RTC_BKP_DR9 0x00000009U
#define RTC_BKP_DR10 0x0000000AU
#endif /* RTC_BKP_NUMBER > 0 */
#if RTC_BKP_NUMBER > 10U
#define RTC_BKP_DR11 0x00000010U
#define RTC_BKP_DR12 0x00000011U
#define RTC_BKP_DR13 0x00000012U
#define RTC_BKP_DR14 0x00000013U
#define RTC_BKP_DR15 0x00000014U
#define RTC_BKP_DR16 0x00000015U
#define RTC_BKP_DR17 0x00000016U
#define RTC_BKP_DR18 0x00000017U
#define RTC_BKP_DR19 0x00000018U
#define RTC_BKP_DR20 0x00000019U
#define RTC_BKP_DR21 0x0000001AU
#define RTC_BKP_DR22 0x0000001BU
#define RTC_BKP_DR23 0x0000001CU
#define RTC_BKP_DR24 0x0000001DU
#define RTC_BKP_DR25 0x0000001EU
#define RTC_BKP_DR26 0x0000001FU
#define RTC_BKP_DR27 0x00000020U
#define RTC_BKP_DR28 0x00000021U
#define RTC_BKP_DR29 0x00000022U
#define RTC_BKP_DR30 0x00000023U
#define RTC_BKP_DR31 0x00000024U
#define RTC_BKP_DR32 0x00000025U
#define RTC_BKP_DR33 0x00000026U
#define RTC_BKP_DR34 0x00000027U
#define RTC_BKP_DR35 0x00000028U
#define RTC_BKP_DR36 0x00000029U
#define RTC_BKP_DR37 0x0000002AU
#define RTC_BKP_DR38 0x0000002BU
#define RTC_BKP_DR39 0x0000002CU
#define RTC_BKP_DR40 0x0000002DU
#define RTC_BKP_DR41 0x0000002EU
#define RTC_BKP_DR42 0x0000002FU
#endif /* RTC_BKP_NUMBER > 10 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
* @{
*/
/**
* @brief Enable the RTC Tamper interrupt.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled
* This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP1: Tamper A interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__))
/**
* @brief Disable the RTC Tamper interrupt.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP1: Tamper A interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(BKP->CSR, (__INTERRUPT__))
/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
* This parameter can be:
* @arg RTC_IT_TAMP1
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET)
/**
* @brief Get the selected RTC Tamper's flag status.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_TAMP1F
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET)
/**
* @brief Get the selected RTC Tamper's flag status.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
* This parameter can be:
* @arg RTC_IT_TAMP1
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET)
/**
* @brief Clear the RTC Tamper's pending flags.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_TAMP1F
* @retval None
*/
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI)
/**
* @brief Enable the RTC Second interrupt.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled
* This parameter can be any combination of the following values:
* @arg RTC_IT_SEC: Second A interrupt
* @retval None
*/
#define __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
/**
* @brief Disable the RTC Second interrupt.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Second interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_SEC: Second A interrupt
* @retval None
*/
#define __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
/**
* @brief Check whether the specified RTC Second interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_SEC: Second A interrupt
* @retval None
*/
#define __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
/**
* @brief Get the selected RTC Second's flag status.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_SEC
* @retval None
*/
#define __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
/**
* @brief Clear the RTC Second's pending flags.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_SEC
* @retval None
*/
#define __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) &= ~(__FLAG__)
/**
* @brief Enable the RTC Overflow interrupt.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled
* This parameter can be any combination of the following values:
* @arg RTC_IT_OW: Overflow A interrupt
* @retval None
*/
#define __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
/**
* @brief Disable the RTC Overflow interrupt.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_OW: Overflow A interrupt
* @retval None
*/
#define __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
/**
* @brief Check whether the specified RTC Overflow interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_OW: Overflow A interrupt
* @retval None
*/
#define __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET)
/**
* @brief Get the selected RTC Overflow's flag status.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_OW
* @retval None
*/
#define __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
/**
* @brief Clear the RTC Overflow's pending flags.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_OW
* @retval None
*/
#define __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RTCEx_Exported_Functions
* @{
*/
/* RTC Tamper functions *****************************************/
/** @addtogroup RTCEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
/**
* @}
*/
/* RTC Second functions *****************************************/
/** @addtogroup RTCEx_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/* Extension Control functions ************************************************/
/** @addtogroup RTCEx_Exported_Functions_Group3
* @{
*/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_RTC_EX_H */

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john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h Normal file
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@@ -0,0 +1,734 @@
/**
******************************************************************************
* @file stm32f1xx_hal_spi.h
* @author MCD Application Team
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_SPI_H
#define STM32F1xx_HAL_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SPI_Exported_Types SPI Exported Types
* @{
*/
/**
* @brief SPI Configuration Structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_Mode */
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
This parameter can be a value of @ref SPI_Direction */
uint32_t DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_Data_Size */
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
This parameter can be a value of @ref SPI_TI_mode */
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_CRC_Calculation */
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
} SPI_InitTypeDef;
/**
* @brief HAL SPI State structure definition
*/
typedef enum
{
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
} HAL_SPI_StateTypeDef;
/**
* @brief SPI handle Structure definition
*/
typedef struct __SPI_HandleTypeDef
{
SPI_TypeDef *Instance; /*!< SPI registers base address */
SPI_InitTypeDef Init; /*!< SPI communication parameters */
const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
__IO uint32_t ErrorCode; /*!< SPI Error code */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
} SPI_HandleTypeDef;
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
/**
* @brief HAL SPI Callback ID enumeration definition
*/
typedef enum
{
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
} HAL_SPI_CallbackIDTypeDef;
/**
* @brief HAL SPI Callback pointer definition
*/
typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_Exported_Constants SPI Exported Constants
* @{
*/
/** @defgroup SPI_Error_Code SPI Error Code
* @{
*/
#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SPI_Mode SPI Mode
* @{
*/
#define SPI_MODE_SLAVE (0x00000000U)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
/**
* @}
*/
/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
#define SPI_DIRECTION_2LINES (0x00000000U)
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
/**
* @}
*/
/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
#define SPI_DATASIZE_8BIT (0x00000000U)
#define SPI_DATASIZE_16BIT SPI_CR1_DFF
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
#define SPI_POLARITY_LOW (0x00000000U)
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
/**
* @}
*/
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
#define SPI_PHASE_1EDGE (0x00000000U)
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
/**
* @}
*/
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
#define SPI_NSS_HARD_INPUT (0x00000000U)
#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
* @{
*/
#define SPI_FIRSTBIT_MSB (0x00000000U)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
/**
* @}
*/
/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
#define SPI_TIMODE_DISABLE (0x00000000U)
/**
* @}
*/
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}
*/
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
* @{
*/
#define SPI_IT_TXE SPI_CR2_TXEIE
#define SPI_IT_RXNE SPI_CR2_RXNEIE
#define SPI_IT_ERR SPI_CR2_ERRIE
/**
* @}
*/
/** @defgroup SPI_Flags_definition SPI Flags Definition
* @{
*/
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY\
| SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SPI_Exported_Macros SPI Exported Macros
* @{
*/
/** @brief Reset SPI handle state.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
do{ \
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Disable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI handle.
* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Check whether the specified SPI interrupt source is enabled or not.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SPI flag is set or not.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
* @arg SPI_FLAG_CRCERR: CRC error flag
* @arg SPI_FLAG_MODF: Mode fault flag
* @arg SPI_FLAG_OVR: Overrun flag
* @arg SPI_FLAG_BSY: Busy flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the SPI CRCERR pending flag.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
/** @brief Clear the SPI MODF pending flag.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg_modf = 0x00U; \
tmpreg_modf = (__HANDLE__)->Instance->SR; \
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
UNUSED(tmpreg_modf); \
} while(0U)
/** @brief Clear the SPI OVR pending flag.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg_ovr = 0x00U; \
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_ovr); \
} while(0U)
/** @brief Enable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/** @brief Disable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SPI_Private_Constants SPI Private Constants
* @{
*/
#define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */
#define SPI_VALID_CRC_ERROR 1U /* CRC error is true */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
/** @brief Set the SPI transmit-only mode.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Set the SPI receive-only mode.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Reset the CRC calculation of the SPI.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_RESET_CRC(__HANDLE__) \
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
} while(0U)
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of SPI SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
* @arg SPI_FLAG_CRCERR: CRC error flag
* @arg SPI_FLAG_MODF: Mode fault flag
* @arg SPI_FLAG_OVR: Overrun flag
* @arg SPI_FLAG_BSY: Busy flag
* @retval SET or RESET.
*/
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of SPI CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
(__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if SPI Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Mode.
* This parameter can be a value of @ref SPI_Mode
* @retval None
*/
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
((__MODE__) == SPI_MODE_MASTER))
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Direction Mode.
* This parameter can be a value of @ref SPI_Direction
* @retval None
*/
#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
((__MODE__) == SPI_DIRECTION_1LINE))
/** @brief Checks if SPI Direction Mode parameter is 2 lines.
* @param __MODE__ specifies the SPI Direction Mode.
* @retval None
*/
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
* @param __MODE__ specifies the SPI Direction Mode.
* @retval None
*/
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
((__MODE__) == SPI_DIRECTION_1LINE))
/** @brief Checks if SPI Data Size parameter is in allowed range.
* @param __DATASIZE__ specifies the SPI Data Size.
* This parameter can be a value of @ref SPI_Data_Size
* @retval None
*/
#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
((__DATASIZE__) == SPI_DATASIZE_8BIT))
/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
* @param __CPOL__ specifies the SPI serial clock steady state.
* This parameter can be a value of @ref SPI_Clock_Polarity
* @retval None
*/
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
((__CPOL__) == SPI_POLARITY_HIGH))
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
* @param __CPHA__ specifies the SPI Clock Phase.
* This parameter can be a value of @ref SPI_Clock_Phase
* @retval None
*/
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
((__CPHA__) == SPI_PHASE_2EDGE))
/** @brief Checks if SPI Slave Select parameter is in allowed range.
* @param __NSS__ specifies the SPI Slave Select management parameter.
* This parameter can be a value of @ref SPI_Slave_Select_management
* @retval None
*/
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
((__NSS__) == SPI_NSS_HARD_INPUT) || \
((__NSS__) == SPI_NSS_HARD_OUTPUT))
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
* This parameter can be a value of @ref SPI_BaudRate_Prescaler
* @retval None
*/
#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
* @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
* @retval None
*/
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
((__BIT__) == SPI_FIRSTBIT_LSB))
/** @brief Checks if SPI TI mode parameter is disabled.
* @param __MODE__ SPI_TIMODE_DISABLE. Device not support Ti Mode.
* This parameter can be a value of @ref SPI_TI_mode
* @retval None
*/
#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE)
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
* This parameter can be a value of @ref SPI_CRC_Calculation
* @retval None
*/
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
* @retval None
*/
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
((__POLYNOMIAL__) <= 0xFFFFU) && \
(((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle.
* @retval None
*/
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SPI_Private_Functions SPI Private Functions
* @{
*/
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPI_Exported_Functions
* @{
*/
/** @addtogroup SPI_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
pSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_SPI_H */

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@@ -0,0 +1,1782 @@
/**
******************************************************************************
* @file stm32f1xx_ll_i2c.h
* @author MCD Application Team
* @brief Header file of I2C LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_I2C_H
#define __STM32F1xx_LL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (I2C1) || defined (I2C2)
/** @defgroup I2C_LL I2C
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_LL_Private_Constants I2C Private Constants
* @{
*/
/* Defines used to perform compute and check in the macros */
#define LL_I2C_MAX_SPEED_STANDARD 100000U
#define LL_I2C_MAX_SPEED_FAST 400000U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2C_LL_Private_Macros I2C Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
* @{
*/
typedef struct
{
uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
uint32_t ClockSpeed; /*!< Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz (in Hz)
This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
uint32_t OwnAddress1; /*!< Specifies the device own address 1.
This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
} LL_I2C_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_I2C_ReadReg function
* @{
*/
#define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
Address matched flag (slave mode) */
#define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
#define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
#define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
#define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
#define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
#define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
#define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
/**
* @}
*/
/** @defgroup I2C_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
* @{
*/
#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
/**
* @}
*/
/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
* @{
*/
#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
/**
* @}
*/
/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
* @{
*/
#define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
/**
* @}
*/
/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
* @{
*/
#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
/**
* @}
*/
/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
* @{
*/
#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
/**
* @}
*/
/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
* @{
*/
#define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
#define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
* @{
*/
#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
#define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
* @{
*/
/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in I2C register
* @param __INSTANCE__ I2C Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in I2C register
* @param __INSTANCE__ I2C Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported Macros Helper
* @{
*/
/**
* @brief Convert Peripheral Clock Frequency in Mhz.
* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
* @retval Value of peripheral clock (in Mhz)
*/
#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
/**
* @brief Convert Peripheral Clock Frequency in Hz.
* @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
* @retval Value of peripheral clock (in Hz)
*/
#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
/**
* @brief Compute I2C Clock rising time.
* @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
* @retval Value between Min_Data=0x02 and Max_Data=0x3F
*/
#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
/**
* @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
* @param __DUTYCYCLE__ This parameter can be one of the following values:
* @arg @ref LL_I2C_DUTYCYCLE_2
* @arg @ref LL_I2C_DUTYCYCLE_16_9
* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
*/
#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
(__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
(__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
/**
* @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
* @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
* @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
*/
#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
/**
* @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
* @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
* @param __DUTYCYCLE__ This parameter can be one of the following values:
* @arg @ref LL_I2C_DUTYCYCLE_2
* @arg @ref LL_I2C_DUTYCYCLE_16_9
* @retval Value between Min_Data=0x001 and Max_Data=0xFFF
*/
#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
(((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
(((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
/**
* @brief Get the Least significant bits of a 10-Bits address.
* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
/**
* @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
* @retval Value between Min_Data=0xF0 and Max_Data=0xF6
*/
#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
/**
* @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
* @retval Value between Min_Data=0xF1 and Max_Data=0xF7
*/
#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
* @{
*/
/** @defgroup I2C_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable I2C peripheral (PE = 1).
* @rmtoll CR1 PE LL_I2C_Enable
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_PE);
}
/**
* @brief Disable I2C peripheral (PE = 0).
* @rmtoll CR1 PE LL_I2C_Disable
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
}
/**
* @brief Check if the I2C peripheral is enabled or disabled.
* @rmtoll CR1 PE LL_I2C_IsEnabled
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
}
/**
* @brief Enable DMA transmission requests.
* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
}
/**
* @brief Disable DMA transmission requests.
* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
}
/**
* @brief Check if DMA transmission requests are enabled or disabled.
* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
}
/**
* @brief Enable DMA reception requests.
* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
}
/**
* @brief Disable DMA reception requests.
* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
}
/**
* @brief Check if DMA reception requests are enabled or disabled.
* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
}
/**
* @brief Get the data register address used for DMA transfer.
* @rmtoll DR DR LL_I2C_DMA_GetRegAddr
* @param I2Cx I2C Instance.
* @retval Address of data register
*/
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
{
return (uint32_t) & (I2Cx->DR);
}
/**
* @brief Enable Clock stretching.
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
}
/**
* @brief Disable Clock stretching.
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
}
/**
* @brief Check if Clock stretching is enabled or disabled.
* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
}
/**
* @brief Enable General Call.
* @note When enabled the Address 0x00 is ACKed.
* @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
}
/**
* @brief Disable General Call.
* @note When disabled the Address 0x00 is NACKed.
* @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
}
/**
* @brief Check if General Call is enabled or disabled.
* @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
}
/**
* @brief Set the Own Address1.
* @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
* OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
* OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
* OAR1 ADDMODE LL_I2C_SetOwnAddress1
* @param I2Cx I2C Instance.
* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
* @param OwnAddrSize This parameter can be one of the following values:
* @arg @ref LL_I2C_OWNADDRESS1_7BIT
* @arg @ref LL_I2C_OWNADDRESS1_10BIT
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
{
MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
}
/**
* @brief Set the 7bits Own Address2.
* @note This action has no effect if own address2 is enabled.
* @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
* @param I2Cx I2C Instance.
* @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
{
MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
}
/**
* @brief Enable acknowledge on Own Address2 match address.
* @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
}
/**
* @brief Disable acknowledge on Own Address2 match address.
* @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
}
/**
* @brief Check if Own Address1 acknowledge is enabled or disabled.
* @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
}
/**
* @brief Configure the Peripheral clock frequency.
* @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
* @param I2Cx I2C Instance.
* @param PeriphClock Peripheral Clock (in Hz)
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
}
/**
* @brief Get the Peripheral clock frequency.
* @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
* @param I2Cx I2C Instance.
* @retval Value of Peripheral Clock (in Hz)
*/
__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
{
return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
}
/**
* @brief Configure the Duty cycle (Fast mode only).
* @rmtoll CCR DUTY LL_I2C_SetDutyCycle
* @param I2Cx I2C Instance.
* @param DutyCycle This parameter can be one of the following values:
* @arg @ref LL_I2C_DUTYCYCLE_2
* @arg @ref LL_I2C_DUTYCYCLE_16_9
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
{
MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
}
/**
* @brief Get the Duty cycle (Fast mode only).
* @rmtoll CCR DUTY LL_I2C_GetDutyCycle
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_DUTYCYCLE_2
* @arg @ref LL_I2C_DUTYCYCLE_16_9
*/
__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
}
/**
* @brief Configure the I2C master clock speed mode.
* @rmtoll CCR FS LL_I2C_SetClockSpeedMode
* @param I2Cx I2C Instance.
* @param ClockSpeedMode This parameter can be one of the following values:
* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
{
MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
}
/**
* @brief Get the the I2C master speed mode.
* @rmtoll CCR FS LL_I2C_GetClockSpeedMode
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
*/
__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
}
/**
* @brief Configure the SCL, SDA rising time.
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll TRISE TRISE LL_I2C_SetRiseTime
* @param I2Cx I2C Instance.
* @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
{
MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
}
/**
* @brief Get the SCL, SDA rising time.
* @rmtoll TRISE TRISE LL_I2C_GetRiseTime
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x02 and Max_Data=0x3F
*/
__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
}
/**
* @brief Configure the SCL high and low period.
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CCR CCR LL_I2C_SetClockPeriod
* @param I2Cx I2C Instance.
* @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
{
MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
}
/**
* @brief Get the SCL high and low period.
* @rmtoll CCR CCR LL_I2C_GetClockPeriod
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
*/
__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
}
/**
* @brief Configure the SCL speed.
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
* TRISE TRISE LL_I2C_ConfigSpeed\n
* CCR FS LL_I2C_ConfigSpeed\n
* CCR DUTY LL_I2C_ConfigSpeed\n
* CCR CCR LL_I2C_ConfigSpeed
* @param I2Cx I2C Instance.
* @param PeriphClock Peripheral Clock (in Hz)
* @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
* @param DutyCycle This parameter can be one of the following values:
* @arg @ref LL_I2C_DUTYCYCLE_2
* @arg @ref LL_I2C_DUTYCYCLE_16_9
* @retval None
*/
__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
uint32_t DutyCycle)
{
uint32_t freqrange = 0x0U;
uint32_t clockconfig = 0x0U;
/* Compute frequency range */
freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
/* Configure I2Cx: Frequency range register */
MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
/* Configure I2Cx: Rise Time register */
MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
/* Configure Speed mode, Duty Cycle and Clock control register value */
if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
{
/* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
__LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
DutyCycle;
}
else
{
/* Set Speed mode at standard for Clock Speed request in standard clock range */
clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
__LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
}
/* Configure I2Cx: Clock control register */
MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
}
/**
* @brief Configure peripheral mode.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBUS LL_I2C_SetMode\n
* CR1 SMBTYPE LL_I2C_SetMode\n
* CR1 ENARP LL_I2C_SetMode
* @param I2Cx I2C Instance.
* @param PeripheralMode This parameter can be one of the following values:
* @arg @ref LL_I2C_MODE_I2C
* @arg @ref LL_I2C_MODE_SMBUS_HOST
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
{
MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
}
/**
* @brief Get peripheral mode.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBUS LL_I2C_GetMode\n
* CR1 SMBTYPE LL_I2C_GetMode\n
* CR1 ENARP LL_I2C_GetMode
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_MODE_I2C
* @arg @ref LL_I2C_MODE_SMBUS_HOST
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
*/
__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
}
/**
* @brief Enable SMBus alert (Host or Device mode)
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is drived low and
* Alert Response Address Header acknowledge is enabled.
* SMBus Host mode:
* - SMBus Alert pin management is supported.
* @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
}
/**
* @brief Disable SMBus alert (Host or Device mode)
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
* Alert Response Address Header acknowledge is disabled.
* SMBus Host mode:
* - SMBus Alert pin management is not supported.
* @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
}
/**
* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
}
/**
* @brief Enable SMBus Packet Error Calculation (PEC).
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
}
/**
* @brief Disable SMBus Packet Error Calculation (PEC).
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
}
/**
* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
}
/**
* @}
*/
/** @defgroup I2C_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable TXE interrupt.
* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
* CR2 ITBUFEN LL_I2C_EnableIT_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
}
/**
* @brief Disable TXE interrupt.
* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
* CR2 ITBUFEN LL_I2C_DisableIT_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
}
/**
* @brief Check if the TXE Interrupt is enabled or disabled.
* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
* CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
}
/**
* @brief Enable RXNE interrupt.
* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
* CR2 ITBUFEN LL_I2C_EnableIT_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
}
/**
* @brief Disable RXNE interrupt.
* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
* CR2 ITBUFEN LL_I2C_DisableIT_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
}
/**
* @brief Check if the RXNE Interrupt is enabled or disabled.
* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
* CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
}
/**
* @brief Enable Events interrupts.
* @note Any of these events will generate interrupt :
* Start Bit (SB)
* Address sent, Address matched (ADDR)
* 10-bit header sent (ADD10)
* Stop detection (STOPF)
* Byte transfer finished (BTF)
*
* @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
* Receive buffer not empty (RXNE)
* Transmit buffer empty (TXE)
* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
}
/**
* @brief Disable Events interrupts.
* @note Any of these events will generate interrupt :
* Start Bit (SB)
* Address sent, Address matched (ADDR)
* 10-bit header sent (ADD10)
* Stop detection (STOPF)
* Byte transfer finished (BTF)
* Receive buffer not empty (RXNE)
* Transmit buffer empty (TXE)
* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
}
/**
* @brief Check if Events interrupts are enabled or disabled.
* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
}
/**
* @brief Enable Buffer interrupts.
* @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
* Receive buffer not empty (RXNE)
* Transmit buffer empty (TXE)
* @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
}
/**
* @brief Disable Buffer interrupts.
* @note Any of these Buffer events will generate interrupt :
* Receive buffer not empty (RXNE)
* Transmit buffer empty (TXE)
* @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
}
/**
* @brief Check if Buffer interrupts are enabled or disabled.
* @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
}
/**
* @brief Enable Error interrupts.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Bus Error detection (BERR)
* Arbitration Loss (ARLO)
* Acknowledge Failure(AF)
* Overrun/Underrun (OVR)
* SMBus Timeout detection (TIMEOUT)
* SMBus PEC error detection (PECERR)
* SMBus Alert pin event detection (SMBALERT)
* @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
}
/**
* @brief Disable Error interrupts.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Bus Error detection (BERR)
* Arbitration Loss (ARLO)
* Acknowledge Failure(AF)
* Overrun/Underrun (OVR)
* SMBus Timeout detection (TIMEOUT)
* SMBus PEC error detection (PECERR)
* SMBus Alert pin event detection (SMBALERT)
* @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
}
/**
* @brief Check if Error interrupts are enabled or disabled.
* @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
}
/**
* @}
*/
/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
* @{
*/
/**
* @brief Indicate the status of Transmit data register empty flag.
* @note RESET: When next data is written in Transmit data register.
* SET: When Transmit data register is empty.
* @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
}
/**
* @brief Indicate the status of Byte Transfer Finished flag.
* RESET: When Data byte transfer not done.
* SET: When Data byte transfer succeeded.
* @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
}
/**
* @brief Indicate the status of Receive data register not empty flag.
* @note RESET: When Receive data register is read.
* SET: When the received data is copied in Receive data register.
* @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
}
/**
* @brief Indicate the status of Start Bit (master mode).
* @note RESET: When No Start condition.
* SET: When Start condition is generated.
* @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
}
/**
* @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
* @note RESET: Clear default value.
* SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
* @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
}
/**
* @brief Indicate the status of 10-bit header sent (master mode).
* @note RESET: When no ADD10 event occurred.
* SET: When the master has sent the first address byte (header).
* @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
}
/**
* @brief Indicate the status of Acknowledge failure flag.
* @note RESET: No acknowledge failure.
* SET: When an acknowledge failure is received after a byte transmission.
* @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
}
/**
* @brief Indicate the status of Stop detection flag (slave mode).
* @note RESET: Clear default value.
* SET: When a Stop condition is detected.
* @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
}
/**
* @brief Indicate the status of Bus error flag.
* @note RESET: Clear default value.
* SET: When a misplaced Start or Stop condition is detected.
* @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
}
/**
* @brief Indicate the status of Arbitration lost flag.
* @note RESET: Clear default value.
* SET: When arbitration lost.
* @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
}
/**
* @brief Indicate the status of Overrun/Underrun flag.
* @note RESET: Clear default value.
* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
* @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
}
/**
* @brief Indicate the status of SMBus PEC error flag in reception.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
}
/**
* @brief Indicate the status of SMBus Timeout detection flag.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
}
/**
* @brief Indicate the status of SMBus alert flag.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
}
/**
* @brief Indicate the status of Bus Busy flag.
* @note RESET: Clear default value.
* SET: When a Start condition is detected.
* @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
}
/**
* @brief Indicate the status of Dual flag.
* @note RESET: Received address matched with OAR1.
* SET: Received address matched with OAR2.
* @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
}
/**
* @brief Indicate the status of SMBus Host address reception (Slave mode).
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: No SMBus Host address
* SET: SMBus Host address received.
* @note This status is cleared by hardware after a STOP condition or repeated START condition.
* @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
}
/**
* @brief Indicate the status of SMBus Device default address reception (Slave mode).
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: No SMBus Device default address
* SET: SMBus Device default address received.
* @note This status is cleared by hardware after a STOP condition or repeated START condition.
* @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
}
/**
* @brief Indicate the status of General call address reception (Slave mode).
* @note RESET: No General call address
* SET: General call address received.
* @note This status is cleared by hardware after a STOP condition or repeated START condition.
* @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
}
/**
* @brief Indicate the status of Master/Slave flag.
* @note RESET: Slave Mode.
* SET: Master Mode.
* @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
}
/**
* @brief Clear Address Matched flag.
* @note Clearing this flag is done by a read access to the I2Cx_SR1
* register followed by a read access to the I2Cx_SR2 register.
* @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
{
__IO uint32_t tmpreg;
tmpreg = I2Cx->SR1;
(void) tmpreg;
tmpreg = I2Cx->SR2;
(void) tmpreg;
}
/**
* @brief Clear Acknowledge failure flag.
* @rmtoll SR1 AF LL_I2C_ClearFlag_AF
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
}
/**
* @brief Clear Stop detection flag.
* @note Clearing this flag is done by a read access to the I2Cx_SR1
* register followed by a write access to I2Cx_CR1 register.
* @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
* CR1 PE LL_I2C_ClearFlag_STOP
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
{
__IO uint32_t tmpreg;
tmpreg = I2Cx->SR1;
(void) tmpreg;
SET_BIT(I2Cx->CR1, I2C_CR1_PE);
}
/**
* @brief Clear Bus error flag.
* @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
}
/**
* @brief Clear Arbitration lost flag.
* @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
}
/**
* @brief Clear Overrun/Underrun flag.
* @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
}
/**
* @brief Clear SMBus PEC error flag.
* @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
}
/**
* @brief Clear SMBus Timeout detection flag.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
}
/**
* @brief Clear SMBus Alert flag.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
}
/**
* @}
*/
/** @defgroup I2C_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Enable Reset of I2C peripheral.
* @rmtoll CR1 SWRST LL_I2C_EnableReset
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
}
/**
* @brief Disable Reset of I2C peripheral.
* @rmtoll CR1 SWRST LL_I2C_DisableReset
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
}
/**
* @brief Check if the I2C peripheral is under reset state or not.
* @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
}
/**
* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
* @note Usage in Slave or Master mode.
* @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
* @param I2Cx I2C Instance.
* @param TypeAcknowledge This parameter can be one of the following values:
* @arg @ref LL_I2C_ACK
* @arg @ref LL_I2C_NACK
* @retval None
*/
__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
{
MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
}
/**
* @brief Generate a START or RESTART condition
* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
* This action has no effect when RELOAD is set.
* @rmtoll CR1 START LL_I2C_GenerateStartCondition
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_START);
}
/**
* @brief Generate a STOP condition after the current byte transfer (master mode).
* @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
}
/**
* @brief Enable bit POS (master/host mode).
* @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
* @rmtoll CR1 POS LL_I2C_EnableBitPOS
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_POS);
}
/**
* @brief Disable bit POS (master/host mode).
* @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
* @rmtoll CR1 POS LL_I2C_DisableBitPOS
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
}
/**
* @brief Check if bit POS is enabled or disabled.
* @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
}
/**
* @brief Indicate the value of transfer direction.
* @note RESET: Bus is in read transfer (peripheral point of view).
* SET: Bus is in write transfer (peripheral point of view).
* @rmtoll SR2 TRA LL_I2C_GetTransferDirection
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_DIRECTION_WRITE
* @arg @ref LL_I2C_DIRECTION_READ
*/
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
}
/**
* @brief Enable DMA last transfer.
* @note This action mean that next DMA EOT is the last transfer.
* @rmtoll CR2 LAST LL_I2C_EnableLastDMA
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
}
/**
* @brief Disable DMA last transfer.
* @note This action mean that next DMA EOT is not the last transfer.
* @rmtoll CR2 LAST LL_I2C_DisableLastDMA
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
}
/**
* @brief Check if DMA last transfer is enabled or disabled.
* @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
}
/**
* @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This feature is cleared by hardware when the PEC byte is transferred or compared,
* or by a START or STOP condition, it is also cleared by software.
* @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
}
/**
* @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
}
/**
* @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
{
return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
}
/**
* @brief Get the SMBus Packet Error byte calculated.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
}
/**
* @brief Read Receive Data register.
* @rmtoll DR DR LL_I2C_ReceiveData8
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
{
return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
}
/**
* @brief Write in Transmit Data Register .
* @rmtoll DR DR LL_I2C_TransmitData8
* @param I2Cx I2C Instance.
* @param Data Value between Min_Data=0x0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
{
MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
* @{
*/
uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* I2C1 || I2C2 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_I2C_H */

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/**
******************************************************************************
* @file stm32f1xx_ll_rtc.h
* @author MCD Application Team
* @brief Header file of RTC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_RTC_H
#define __STM32F1xx_LL_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(RTC)
/** @defgroup RTC_LL RTC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_Private_Macros RTC Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
* @{
*/
/**
* @brief RTC Init structures definition
*/
typedef struct
{
uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF
This feature can be modified afterwards using unitary function
@ref LL_RTC_SetAsynchPrescaler(). */
uint32_t OutPutSource; /*!< Specifies which signal will be routed to the RTC Tamper pin.
This parameter can be a value of @ref LL_RTC_Output_Source
This feature can be modified afterwards using unitary function
@ref LL_RTC_SetOutputSource(). */
} LL_RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint8_t Hours; /*!< Specifies the RTC Time Hours.
This parameter must be a number between Min_Data = 0 and Max_Data = 23 */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
} LL_RTC_TimeTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
} LL_RTC_AlarmTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
* @{
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_EC_FORMAT FORMAT
* @{
*/
#define LL_RTC_FORMAT_BIN (0x000000000U) /*!< Binary data format */
#define LL_RTC_FORMAT_BCD (0x000000001U) /*!< BCD data format */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup RTC_LL_EC_BKP BACKUP
* @{
*/
#if RTC_BKP_NUMBER > 0
#define LL_RTC_BKP_DR1 (0x00000001U)
#define LL_RTC_BKP_DR2 (0x00000002U)
#define LL_RTC_BKP_DR3 (0x00000003U)
#define LL_RTC_BKP_DR4 (0x00000004U)
#define LL_RTC_BKP_DR5 (0x00000005U)
#define LL_RTC_BKP_DR6 (0x00000006U)
#define LL_RTC_BKP_DR7 (0x00000007U)
#define LL_RTC_BKP_DR8 (0x00000008U)
#define LL_RTC_BKP_DR9 (0x00000009U)
#define LL_RTC_BKP_DR10 (0x0000000AU)
#endif /* RTC_BKP_NUMBER > 0 */
#if RTC_BKP_NUMBER > 10
#define LL_RTC_BKP_DR11 (0x00000010U)
#define LL_RTC_BKP_DR12 (0x00000011U)
#define LL_RTC_BKP_DR13 (0x00000012U)
#define LL_RTC_BKP_DR14 (0x00000013U)
#define LL_RTC_BKP_DR15 (0x00000014U)
#define LL_RTC_BKP_DR16 (0x00000015U)
#define LL_RTC_BKP_DR17 (0x00000016U)
#define LL_RTC_BKP_DR18 (0x00000017U)
#define LL_RTC_BKP_DR19 (0x00000018U)
#define LL_RTC_BKP_DR20 (0x00000019U)
#define LL_RTC_BKP_DR21 (0x0000001AU)
#define LL_RTC_BKP_DR22 (0x0000001BU)
#define LL_RTC_BKP_DR23 (0x0000001CU)
#define LL_RTC_BKP_DR24 (0x0000001DU)
#define LL_RTC_BKP_DR25 (0x0000001EU)
#define LL_RTC_BKP_DR26 (0x0000001FU)
#define LL_RTC_BKP_DR27 (0x00000020U)
#define LL_RTC_BKP_DR28 (0x00000021U)
#define LL_RTC_BKP_DR29 (0x00000022U)
#define LL_RTC_BKP_DR30 (0x00000023U)
#define LL_RTC_BKP_DR31 (0x00000024U)
#define LL_RTC_BKP_DR32 (0x00000025U)
#define LL_RTC_BKP_DR33 (0x00000026U)
#define LL_RTC_BKP_DR34 (0x00000027U)
#define LL_RTC_BKP_DR35 (0x00000028U)
#define LL_RTC_BKP_DR36 (0x00000029U)
#define LL_RTC_BKP_DR37 (0x0000002AU)
#define LL_RTC_BKP_DR38 (0x0000002BU)
#define LL_RTC_BKP_DR39 (0x0000002CU)
#define LL_RTC_BKP_DR40 (0x0000002DU)
#define LL_RTC_BKP_DR41 (0x0000002EU)
#define LL_RTC_BKP_DR42 (0x0000002FU)
#endif /* RTC_BKP_NUMBER > 10 */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPLEVEL Tamper Active Level
* @{
*/
#define LL_RTC_TAMPER_ACTIVELEVEL_LOW BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
#define LL_RTC_TAMPER_ACTIVELEVEL_HIGH (0x00000000U) /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
/**
* @}
*/
/** @defgroup LL_RTC_Output_Source Clock Source to output on the Tamper Pin
* @{
*/
#define LL_RTC_CALIB_OUTPUT_NONE (0x00000000U) /*!< Calibration output disabled */
#define LL_RTC_CALIB_OUTPUT_RTCCLOCK BKP_RTCCR_CCO /*!< Calibration output is RTC Clock with a frequency divided by 64 on the TAMPER Pin */
#define LL_RTC_CALIB_OUTPUT_ALARM BKP_RTCCR_ASOE /*!< Calibration output is Alarm pulse signal on the TAMPER pin */
#define LL_RTC_CALIB_OUTPUT_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Calibration output is Second pulse signal on the TAMPER pin*/
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
* @{
*/
/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in RTC register
* @param __INSTANCE__ RTC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in RTC register
* @param __INSTANCE__ RTC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup RTC_LL_EM_Convert Convert helper Macros
* @{
*/
/**
* @brief Helper macro to convert a value from 2 digit decimal format to BCD format
* @param __VALUE__ Byte to be converted
* @retval Converted byte
*/
#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
/**
* @brief Helper macro to convert a value from BCD format to 2 digit decimal format
* @param __VALUE__ BCD value to be converted
* @retval Converted byte
*/
#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
* @{
*/
/** @defgroup RTC_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Set Asynchronous prescaler factor
* @rmtoll PRLH PRL LL_RTC_SetAsynchPrescaler\n
* @rmtoll PRLL PRL LL_RTC_SetAsynchPrescaler\n
* @param RTCx RTC Instance
* @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0xFFFFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
{
MODIFY_REG(RTCx->PRLH, RTC_PRLH_PRL, (AsynchPrescaler >> 16));
MODIFY_REG(RTCx->PRLL, RTC_PRLL_PRL, (AsynchPrescaler & RTC_PRLL_PRL));
}
/**
* @brief Get Asynchronous prescaler factor
* @rmtoll DIVH DIV LL_RTC_GetDivider\n
* @rmtoll DIVL DIV LL_RTC_GetDivider\n
* @param RTCx RTC Instance
* @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_GetDivider(RTC_TypeDef *RTCx)
{
register uint16_t Highprescaler = 0, Lowprescaler = 0;
Highprescaler = READ_REG(RTCx->DIVH & RTC_DIVH_RTC_DIV);
Lowprescaler = READ_REG(RTCx->DIVL & RTC_DIVL_RTC_DIV);
return (((uint32_t) Highprescaler << 16U) | Lowprescaler);
}
/**
* @brief Set Output Source
* @rmtoll RTCCR CCO LL_RTC_SetOutputSource
* @rmtoll RTCCR ASOE LL_RTC_SetOutputSource
* @rmtoll RTCCR ASOS LL_RTC_SetOutputSource
* @param BKPx BKP Instance
* @param OutputSource This parameter can be one of the following values:
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
* @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK
* @arg @ref LL_RTC_CALIB_OUTPUT_ALARM
* @arg @ref LL_RTC_CALIB_OUTPUT_SECOND
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetOutputSource(BKP_TypeDef *BKPx, uint32_t OutputSource)
{
MODIFY_REG(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), OutputSource);
}
/**
* @brief Get Output Source
* @rmtoll RTCCR CCO LL_RTC_GetOutPutSource
* @rmtoll RTCCR ASOE LL_RTC_GetOutPutSource
* @rmtoll RTCCR ASOS LL_RTC_GetOutPutSource
* @param BKPx BKP Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
* @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK
* @arg @ref LL_RTC_CALIB_OUTPUT_ALARM
* @arg @ref LL_RTC_CALIB_OUTPUT_SECOND
*/
__STATIC_INLINE uint32_t LL_RTC_GetOutPutSource(BKP_TypeDef *BKPx)
{
return (uint32_t)(READ_BIT(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS)));
}
/**
* @brief Enable the write protection for RTC registers.
* @rmtoll CRL CNF LL_RTC_EnableWriteProtection
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CRL, RTC_CRL_CNF);
}
/**
* @brief Disable the write protection for RTC registers.
* @rmtoll CRL RTC_CRL_CNF LL_RTC_DisableWriteProtection
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CRL, RTC_CRL_CNF);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Time Time
* @{
*/
/**
* @brief Set time counter in BCD format
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function)
* @rmtoll CNTH CNT LL_RTC_TIME_Set\n
* CNTL CNT LL_RTC_TIME_Set\n
* @param RTCx RTC Instance
* @param TimeCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_Set(RTC_TypeDef *RTCx, uint32_t TimeCounter)
{
/* Set RTC COUNTER MSB word */
WRITE_REG(RTCx->CNTH, (TimeCounter >> 16U));
/* Set RTC COUNTER LSB word */
WRITE_REG(RTCx->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT));
}
/**
* @brief Get time counter in BCD format
* @rmtoll CNTH CNT LL_RTC_TIME_Get\n
* CNTL CNT LL_RTC_TIME_Get\n
* @param RTCx RTC Instance
* @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
{
register uint16_t high = 0, low = 0;
high = READ_REG(RTCx->CNTH & RTC_CNTH_RTC_CNT);
low = READ_REG(RTCx->CNTL & RTC_CNTL_RTC_CNT);
return ((uint32_t)(((uint32_t) high << 16U) | low));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_ALARM ALARM
* @{
*/
/**
* @brief Set Alarm Counter
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll ALRH ALR LL_RTC_ALARM_Set\n
* @rmtoll ALRL ALR LL_RTC_ALARM_Set\n
* @param RTCx RTC Instance
* @param AlarmCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALARM_Set(RTC_TypeDef *RTCx, uint32_t AlarmCounter)
{
/* Set RTC COUNTER MSB word */
WRITE_REG(RTCx->ALRH, (AlarmCounter >> 16));
/* Set RTC COUNTER LSB word */
WRITE_REG(RTCx->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR));
}
/**
* @brief Get Alarm Counter
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll ALRH ALR LL_RTC_ALARM_Get\n
* @rmtoll ALRL ALR LL_RTC_ALARM_Get\n
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_RTC_ALARM_Get(RTC_TypeDef *RTCx)
{
register uint16_t high = 0, low = 0;
high = READ_REG(RTCx->ALRH & RTC_ALRH_RTC_ALR);
low = READ_REG(RTCx->ALRL & RTC_ALRL_RTC_ALR);
return (((uint32_t) high << 16U) | low);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Tamper Tamper
* @{
*/
/**
* @brief Enable RTC_TAMPx input detection
* @rmtoll CR TPE LL_RTC_TAMPER_Enable\n
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_Enable(BKP_TypeDef *BKPx)
{
SET_BIT(BKPx->CR, BKP_CR_TPE);
}
/**
* @brief Disable RTC_TAMPx Tamper
* @rmtoll CR TPE LL_RTC_TAMPER_Disable\n
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_Disable(BKP_TypeDef *BKPx)
{
CLEAR_BIT(BKP->CR, BKP_CR_TPE);
}
/**
* @brief Enable Active level for Tamper input
* @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n
* @param BKPx BKP Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_LOW
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_HIGH
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_SetActiveLevel(BKP_TypeDef *BKPx, uint32_t Tamper)
{
MODIFY_REG(BKPx->CR, BKP_CR_TPAL, Tamper);
}
/**
* @brief Disable Active level for Tamper input
* @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n
* @retval None
*/
__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetActiveLevel(BKP_TypeDef *BKPx)
{
return (uint32_t)(READ_BIT(BKPx->CR, BKP_CR_TPAL));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
* @{
*/
/**
* @brief Writes a data in a specified RTC Backup data register.
* @rmtoll BKPDR DR LL_RTC_BKP_SetRegister
* @param BKPx BKP Instance
* @param BackupRegister This parameter can be one of the following values:
* @arg @ref LL_RTC_BKP_DR1
* @arg @ref LL_RTC_BKP_DR2
* @arg @ref LL_RTC_BKP_DR3
* @arg @ref LL_RTC_BKP_DR4
* @arg @ref LL_RTC_BKP_DR5
* @arg @ref LL_RTC_BKP_DR6
* @arg @ref LL_RTC_BKP_DR7
* @arg @ref LL_RTC_BKP_DR8
* @arg @ref LL_RTC_BKP_DR9
* @arg @ref LL_RTC_BKP_DR10
* @arg @ref LL_RTC_BKP_DR11 (*)
* @arg @ref LL_RTC_BKP_DR12 (*)
* @arg @ref LL_RTC_BKP_DR13 (*)
* @arg @ref LL_RTC_BKP_DR14 (*)
* @arg @ref LL_RTC_BKP_DR15 (*)
* @arg @ref LL_RTC_BKP_DR16 (*)
* @arg @ref LL_RTC_BKP_DR17 (*)
* @arg @ref LL_RTC_BKP_DR18 (*)
* @arg @ref LL_RTC_BKP_DR19 (*)
* @arg @ref LL_RTC_BKP_DR20 (*)
* @arg @ref LL_RTC_BKP_DR21 (*)
* @arg @ref LL_RTC_BKP_DR22 (*)
* @arg @ref LL_RTC_BKP_DR23 (*)
* @arg @ref LL_RTC_BKP_DR24 (*)
* @arg @ref LL_RTC_BKP_DR25 (*)
* @arg @ref LL_RTC_BKP_DR26 (*)
* @arg @ref LL_RTC_BKP_DR27 (*)
* @arg @ref LL_RTC_BKP_DR28 (*)
* @arg @ref LL_RTC_BKP_DR29 (*)
* @arg @ref LL_RTC_BKP_DR30 (*)
* @arg @ref LL_RTC_BKP_DR31 (*)
* @arg @ref LL_RTC_BKP_DR32 (*)
* @arg @ref LL_RTC_BKP_DR33 (*)
* @arg @ref LL_RTC_BKP_DR34 (*)
* @arg @ref LL_RTC_BKP_DR35 (*)
* @arg @ref LL_RTC_BKP_DR36 (*)
* @arg @ref LL_RTC_BKP_DR37 (*)
* @arg @ref LL_RTC_BKP_DR38 (*)
* @arg @ref LL_RTC_BKP_DR39 (*)
* @arg @ref LL_RTC_BKP_DR40 (*)
* @arg @ref LL_RTC_BKP_DR41 (*)
* @arg @ref LL_RTC_BKP_DR42 (*)
* (*) value not defined in all devices.
* @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_BKP_SetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister, uint32_t Data)
{
register uint32_t tmp = 0U;
tmp = (uint32_t)BKP_BASE;
tmp += (BackupRegister * 4U);
/* Write the specified register */
*(__IO uint32_t *)tmp = (uint32_t)Data;
}
/**
* @brief Reads data from the specified RTC Backup data Register.
* @rmtoll BKPDR DR LL_RTC_BKP_GetRegister
* @param BKPx BKP Instance
* @param BackupRegister This parameter can be one of the following values:
* @arg @ref LL_RTC_BKP_DR1
* @arg @ref LL_RTC_BKP_DR2
* @arg @ref LL_RTC_BKP_DR3
* @arg @ref LL_RTC_BKP_DR4
* @arg @ref LL_RTC_BKP_DR5
* @arg @ref LL_RTC_BKP_DR6
* @arg @ref LL_RTC_BKP_DR7
* @arg @ref LL_RTC_BKP_DR8
* @arg @ref LL_RTC_BKP_DR9
* @arg @ref LL_RTC_BKP_DR10
* @arg @ref LL_RTC_BKP_DR11 (*)
* @arg @ref LL_RTC_BKP_DR12 (*)
* @arg @ref LL_RTC_BKP_DR13 (*)
* @arg @ref LL_RTC_BKP_DR14 (*)
* @arg @ref LL_RTC_BKP_DR15 (*)
* @arg @ref LL_RTC_BKP_DR16 (*)
* @arg @ref LL_RTC_BKP_DR17 (*)
* @arg @ref LL_RTC_BKP_DR18 (*)
* @arg @ref LL_RTC_BKP_DR19 (*)
* @arg @ref LL_RTC_BKP_DR20 (*)
* @arg @ref LL_RTC_BKP_DR21 (*)
* @arg @ref LL_RTC_BKP_DR22 (*)
* @arg @ref LL_RTC_BKP_DR23 (*)
* @arg @ref LL_RTC_BKP_DR24 (*)
* @arg @ref LL_RTC_BKP_DR25 (*)
* @arg @ref LL_RTC_BKP_DR26 (*)
* @arg @ref LL_RTC_BKP_DR27 (*)
* @arg @ref LL_RTC_BKP_DR28 (*)
* @arg @ref LL_RTC_BKP_DR29 (*)
* @arg @ref LL_RTC_BKP_DR30 (*)
* @arg @ref LL_RTC_BKP_DR31 (*)
* @arg @ref LL_RTC_BKP_DR32 (*)
* @arg @ref LL_RTC_BKP_DR33 (*)
* @arg @ref LL_RTC_BKP_DR34 (*)
* @arg @ref LL_RTC_BKP_DR35 (*)
* @arg @ref LL_RTC_BKP_DR36 (*)
* @arg @ref LL_RTC_BKP_DR37 (*)
* @arg @ref LL_RTC_BKP_DR38 (*)
* @arg @ref LL_RTC_BKP_DR39 (*)
* @arg @ref LL_RTC_BKP_DR40 (*)
* @arg @ref LL_RTC_BKP_DR41 (*)
* @arg @ref LL_RTC_BKP_DR42 (*)
* @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister)
{
register uint32_t tmp = 0U;
tmp = (uint32_t)BKP_BASE;
tmp += (BackupRegister * 4U);
/* Read the specified register */
return ((*(__IO uint32_t *)tmp) & BKP_DR1_D);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Calibration Calibration
* @{
*/
/**
* @brief Set the coarse digital calibration
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function)
* @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n
* @param BKPx RTC Instance
* @param Value value of coarse calibration expressed in ppm (coded on 5 bits)
* @note This Calibration value should be between 0 and 121 when using positive sign with a 4-ppm step.
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_SetCoarseDigital(BKP_TypeDef *BKPx, uint32_t Value)
{
MODIFY_REG(BKPx->RTCCR, BKP_RTCCR_CAL, Value);
}
/**
* @brief Get the coarse digital calibration value
* @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n
* @param BKPx BKP Instance
* @retval value of coarse calibration expressed in ppm (coded on 5 bits)
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigital(BKP_TypeDef *BKPx)
{
return (uint32_t)(READ_BIT(BKPx->RTCCR, BKP_RTCCR_CAL));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Get RTC_TAMPI Interruption detection flag
* @rmtoll CSR TIF LL_RTC_IsActiveFlag_TAMPI
* @param BKPx BKP Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPI(BKP_TypeDef *BKPx)
{
return (READ_BIT(BKPx->CSR, BKP_CSR_TIF) == (BKP_CSR_TIF));
}
/**
* @brief Clear RTC_TAMP Interruption detection flag
* @rmtoll CSR CTI LL_RTC_ClearFlag_TAMPI
* @param BKPx BKP Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMPI(BKP_TypeDef *BKPx)
{
SET_BIT(BKPx->CSR, BKP_CSR_CTI);
}
/**
* @brief Get RTC_TAMPE Event detection flag
* @rmtoll CSR TEF LL_RTC_IsActiveFlag_TAMPE
* @param BKPx BKP Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPE(BKP_TypeDef *BKPx)
{
return (READ_BIT(BKPx->CSR, BKP_CSR_TEF) == (BKP_CSR_TEF));
}
/**
* @brief Clear RTC_TAMPE Even detection flag
* @rmtoll CSR CTE LL_RTC_ClearFlag_TAMPE
* @param BKPx BKP Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMPE(BKP_TypeDef *BKPx)
{
SET_BIT(BKPx->CSR, BKP_CSR_CTE);
}
/**
* @brief Get Alarm flag
* @rmtoll CRL ALRF LL_RTC_IsActiveFlag_ALR
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALR(RTC_TypeDef *RTCx)
{
return (READ_BIT(RTCx->CRL, RTC_CRL_ALRF) == (RTC_CRL_ALRF));
}
/**
* @brief Clear Alarm flag
* @rmtoll CRL ALRF LL_RTC_ClearFlag_ALR
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ALR(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CRL, RTC_CRL_ALRF);
}
/**
* @brief Get Registers synchronization flag
* @rmtoll CRL RSF LL_RTC_IsActiveFlag_RS
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
{
return (READ_BIT(RTCx->CRL, RTC_CRL_RSF) == (RTC_CRL_RSF));
}
/**
* @brief Clear Registers synchronization flag
* @rmtoll CRL RSF LL_RTC_ClearFlag_RS
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CRL, RTC_CRL_RSF);
}
/**
* @brief Get Registers OverFlow flag
* @rmtoll CRL OWF LL_RTC_IsActiveFlag_OW
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_OW(RTC_TypeDef *RTCx)
{
return (READ_BIT(RTCx->CRL, RTC_CRL_OWF) == (RTC_CRL_OWF));
}
/**
* @brief Clear Registers OverFlow flag
* @rmtoll CRL OWF LL_RTC_ClearFlag_OW
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_OW(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CRL, RTC_CRL_OWF);
}
/**
* @brief Get Registers synchronization flag
* @rmtoll CRL SECF LL_RTC_IsActiveFlag_SEC
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SEC(RTC_TypeDef *RTCx)
{
return (READ_BIT(RTCx->CRL, RTC_CRL_SECF) == (RTC_CRL_SECF));
}
/**
* @brief Clear Registers synchronization flag
* @rmtoll CRL SECF LL_RTC_ClearFlag_SEC
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_SEC(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CRL, RTC_CRL_SECF);
}
/**
* @brief Get RTC Operation OFF status flag
* @rmtoll CRL RTOFF LL_RTC_IsActiveFlag_RTOF
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RTOF(RTC_TypeDef *RTCx)
{
return (READ_BIT(RTCx->CRL, RTC_CRL_RTOFF) == (RTC_CRL_RTOFF));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable Alarm interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll CRH ALRIE LL_RTC_EnableIT_ALR
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ALR(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CRH, RTC_CRH_ALRIE);
}
/**
* @brief Disable Alarm interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll CRH ALRIE LL_RTC_DisableIT_ALR
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ALR(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CRH, RTC_CRH_ALRIE);
}
/**
* @brief Check if Alarm interrupt is enabled or not
* @rmtoll CRH ALRIE LL_RTC_IsEnabledIT_ALR
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALR(RTC_TypeDef *RTCx)
{
return (READ_BIT(RTCx->CRH, RTC_CRH_ALRIE) == (RTC_CRH_ALRIE));
}
/**
* @brief Enable Second Interrupt interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll CRH SECIE LL_RTC_EnableIT_SEC
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_SEC(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CRH, RTC_CRH_SECIE);
}
/**
* @brief Disable Second interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll CRH SECIE LL_RTC_DisableIT_SEC
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_SEC(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CRH, RTC_CRH_SECIE);
}
/**
* @brief Check if Second interrupt is enabled or not
* @rmtoll CRH SECIE LL_RTC_IsEnabledIT_SEC
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SEC(RTC_TypeDef *RTCx)
{
return (READ_BIT(RTCx->CRH, RTC_CRH_SECIE) == (RTC_CRH_SECIE));
}
/**
* @brief Enable OverFlow interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll CRH OWIE LL_RTC_EnableIT_OW
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_OW(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CRH, RTC_CRH_OWIE);
}
/**
* @brief Disable OverFlow interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll CRH OWIE LL_RTC_DisableIT_OW
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_OW(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CRH, RTC_CRH_OWIE);
}
/**
* @brief Check if OverFlow interrupt is enabled or not
* @rmtoll CRH OWIE LL_RTC_IsEnabledIT_OW
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_OW(RTC_TypeDef *RTCx)
{
return (READ_BIT(RTCx->CRH, RTC_CRH_OWIE) == (RTC_CRH_OWIE));
}
/**
* @brief Enable Tamper interrupt
* @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP
* @param BKPx BKP Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP(BKP_TypeDef *BKPx)
{
SET_BIT(BKPx->CSR, BKP_CSR_TPIE);
}
/**
* @brief Disable Tamper interrupt
* @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP
* @param BKPx BKP Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP(BKP_TypeDef *BKPx)
{
CLEAR_BIT(BKPx->CSR, BKP_CSR_TPIE);
}
/**
* @brief Check if all the TAMPER interrupts are enabled or not
* @rmtoll CSR TPIE LL_RTC_IsEnabledIT_TAMP
* @param BKPx BKP Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(BKP_TypeDef *BKPx)
{
return (READ_BIT(BKPx->CSR, BKP_CSR_TPIE) == BKP_CSR_TPIE);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter);
ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RTC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_RTC_H */

1951
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h Normal file
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@@ -0,0 +1,1951 @@
/**
******************************************************************************
* @file stm32f1xx_ll_spi.h
* @author MCD Application Team
* @brief Header file of SPI LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_SPI_H
#define STM32F1xx_LL_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (SPI1) || defined (SPI2) || defined (SPI3)
/** @defgroup SPI_LL SPI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
* @{
*/
/**
* @brief SPI Init structures definition
*/
typedef struct
{
uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
This feature can be modified afterwards using unitary
function @ref LL_SPI_SetTransferDirection().*/
uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
This parameter can be a value of @ref SPI_LL_EC_MODE.
This feature can be modified afterwards using unitary
function @ref LL_SPI_SetMode().*/
uint32_t DataWidth; /*!< Specifies the SPI data width.
This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
This feature can be modified afterwards using unitary
function @ref LL_SPI_SetDataWidth().*/
uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_LL_EC_POLARITY.
This feature can be modified afterwards using unitary
function @ref LL_SPI_SetClockPolarity().*/
uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_LL_EC_PHASE.
This feature can be modified afterwards using unitary
function @ref LL_SPI_SetClockPhase().*/
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
or by software using the SSI bit.
This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
This feature can be modified afterwards using unitary
function @ref LL_SPI_SetNSSMode().*/
uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used
to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
@note The communication clock is derived from the master clock.
The slave clock does not need to be set.
This feature can be modified afterwards using unitary
function @ref LL_SPI_SetBaudRatePrescaler().*/
uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
This feature can be modified afterwards using unitary
function @ref LL_SPI_SetTransferBitOrder().*/
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
This feature can be modified afterwards using unitary
functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary
function @ref LL_SPI_SetCRCPolynomial().*/
} LL_SPI_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
* @{
*/
/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_SPI_ReadReg function
* @{
*/
#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
/**
* @}
*/
/** @defgroup SPI_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
* @{
*/
#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
/**
* @}
*/
/** @defgroup SPI_LL_EC_MODE Operation Mode
* @{
*/
#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
/**
* @}
*/
/** @defgroup SPI_LL_EC_PHASE Clock Phase
* @{
*/
#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
/**
* @}
*/
/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
* @{
*/
#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
/**
* @}
*/
/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
* @{
*/
#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
/**
* @}
*/
/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
* @{
*/
#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
/**
* @}
*/
/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
* @{
*/
#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
/**
* @}
*/
/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
* @{
*/
#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
/**
* @}
*/
/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
* @{
*/
#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
* @{
*/
#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
* @{
*/
/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in SPI register
* @param __INSTANCE__ SPI Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in SPI register
* @param __INSTANCE__ SPI Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
* @{
*/
/** @defgroup SPI_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable SPI peripheral
* @rmtoll CR1 SPE LL_SPI_Enable
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_SPE);
}
/**
* @brief Disable SPI peripheral
* @note When disabling the SPI, follow the procedure described in the Reference Manual.
* @rmtoll CR1 SPE LL_SPI_Disable
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
}
/**
* @brief Check if SPI peripheral is enabled
* @rmtoll CR1 SPE LL_SPI_IsEnabled
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
}
/**
* @brief Set SPI operation mode to Master or Slave
* @note This bit should not be changed when communication is ongoing.
* @rmtoll CR1 MSTR LL_SPI_SetMode\n
* CR1 SSI LL_SPI_SetMode
* @param SPIx SPI Instance
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_SPI_MODE_MASTER
* @arg @ref LL_SPI_MODE_SLAVE
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
}
/**
* @brief Get SPI operation mode (Master or Slave)
* @rmtoll CR1 MSTR LL_SPI_GetMode\n
* CR1 SSI LL_SPI_GetMode
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_MODE_MASTER
* @arg @ref LL_SPI_MODE_SLAVE
*/
__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
}
/**
* @brief Set clock phase
* @note This bit should not be changed when communication is ongoing.
* This bit is not used in SPI TI mode.
* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
* @param SPIx SPI Instance
* @param ClockPhase This parameter can be one of the following values:
* @arg @ref LL_SPI_PHASE_1EDGE
* @arg @ref LL_SPI_PHASE_2EDGE
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
}
/**
* @brief Get clock phase
* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_PHASE_1EDGE
* @arg @ref LL_SPI_PHASE_2EDGE
*/
__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
}
/**
* @brief Set clock polarity
* @note This bit should not be changed when communication is ongoing.
* This bit is not used in SPI TI mode.
* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
* @param SPIx SPI Instance
* @param ClockPolarity This parameter can be one of the following values:
* @arg @ref LL_SPI_POLARITY_LOW
* @arg @ref LL_SPI_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
}
/**
* @brief Get clock polarity
* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_POLARITY_LOW
* @arg @ref LL_SPI_POLARITY_HIGH
*/
__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
}
/**
* @brief Set baud rate prescaler
* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
* @param SPIx SPI Instance
* @param BaudRate This parameter can be one of the following values:
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
}
/**
* @brief Get baud rate prescaler
* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
*/
__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
}
/**
* @brief Set transfer bit order
* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
* @param SPIx SPI Instance
* @param BitOrder This parameter can be one of the following values:
* @arg @ref LL_SPI_LSB_FIRST
* @arg @ref LL_SPI_MSB_FIRST
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
}
/**
* @brief Get transfer bit order
* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_LSB_FIRST
* @arg @ref LL_SPI_MSB_FIRST
*/
__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
}
/**
* @brief Set transfer direction mode
* @note For Half-Duplex mode, Rx Direction is set by default.
* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
* CR1 BIDIOE LL_SPI_SetTransferDirection
* @param SPIx SPI Instance
* @param TransferDirection This parameter can be one of the following values:
* @arg @ref LL_SPI_FULL_DUPLEX
* @arg @ref LL_SPI_SIMPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
}
/**
* @brief Get transfer direction mode
* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
* CR1 BIDIOE LL_SPI_GetTransferDirection
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_FULL_DUPLEX
* @arg @ref LL_SPI_SIMPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
*/
__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
}
/**
* @brief Set frame data width
* @rmtoll CR1 DFF LL_SPI_SetDataWidth
* @param SPIx SPI Instance
* @param DataWidth This parameter can be one of the following values:
* @arg @ref LL_SPI_DATAWIDTH_8BIT
* @arg @ref LL_SPI_DATAWIDTH_16BIT
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
}
/**
* @brief Get frame data width
* @rmtoll CR1 DFF LL_SPI_GetDataWidth
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_DATAWIDTH_8BIT
* @arg @ref LL_SPI_DATAWIDTH_16BIT
*/
__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_CRC_Management CRC Management
* @{
*/
/**
* @brief Enable CRC
* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
}
/**
* @brief Disable CRC
* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
}
/**
* @brief Check if CRC is enabled
* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
}
/**
* @brief Set CRCNext to transfer CRC on the line
* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
}
/**
* @brief Set polynomial for CRC calculation
* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
* @param SPIx SPI Instance
* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
{
WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
}
/**
* @brief Get polynomial for CRC calculation
* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->CRCPR));
}
/**
* @brief Get Rx CRC
* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->RXCRCR));
}
/**
* @brief Get Tx CRC
* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->TXCRCR));
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
* @{
*/
/**
* @brief Set NSS mode
* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
* @param SPIx SPI Instance
* @param NSS This parameter can be one of the following values:
* @arg @ref LL_SPI_NSS_SOFT
* @arg @ref LL_SPI_NSS_HARD_INPUT
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
}
/**
* @brief Get NSS mode
* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_NSS_SOFT
* @arg @ref LL_SPI_NSS_HARD_INPUT
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
*/
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
{
uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
return (Ssm | Ssoe);
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Check if Rx buffer is not empty
* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
}
/**
* @brief Check if Tx buffer is empty
* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
}
/**
* @brief Get CRC error flag
* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
}
/**
* @brief Get mode fault error flag
* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
}
/**
* @brief Get overrun error flag
* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
}
/**
* @brief Get busy flag
* @note The BSY flag is cleared under any one of the following conditions:
* -When the SPI is correctly disabled
* -When a fault is detected in Master mode (MODF bit set to 1)
* -In Master mode, when it finishes a data transmission and no new data is ready to be
* sent
* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
* each data transfer.
* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
}
/**
* @brief Clear CRC error flag
* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
}
/**
* @brief Clear mode fault error flag
* @note Clearing this flag is done by a read access to the SPIx_SR
* register followed by a write access to the SPIx_CR1 register
* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
{
__IO uint32_t tmpreg_sr;
tmpreg_sr = SPIx->SR;
(void) tmpreg_sr;
CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
}
/**
* @brief Clear overrun error flag
* @note Clearing this flag is done by a read access to the SPIx_DR
* register followed by a read access to the SPIx_SR register
* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
{
__IO uint32_t tmpreg;
tmpreg = SPIx->DR;
(void) tmpreg;
tmpreg = SPIx->SR;
(void) tmpreg;
}
/**
* @brief Clear frame format error flag
* @note Clearing this flag is done by reading SPIx_SR register
* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
{
__IO uint32_t tmpreg;
tmpreg = SPIx->SR;
(void) tmpreg;
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
* @{
*/
/**
* @brief Enable error interrupt
* @note This bit controls the generation of an interrupt when an error condition
* occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
}
/**
* @brief Enable Rx buffer not empty interrupt
* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
}
/**
* @brief Enable Tx buffer empty interrupt
* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
}
/**
* @brief Disable error interrupt
* @note This bit controls the generation of an interrupt when an error condition
* occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
}
/**
* @brief Disable Rx buffer not empty interrupt
* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
}
/**
* @brief Disable Tx buffer empty interrupt
* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
}
/**
* @brief Check if error interrupt is enabled
* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
}
/**
* @brief Check if Rx buffer not empty interrupt is enabled
* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if Tx buffer empty interrupt
* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_DMA_Management DMA Management
* @{
*/
/**
* @brief Enable DMA Rx
* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
}
/**
* @brief Disable DMA Rx
* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
}
/**
* @brief Check if DMA Rx is enabled
* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA Tx
* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
}
/**
* @brief Disable DMA Tx
* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
}
/**
* @brief Check if DMA Tx is enabled
* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
}
/**
* @brief Get the data register address used for DMA transfer
* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
* @param SPIx SPI Instance
* @retval Address of data register
*/
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx)
{
return (uint32_t) &(SPIx->DR);
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_DATA_Management DATA Management
* @{
*/
/**
* @brief Read 8-Bits in the data register
* @rmtoll DR DR LL_SPI_ReceiveData8
* @param SPIx SPI Instance
* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
{
return (*((__IO uint8_t *)&SPIx->DR));
}
/**
* @brief Read 16-Bits in the data register
* @rmtoll DR DR LL_SPI_ReceiveData16
* @param SPIx SPI Instance
* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
{
return (uint16_t)(READ_REG(SPIx->DR));
}
/**
* @brief Write 8-Bits in the data register
* @rmtoll DR DR LL_SPI_TransmitData8
* @param SPIx SPI Instance
* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
{
#if defined (__GNUC__)
__IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
*spidr = TxData;
#else
*((__IO uint8_t *)&SPIx->DR) = TxData;
#endif /* __GNUC__ */
}
/**
* @brief Write 16-Bits in the data register
* @rmtoll DR DR LL_SPI_TransmitData16
* @param SPIx SPI Instance
* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{
#if defined (__GNUC__)
__IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
*spidr = TxData;
#else
SPIx->DR = TxData;
#endif /* __GNUC__ */
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#if defined(SPI_I2S_SUPPORT)
/** @defgroup I2S_LL I2S
* @{
*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
* @{
*/
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_LL_EC_MODE
This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_LL_EC_STANDARD
This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_LL_EC_POLARITY
This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
} LL_I2S_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
* @{
*/
/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_I2S_ReadReg function
* @{
*/
#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
/**
* @}
*/
/** @defgroup SPI_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
* @{
*/
#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
/**
* @}
*/
/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
* @{
*/
#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
/**
* @}
*/
/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
* @{
*/
#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
/**
* @}
*/
/** @defgroup I2S_LL_EC_STANDARD I2s Standard
* @{
*/
#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
/**
* @}
*/
/** @defgroup I2S_LL_EC_MODE Operation Mode
* @{
*/
#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
/**
* @}
*/
/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
* @{
*/
#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
* @{
*/
#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
/**
* @}
*/
/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
* @{
*/
#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
* @{
*/
/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in I2S register
* @param __INSTANCE__ I2S Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in I2S register
* @param __INSTANCE__ I2S Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
* @{
*/
/** @defgroup I2S_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Select I2S mode and Enable I2S peripheral
* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
* I2SCFGR I2SE LL_I2S_Enable
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
}
/**
* @brief Disable I2S peripheral
* @rmtoll I2SCFGR I2SE LL_I2S_Disable
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
}
/**
* @brief Check if I2S peripheral is enabled
* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
}
/**
* @brief Set I2S data frame length
* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
* I2SCFGR CHLEN LL_I2S_SetDataFormat
* @param SPIx SPI Instance
* @param DataFormat This parameter can be one of the following values:
* @arg @ref LL_I2S_DATAFORMAT_16B
* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
* @arg @ref LL_I2S_DATAFORMAT_24B
* @arg @ref LL_I2S_DATAFORMAT_32B
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
{
MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
}
/**
* @brief Get I2S data frame length
* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
* I2SCFGR CHLEN LL_I2S_GetDataFormat
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2S_DATAFORMAT_16B
* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
* @arg @ref LL_I2S_DATAFORMAT_24B
* @arg @ref LL_I2S_DATAFORMAT_32B
*/
__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
}
/**
* @brief Set I2S clock polarity
* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
* @param SPIx SPI Instance
* @param ClockPolarity This parameter can be one of the following values:
* @arg @ref LL_I2S_POLARITY_LOW
* @arg @ref LL_I2S_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
{
SET_BIT(SPIx->I2SCFGR, ClockPolarity);
}
/**
* @brief Get I2S clock polarity
* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2S_POLARITY_LOW
* @arg @ref LL_I2S_POLARITY_HIGH
*/
__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
}
/**
* @brief Set I2S standard protocol
* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
* I2SCFGR PCMSYNC LL_I2S_SetStandard
* @param SPIx SPI Instance
* @param Standard This parameter can be one of the following values:
* @arg @ref LL_I2S_STANDARD_PHILIPS
* @arg @ref LL_I2S_STANDARD_MSB
* @arg @ref LL_I2S_STANDARD_LSB
* @arg @ref LL_I2S_STANDARD_PCM_SHORT
* @arg @ref LL_I2S_STANDARD_PCM_LONG
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
{
MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
}
/**
* @brief Get I2S standard protocol
* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
* I2SCFGR PCMSYNC LL_I2S_GetStandard
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2S_STANDARD_PHILIPS
* @arg @ref LL_I2S_STANDARD_MSB
* @arg @ref LL_I2S_STANDARD_LSB
* @arg @ref LL_I2S_STANDARD_PCM_SHORT
* @arg @ref LL_I2S_STANDARD_PCM_LONG
*/
__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
}
/**
* @brief Set I2S transfer mode
* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
* @param SPIx SPI Instance
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_I2S_MODE_SLAVE_TX
* @arg @ref LL_I2S_MODE_SLAVE_RX
* @arg @ref LL_I2S_MODE_MASTER_TX
* @arg @ref LL_I2S_MODE_MASTER_RX
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
{
MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
}
/**
* @brief Get I2S transfer mode
* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2S_MODE_SLAVE_TX
* @arg @ref LL_I2S_MODE_SLAVE_RX
* @arg @ref LL_I2S_MODE_MASTER_TX
* @arg @ref LL_I2S_MODE_MASTER_RX
*/
__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
}
/**
* @brief Set I2S linear prescaler
* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
* @param SPIx SPI Instance
* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
{
MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
}
/**
* @brief Get I2S linear prescaler
* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
* @param SPIx SPI Instance
* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
}
/**
* @brief Set I2S parity prescaler
* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
* @param SPIx SPI Instance
* @param PrescalerParity This parameter can be one of the following values:
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
{
MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
}
/**
* @brief Get I2S parity prescaler
* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
*/
__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
}
/**
* @brief Enable the master clock output (Pin MCK)
* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
}
/**
* @brief Disable the master clock output (Pin MCK)
* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
}
/**
* @brief Check if the master clock output (Pin MCK) is enabled
* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup I2S_LL_EF_FLAG FLAG Management
* @{
*/
/**
* @brief Check if Rx buffer is not empty
* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_RXNE(SPIx);
}
/**
* @brief Check if Tx buffer is empty
* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_TXE(SPIx);
}
/**
* @brief Get busy flag
* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_BSY(SPIx);
}
/**
* @brief Get overrun error flag
* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_OVR(SPIx);
}
/**
* @brief Get underrun error flag
* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
}
/**
* @brief Get channel side flag.
* @note 0: Channel Left has to be transmitted or has been received\n
* 1: Channel Right has to be transmitted or has been received\n
* It has no significance in PCM mode.
* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
}
/**
* @brief Clear overrun error flag
* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
{
LL_SPI_ClearFlag_OVR(SPIx);
}
/**
* @brief Clear underrun error flag
* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
{
__IO uint32_t tmpreg;
tmpreg = SPIx->SR;
(void)tmpreg;
}
/**
* @brief Clear frame format error flag
* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
{
LL_SPI_ClearFlag_FRE(SPIx);
}
/**
* @}
*/
/** @defgroup I2S_LL_EF_IT Interrupt Management
* @{
*/
/**
* @brief Enable error IT
* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
{
LL_SPI_EnableIT_ERR(SPIx);
}
/**
* @brief Enable Rx buffer not empty IT
* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
{
LL_SPI_EnableIT_RXNE(SPIx);
}
/**
* @brief Enable Tx buffer empty IT
* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
{
LL_SPI_EnableIT_TXE(SPIx);
}
/**
* @brief Disable error IT
* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
{
LL_SPI_DisableIT_ERR(SPIx);
}
/**
* @brief Disable Rx buffer not empty IT
* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
{
LL_SPI_DisableIT_RXNE(SPIx);
}
/**
* @brief Disable Tx buffer empty IT
* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
{
LL_SPI_DisableIT_TXE(SPIx);
}
/**
* @brief Check if ERR IT is enabled
* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_ERR(SPIx);
}
/**
* @brief Check if RXNE IT is enabled
* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_RXNE(SPIx);
}
/**
* @brief Check if TXE IT is enabled
* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_TXE(SPIx);
}
/**
* @}
*/
/** @defgroup I2S_LL_EF_DMA DMA Management
* @{
*/
/**
* @brief Enable DMA Rx
* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
{
LL_SPI_EnableDMAReq_RX(SPIx);
}
/**
* @brief Disable DMA Rx
* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
{
LL_SPI_DisableDMAReq_RX(SPIx);
}
/**
* @brief Check if DMA Rx is enabled
* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledDMAReq_RX(SPIx);
}
/**
* @brief Enable DMA Tx
* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
{
LL_SPI_EnableDMAReq_TX(SPIx);
}
/**
* @brief Disable DMA Tx
* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
{
LL_SPI_DisableDMAReq_TX(SPIx);
}
/**
* @brief Check if DMA Tx is enabled
* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledDMAReq_TX(SPIx);
}
/**
* @}
*/
/** @defgroup I2S_LL_EF_DATA DATA Management
* @{
*/
/**
* @brief Read 16-Bits in data register
* @rmtoll DR DR LL_I2S_ReceiveData16
* @param SPIx SPI Instance
* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
{
return LL_SPI_ReceiveData16(SPIx);
}
/**
* @brief Write 16-Bits in data register
* @rmtoll DR DR LL_I2S_TransmitData16
* @param SPIx SPI Instance
* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{
LL_SPI_TransmitData16(SPIx, TxData);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* SPI_I2S_SUPPORT */
#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_SPI_H */

2436
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c Normal file
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@@ -0,0 +1,2436 @@
/**
******************************************************************************
* @file stm32f1xx_hal_can.c
* @author MCD Application Team
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions
* + Configuration functions
* + Control functions
* + Interrupts management
* + Callbacks functions
* + Peripheral State and Error functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Initialize the CAN low level resources by implementing the
HAL_CAN_MspInit():
(++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
(++) Configure CAN pins
(+++) Enable the clock for the CAN GPIOs
(+++) Configure CAN pins as alternate function
(++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
(+++) Configure the CAN interrupt priority using
HAL_NVIC_SetPriority()
(+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In CAN IRQ handler, call HAL_CAN_IRQHandler()
(#) Initialize the CAN peripheral using HAL_CAN_Init() function. This
function resorts to HAL_CAN_MspInit() for low-level initialization.
(#) Configure the reception filters using the following configuration
functions:
(++) HAL_CAN_ConfigFilter()
(#) Start the CAN module using HAL_CAN_Start() function. At this level
the node is active on the bus: it receive messages, and can send
messages.
(#) To manage messages transmission, the following Tx control functions
can be used:
(++) HAL_CAN_AddTxMessage() to request transmission of a new
message.
(++) HAL_CAN_AbortTxRequest() to abort transmission of a pending
message.
(++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx
mailboxes.
(++) HAL_CAN_IsTxMessagePending() to check if a message is pending
in a Tx mailbox.
(++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message
sent, if time triggered communication mode is enabled.
(#) When a message is received into the CAN Rx FIFOs, it can be retrieved
using the HAL_CAN_GetRxMessage() function. The function
HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are
stored in the Rx Fifo.
(#) Calling the HAL_CAN_Stop() function stops the CAN module.
(#) The deinitialization is achieved with HAL_CAN_DeInit() function.
*** Polling mode operation ***
==============================
[..]
(#) Reception:
(++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel()
until at least one message is received.
(++) Then get the message using HAL_CAN_GetRxMessage().
(#) Transmission:
(++) Monitor the Tx mailboxes availability until at least one Tx
mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel().
(++) Then request transmission of a message using
HAL_CAN_AddTxMessage().
*** Interrupt mode operation ***
================================
[..]
(#) Notifications are activated using HAL_CAN_ActivateNotification()
function. Then, the process can be controlled through the
available user callbacks: HAL_CAN_xxxCallback(), using same APIs
HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage().
(#) Notifications can be deactivated using
HAL_CAN_DeactivateNotification() function.
(#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and
CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig
the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and
HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options
here.
(++) Directly get the Rx message in the callback, using
HAL_CAN_GetRxMessage().
(++) Or deactivate the notification in the callback without
getting the Rx message. The Rx message can then be got later
using HAL_CAN_GetRxMessage(). Once the Rx message have been
read, the notification can be activated again.
*** Sleep mode ***
==================
[..]
(#) The CAN peripheral can be put in sleep mode (low power), using
HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the
current CAN activity (transmission or reception of a CAN frame) will
be completed.
(#) A notification can be activated to be informed when the sleep mode
will be entered.
(#) It can be checked if the sleep mode is entered using
HAL_CAN_IsSleepActive().
Note that the CAN state (accessible from the API HAL_CAN_GetState())
is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is
submitted (the sleep mode is not yet entered), and become
HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
(#) The wake-up from sleep mode can be triggered by two ways:
(++) Using HAL_CAN_WakeUp(). When returning from this function,
the sleep mode is exited (if return status is HAL_OK).
(++) When a start of Rx CAN frame is detected by the CAN peripheral,
if automatic wake up mode is enabled.
*** Callback registration ***
=============================================
The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function HAL_CAN_RegisterCallback() to register an interrupt callback.
Function HAL_CAN_RegisterCallback() allows to register following callbacks:
(+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback.
(+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback.
(+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback.
(+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback.
(+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback.
(+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback.
(+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback.
(+) RxFifo0FullCallback : Rx Fifo 0 Full Callback.
(+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback.
(+) RxFifo1FullCallback : Rx Fifo 1 Full Callback.
(+) SleepCallback : Sleep Callback.
(+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback.
(+) ErrorCallback : Error Callback.
(+) MspInitCallback : CAN MspInit.
(+) MspDeInitCallback : CAN MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default
weak function.
HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback.
(+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback.
(+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback.
(+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback.
(+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback.
(+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback.
(+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback.
(+) RxFifo0FullCallback : Rx Fifo 0 Full Callback.
(+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback.
(+) RxFifo1FullCallback : Rx Fifo 1 Full Callback.
(+) SleepCallback : Sleep Callback.
(+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback.
(+) ErrorCallback : Error Callback.
(+) MspInitCallback : CAN MspInit.
(+) MspDeInitCallback : CAN MspDeInit.
By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET,
all callbacks are set to the corresponding weak functions:
example HAL_CAN_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when
these callbacks are null (not registered beforehand).
if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit()
or HAL_CAN_Init() function.
When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#if defined(CAN1)
/** @defgroup CAN CAN
* @brief CAN driver modules
* @{
*/
#ifdef HAL_CAN_MODULE_ENABLED
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
#define CAN_TIMEOUT_VALUE 10U
#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) HAL_CAN_Init : Initialize and configure the CAN.
(+) HAL_CAN_DeInit : De-initialize the CAN.
(+) HAL_CAN_MspInit : Initialize the CAN MSP.
(+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP.
@endverbatim
* @{
*/
/**
* @brief Initializes the CAN peripheral according to the specified
* parameters in the CAN_InitStruct.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));
assert_param(IS_CAN_MODE(hcan->Init.Mode));
assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));
assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
if (hcan->State == HAL_CAN_STATE_RESET)
{
/* Reset callbacks to legacy functions */
hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */
hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */
hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */
hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */
hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */
hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */
hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */
hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */
hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */
hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */
hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */
hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */
hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */
if (hcan->MspInitCallback == NULL)
{
hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware: CLOCK, NVIC */
hcan->MspInitCallback(hcan);
}
#else
if (hcan->State == HAL_CAN_STATE_RESET)
{
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait initialisation acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
return HAL_ERROR;
}
}
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
/* Get tick */
tickstart = HAL_GetTick();
/* Check Sleep mode leave acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
return HAL_ERROR;
}
}
/* Set the time triggered communication mode */
if (hcan->Init.TimeTriggeredMode == ENABLE)
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
}
/* Set the automatic bus-off management */
if (hcan->Init.AutoBusOff == ENABLE)
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
}
/* Set the automatic wake-up mode */
if (hcan->Init.AutoWakeUp == ENABLE)
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
}
/* Set the automatic retransmission */
if (hcan->Init.AutoRetransmission == ENABLE)
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
}
else
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
}
/* Set the receive FIFO locked mode */
if (hcan->Init.ReceiveFifoLocked == ENABLE)
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
}
/* Set the transmit FIFO priority */
if (hcan->Init.TransmitFifoPriority == ENABLE)
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
}
/* Set the bit timing register */
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
hcan->Init.SyncJumpWidth |
hcan->Init.TimeSeg1 |
hcan->Init.TimeSeg2 |
(hcan->Init.Prescaler - 1U)));
/* Initialize the error code */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Deinitializes the CAN peripheral registers to their default
* reset values.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
{
/* Check CAN handle */
if (hcan == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
/* Stop the CAN module */
(void)HAL_CAN_Stop(hcan);
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
if (hcan->MspDeInitCallback == NULL)
{
hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: CLOCK, NVIC */
hcan->MspDeInitCallback(hcan);
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
/* Reset the CAN ErrorCode */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Change CAN state */
hcan->State = HAL_CAN_STATE_RESET;
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the CAN MSP.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the CAN MSP.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_MspDeInit could be implemented in the user file
*/
}
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/**
* @brief Register a CAN CallBack.
* To be used instead of the weak predefined callback
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for CAN module
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID
* @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID
* @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID
* @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID
* @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID
* @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID
* @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID
* @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID
* @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID
* @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID
* @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID
* @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID
* @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID,
void (* pCallback)(CAN_HandleTypeDef *_hcan))
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hcan->State == HAL_CAN_STATE_READY)
{
switch (CallbackID)
{
case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
hcan->TxMailbox0CompleteCallback = pCallback;
break;
case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
hcan->TxMailbox1CompleteCallback = pCallback;
break;
case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
hcan->TxMailbox2CompleteCallback = pCallback;
break;
case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
hcan->TxMailbox0AbortCallback = pCallback;
break;
case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
hcan->TxMailbox1AbortCallback = pCallback;
break;
case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
hcan->TxMailbox2AbortCallback = pCallback;
break;
case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
hcan->RxFifo0MsgPendingCallback = pCallback;
break;
case HAL_CAN_RX_FIFO0_FULL_CB_ID :
hcan->RxFifo0FullCallback = pCallback;
break;
case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
hcan->RxFifo1MsgPendingCallback = pCallback;
break;
case HAL_CAN_RX_FIFO1_FULL_CB_ID :
hcan->RxFifo1FullCallback = pCallback;
break;
case HAL_CAN_SLEEP_CB_ID :
hcan->SleepCallback = pCallback;
break;
case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
hcan->WakeUpFromRxMsgCallback = pCallback;
break;
case HAL_CAN_ERROR_CB_ID :
hcan->ErrorCallback = pCallback;
break;
case HAL_CAN_MSPINIT_CB_ID :
hcan->MspInitCallback = pCallback;
break;
case HAL_CAN_MSPDEINIT_CB_ID :
hcan->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hcan->State == HAL_CAN_STATE_RESET)
{
switch (CallbackID)
{
case HAL_CAN_MSPINIT_CB_ID :
hcan->MspInitCallback = pCallback;
break;
case HAL_CAN_MSPDEINIT_CB_ID :
hcan->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a CAN CallBack.
* CAN callback is redirected to the weak predefined callback
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for CAN module
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID
* @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID
* @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID
* @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID
* @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID
* @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID
* @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID
* @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID
* @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID
* @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID
* @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID
* @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID
* @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (hcan->State == HAL_CAN_STATE_READY)
{
switch (CallbackID)
{
case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback;
break;
case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback;
break;
case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback;
break;
case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback;
break;
case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback;
break;
case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback;
break;
case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback;
break;
case HAL_CAN_RX_FIFO0_FULL_CB_ID :
hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback;
break;
case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback;
break;
case HAL_CAN_RX_FIFO1_FULL_CB_ID :
hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback;
break;
case HAL_CAN_SLEEP_CB_ID :
hcan->SleepCallback = HAL_CAN_SleepCallback;
break;
case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback;
break;
case HAL_CAN_ERROR_CB_ID :
hcan->ErrorCallback = HAL_CAN_ErrorCallback;
break;
case HAL_CAN_MSPINIT_CB_ID :
hcan->MspInitCallback = HAL_CAN_MspInit;
break;
case HAL_CAN_MSPDEINIT_CB_ID :
hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
break;
default :
/* Update the error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hcan->State == HAL_CAN_STATE_RESET)
{
switch (CallbackID)
{
case HAL_CAN_MSPINIT_CB_ID :
hcan->MspInitCallback = HAL_CAN_MspInit;
break;
case HAL_CAN_MSPDEINIT_CB_ID :
hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
break;
default :
/* Update the error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
* @brief Configuration functions.
*
@verbatim
==============================================================================
##### Configuration functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) HAL_CAN_ConfigFilter : Configure the CAN reception filters
@endverbatim
* @{
*/
/**
* @brief Configures the CAN reception filter according to the specified
* parameters in the CAN_FilterInitStruct.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
* contains the filter configuration information.
* @retval None
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig)
{
uint32_t filternbrbitpos;
CAN_TypeDef *can_ip = hcan->Instance;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Check the parameters */
assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));
assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));
assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));
assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation));
#if defined(CAN2)
/* CAN1 and CAN2 are dual instances with 28 common filters banks */
/* Select master instance to access the filter banks */
can_ip = CAN1;
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
#else
/* CAN1 is single instance with 14 dedicated filters banks */
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
#endif /* CAN3 */
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
#if defined(CAN2)
/* Select the start filter number of CAN2 slave instance */
CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
#endif /* CAN3 */
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
/* Filter Deactivation */
CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
{
/* 16-bit scale for the filter */
CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
{
/* 32-bit scale for the filter */
SET_BIT(can_ip->FS1R, filternbrbitpos);
/* 32-bit identifier or First 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
/* 32-bit mask or Second 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
}
/* Filter Mode */
if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
{
/* Id/Mask mode for the filter*/
CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
}
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
/* Identifier list mode for the filter*/
SET_BIT(can_ip->FM1R, filternbrbitpos);
}
/* Filter FIFO assignment */
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
{
/* FIFO 0 assignation for the filter */
CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
}
else
{
/* FIFO 1 assignation for the filter */
SET_BIT(can_ip->FFA1R, filternbrbitpos);
}
/* Filter activation */
if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
{
SET_BIT(can_ip->FA1R, filternbrbitpos);
}
/* Leave the initialisation mode for the filter */
CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @}
*/
/** @defgroup CAN_Exported_Functions_Group3 Control functions
* @brief Control functions
*
@verbatim
==============================================================================
##### Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) HAL_CAN_Start : Start the CAN module
(+) HAL_CAN_Stop : Stop the CAN module
(+) HAL_CAN_RequestSleep : Request sleep mode entry.
(+) HAL_CAN_WakeUp : Wake up from sleep mode.
(+) HAL_CAN_IsSleepActive : Check is sleep mode is active.
(+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes
and activate the corresponding
transmission request
(+) HAL_CAN_AbortTxRequest : Abort transmission request
(+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level
(+) HAL_CAN_IsTxMessagePending : Check if a transmission request is
pending on the selected Tx mailbox
(+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO
(+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level
@endverbatim
* @{
*/
/**
* @brief Start the CAN module.
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_READY)
{
/* Change CAN peripheral state */
hcan->State = HAL_CAN_STATE_LISTENING;
/* Request leave initialisation */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
return HAL_ERROR;
}
}
/* Reset the CAN ErrorCode */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Stop the CAN module and enable access to configuration registers.
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
{
uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_LISTENING)
{
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
return HAL_ERROR;
}
}
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
/* Change CAN peripheral state */
hcan->State = HAL_CAN_STATE_READY;
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;
return HAL_ERROR;
}
}
/**
* @brief Request the sleep mode (low power) entry.
* When returning from this function, Sleep mode will be entered
* as soon as the current CAN activity (transmission or reception
* of a CAN frame) has been completed.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
{
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Request Sleep mode */
SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
/* Return function status */
return HAL_ERROR;
}
}
/**
* @brief Wake up from sleep mode.
* When returning with HAL_OK status from this function, Sleep mode
* is exited.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Wake up request */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
/* Wait sleep mode is exited */
do
{
/* Increment counter */
count++;
/* Check if timeout is reached */
if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
return HAL_ERROR;
}
} while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @brief Check is sleep mode is active.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval Status
* - 0 : Sleep mode is not active.
* - 1 : Sleep mode is active.
*/
uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan)
{
uint32_t status = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Check Sleep mode */
if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
status = 1U;
}
}
/* Return function status */
return status;
}
/**
* @brief Add a message to the first free Tx mailbox and activate the
* corresponding transmission request.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @param pHeader pointer to a CAN_TxHeaderTypeDef structure.
* @param aData array containing the payload of the Tx frame.
* @param pTxMailbox pointer to a variable where the function will return
* the TxMailbox used to store the Tx message.
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
const uint8_t aData[], uint32_t *pTxMailbox)
{
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
uint32_t tsr = READ_REG(hcan->Instance->TSR);
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(pHeader->IDE));
assert_param(IS_CAN_RTR(pHeader->RTR));
assert_param(IS_CAN_DLC(pHeader->DLC));
if (pHeader->IDE == CAN_ID_STD)
{
assert_param(IS_CAN_STDID(pHeader->StdId));
}
else
{
assert_param(IS_CAN_EXTID(pHeader->ExtId));
}
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Check that all the Tx mailboxes are not full */
if (((tsr & CAN_TSR_TME0) != 0U) ||
((tsr & CAN_TSR_TME1) != 0U) ||
((tsr & CAN_TSR_TME2) != 0U))
{
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
/* Set up the Id */
if (pHeader->IDE == CAN_ID_STD)
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
pHeader->RTR);
}
else
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
pHeader->IDE |
pHeader->RTR);
}
/* Set up the DLC */
hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
/* Set up the Transmit Global Time mode */
if (pHeader->TransmitGlobalTime == ENABLE)
{
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
}
/* Set up the data field */
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |
((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
return HAL_ERROR;
}
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @brief Abort transmission requests
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @param TxMailboxes List of the Tx Mailboxes to abort.
* This parameter can be any combination of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
{
HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Check Tx Mailbox 0 */
if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U)
{
/* Add cancellation request for Tx Mailbox 0 */
SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
}
/* Check Tx Mailbox 1 */
if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U)
{
/* Add cancellation request for Tx Mailbox 1 */
SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
}
/* Check Tx Mailbox 2 */
if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U)
{
/* Add cancellation request for Tx Mailbox 2 */
SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
}
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @brief Return Tx Mailboxes free level: number of free Tx Mailboxes.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval Number of free Tx Mailboxes.
*/
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan)
{
uint32_t freelevel = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Check Tx Mailbox 0 status */
if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U)
{
freelevel++;
}
/* Check Tx Mailbox 1 status */
if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U)
{
freelevel++;
}
/* Check Tx Mailbox 2 status */
if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U)
{
freelevel++;
}
}
/* Return Tx Mailboxes free level */
return freelevel;
}
/**
* @brief Check if a transmission request is pending on the selected Tx
* Mailboxes.
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @param TxMailboxes List of Tx Mailboxes to check.
* This parameter can be any combination of @arg CAN_Tx_Mailboxes.
* @retval Status
* - 0 : No pending transmission request on any selected Tx Mailboxes.
* - 1 : Pending transmission request on at least one of the selected
* Tx Mailbox.
*/
uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
{
uint32_t status = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Check pending transmission request on the selected Tx Mailboxes */
if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
{
status = 1U;
}
}
/* Return status */
return status;
}
/**
* @brief Return timestamp of Tx message sent, if time triggered communication
mode is enabled.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @param TxMailbox Tx Mailbox where the timestamp of message sent will be
* read.
* This parameter can be one value of @arg CAN_Tx_Mailboxes.
* @retval Timestamp of message sent from Tx Mailbox.
*/
uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
{
uint32_t timestamp = 0U;
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Select the Tx mailbox */
transmitmailbox = POSITION_VAL(TxMailbox);
/* Get timestamp */
timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;
}
/* Return the timestamp */
return timestamp;
}
/**
* @brief Get an CAN frame from the Rx FIFO zone into the message RAM.
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @param RxFifo Fifo number of the received message to be read.
* This parameter can be a value of @arg CAN_receive_FIFO_number.
* @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header
* of the Rx frame will be stored.
* @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
HAL_CAN_StateTypeDef state = hcan->State;
assert_param(IS_CAN_RX_FIFO(RxFifo));
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Check the Rx FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
{
/* Check that the Rx FIFO 0 is not empty */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
return HAL_ERROR;
}
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
return HAL_ERROR;
}
}
/* Get the header */
pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
if (pHeader->IDE == CAN_ID_STD)
{
pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
}
else
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
{
/* Truncate DLC to 8 if received field is over range */
pHeader->DLC = 8U;
}
else
{
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
}
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
/* Get the data */
aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
/* Release the FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
{
/* Release RX FIFO 0 */
SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Release RX FIFO 1 */
SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
}
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @brief Return Rx FIFO fill level.
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @param RxFifo Rx FIFO.
* This parameter can be a value of @arg CAN_receive_FIFO_number.
* @retval Number of messages available in Rx FIFO.
*/
uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo)
{
uint32_t filllevel = 0U;
HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_RX_FIFO(RxFifo));
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
if (RxFifo == CAN_RX_FIFO0)
{
filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
}
else /* RxFifo == CAN_RX_FIFO1 */
{
filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
}
}
/* Return Rx FIFO fill level */
return filllevel;
}
/**
* @}
*/
/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
* @brief Interrupts management
*
@verbatim
==============================================================================
##### Interrupts management #####
==============================================================================
[..] This section provides functions allowing to:
(+) HAL_CAN_ActivateNotification : Enable interrupts
(+) HAL_CAN_DeactivateNotification : Disable interrupts
(+) HAL_CAN_IRQHandler : Handles CAN interrupt request
@endverbatim
* @{
*/
/**
* @brief Enable interrupts.
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @param ActiveITs indicates which interrupts will be enabled.
* This parameter can be any combination of @arg CAN_Interrupts.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
{
HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_IT(ActiveITs));
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Enable the selected interrupts */
__HAL_CAN_ENABLE_IT(hcan, ActiveITs);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @brief Disable interrupts.
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @param InactiveITs indicates which interrupts will be disabled.
* This parameter can be any combination of @arg CAN_Interrupts.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
{
HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_IT(InactiveITs));
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Disable the selected interrupts */
__HAL_CAN_DISABLE_IT(hcan, InactiveITs);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @brief Handles CAN interrupt request
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
{
uint32_t errorcode = HAL_CAN_ERROR_NONE;
uint32_t interrupts = READ_REG(hcan->Instance->IER);
uint32_t msrflags = READ_REG(hcan->Instance->MSR);
uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
uint32_t esrflags = READ_REG(hcan->Instance->ESR);
/* Transmit Mailbox empty interrupt management *****************************/
if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
{
/* Transmit Mailbox 0 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP0) != 0U)
{
/* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
if ((tsrflags & CAN_TSR_TXOK0) != 0U)
{
/* Transmission Mailbox 0 complete callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0CompleteCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST0) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST0;
}
else if ((tsrflags & CAN_TSR_TERR0) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR0;
}
else
{
/* Transmission Mailbox 0 abort callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0AbortCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
/* Transmit Mailbox 1 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP1) != 0U)
{
/* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
if ((tsrflags & CAN_TSR_TXOK1) != 0U)
{
/* Transmission Mailbox 1 complete callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1CompleteCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST1) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST1;
}
else if ((tsrflags & CAN_TSR_TERR1) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR1;
}
else
{
/* Transmission Mailbox 1 abort callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1AbortCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
/* Transmit Mailbox 2 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP2) != 0U)
{
/* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
if ((tsrflags & CAN_TSR_TXOK2) != 0U)
{
/* Transmission Mailbox 2 complete callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2CompleteCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST2) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST2;
}
else if ((tsrflags & CAN_TSR_TERR2) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR2;
}
else
{
/* Transmission Mailbox 2 abort callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2AbortCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
}
/* Receive FIFO 0 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
{
if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
{
/* Set CAN error code to Rx Fifo 0 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV0;
/* Clear FIFO0 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
}
}
/* Receive FIFO 0 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
{
if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
{
/* Clear FIFO 0 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
/* Receive FIFO 0 full Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0FullCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 0 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
{
/* Check if message is still pending */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
{
/* Receive FIFO 0 message pending Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0MsgPendingCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
{
if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
{
/* Set CAN error code to Rx Fifo 1 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV1;
/* Clear FIFO1 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
}
}
/* Receive FIFO 1 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
{
if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
{
/* Clear FIFO 1 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
/* Receive FIFO 1 full Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1FullCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
{
/* Check if message is still pending */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
{
/* Receive FIFO 1 message pending Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1MsgPendingCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Sleep interrupt management *********************************************/
if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
{
if ((msrflags & CAN_MSR_SLAKI) != 0U)
{
/* Clear Sleep interrupt Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
/* Sleep Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->SleepCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_SleepCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* WakeUp interrupt management *********************************************/
if ((interrupts & CAN_IT_WAKEUP) != 0U)
{
if ((msrflags & CAN_MSR_WKUI) != 0U)
{
/* Clear WakeUp Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
/* WakeUp Callback */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->WakeUpFromRxMsgCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_WakeUpFromRxMsgCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Error interrupts management *********************************************/
if ((interrupts & CAN_IT_ERROR) != 0U)
{
if ((msrflags & CAN_MSR_ERRI) != 0U)
{
/* Check Error Warning Flag */
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
((esrflags & CAN_ESR_EWGF) != 0U))
{
/* Set CAN error code to Error Warning */
errorcode |= HAL_CAN_ERROR_EWG;
/* No need for clear of Error Warning Flag as read-only */
}
/* Check Error Passive Flag */
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
((esrflags & CAN_ESR_EPVF) != 0U))
{
/* Set CAN error code to Error Passive */
errorcode |= HAL_CAN_ERROR_EPV;
/* No need for clear of Error Passive Flag as read-only */
}
/* Check Bus-off Flag */
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
((esrflags & CAN_ESR_BOFF) != 0U))
{
/* Set CAN error code to Bus-Off */
errorcode |= HAL_CAN_ERROR_BOF;
/* No need for clear of Error Bus-Off as read-only */
}
/* Check Last Error Code Flag */
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
((esrflags & CAN_ESR_LEC) != 0U))
{
switch (esrflags & CAN_ESR_LEC)
{
case (CAN_ESR_LEC_0):
/* Set CAN error code to Stuff error */
errorcode |= HAL_CAN_ERROR_STF;
break;
case (CAN_ESR_LEC_1):
/* Set CAN error code to Form error */
errorcode |= HAL_CAN_ERROR_FOR;
break;
case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
/* Set CAN error code to Acknowledgement error */
errorcode |= HAL_CAN_ERROR_ACK;
break;
case (CAN_ESR_LEC_2):
/* Set CAN error code to Bit recessive error */
errorcode |= HAL_CAN_ERROR_BR;
break;
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
/* Set CAN error code to Bit Dominant error */
errorcode |= HAL_CAN_ERROR_BD;
break;
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
/* Set CAN error code to CRC error */
errorcode |= HAL_CAN_ERROR_CRC;
break;
default:
break;
}
/* Clear Last error code Flag */
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
}
}
/* Clear ERRI Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
}
/* Call the Error call Back in case of Errors */
if (errorcode != HAL_CAN_ERROR_NONE)
{
/* Update error code in handle */
hcan->ErrorCode |= errorcode;
/* Call Error callback function */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->ErrorCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/**
* @}
*/
/** @defgroup CAN_Exported_Functions_Group5 Callback functions
* @brief CAN Callback functions
*
@verbatim
==============================================================================
##### Callback functions #####
==============================================================================
[..]
This subsection provides the following callback functions:
(+) HAL_CAN_TxMailbox0CompleteCallback
(+) HAL_CAN_TxMailbox1CompleteCallback
(+) HAL_CAN_TxMailbox2CompleteCallback
(+) HAL_CAN_TxMailbox0AbortCallback
(+) HAL_CAN_TxMailbox1AbortCallback
(+) HAL_CAN_TxMailbox2AbortCallback
(+) HAL_CAN_RxFifo0MsgPendingCallback
(+) HAL_CAN_RxFifo0FullCallback
(+) HAL_CAN_RxFifo1MsgPendingCallback
(+) HAL_CAN_RxFifo1FullCallback
(+) HAL_CAN_SleepCallback
(+) HAL_CAN_WakeUpFromRxMsgCallback
(+) HAL_CAN_ErrorCallback
@endverbatim
* @{
*/
/**
* @brief Transmission Mailbox 0 complete callback.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
user file
*/
}
/**
* @brief Transmission Mailbox 1 complete callback.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
user file
*/
}
/**
* @brief Transmission Mailbox 2 complete callback.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
user file
*/
}
/**
* @brief Transmission Mailbox 0 Cancellation callback.
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
user file
*/
}
/**
* @brief Transmission Mailbox 1 Cancellation callback.
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
user file
*/
}
/**
* @brief Transmission Mailbox 2 Cancellation callback.
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
user file
*/
}
/**
* @brief Rx FIFO 0 message pending callback.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
user file
*/
}
/**
* @brief Rx FIFO 0 full callback.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo0FullCallback could be implemented in the user
file
*/
}
/**
* @brief Rx FIFO 1 message pending callback.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
user file
*/
}
/**
* @brief Rx FIFO 1 full callback.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1FullCallback could be implemented in the user
file
*/
}
/**
* @brief Sleep callback.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_SleepCallback could be implemented in the user file
*/
}
/**
* @brief WakeUp from Rx message callback.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
user file
*/
}
/**
* @brief Error CAN callback.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
* @brief CAN Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
==============================================================================
[..]
This subsection provides functions allowing to :
(+) HAL_CAN_GetState() : Return the CAN state.
(+) HAL_CAN_GetError() : Return the CAN error codes if any.
(+) HAL_CAN_ResetError(): Reset the CAN error codes if any.
@endverbatim
* @{
*/
/**
* @brief Return the CAN state.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL state
*/
HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan)
{
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Check sleep mode acknowledge flag */
if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
/* Sleep mode is active */
state = HAL_CAN_STATE_SLEEP_ACTIVE;
}
/* Check sleep mode request flag */
else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U)
{
/* Sleep mode request is pending */
state = HAL_CAN_STATE_SLEEP_PENDING;
}
else
{
/* Neither sleep mode request nor sleep mode acknowledge */
}
}
/* Return CAN state */
return state;
}
/**
* @brief Return the CAN error code.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval CAN Error Code
*/
uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan)
{
/* Return CAN error code */
return hcan->ErrorCode;
}
/**
* @brief Reset the CAN error code.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
(state == HAL_CAN_STATE_LISTENING))
{
/* Reset CAN error code */
hcan->ErrorCode = 0U;
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
status = HAL_ERROR;
}
/* Return the status */
return status;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CAN_MODULE_ENABLED */
/**
* @}
*/
#endif /* CAN1 */
/**
* @}
*/

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/**
******************************************************************************
* @file stm32f1xx_hal_rtc.c
* @author MCD Application Team
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
* + Initialization and de-initialization functions
* + RTC Time and Date functions
* + RTC Alarm functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(+) Enable the RTC domain access (see description in the section above).
(+) Configure the RTC Prescaler (Asynchronous prescaler to generate RTC 1Hz time base)
using the HAL_RTC_Init() function.
*** Time and Date configuration ***
===================================
[..]
(+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
and HAL_RTC_SetDate() functions.
(+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
*** Alarm configuration ***
===========================
[..]
(+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
(+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
*** Tamper configuration ***
============================
[..]
(+) Enable the RTC Tamper and configure the Tamper Level using the
HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
mode using HAL_RTCEx_SetTamper_IT() function.
(+) The TAMPER1 alternate function can be mapped to PC13
*** Backup Data Registers configuration ***
===========================================
[..]
(+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
function.
(+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
function.
##### WARNING: Drivers Restrictions #####
==================================================================
[..] RTC version used on STM32F1 families is version V1. All the features supported by V2
(other families) will be not supported on F1.
[..] As on V2, main RTC features are managed by HW. But on F1, date feature is completely
managed by SW.
[..] Then, there are some restrictions compared to other families:
(+) Only format 24 hours supported in HAL (format 12 hours not supported)
(+) Date is saved in SRAM. Then, when MCU is in STOP or STANDBY mode, date will be lost.
User should implement a way to save date before entering in low power mode (an
example is provided with firmware package based on backup registers)
(+) Date is automatically updated each time a HAL_RTC_GetTime or HAL_RTC_GetDate is called.
(+) Alarm detection is limited to 1 day. It will expire only 1 time (no alarm repetition, need
to program a new alarm)
##### Backup Domain Operating Condition #####
==============================================================================
[..] The real-time clock (RTC) and the RTC backup registers can be powered
from the VBAT voltage when the main VDD supply is powered off.
To retain the content of the RTC backup registers and supply the RTC
when VDD is turned off, VBAT pin can be connected to an optional
standby voltage supplied by a battery or by another source.
[..] To allow the RTC operating even when the main digital supply (VDD) is turned
off, the VBAT pin powers the following blocks:
(#) The RTC
(#) The LSE oscillator
(#) The backup SRAM when the low power backup regulator is enabled
(#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
[..] When the backup domain is supplied by VDD (analog switch connected to VDD),
the following pins are available:
(+) PC13 can be used as a Tamper pin
[..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
because VDD is not present), the following pins are available:
(+) PC13 can be used as the Tamper pin
##### Backup Domain Reset #####
==================================================================
[..] The backup domain reset sets all RTC registers and the RCC_BDCR register
to their reset values.
[..] A backup domain reset is generated when one of the following events occurs:
(#) Software reset, triggered by setting the BDRST bit in the
RCC Backup domain control register (RCC_BDCR).
(#) VDD or VBAT power on, if both supplies have previously been powered off.
(#) Tamper detection event resets all data backup registers.
##### Backup Domain Access #####
==================================================================
[..] After reset, the backup domain (RTC registers, RTC backup data
registers and backup SRAM) is protected against possible unwanted write
accesses.
[..] To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Call the function HAL_RCCEx_PeriphCLKConfig in using RCC_PERIPHCLK_RTC for
PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSE)
(+) Enable the BKP clock in using __HAL_RCC_BKP_CLK_ENABLE()
##### RTC and low power modes #####
==================================================================
[..] The MCU can be woken up from a low power mode by an RTC alternate
function.
[..] The RTC alternate functions are the RTC alarms (Alarm A),
and RTC tamper event detection.
These RTC alternate functions can wake up the system from the Stop and
Standby low power modes.
[..] The system can also wake up from low power modes without depending
on an external interrupt (Auto-wakeup mode), by using the RTC alarm.
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
[..]
Function HAL_RTC_RegisterCallback() allows to register following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
(+) Tamper1EventCallback : RTC Tamper 1 Event callback.
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
[..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
weak function.
HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
(+) Tamper1EventCallback : RTC Tamper 1 Event callback.
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
[..]
By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
all callbacks are set to the corresponding weak functions :
example AlarmAEventCallback().
Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
(not registered beforehand).
If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
[..]
Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
or HAL_RTC_Init() function.
[..]
When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup RTC RTC
* @brief RTC HAL module driver
* @{
*/
#ifdef HAL_RTC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup RTC_Private_Constants RTC Private Constants
* @{
*/
#define RTC_ALARM_RESETVALUE_REGISTER (uint16_t)0xFFFF
#define RTC_ALARM_RESETVALUE 0xFFFFFFFFU
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
*/
static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc);
static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter);
static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef *hrtc);
static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter);
static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
static uint8_t RTC_ByteToBcd2(uint8_t Value);
static uint8_t RTC_Bcd2ToByte(uint8_t Value);
static uint8_t RTC_IsLeapYear(uint16_t nYear);
static void RTC_DateUpdate(RTC_HandleTypeDef *hrtc, uint32_t DayElapsed);
static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay);
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to initialize and configure the
RTC Prescaler (Asynchronous), disable RTC registers Write protection,
enter and exit the RTC initialization mode,
RTC registers synchronization check and reference clock detection enable.
(#) The RTC Prescaler should be programmed to generate the RTC 1Hz time base.
(#) All RTC registers are Write protected. Writing to the RTC registers
is enabled by setting the CNF bit in the RTC_CRL register.
(#) To read the calendar after wakeup from low power modes (Standby or Stop)
the software must first wait for the RSF bit (Register Synchronized Flag)
in the RTC_CRL register to be set by hardware.
The HAL_RTC_WaitForSynchro() function implements the above software
sequence (RSF clear and RSF check).
@endverbatim
* @{
*/
/**
* @brief Initializes the RTC peripheral
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
uint32_t prescaler = 0U;
/* Check input parameters */
if (hrtc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
assert_param(IS_RTC_CALIB_OUTPUT(hrtc->Init.OutPut));
assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
if (hrtc->State == HAL_RTC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrtc->Lock = HAL_UNLOCKED;
hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
if (hrtc->MspInitCallback == NULL)
{
hrtc->MspInitCallback = HAL_RTC_MspInit;
}
/* Init the low level hardware */
hrtc->MspInitCallback(hrtc);
if (hrtc->MspDeInitCallback == NULL)
{
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
}
}
#else
if (hrtc->State == HAL_RTC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrtc->Lock = HAL_UNLOCKED;
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Waiting for synchro */
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
return HAL_ERROR;
}
/* Set Initialization mode */
if (RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
return HAL_ERROR;
}
else
{
/* Clear Flags Bits */
CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC));
if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE)
{
/* Disable the selected Tamper pin */
CLEAR_BIT(BKP->CR, BKP_CR_TPE);
}
/* Set the signal which will be routed to RTC Tamper pin*/
MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut);
if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND)
{
/* RTC Prescaler provided directly by end-user*/
prescaler = hrtc->Init.AsynchPrediv;
}
else
{
/* RTC Prescaler will be automatically calculated to get 1 second timebase */
/* Get the RTCCLK frequency */
prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC);
/* Check that RTC clock is enabled*/
if (prescaler == 0U)
{
/* Should not happen. Frequency is not available*/
hrtc->State = HAL_RTC_STATE_ERROR;
return HAL_ERROR;
}
else
{
/* RTC period = RTCCLK/(RTC_PR + 1) */
prescaler = prescaler - 1U;
}
}
/* Configure the RTC_PRLH / RTC_PRLL */
WRITE_REG(hrtc->Instance->PRLH, ((prescaler >> 16U) & RTC_PRLH_PRL));
WRITE_REG(hrtc->Instance->PRLL, (prescaler & RTC_PRLL_PRL));
/* Wait for synchro */
if (RTC_ExitInitMode(hrtc) != HAL_OK)
{
hrtc->State = HAL_RTC_STATE_ERROR;
return HAL_ERROR;
}
/* Initialize date to 1st of January 2000 */
hrtc->DateToUpdate.Year = 0x00U;
hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY;
hrtc->DateToUpdate.Date = 0x01U;
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_READY;
return HAL_OK;
}
}
/**
* @brief DeInitializes the RTC peripheral
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @note This function does not reset the RTC Backup Data registers.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
{
/* Check input parameters */
if (hrtc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Set Initialization mode */
if (RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
/* Release Lock */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
else
{
CLEAR_REG(hrtc->Instance->CNTL);
CLEAR_REG(hrtc->Instance->CNTH);
WRITE_REG(hrtc->Instance->PRLL, 0x00008000U);
CLEAR_REG(hrtc->Instance->PRLH);
/* Reset All CRH/CRL bits */
CLEAR_REG(hrtc->Instance->CRH);
CLEAR_REG(hrtc->Instance->CRL);
if (RTC_ExitInitMode(hrtc) != HAL_OK)
{
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
}
/* Wait for synchro*/
HAL_RTC_WaitForSynchro(hrtc);
/* Clear RSF flag */
CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF);
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
if (hrtc->MspDeInitCallback == NULL)
{
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
}
/* DeInit the low level hardware: CLOCK, NVIC.*/
hrtc->MspDeInitCallback(hrtc);
#else
/* De-Initialize RTC MSP */
HAL_RTC_MspDeInit(hrtc);
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
hrtc->State = HAL_RTC_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User RTC Callback
* To be used instead of the weak predefined callback
* @param hrtc RTC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
* @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hrtc);
if (HAL_RTC_STATE_READY == hrtc->State)
{
switch (CallbackID)
{
case HAL_RTC_ALARM_A_EVENT_CB_ID :
hrtc->AlarmAEventCallback = pCallback;
break;
case HAL_RTC_TAMPER1_EVENT_CB_ID :
hrtc->Tamper1EventCallback = pCallback;
break;
case HAL_RTC_MSPINIT_CB_ID :
hrtc->MspInitCallback = pCallback;
break;
case HAL_RTC_MSPDEINIT_CB_ID :
hrtc->MspDeInitCallback = pCallback;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_RTC_STATE_RESET == hrtc->State)
{
switch (CallbackID)
{
case HAL_RTC_MSPINIT_CB_ID :
hrtc->MspInitCallback = pCallback;
break;
case HAL_RTC_MSPDEINIT_CB_ID :
hrtc->MspDeInitCallback = pCallback;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hrtc);
return status;
}
/**
* @brief Unregister an RTC Callback
* RTC callback is redirected to the weak predefined callback
* @param hrtc RTC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
* @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hrtc);
if (HAL_RTC_STATE_READY == hrtc->State)
{
switch (CallbackID)
{
case HAL_RTC_ALARM_A_EVENT_CB_ID :
hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
break;
case HAL_RTC_TAMPER1_EVENT_CB_ID :
hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
break;
case HAL_RTC_MSPINIT_CB_ID :
hrtc->MspInitCallback = HAL_RTC_MspInit;
break;
case HAL_RTC_MSPDEINIT_CB_ID :
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_RTC_STATE_RESET == hrtc->State)
{
switch (CallbackID)
{
case HAL_RTC_MSPINIT_CB_ID :
hrtc->MspInitCallback = HAL_RTC_MspInit;
break;
case HAL_RTC_MSPDEINIT_CB_ID :
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hrtc);
return status;
}
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @brief Initializes the RTC MSP.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the RTC MSP.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group2 Time and Date functions
* @brief RTC Time and Date functions
*
@verbatim
===============================================================================
##### RTC Time and Date functions #####
===============================================================================
[..] This section provides functions allowing to configure Time and Date features
@endverbatim
* @{
*/
/**
* @brief Sets RTC current time.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t counter_time = 0U, counter_alarm = 0U;
/* Check input parameters */
if ((hrtc == NULL) || (sTime == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
if (Format == RTC_FORMAT_BIN)
{
assert_param(IS_RTC_HOUR24(sTime->Hours));
assert_param(IS_RTC_MINUTES(sTime->Minutes));
assert_param(IS_RTC_SECONDS(sTime->Seconds));
counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600U) + \
((uint32_t)sTime->Minutes * 60U) + \
((uint32_t)sTime->Seconds));
}
else
{
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600U) + \
((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60U) + \
((uint32_t)(RTC_Bcd2ToByte(sTime->Seconds))));
}
/* Write time counter in RTC registers */
if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
else
{
/* Clear Second and overflow flags */
CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
/* Read current Alarm counter in RTC registers */
counter_alarm = RTC_ReadAlarmCounter(hrtc);
/* Set again alarm to match with new time if enabled */
if (counter_alarm != RTC_ALARM_RESETVALUE)
{
if (counter_alarm < counter_time)
{
/* Add 1 day to alarm counter*/
counter_alarm += (uint32_t)(24U * 3600U);
/* Write new Alarm counter in RTC registers */
if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
}
}
hrtc->State = HAL_RTC_STATE_READY;
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
}
/**
* @brief Gets RTC current time.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t counter_time = 0U, counter_alarm = 0U, days_elapsed = 0U, hours = 0U;
/* Check input parameters */
if ((hrtc == NULL) || (sTime == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
/* Check if counter overflow occurred */
if (__HAL_RTC_OVERFLOW_GET_FLAG(hrtc, RTC_FLAG_OW))
{
return HAL_ERROR;
}
/* Read the time counter*/
counter_time = RTC_ReadTimeCounter(hrtc);
/* Fill the structure fields with the read parameters */
hours = counter_time / 3600U;
sTime->Minutes = (uint8_t)((counter_time % 3600U) / 60U);
sTime->Seconds = (uint8_t)((counter_time % 3600U) % 60U);
if (hours >= 24U)
{
/* Get number of days elapsed from last calculation */
days_elapsed = (hours / 24U);
/* Set Hours in RTC_TimeTypeDef structure*/
sTime->Hours = (hours % 24U);
/* Read Alarm counter in RTC registers */
counter_alarm = RTC_ReadAlarmCounter(hrtc);
/* Calculate remaining time to reach alarm (only if set and not yet expired)*/
if ((counter_alarm != RTC_ALARM_RESETVALUE) && (counter_alarm > counter_time))
{
counter_alarm -= counter_time;
}
else
{
/* In case of counter_alarm < counter_time */
/* Alarm expiration already occurred but alarm not deactivated */
counter_alarm = RTC_ALARM_RESETVALUE;
}
/* Set updated time in decreasing counter by number of days elapsed */
counter_time -= (days_elapsed * 24U * 3600U);
/* Write time counter in RTC registers */
if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
{
return HAL_ERROR;
}
/* Set updated alarm to be set */
if (counter_alarm != RTC_ALARM_RESETVALUE)
{
counter_alarm += counter_time;
/* Write time counter in RTC registers */
if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
{
return HAL_ERROR;
}
}
else
{
/* Alarm already occurred. Set it to reset values to avoid unexpected expiration */
if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
{
return HAL_ERROR;
}
}
/* Update date */
RTC_DateUpdate(hrtc, days_elapsed);
}
else
{
sTime->Hours = hours;
}
/* Check the input parameters format */
if (Format != RTC_FORMAT_BIN)
{
/* Convert the time structure parameters to BCD format */
sTime->Hours = (uint8_t)RTC_ByteToBcd2(sTime->Hours);
sTime->Minutes = (uint8_t)RTC_ByteToBcd2(sTime->Minutes);
sTime->Seconds = (uint8_t)RTC_ByteToBcd2(sTime->Seconds);
}
return HAL_OK;
}
/**
* @brief Sets RTC current date.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sDate: Pointer to date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
uint32_t counter_time = 0U, counter_alarm = 0U, hours = 0U;
/* Check input parameters */
if ((hrtc == NULL) || (sDate == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
if (Format == RTC_FORMAT_BIN)
{
assert_param(IS_RTC_YEAR(sDate->Year));
assert_param(IS_RTC_MONTH(sDate->Month));
assert_param(IS_RTC_DATE(sDate->Date));
/* Change the current date */
hrtc->DateToUpdate.Year = sDate->Year;
hrtc->DateToUpdate.Month = sDate->Month;
hrtc->DateToUpdate.Date = sDate->Date;
}
else
{
assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
/* Change the current date */
hrtc->DateToUpdate.Year = RTC_Bcd2ToByte(sDate->Year);
hrtc->DateToUpdate.Month = RTC_Bcd2ToByte(sDate->Month);
hrtc->DateToUpdate.Date = RTC_Bcd2ToByte(sDate->Date);
}
/* WeekDay set by user can be ignored because automatically calculated */
hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(hrtc->DateToUpdate.Year, hrtc->DateToUpdate.Month, hrtc->DateToUpdate.Date);
sDate->WeekDay = hrtc->DateToUpdate.WeekDay;
/* Reset time to be aligned on the same day */
/* Read the time counter*/
counter_time = RTC_ReadTimeCounter(hrtc);
/* Fill the structure fields with the read parameters */
hours = counter_time / 3600U;
if (hours > 24U)
{
/* Set updated time in decreasing counter by number of days elapsed */
counter_time -= ((hours / 24U) * 24U * 3600U);
/* Write time counter in RTC registers */
if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
/* Read current Alarm counter in RTC registers */
counter_alarm = RTC_ReadAlarmCounter(hrtc);
/* Set again alarm to match with new time if enabled */
if (counter_alarm != RTC_ALARM_RESETVALUE)
{
if (counter_alarm < counter_time)
{
/* Add 1 day to alarm counter*/
counter_alarm += (uint32_t)(24U * 3600U);
/* Write new Alarm counter in RTC registers */
if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
}
}
}
hrtc->State = HAL_RTC_STATE_READY ;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @brief Gets RTC current date.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sDate: Pointer to Date structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
RTC_TimeTypeDef stime = {0U};
/* Check input parameters */
if ((hrtc == NULL) || (sDate == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
/* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
{
return HAL_ERROR;
}
/* Fill the structure fields with the read parameters */
sDate->WeekDay = hrtc->DateToUpdate.WeekDay;
sDate->Year = hrtc->DateToUpdate.Year;
sDate->Month = hrtc->DateToUpdate.Month;
sDate->Date = hrtc->DateToUpdate.Date;
/* Check the input parameters format */
if (Format != RTC_FORMAT_BIN)
{
/* Convert the date structure parameters to BCD format */
sDate->Year = (uint8_t)RTC_ByteToBcd2(sDate->Year);
sDate->Month = (uint8_t)RTC_ByteToBcd2(sDate->Month);
sDate->Date = (uint8_t)RTC_ByteToBcd2(sDate->Date);
}
return HAL_OK;
}
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group3 Alarm functions
* @brief RTC Alarm functions
*
@verbatim
===============================================================================
##### RTC Alarm functions #####
===============================================================================
[..] This section provides functions allowing to configure Alarm feature
@endverbatim
* @{
*/
/**
* @brief Sets the specified RTC Alarm.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
uint32_t counter_alarm = 0U, counter_time;
RTC_TimeTypeDef stime = {0U};
/* Check input parameters */
if ((hrtc == NULL) || (sAlarm == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_ALARM(sAlarm->Alarm));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
/* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
{
return HAL_ERROR;
}
/* Convert time in seconds */
counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \
((uint32_t)stime.Minutes * 60U) + \
((uint32_t)stime.Seconds));
if (Format == RTC_FORMAT_BIN)
{
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \
((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \
((uint32_t)sAlarm->AlarmTime.Seconds));
}
else
{
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \
((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \
((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
}
/* Check that requested alarm should expire in the same day (otherwise add 1 day) */
if (counter_alarm < counter_time)
{
/* Add 1 day to alarm counter*/
counter_alarm += (uint32_t)(24U * 3600U);
}
/* Write Alarm counter in RTC registers */
if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
else
{
hrtc->State = HAL_RTC_STATE_READY;
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
}
/**
* @brief Sets the specified RTC Alarm with Interrupt
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
uint32_t counter_alarm = 0U, counter_time;
RTC_TimeTypeDef stime = {0U};
/* Check input parameters */
if ((hrtc == NULL) || (sAlarm == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_ALARM(sAlarm->Alarm));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
/* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
{
return HAL_ERROR;
}
/* Convert time in seconds */
counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \
((uint32_t)stime.Minutes * 60U) + \
((uint32_t)stime.Seconds));
if (Format == RTC_FORMAT_BIN)
{
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \
((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \
((uint32_t)sAlarm->AlarmTime.Seconds));
}
else
{
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \
((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \
((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
}
/* Check that requested alarm should expire in the same day (otherwise add 1 day) */
if (counter_alarm < counter_time)
{
/* Add 1 day to alarm counter*/
counter_alarm += (uint32_t)(24U * 3600U);
}
/* Write alarm counter in RTC registers */
if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
else
{
/* Clear flag alarm A */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Configure the Alarm interrupt */
__HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
/* RTC Alarm Interrupt Configuration: EXTI configuration */
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
hrtc->State = HAL_RTC_STATE_READY;
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
}
/**
* @brief Gets the RTC Alarm value and masks.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sAlarm: Pointer to Date structure
* @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A: Alarm
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
{
uint32_t counter_alarm = 0U;
/* Prevent unused argument(s) compilation warning */
UNUSED(Alarm);
/* Check input parameters */
if ((hrtc == NULL) || (sAlarm == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_ALARM(Alarm));
/* Read Alarm counter in RTC registers */
counter_alarm = RTC_ReadAlarmCounter(hrtc);
/* Fill the structure with the read parameters */
/* Set hours in a day range (between 0 to 24)*/
sAlarm->AlarmTime.Hours = (uint32_t)((counter_alarm / 3600U) % 24U);
sAlarm->AlarmTime.Minutes = (uint32_t)((counter_alarm % 3600U) / 60U);
sAlarm->AlarmTime.Seconds = (uint32_t)((counter_alarm % 3600U) % 60U);
if (Format != RTC_FORMAT_BIN)
{
sAlarm->AlarmTime.Hours = RTC_ByteToBcd2(sAlarm->AlarmTime.Hours);
sAlarm->AlarmTime.Minutes = RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes);
sAlarm->AlarmTime.Seconds = RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds);
}
return HAL_OK;
}
/**
* @brief Deactivate the specified RTC Alarm
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A: AlarmA
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(Alarm);
/* Check the parameters */
assert_param(IS_RTC_ALARM(Alarm));
/* Check input parameters */
if (hrtc == NULL)
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
/* Set Initialization mode */
if (RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
else
{
/* Clear flag alarm A */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Set to default values ALRH & ALRL registers */
WRITE_REG(hrtc->Instance->ALRH, RTC_ALARM_RESETVALUE_REGISTER);
WRITE_REG(hrtc->Instance->ALRL, RTC_ALARM_RESETVALUE_REGISTER);
/* RTC Alarm Interrupt Configuration: Disable EXTI configuration */
__HAL_RTC_ALARM_EXTI_DISABLE_IT();
/* Wait for synchro */
if (RTC_ExitInitMode(hrtc) != HAL_OK)
{
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
}
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @brief This function handles Alarm interrupt request.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
{
if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA))
{
/* Get the status of the Interrupt */
if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET)
{
/* AlarmA callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->AlarmAEventCallback(hrtc);
#else
HAL_RTC_AlarmAEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Alarm interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
}
}
/* Clear the EXTI's line Flag for RTC Alarm */
__HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
/**
* @brief Alarm A callback.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_AlarmAEventCallback could be implemented in the user file
*/
}
/**
* @brief This function handles AlarmA Polling request.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
/* Check input parameters */
if (hrtc == NULL)
{
return HAL_ERROR;
}
while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
{
if (Timeout != HAL_MAX_DELAY)
{
if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
/* Clear the Alarm interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
return HAL_OK;
}
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Get RTC state
@endverbatim
* @{
*/
/**
* @brief Returns the RTC state.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL state
*/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
{
return hrtc->State;
}
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group5 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Wait for RTC Time and Date Synchronization
@endverbatim
* @{
*/
/**
* @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
* are synchronized with RTC APB clock.
* @note This function must be called before any read operation after an APB reset
* or an APB clock stop.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0U;
/* Check input parameters */
if (hrtc == NULL)
{
return HAL_ERROR;
}
/* Clear RSF flag */
CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF);
tickstart = HAL_GetTick();
/* Wait the registers to be synchronised */
while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup RTC_Private_Functions
* @{
*/
/**
* @brief Read the time counter available in RTC_CNT registers.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval Time counter
*/
static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc)
{
uint16_t high1 = 0U, high2 = 0U, low = 0U;
uint32_t timecounter = 0U;
high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT);
low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT);
high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT);
if (high1 != high2)
{
/* In this case the counter roll over during reading of CNTL and CNTH registers,
read again CNTL register then return the counter value */
timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT));
}
else
{
/* No counter roll over during reading of CNTL and CNTH registers, counter
value is equal to first value of CNTL and CNTH */
timecounter = (((uint32_t) high1 << 16U) | low);
}
return timecounter;
}
/**
* @brief Write the time counter in RTC_CNT registers.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param TimeCounter: Counter to write in RTC_CNT registers
* @retval HAL status
*/
static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter)
{
HAL_StatusTypeDef status = HAL_OK;
/* Set Initialization mode */
if (RTC_EnterInitMode(hrtc) != HAL_OK)
{
status = HAL_ERROR;
}
else
{
/* Set RTC COUNTER MSB word */
WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U));
/* Set RTC COUNTER LSB word */
WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT));
/* Wait for synchro */
if (RTC_ExitInitMode(hrtc) != HAL_OK)
{
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Read the time counter available in RTC_ALR registers.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval Time counter
*/
static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef *hrtc)
{
uint16_t high1 = 0U, low = 0U;
high1 = READ_REG(hrtc->Instance->ALRH & RTC_CNTH_RTC_CNT);
low = READ_REG(hrtc->Instance->ALRL & RTC_CNTL_RTC_CNT);
return (((uint32_t) high1 << 16U) | low);
}
/**
* @brief Write the time counter in RTC_ALR registers.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param AlarmCounter: Counter to write in RTC_ALR registers
* @retval HAL status
*/
static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter)
{
HAL_StatusTypeDef status = HAL_OK;
/* Set Initialization mode */
if (RTC_EnterInitMode(hrtc) != HAL_OK)
{
status = HAL_ERROR;
}
else
{
/* Set RTC COUNTER MSB word */
WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16U));
/* Set RTC COUNTER LSB word */
WRITE_REG(hrtc->Instance->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR));
/* Wait for synchro */
if (RTC_ExitInitMode(hrtc) != HAL_OK)
{
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Enters the RTC Initialization mode.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0U;
tickstart = HAL_GetTick();
/* Wait till RTC is in INIT state and if Time out is reached exit */
while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
return HAL_OK;
}
/**
* @brief Exit the RTC Initialization mode.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0U;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
tickstart = HAL_GetTick();
/* Wait till RTC is in INIT state and if Time out is reached exit */
while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @brief Converts a 2 digit decimal to BCD format.
* @param Value: Byte to be converted
* @retval Converted byte
*/
static uint8_t RTC_ByteToBcd2(uint8_t Value)
{
uint32_t bcdhigh = 0U;
while (Value >= 10U)
{
bcdhigh++;
Value -= 10U;
}
return ((uint8_t)(bcdhigh << 4U) | Value);
}
/**
* @brief Converts from 2 digit BCD to Binary.
* @param Value: BCD value to be converted
* @retval Converted word
*/
static uint8_t RTC_Bcd2ToByte(uint8_t Value)
{
uint32_t tmp = 0U;
tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U;
return (tmp + (Value & (uint8_t)0x0F));
}
/**
* @brief Updates date when time is 23:59:59.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param DayElapsed: Number of days elapsed from last date update
* @retval None
*/
static void RTC_DateUpdate(RTC_HandleTypeDef *hrtc, uint32_t DayElapsed)
{
uint32_t year = 0U, month = 0U, day = 0U;
uint32_t loop = 0U;
/* Get the current year*/
year = hrtc->DateToUpdate.Year;
/* Get the current month and day */
month = hrtc->DateToUpdate.Month;
day = hrtc->DateToUpdate.Date;
for (loop = 0U; loop < DayElapsed; loop++)
{
if ((month == 1U) || (month == 3U) || (month == 5U) || (month == 7U) || \
(month == 8U) || (month == 10U) || (month == 12U))
{
if (day < 31U)
{
day++;
}
/* Date structure member: day = 31 */
else
{
if (month != 12U)
{
month++;
day = 1U;
}
/* Date structure member: day = 31 & month =12 */
else
{
month = 1U;
day = 1U;
year++;
}
}
}
else if ((month == 4U) || (month == 6U) || (month == 9U) || (month == 11U))
{
if (day < 30U)
{
day++;
}
/* Date structure member: day = 30 */
else
{
month++;
day = 1U;
}
}
else if (month == 2U)
{
if (day < 28U)
{
day++;
}
else if (day == 28U)
{
/* Leap year */
if (RTC_IsLeapYear(year))
{
day++;
}
else
{
month++;
day = 1U;
}
}
else if (day == 29U)
{
month++;
day = 1U;
}
}
}
/* Update year */
hrtc->DateToUpdate.Year = year;
/* Update day and month */
hrtc->DateToUpdate.Month = month;
hrtc->DateToUpdate.Date = day;
/* Update day of the week */
hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(year, month, day);
}
/**
* @brief Check whether the passed year is Leap or not.
* @param nYear year to check
* @retval 1: leap year
* 0: not leap year
*/
static uint8_t RTC_IsLeapYear(uint16_t nYear)
{
if ((nYear % 4U) != 0U)
{
return 0U;
}
if ((nYear % 100U) != 0U)
{
return 1U;
}
if ((nYear % 400U) == 0U)
{
return 1U;
}
else
{
return 0U;
}
}
/**
* @brief Determines the week number, the day number and the week day number.
* @param nYear year to check
* @param nMonth Month to check
* @param nDay Day to check
* @note Day is calculated with hypothesis that year > 2000
* @retval Value which can take one of the following parameters:
* @arg RTC_WEEKDAY_MONDAY
* @arg RTC_WEEKDAY_TUESDAY
* @arg RTC_WEEKDAY_WEDNESDAY
* @arg RTC_WEEKDAY_THURSDAY
* @arg RTC_WEEKDAY_FRIDAY
* @arg RTC_WEEKDAY_SATURDAY
* @arg RTC_WEEKDAY_SUNDAY
*/
static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay)
{
uint32_t year = 0U, weekday = 0U;
year = 2000U + nYear;
if (nMonth < 3U)
{
/*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/
weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + ((year - 1U) / 4U) - ((year - 1U) / 100U) + ((year - 1U) / 400U)) % 7U;
}
else
{
/*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/
weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + (year / 4U) - (year / 100U) + (year / 400U) - 2U) % 7U;
}
return (uint8_t)weekday;
}
/**
* @}
*/
#endif /* HAL_RTC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

575
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c Normal file
View File

@@ -0,0 +1,575 @@
/**
******************************************************************************
* @file stm32f1xx_hal_rtc_ex.c
* @author MCD Application Team
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
* + RTC Tamper functions
* + Extension Control functions
* + Extension RTC features functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_RTC_MODULE_ENABLED
/** @defgroup RTCEx RTCEx
* @brief RTC Extended HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
*/
/** @defgroup RTCEx_Exported_Functions_Group1 RTC Tamper functions
* @brief RTC Tamper functions
*
@verbatim
===============================================================================
##### RTC Tamper functions #####
===============================================================================
[..] This section provides functions allowing to configure Tamper feature
@endverbatim
* @{
*/
/**
* @brief Sets Tamper
* @note By calling this API we disable the tamper interrupt for all tampers.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sTamper: Pointer to Tamper Structure.
* @note Tamper can be enabled only if ASOE and CCO bit are reset
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
{
/* Check input parameters */
if ((hrtc == NULL) || (sTamper == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
if (HAL_IS_BIT_SET(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE)))
{
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger)));
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @brief Sets Tamper with interrupt.
* @note By calling this API we force the tamper interrupt for all tampers.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sTamper: Pointer to RTC Tamper.
* @note Tamper can be enabled only if ASOE and CCO bit are reset
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
{
/* Check input parameters */
if ((hrtc == NULL) || (sTamper == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
if (HAL_IS_BIT_SET(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE)))
{
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger)));
/* Configure the Tamper Interrupt in the BKP->CSR */
__HAL_RTC_TAMPER_ENABLE_IT(hrtc, RTC_IT_TAMP1);
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @brief Deactivates Tamper.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param Tamper: Selected tamper pin.
* This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
{
/* Check input parameters */
if (hrtc == NULL)
{
return HAL_ERROR;
}
/* Prevent unused argument(s) compilation warning */
UNUSED(Tamper);
assert_param(IS_RTC_TAMPER(Tamper));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
/* Disable the selected Tamper pin */
CLEAR_BIT(BKP->CR, BKP_CR_TPE);
/* Disable the Tamper Interrupt in the BKP->CSR */
/* Configure the Tamper Interrupt in the BKP->CSR */
__HAL_RTC_TAMPER_DISABLE_IT(hrtc, RTC_IT_TAMP1);
/* Clear the Tamper interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
SET_BIT(BKP->CSR, BKP_CSR_CTE);
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @brief This function handles Tamper interrupt request.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
{
/* Get the status of the Interrupt */
if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP1))
{
/* Get the TAMPER Interrupt enable bit and pending bit */
if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET)
{
/* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->Tamper1EventCallback(hrtc);
#else
HAL_RTCEx_Tamper1EventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Tamper interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
}
}
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
/**
* @brief Tamper 1 callback.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
*/
}
/**
* @brief This function handles Tamper1 Polling.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
/* Check input parameters */
if (hrtc == NULL)
{
return HAL_ERROR;
}
/* Get the status of the Interrupt */
while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == RESET)
{
if (Timeout != HAL_MAX_DELAY)
{
if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
/* Clear the Tamper Flag */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
return HAL_OK;
}
/**
* @}
*/
/** @defgroup RTCEx_Exported_Functions_Group2 RTC Second functions
* @brief RTC Second functions
*
@verbatim
===============================================================================
##### RTC Second functions #####
===============================================================================
[..] This section provides functions implementing second interrupt handlers
@endverbatim
* @{
*/
/**
* @brief Sets Interrupt for second
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc)
{
/* Check input parameters */
if (hrtc == NULL)
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
/* Enable Second interruption */
__HAL_RTC_SECOND_ENABLE_IT(hrtc, RTC_IT_SEC);
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @brief Deactivates Second.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc)
{
/* Check input parameters */
if (hrtc == NULL)
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
/* Deactivate Second interruption*/
__HAL_RTC_SECOND_DISABLE_IT(hrtc, RTC_IT_SEC);
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @brief This function handles second interrupt request.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef *hrtc)
{
if (__HAL_RTC_SECOND_GET_IT_SOURCE(hrtc, RTC_IT_SEC))
{
/* Get the status of the Interrupt */
if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_SEC))
{
/* Check if Overrun occurred */
if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_OW))
{
/* Second error callback */
HAL_RTCEx_RTCEventErrorCallback(hrtc);
/* Clear flag Second */
__HAL_RTC_OVERFLOW_CLEAR_FLAG(hrtc, RTC_FLAG_OW);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
}
else
{
/* Second callback */
HAL_RTCEx_RTCEventCallback(hrtc);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
/* Clear flag Second */
__HAL_RTC_SECOND_CLEAR_FLAG(hrtc, RTC_FLAG_SEC);
}
}
}
/**
* @brief Second event callback.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTCEx_RTCEventCallback could be implemented in the user file
*/
}
/**
* @brief Second event error callback.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTCEx_RTCEventErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
===============================================================================
##### Extension Peripheral Control functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Writes a data in a specified RTC Backup data register
(+) Read a data in a specified RTC Backup data register
(+) Sets the Smooth calibration parameters.
@endverbatim
* @{
*/
/**
* @brief Writes a data in a specified RTC Backup data register.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param BackupRegister: RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
* specify the register (depending devices).
* @param Data: Data to be written in the specified RTC Backup data register.
* @retval None
*/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
{
uint32_t tmp = 0U;
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
tmp = (uint32_t)BKP_BASE;
tmp += (BackupRegister * 4U);
*(__IO uint32_t *) tmp = (Data & BKP_DR1_D);
}
/**
* @brief Reads data from the specified RTC Backup data Register.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param BackupRegister: RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
* specify the register (depending devices).
* @retval Read value
*/
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
{
uint32_t backupregister = 0U;
uint32_t pvalue = 0U;
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
backupregister = (uint32_t)BKP_BASE;
backupregister += (BackupRegister * 4U);
pvalue = (*(__IO uint32_t *)(backupregister)) & BKP_DR1_D;
/* Read the specified register */
return pvalue;
}
/**
* @brief Sets the Smooth calibration parameters.
* @param hrtc: RTC handle
* @param SmoothCalibPeriod: Not used (only present for compatibility with another families)
* @param SmoothCalibPlusPulses: Not used (only present for compatibility with another families)
* @param SmouthCalibMinusPulsesValue: specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x7F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
{
/* Check input parameters */
if (hrtc == NULL)
{
return HAL_ERROR;
}
/* Prevent unused argument(s) compilation warning */
UNUSED(SmoothCalibPeriod);
UNUSED(SmoothCalibPlusPulses);
/* Check the parameters */
assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
/* Sets RTC Clock Calibration value.*/
MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, SmouthCalibMinusPulsesValue);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_RTC_MODULE_ENABLED */
/**
* @}
*/

4025
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c Normal file
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@@ -0,0 +1,4025 @@
/**
******************************************************************************
* @file stm32f1xx_hal_spi.c
* @author MCD Application Team
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The SPI HAL driver can be used as follows:
(#) Declare a SPI_HandleTypeDef handle structure, for example:
SPI_HandleTypeDef hspi;
(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
(##) Enable the SPIx interface clock
(##) SPI pins configuration
(+++) Enable the clock for the SPI GPIOs
(+++) Configure these SPI pins as alternate function push-pull
(##) NVIC configuration if you need to use interrupt process
(+++) Configure the SPIx interrupt priority
(+++) Enable the NVIC SPI IRQ handle
(##) DMA Configuration if you need to use DMA process
(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
(+++) Enable the DMAx clock
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream/Channel
(+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx
or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customized HAL_SPI_MspInit() API.
[..]
Circular mode restriction:
(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
(##) Master 2Lines RxOnly
(##) Master 1Line Rx
(#) The CRC feature is not managed when the DMA circular mode is enabled
(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
[..]
Master Receive mode restriction:
(#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
does not initiate a new transfer the following procedure has to be respected:
(##) HAL_SPI_DeInit()
(##) HAL_SPI_Init()
[..]
Callback registration:
(#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
Function HAL_SPI_RegisterCallback() allows to register following callbacks:
(++) TxCpltCallback : SPI Tx Completed callback
(++) RxCpltCallback : SPI Rx Completed callback
(++) TxRxCpltCallback : SPI TxRx Completed callback
(++) TxHalfCpltCallback : SPI Tx Half Completed callback
(++) RxHalfCpltCallback : SPI Rx Half Completed callback
(++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
(++) ErrorCallback : SPI Error callback
(++) AbortCpltCallback : SPI Abort callback
(++) MspInitCallback : SPI Msp Init callback
(++) MspDeInitCallback : SPI Msp DeInit callback
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
weak function.
HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(++) TxCpltCallback : SPI Tx Completed callback
(++) RxCpltCallback : SPI Rx Completed callback
(++) TxRxCpltCallback : SPI TxRx Completed callback
(++) TxHalfCpltCallback : SPI Tx Half Completed callback
(++) RxHalfCpltCallback : SPI Rx Half Completed callback
(++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
(++) ErrorCallback : SPI Error callback
(++) AbortCpltCallback : SPI Abort callback
(++) MspInitCallback : SPI Msp Init callback
(++) MspDeInitCallback : SPI Msp DeInit callback
[..]
By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
or HAL_SPI_Init() function.
[..]
When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
[..]
Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
the following table resume the max SPI frequency reached with data size 8bits/16bits,
according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
@endverbatim
Additional table :
DataSize = SPI_DATASIZE_8BIT:
+----------------------------------------------------------------------------------------------+
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
| Process | Transfer mode |---------------------|----------------------|----------------------|
| | | Master | Slave | Master | Slave | Master | Slave |
|==============================================================================================|
| T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
| X |----------------|----------|----------|-----------|----------|-----------|----------|
| / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
| R |----------------|----------|----------|-----------|----------|-----------|----------|
| X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
|=========|================|==========|==========|===========|==========|===========|==========|
| | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
| |----------------|----------|----------|-----------|----------|-----------|----------|
| R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
| X |----------------|----------|----------|-----------|----------|-----------|----------|
| | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
|=========|================|==========|==========|===========|==========|===========|==========|
| | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
| |----------------|----------|----------|-----------|----------|-----------|----------|
| T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
| X |----------------|----------|----------|-----------|----------|-----------|----------|
| | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
+----------------------------------------------------------------------------------------------+
DataSize = SPI_DATASIZE_16BIT:
+----------------------------------------------------------------------------------------------+
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
| Process | Transfer mode |---------------------|----------------------|----------------------|
| | | Master | Slave | Master | Slave | Master | Slave |
|==============================================================================================|
| T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
| X |----------------|----------|----------|-----------|----------|-----------|----------|
| / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA |
| R |----------------|----------|----------|-----------|----------|-----------|----------|
| X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
|=========|================|==========|==========|===========|==========|===========|==========|
| | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 |
| |----------------|----------|----------|-----------|----------|-----------|----------|
| R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
| X |----------------|----------|----------|-----------|----------|-----------|----------|
| | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
|=========|================|==========|==========|===========|==========|===========|==========|
| | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 |
| |----------------|----------|----------|-----------|----------|-----------|----------|
| T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 |
| X |----------------|----------|----------|-----------|----------|-----------|----------|
| | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
+----------------------------------------------------------------------------------------------+
@note The max SPI frequency depend on SPI data size (8bits, 16bits),
SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
@note
(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and
HAL_SPI_TransmitReceive_DMA()
(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup SPI SPI
* @brief SPI HAL module driver
* @{
*/
#ifdef HAL_SPI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
#if (USE_SPI_CRC != 0U) && defined(SPI_CRC_ERROR_WORKAROUND_FEATURE)
/* CRC WORKAROUND FEATURE: Variable used to determine if device is impacted by implementation
* of workaround related to wrong CRC errors detection on SPI2. Conditions in which this workaround
* has to be applied, are:
* - STM32F101CDE/STM32F103CDE
* - Revision ID : Z
* - SPI2
* - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
* the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
* + If the value is 0, the complete data transfer is successful.
* + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
* If CRCERR is found reset, the complete data transfer is considered successful.
*
* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
* CRC errors wrongly detected
*/
/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode
* Revision ID information is only available in Debug mode, so Workaround could not be implemented
* to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
* So, in case of Revision Z F101 or F103 devices, below define should be assigned to 1.
*/
#define USE_SPI_CRC_ERROR_WORKAROUND 0U
#endif /* USE_SPI_CRC */
/** @defgroup SPI_Private_Constants SPI Private Constants
* @{
*/
#define SPI_DEFAULT_TIMEOUT 100U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup SPI_Private_Functions SPI Private Functions
* @{
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart);
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
#if (USE_SPI_CRC != 0U)
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
#endif /* USE_SPI_CRC */
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
de-initialize the SPIx peripheral:
(+) User must implement HAL_SPI_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
(+) Call the function HAL_SPI_Init() to configure the selected device with
the selected configuration:
(++) Mode
(++) Direction
(++) Data Size
(++) Clock Polarity and Phase
(++) NSS Management
(++) BaudRate Prescaler
(++) FirstBit
(++) TIMode
(++) CRC Calculation
(++) CRC Polynomial if CRC enabled
(+) Call the function HAL_SPI_DeInit() to restore the default configuration
of the selected SPIx peripheral.
@endverbatim
* @{
*/
/**
* @brief Initialize the SPI according to the specified parameters
* in the SPI_InitTypeDef and initialize the associated handle.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
/* Check the SPI handle allocation */
if (hspi == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
assert_param(IS_SPI_MODE(hspi->Init.Mode));
assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
/* TI mode is not supported on this device.
TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE */
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
}
}
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
}
#if (USE_SPI_CRC != 0U)
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
/* Init the SPI Callback settings */
hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
if (hspi->MspInitCallback == NULL)
{
hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
(hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
(hspi->Init.DataSize & SPI_CR1_DFF) |
(hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
(hspi->Init.CLKPhase & SPI_CR1_CPHA) |
(hspi->Init.NSS & SPI_CR1_SSM) |
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
/* Configure : NSS management */
WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
#if (USE_SPI_CRC != 0U)
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
/* Configure : CRC Polynomial */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_READY;
return HAL_OK;
}
/**
* @brief De-Initialize the SPI peripheral.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
{
/* Check the SPI handle allocation */
if (hspi == NULL)
{
return HAL_ERROR;
}
/* Check SPI Instance parameter */
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
hspi->State = HAL_SPI_STATE_BUSY;
/* Disable the SPI Peripheral Clock */
__HAL_SPI_DISABLE(hspi);
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
if (hspi->MspDeInitCallback == NULL)
{
hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
hspi->MspDeInitCallback(hspi);
#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_SPI_MspDeInit(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hspi);
return HAL_OK;
}
/**
* @brief Initialize the SPI MSP.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_MspInit should be implemented in the user file
*/
}
/**
* @brief De-Initialize the SPI MSP.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_MspDeInit should be implemented in the user file
*/
}
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User SPI Callback
* To be used instead of the weak predefined callback
* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI.
* @param CallbackID ID of the callback to be registered
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
pSPI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hspi);
if (HAL_SPI_STATE_READY == hspi->State)
{
switch (CallbackID)
{
case HAL_SPI_TX_COMPLETE_CB_ID :
hspi->TxCpltCallback = pCallback;
break;
case HAL_SPI_RX_COMPLETE_CB_ID :
hspi->RxCpltCallback = pCallback;
break;
case HAL_SPI_TX_RX_COMPLETE_CB_ID :
hspi->TxRxCpltCallback = pCallback;
break;
case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
hspi->TxHalfCpltCallback = pCallback;
break;
case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
hspi->RxHalfCpltCallback = pCallback;
break;
case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
hspi->TxRxHalfCpltCallback = pCallback;
break;
case HAL_SPI_ERROR_CB_ID :
hspi->ErrorCallback = pCallback;
break;
case HAL_SPI_ABORT_CB_ID :
hspi->AbortCpltCallback = pCallback;
break;
case HAL_SPI_MSPINIT_CB_ID :
hspi->MspInitCallback = pCallback;
break;
case HAL_SPI_MSPDEINIT_CB_ID :
hspi->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_SPI_STATE_RESET == hspi->State)
{
switch (CallbackID)
{
case HAL_SPI_MSPINIT_CB_ID :
hspi->MspInitCallback = pCallback;
break;
case HAL_SPI_MSPDEINIT_CB_ID :
hspi->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hspi);
return status;
}
/**
* @brief Unregister an SPI Callback
* SPI callback is redirected to the weak predefined callback
* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI.
* @param CallbackID ID of the callback to be unregistered
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hspi);
if (HAL_SPI_STATE_READY == hspi->State)
{
switch (CallbackID)
{
case HAL_SPI_TX_COMPLETE_CB_ID :
hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_SPI_RX_COMPLETE_CB_ID :
hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_SPI_TX_RX_COMPLETE_CB_ID :
hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
break;
case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
break;
case HAL_SPI_ERROR_CB_ID :
hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_SPI_ABORT_CB_ID :
hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_SPI_MSPINIT_CB_ID :
hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
break;
case HAL_SPI_MSPDEINIT_CB_ID :
hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_SPI_STATE_RESET == hspi->State)
{
switch (CallbackID)
{
case HAL_SPI_MSPINIT_CB_ID :
hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
break;
case HAL_SPI_MSPDEINIT_CB_ID :
hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hspi);
return status;
}
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
==============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the SPI
data transfers.
[..] The SPI supports master and slave mode :
(#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode: The communication is performed using Interrupts
or DMA, These APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
will be executed respectively at the end of the transmit or Receive process
The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
exist for 1Line (simplex) and 2Lines (full duplex) modes.
@endverbatim
* @{
*/
/**
* @brief Transmit an amount of data in blocking mode.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData pointer to data buffer
* @param Size amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
uint16_t initial_TxXferCount;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
initial_TxXferCount = Size;
if (hspi->State != HAL_SPI_STATE_READY)
{
return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hspi);
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
/*Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
hspi->RxXferSize = 0U;
hspi->RxXferCount = 0U;
hspi->TxISR = NULL;
hspi->RxISR = NULL;
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Transmit data in 16 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
/* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0U)
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
}
}
}
/* Transmit data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
}
while (hspi->TxXferCount > 0U)
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
}
}
}
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
return HAL_ERROR;
}
else
{
return HAL_OK;
}
}
/**
* @brief Receive an amount of data in blocking mode.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData pointer to data buffer
* @param Size amount of data to be received
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
uint32_t tickstart;
if (hspi->State != HAL_SPI_STATE_READY)
{
return HAL_BUSY;
}
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
}
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hspi);
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pRxBuffPtr = (uint8_t *)pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
/*Init field not used in handle to zero */
hspi->pTxBuffPtr = (uint8_t *)NULL;
hspi->TxXferSize = 0U;
hspi->TxXferCount = 0U;
hspi->RxISR = NULL;
hspi->TxISR = NULL;
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
/* this is done to handle the CRCNEXT before the latest data */
hspi->RxXferCount--;
}
#endif /* USE_SPI_CRC */
/* Configure communication direction: 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi);
}
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Receive data in 8 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
{
/* Transfer loop */
while (hspi->RxXferCount > 0U)
{
/* Check the RXNE flag */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
/* read the received data */
(* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint8_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
}
}
}
else
{
/* Transfer loop */
while (hspi->RxXferCount > 0U)
{
/* Check the RXNE flag */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
}
}
}
#if (USE_SPI_CRC != 0U)
/* Handle the CRC Transmission */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* freeze the CRC before the latest data */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
/* Check if CRCNEXT is well reset by hardware */
if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
{
/* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
/* Read the latest data */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* the latest data has not been received */
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
/* Receive last data in 16 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
}
/* Receive last data in 8 Bit mode */
else
{
(*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
}
/* Wait the CRC data */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
/* Read CRC to Flush DR and RXNE flag */
tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
/* Check if CRC error is valid or not (workaround to be applied or not) */
if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Reset CRC Calculation */
SPI_RESET_CRC(hspi);
}
else
{
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
#endif /* USE_SPI_CRC */
hspi->State = HAL_SPI_STATE_READY;
/* Unlock the process */
__HAL_UNLOCK(hspi);
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
return HAL_ERROR;
}
else
{
return HAL_OK;
}
}
/**
* @brief Transmit and Receive an amount of data in blocking mode.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pTxData pointer to transmission data buffer
* @param pRxData pointer to reception data buffer
* @param Size amount of data to be sent and received
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout)
{
uint16_t initial_TxXferCount;
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
initial_TxXferCount = Size;
if (!((tmp_state == HAL_SPI_STATE_READY) || \
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
(tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hspi);
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferCount = Size;
hspi->RxXferSize = Size;
hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferCount = Size;
hspi->TxXferSize = Size;
/*Init field not used in handle to zero */
hspi->RxISR = NULL;
hspi->TxISR = NULL;
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Transmit and Receive data in 16 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
}
/* Check RXNE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
}
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
{
hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
}
}
/* Transmit and Receive data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
*(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
}
/* Wait until RXNE flag is reset */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
{
(*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr++;
hspi->RxXferCount--;
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
}
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
{
hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
}
}
#if (USE_SPI_CRC != 0U)
/* Read CRC from DR to close CRC calculation process */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until TXE flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
/* Read CRC */
tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
}
/* Check if CRC error occurred */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
/* Check if CRC error is valid or not (workaround to be applied or not) */
if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Reset CRC Calculation */
SPI_RESET_CRC(hspi);
__HAL_UNLOCK(hspi);
return HAL_ERROR;
}
else
{
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
__HAL_UNLOCK(hspi);
return HAL_ERROR;
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
/* Unlock the process */
__HAL_UNLOCK(hspi);
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
return HAL_ERROR;
}
else
{
return HAL_OK;
}
}
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData pointer to data buffer
* @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
if (hspi->State != HAL_SPI_STATE_READY)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hspi);
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
/* Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
hspi->RxXferSize = 0U;
hspi->RxXferCount = 0U;
hspi->RxISR = NULL;
/* Set the function for IT treatment */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->TxISR = SPI_TxISR_16BIT;
}
else
{
hspi->TxISR = SPI_TxISR_8BIT;
}
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Process Unlocked */
__HAL_UNLOCK(hspi);
/* Enable TXE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
return HAL_OK;
}
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData pointer to data buffer
* @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
if (hspi->State != HAL_SPI_STATE_READY)
{
return HAL_BUSY;
}
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
}
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hspi);
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pRxBuffPtr = (uint8_t *)pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
/* Init field not used in handle to zero */
hspi->pTxBuffPtr = (uint8_t *)NULL;
hspi->TxXferSize = 0U;
hspi->TxXferCount = 0U;
hspi->TxISR = NULL;
/* Set the function for IT treatment */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->RxISR = SPI_RxISR_16BIT;
}
else
{
hspi->RxISR = SPI_RxISR_8BIT;
}
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Note : The SPI must be enabled after unlocking current process
to avoid the risk of SPI interrupt handle execution before current
process unlock */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Process Unlocked */
__HAL_UNLOCK(hspi);
/* Enable RXNE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
return HAL_OK;
}
/**
* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pTxData pointer to transmission data buffer
* @param pRxData pointer to reception data buffer
* @param Size amount of data to be sent and received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) || \
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
(tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hspi);
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
/* Set the function for IT treatment */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->RxISR = SPI_2linesRxISR_16BIT;
hspi->TxISR = SPI_2linesTxISR_16BIT;
}
else
{
hspi->RxISR = SPI_2linesRxISR_8BIT;
hspi->TxISR = SPI_2linesTxISR_8BIT;
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Process Unlocked */
__HAL_UNLOCK(hspi);
/* Enable TXE, RXNE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
return HAL_OK;
}
/**
* @brief Transmit an amount of data in non-blocking mode with DMA.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData pointer to data buffer
* @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
/* Check tx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
if (hspi->State != HAL_SPI_STATE_READY)
{
return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hspi);
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
/* Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
hspi->TxISR = NULL;
hspi->RxISR = NULL;
hspi->RxXferSize = 0U;
hspi->RxXferCount = 0U;
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Set the SPI TxDMA Half transfer complete callback */
hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
/* Set the SPI TxDMA transfer complete callback */
hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
/* Set the DMA error callback */
hspi->hdmatx->XferErrorCallback = SPI_DMAError;
/* Set the DMA AbortCpltCallback */
hspi->hdmatx->XferAbortCallback = NULL;
/* Enable the Tx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
hspi->TxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_ERROR;
}
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Process Unlocked */
__HAL_UNLOCK(hspi);
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
return HAL_OK;
}
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
* @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData pointer to data buffer
* @note When the CRC feature is enabled the pData Length must be Size + 1.
* @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
/* Check rx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
if (hspi->State != HAL_SPI_STATE_READY)
{
return HAL_BUSY;
}
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
/* Check tx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
}
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hspi);
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pRxBuffPtr = (uint8_t *)pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
/*Init field not used in handle to zero */
hspi->RxISR = NULL;
hspi->TxISR = NULL;
hspi->TxXferSize = 0U;
hspi->TxXferCount = 0U;
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Set the SPI RxDMA Half transfer complete callback */
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
/* Set the SPI Rx DMA transfer complete callback */
hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
/* Set the DMA error callback */
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
/* Set the DMA AbortCpltCallback */
hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
hspi->RxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_ERROR;
}
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Process Unlocked */
__HAL_UNLOCK(hspi);
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
return HAL_OK;
}
/**
* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pTxData pointer to transmission data buffer
* @param pRxData pointer to reception data buffer
* @note When the CRC feature is enabled the pRxData Length must be Size + 1
* @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
/* Check rx & tx dma handles */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) ||
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
(tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hspi);
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
/* Init field not used in handle to zero */
hspi->RxISR = NULL;
hspi->TxISR = NULL;
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
/* Set the SPI Rx DMA Half transfer complete callback */
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
}
else
{
/* Set the SPI Tx/Rx DMA Half transfer complete callback */
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
}
/* Set the DMA error callback */
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
/* Set the DMA AbortCpltCallback */
hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
hspi->RxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_ERROR;
}
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
is performed in DMA reception complete callback */
hspi->hdmatx->XferHalfCpltCallback = NULL;
hspi->hdmatx->XferCpltCallback = NULL;
hspi->hdmatx->XferErrorCallback = NULL;
hspi->hdmatx->XferAbortCallback = NULL;
/* Enable the Tx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
hspi->TxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_ERROR;
}
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Process Unlocked */
__HAL_UNLOCK(hspi);
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
return HAL_OK;
}
/**
* @brief Abort ongoing transfer (blocking mode).
* @param hspi SPI handle.
* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
* started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable SPI Interrupts (depending of transfer direction)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode;
__IO uint32_t count;
__IO uint32_t resetcount;
/* Initialized local variable */
errorcode = HAL_OK;
resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
count = resetcount;
/* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
{
hspi->TxISR = SPI_AbortTx_ISR;
/* Wait HAL_SPI_STATE_ABORT state */
do
{
if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
count--;
} while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
{
hspi->RxISR = SPI_AbortRx_ISR;
/* Wait HAL_SPI_STATE_ABORT state */
do
{
if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
count--;
} while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
/* Disable the SPI DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
{
/* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
if (hspi->hdmatx != NULL)
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
hspi->hdmatx->XferAbortCallback = NULL;
/* Abort DMA Tx Handle linked to SPI Peripheral */
if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
/* Disable Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
/* Wait until TXE flag is set */
do
{
if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
count--;
} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
}
}
/* Disable the SPI DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
{
/* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
if (hspi->hdmarx != NULL)
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
hspi->hdmarx->XferAbortCallback = NULL;
/* Abort DMA Rx Handle linked to SPI Peripheral */
if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
/* Disable peripheral */
__HAL_SPI_DISABLE(hspi);
/* Disable Rx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
}
}
/* Reset Tx and Rx transfer counters */
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
/* Check error during Abort procedure */
if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
{
/* return HAL_Error in case of error during Abort procedure */
errorcode = HAL_ERROR;
}
else
{
/* Reset errorCode */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
}
/* Clear the Error flags in the SR register */
__HAL_SPI_CLEAR_OVRFLAG(hspi);
/* Restore hspi->state to ready */
hspi->State = HAL_SPI_STATE_READY;
return errorcode;
}
/**
* @brief Abort ongoing transfer (Interrupt mode).
* @param hspi SPI handle.
* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
* started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable SPI Interrupts (depending of transfer direction)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode;
uint32_t abortcplt ;
__IO uint32_t count;
__IO uint32_t resetcount;
/* Initialized local variable */
errorcode = HAL_OK;
abortcplt = 1U;
resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
count = resetcount;
/* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
/* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
{
hspi->TxISR = SPI_AbortTx_ISR;
/* Wait HAL_SPI_STATE_ABORT state */
do
{
if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
count--;
} while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
{
hspi->RxISR = SPI_AbortRx_ISR;
/* Wait HAL_SPI_STATE_ABORT state */
do
{
if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
count--;
} while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
if (hspi->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
Otherwise, set it to NULL */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
{
hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
}
else
{
hspi->hdmatx->XferAbortCallback = NULL;
}
}
/* DMA Rx Handle is valid */
if (hspi->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
Otherwise, set it to NULL */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
{
hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
}
else
{
hspi->hdmarx->XferAbortCallback = NULL;
}
}
/* Disable the SPI DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
{
/* Abort the SPI DMA Tx Stream/Channel */
if (hspi->hdmatx != NULL)
{
/* Abort DMA Tx Handle linked to SPI Peripheral */
if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
{
hspi->hdmatx->XferAbortCallback = NULL;
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
else
{
abortcplt = 0U;
}
}
}
/* Disable the SPI DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
{
/* Abort the SPI DMA Rx Stream/Channel */
if (hspi->hdmarx != NULL)
{
/* Abort DMA Rx Handle linked to SPI Peripheral */
if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
{
hspi->hdmarx->XferAbortCallback = NULL;
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
else
{
abortcplt = 0U;
}
}
}
if (abortcplt == 1U)
{
/* Reset Tx and Rx transfer counters */
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
/* Check error during Abort procedure */
if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
{
/* return HAL_Error in case of error during Abort procedure */
errorcode = HAL_ERROR;
}
else
{
/* Reset errorCode */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
}
/* Clear the Error flags in the SR register */
__HAL_SPI_CLEAR_OVRFLAG(hspi);
/* Restore hspi->State to Ready */
hspi->State = HAL_SPI_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->AbortCpltCallback(hspi);
#else
HAL_SPI_AbortCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
return errorcode;
}
/**
* @brief Pause the DMA Transfer.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
{
/* Process Locked */
__HAL_LOCK(hspi);
/* Disable the SPI DMA Tx & Rx requests */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_OK;
}
/**
* @brief Resume the DMA Transfer.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
{
/* Process Locked */
__HAL_LOCK(hspi);
/* Enable the SPI DMA Tx & Rx requests */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_OK;
}
/**
* @brief Stop the DMA Transfer.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or
HAL_SPI_TxRxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or
HAL_SPI_TxRxCpltCallback()
*/
/* Abort the SPI DMA tx Stream/Channel */
if (hspi->hdmatx != NULL)
{
if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
}
}
/* Abort the SPI DMA rx Stream/Channel */
if (hspi->hdmarx != NULL)
{
if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
}
}
/* Disable the SPI DMA Tx & Rx requests */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
hspi->State = HAL_SPI_STATE_READY;
return errorcode;
}
/**
* @brief Handle SPI interrupt request.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval None
*/
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
{
uint32_t itsource = hspi->Instance->CR2;
uint32_t itflag = hspi->Instance->SR;
/* SPI in mode Receiver ----------------------------------------------------*/
if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
(SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
{
hspi->RxISR(hspi);
return;
}
/* SPI in mode Transmitter -------------------------------------------------*/
if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
{
hspi->TxISR(hspi);
return;
}
/* SPI in Error Treatment --------------------------------------------------*/
if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET))
&& (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
{
/* SPI Overrun error interrupt occurred ----------------------------------*/
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
{
if (hspi->State != HAL_SPI_STATE_BUSY_TX)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
else
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
return;
}
}
/* SPI Mode Fault error interrupt occurred -------------------------------*/
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
__HAL_SPI_CLEAR_MODFFLAG(hspi);
}
/* SPI Frame error interrupt occurred ------------------------------------*/
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
/* Disable all interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
hspi->State = HAL_SPI_STATE_READY;
/* Disable the SPI DMA requests if enabled */
if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
{
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
/* Abort the SPI DMA Rx channel */
if (hspi->hdmarx != NULL)
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
}
}
/* Abort the SPI DMA Tx channel */
if (hspi->hdmatx != NULL)
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
}
}
}
else
{
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
return;
}
}
/**
* @brief Tx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxCpltCallback should be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_RxCpltCallback should be implemented in the user file
*/
}
/**
* @brief Tx and Rx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxRxCpltCallback should be implemented in the user file
*/
}
/**
* @brief Tx Half Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
*/
}
/**
* @brief Rx Half Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
*/
}
/**
* @brief Tx and Rx Half Transfer callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
*/
}
/**
* @brief SPI error callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_ErrorCallback should be implemented in the user file
*/
/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
and user can use HAL_SPI_GetError() API to check the latest error occurred
*/
}
/**
* @brief SPI Abort Complete callback.
* @param hspi SPI handle.
* @retval None
*/
__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_AbortCpltCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief SPI control functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the SPI.
(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
@endverbatim
* @{
*/
/**
* @brief Return the SPI handle state.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval SPI state
*/
HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi)
{
/* Return SPI handle state */
return hspi->State;
}
/**
* @brief Return the SPI error code.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval SPI error code in bitmap format
*/
uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi)
{
/* Return SPI ErrorCode */
return hspi->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup SPI_Private_Functions
* @brief Private functions
* @{
*/
/**
* @brief DMA SPI transmit process complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* DMA Normal Mode */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
{
/* Disable ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
/* Disable Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Clear overrun flag in 2 Lines communication mode because received data is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
hspi->TxXferCount = 0U;
hspi->State = HAL_SPI_STATE_READY;
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
/* Call user Tx complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->TxCpltCallback(hspi);
#else
HAL_SPI_TxCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPI receive process complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* DMA Normal Mode */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
{
/* Disable ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
#if (USE_SPI_CRC != 0U)
/* CRC handling */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until RXNE flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC */
tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
}
#endif /* USE_SPI_CRC */
/* Check if we are in Master RX 2 line mode */
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
}
else
{
/* Normal case */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
}
/* Check the end of the transaction */
if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
hspi->RxXferCount = 0U;
hspi->State = HAL_SPI_STATE_READY;
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
/* Check if CRC error is valid or not (workaround to be applied or not) */
if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Reset CRC Calculation */
SPI_RESET_CRC(hspi);
}
else
{
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
#endif /* USE_SPI_CRC */
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
/* Call user Rx complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->RxCpltCallback(hspi);
#else
HAL_SPI_RxCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPI transmit receive process complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* DMA Normal Mode */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
{
/* Disable ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
#if (USE_SPI_CRC != 0U)
/* CRC handling */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait the CRC data */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC to Flush DR and RXNE flag */
tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Disable Rx/Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
hspi->TxXferCount = 0U;
hspi->RxXferCount = 0U;
hspi->State = HAL_SPI_STATE_READY;
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
/* Check if CRC error is valid or not (workaround to be applied or not) */
if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Reset CRC Calculation */
SPI_RESET_CRC(hspi);
}
else
{
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
#endif /* USE_SPI_CRC */
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
/* Call user TxRx complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->TxRxCpltCallback(hspi);
#else
HAL_SPI_TxRxCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPI half transmit process complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user Tx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->TxHalfCpltCallback(hspi);
#else
HAL_SPI_TxHalfCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPI half receive process complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user Rx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->RxHalfCpltCallback(hspi);
#else
HAL_SPI_RxHalfCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPI half transmit receive process complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user TxRx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->TxRxHalfCpltCallback(hspi);
#else
HAL_SPI_TxRxHalfCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPI communication error callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
hspi->State = HAL_SPI_STATE_READY;
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPI communication abort callback, when initiated by HAL services on Error
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPI Tx communication abort callback, when initiated by user
* (To be called at end of DMA Tx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Rx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
__IO uint32_t count;
hspi->hdmatx->XferAbortCallback = NULL;
count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Disable Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
/* Wait until TXE flag is set */
do
{
if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
count--;
} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Check if an Abort process is still ongoing */
if (hspi->hdmarx != NULL)
{
if (hspi->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
/* Check no error during Abort procedure */
if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
{
/* Reset errorCode */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
}
/* Clear the Error flags in the SR register */
__HAL_SPI_CLEAR_OVRFLAG(hspi);
/* Restore hspi->State to Ready */
hspi->State = HAL_SPI_STATE_READY;
/* Call user Abort complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->AbortCpltCallback(hspi);
#else
HAL_SPI_AbortCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPI Rx communication abort callback, when initiated by user
* (To be called at end of DMA Rx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Tx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
hspi->hdmarx->XferAbortCallback = NULL;
/* Disable Rx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
/* Check Busy flag */
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
}
/* Check if an Abort process is still ongoing */
if (hspi->hdmatx != NULL)
{
if (hspi->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
/* Check no error during Abort procedure */
if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
{
/* Reset errorCode */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
}
/* Clear the Error flags in the SR register */
__HAL_SPI_CLEAR_OVRFLAG(hspi);
/* Restore hspi->State to Ready */
hspi->State = HAL_SPI_STATE_READY;
/* Call user Abort complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->AbortCpltCallback(hspi);
#else
HAL_SPI_AbortCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 8bit mode */
*hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
hspi->pRxBuffPtr++;
hspi->RxXferCount--;
/* Check end of the reception */
if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_2linesRxISR_8BITCRC;
return;
}
#endif /* USE_SPI_CRC */
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
#if (USE_SPI_CRC != 0U)
/**
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
__IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
/* Initialize the 8bit temporary pointer */
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
/* Read 8bit CRC to flush Data Register */
tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
UNUSED(tmpreg8);
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
#endif /* USE_SPI_CRC */
/**
* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
*(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
/* Check the end of the transmission */
if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Set CRC Next Bit to send CRC */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
return;
}
#endif /* USE_SPI_CRC */
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
if (hspi->RxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
/**
* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_2linesRxISR_16BITCRC;
return;
}
#endif /* USE_SPI_CRC */
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
__IO uint32_t tmpreg = 0U;
/* Read 16bit CRC to flush Data Register */
tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
SPI_CloseRxTx_ISR(hspi);
}
#endif /* USE_SPI_CRC */
/**
* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in 16 Bit mode */
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
/* Enable CRC Transmission */
if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Set CRC Next Bit to send CRC */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
return;
}
#endif /* USE_SPI_CRC */
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
if (hspi->RxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 8-bit receive in Interrupt context.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
__IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
/* Initialize the 8bit temporary pointer */
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
/* Read 8bit CRC to flush Data Register */
tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
UNUSED(tmpreg8);
SPI_CloseRx_ISR(hspi);
}
#endif /* USE_SPI_CRC */
/**
* @brief Manage the receive 8-bit in Interrupt context.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
*hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
hspi->pRxBuffPtr++;
hspi->RxXferCount--;
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
/* Check if CRCNEXT is well reset by hardware */
if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
{
/* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_RxISR_8BITCRC;
return;
}
#endif /* USE_SPI_CRC */
SPI_CloseRx_ISR(hspi);
}
}
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 16-bit receive in Interrupt context.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
__IO uint32_t tmpreg = 0U;
/* Read 16bit CRC to flush Data Register */
tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
SPI_CloseRx_ISR(hspi);
}
#endif /* USE_SPI_CRC */
/**
* @brief Manage the 16-bit receive in Interrupt context.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
/* Check if CRCNEXT is well reset by hardware */
if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
{
/* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_RxISR_16BITCRC;
return;
}
#endif /* USE_SPI_CRC */
SPI_CloseRx_ISR(hspi);
}
}
/**
* @brief Handle the data 8-bit transmit in Interrupt mode.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
*(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
SPI_CloseTx_ISR(hspi);
}
}
/**
* @brief Handle the data 16-bit transmit in Interrupt mode.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in 16 Bit mode */
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
SPI_CloseTx_ISR(hspi);
}
}
/**
* @brief Handle SPI Communication Timeout.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param Flag SPI flag to check
* @param State flag state to check
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
tmp_tickstart = HAL_GetTick();
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
{
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return HAL_TIMEOUT;
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
{
tmp_timeout = 0U;
}
count--;
}
}
return HAL_OK;
}
/**
* @brief Handle the check of the RX transaction complete.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))
{
/* Wait the RXNE reset */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
}
else
{
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @brief Handle the check of the RXTX or TX transaction complete.
* @param hspi SPI handle
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
/* Wait until TXE flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
return HAL_OK;
}
/**
* @brief Handle the end of the RXTX transaction.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
uint32_t tickstart;
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Disable ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
/* Wait until TXE flag is set */
do
{
if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
break;
}
count--;
} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
/* Check if CRC error is valid or not (workaround to be applied or not) */
if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
{
hspi->State = HAL_SPI_STATE_READY;
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Reset CRC Calculation */
SPI_RESET_CRC(hspi);
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
else
{
#endif /* USE_SPI_CRC */
if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_READY;
/* Call user Rx complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->RxCpltCallback(hspi);
#else
HAL_SPI_RxCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
hspi->State = HAL_SPI_STATE_READY;
/* Call user TxRx complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->TxRxCpltCallback(hspi);
#else
HAL_SPI_TxRxCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
else
{
hspi->State = HAL_SPI_STATE_READY;
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
#if (USE_SPI_CRC != 0U)
}
#endif /* USE_SPI_CRC */
}
/**
* @brief Handle the end of the RX transaction.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
{
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
/* Check the end of the transaction */
if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
/* Check if CRC error is valid or not (workaround to be applied or not) */
if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Reset CRC Calculation */
SPI_RESET_CRC(hspi);
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
else
{
#endif /* USE_SPI_CRC */
if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
/* Call user Rx complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->RxCpltCallback(hspi);
#else
HAL_SPI_RxCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
#if (USE_SPI_CRC != 0U)
}
#endif /* USE_SPI_CRC */
}
/**
* @brief Handle the end of the TX transaction.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
uint32_t tickstart;
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Wait until TXE flag is set */
do
{
if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
break;
}
count--;
} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Disable TXE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
/* Call user Rx complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->TxCpltCallback(hspi);
#else
HAL_SPI_TxCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
/**
* @brief Handle abort a Rx transaction.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
{
__IO uint32_t tmpreg = 0U;
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Wait until TXE flag is set */
do
{
if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
count--;
} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
/* Flush Data Register by a blank read */
tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
hspi->State = HAL_SPI_STATE_ABORT;
}
/**
* @brief Handle abort a Tx or Rx/Tx transaction.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
{
/* Disable TXEIE interrupt */
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
hspi->State = HAL_SPI_STATE_ABORT;
}
#if (USE_SPI_CRC != 0U)
/**
* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
* according to SPI instance, Device type, and revision ID.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
*/
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
{
#if defined(SPI_CRC_ERROR_WORKAROUND_FEATURE) && (USE_SPI_CRC_ERROR_WORKAROUND != 0U)
/* Check how to handle this CRC error (workaround to be applied or not) */
/* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES
(DocID14732 Rev 13)) */
if (hspi->Instance == SPI2)
{
if (hspi->Instance->RXCRCR == 0U)
{
return (SPI_INVALID_CRC_ERROR);
}
}
#endif /* USE_SPI_CRC_ERROR_WORKAROUND */
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
return (SPI_VALID_CRC_ERROR);
}
#endif /* USE_SPI_CRC */
/**
* @}
*/
#endif /* HAL_SPI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

191
john103C6T6/MDK-ARM/john103C6T6.uvoptx
View File

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<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_hal_i2c.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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<File>
<GroupNumber>3</GroupNumber>
<FileNumber>37</FileNumber>
<FileType>1</FileType>
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<tvExpOptDlg>0</tvExpOptDlg>
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<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_hal_rtc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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<File>
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<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_hal_rtc_ex.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<File>
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<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_hal_spi.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -704,7 +817,7 @@
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<File>
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<FileNumber>32</FileNumber>
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -716,7 +829,7 @@
</File>
<File>
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<FileNumber>33</FileNumber>
<FileNumber>42</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@@ -736,7 +849,7 @@
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>34</FileNumber>
<FileNumber>43</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>

506
john103C6T6/MDK-ARM/john103C6T6.uvprojx
View File

@@ -133,7 +133,7 @@
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4101</DriverSelection>
</Flash1>
@@ -501,6 +501,230 @@
</FileArmAds>
</FileOption>
</File>
<File>
<FileName>can.c</FileName>
<FileType>1</FileType>
<FilePath>../Core/Src/can.c</FilePath>
<FileOption>
<CommonProperty>
<UseCPPCompiler>2</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
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<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
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</FileArmAds>
</FileOption>
</File>
<File>
<FileName>i2c.c</FileName>
<FileType>1</FileType>
<FilePath>../Core/Src/i2c.c</FilePath>
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@@ -698,6 +922,286 @@
<FileType>1</FileType>
<FilePath>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c</FilePath>
</File>
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<FileName>stm32f1xx_hal_can.c</FileName>
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<CustomArgument></CustomArgument>
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90
john103C6T6/john103C6T6.ioc
View File

@@ -9,19 +9,27 @@ ADC1.master=1
CAD.formats=
CAD.pinconfig=
CAD.provider=
CAN.CalculateBaudRate=749999
CAN.CalculateTimeBit=1333
CAN.CalculateTimeQuantum=444.44444444444446
CAN.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate
File.Version=6
GPIO.groupedBy=Group By Peripherals
KeepUserPlacement=false
Mcu.CPN=STM32F103C6T6A
Mcu.Family=STM32F1
Mcu.IP0=ADC1
Mcu.IP1=NVIC
Mcu.IP2=RCC
Mcu.IP3=SYS
Mcu.IP4=TIM1
Mcu.IP5=TIM2
Mcu.IP6=USART1
Mcu.IPNb=7
Mcu.IP1=CAN
Mcu.IP10=USART1
Mcu.IP2=I2C1
Mcu.IP3=NVIC
Mcu.IP4=RCC
Mcu.IP5=RTC
Mcu.IP6=SPI1
Mcu.IP7=SYS
Mcu.IP8=TIM1
Mcu.IP9=TIM2
Mcu.IPNb=11
Mcu.Name=STM32F103C(4-6)Tx
Mcu.Package=LQFP48
Mcu.Pin0=PC13-TAMPER-RTC
@@ -40,22 +48,32 @@ Mcu.Pin2=PD1-OSC_OUT
Mcu.Pin20=PA8
Mcu.Pin21=PA9
Mcu.Pin22=PA10
Mcu.Pin23=PA13
Mcu.Pin24=PA14
Mcu.Pin25=PB6
Mcu.Pin26=PB7
Mcu.Pin27=VP_ADC1_Vref_Input
Mcu.Pin28=VP_SYS_VS_tim3
Mcu.Pin29=VP_TIM1_VS_ClockSourceINT
Mcu.Pin23=PA11
Mcu.Pin24=PA12
Mcu.Pin25=PA13
Mcu.Pin26=PA14
Mcu.Pin27=PB3
Mcu.Pin28=PB4
Mcu.Pin29=PB5
Mcu.Pin3=PA0-WKUP
Mcu.Pin30=VP_TIM2_VS_ClockSourceINT
Mcu.Pin30=PB6
Mcu.Pin31=PB7
Mcu.Pin32=PB8
Mcu.Pin33=PB9
Mcu.Pin34=VP_ADC1_TempSens_Input
Mcu.Pin35=VP_ADC1_Vref_Input
Mcu.Pin36=VP_RTC_VS_RTC_Activate
Mcu.Pin37=VP_RTC_VS_RTC_Calendar
Mcu.Pin38=VP_SYS_VS_tim3
Mcu.Pin39=VP_TIM1_VS_ClockSourceINT
Mcu.Pin4=PA1
Mcu.Pin40=VP_TIM2_VS_ClockSourceINT
Mcu.Pin5=PA2
Mcu.Pin6=PA3
Mcu.Pin7=PA4
Mcu.Pin8=PA5
Mcu.Pin9=PA6
Mcu.PinsNb=31
Mcu.PinsNb=41
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F103C6Tx
@@ -83,13 +101,14 @@ NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA0-WKUP.Locked=true
PA0-WKUP.Signal=GPIO_Input
PA1.GPIOParameters=GPIO_Speed,GPIO_Label
PA1.GPIO_Label=One-wire
PA1.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PA1.Locked=true
PA1.Signal=GPIO_Output
PA10.Locked=true
PA10.Signal=GPIO_Output
PA11.Mode=CAN_Activate
PA11.Signal=CAN_RX
PA12.Mode=CAN_Activate
PA12.Signal=CAN_TX
PA13.Mode=Serial_Wire
PA13.Signal=SYS_JTMS-SWDIO
PA14.Mode=Serial_Wire
@@ -128,12 +147,22 @@ PB15.Locked=true
PB15.Signal=GPIO_Output
PB2.Locked=true
PB2.Signal=GPIO_Output
PB3.Mode=Full_Duplex_Master
PB3.Signal=SPI1_SCK
PB4.Mode=Full_Duplex_Master
PB4.Signal=SPI1_MISO
PB5.Mode=Full_Duplex_Master
PB5.Signal=SPI1_MOSI
PB6.Mode=Asynchronous
PB6.Signal=USART1_TX
PB7.Mode=Asynchronous
PB7.Signal=USART1_RX
PC13-TAMPER-RTC.Locked=true
PC13-TAMPER-RTC.Signal=GPIO_Output
PB8.Mode=I2C
PB8.Signal=I2C1_SCL
PB9.Mode=I2C
PB9.Signal=I2C1_SDA
PC13-TAMPER-RTC.Mode=Tamper
PC13-TAMPER-RTC.Signal=RTC_TAMPER
PD0-OSC_IN.Mode=HSE-External-Oscillator
PD0-OSC_IN.Signal=RCC_OSC_IN
PD1-OSC_OUT.Mode=HSE-External-Oscillator
@@ -169,7 +198,7 @@ ProjectManager.ToolChainLocation=
ProjectManager.UAScriptAfterPath=
ProjectManager.UAScriptBeforePath=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_TIM1_Init-TIM1-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_TIM2_Init-TIM2-false-HAL-true
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_TIM1_Init-TIM1-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_TIM2_Init-TIM2-false-HAL-true,6-MX_ADC1_Init-ADC1-false-HAL-true
RCC.ADCFreqValue=12000000
RCC.ADCPresc=RCC_ADCPCLK2_DIV6
RCC.AHBFreq_Value=72000000
@@ -181,7 +210,7 @@ RCC.APB2TimFreq_Value=72000000
RCC.FCLKCortexFreq_Value=72000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=72000000
RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,USBPrescaler,VCOOutput2Freq_Value
RCC.MCOFreq_Value=72000000
RCC.PLLCLKFreq_Value=72000000
RCC.PLLMCOFreq_Value=36000000
@@ -190,8 +219,15 @@ RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.SYSCLKFreq_VALUE=72000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.TimSysFreq_Value=72000000
RCC.USBFreq_Value=72000000
RCC.USBFreq_Value=48000000
RCC.USBPrescaler=RCC_USBCLKSOURCE_PLL_DIV1_5
RCC.VCOOutput2Freq_Value=8000000
SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
SPI1.CalculateBaudRate=36.0 MBits/s
SPI1.Direction=SPI_DIRECTION_2LINES
SPI1.IPParameters=VirtualType,Mode,Direction,BaudRatePrescaler,CalculateBaudRate
SPI1.Mode=SPI_MODE_MASTER
SPI1.VirtualType=VM_MASTER
TIM1.IPParameters=Prescaler,Period
TIM1.Period=65535
TIM1.Prescaler=0
@@ -200,8 +236,14 @@ TIM2.Period=65535
TIM2.Prescaler=7199
USART1.IPParameters=VirtualMode
USART1.VirtualMode=VM_ASYNC
VP_ADC1_TempSens_Input.Mode=IN-TempSens
VP_ADC1_TempSens_Input.Signal=ADC1_TempSens_Input
VP_ADC1_Vref_Input.Mode=IN-Vrefint
VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar
VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar
VP_SYS_VS_tim3.Mode=TIM3
VP_SYS_VS_tim3.Signal=SYS_VS_tim3
VP_TIM1_VS_ClockSourceINT.Mode=Internal