init commit.
Проект каким он достался от Димы.
This commit is contained in:
@@ -0,0 +1,1879 @@
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// TI File $Revision: /main/10 $
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// Checkin $Date: April 21, 2008 15:43:40 $
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//###########################################################################
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//
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// FILE: Example_2833xSWPrioritizedDefaultIsr.c
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//
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// TITLE: DSP2833x Device Default Software Prioritized Interrupt Service Routines.
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//
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// This file is based on the standard DSP2833x_SWPrioritizedDefaultIsr.c
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// The ISR routines have been modified slightly to provide a trace
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// mechanism used for this example
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//
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//###########################################################################
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//
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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#include "DSP2833x_SWPrioritizedIsrLevels.h"
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// Defined in the Example_28xSWPrioritizedInterrupts.c file
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// for this example only
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extern Uint16 ISRTrace[50];
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extern Uint16 ISRTraceIndex;
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// Used for ISR delays
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Uint16 i;
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// Connected to INT13 of CPU (use MINT13 mask):
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// Note CPU-Timer1 is reserved for TI use, however XINT13
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// ISR can be used by the user.
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#if (INT13PL != 0)
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interrupt void INT13_ISR(void) // INT13 or CPU-Timer1
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{
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IER |= MINT13; // Set "global" priority
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EINT;
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// Insert ISR Code here
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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#endif
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// Connected to INT14 of CPU (use MINT14 mask):
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#if (INT14PL != 0)
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interrupt void INT14_ISR(void) // CPU-Timer2
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{
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IER |= MINT14; // Set "global" priority
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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#endif
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// Connected to int15 of CPU (use MINT15 mask):
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#if (INT15PL != 0)
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interrupt void DATALOG_ISR(void) // Datalogging interrupt
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{
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IER |= MINT15; // Set "global" priority
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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#endif
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// Connected to int16 of CPU (use MINT16 mask):
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#if (INT16PL != 0)
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interrupt void RTOSINT_ISR(void) // RTOS interrupt
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{
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IER |= MINT16; // Set "global" priority
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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#endif
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// Connected to EMUINT of CPU (non-maskable):
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interrupt void EMUINT_ISR(void) // Emulation interrupt
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to NMI of CPU (non-maskable):
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interrupt void NMI_ISR(void) // Non-maskable interrupt
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to ITRAP of CPU (non-maskable):
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interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER1 of CPU (non-maskable):
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interrupt void USER1_ISR(void) // User Defined trap 1
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER2 of CPU (non-maskable):
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interrupt void USER2_ISR(void) // User Defined trap 2
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER3 of CPU (non-maskable):
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interrupt void USER3_ISR(void) // User Defined trap 3
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER4 of CPU (non-maskable):
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interrupt void USER4_ISR(void) // User Defined trap 4
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER5 of CPU (non-maskable):
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interrupt void USER5_ISR(void) // User Defined trap 5
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER6 of CPU (non-maskable):
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interrupt void USER6_ISR(void) // User Defined trap 6
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER7 of CPU (non-maskable):
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interrupt void USER7_ISR(void) // User Defined trap 7
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER8 of CPU (non-maskable):
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interrupt void USER8_ISR(void) // User Defined trap 8
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER9 of CPU (non-maskable):
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interrupt void USER9_ISR(void) // User Defined trap 9
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER10 of CPU (non-maskable):
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interrupt void USER10_ISR(void) // User Defined trap 10
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER11 of CPU (non-maskable):
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interrupt void USER11_ISR(void) // User Defined trap 11
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// Connected to USER12 of CPU (non-maskable):
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interrupt void USER12_ISR(void) // User Defined trap 12
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{
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EINT;
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// Insert ISR Code here.......
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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asm (" ESTOP0");
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for(;;);
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}
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// -----------------------------------------------------------
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// PIE Group 1 - MUXed into CPU INT1
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// -----------------------------------------------------------
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// Connected to PIEIER1_1 (use MINT1 and MG11 masks):
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#if (G11PL != 0)
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interrupt void SEQ1INT_ISR( void ) // ADC
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{
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
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IER |= M_INT1;
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IER &= MINT1; // Set "global" priority
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PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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// Insert ISR Code here.......
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for(i = 1; i <= 10; i++) {}
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// Restore registers saved:
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DINT;
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PieCtrlRegs.PIEIER1.all = TempPIEIER;
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// Add ISR to Trace
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ISRTrace[ISRTraceIndex] = 0x0011;
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ISRTraceIndex++;
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}
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#endif
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// Connected to PIEIER1_2 (use MINT1 and MG12 masks):
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#if (G12PL != 0)
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interrupt void SEQ2INT_ISR( void ) // ADC
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{
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
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IER |= M_INT1;
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IER &= MINT1; // Set "global" priority
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PieCtrlRegs.PIEIER1.all &= MG12; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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// Insert ISR Code here.......
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for(i = 1; i <= 10; i++) {}
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// Restore registers saved:
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DINT;
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PieCtrlRegs.PIEIER1.all = TempPIEIER;
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// Add ISR to Trace
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ISRTrace[ISRTraceIndex] = 0x0012;
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ISRTraceIndex++;
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}
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#endif
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// Connected to PIEIER1_4 (use MINT1 and MG14 masks):
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#if (G14PL != 0)
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interrupt void XINT1_ISR(void)
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{
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
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IER |= M_INT1;
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IER &= MINT1; // Set "global" priority
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PieCtrlRegs.PIEIER1.all &= MG14; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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// Insert ISR Code here.......
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asm(" NOP");
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// Restore registers saved:
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DINT;
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PieCtrlRegs.PIEIER1.all = TempPIEIER;
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// Add ISR to Trace
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ISRTrace[ISRTraceIndex] = 0x0014;
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ISRTraceIndex++;
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}
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#endif
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// Connected to PIEIER1_5 (use MINT1 and MG15 masks):
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#if (G15PL != 0)
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interrupt void XINT2_ISR(void)
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{
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
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IER |= M_INT1;
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IER &= MINT1; // Set "global" priority
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PieCtrlRegs.PIEIER1.all &= MG15; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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// Insert ISR Code here.......
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for(i = 1; i <= 10; i++) {}
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// Restore registers saved:
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DINT;
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PieCtrlRegs.PIEIER1.all = TempPIEIER;
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// Add ISR to Trace
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ISRTrace[ISRTraceIndex] = 0x0015;
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ISRTraceIndex++;
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}
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#endif
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// Connected to PIEIER1_6 (use MINT1 and MG16 masks):
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#if (G16PL != 0)
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interrupt void ADCINT_ISR(void) // ADC
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{
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
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IER |= M_INT1;
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IER &= MINT1; // Set "global" priority
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PieCtrlRegs.PIEIER1.all &= MG16; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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|
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// Insert ISR Code here.......
|
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for(i = 1; i <= 10; i++) {}
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// Restore registers saved:
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DINT;
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PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
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|
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// Add ISR to Trace
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ISRTrace[ISRTraceIndex] = 0x0016;
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ISRTraceIndex++;
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}
|
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#endif
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// Connected to PIEIER1_7 (use MINT1 and MG17 masks):
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#if (G17PL != 0)
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interrupt void TINT0_ISR(void) // CPU-Timer 0
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{
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// Set interrupt priority:
|
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
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IER |= M_INT1;
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IER &= MINT1; // Set "global" priority
|
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PieCtrlRegs.PIEIER1.all &= MG17; // Set "group" priority
|
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
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EINT;
|
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|
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// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
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|
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// Restore registers saved:
|
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DINT;
|
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PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
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|
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// Add ISR to Trace
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ISRTrace[ISRTraceIndex] = 0x0017;
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ISRTraceIndex++;
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}
|
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#endif
|
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|
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// Connected to PIEIER1_8 (use MINT1 and MG18 masks):
|
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#if (G18PL != 0)
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interrupt void WAKEINT_ISR(void) // WD/LPM
|
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{
|
||||
// Set interrupt priority:
|
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
|
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IER |= M_INT1;
|
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IER &= MINT1; // Set "global" priority
|
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PieCtrlRegs.PIEIER1.all &= MG18; // Set "group" priority
|
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
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EINT;
|
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|
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// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
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|
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// Restore registers saved:
|
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DINT;
|
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PieCtrlRegs.PIEIER1.all = TempPIEIER;
|
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|
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// Add ISR to Trace
|
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ISRTrace[ISRTraceIndex] = 0x0018;
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ISRTraceIndex++;
|
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}
|
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#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 2 - MUXed into CPU INT2
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER2_1 (use MINT2 and MG21 masks):
|
||||
#if (G21PL != 0)
|
||||
interrupt void EPWM1_TZINT_ISR(void) // ePWM1 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
//Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0021;
|
||||
ISRTraceIndex++;
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_2 (use MINT2 and MG22 masks):
|
||||
#if (G22PL != 0)
|
||||
interrupt void EPWM2_TZINT_ISR(void) // ePWM2 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG22; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0022;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_3 (use MINT2 and MG23 masks):
|
||||
#if (G23PL != 0)
|
||||
interrupt void EPWM3_TZINT_ISR(void) // ePWM3 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG23; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0023;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_4 (use MINT2 and MG24 masks):
|
||||
#if (G24PL != 0)
|
||||
interrupt void EPWM4_TZINT_ISR(void) // ePWM4 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0024;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_5 (use MINT2 and MG25 masks):
|
||||
#if (G25PL != 0)
|
||||
interrupt void EPWM5_TZINT_ISR(void) // ePWM5 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG25; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0025;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER2_6 (use MINT2 and MG26 masks):
|
||||
#if (G26PL != 0)
|
||||
interrupt void EPWM6_TZINT_ISR(void) // ePWM6 Trip Zone
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
|
||||
IER |= M_INT2;
|
||||
IER &= MINT2; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER2.all &= MG26; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER2.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0026;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 3 - MUXed into CPU INT3
|
||||
// -----------------------------------------------------------
|
||||
|
||||
|
||||
// Connected to PIEIER3_1 (use MINT3 and MG31 masks):
|
||||
#if (G31PL != 0)
|
||||
interrupt void EPWM1_INT_ISR(void) // ePWM1 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0031;
|
||||
ISRTraceIndex++;
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_2 (use MINT3 and MG32 masks):
|
||||
#if (G32PL != 0)
|
||||
interrupt void EPWM2_INT_ISR(void) // ePWM2 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG32; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0032;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_3 (use MINT3 and MG33 masks):
|
||||
#if (G33PL != 0)
|
||||
interrupt void EPWM3_INT_ISR(void) // ePWM3 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG33; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0033;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_4 (use MINT3 and MG34 masks):
|
||||
#if (G34PL != 0)
|
||||
interrupt void EPWM4_INT_ISR(void) // ePWM4 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG34; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0034;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_5 (use MINT3 and MG35 masks):
|
||||
#if (G35PL != 0)
|
||||
interrupt void EPWM5_INT_ISR(void) // ePWM5 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG35; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0035;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER3_6 (use MINT3 and MG36 masks):
|
||||
#if (G36PL != 0)
|
||||
interrupt void EPWM6_INT_ISR(void) // ePWM6 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all;
|
||||
IER |= M_INT3;
|
||||
IER &= MINT3; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER3.all &= MG36; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER3.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0036;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 4 - MUXed into CPU INT4
|
||||
// -----------------------------------------------------------
|
||||
|
||||
|
||||
// Connected to PIEIER4_1 (use MINT4 and MG41 masks):
|
||||
#if (G41PL != 0)
|
||||
interrupt void ECAP1_INT_ISR(void) // eCAP1 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG41; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0041;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_2 (use MINT4 and MG42 masks):
|
||||
#if (G42PL != 0)
|
||||
interrupt void ECAP2_INT_ISR(void) // eCAP2 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG42; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0042;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_3 (use MINT4 and MG43 masks):
|
||||
#if (G43PL != 0)
|
||||
interrupt void ECAP3_INT_ISR(void) // eCAP3 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG43; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0043;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_4 (use MINT4 and MG44 masks):
|
||||
#if (G44PL != 0)
|
||||
interrupt void ECAP4_INT_ISR(void) // eCAP4 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0044;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_5 (use MINT4 and MG45 masks):
|
||||
#if (G44PL != 0)
|
||||
interrupt void ECAP5_INT_ISR(void) // eCAP5 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG45; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0045;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER4_6 (use MINT4 and MG46 masks):
|
||||
#if (G44PL != 0)
|
||||
interrupt void ECAP6_INT_ISR(void) // eCAP6 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all;
|
||||
IER |= M_INT4;
|
||||
IER &= MINT4; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER4.all &= MG46; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER4.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0046;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 5 - MUXed into CPU INT5
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER5_1 (use MINT5 and MG51 masks):
|
||||
#if (G51PL != 0)
|
||||
interrupt void EQEP1_INT_ISR(void) // eQEP1 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
|
||||
IER |= M_INT5;
|
||||
IER &= MINT5; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER5.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0051;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER5_2 (use MINT5 and MG52 masks):
|
||||
#if (G52PL != 0)
|
||||
interrupt void EQEP2_INT_ISR(void) // eQEP2 Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all;
|
||||
IER |= M_INT5;
|
||||
IER &= MINT5; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER5.all &= MG52; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER5.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0052;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 6 - MUXed into CPU INT6
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER6_1 (use MINT6 and MG61 masks):
|
||||
#if (G61PL != 0)
|
||||
interrupt void SPIRXINTA_ISR(void) // SPI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG61; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0061;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_2 (use MINT6 and MG62 masks):
|
||||
#if (G62PL != 0)
|
||||
interrupt void SPITXINTA_ISR(void) // SPI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG62; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0062;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_3 (use MINT6 and MG63 masks):
|
||||
#if (G63PL != 0)
|
||||
interrupt void MRINTB_ISR(void) // McBSP-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG63; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0063;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_4 (use MINT6 and MG64 masks):
|
||||
#if (G64PL != 0)
|
||||
interrupt void MXINTB_ISR(void) // McBSP-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG64; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0064;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// Connected to PIEIER6_5 (use MINT6 and MG65 masks):
|
||||
#if (G65PL != 0)
|
||||
interrupt void MRINTA_ISR(void) // McBSP-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG65; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0065;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER6_6 (use MINT6 and MG66 masks):
|
||||
#if (G66PL != 0)
|
||||
interrupt void MXINTA_ISR(void) // McBSP-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
|
||||
IER |= M_INT6;
|
||||
IER &= MINT6; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER6.all &= MG66; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER6.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0066;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 7 - MUXed into CPU INT7
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER7_1 (use MINT7 and MG71 masks):
|
||||
#if (G71PL != 0)
|
||||
interrupt void DINTCH1_ISR(void) // DMA-Channel 1
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG71; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0071;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_2 (use MINT7 and MG72 masks):
|
||||
#if (G72PL != 0)
|
||||
interrupt void DINTCH2_ISR(void) // DMA-Channel 2
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG72; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0072;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_3 (use MINT7 and MG73 masks):
|
||||
#if (G73PL != 0)
|
||||
interrupt void DINTCH3_ISR(void) // DMA-Channel 3
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG73; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0073;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_4 (use MINT7 and MG74 masks):
|
||||
#if (G74PL != 0)
|
||||
interrupt void DINTCH4_ISR(void) // DMA-Channel 4
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG74; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0074;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_5 (use MINT7 and MG75 masks):
|
||||
#if (G75PL != 0)
|
||||
interrupt void DINTCH5_ISR(void) // DMA-Channel 5
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG75; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0075;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER7_6 (use MINT7 and MG76 masks):
|
||||
#if (G76PL != 0)
|
||||
interrupt void DINTCH6_ISR(void) // DMA-Channel 6
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER7.all;
|
||||
IER |= M_INT7;
|
||||
IER &= MINT7; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER7.all &= MG76; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER7.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0076;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 8 - MUXed into CPU INT8
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER8_1 (use MINT8 and MG81 masks):
|
||||
#if (G81PL != 0)
|
||||
interrupt void I2CINT1A_ISR(void) // I2C-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER8.all &= MG81; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0081;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER8_2 (use MINT8 and MG82 masks):
|
||||
#if (G82PL != 0)
|
||||
interrupt void I2CINT2A_ISR(void) // I2C-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER8.all &= MG82; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0082;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER8_5 (use MINT8 and MG85 masks):
|
||||
#if (G85PL != 0)
|
||||
interrupt void SCIRXINTC_ISR(void) // SCI-C
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER8.all &= MG85; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0085;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER8_6 (use MINT8 and MG86 masks):
|
||||
#if (G86PL != 0)
|
||||
interrupt void SCITXINTC_ISR(void) // SCI-C
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER8.all;
|
||||
IER |= M_INT8;
|
||||
IER &= MINT8; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER8.all &= MG86; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER8.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0086;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 9 - MUXed into CPU INT9
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER9_1 (use MINT9 and MG91 masks):
|
||||
#if (G91PL != 0)
|
||||
interrupt void SCIRXINTA_ISR(void) // SCI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0091;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_2 (use MINT9 and MG92 masks):
|
||||
#if (G92PL != 0)
|
||||
interrupt void SCITXINTA_ISR(void) // SCI-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0092;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Connected to PIEIER9_3 (use MINT9 and MG93 masks):
|
||||
#if (G93PL != 0)
|
||||
interrupt void SCIRXINTB_ISR(void) // SCI-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0093;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_4 (use MINT9 and MG94 masks):
|
||||
#if (G94PL != 0)
|
||||
interrupt void SCITXINTB_ISR(void) // SCI-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0094;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_5 (use MINT9 and MG95 masks):
|
||||
#if (G95PL != 0)
|
||||
interrupt void ECAN0INTA_ISR(void) // eCAN-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0095;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_6 (use MINT9 and MG96 masks):
|
||||
#if (G96PL != 0)
|
||||
interrupt void ECAN1INTA_ISR(void) // eCAN-A
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0096;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_7 (use MINT9 and MG97 masks):
|
||||
#if (G97PL != 0)
|
||||
interrupt void ECAN0INTB_ISR(void) // eCAN-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0097;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER9_8 (use MINT9 and MG98 masks):
|
||||
#if (G98PL != 0)
|
||||
interrupt void ECAN1INTB_ISR(void) // eCAN-B
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
|
||||
IER |= M_INT9;
|
||||
IER &= MINT9; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER9.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0098;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 10 - MUXed into CPU int10
|
||||
// -----------------------------------------------------------
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 11 - MUXed into CPU int11
|
||||
// -----------------------------------------------------------
|
||||
// -----------------------------------------------------------
|
||||
// PIE Group 12 - MUXed into CPU int12
|
||||
// -----------------------------------------------------------
|
||||
|
||||
// Connected to PIEIER12_1 (use MINT12 and MG121 masks):
|
||||
#if (G121PL != 0)
|
||||
interrupt void XINT3_ISR(void) // External Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG121; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0121;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_2 (use MINT12 and MG122 masks):
|
||||
#if (G122PL != 0)
|
||||
interrupt void XINT4_ISR(void) // External Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG122; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0122;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Connected to PIEIER12_3 (use MINT12 and MG123 masks):
|
||||
#if (G123PL != 0)
|
||||
interrupt void XINT5_ISR(void) // External Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG123; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0123;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_4 (use MINT12 and MG124 masks):
|
||||
#if (G124PL != 0)
|
||||
interrupt void XINT6_ISR(void) // External Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG124; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0124;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_5 (use MINT12 and MG125 masks):
|
||||
#if (G125PL != 0)
|
||||
interrupt void XINT7_ISR(void) // External Interrupt
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG125; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0125;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_7 (use MINT12 and MG127 masks):
|
||||
#if (G127PL != 0)
|
||||
interrupt void LVF_ISR(void) // FPA32
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG127; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0127;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
// Connected to PIEIER12_8 (use MINT12 and MG128 masks):
|
||||
#if (G128PL != 0)
|
||||
interrupt void LUF_ISR(void) // FPA32
|
||||
{
|
||||
// Set interrupt priority:
|
||||
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER12.all;
|
||||
IER |= M_INT12;
|
||||
IER &= MINT12; // Set "global" priority
|
||||
PieCtrlRegs.PIEIER12.all &= MG128; // Set "group" priority
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
|
||||
EINT;
|
||||
|
||||
// Insert ISR Code here.......
|
||||
for(i = 1; i <= 10; i++) {}
|
||||
|
||||
// Restore registers saved:
|
||||
DINT;
|
||||
PieCtrlRegs.PIEIER12.all = TempPIEIER;
|
||||
|
||||
// Add ISR to Trace
|
||||
ISRTrace[ISRTraceIndex] = 0x0128;
|
||||
ISRTraceIndex++;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Catch All Default ISRs:
|
||||
//
|
||||
|
||||
interrupt void PIE_RESERVED(void) // Reserved space. For test.
|
||||
{
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void INT_NOTUSED_ISR(void) // Reserved space. For test.
|
||||
{
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
interrupt void rsvd_ISR(void) // For test
|
||||
{
|
||||
asm (" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,597 @@
|
||||
// TI File $Revision: /main/10 $
|
||||
// Checkin $Date: April 21, 2008 15:43:45 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: Example_2833xSWPrioritizedInterrupts.c
|
||||
//
|
||||
// TITLE: DSP2833x Software Prioritized Interrupt Example.
|
||||
//
|
||||
// ASSUMPTIONS:
|
||||
//
|
||||
// This program requires the DSP2833x header files.
|
||||
//
|
||||
// As supplied, this project is configured for "boot to SARAM"
|
||||
// operation. The 2833x Boot Mode table is shown below.
|
||||
// For information on configuring the boot mode of an eZdsp,
|
||||
// please refer to the documentation included with the eZdsp,
|
||||
//
|
||||
// $Boot_Table:
|
||||
//
|
||||
// GPIO87 GPIO86 GPIO85 GPIO84
|
||||
// XA15 XA14 XA13 XA12
|
||||
// PU PU PU PU
|
||||
// ==========================================
|
||||
// 1 1 1 1 Jump to Flash
|
||||
// 1 1 1 0 SCI-A boot
|
||||
// 1 1 0 1 SPI-A boot
|
||||
// 1 1 0 0 I2C-A boot
|
||||
// 1 0 1 1 eCAN-A boot
|
||||
// 1 0 1 0 McBSP-A boot
|
||||
// 1 0 0 1 Jump to XINTF x16
|
||||
// 1 0 0 0 Jump to XINTF x32
|
||||
// 0 1 1 1 Jump to OTP
|
||||
// 0 1 1 0 Parallel GPIO I/O boot
|
||||
// 0 1 0 1 Parallel XINTF boot
|
||||
// 0 1 0 0 Jump to SARAM <- "boot to SARAM"
|
||||
// 0 0 1 1 Branch to check boot mode
|
||||
// 0 0 1 0 Boot to flash, bypass ADC cal
|
||||
// 0 0 0 1 Boot to SARAM, bypass ADC cal
|
||||
// 0 0 0 0 Boot to SCI-A, bypass ADC cal
|
||||
// Boot_Table_End$
|
||||
//
|
||||
// DESCRIPTION:
|
||||
//
|
||||
// For most applications, the hardware prioritization of the
|
||||
// the PIE module is sufficient. For applications that need custom
|
||||
// prioritization, this example illustrates an example of
|
||||
// how this can be done through software.
|
||||
//
|
||||
// For more information on F2833x interrupt priorities, refer to the
|
||||
// Example_2833xISRPriorities.pdf file included with the DSP2833x/doc directory.
|
||||
//
|
||||
// This program simulates interrupt conflicts by writing to the
|
||||
// PIEIFR registers. This will simulate multiple interrupts coming into
|
||||
// the PIE block at the same time.
|
||||
//
|
||||
// The interrupt service routine routines are software prioritized
|
||||
// by the table found in the DSP2833x_SWPrioritizedIsrLevels.h file.
|
||||
//
|
||||
// 1) Before compiling you must set the Global and Group interrupt priorities
|
||||
// in the DSP2833x_SWPrioritizedIsrLevels.h file.
|
||||
//
|
||||
// 2) Then select which test you want to run with the #define TEST directive
|
||||
// at the top of this file (select a test between 1 and 10)
|
||||
//
|
||||
// 3) Compile the code, load, and run
|
||||
//
|
||||
// 4) At the end of each test there is a hard coded breakpoint (ESTOP0). When code
|
||||
// stops at the breakpoint, examine the ISRTrace buffer to see the order
|
||||
// in which the ISR's completed. All PIE interrupts will add to the
|
||||
// ISRTrace.
|
||||
//
|
||||
// The ISRTrace will consist of a list of hex values as shown:
|
||||
//
|
||||
// 0x00wx <- PIE Group w interrup x finished first
|
||||
// 0x00yz <- PIE Group y interrupt z finished next
|
||||
//
|
||||
// 5) If desired, set a new set of Global and Group interrupt priorites
|
||||
// and repeat the test to see the change.
|
||||
//
|
||||
//
|
||||
// Watch Variables:
|
||||
// ISRTrace[50] Trace of ISR's in the order they complete
|
||||
// After each test, examine this buffer
|
||||
// to determine if the ISR's completed in
|
||||
// the order desired.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
|
||||
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
|
||||
#include "DSP2833x_SWPrioritizedIsrLevels.h"
|
||||
|
||||
#define TEST 1 // Select a test number: 1 through 10
|
||||
|
||||
// Define which interrupts are used in the PIE for each group.
|
||||
#define ISRS_GROUP1 (M_INT1|M_INT2|M_INT4|M_INT5|M_INT6|M_INT7|M_INT8)
|
||||
#define ISRS_GROUP2 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6)
|
||||
#define ISRS_GROUP3 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6)
|
||||
#define ISRS_GROUP4 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6)
|
||||
#define ISRS_GROUP5 (M_INT1|M_INT2)
|
||||
#define ISRS_GROUP6 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6)
|
||||
#define ISRS_GROUP7 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6)
|
||||
#define ISRS_GROUP8 (M_INT1|M_INT2|M_INT5|M_INT6)
|
||||
#define ISRS_GROUP9 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT7|M_INT8)
|
||||
#define ISRS_GROUP12 (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT7|M_INT8)
|
||||
|
||||
|
||||
// This array will be used as a trace to check the order that the
|
||||
// interrupts were serviced
|
||||
Uint16 ISRTrace[50];
|
||||
Uint16 ISRTraceIndex; // used to update an element in the trace buffer
|
||||
|
||||
void main(void)
|
||||
{
|
||||
Uint16 i;
|
||||
|
||||
// Step 1. Initialize System Control:
|
||||
// PLL, WatchDog, enable Peripheral Clocks
|
||||
// This example function is found in the DSP2833x_SysCtrl.c file.
|
||||
InitSysCtrl();
|
||||
|
||||
// Step 2. Initalize GPIO:
|
||||
// This example function is found in the DSP2833x_Gpio.c file and
|
||||
// illustrates how to set the GPIO to it's default state.
|
||||
// InitGpio(); // Skipped for this example
|
||||
|
||||
|
||||
// Step 3. Clear all interrupts and initialize PIE vector table:
|
||||
// Disable CPU interrupts
|
||||
DINT;
|
||||
|
||||
// Initialize PIE control registers to their default state.
|
||||
// The default state is all PIE interrupts disabled and flags
|
||||
// are cleared.
|
||||
// This function is found in the DSP2833x_PieCtrl.c file.
|
||||
InitPieCtrl();
|
||||
|
||||
// Disable CPU interrupts and clear all CPU interrupt flags:
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
// This will populate the entire table, even if the interrupt
|
||||
// is not used in this example. This is useful for debug purposes.
|
||||
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
|
||||
// This function is found in DSP2833x_PieVect.c.
|
||||
InitPieVectTable();
|
||||
|
||||
// Step 4. Initialize all the Device Peripherals:
|
||||
// This function is found in DSP2833x_InitPeripherals.c
|
||||
// InitPeripherals(); // Not required for this example
|
||||
|
||||
// Step 5. User specific code, enable interrupts:
|
||||
|
||||
#if (TEST==1)
|
||||
// Force all group 1 interrupts at once by writing to the PIEIFR1 register
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 1 interrupt 1-8
|
||||
PieCtrlRegs.PIEIER1.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 1 is clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = M_INT1;
|
||||
|
||||
// Enable CPU INT1
|
||||
IER |= M_INT1;
|
||||
|
||||
// Force all valid interrupts for Group 1
|
||||
PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;
|
||||
|
||||
// Enable global Interrupts CPU level:
|
||||
EINT; // Enable Global interrupt INTM
|
||||
|
||||
// Wait for all Group 1 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR1.all != 0x0000 ){}
|
||||
|
||||
// Stop here and check the ISRTrace to determine which order the
|
||||
// ISR Routines completed. The order is dependant on the priority
|
||||
// assigned in the DSP2833x_SWPrioritizedIsrLevels.h file
|
||||
//
|
||||
// The ISRTrace will contain a list of values corresponding to the
|
||||
// interrupts serviced in the order they were serviced.
|
||||
// For example if the ISRTrace looks like this
|
||||
// 0x0014 ISR Group 1 interrupt 4
|
||||
// 0x0017 ISR Group 1 interrupt 7
|
||||
// 0x0016 ISR Group 1 interrupt 6
|
||||
// 0x0015 ISR Group 1 interrupt 5
|
||||
// 0x0018 ISR Group 1 interrupt 8
|
||||
// 0x0012 ISR Group 1 interrupt 2
|
||||
// 0x0011 ISR Group 1 interrupt 1
|
||||
// 0x0000 end of trace
|
||||
asm(" ESTOP0");
|
||||
#endif
|
||||
#if (TEST == 2)
|
||||
// CASE 2:
|
||||
// Force all group 2 interrupts at once by writing to the PIEIFR2 register
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 2 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER2.all = 0x00FF;
|
||||
|
||||
// Enable CPU INT2
|
||||
IER |= (M_INT2);
|
||||
|
||||
// Make sure PIEACK for group 2 is clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = M_INT2;
|
||||
|
||||
// Force all valid interrupts for Group 2
|
||||
PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
|
||||
// Wait for all group 2 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR2.all != 0x0000 ){}
|
||||
|
||||
// Stop here and check the order the ISR's were serviced in the
|
||||
// ISRTrace
|
||||
asm(" ESTOP0");
|
||||
|
||||
#endif
|
||||
#if (TEST == 3)
|
||||
// CASE 3:
|
||||
// Force all group 3 interrupts at once by writing to the PIEIFR3 register
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 3 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER3.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 3 is clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = M_INT3;
|
||||
|
||||
// Enable CPU INT3
|
||||
IER |= (M_INT3);
|
||||
|
||||
// Force all valid interrupts for Group 3
|
||||
PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
// Wait for all group 3 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR3.all != 0x0000 ){}
|
||||
|
||||
// Stop here and check the order the ISR's were serviced in the
|
||||
// ISRTrace
|
||||
asm(" ESTOP0");
|
||||
#endif
|
||||
#if (TEST == 4)
|
||||
// CASE 4:
|
||||
// Force all group 4 interrupts at once by writing to the PIEIFR4 register
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 4 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER4.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 3 is clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = M_INT4;
|
||||
|
||||
// Enable CPU INT4
|
||||
IER |= (M_INT4);
|
||||
|
||||
// Force all valid interrupts for Group 4
|
||||
PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
// Wait for all group 4 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR4.all != 0x0000 ){}
|
||||
|
||||
// Stop here and check the order the ISR's were serviced in the
|
||||
// ISRTrace
|
||||
asm(" ESTOP0");
|
||||
#endif
|
||||
#if (TEST == 5)
|
||||
// CASE 5:
|
||||
// Force all group 5 interrupts at once by writing to the PIEIFR5 register
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 5 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER5.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 5 is clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = M_INT5;
|
||||
|
||||
// Enable CPU INT5
|
||||
IER |= (M_INT5);
|
||||
|
||||
// Force all valid interrupts for Group 5
|
||||
PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
// Wait for all group 5 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR5.all != 0x0000 ){}
|
||||
|
||||
// Stop here and check the order the ISR's were serviced in the
|
||||
// ISRTrace
|
||||
asm(" ESTOP0");
|
||||
#endif
|
||||
#if (TEST == 6)
|
||||
|
||||
// CASE 6:
|
||||
// Force all group 6 interrupts at once by writing to the PIEIFR6 register
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 6 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER6.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 6 is clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = M_INT6;
|
||||
|
||||
// Enable CPU INT6
|
||||
IER |= (M_INT6);
|
||||
|
||||
// Force all valid interrupts for Group 6
|
||||
PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
|
||||
// Wait for all group 6 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR6.all != 0x0000 ){}
|
||||
|
||||
// Stop here and check the order the ISR's were serviced in the
|
||||
// ISRTrace
|
||||
asm(" ESTOP0");
|
||||
|
||||
#endif
|
||||
#if (TEST == 7)
|
||||
// CASE 7:
|
||||
// Force all group 9 interrupts at once by writing to the PIEIFR4 register
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 9 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER9.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 9 is clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = M_INT9;
|
||||
|
||||
// Enable CPU INT9
|
||||
IER |= (M_INT9);
|
||||
|
||||
// Force all valid interrupts for Group 9
|
||||
PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
// Wait for all group 9 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR9.all != 0x0000 ){}
|
||||
|
||||
// Stop here and check the order the ISR's were serviced in the
|
||||
// ISRTrace
|
||||
asm(" ESTOP0");
|
||||
|
||||
#endif
|
||||
#if (TEST == 8)
|
||||
// CASE 8:
|
||||
// Force all group 1 and group 2 interrupts at once
|
||||
|
||||
// Setup next test - fire interrupts from Group 1 and Group 2
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 1 and group 2 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER1.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER2.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 1 & 2 are clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = (M_INT3 | M_INT2);
|
||||
|
||||
// Enable CPU INT1 and INT2
|
||||
IER |= (M_INT1|M_INT2);
|
||||
|
||||
// Force all valid interrupts for Group 1 and from Group 2
|
||||
PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;
|
||||
PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
// Wait for all group 1 and group 2 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR1.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR2.all != 0x0000 ){}
|
||||
|
||||
// Check the ISRTrace to determine which order the ISR Routines completed
|
||||
asm(" ESTOP0");
|
||||
|
||||
#endif
|
||||
#if (TEST == 9)
|
||||
// CASE 9:
|
||||
// Force all group 1 and group 2 and group 3 interrupts at once
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable PIE group 1, 2 and 3 interrupts 1-8
|
||||
PieCtrlRegs.PIEIER1.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER2.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER3.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 1, 2 & 3 are clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = (M_INT3|M_INT2|M_INT3);
|
||||
|
||||
// Enable CPU INT1, INT2 & INT3
|
||||
IER |= (M_INT1|M_INT2|M_INT3);
|
||||
|
||||
// Force all valid interrupts for Group1, 2 and 3
|
||||
PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;
|
||||
PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;
|
||||
PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3;
|
||||
|
||||
// Enable Global interrupts
|
||||
EINT;
|
||||
|
||||
// Wait for all group 1 and group 2 and group 3 interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR1.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR2.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR3.all != 0x0000 ) {}
|
||||
|
||||
// Check the ISRTrace to determine which order the ISR Routines completed
|
||||
asm(" ESTOP0");
|
||||
|
||||
#endif
|
||||
#if (TEST == 10)
|
||||
// CASE 10:
|
||||
// Force all used PIE interrupts at once
|
||||
|
||||
// Prepare for the test:
|
||||
// Disable interrupts
|
||||
// Clear the trace buffer, PIE Control Register, CPU IER and IFR registers
|
||||
DINT;
|
||||
for(i = 0; i < 50; i++) ISRTrace[i] = 0;
|
||||
ISRTraceIndex = 0;
|
||||
InitPieCtrl();
|
||||
IER = 0;
|
||||
IFR &= 0;
|
||||
|
||||
// Enable the PIE block
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
// Enable all PIE group interrupts 1-8
|
||||
PieCtrlRegs.PIEIER1.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER2.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER3.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER4.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER5.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER6.all = 0x00FF;
|
||||
PieCtrlRegs.PIEIER9.all = 0x00FF;
|
||||
|
||||
// Make sure PIEACK for group 1, 2, 3, 4, 5, 6 and 9 are clear (default after reset)
|
||||
PieCtrlRegs.PIEACK.all = (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT9);
|
||||
|
||||
// Enable CPU INT1, INT2, INT3, INT4, INT5, INT6 and INT9
|
||||
IER |= (M_INT1|M_INT2|M_INT3|M_INT4|M_INT5|M_INT6|M_INT9);
|
||||
|
||||
// Force all valid interrupts for all PIE groups
|
||||
PieCtrlRegs.PIEIFR1.all = ISRS_GROUP1;
|
||||
PieCtrlRegs.PIEIFR2.all = ISRS_GROUP2;
|
||||
PieCtrlRegs.PIEIFR3.all = ISRS_GROUP3;
|
||||
PieCtrlRegs.PIEIFR4.all = ISRS_GROUP4;
|
||||
PieCtrlRegs.PIEIFR5.all = ISRS_GROUP5;
|
||||
PieCtrlRegs.PIEIFR6.all = ISRS_GROUP6;
|
||||
PieCtrlRegs.PIEIFR9.all = ISRS_GROUP9;
|
||||
|
||||
// Enable Global interrupts - CPU level
|
||||
EINT;
|
||||
|
||||
// Wait for all group interrupts to be serviced
|
||||
while(PieCtrlRegs.PIEIFR1.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR2.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR3.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR4.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR5.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR6.all != 0x0000
|
||||
|| PieCtrlRegs.PIEIFR9.all != 0x0000 ) {}
|
||||
|
||||
// Check the ISRTrace to determine which order the ISR Routines completed
|
||||
asm(" ESTOP0");
|
||||
#endif
|
||||
}
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: August 9, 2007 17:23:56 $
|
||||
//###########################################################################
|
||||
//
|
||||
// This .gel file can be used to help load and build the example project.
|
||||
// It should be unloaded from Code Composer Studio before loading another
|
||||
// project.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
|
||||
// $Release Date: August 1, 2008 $
|
||||
//###########################################################################
|
||||
*/
|
||||
|
||||
menuitem "DSP2833x Software Prioritized Interrupts"
|
||||
|
||||
hotmenu Load_and_Build_Project()
|
||||
{
|
||||
GEL_ProjectLoad("Example_2833xSWPrioritizedInterrupts.pjt");
|
||||
GEL_ProjectBuild("Example_2833xSWPrioritizedInterrupts.pjt");
|
||||
Setup_WatchWindow();
|
||||
}
|
||||
|
||||
hotmenu Load_Code()
|
||||
{
|
||||
GEL_Load(".\\debug\\Example_2833xSWPrioritizedInterrupts.out");
|
||||
Setup_WatchWindow();
|
||||
}
|
||||
|
||||
hotmenu Setup_WatchWindow()
|
||||
{
|
||||
GEL_WatchReset();
|
||||
GEL_WatchAdd("ISRTrace,x");
|
||||
GEL_WatchAdd("TempPIEIER,x");
|
||||
GEL_WatchAdd("PieCtrlRegs,x");
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
|
||||
|
||||
[Project Settings]
|
||||
ProjectName="DSP2833x"
|
||||
ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\"
|
||||
ProjectType=Executable
|
||||
CPUFamily=TMS320C28XX
|
||||
Tool="Compiler"
|
||||
Tool="DspBiosBuilder"
|
||||
Tool="Linker"
|
||||
Config="Debug"
|
||||
Config="Release"
|
||||
|
||||
[Source Files]
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_SWPrioritizedPieVect.c"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm"
|
||||
Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
|
||||
Source="Example_2833xSWPrioritizedDefaultIsr.c"
|
||||
Source="Example_2833xSWPrioritizedInterrupts.c"
|
||||
Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd"
|
||||
Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
|
||||
|
||||
["Compiler" Settings: "Debug"]
|
||||
Options=-g -q -pdr -o2 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28
|
||||
|
||||
["Compiler" Settings: "Release"]
|
||||
Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\sw_prioritized_interrupts\Release" -d"LARGE_MODEL" -ml -v28
|
||||
|
||||
["DspBiosBuilder" Settings: "Debug"]
|
||||
Options=-v28
|
||||
|
||||
["DspBiosBuilder" Settings: "Release"]
|
||||
Options=-v28
|
||||
|
||||
["Linker" Settings: "Debug"]
|
||||
Options=-q -c -m".\Debug\Example_2833xSWPrioritizedInterrupts.map" -o".\Debug\Example_2833xSWPrioritizedInterrupts.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib"
|
||||
|
||||
["Linker" Settings: "Release"]
|
||||
Options=-q -c -o".\Release\Example_2833xSWPrioritizedInterrupts.out" -x
|
||||
|
||||
Reference in New Issue
Block a user