init commit.
Проект каким он достался от Димы.
This commit is contained in:
@@ -0,0 +1,403 @@
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//###########################################################################
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//
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// FILE: Example_2833xMCBSP_DLB_DMA.c
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//
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// TITLE: DSP2833x Device McBSP Digital Loop Back with DMA program
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//
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// ASSUMPTIONS:
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//
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// This program requires the DSP2833x header files.
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// As supplied, this project is configured for "boot to SARAM"
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// operation. The 2833x Boot Mode table is shown below.
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// For information on configuring the boot mode of an eZdsp,
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// please refer to the documentation included with the eZdsp,
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//
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// $Boot_Table:
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//
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// GPIO87 GPIO86 GPIO85 GPIO84
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// XA15 XA14 XA13 XA12
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// PU PU PU PU
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// ==========================================
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// 1 1 1 1 Jump to Flash
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// 1 1 1 0 SCI-A boot
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// 1 1 0 1 SPI-A boot
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// 1 1 0 0 I2C-A boot
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// 1 0 1 1 eCAN-A boot
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// 1 0 1 0 McBSP-A boot
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// 1 0 0 1 Jump to XINTF x16
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// 1 0 0 0 Jump to XINTF x32
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// 0 1 1 1 Jump to OTP
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// 0 1 1 0 Parallel GPIO I/O boot
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// 0 1 0 1 Parallel XINTF boot
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// 0 1 0 0 Jump to SARAM <- "boot to SARAM"
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// 0 0 1 1 Branch to check boot mode
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// 0 0 1 0 Boot to flash, bypass ADC cal
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// 0 0 0 1 Boot to SARAM, bypass ADC cal
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// 0 0 0 0 Boot to SCI-A, bypass ADC cal
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// Boot_Table_End$
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//
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// DESCRIPTION:
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//
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// This program is a McBSP example that uses the internal loopback of
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// the peripheral and utilizes the DMA to transfer data from one buffer
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// to the McBSP, and then from the McBSP to another buffer.
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//
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// Initially, sdata[] is filled with values from 0x0000- 0x007F. The DMA
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// moves the values in sdata[] one by one to the DXRx registers of the McBSP.
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// These values are transmitted and subsequently received by the McBSP.
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// Then, the DMA moves each data value to rdata[] as it is received by the McBSP.
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//
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// Three different serial word sizes can be tested.
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//
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// Before compiling this project:
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// * Select the serial word size (8/16/32) by using
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// the #define statements at the beginning of the code.
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//
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// The program loops forever after all values have been transferred to sdata.
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// It is up to the user to stop the program.
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//
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//
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// By default for the McBSP examples, the McBSP sample rate generator (SRG) input
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// clock frequency is LSPCLK (150E6/4 or 100E6/4) assuming SYSCLKOUT = 150 MHz or
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// 100 MHz respectively. If while testing, the SRG input frequency
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// is changed, the #define MCBSP_SRG_FREQ (150E6/4 or 100E6/4) in the Mcbsp.c file must
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// also be updated accordingly. This define is used to determine the Mcbsp initialization
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// delay after the SRG is enabled, which must be at least 2 SRG clock cycles.
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//
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// Watch Variables:
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// sdata
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// rdata
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//
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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// Choose a word size. Uncomment one of the following lines
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#define WORD_SIZE 8 // Run a loopback test in 8-bit mode
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//#define WORD_SIZE 16 // Run a loopback test in 16-bit mode
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//#define WORD_SIZE 32 // Run a loopback test in 32-bit mode
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// Prototype statements for functions found within this file.
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interrupt void local_D_INTCH1_ISR(void);
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interrupt void local_D_INTCH2_ISR(void);
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void mcbsp_init_dlb(void);
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void init_dma(void);
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void init_dma_32(void);
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void start_dma(void);
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void error(void);
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// Place sdata and rdata buffers in DMA-accessible RAM (L4 for this example)
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#pragma DATA_SECTION(sdata, "DMARAML4")
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#pragma DATA_SECTION(rdata, "DMARAML4")
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Uint16 sdata[128]; // Sent Data
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Uint16 rdata[128]; // Recieved Data
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Uint16 data_size; // Word Length variable
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void main(void)
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{
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Uint16 i;
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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InitSysCtrl();
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// Step 2. Initalize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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// InitGpio(); // Skipped for this example
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// Setup only the GP I/O only for McBSP-A functionality
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InitMcbspaGpio();
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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DINT;
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// Initialize PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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InitPieCtrl();
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// Disable CPU interrupts and clear all CPU interrupt flags:
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IER = 0x0000;
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IFR = 0x0000;
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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InitPieVectTable();
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// Interrupts that are used in this example are re-mapped to
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// ISR functions found within this file.
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EALLOW; // Allow access to EALLOW protected registers
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PieVectTable.DINTCH1= &local_D_INTCH1_ISR;
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PieVectTable.DINTCH2= &local_D_INTCH2_ISR;
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EDIS; // Disable access to EALLOW protected registers
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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// InitPeripherals(); // Not required for this example
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// Step 5. User specific code, enable interrupts:
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data_size = WORD_SIZE;
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for (i=0; i<128; i++)
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{
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sdata[i] = i; // Fill sdata with values between 0 and 0x007F
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rdata[i] = 0; // Initialize rdata to all 0x0000.
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}
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if (data_size == 32)
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{
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init_dma_32(); // DMA Initialization for 32-bit transfers
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} else
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{
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init_dma(); // 1. When using DMA, initialize DMA with peripheral interrupts first.
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}
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start_dma();
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mcbsp_init_dlb(); // 2. Then initialize and release peripheral (McBSP) from Reset.
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// Enable interrupts required for this example
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PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
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PieCtrlRegs.PIEIER6.bit.INTx5=1; // Enable PIE Group 6, INT 5
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PieCtrlRegs.PIEIER6.bit.INTx6=1; // Enable PIE Group 6, INT 6
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PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable PIE Group 7, INT 1 (DMA CH1)
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PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable PIE Group 7, INT 2 (DMA CH2)
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IER=0x60; // Enable CPU INT groups 6 and 7
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EINT; // Enable Global Interrupts
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// Step 6. IDLE loop. Just sit and loop forever (optional):
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for(;;);
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}
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// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here:
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void error(void)
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{
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asm(" ESTOP0"); // Test failed!! Stop!
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for (;;);
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}
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void mcbsp_init_dlb()
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{
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McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
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McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
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McbspaRegs.SPCR1.bit.DLB = 1; // Enable DLB mode. Comment out for non-DLB mode.
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McbspaRegs.MFFINT.all=0x0; // Disable all interrupts
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McbspaRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive)
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McbspaRegs.RCR1.all=0x0;
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McbspaRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit)
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McbspaRegs.XCR1.all=0x0;
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McbspaRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
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McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods
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McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
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McbspaRegs.SRGR1.bit.CLKGDV = 0; // CLKG frequency = LSPCLK/(CLKGDV+1)
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McbspaRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source
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McbspaRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source
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//*************** Initialize McBSP Data Length
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if(data_size == 8) // Run a loopback test in 8-bit mode
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{
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InitMcbspa8bit();
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}
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if(data_size == 16) // Run a loopback test in 16-bit mode
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{
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InitMcbspa16bit();
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}
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if(data_size == 32) // Run a loopback test in 32-bit mode
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{
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InitMcbspa32bit();
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}
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//************* Enable Sample rate generator
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McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
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delay_loop(); // Wait at least 2 SRG clock cycles
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McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
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McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
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McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
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}
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// DMA Initialization for data size <= 16-bit
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void init_dma()
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{
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EALLOW;
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DmaRegs.DMACTRL.bit.HARDRESET = 1;
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asm(" NOP"); // Only 1 NOP needed per Design
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DmaRegs.CH1.MODE.bit.CHINTE = 0;
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// Channel 1, McBSPA transmit
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DmaRegs.CH1.BURST_SIZE.all = 0; // 1 word/burst
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DmaRegs.CH1.SRC_BURST_STEP = 0; // no effect when using 1 word/burst
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DmaRegs.CH1.DST_BURST_STEP = 0; // no effect when using 1 word/burst
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DmaRegs.CH1.TRANSFER_SIZE = 127; // Interrupt every frame (127 bursts/transfer)
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DmaRegs.CH1.SRC_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst
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DmaRegs.CH1.DST_TRANSFER_STEP = 0; // Don't move destination address
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DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &sdata[0]; // Start address = buffer
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DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &sdata[0]; // Not needed unless using wrap function
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DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all; // Start address = McBSPA DXR
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DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all; // Not needed unless using wrap function
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DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear peripheral interrupt event flag
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DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear sync flag
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DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear sync error flag
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DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap
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DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap
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DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal
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DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal
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DmaRegs.CH1.MODE.bit.CHINTE = 1; // Enable channel interrupt
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DmaRegs.CH1.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer
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DmaRegs.CH1.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event
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DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA; // Peripheral interrupt select = McBSP MXSYNCA
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DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
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// Channel 2, McBSPA Receive
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DmaRegs.CH2.MODE.bit.CHINTE = 0;
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DmaRegs.CH2.BURST_SIZE.all = 0; // 1 word/burst
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DmaRegs.CH2.SRC_BURST_STEP = 0; // no effect when using 1 word/burst
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DmaRegs.CH2.DST_BURST_STEP = 0; // no effect when using 1 word/burst
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DmaRegs.CH2.TRANSFER_SIZE = 127; // Interrupt every 127 bursts/transfer
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DmaRegs.CH2.SRC_TRANSFER_STEP = 0; // Don't move source address
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DmaRegs.CH2.DST_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst
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DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all; // Start address = McBSPA DRR
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DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all; // Not needed unless using wrap function
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DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &rdata[0]; // Start address = Receive buffer (for McBSP-A)
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DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &rdata[0]; // Not needed unless using wrap function
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DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear peripheral interrupt event flag
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DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear sync flag
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DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear sync error flag
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DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap
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DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap
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DmaRegs.CH2.MODE.bit.CHINTE = 1; // Enable channel interrupt
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DmaRegs.CH2.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer
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DmaRegs.CH2.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event
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DmaRegs.CH2.MODE.bit.PERINTSEL = DMA_MREVTA; // Peripheral interrupt select = McBSP MRSYNCA
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DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
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EDIS;
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}
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// DMA Initialization for data size > 16-bit and <= 32-bit.
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void init_dma_32()
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{
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EALLOW;
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DmaRegs.DMACTRL.bit.HARDRESET = 1;
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asm(" NOP"); // Only 1 NOP needed per Design
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// Channel 1, McBSPA transmit
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DmaRegs.CH1.BURST_SIZE.all = 1; // 2 word/burst
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DmaRegs.CH1.SRC_BURST_STEP = 1; // increment 1 16-bit addr. btwn words
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DmaRegs.CH1.DST_BURST_STEP = 1; // increment 1 16-bit addr. btwn words
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DmaRegs.CH1.TRANSFER_SIZE = 63; // Interrupt every 63 bursts/transfer
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DmaRegs.CH1.SRC_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst
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DmaRegs.CH1.DST_TRANSFER_STEP = 0xFFFF; // Go back to DXR2
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DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &sdata[0]; // Start address = buffer
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DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &sdata[0]; // Not needed unless using wrap function
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DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all; // Start address = McBSPA DXR2
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DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all; // Not needed unless using wrap function
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DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear sync flag
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DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear sync error flag
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DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap
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DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap
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DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal
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DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal
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DmaRegs.CH1.MODE.bit.CHINTE = 1; // Enable channel interrupt
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DmaRegs.CH1.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer
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DmaRegs.CH1.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event
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DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA; // Peripheral interrupt select = McBSP MXSYNCA
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DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
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// Channel 2, McBSPA Receive
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DmaRegs.CH2.BURST_SIZE.all = 1; // 2 words/burst
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DmaRegs.CH2.SRC_BURST_STEP = 1; // Increment 1 16-bit addr. btwn words
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DmaRegs.CH2.DST_BURST_STEP = 1; // Increment 1 16-bit addr. btwn words
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DmaRegs.CH2.TRANSFER_SIZE = 63; // Interrupt every 63 bursts/transfer
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DmaRegs.CH2.SRC_TRANSFER_STEP = 0xFFFF; // Decrement back to DRR2
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DmaRegs.CH2.DST_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst
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DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; // Start address = McBSPA DRR
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DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; // Not needed unless using wrap function
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DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &rdata[0]; // Start address = Receive buffer (for McBSP-A)
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DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &rdata[0]; // Not needed unless using wrap function
|
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DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear sync flag
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DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear sync error flag
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DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap
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||||
DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap
|
||||
DmaRegs.CH2.MODE.bit.CHINTE = 1; // Enable channel interrupt
|
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DmaRegs.CH2.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer
|
||||
DmaRegs.CH2.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event
|
||||
DmaRegs.CH2.MODE.bit.PERINTSEL = DMA_MREVTA; // Peripheral interrupt select = McBSP MRSYNCA
|
||||
DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
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EDIS;
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||||
}
|
||||
void start_dma (void)
|
||||
{
|
||||
EALLOW;
|
||||
DmaRegs.CH1.CONTROL.bit.RUN = 1; // Start DMA Transmit from McBSP-A
|
||||
DmaRegs.CH2.CONTROL.bit.RUN = 1; // Start DMA Receive from McBSP-A
|
||||
|
||||
EDIS;
|
||||
}
|
||||
// INT7.1
|
||||
interrupt void local_D_INTCH1_ISR(void) // DMA Ch1
|
||||
{
|
||||
EALLOW; // NEED TO EXECUTE EALLOW INSIDE ISR !!!
|
||||
DmaRegs.CH1.CONTROL.bit.RUN=0; // Re-enable DMA CH1. Should be done every transfer
|
||||
PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
|
||||
EDIS;
|
||||
return;
|
||||
}
|
||||
|
||||
// INT7.2
|
||||
interrupt void local_D_INTCH2_ISR(void) // DMA Ch2
|
||||
{
|
||||
Uint16 i;
|
||||
EALLOW; // NEED TO EXECUTE EALLOW INSIDE ISR !!!
|
||||
DmaRegs.CH2.CONTROL.bit.RUN = 0; // Re-enable DMA CH2. Should be done every transfer
|
||||
PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // To receive more interrupts from this PIE group, acknowledge this interrupt
|
||||
for (i=0; i<128; i++)
|
||||
{
|
||||
if(data_size == 8)
|
||||
{
|
||||
if( (rdata[i]&0x00FF) !=(sdata[i]&0x00FF)) error( ); // Check for correct received data
|
||||
}
|
||||
else if (data_size == 16)
|
||||
{
|
||||
if (rdata[i] != sdata[i]) error(); // STOP if there is an error !!
|
||||
}
|
||||
else if (data_size == 32)
|
||||
{
|
||||
if ((rdata[i])!=(sdata[i])) error ();
|
||||
}
|
||||
}
|
||||
EDIS;
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
//===========================================================================
|
||||
// No more.
|
||||
//===========================================================================
|
||||
|
||||
|
||||
@@ -0,0 +1,22 @@
|
||||
menuitem "DSP2833x McBSP DMA"
|
||||
|
||||
hotmenu Load_and_Build_Project()
|
||||
{
|
||||
GEL_ProjectLoad("Example_2833xMcBSP_DLB_DMA.pjt");
|
||||
GEL_ProjectBuild("Example_2833xMcBSP_DLB_DMA.pjt");
|
||||
Setup_WatchWindow();
|
||||
}
|
||||
|
||||
hotmenu Load_Code()
|
||||
{
|
||||
GEL_Load(".\\debug\\Example_2833xMcBSP_DLB_DMA.out");
|
||||
Setup_WatchWindow();
|
||||
}
|
||||
hotmenu Setup_WatchWindow()
|
||||
{
|
||||
GEL_WatchReset();
|
||||
GEL_WatchAdd("rdata,x");
|
||||
GEL_WatchAdd("sdata,x");
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,52 @@
|
||||
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
|
||||
|
||||
[Project Settings]
|
||||
ProjectName="DSP2833x"
|
||||
ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\"
|
||||
ProjectType=Executable
|
||||
CPUFamily=TMS320C28XX
|
||||
Tool="Compiler"
|
||||
Tool="CustomBuilder"
|
||||
Tool="DspBiosBuilder"
|
||||
Tool="Linker"
|
||||
Config="Debug"
|
||||
Config="Release"
|
||||
|
||||
[Source Files]
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_McBSP.c"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c"
|
||||
Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm"
|
||||
Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
|
||||
Source="Example_2833xMcBSP_DLB_DMA.c"
|
||||
Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd"
|
||||
Source="..\..\DSP2833x_headers\cmd\DSP2833x_Headers_nonBIOS.cmd"
|
||||
|
||||
["Compiler" Settings: "Debug"]
|
||||
Options=-g -q -pdr -as -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" --float_support=fpu32 -ml -mt -v28
|
||||
|
||||
["Compiler" Settings: "Release"]
|
||||
Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\mcbsp_loopback_dma\Release" -d"LARGE_MODEL" -ml -v28
|
||||
|
||||
["DspBiosBuilder" Settings: "Debug"]
|
||||
Options=-v28
|
||||
|
||||
["DspBiosBuilder" Settings: "Release"]
|
||||
Options=-v28
|
||||
|
||||
["Linker" Settings: "Debug"]
|
||||
Options=-q -c -m".\Debug\Example_2833xMcBSP_DLB_DMA.map" -o".\Debug\Example_2833xMcBSP_DLB_DMA.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib"
|
||||
|
||||
["Linker" Settings: "Release"]
|
||||
Options=-q -c -o".\Release\Example_2833xMcBSP_DLB_DMA.out" -x
|
||||
|
||||
["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Debug"]
|
||||
LinkOrder=1
|
||||
|
||||
["..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd" Settings: "Release"]
|
||||
LinkOrder=1
|
||||
|
||||
Reference in New Issue
Block a user