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Проект каким он достался от Димы.
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nelolik
2021-02-15 09:56:02 +03:00
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183
v120/DSP2833x_examples/epwm_dma/DSP2833x_EPWMDM_Headers_BIOS.cmd Normal file
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/*
// TI File $Revision: /main/1 $
// Checkin $Date: June 19, 2008 10:23:49 $
//###########################################################################
//
// FILE: DSP2833x_Headers_BIOS.cmd
//
// TITLE: DSP2833x Peripheral registers linker command file
//
// DESCRIPTION:
//
// This file is for use in BIOS applications.
//
// Linker command file to place the peripheral structures
// used within the DSP2833x headerfiles into the correct memory
// mapped locations.
//
// This version of the file does not include the PieVectorTable structure.
// For non-BIOS applications, please use the DSP2833x_Headers_nonBIOS.cmd
// file which includes the PieVectorTable structure.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
*/
MEMORY
{
PAGE 0: /* Program Memory */
PAGE 1: /* Data Memory */
DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */
FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */
CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */
ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */
XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */
CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
DMA : origin = 0x001000, length = 0x000200 /* DMA registers */
MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */
MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */
ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */
ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */
ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */
ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */
ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */
ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */
ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */
ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */
ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */
ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */
EPWM1 : origin = 0x005800, length = 0x000022 /* Enhanced PWM 1 registers */
EPWM2 : origin = 0x005840, length = 0x000022 /* Enhanced PWM 2 registers */
EPWM3 : origin = 0x005880, length = 0x000022 /* Enhanced PWM 3 registers */
EPWM4 : origin = 0x0058C0, length = 0x000022 /* Enhanced PWM 4 registers */
EPWM5 : origin = 0x005900, length = 0x000022 /* Enhanced PWM 5 registers */
EPWM6 : origin = 0x005940, length = 0x000022 /* Enhanced PWM 6 registers */
ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */
ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */
ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */
ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */
ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */
ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */
EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */
EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */
GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */
GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */
GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */
SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */
SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */
SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */
XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */
ADC : origin = 0x007100, length = 0x000020 /* ADC registers */
SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */
SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */
I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */
PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */
}
SECTIONS
{
/*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/
PieVectTableFile : > PIEVECT, PAGE = 1, TYPE = DSECT
/*** Peripheral Frame 0 Register Structures ***/
DevEmuRegsFile : > DEV_EMU, PAGE = 1
FlashRegsFile : > FLASH_REGS, PAGE = 1
CsmRegsFile : > CSM, PAGE = 1
AdcMirrorFile : > ADC_MIRROR, PAGE = 1
XintfRegsFile : > XINTF, PAGE = 1
CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
DmaRegsFile : > DMA, PAGE = 1
/*** Peripheral Frame 3 Register Structures ***/
McbspaRegsFile : > MCBSPA, PAGE = 1
McbspbRegsFile : > MCBSPB, PAGE = 1
/*** Peripheral Frame 1 Register Structures ***/
ECanaRegsFile : > ECANA, PAGE = 1
ECanaLAMRegsFile : > ECANA_LAM PAGE = 1
ECanaMboxesFile : > ECANA_MBOX PAGE = 1
ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1
ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1
ECanbRegsFile : > ECANB, PAGE = 1
ECanbLAMRegsFile : > ECANB_LAM PAGE = 1
ECanbMboxesFile : > ECANB_MBOX PAGE = 1
ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1
ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1
EPwm1RegsFile : > EPWM1 PAGE = 1
EPwm2RegsFile : > EPWM2 PAGE = 1
EPwm3RegsFile : > EPWM3 PAGE = 1
EPwm4RegsFile : > EPWM4 PAGE = 1
EPwm5RegsFile : > EPWM5 PAGE = 1
EPwm6RegsFile : > EPWM6 PAGE = 1
ECap1RegsFile : > ECAP1 PAGE = 1
ECap2RegsFile : > ECAP2 PAGE = 1
ECap3RegsFile : > ECAP3 PAGE = 1
ECap4RegsFile : > ECAP4 PAGE = 1
ECap5RegsFile : > ECAP5 PAGE = 1
ECap6RegsFile : > ECAP6 PAGE = 1
EQep1RegsFile : > EQEP1 PAGE = 1
EQep2RegsFile : > EQEP2 PAGE = 1
GpioCtrlRegsFile : > GPIOCTRL PAGE = 1
GpioDataRegsFile : > GPIODAT PAGE = 1
GpioIntRegsFile : > GPIOINT PAGE = 1
/*** Peripheral Frame 2 Register Structures ***/
SysCtrlRegsFile : > SYSTEM, PAGE = 1
SpiaRegsFile : > SPIA, PAGE = 1
SciaRegsFile : > SCIA, PAGE = 1
XIntruptRegsFile : > XINTRUPT, PAGE = 1
AdcRegsFile : > ADC, PAGE = 1
ScibRegsFile : > SCIB, PAGE = 1
ScicRegsFile : > SCIC, PAGE = 1
I2caRegsFile : > I2CA, PAGE = 1
/*** Code Security Module Register Structures ***/
CsmPwlFile : > CSM_PWL, PAGE = 1
/*** Device Part ID Register Structures ***/
PartIdRegsFile : > PARTID, PAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

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/*
// TI File $Revision: /main/1 $
// Checkin $Date: June 19, 2008 10:23:45 $
//###########################################################################
//
// FILE: DSP2833x_Headers_nonBIOS.cmd
//
// TITLE: DSP2833x Peripheral registers linker command file
//
// DESCRIPTION:
//
// This file is for use in Non-BIOS applications.
//
// Linker command file to place the peripheral structures
// used within the DSP2833x headerfiles into the correct memory
// mapped locations.
//
// This version of the file includes the PieVectorTable structure.
// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file
// which does not include the PieVectorTable structure.
//
//###########################################################################
*/
MEMORY
{
PAGE 0: /* Program Memory */
PAGE 1: /* Data Memory */
DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */
FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */
CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */
ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */
XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */
CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */
DMA : origin = 0x001000, length = 0x000200 /* DMA registers */
MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */
MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */
ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */
ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */
ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */
ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */
ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */
ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */
ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */
ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */
ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */
ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */
EPWM1 : origin = 0x005800, length = 0x000022 /* Enhanced PWM 1 registers */
EPWM2 : origin = 0x005840, length = 0x000022 /* Enhanced PWM 2 registers */
EPWM3 : origin = 0x005880, length = 0x000022 /* Enhanced PWM 3 registers */
EPWM4 : origin = 0x0058C0, length = 0x000022 /* Enhanced PWM 4 registers */
EPWM5 : origin = 0x005900, length = 0x000022 /* Enhanced PWM 5 registers */
EPWM6 : origin = 0x005940, length = 0x000022 /* Enhanced PWM 6 registers */
ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */
ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */
ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */
ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */
ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */
ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */
EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */
EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */
GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */
GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */
GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */
SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */
SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */
SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */
XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */
ADC : origin = 0x007100, length = 0x000020 /* ADC registers */
SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */
SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */
I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */
PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */
}
SECTIONS
{
PieVectTableFile : > PIE_VECT, PAGE = 1
/*** Peripheral Frame 0 Register Structures ***/
DevEmuRegsFile : > DEV_EMU, PAGE = 1
FlashRegsFile : > FLASH_REGS, PAGE = 1
CsmRegsFile : > CSM, PAGE = 1
AdcMirrorFile : > ADC_MIRROR, PAGE = 1
XintfRegsFile : > XINTF, PAGE = 1
CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
DmaRegsFile : > DMA, PAGE = 1
/*** Peripheral Frame 3 Register Structures ***/
McbspaRegsFile : > MCBSPA, PAGE = 1
McbspbRegsFile : > MCBSPB, PAGE = 1
/*** Peripheral Frame 1 Register Structures ***/
ECanaRegsFile : > ECANA, PAGE = 1
ECanaLAMRegsFile : > ECANA_LAM PAGE = 1
ECanaMboxesFile : > ECANA_MBOX PAGE = 1
ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1
ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1
ECanbRegsFile : > ECANB, PAGE = 1
ECanbLAMRegsFile : > ECANB_LAM PAGE = 1
ECanbMboxesFile : > ECANB_MBOX PAGE = 1
ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1
ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1
EPwm1RegsFile : > EPWM1 PAGE = 1
EPwm2RegsFile : > EPWM2 PAGE = 1
EPwm3RegsFile : > EPWM3 PAGE = 1
EPwm4RegsFile : > EPWM4 PAGE = 1
EPwm5RegsFile : > EPWM5 PAGE = 1
EPwm6RegsFile : > EPWM6 PAGE = 1
ECap1RegsFile : > ECAP1 PAGE = 1
ECap2RegsFile : > ECAP2 PAGE = 1
ECap3RegsFile : > ECAP3 PAGE = 1
ECap4RegsFile : > ECAP4 PAGE = 1
ECap5RegsFile : > ECAP5 PAGE = 1
ECap6RegsFile : > ECAP6 PAGE = 1
EQep1RegsFile : > EQEP1 PAGE = 1
EQep2RegsFile : > EQEP2 PAGE = 1
GpioCtrlRegsFile : > GPIOCTRL PAGE = 1
GpioDataRegsFile : > GPIODAT PAGE = 1
GpioIntRegsFile : > GPIOINT PAGE = 1
/*** Peripheral Frame 2 Register Structures ***/
SysCtrlRegsFile : > SYSTEM, PAGE = 1
SpiaRegsFile : > SPIA, PAGE = 1
SciaRegsFile : > SCIA, PAGE = 1
XIntruptRegsFile : > XINTRUPT, PAGE = 1
AdcRegsFile : > ADC, PAGE = 1
ScibRegsFile : > SCIB, PAGE = 1
ScicRegsFile : > SCIC, PAGE = 1
I2caRegsFile : > I2CA, PAGE = 1
/*** Code Security Module Register Structures ***/
CsmPwlFile : > CSM_PWL, PAGE = 1
/*** Device Part ID Register Structures ***/
PartIdRegsFile : > PARTID, PAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

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//###########################################################################
//
// FILE: Example_2833xEPwm_DMA.c
//
// TITLE: DSP2833x Device DMA interface with ePWM example.
//
// ASSUMPTIONS:
//
// This program requires the DSP2833x header files.
//
// As supplied, this project is configured for "boot to SARAM"
// operation. The 2833x Boot Mode table is shown below.
// For information on configuring the boot mode of an eZdsp,
// please refer to the documentation included with the eZdsp,
//
// $Boot_Table:
//
// GPIO87 GPIO86 GPIO85 GPIO84
// XA15 XA14 XA13 XA12
// PU PU PU PU
// ==========================================
// 1 1 1 1 Jump to Flash
// 1 1 1 0 SCI-A boot
// 1 1 0 1 SPI-A boot
// 1 1 0 0 I2C-A boot
// 1 0 1 1 eCAN-A boot
// 1 0 1 0 McBSP-A boot
// 1 0 0 1 Jump to XINTF x16
// 1 0 0 0 Jump to XINTF x32
// 0 1 1 1 Jump to OTP
// 0 1 1 0 Parallel GPIO I/O boot
// 0 1 0 1 Parallel XINTF boot
// 0 1 0 0 Jump to SARAM <- "boot to SARAM"
// 0 0 1 1 Branch to check boot mode
// 0 0 1 0 Boot to flash, bypass ADC cal
// 0 0 0 1 Boot to SARAM, bypass ADC cal
// 0 0 0 0 Boot to SCI-A, bypass ADC cal
// Boot_Table_End$
//
// DESCRIPTION:
//
// This example demonstrates several cases where the DMA is triggered from
// SOC signals generated by ePWM modules.
//
// DMA CH1 setup:
// Trigger = ADCSOCA from ePWM1
// Datasize = 16 bits
// Source = VarA
// Dest = EPwm1Regs.TBPRD
// Burst = One word / burst
// Transfer = One burst / transfer
// CPU int = every transfer
//
// DMA CH2 setup:
// Trigger = ADCSOCB from ePWM2
// Datasize = 32 bits
// Source = VarB
// Dest = EPwm1Regs.CMPA.all
// Burst = One 32-bit word / burst
// Transfer = One burst / transfer
// CPU int = none
//
// DMA CH3 setup:
// Trigger = ADC SEQ1INT
// Datasize = 32 bits
// Source = AdcMirror.ADCRESULT[0-5]
// Dest = ADCbuffer
// Burst = Three 32-bit words / burst
// Transfer = One burst / transfer
// CPU int = none
//
// Watch Variables:
//
// EPwm1Regs.TBPRD
// EPwm1Regs.CMPA.all
// ADCbuffer
// InterruptCount
//
//###########################################################################
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
// Prototype statements for functions found within this file.
void delay_loop(void);
void DMAInitialize(void);
void DMACH1Config(void);
void DMACH2Config(void);
void DMACH3Config(void);
void ConfigAdc(void);
void config_ePWM1_to_generate_ADCSOCA(void);
void config_ePWM2_to_generate_ADCSOCB(void);
interrupt void local_DINTCH1_ISR(void);
// Global Variables
#pragma DATA_SECTION(ADCbuffer,"DMARAML4");
volatile Uint32 ADCbuffer[3];
Uint16 VarA;
Uint32 VarB;
volatile Uint16 *MAPCNF = (Uint16 *)0x00702E;
Uint16 InterruptCount;
void main(void)
{
Uint16 i;
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// For this example use the following configuration:
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
EALLOW;
// Initialize PIE vector for CPU interrupt:
PieVectTable.DINTCH1 = &local_DINTCH1_ISR; // Point to DMA CH1 ISR
PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE
EDIS;
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
// Step 5. User specific code:
InterruptCount = 0;
EALLOW;
GpioCtrlRegs.GPADIR.all = 0xFFFFFFFF; // All outputs
SysCtrlRegs.MAPCNF.bit.MAPEPWM = 1; // Remap ePWMs for DMA access
EDIS;
GpioDataRegs.GPASET.all = 0xFFFFFFFF;
delay_loop();
GpioDataRegs.GPACLEAR.all = 0x00000002;
for(i=0; i<3; i++)
{
ADCbuffer[i] = ((Uint32)i*0x00011000) + 0x00044000;
}
VarA = 75;
VarB = 0x652000;
// Enable and configure clocks to peripherals:
EALLOW;
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // Enable SYSCLK to DMA
EDIS;
DMAInitialize();
DMACH1Config();
DMACH2Config();
DMACH3Config();
// Enable all interrupts:
IER = M_INT7; // Enable INT7 (7.1 DMA Ch1)
EINT;
InitAdc();
ConfigAdc();
config_ePWM1_to_generate_ADCSOCA();
config_ePWM2_to_generate_ADCSOCB();
EALLOW;
DmaRegs.CH1.CONTROL.bit.RUN = 1;
DmaRegs.CH2.CONTROL.bit.RUN = 1;
DmaRegs.CH3.CONTROL.bit.RUN = 1;
asm(" NOP");
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Up count mode
EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Up count mode
EDIS;
for(;;) {}
}
//===========================================================================
// DMA Functions
//===========================================================================
void DMAInitialize(void)
{
EALLOW;
// Perform a hard reset on DMA
DmaRegs.DMACTRL.bit.HARDRESET = 1;
// always perform one NOP after a HARDRESET
asm(" NOP");
// Stop DMA on emulation suspend
DmaRegs.DEBUGCTRL.bit.FREE = 0;
EDIS;
}
void DMACH1Config(void)
{
EALLOW;
// Configure CH1:
//
// Reset selected channel via CONTROL Register:
// DmaRegs.CH1.CONTROL.bit.SOFTRESET = 1; // Perform SOFT reset on channel (clears all counters)
// Set up MODE Register:
DmaRegs.CH1.MODE.bit.PERINTSEL = 18; // ePWM1 SOCA as peripheral interrupt source
DmaRegs.CH1.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled
DmaRegs.CH1.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt
DmaRegs.CH1.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer
DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal
DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal
DmaRegs.CH1.MODE.bit.DATASIZE = 0; // 16-bit data size transfers
DmaRegs.CH1.MODE.bit.CHINTMODE = 0; // Generate interrupt to CPU at the beg of transfer
DmaRegs.CH1.MODE.bit.CHINTE = 1; // Channel Interrupt to CPU enabled
// Set up BURST registers:
DmaRegs.CH1.BURST_SIZE.all = 0; // Number (N-1) of 16-bit words transferred in a burst
DmaRegs.CH1.SRC_BURST_STEP = 0; // Not needed since BURST_SIZE = 0
DmaRegs.CH1.DST_BURST_STEP = 0; // Not needed since BURST_SIZE = 0
// Set up TRANSFER registers:
DmaRegs.CH1.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer
DmaRegs.CH1.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
DmaRegs.CH1.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
// Set up WRAP registers:
DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around
DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around
DmaRegs.CH1.SRC_WRAP_STEP = 0;
DmaRegs.CH1.DST_WRAP_STEP = 0;
// Set up SOURCE address:
DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &VarA; // Point to variable in RAM
// Set up DESTINATION address:
DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &EPwm1Regs.TBPRD; // Point to ePWM1 TBPRD register remapped for DMA
// need to make sure .cmd file has ePWMs remapped
// Clear any spurious flags:
DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
EDIS;
}
void DMACH2Config(void)
{
EALLOW;
// Configure CH2:
//
// Reset selected channel via CONTROL Register:
// DmaRegs.CH2.CONTROL.bit.SOFTRESET = 1; // Perform SOFT reset on channel (clears all counters)
// Set up MODE Register:
DmaRegs.CH2.MODE.bit.PERINTSEL = 21; // ePWM2 SOCB as peripheral interrupt source
DmaRegs.CH2.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled
DmaRegs.CH2.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt
DmaRegs.CH2.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer
DmaRegs.CH2.MODE.bit.SYNCE = 0; // No sync signal
DmaRegs.CH2.MODE.bit.SYNCSEL = 0; // No sync signal
DmaRegs.CH2.MODE.bit.DATASIZE = 1; // 32-bit data size transfers
DmaRegs.CH2.MODE.bit.CHINTMODE = 0;
DmaRegs.CH2.MODE.bit.CHINTE = 0; // Channel Interrupt to CPU disabled
// Set up BURST registers:
DmaRegs.CH2.BURST_SIZE.all = 1; // Number (N-1) of 16-bit words transferred in a burst
DmaRegs.CH2.SRC_BURST_STEP = 0x0000; // Not needed since only 1 32-bit move per burst
DmaRegs.CH2.DST_BURST_STEP = 0x0000; // Not needed since only 1 32-bit move per burst
// Set up TRANSFER registers:
DmaRegs.CH2.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer
DmaRegs.CH2.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
DmaRegs.CH2.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
// Set up WRAP registers:
DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around
DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around
DmaRegs.CH2.SRC_WRAP_STEP = 0;
DmaRegs.CH2.DST_WRAP_STEP = 0;
// Set up SOURCE address:
DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &VarB; // Point to variable in RAM
// Set up DESTINATION address:
DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &EPwm1Regs.CMPA.all; // Point to ePWM1 CMPAHR/CMPA registers
// Clear any spurious flags:
DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
EDIS;
}
void DMACH3Config(void)
{
EALLOW;
// Configure CH3:
//
// Set up MODE Register:
DmaRegs.CH3.MODE.bit.PERINTSEL = 1; // ADC SEQ1INT as peripheral interrupt source
DmaRegs.CH3.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled
DmaRegs.CH3.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt
DmaRegs.CH3.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer
DmaRegs.CH3.MODE.bit.SYNCE = 0; // No sync signal
DmaRegs.CH3.MODE.bit.SYNCSEL = 0; // No sync signal
DmaRegs.CH3.MODE.bit.DATASIZE = 1; // 32-bit data size transfers
DmaRegs.CH3.MODE.bit.CHINTMODE = 0;
DmaRegs.CH3.MODE.bit.CHINTE = 0; // Channel Interrupt to CPU disabled
// Set up BURST registers:
DmaRegs.CH3.BURST_SIZE.all = 5; // Number (N-1) of 16-bit words transferred in a burst
DmaRegs.CH3.SRC_BURST_STEP = 2; // Increment source burst address by 2 (32-bit)
DmaRegs.CH3.DST_BURST_STEP = 2; // Increment destination burst address by 2 (32-bit)
// Set up TRANSFER registers:
DmaRegs.CH3.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer
DmaRegs.CH3.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
DmaRegs.CH3.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
// Set up WRAP registers:
DmaRegs.CH3.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around
DmaRegs.CH3.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around
DmaRegs.CH3.SRC_WRAP_STEP = 0;
DmaRegs.CH3.DST_WRAP_STEP = 0;
// Set up SOURCE address:
DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32) &AdcMirror.ADCRESULT0; // Point to first RESULT reg
// Set up DESTINATION address:
DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32) &ADCbuffer[0]; // Point to beginning of ADCbuffer
// Clear any spurious flags:
DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
EDIS;
}
interrupt void local_DINTCH1_ISR(void) // DMA INT7.1
{
GpioDataRegs.GPATOGGLE.all = 0x00000001; // Toggle GPIOA0
InterruptCount++;
if((DmaRegs.CH1.CONTROL.bit.OVRFLG == 1) || (DmaRegs.CH2.CONTROL.bit.OVRFLG == 1) ||
(DmaRegs.CH3.CONTROL.bit.OVRFLG == 1))
{
asm(" ESTOP0");
}
PieCtrlRegs.PIEACK.bit.ACK7 = 1; // Clear PIEIFR bit
}
void ConfigAdc(void)
{
AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 7;
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0; // ADCINA0
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 1; // ADCINA1
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 2; // ADCINA2
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 3; // ADCINA3
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 4; // ADCINA4
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 5; // ADCINA5
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1; // Enable ADC to accept ePWM_SOCA trigger
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear interrupt flag
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt
}
void config_ePWM1_to_generate_ADCSOCA(void)
{
// Configure ePWM1 Timer
// Interrupt triggers ADCSOCA
EALLOW;
EPwm1Regs.TBPRD = 74; // Setup period (one off so DMA transfer will be obvious)
EPwm1Regs.CMPA.all = 0x501000;
EPwm1Regs.ETSEL.bit.SOCASEL = 2; // ADCSOCA on TBCTR=TBPRD
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate SOCA on 1st event
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA generation
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // /1 clock mode
EDIS;
}
void config_ePWM2_to_generate_ADCSOCB(void)
{
// Configure ePWM2 Timer
// Interrupt triggers ADCSOCB
EALLOW;
EPwm2Regs.TBPRD = 150; // Setup periodSetup period
EPwm2Regs.CMPA.all = 0x200000;
EPwm2Regs.ETSEL.bit.SOCBSEL = 2; // ADCSOCB on TBCTR=TBPRD
EPwm2Regs.ETPS.bit.SOCBPRD = 1; // Generate SOCB on 1st event
EPwm2Regs.ETSEL.bit.SOCBEN = 1; // Enable SOCB generation
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // /1 clock mode
EDIS;
}
void delay_loop()
{
short i;
for (i = 0; i < 1000; i++) {}
}
//===========================================================================
// No more.
//===========================================================================

43
v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.gel Normal file
View File

@@ -0,0 +1,43 @@
/*
// TI File $Revision: /main/1 $
// Checkin $Date: June 19, 2008 10:25:20 $
//###########################################################################
//
// This .gel file can be used to help load and build the example project.
// It should be unloaded from Code Composer Studio before loading another
// project.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
*/
menuitem "DSP2833x ePWM DMA"
hotmenu Load_and_Build_Project()
{
GEL_ProjectLoad("Example_2833xEPwm_DMA.pjt");
GEL_ProjectBuild("Example_2833xEPwm_DMA.pjt");
Setup_WatchWindow();
}
hotmenu Load_Code()
{
GEL_Load(".\\debug\\Example_2833xEPwm_DMA.out");
Setup_WatchWindow();
}
hotmenu Setup_WatchWindow()
{
GEL_WatchReset();
GEL_WatchAdd("EPwm1Regs.TBPRD,x");
GEL_WatchAdd("EPwm1Regs.CMPA.all,x");
GEL_WatchAdd("ADCbuffer,x");
GEL_WatchAdd("InterruptCount,x");
GEL_WatchAdd("EPwm1Regs,x");
}

46
v120/DSP2833x_examples/epwm_dma/Example_2833xEPwm_DMA.pjt Normal file
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@@ -0,0 +1,46 @@
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
[Project Settings]
ProjectName="DSP2833x"
ProjectDir="C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\"
ProjectType=Executable
CPUFamily=TMS320C28XX
Tool="Compiler"
Tool="CustomBuilder"
Tool="DspBiosBuilder"
Tool="Linker"
Config="Debug"
Config="Release"
[Source Files]
Source="..\..\DSP2833x_common\source\DSP2833x_Adc.c"
Source="..\..\DSP2833x_common\source\DSP2833x_ADC_cal.asm"
Source="..\..\DSP2833x_common\source\DSP2833x_CodeStartBranch.asm"
Source="..\..\DSP2833x_common\source\DSP2833x_DefaultIsr.c"
Source="..\..\DSP2833x_common\source\DSP2833x_PieCtrl.c"
Source="..\..\DSP2833x_common\source\DSP2833x_PieVect.c"
Source="..\..\DSP2833x_common\source\DSP2833x_SysCtrl.c"
Source="..\..\DSP2833x_common\source\DSP2833x_usDelay.asm"
Source="..\..\DSP2833x_headers\source\DSP2833x_GlobalVariableDefs.c"
Source="Example_2833xEPwm_DMA.c"
Source="..\..\DSP2833x_common\cmd\28335_RAM_lnk.cmd"
Source="DSP2833x_EPWMDM_Headers_nonBIOS.cmd"
["Compiler" Settings: "Debug"]
Options=-g -q -pdr -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\Debug" -fs"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\Debug" -i"..\..\DSP2833x_headers\include" -i"..\..\DSP2833x_common\include" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28 --float_support=fpu32
["Compiler" Settings: "Release"]
Options=-q -o3 -fr"C:\tidcs\c28\DSP2833x\v120\DSP2833x_examples\epwm_dma\Release" -d"LARGE_MODEL" -ml -v28
["DspBiosBuilder" Settings: "Debug"]
Options=-v28
["DspBiosBuilder" Settings: "Release"]
Options=-v28
["Linker" Settings: "Debug"]
Options=-q -c -ecode_start -m".\Debug\Example_2833xEPwm_DMA.map" -o".\Debug\Example_2833xEPwm_DMA.out" -stack0x380 -w -x -i"..\..\DSP2833x_headers\include" -l"rts2800_fpu32.lib"
["Linker" Settings: "Release"]
Options=-q -c -m".\Release\Example_2833xEPwm_DMA.map" -o".\Release\Example_2833xEPwm_DMA.out" -x