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Проект каким он достался от Димы.
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nelolik
2021-02-15 09:56:02 +03:00
commit b8a0477c5c
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176
v120/DSP2833x_common/cmd/28332_RAM_lnk.cmd Normal file
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/*
// TI File $Revision: /main/9 $
// Checkin $Date: July 9, 2008 13:43:25 $
//###########################################################################
//
// FILE: 28332_RAM_lnk.cmd
//
// TITLE: Linker Command File For 28332 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 28332 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28332
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28332 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
/* BOOT_RSVD is used by the boot ROM for stack. */
/* This section is only reserved to keep the BOOT ROM from */
/* corrupting this area during the debug process */
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2 : origin = 0x00A000, length = 0x001000
RAML3 : origin = 0x00B000, length = 0x001000
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
ADC_CAL : origin = 0x380080, length = 0x000009
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
SECTIONS
{
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
codestart : > BEGIN, PAGE = 0
ramfuncs : > RAML0, PAGE = 0
.text : > RAML1, PAGE = 0
.cinit : > RAML0, PAGE = 0
.pinit : > RAML0, PAGE = 0
.switch : > RAML0, PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > RAML4, PAGE = 1
.econst : > RAML5, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > RAML1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
ZONE7DATA : > ZONE7B, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

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v120/DSP2833x_common/cmd/28334_RAM_lnk.cmd Normal file
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/*
// TI File $Revision: /main/8 $
// Checkin $Date: July 9, 2008 13:43:30 $
//###########################################################################
//
// FILE: 28334_RAM_lnk.cmd
//
// TITLE: Linker Command File For 28334 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 28334 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28334
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28334 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
/* BOOT_RSVD is used by the boot ROM for stack. */
/* This section is only reserved to keep the BOOT ROM from */
/* corrupting this area during the debug process */
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2 : origin = 0x00A000, length = 0x001000
RAML3 : origin = 0x00B000, length = 0x001000
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
ADC_CAL : origin = 0x380080, length = 0x000009
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
RAML6 : origin = 0x00E000, length = 0x001000
RAML7 : origin = 0x00F000, length = 0x001000
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
SECTIONS
{
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
codestart : > BEGIN, PAGE = 0
ramfuncs : > RAML0, PAGE = 0
.text : > RAML1, PAGE = 0
.cinit : > RAML0, PAGE = 0
.pinit : > RAML0, PAGE = 0
.switch : > RAML0, PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > RAML4, PAGE = 1
.econst : > RAML5, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > RAML1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
ZONE7DATA : > ZONE7B, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

176
v120/DSP2833x_common/cmd/28335_RAM_lnk.cmd Normal file
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/*
// TI File $Revision: /main/10 $
// Checkin $Date: July 9, 2008 13:43:36 $
//###########################################################################
//
// FILE: 28335_RAM_lnk.cmd
//
// TITLE: Linker Command File For 28335 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 28335 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28335
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28335 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
/* BOOT_RSVD is used by the boot ROM for stack. */
/* This section is only reserved to keep the BOOT ROM from */
/* corrupting this area during the debug process */
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2 : origin = 0x00A000, length = 0x001000
RAML3 : origin = 0x00B000, length = 0x001000
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
ADC_CAL : origin = 0x380080, length = 0x000009
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
BOOTROM : origin = 0x3FF27C, length = 0x000D44
PAGE 1 :
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
RAML6 : origin = 0x00E000, length = 0x001000
RAML7 : origin = 0x00F000, length = 0x001000
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
SECTIONS
{
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
codestart : > BEGIN, PAGE = 0
ramfuncs : > RAML0, PAGE = 0
.text : > RAML1, PAGE = 0
.cinit : > RAML0, PAGE = 0
.pinit : > RAML0, PAGE = 0
.switch : > RAML0, PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > RAML4, PAGE = 1
.econst : > RAML5, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > RAML1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
ZONE7DATA : > ZONE7B, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

197
v120/DSP2833x_common/cmd/F28332.cmd Normal file
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/*
// TI File $Revision: /main/9 $
// Checkin $Date: July 9, 2008 13:43:41 $
//###########################################################################
//
// FILE: F28332.cmd
//
// TITLE: Linker Command File For F28332 Device
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28332
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28332 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
ZONE6 : origin = 0x100000, length = 0x100000 /* XINTF zone 6 */
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
ZONE7B : origin = 0x20FC00, length = 0x0000400 /* XINTF zone 7 - data space */
FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAML4 PAGE = 1
.esysmem : > RAMM1 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHC PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate DMA-accessible RAM sections: */
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
/* Allocate 0x400 of XINTF Zone 7 to storing data */
ZONE7DATA : > ZONE7B, PAGE = 1
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

203
v120/DSP2833x_common/cmd/F28334.cmd Normal file
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/*
// TI File $Revision: /main/9 $
// Checkin $Date: July 9, 2008 13:43:49 $
//###########################################################################
//
// FILE: F28334.cmd
//
// TITLE: Linker Command File For F28334 Device
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28334
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28334 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
ZONE6 : origin = 0x100000, length = 0x0100000 /* XINTF zone 6 */
ZONE7A : origin = 0x200000, length = 0x000FC00 /* XINTF zone 7 - program space */
FLASHH : origin = 0x320000, length = 0x004000 /* on-chip FLASH */
FLASHG : origin = 0x324000, length = 0x004000 /* on-chip FLASH */
FLASHF : origin = 0x328000, length = 0x004000 /* on-chip FLASH */
FLASHE : origin = 0x32C000, length = 0x004000 /* on-chip FLASH */
FLASHD : origin = 0x330000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x334000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x33C000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
FLASHB : origin = 0x338000, length = 0x004000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAML4 PAGE = 1
.esysmem : > RAMM1 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHC PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate DMA-accessible RAM sections: */
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
/* Allocate 0x400 of XINTF Zone 7 to storing data */
ZONE7DATA : > ZONE7B, PAGE = 1
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

203
v120/DSP2833x_common/cmd/F28335.cmd Normal file
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/*
// TI File $Revision: /main/10 $
// Checkin $Date: July 9, 2008 13:43:56 $
//###########################################################################
//
// FILE: F28335.cmd
//
// TITLE: Linker Command File For F28335 Device
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28335
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28335 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */
ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */
FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */
FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */
FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */
FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */
FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */
FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */
FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAML4 PAGE = 1
.esysmem : > RAMM1 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHC PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate DMA-accessible RAM sections: */
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
/* Allocate 0x400 of XINTF Zone 7 to storing data */
ZONE7DATA : > ZONE7B, PAGE = 1
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

2822
v120/DSP2833x_common/gel/f28232.gel Normal file
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@@ -0,0 +1,2822 @@
/********************************************************************/
/* f28232.gel */
/* Version 3.30.2 */
/* */
/* This GEL file is to be used with the TMS320F28232 DSP. */
/* Changes may be required to support specific hardware designs. */
/* */
/* Code Composer Studio supports six reserved GEL functions that */
/* automatically get executed if they are defined. They are: */
/* */
/* StartUp() - Executed whenever CCS is invoked */
/* OnReset() - Executed after Debug->Reset CPU */
/* OnRestart() - Executed after Debug->Restart */
/* OnPreFileLoaded() - Executed before File->Load Program */
/* OnFileLoaded() - Executed after File->Load Program */
/* OnTargetConnect() - Executed after Debug->Connect */
/* */
/********************************************************************/
StartUp()
{
/* The next line automatically loads the .gel file that comes */
/* with the DSP2833x Peripheral Header Files download. To use, */
/* uncomment, and adjust the directory path as needed. */
// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel");
}
OnReset(int nErrorCode)
{
C28x_Mode();
Unlock_CSM();
ADC_Cal();
}
OnRestart(int nErrorCode)
{
/* CCS will call OnRestart() when you do a Debug->Restart and */
/* after you load a new file. Between running interrupt based */
/* programs, this function will clear interrupts and help keep */
/* the processor from going off into invalid memory. */
C28x_Mode();
IER = 0;
IFR = 0;
ADC_Cal();
}
int TxtOutCtl=0;
OnPreFileLoaded()
{
XINTF_Enable();
if (TxtOutCtl==0)
{
GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use.");
TxtOutCtl=1;
}
}
OnFileLoaded(int nErrorCode, int bSymbolsOnly)
{
ADC_Cal();
}
OnTargetConnect()
{
C28x_Mode();
F28232_Memory_Map(); /* Initialize the CCS memory map */
/* Check to see if CCS has been started-up with the DSP already */
/* running in real-time mode. The user can add whatever */
/* custom initialization stuff they want to each case. */
if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */
{
}
else /* Do stop-mode target initialization */
{
GEL_Reset(); /* Reset DSP */
}
}
/********************************************************************/
/* These functions are launched by the GEL_Toolbar button plugin */
/********************************************************************/
GEL_Toolbar1()
{
Run_Realtime_with_Reset();
}
GEL_Toolbar2()
{
Run_Realtime_with_Restart();
}
GEL_Toolbar3()
{
Full_Halt();
}
GEL_Toolbar4()
{
Full_Halt_with_Reset();
}
int GEL_Toolbar5_Toggle = 0;
GEL_Toolbar5()
{
if(GEL_Toolbar5_Toggle == 0)
{
GEL_Toolbar5_Toggle = 1;
GEL_OpenWindow("GEL_Buttons",1,4);
GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0);
GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1);
GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2);
GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3);
}
else
{
GEL_Toolbar5_Toggle = 0;
GEL_CloseWindow("GEL_Buttons");
}
}
/********************************************************************/
/* These functions are useful to engage/dis-enagage realtime */
/* emulation mode during debug. They save the user from having to */
/* manually perform these steps in CCS. */
/********************************************************************/
menuitem "Realtime Emulation Control";
hotmenu Run_Realtime_with_Reset()
{
GEL_Reset(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Run_Realtime_with_Restart()
{
GEL_Restart(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Full_Halt()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
}
hotmenu Full_Halt_with_Reset()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
GEL_Reset(); /* Reset the DSP */
}
/********************************************************************/
/* F28232 Memory Map */
/* */
/* Note: M0M1MAP and VMAP signals tied high on F28232 core */
/* */
/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */
/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */
/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */
/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */
/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */
/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */
/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */
/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */
/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */
/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */
/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */
/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */
/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */
/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */
/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */
/* 0x330000 - 0x33ffff Flash (Prog and Data) */
/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */
/* 0x380090 - 0x380090 PARTID value (Prog and Data) */
/* 0x380400 - 0x3807ff OTP (Prog and Data) */
/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */
/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */
/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */
/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */
/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */
/********************************************************************/
menuitem "Initialize Memory Map";
hotmenu F28232_Memory_Map()
{
GEL_MapReset();
GEL_MapOn();
/* Program memory map */
GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x330000,0,0x10000,1,0); /* FLASH */
GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */
GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */
/* Data memory map */
GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */
GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */
GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */
GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */
GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x330000,1,0x10000,1,0); /* FLASH */
GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */
GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */
}
/********************************************************************/
/* The ESTOP0 fill functions are useful for debug. They fill the */
/* RAM with software breakpoints that will trap runaway code. */
/********************************************************************/
hotmenu Fill_F28232_RAM_with_ESTOP0()
{
GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */
GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */
GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */
GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */
}
/********************************************************************/
menuitem "Watchdog";
hotmenu Disable_WD()
{
*0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */
*0x7025 = 0x0055; /* Service the WD */
*0x7025 = 0x00AA; /* once to be safe. */
GEL_TextOut("\nWatchdog Timer Disabled");
}
/********************************************************************/
menuitem "Code Security Module"
hotmenu Unlock_CSM()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
/* Write passwords to the KEY registers. 0xFFFF's are dummy passwords.
User should replace them with the correct password for their DSP */
*0xAE0 = 0xFFFF;
*0xAE1 = 0xFFFF;
*0xAE2 = 0xFFFF;
*0xAE3 = 0xFFFF;
*0xAE4 = 0xFFFF;
*0xAE5 = 0xFFFF;
*0xAE6 = 0xFFFF;
*0xAE7 = 0xFFFF;
}
/********************************************************************/
menuitem "Addressing Modes";
hotmenu C28x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C24x_Mode()
{
ST1 = ST1 | 0x0100; /* AMODE = 1 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C27x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */
}
/********************************************************************/
/* PLL Ratios */
/* */
/* The following table describes the PLL clocking ratios (0..10) */
/* */
/* Ratio CLKIN Description */
/* ----- -------------- ------------ */
/* 0 OSCCLK/2 PLL bypassed */
/* 1 (OSCCLK * 1)/2 10 Mhz for 20 Mhz CLKIN */
/* 2 (OSCCLK * 2)/2 20 Mhz for 20 Mhz CLKIN */
/* 3 (OSCCLK * 3)/2 30 Mhz for 20 Mhz CLKIN */
/* 4 (OSCCLK * 4)/2 40 Mhz for 20 Mhz CLKIN */
/* 5 (OSCCLK * 5)/2 50 Mhz for 20 Mhz CLKIN */
/* 6 (OSCCLK * 6)/2 60 Mhz for 20 Mhz CLKIN */
/* 7 (OSCCLK * 7)/2 70 Mhz for 20 Mhz CLKIN */
/* 8 (OSCCLK * 8)/2 80 Mhz for 20 Mhz CLKIN */
/* 9 (OSCCLK * 9)/2 90 Mhz for 20 Mhz CLKIN */
/* 10 (OSCCLK * 10)/2 100 Mhz for 20 Mhz CLKIN */
/********************************************************************/
menuitem "Set PLL Ratio";
hotmenu Bypass()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */
PLL_Wait();
}
hotmenu OSCCLK_x1_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x2_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x3_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x4_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x5_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x6_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x7_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x8_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x9_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x10_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */
PLL_Wait();
}
// hotmenu OSCCLK_x1_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x2_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x3_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x4_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x5_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x6_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x7_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x8_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x9_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x10_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */
// PLL_Wait();
// }
/********************************************************************/
/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */
/********************************************************************/
DIVSEL_div2()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
temp = *PLLSTS;
temp &= 0xFE7F; /* Clear bits 7 & 8 */
temp |= 2 << 7; /* Set bit 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
/********************************************************************/
/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to /1 */
/********************************************************************/
DIVSEL_div1()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */
wait();
temp = *PLLSTS;
temp |= 3 << 7; /* Set bits 7 & 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
wait()
{
int delay = 0;
for (delay = 0; delay <= 5; delay ++)
{}
}
/********************************************************************/
/* For F2823x devices, check the PLLOCKS bit for PLL lock. */
/********************************************************************/
PLL_Wait()
{
int PLLSTS;
int delay = 0;
PLLSTS = 0x7011;
while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001)
{
delay++;
GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
/********************************************************************/
/* Load the ADC Calibration values from TI OTP */
/********************************************************************/
menuitem "ADC Calibration"
hotmenu ADC_Cal()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
if(((*0x0AEF) & 0x0001) == 0)
{
XAR0 = *0x701C;
*0x701C |= 0x0008;
*0x711C = *0x380083;
*0x711D = *0x380085;
*0x701C = XAR0;
XAR0 = 0;
}
else
{
GEL_TextOut("\nADC Calibration not complete, device is secure");
}
}
/********************************************************************/
/* Enable the XINTF and configure GPIOs for XINTF function */
/********************************************************************/
menuitem "XINTF Enable"
hotmenu XINTF_Enable()
{
/* enable XINTF clock (XTIMCLK) */
*0x7020 = 0x3700;
/* GPBMUX1: XA0-XA7, XA16, XZCS0, */
/* XZCS7, XREADY, XRNW, XWE0 */
/* GPAMUX2: XA17-XA19, XZCS6 */
/* GPCMUX2: XA8-XA15 */
/* GPCMUX1: XD0-XD15 */
*(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */
*(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */
*(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */
*(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */
/* Uncomment for x32 data bus */
/* GPBMUX2: XD16-XD31 */
// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */
/* Zone timing.
/* Each zone can be configured seperately */
/* Uncomment the x16 or the x32 timing */
/* depending on the data bus width for */
/* the zone */
/* x16 Timing */
*(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */
*(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */
*(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */
/* x32 Timing:
// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */
}
/********************************************************************/
/* The below are used to display the symbolic names of the F28232 */
/* memory mapped registers in the watch window. To view these */
/* registers, click on the GEL menu button in Code Composer Studio, */
/* then select which registers or groups of registers you want to */
/* view. They will appear in the watch window under the Watch1 tab. */
/********************************************************************/
/* Add a space line to the GEL menu */
menuitem "______________________________________";
hotmenu __() {}
/********************************************************************/
/* A/D Converter Registers */
/********************************************************************/
menuitem "Watch ADC Registers";
hotmenu All_ADC_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
hotmenu ADC_Control_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
}
hotmenu ADCCHSELSEQx_Regs()
{
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
}
hotmenu ADCRESULT_0_to_7()
{
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
}
hotmenu ADCRESULT_8_to_15()
{
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
}
hotmenu ADCRESULT_Mirror_0_to_7()
{
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
}
hotmenu ADCRESULT_Mirror_8_to_15()
{
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
/********************************************************************/
/* Clocking and Low-Power Registers */
/********************************************************************/
menuitem "Watch Clocking and Low-Power Registers";
hotmenu All_Clocking_and_Low_Power_Regs()
{
GEL_WatchAdd("*0x7010,x","XCLK");
GEL_WatchAdd("*0x7011,x","PLLSTS");
GEL_WatchAdd("*0x701A,x","HISPCP");
GEL_WatchAdd("*0x701B,x","LOSPCP");
GEL_WatchAdd("*0x701C,x","PCLKCR0");
GEL_WatchAdd("*0x701D,x","PCLKCR1");
GEL_WatchAdd("*0x701E,x","LPMCR0");
GEL_WatchAdd("*0x7020,x","PCLKCR3");
GEL_WatchAdd("*0x7021,x","PLLCR");
}
/********************************************************************/
/* Code Security Module Registers */
/********************************************************************/
menuitem "Watch Code Security Module Registers";
hotmenu CSMSCR()
{
GEL_WatchAdd("*0x0AEF,x","CSMSCR");
GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit");
GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit");
}
hotmenu PWL_Locations()
{
GEL_WatchAdd("*0x33FFF8,x","PWL0");
GEL_WatchAdd("*0x33FFF9,x","PWL1");
GEL_WatchAdd("*0x33FFFA,x","PWL2");
GEL_WatchAdd("*0x33FFFB,x","PWL3");
GEL_WatchAdd("*0x33FFFC,x","PWL4");
GEL_WatchAdd("*0x33FFFD,x","PWL5");
GEL_WatchAdd("*0x33FFFE,x","PWL6");
GEL_WatchAdd("*0x33FFFF,x","PWL7");
}
/********************************************************************/
/* CPU Timer Registers */
/********************************************************************/
menuitem "Watch CPU Timer Registers";
hotmenu All_CPU_Timer0_Regs()
{
GEL_WatchAdd("*0x0C00,x","TIMER0TIM");
GEL_WatchAdd("*0x0C01,x","TIMER0TIMH");
GEL_WatchAdd("*0x0C02,x","TIMER0PRD");
GEL_WatchAdd("*0x0C03,x","TIMER0PRDH");
GEL_WatchAdd("*0x0C04,x","TIMER0TCR");
GEL_WatchAdd("*0x0C06,x","TIMER0TPR");
GEL_WatchAdd("*0x0C07,x","TIMER0TPRH");
}
hotmenu All_CPU_Timer1_Regs()
{
GEL_WatchAdd("*0x0C08,x","TIMER1TIM");
GEL_WatchAdd("*0x0C09,x","TIMER1TIMH");
GEL_WatchAdd("*0x0C0A,x","TIMER1PRD");
GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH");
GEL_WatchAdd("*0x0C0C,x","TIMER1TCR");
GEL_WatchAdd("*0x0C0E,x","TIMER1TPR");
GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH");
}
hotmenu All_CPU_Timer2_Regs()
{
GEL_WatchAdd("*0x0C10,x","TIMER2TIM");
GEL_WatchAdd("*0x0C11,x","TIMER2TIMH");
GEL_WatchAdd("*0x0C12,x","TIMER2PRD");
GEL_WatchAdd("*0x0C13,x","TIMER2PRDH");
GEL_WatchAdd("*0x0C14,x","TIMER2TCR");
GEL_WatchAdd("*0x0C16,x","TIMER2TPR");
GEL_WatchAdd("*0x0C17,x","TIMER2TPRH");
}
/********************************************************************/
/* Device Emulation Registers */
/********************************************************************/
menuitem "Watch Device Emulation Registers";
hotmenu All_Emulation_Regs()
{
GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF");
GEL_WatchAdd("*0x0882,x","CLASSID");
GEL_WatchAdd("*0x0883,x","REVID");
GEL_WatchAdd("*0x0884,x","PROTSTART");
GEL_WatchAdd("*0x0885,x","PROTRANGE");
GEL_WatchAdd("*0x380090,x","PARTID");
}
/********************************************************************/
/* DMA Registers */
/********************************************************************/
menuitem "Watch DMA Registers";
hotmenu All_DMA_Regs()
{
GEL_WatchAdd("*0x1000,x","DMACTRL");
GEL_WatchAdd("*0x1001,x","DEBUGCTRL");
GEL_WatchAdd("*0x1002,x","REVISION");
GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1");
GEL_WatchAdd("*0x1006,x","PRIORITYSTAT");
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_1_regs()
{
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_2_regs()
{
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_3_regs()
{
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_4_regs()
{
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_5_regs()
{
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_6_regs()
{
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
/********************************************************************/
/* eCAN Registers */
/********************************************************************/
menuitem "Watch eCAN Registers";
hotmenu eCAN_A_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME");
GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD");
GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS");
GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR");
GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA");
GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA");
GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP");
GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML");
GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP");
GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC");
GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC");
GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES");
GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC");
GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC");
GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0");
GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM");
GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1");
GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM");
GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL");
GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC");
GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC");
GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC");
GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT");
GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC");
GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS");
}
hotmenu eCAN_A_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0");
GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0");
GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0");
GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0");
GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0");
GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0");
GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0");
GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1");
GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1");
GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1");
GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1");
GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1");
GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1");
GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1");
}
hotmenu eCAN_A_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2");
GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2");
GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2");
GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2");
GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2");
GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2");
GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2");
GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3");
GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3");
GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3");
GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3");
GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3");
GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3");
GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3");
}
hotmenu eCAN_A_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4");
GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4");
GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4");
GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4");
GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4");
GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4");
GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4");
GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5");
GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5");
GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5");
GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5");
GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5");
GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5");
GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5");
}
hotmenu eCAN_A_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6");
GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6");
GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6");
GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6");
GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6");
GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6");
GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6");
GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7");
GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7");
GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7");
GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7");
GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7");
GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7");
GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7");
}
hotmenu eCAN_A_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8");
GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8");
GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8");
GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8");
GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8");
GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8");
GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8");
GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9");
GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9");
GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9");
GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9");
GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9");
GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9");
GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9");
}
hotmenu eCAN_A_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10");
GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10");
GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10");
GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10");
GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10");
GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10");
GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10");
GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11");
GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11");
GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11");
GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11");
GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11");
GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11");
GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11");
}
hotmenu eCAN_A_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12");
GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12");
GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12");
GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12");
GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12");
GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12");
GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12");
GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13");
GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13");
GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13");
GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13");
GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13");
GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13");
GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13");
}
hotmenu eCAN_A_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14");
GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14");
GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14");
GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14");
GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14");
GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14");
GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14");
GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15");
GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15");
GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15");
GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15");
GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15");
GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15");
GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15");
}
hotmenu eCAN_A_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16");
GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16");
GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16");
GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16");
GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16");
GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16");
GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16");
GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17");
GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17");
GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17");
GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17");
GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17");
GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17");
GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17");
}
hotmenu eCAN_A_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18");
GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18");
GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18");
GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18");
GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18");
GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18");
GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18");
GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19");
GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19");
GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19");
GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19");
GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19");
GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19");
GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19");
}
hotmenu eCAN_A_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20");
GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20");
GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20");
GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20");
GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20");
GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20");
GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20");
GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21");
GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21");
GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21");
GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21");
GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21");
GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21");
GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21");
}
hotmenu eCAN_A_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22");
GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22");
GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22");
GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22");
GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22");
GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22");
GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22");
GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23");
GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23");
GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23");
GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23");
GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23");
GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23");
GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23");
}
hotmenu eCAN_A_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24");
GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24");
GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24");
GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24");
GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24");
GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24");
GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24");
GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25");
GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25");
GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25");
GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25");
GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25");
GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25");
GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25");
}
hotmenu eCAN_A_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26");
GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26");
GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26");
GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26");
GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26");
GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26");
GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26");
GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27");
GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27");
GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27");
GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27");
GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27");
GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27");
GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27");
}
hotmenu eCAN_A_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28");
GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28");
GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28");
GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28");
GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28");
GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28");
GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28");
GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29");
GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29");
GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29");
GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29");
GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29");
GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29");
GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29");
}
hotmenu eCAN_A_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30");
GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30");
GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30");
GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30");
GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30");
GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30");
GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30");
GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31");
GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31");
GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31");
GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31");
GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31");
GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31");
GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31");
}
hotmenu eCAN_B_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME");
GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD");
GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS");
GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR");
GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA");
GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA");
GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP");
GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML");
GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP");
GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC");
GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC");
GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES");
GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC");
GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC");
GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0");
GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM");
GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1");
GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM");
GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL");
GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC");
GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC");
GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC");
GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT");
GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC");
GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS");
}
hotmenu eCAN_B_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0");
GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0");
GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0");
GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0");
GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0");
GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0");
GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0");
GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1");
GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1");
GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1");
GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1");
GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1");
GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1");
GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1");
}
hotmenu eCAN_B_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2");
GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2");
GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2");
GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2");
GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2");
GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2");
GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2");
GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3");
GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3");
GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3");
GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3");
GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3");
GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3");
GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3");
}
hotmenu eCAN_B_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4");
GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4");
GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4");
GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4");
GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4");
GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4");
GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4");
GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5");
GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5");
GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5");
GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5");
GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5");
GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5");
GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5");
}
hotmenu eCAN_B_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6");
GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6");
GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6");
GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6");
GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6");
GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6");
GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6");
GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7");
GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7");
GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7");
GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7");
GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7");
GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7");
GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7");
}
hotmenu eCAN_B_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8");
GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8");
GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8");
GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8");
GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8");
GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8");
GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8");
GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9");
GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9");
GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9");
GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9");
GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9");
GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9");
GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9");
}
hotmenu eCAN_B_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10");
GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10");
GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10");
GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10");
GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10");
GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10");
GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10");
GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11");
GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11");
GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11");
GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11");
GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11");
GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11");
GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11");
}
hotmenu eCAN_B_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12");
GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12");
GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12");
GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12");
GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12");
GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12");
GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12");
GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13");
GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13");
GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13");
GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13");
GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13");
GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13");
GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13");
}
hotmenu eCAN_B_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14");
GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14");
GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14");
GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14");
GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14");
GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14");
GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14");
GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15");
GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15");
GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15");
GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15");
GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15");
GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15");
GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15");
}
hotmenu eCAN_B_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16");
GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16");
GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16");
GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16");
GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16");
GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16");
GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16");
GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17");
GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17");
GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17");
GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17");
GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17");
GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17");
GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17");
}
hotmenu eCAN_B_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18");
GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18");
GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18");
GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18");
GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18");
GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18");
GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18");
GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19");
GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19");
GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19");
GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19");
GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19");
GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19");
GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19");
}
hotmenu eCAN_B_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20");
GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20");
GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20");
GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20");
GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20");
GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20");
GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20");
GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21");
GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21");
GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21");
GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21");
GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21");
GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21");
GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21");
}
hotmenu eCAN_B_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22");
GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22");
GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22");
GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22");
GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22");
GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22");
GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22");
GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23");
GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23");
GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23");
GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23");
GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23");
GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23");
GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23");
}
hotmenu eCAN_B_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24");
GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24");
GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24");
GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24");
GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24");
GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24");
GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24");
GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25");
GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25");
GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25");
GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25");
GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25");
GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25");
GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25");
}
hotmenu eCAN_B_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26");
GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26");
GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26");
GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26");
GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26");
GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26");
GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26");
GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27");
GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27");
GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27");
GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27");
GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27");
GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27");
GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27");
}
hotmenu eCAN_B_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28");
GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28");
GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28");
GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28");
GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28");
GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28");
GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28");
GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29");
GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29");
GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29");
GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29");
GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29");
GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29");
GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29");
}
hotmenu eCAN_B_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30");
GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30");
GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30");
GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30");
GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30");
GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30");
GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30");
GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31");
GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31");
GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31");
GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31");
GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31");
GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31");
GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31");
}
/********************************************************************/
/* Enhanced Capture Registers */
/********************************************************************/
menuitem "Watch eCAP Registers";
hotmenu eCAP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT");
GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS");
GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1");
GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2");
GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3");
GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4");
GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1");
GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2");
GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT");
GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG");
GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR");
GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC");
}
hotmenu eCAP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT");
GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS");
GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1");
GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2");
GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3");
GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4");
GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1");
GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2");
GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT");
GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG");
GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR");
GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC");
}
hotmenu eCAP3_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT");
GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS");
GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1");
GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2");
GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3");
GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4");
GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1");
GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2");
GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT");
GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG");
GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR");
GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC");
}
hotmenu eCAP4_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT");
GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS");
GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1");
GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2");
GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3");
GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4");
GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1");
GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2");
GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT");
GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG");
GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR");
GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC");
}
/********************************************************************/
/* Enhanced PWM Registers */
/********************************************************************/
menuitem "Watch ePWM Registers";
hotmenu ePWM1_All_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL");
GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG");
}
hotmenu ePWM1_TB_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
}
hotmenu ePWM1_CMP_Regs()
{
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
}
hotmenu ePWM1_AQ_Regs()
{
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
}
hotmenu ePWM1_DB_Regs()
{
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
}
hotmenu ePWM1_TZ_Regs()
{
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
}
hotmenu ePWM1_ET_Regs()
{
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
}
hotmenu ePWM2_All_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL");
GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG");
}
hotmenu ePWM2_TB_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
}
hotmenu ePWM2_CMP_Regs()
{
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
}
hotmenu ePWM2_AQ_Regs()
{
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
}
hotmenu ePWM2_DB_Regs()
{
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
}
hotmenu ePWM2_TZ_Regs()
{
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
}
hotmenu ePWM2_ET_Regs()
{
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
}
hotmenu ePWM3_All_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL");
GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG");
}
hotmenu ePWM3_TB_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
}
hotmenu ePWM3_CMP_Regs()
{
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
}
hotmenu ePWM3_AQ_Regs()
{
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
}
hotmenu ePWM3_DB_Regs()
{
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
}
hotmenu ePWM3_TZ_Regs()
{
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
}
hotmenu ePWM3_ET_Regs()
{
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
}
hotmenu ePWM4_All_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL");
GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG");
}
hotmenu ePWM4_TB_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
}
hotmenu ePWM4_CMP_Regs()
{
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
}
hotmenu ePWM4_AQ_Regs()
{
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
}
hotmenu ePWM4_DB_Regs()
{
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
}
hotmenu ePWM4_TZ_Regs()
{
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
}
hotmenu ePWM4_ET_Regs()
{
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
}
hotmenu ePWM5_All_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL");
}
hotmenu ePWM5_TB_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
}
hotmenu ePWM5_CMP_Regs()
{
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
}
hotmenu ePWM5_AQ_Regs()
{
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
}
hotmenu ePWM5_DB_Regs()
{
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
}
hotmenu ePWM5_TZ_Regs()
{
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
}
hotmenu ePWM5_ET_Regs()
{
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
}
hotmenu ePWM6_All_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL");
}
hotmenu ePWM6_TB_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
}
hotmenu ePWM6_CMP_Regs()
{
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
}
hotmenu ePWM6_AQ_Regs()
{
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
}
hotmenu ePWM6_DB_Regs()
{
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
}
hotmenu ePWM6_TZ_Regs()
{
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
}
hotmenu ePWM6_ET_Regs()
{
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
}
/********************************************************************/
/* Enhanced EQEP Registers */
/********************************************************************/
menuitem "Watch eQEP"
hotmenu eQEP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT");
GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR");
GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD");
GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR");
GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD");
GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL");
GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL");
GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL");
GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL");
GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT");
GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG");
GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR");
GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC");
GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS");
GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR");
GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD");
GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT");
GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT");
}
hotmenu eQEP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT");
GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR");
GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD");
GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR");
GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD");
GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL");
GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL");
GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL");
GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL");
GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT");
GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG");
GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR");
GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC");
GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS");
GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR");
GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD");
GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT");
GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT");
}
/********************************************************************/
/* External Interface Registers */
/********************************************************************/
menuitem "Watch External Interface Registers";
hotmenu All_External_Interface_Regs()
{
GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0");
GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6");
GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7");
GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2");
GEL_WatchAdd("*0x0B38,x","XBANK");
GEL_WatchAdd("*0x0B3A,x","XREVISION");
GEL_WatchAdd("*0x0B3D,x","XRESET");
}
/********************************************************************/
/* External Interrupt Registers */
/********************************************************************/
menuitem "Watch External Interrupt Registers";
hotmenu All_XINT_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
hotmenu XINT_Control_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
}
hotmenu XINT_Counter_Regs()
{
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
/********************************************************************/
/* GPIO Registers */
/********************************************************************/
menuitem "Watch GPIO Registers";
hotmenu All_GPIO_CONTROL_Regs()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
}
hotmenu All_GPIO_DATA_Regs()
{
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
hotmenu All_GPIO_INTERRUPT_Regs()
{
GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL");
GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL");
GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL");
GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL");
GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL");
GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL");
GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL");
GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL");
GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL");
}
hotmenu All_GPA_Registers()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
}
hotmenu All_GPB_Registers()
{
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
}
hotmenu All_GPC_Registers()
{
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
/********************************************************************/
/* Multichannel Serial Port Registers */
/********************************************************************/
menuitem "Watch McBSP Registers";
hotmenu All_McBSP_A_Regs()
{
GEL_WatchAdd("*0x5000,x","McBSPA DRR2");
GEL_WatchAdd("*0x5001,x","McBSPA DRR1");
GEL_WatchAdd("*0x5002,x","McBSPA DXR2");
GEL_WatchAdd("*0x5003,x","McBSPA DXR1");
GEL_WatchAdd("*0x5004,x","McBSPA SPCR2");
GEL_WatchAdd("*0x5005,x","McBSPA SPCR1");
GEL_WatchAdd("*0x5006,x","McBSPA RCR2");
GEL_WatchAdd("*0x5007,x","McBSPA RCR1");
GEL_WatchAdd("*0x5008,x","McBSPA XCR2");
GEL_WatchAdd("*0x5009,x","McBSPA XCR1");
GEL_WatchAdd("*0x500A,x","McBSPA SRGR2");
GEL_WatchAdd("*0x500B,x","McBSPA SRGR1");
GEL_WatchAdd("*0x500C,x","McBSPA MCR2");
GEL_WatchAdd("*0x500D,x","McBSPA MCR1");
GEL_WatchAdd("*0x500E,x","McBSPA RCERA");
GEL_WatchAdd("*0x500F,x","McBSPA RCERB");
GEL_WatchAdd("*0x5010,x","McBSPA XCERA");
GEL_WatchAdd("*0x5011,x","McBSPA XCERB");
GEL_WatchAdd("*0x5012,x","McBSPA PCR1");
GEL_WatchAdd("*0x5013,x","McBSPA RCERC");
GEL_WatchAdd("*0x5014,x","McBSPA RCERD");
GEL_WatchAdd("*0x5015,x","McBSPA XCERC");
GEL_WatchAdd("*0x5016,x","McBSPA XCERD");
GEL_WatchAdd("*0x5017,x","McBSPA RCERE");
GEL_WatchAdd("*0x5018,x","McBSPA RCERF");
GEL_WatchAdd("*0x5019,x","McBSPA XCERE");
GEL_WatchAdd("*0x501A,x","McBSPA XCERF");
GEL_WatchAdd("*0x501B,x","McBSPA RCERG");
GEL_WatchAdd("*0x501C,x","McBSPA RCERH");
GEL_WatchAdd("*0x501D,x","McBSPA XCERG");
GEL_WatchAdd("*0x501E,x","McBSPA XCERH");
GEL_WatchAdd("*0x5023,x","McBSPA MFFINT");
GEL_WatchAdd("*0x503F,x","McBSPA Revision");
}
/********************************************************************/
/* I2C Registers */
/********************************************************************/
menuitem "Watch I2C Registers";
hotmenu All_I2C_Regs()
{
GEL_WatchAdd("*0x7900,x","I2COAR");
GEL_WatchAdd("*0x7901,x","I2CIER");
GEL_WatchAdd("*0x7902,x","I2CSTR");
GEL_WatchAdd("*0x7903,x","I2CCLKL");
GEL_WatchAdd("*0x7904,x","I2CCLKH");
GEL_WatchAdd("*0x7905,x","I2CCNT");
GEL_WatchAdd("*0x7906,x","I2CDRR");
GEL_WatchAdd("*0x7907,x","I2CSAR");
GEL_WatchAdd("*0x7908,x","I2CDXR");
GEL_WatchAdd("*0x7909,x","I2CMDR");
GEL_WatchAdd("*0x790A,x","I2CISRC");
GEL_WatchAdd("*0x790C,x","I2CPSC");
GEL_WatchAdd("*0x7920,x","I2CFFTX");
GEL_WatchAdd("*0x7921,x","I2CFFRX");
}
/********************************************************************/
/* Peripheral Interrupt Expansion Registers */
/********************************************************************/
menuitem "Watch Peripheral Interrupt Expansion Registers";
hotmenu All_PIE_Regs()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
GEL_WatchAdd("*0x0CE1,x","PIEACK");
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
hotmenu PIECTRL()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
}
hotmenu PIEACK()
{
GEL_WatchAdd("*0x0CE1,x","PIEACK");
}
hotmenu PIEIER1_and_PIEIFR1()
{
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
}
hotmenu PIEIER2_and_PIEIFR2()
{
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
}
hotmenu PIEIER3_and_PIEIFR3()
{
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
}
hotmenu PIEIER4_and_PIEIFR4()
{
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
}
hotmenu PIEIER5_and_PIEIFR5()
{
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
}
hotmenu PIEIER6_and_PIEIFR6()
{
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
}
hotmenu PIEIER7_and_PIEIFR7()
{
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
}
hotmenu PIEIER8_and_PIEIFR8()
{
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
}
hotmenu PIEIER9_and_PIEIFR9()
{
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
}
hotmenu PIEIFR10_and_PIEIFR10()
{
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
}
hotmenu PIEIER11_and_PIEIFR11()
{
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
}
hotmenu PIEIER12_and_PIEIFR12()
{
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
/********************************************************************/
/* Serial Communication Interface Registers */
/********************************************************************/
menuitem "Watch SCI Registers";
hotmenu SCI_A_All_Regs()
{
GEL_WatchAdd("*0x7050,x","SCICCRA");
GEL_WatchAdd("*0x7051,x","SCICTL1A");
GEL_WatchAdd("*0x7052,x","SCIHBAUDA");
GEL_WatchAdd("*0x7053,x","SCILBAUDA");
GEL_WatchAdd("*0x7054,x","SCICTL2A");
GEL_WatchAdd("*0x7055,x","SCIRXSTA");
GEL_WatchAdd("*0x7056,x","SCIRXEMUA");
GEL_WatchAdd("*0x7057,x","SCIRXBUFA");
GEL_WatchAdd("*0x7059,x","SCITXBUFA");
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
GEL_WatchAdd("*0x705F,x","SCIPRIA");
}
hotmenu SCI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
}
hotmenu SCI_B_All_Regs()
{
GEL_WatchAdd("*0x7750,x","SCICCRB");
GEL_WatchAdd("*0x7751,x","SCICTL1B");
GEL_WatchAdd("*0x7752,x","SCIHBAUDB");
GEL_WatchAdd("*0x7753,x","SCILBAUDB");
GEL_WatchAdd("*0x7754,x","SCICTL2B");
GEL_WatchAdd("*0x7755,x","SCIRXSTB");
GEL_WatchAdd("*0x7756,x","SCIRXEMUB");
GEL_WatchAdd("*0x7757,x","SCIRXBUFB");
GEL_WatchAdd("*0x7759,x","SCITXBUFB");
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
GEL_WatchAdd("*0x775F,x","SCIPRIB");
}
hotmenu SCI_B_FIFO_Registers()
{
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
}
/********************************************************************/
/* Serial Peripheral Interface Registers */
/********************************************************************/
menuitem "Watch SPI Registers";
hotmenu SPI_A_All_Regs()
{
GEL_WatchAdd("*0x7040,x","SPIA SPICCR");
GEL_WatchAdd("*0x7041,x","SPIA SPICTL");
GEL_WatchAdd("*0x7042,x","SPIA SPIST");
GEL_WatchAdd("*0x7044,x","SPIA SPIBRR");
GEL_WatchAdd("*0x7046,x","SPIA SPIEMU");
GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF");
GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF");
GEL_WatchAdd("*0x7049,x","SPIA SPIDAT");
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
GEL_WatchAdd("*0x704F,x","SPIA SPIPRI");
}
hotmenu SPI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
}
/********************************************************************/
/* Watchdog Timer Registers */
/********************************************************************/
menuitem "Watch Watchdog Timer Registers";
hotmenu All_Watchdog_Regs()
{
GEL_WatchAdd("*0x7023,x","WDCNTR");
GEL_WatchAdd("*0x7025,x","WDKEY");
GEL_WatchAdd("*0x7029,x","WDCR");
GEL_WatchAdd("*0x7022,x","SCSR");
}
/********************************************************************/
/*** End of file ***/

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v120/DSP2833x_common/gel/f28234.gel Normal file
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@@ -0,0 +1,2930 @@
/********************************************************************/
/* f28234.gel */
/* Version 3.30.2 */
/* */
/* This GEL file is to be used with the TMS320F28234 DSP. */
/* Changes may be required to support specific hardware designs. */
/* */
/* Code Composer Studio supports six reserved GEL functions that */
/* automatically get executed if they are defined. They are: */
/* */
/* StartUp() - Executed whenever CCS is invoked */
/* OnReset() - Executed after Debug->Reset CPU */
/* OnRestart() - Executed after Debug->Restart */
/* OnPreFileLoaded() - Executed before File->Load Program */
/* OnFileLoaded() - Executed after File->Load Program */
/* OnTargetConnect() - Executed after Debug->Connect */
/* */
/********************************************************************/
StartUp()
{
/* The next line automatically loads the .gel file that comes */
/* with the DSP2833x Peripheral Header Files download. To use, */
/* uncomment, and adjust the directory path as needed. */
// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel");
}
OnReset(int nErrorCode)
{
C28x_Mode();
Unlock_CSM();
ADC_Cal();
}
OnRestart(int nErrorCode)
{
/* CCS will call OnRestart() when you do a Debug->Restart and */
/* after you load a new file. Between running interrupt based */
/* programs, this function will clear interrupts and help keep */
/* the processor from going off into invalid memory. */
C28x_Mode();
IER = 0;
IFR = 0;
ADC_Cal();
}
int TxtOutCtl=0;
OnPreFileLoaded()
{
XINTF_Enable();
if (TxtOutCtl==0)
{
GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use.");
TxtOutCtl=1;
}
}
OnFileLoaded(int nErrorCode, int bSymbolsOnly)
{
ADC_Cal();
}
OnTargetConnect()
{
C28x_Mode();
F28234_Memory_Map(); /* Initialize the CCS memory map */
/* Check to see if CCS has been started-up with the DSP already */
/* running in real-time mode. The user can add whatever */
/* custom initialization stuff they want to each case. */
if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */
{
}
else /* Do stop-mode target initialization */
{
GEL_Reset(); /* Reset DSP */
}
}
/********************************************************************/
/* These functions are launched by the GEL_Toolbar button plugin */
/********************************************************************/
GEL_Toolbar1()
{
Run_Realtime_with_Reset();
}
GEL_Toolbar2()
{
Run_Realtime_with_Restart();
}
GEL_Toolbar3()
{
Full_Halt();
}
GEL_Toolbar4()
{
Full_Halt_with_Reset();
}
int GEL_Toolbar5_Toggle = 0;
GEL_Toolbar5()
{
if(GEL_Toolbar5_Toggle == 0)
{
GEL_Toolbar5_Toggle = 1;
GEL_OpenWindow("GEL_Buttons",1,4);
GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0);
GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1);
GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2);
GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3);
}
else
{
GEL_Toolbar5_Toggle = 0;
GEL_CloseWindow("GEL_Buttons");
}
}
/********************************************************************/
/* These functions are useful to engage/dis-enagage realtime */
/* emulation mode during debug. They save the user from having to */
/* manually perform these steps in CCS. */
/********************************************************************/
menuitem "Realtime Emulation Control";
hotmenu Run_Realtime_with_Reset()
{
GEL_Reset(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Run_Realtime_with_Restart()
{
GEL_Restart(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Full_Halt()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
}
hotmenu Full_Halt_with_Reset()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
GEL_Reset(); /* Reset the DSP */
}
/********************************************************************/
/* F28234 Memory Map */
/* */
/* Note: M0M1MAP and VMAP signals tied high on F28234 core */
/* */
/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */
/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */
/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */
/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */
/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */
/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */
/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */
/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */
/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */
/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */
/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */
/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */
/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */
/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */
/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */
/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */
/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */
/* 0x320000 - 0x33ffff Flash (Prog and Data) */
/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */
/* 0x380090 - 0x380090 PARTID value (Prog and Data) */
/* 0x380400 - 0x3807ff OTP (Prog and Data) */
/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */
/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */
/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */
/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */
/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */
/********************************************************************/
menuitem "Initialize Memory Map";
hotmenu F28234_Memory_Map()
{
GEL_MapReset();
GEL_MapOn();
/* Program memory map */
GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */
GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */
GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x320000,0,0x20000,1,0); /* FLASH */
GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */
GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */
/* Data memory map */
GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */
GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */
GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */
GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */
GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */
GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */
GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x320000,1,0x20000,1,0); /* FLASH */
GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */
GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */
}
/********************************************************************/
/* The ESTOP0 fill functions are useful for debug. They fill the */
/* RAM with software breakpoints that will trap runaway code. */
/********************************************************************/
hotmenu Fill_F28234_RAM_with_ESTOP0()
{
GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */
GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */
GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */
GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */
GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */
}
/********************************************************************/
menuitem "Watchdog";
hotmenu Disable_WD()
{
*0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */
*0x7025 = 0x0055; /* Service the WD */
*0x7025 = 0x00AA; /* once to be safe. */
GEL_TextOut("\nWatchdog Timer Disabled");
}
/********************************************************************/
menuitem "Code Security Module"
hotmenu Unlock_CSM()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
/* Write passwords to the KEY registers. 0xFFFF's are dummy passwords.
User should replace them with the correct password for their DSP */
*0xAE0 = 0xFFFF;
*0xAE1 = 0xFFFF;
*0xAE2 = 0xFFFF;
*0xAE3 = 0xFFFF;
*0xAE4 = 0xFFFF;
*0xAE5 = 0xFFFF;
*0xAE6 = 0xFFFF;
*0xAE7 = 0xFFFF;
}
/********************************************************************/
menuitem "Addressing Modes";
hotmenu C28x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C24x_Mode()
{
ST1 = ST1 | 0x0100; /* AMODE = 1 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C27x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */
}
/********************************************************************/
/* PLL Ratios */
/* */
/* The following table describes the PLL clocking ratios (0..10) */
/* */
/* Ratio CLKIN Description */
/* ----- -------------- ------------ */
/* 0 OSCCLK/2 PLL bypassed */
/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */
/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */
/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */
/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */
/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */
/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */
/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */
/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */
/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */
/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */
/********************************************************************/
menuitem "Set PLL Ratio";
hotmenu Bypass()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */
PLL_Wait();
}
hotmenu OSCCLK_x1_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x2_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x3_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x4_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x5_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x6_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x7_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x8_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x9_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x10_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */
PLL_Wait();
}
// hotmenu OSCCLK_x1_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x2_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x3_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x4_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x5_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x6_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x7_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x8_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x9_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x10_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */
// PLL_Wait();
// }
/********************************************************************/
/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */
/********************************************************************/
DIVSEL_div2()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
temp = *PLLSTS;
temp &= 0xFE7F; /* Clear bits 7 & 8 */
temp |= 2 << 7; /* Set bit 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
/********************************************************************/
/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to /1 */
/********************************************************************/
DIVSEL_div1()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */
wait();
temp = *PLLSTS;
temp |= 3 << 7; /* Set bits 7 & 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
wait()
{
int delay = 0;
for (delay = 0; delay <= 5; delay ++)
{}
}
/********************************************************************/
/* For F2823x devices, check the PLLOCKS bit for PLL lock. */
/********************************************************************/
PLL_Wait()
{
int PLLSTS;
int delay = 0;
PLLSTS = 0x7011;
while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001)
{
delay++;
GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
/********************************************************************/
/* Load the ADC Calibration values from TI OTP */
/********************************************************************/
menuitem "ADC Calibration"
hotmenu ADC_Cal()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
if(((*0x0AEF) & 0x0001) == 0)
{
XAR0 = *0x701C;
*0x701C |= 0x0008;
*0x711C = *0x380083;
*0x711D = *0x380085;
*0x701C = XAR0;
XAR0 = 0;
}
else
{
GEL_TextOut("\nADC Calibration not complete, device is secure");
}
}
/********************************************************************/
/* Enable the XINTF and configure GPIOs for XINTF function */
/********************************************************************/
menuitem "XINTF Enable"
hotmenu XINTF_Enable()
{
/* enable XINTF clock (XTIMCLK) */
*0x7020 = 0x3700;
/* GPBMUX1: XA0-XA7, XA16, XZCS0, */
/* XZCS7, XREADY, XRNW, XWE0 */
/* GPAMUX2: XA17-XA19, XZCS6 */
/* GPCMUX2: XA8-XA15 */
/* GPCMUX1: XD0-XD15 */
*(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */
*(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */
*(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */
*(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */
/* Uncomment for x32 data bus */
/* GPBMUX2: XD16-XD31 */
// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */
/* Zone timing.
/* Each zone can be configured seperately */
/* Uncomment the x16 or the x32 timing */
/* depending on the data bus width for */
/* the zone */
/* x16 Timing */
*(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */
*(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */
*(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */
/* x32 Timing:
// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */
}
/********************************************************************/
/* The below are used to display the symbolic names of the F28234 */
/* memory mapped registers in the watch window. To view these */
/* registers, click on the GEL menu button in Code Composer Studio, */
/* then select which registers or groups of registers you want to */
/* view. They will appear in the watch window under the Watch1 tab. */
/********************************************************************/
/* Add a space line to the GEL menu */
menuitem "______________________________________";
hotmenu __() {}
/********************************************************************/
/* A/D Converter Registers */
/********************************************************************/
menuitem "Watch ADC Registers";
hotmenu All_ADC_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
hotmenu ADC_Control_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
}
hotmenu ADCCHSELSEQx_Regs()
{
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
}
hotmenu ADCRESULT_0_to_7()
{
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
}
hotmenu ADCRESULT_8_to_15()
{
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
}
hotmenu ADCRESULT_Mirror_0_to_7()
{
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
}
hotmenu ADCRESULT_Mirror_8_to_15()
{
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
/********************************************************************/
/* Clocking and Low-Power Registers */
/********************************************************************/
menuitem "Watch Clocking and Low-Power Registers";
hotmenu All_Clocking_and_Low_Power_Regs()
{
GEL_WatchAdd("*0x7010,x","XCLK");
GEL_WatchAdd("*0x7011,x","PLLSTS");
GEL_WatchAdd("*0x701A,x","HISPCP");
GEL_WatchAdd("*0x701B,x","LOSPCP");
GEL_WatchAdd("*0x701C,x","PCLKCR0");
GEL_WatchAdd("*0x701D,x","PCLKCR1");
GEL_WatchAdd("*0x701E,x","LPMCR0");
GEL_WatchAdd("*0x7020,x","PCLKCR3");
GEL_WatchAdd("*0x7021,x","PLLCR");
}
/********************************************************************/
/* Code Security Module Registers */
/********************************************************************/
menuitem "Watch Code Security Module Registers";
hotmenu CSMSCR()
{
GEL_WatchAdd("*0x0AEF,x","CSMSCR");
GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit");
GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit");
}
hotmenu PWL_Locations()
{
GEL_WatchAdd("*0x33FFF8,x","PWL0");
GEL_WatchAdd("*0x33FFF9,x","PWL1");
GEL_WatchAdd("*0x33FFFA,x","PWL2");
GEL_WatchAdd("*0x33FFFB,x","PWL3");
GEL_WatchAdd("*0x33FFFC,x","PWL4");
GEL_WatchAdd("*0x33FFFD,x","PWL5");
GEL_WatchAdd("*0x33FFFE,x","PWL6");
GEL_WatchAdd("*0x33FFFF,x","PWL7");
}
/********************************************************************/
/* CPU Timer Registers */
/********************************************************************/
menuitem "Watch CPU Timer Registers";
hotmenu All_CPU_Timer0_Regs()
{
GEL_WatchAdd("*0x0C00,x","TIMER0TIM");
GEL_WatchAdd("*0x0C01,x","TIMER0TIMH");
GEL_WatchAdd("*0x0C02,x","TIMER0PRD");
GEL_WatchAdd("*0x0C03,x","TIMER0PRDH");
GEL_WatchAdd("*0x0C04,x","TIMER0TCR");
GEL_WatchAdd("*0x0C06,x","TIMER0TPR");
GEL_WatchAdd("*0x0C07,x","TIMER0TPRH");
}
hotmenu All_CPU_Timer1_Regs()
{
GEL_WatchAdd("*0x0C08,x","TIMER1TIM");
GEL_WatchAdd("*0x0C09,x","TIMER1TIMH");
GEL_WatchAdd("*0x0C0A,x","TIMER1PRD");
GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH");
GEL_WatchAdd("*0x0C0C,x","TIMER1TCR");
GEL_WatchAdd("*0x0C0E,x","TIMER1TPR");
GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH");
}
hotmenu All_CPU_Timer2_Regs()
{
GEL_WatchAdd("*0x0C10,x","TIMER2TIM");
GEL_WatchAdd("*0x0C11,x","TIMER2TIMH");
GEL_WatchAdd("*0x0C12,x","TIMER2PRD");
GEL_WatchAdd("*0x0C13,x","TIMER2PRDH");
GEL_WatchAdd("*0x0C14,x","TIMER2TCR");
GEL_WatchAdd("*0x0C16,x","TIMER2TPR");
GEL_WatchAdd("*0x0C17,x","TIMER2TPRH");
}
/********************************************************************/
/* Device Emulation Registers */
/********************************************************************/
menuitem "Watch Device Emulation Registers";
hotmenu All_Emulation_Regs()
{
GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF");
GEL_WatchAdd("*0x0882,x","CLASSID");
GEL_WatchAdd("*0x0883,x","REVID");
GEL_WatchAdd("*0x0884,x","PROTSTART");
GEL_WatchAdd("*0x0885,x","PROTRANGE");
GEL_WatchAdd("*0x380090,x","PARTID");
}
/********************************************************************/
/* DMA Registers */
/********************************************************************/
menuitem "Watch DMA Registers";
hotmenu All_DMA_Regs()
{
GEL_WatchAdd("*0x1000,x","DMACTRL");
GEL_WatchAdd("*0x1001,x","DEBUGCTRL");
GEL_WatchAdd("*0x1002,x","REVISION");
GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1");
GEL_WatchAdd("*0x1006,x","PRIORITYSTAT");
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_1_regs()
{
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_2_regs()
{
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_3_regs()
{
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_4_regs()
{
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_5_regs()
{
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_6_regs()
{
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
/********************************************************************/
/* eCAN Registers */
/********************************************************************/
menuitem "Watch eCAN Registers";
hotmenu eCAN_A_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME");
GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD");
GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS");
GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR");
GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA");
GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA");
GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP");
GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML");
GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP");
GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC");
GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC");
GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES");
GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC");
GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC");
GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0");
GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM");
GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1");
GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM");
GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL");
GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC");
GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC");
GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC");
GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT");
GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC");
GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS");
}
hotmenu eCAN_A_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0");
GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0");
GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0");
GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0");
GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0");
GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0");
GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0");
GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1");
GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1");
GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1");
GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1");
GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1");
GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1");
GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1");
}
hotmenu eCAN_A_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2");
GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2");
GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2");
GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2");
GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2");
GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2");
GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2");
GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3");
GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3");
GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3");
GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3");
GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3");
GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3");
GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3");
}
hotmenu eCAN_A_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4");
GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4");
GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4");
GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4");
GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4");
GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4");
GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4");
GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5");
GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5");
GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5");
GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5");
GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5");
GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5");
GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5");
}
hotmenu eCAN_A_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6");
GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6");
GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6");
GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6");
GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6");
GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6");
GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6");
GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7");
GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7");
GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7");
GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7");
GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7");
GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7");
GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7");
}
hotmenu eCAN_A_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8");
GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8");
GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8");
GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8");
GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8");
GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8");
GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8");
GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9");
GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9");
GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9");
GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9");
GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9");
GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9");
GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9");
}
hotmenu eCAN_A_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10");
GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10");
GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10");
GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10");
GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10");
GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10");
GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10");
GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11");
GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11");
GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11");
GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11");
GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11");
GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11");
GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11");
}
hotmenu eCAN_A_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12");
GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12");
GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12");
GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12");
GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12");
GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12");
GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12");
GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13");
GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13");
GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13");
GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13");
GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13");
GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13");
GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13");
}
hotmenu eCAN_A_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14");
GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14");
GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14");
GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14");
GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14");
GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14");
GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14");
GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15");
GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15");
GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15");
GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15");
GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15");
GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15");
GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15");
}
hotmenu eCAN_A_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16");
GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16");
GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16");
GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16");
GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16");
GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16");
GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16");
GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17");
GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17");
GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17");
GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17");
GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17");
GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17");
GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17");
}
hotmenu eCAN_A_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18");
GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18");
GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18");
GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18");
GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18");
GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18");
GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18");
GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19");
GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19");
GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19");
GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19");
GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19");
GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19");
GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19");
}
hotmenu eCAN_A_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20");
GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20");
GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20");
GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20");
GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20");
GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20");
GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20");
GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21");
GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21");
GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21");
GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21");
GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21");
GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21");
GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21");
}
hotmenu eCAN_A_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22");
GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22");
GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22");
GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22");
GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22");
GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22");
GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22");
GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23");
GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23");
GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23");
GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23");
GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23");
GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23");
GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23");
}
hotmenu eCAN_A_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24");
GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24");
GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24");
GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24");
GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24");
GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24");
GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24");
GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25");
GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25");
GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25");
GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25");
GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25");
GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25");
GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25");
}
hotmenu eCAN_A_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26");
GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26");
GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26");
GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26");
GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26");
GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26");
GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26");
GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27");
GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27");
GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27");
GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27");
GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27");
GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27");
GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27");
}
hotmenu eCAN_A_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28");
GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28");
GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28");
GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28");
GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28");
GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28");
GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28");
GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29");
GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29");
GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29");
GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29");
GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29");
GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29");
GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29");
}
hotmenu eCAN_A_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30");
GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30");
GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30");
GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30");
GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30");
GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30");
GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30");
GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31");
GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31");
GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31");
GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31");
GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31");
GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31");
GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31");
}
hotmenu eCAN_B_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME");
GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD");
GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS");
GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR");
GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA");
GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA");
GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP");
GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML");
GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP");
GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC");
GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC");
GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES");
GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC");
GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC");
GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0");
GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM");
GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1");
GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM");
GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL");
GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC");
GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC");
GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC");
GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT");
GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC");
GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS");
}
hotmenu eCAN_B_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0");
GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0");
GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0");
GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0");
GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0");
GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0");
GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0");
GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1");
GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1");
GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1");
GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1");
GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1");
GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1");
GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1");
}
hotmenu eCAN_B_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2");
GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2");
GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2");
GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2");
GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2");
GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2");
GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2");
GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3");
GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3");
GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3");
GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3");
GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3");
GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3");
GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3");
}
hotmenu eCAN_B_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4");
GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4");
GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4");
GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4");
GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4");
GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4");
GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4");
GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5");
GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5");
GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5");
GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5");
GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5");
GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5");
GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5");
}
hotmenu eCAN_B_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6");
GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6");
GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6");
GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6");
GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6");
GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6");
GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6");
GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7");
GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7");
GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7");
GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7");
GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7");
GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7");
GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7");
}
hotmenu eCAN_B_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8");
GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8");
GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8");
GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8");
GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8");
GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8");
GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8");
GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9");
GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9");
GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9");
GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9");
GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9");
GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9");
GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9");
}
hotmenu eCAN_B_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10");
GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10");
GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10");
GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10");
GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10");
GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10");
GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10");
GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11");
GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11");
GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11");
GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11");
GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11");
GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11");
GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11");
}
hotmenu eCAN_B_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12");
GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12");
GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12");
GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12");
GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12");
GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12");
GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12");
GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13");
GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13");
GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13");
GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13");
GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13");
GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13");
GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13");
}
hotmenu eCAN_B_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14");
GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14");
GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14");
GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14");
GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14");
GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14");
GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14");
GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15");
GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15");
GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15");
GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15");
GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15");
GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15");
GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15");
}
hotmenu eCAN_B_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16");
GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16");
GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16");
GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16");
GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16");
GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16");
GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16");
GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17");
GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17");
GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17");
GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17");
GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17");
GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17");
GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17");
}
hotmenu eCAN_B_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18");
GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18");
GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18");
GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18");
GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18");
GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18");
GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18");
GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19");
GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19");
GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19");
GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19");
GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19");
GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19");
GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19");
}
hotmenu eCAN_B_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20");
GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20");
GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20");
GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20");
GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20");
GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20");
GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20");
GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21");
GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21");
GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21");
GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21");
GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21");
GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21");
GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21");
}
hotmenu eCAN_B_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22");
GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22");
GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22");
GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22");
GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22");
GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22");
GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22");
GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23");
GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23");
GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23");
GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23");
GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23");
GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23");
GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23");
}
hotmenu eCAN_B_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24");
GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24");
GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24");
GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24");
GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24");
GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24");
GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24");
GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25");
GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25");
GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25");
GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25");
GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25");
GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25");
GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25");
}
hotmenu eCAN_B_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26");
GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26");
GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26");
GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26");
GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26");
GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26");
GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26");
GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27");
GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27");
GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27");
GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27");
GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27");
GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27");
GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27");
}
hotmenu eCAN_B_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28");
GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28");
GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28");
GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28");
GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28");
GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28");
GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28");
GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29");
GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29");
GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29");
GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29");
GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29");
GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29");
GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29");
}
hotmenu eCAN_B_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30");
GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30");
GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30");
GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30");
GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30");
GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30");
GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30");
GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31");
GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31");
GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31");
GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31");
GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31");
GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31");
GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31");
}
/********************************************************************/
/* Enhanced Capture Registers */
/********************************************************************/
menuitem "Watch eCAP Registers";
hotmenu eCAP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT");
GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS");
GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1");
GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2");
GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3");
GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4");
GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1");
GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2");
GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT");
GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG");
GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR");
GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC");
}
hotmenu eCAP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT");
GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS");
GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1");
GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2");
GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3");
GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4");
GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1");
GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2");
GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT");
GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG");
GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR");
GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC");
}
hotmenu eCAP3_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT");
GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS");
GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1");
GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2");
GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3");
GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4");
GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1");
GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2");
GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT");
GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG");
GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR");
GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC");
}
hotmenu eCAP4_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT");
GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS");
GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1");
GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2");
GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3");
GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4");
GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1");
GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2");
GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT");
GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG");
GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR");
GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC");
}
hotmenu eCAP5_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT");
GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS");
GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1");
GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2");
GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3");
GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4");
GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1");
GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2");
GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT");
GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG");
GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR");
GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC");
}
hotmenu eCAP6_All_Regs()
{
GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT");
GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS");
GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1");
GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2");
GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3");
GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4");
GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1");
GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2");
GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT");
GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG");
GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR");
GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC");
}
/********************************************************************/
/* Enhanced PWM Registers */
/********************************************************************/
menuitem "Watch ePWM Registers";
hotmenu ePWM1_All_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL");
GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG");
}
hotmenu ePWM1_TB_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
}
hotmenu ePWM1_CMP_Regs()
{
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
}
hotmenu ePWM1_AQ_Regs()
{
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
}
hotmenu ePWM1_DB_Regs()
{
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
}
hotmenu ePWM1_TZ_Regs()
{
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
}
hotmenu ePWM1_ET_Regs()
{
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
}
hotmenu ePWM2_All_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL");
GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG");
}
hotmenu ePWM2_TB_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
}
hotmenu ePWM2_CMP_Regs()
{
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
}
hotmenu ePWM2_AQ_Regs()
{
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
}
hotmenu ePWM2_DB_Regs()
{
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
}
hotmenu ePWM2_TZ_Regs()
{
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
}
hotmenu ePWM2_ET_Regs()
{
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
}
hotmenu ePWM3_All_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL");
GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG");
}
hotmenu ePWM3_TB_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
}
hotmenu ePWM3_CMP_Regs()
{
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
}
hotmenu ePWM3_AQ_Regs()
{
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
}
hotmenu ePWM3_DB_Regs()
{
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
}
hotmenu ePWM3_TZ_Regs()
{
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
}
hotmenu ePWM3_ET_Regs()
{
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
}
hotmenu ePWM4_All_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL");
GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG");
}
hotmenu ePWM4_TB_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
}
hotmenu ePWM4_CMP_Regs()
{
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
}
hotmenu ePWM4_AQ_Regs()
{
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
}
hotmenu ePWM4_DB_Regs()
{
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
}
hotmenu ePWM4_TZ_Regs()
{
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
}
hotmenu ePWM4_ET_Regs()
{
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
}
hotmenu ePWM5_All_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL");
GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG");
}
hotmenu ePWM5_TB_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
}
hotmenu ePWM5_CMP_Regs()
{
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
}
hotmenu ePWM5_AQ_Regs()
{
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
}
hotmenu ePWM5_DB_Regs()
{
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
}
hotmenu ePWM5_TZ_Regs()
{
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
}
hotmenu ePWM5_ET_Regs()
{
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
}
hotmenu ePWM6_All_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL");
GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG");
}
hotmenu ePWM6_TB_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
}
hotmenu ePWM6_CMP_Regs()
{
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
}
hotmenu ePWM6_AQ_Regs()
{
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
}
hotmenu ePWM6_DB_Regs()
{
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
}
hotmenu ePWM6_TZ_Regs()
{
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
}
hotmenu ePWM6_ET_Regs()
{
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
}
/********************************************************************/
/* Enhanced EQEP Registers */
/********************************************************************/
menuitem "Watch eQEP"
hotmenu eQEP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT");
GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR");
GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD");
GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR");
GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD");
GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL");
GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL");
GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL");
GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL");
GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT");
GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG");
GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR");
GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC");
GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS");
GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR");
GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD");
GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT");
GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT");
}
hotmenu eQEP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT");
GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR");
GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD");
GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR");
GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD");
GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL");
GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL");
GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL");
GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL");
GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT");
GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG");
GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR");
GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC");
GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS");
GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR");
GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD");
GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT");
GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT");
}
/********************************************************************/
/* External Interface Registers */
/********************************************************************/
menuitem "Watch External Interface Registers";
hotmenu All_External_Interface_Regs()
{
GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0");
GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6");
GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7");
GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2");
GEL_WatchAdd("*0x0B38,x","XBANK");
GEL_WatchAdd("*0x0B3A,x","XREVISION");
GEL_WatchAdd("*0x0B3D,x","XRESET");
}
/********************************************************************/
/* External Interrupt Registers */
/********************************************************************/
menuitem "Watch External Interrupt Registers";
hotmenu All_XINT_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
hotmenu XINT_Control_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
}
hotmenu XINT_Counter_Regs()
{
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
/********************************************************************/
/* GPIO Registers */
/********************************************************************/
menuitem "Watch GPIO Registers";
hotmenu All_GPIO_CONTROL_Regs()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
}
hotmenu All_GPIO_DATA_Regs()
{
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
hotmenu All_GPIO_INTERRUPT_Regs()
{
GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL");
GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL");
GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL");
GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL");
GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL");
GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL");
GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL");
GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL");
GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL");
}
hotmenu All_GPA_Registers()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
}
hotmenu All_GPB_Registers()
{
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
}
hotmenu All_GPC_Registers()
{
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
/********************************************************************/
/* Multichannel Serial Port Registers */
/********************************************************************/
menuitem "Watch McBSP Registers";
hotmenu All_McBSP_A_Regs()
{
GEL_WatchAdd("*0x5000,x","McBSPA DRR2");
GEL_WatchAdd("*0x5001,x","McBSPA DRR1");
GEL_WatchAdd("*0x5002,x","McBSPA DXR2");
GEL_WatchAdd("*0x5003,x","McBSPA DXR1");
GEL_WatchAdd("*0x5004,x","McBSPA SPCR2");
GEL_WatchAdd("*0x5005,x","McBSPA SPCR1");
GEL_WatchAdd("*0x5006,x","McBSPA RCR2");
GEL_WatchAdd("*0x5007,x","McBSPA RCR1");
GEL_WatchAdd("*0x5008,x","McBSPA XCR2");
GEL_WatchAdd("*0x5009,x","McBSPA XCR1");
GEL_WatchAdd("*0x500A,x","McBSPA SRGR2");
GEL_WatchAdd("*0x500B,x","McBSPA SRGR1");
GEL_WatchAdd("*0x500C,x","McBSPA MCR2");
GEL_WatchAdd("*0x500D,x","McBSPA MCR1");
GEL_WatchAdd("*0x500E,x","McBSPA RCERA");
GEL_WatchAdd("*0x500F,x","McBSPA RCERB");
GEL_WatchAdd("*0x5010,x","McBSPA XCERA");
GEL_WatchAdd("*0x5011,x","McBSPA XCERB");
GEL_WatchAdd("*0x5012,x","McBSPA PCR1");
GEL_WatchAdd("*0x5013,x","McBSPA RCERC");
GEL_WatchAdd("*0x5014,x","McBSPA RCERD");
GEL_WatchAdd("*0x5015,x","McBSPA XCERC");
GEL_WatchAdd("*0x5016,x","McBSPA XCERD");
GEL_WatchAdd("*0x5017,x","McBSPA RCERE");
GEL_WatchAdd("*0x5018,x","McBSPA RCERF");
GEL_WatchAdd("*0x5019,x","McBSPA XCERE");
GEL_WatchAdd("*0x501A,x","McBSPA XCERF");
GEL_WatchAdd("*0x501B,x","McBSPA RCERG");
GEL_WatchAdd("*0x501C,x","McBSPA RCERH");
GEL_WatchAdd("*0x501D,x","McBSPA XCERG");
GEL_WatchAdd("*0x501E,x","McBSPA XCERH");
GEL_WatchAdd("*0x5023,x","McBSPA MFFINT");
GEL_WatchAdd("*0x503F,x","McBSPA Revision");
}
hotmenu All_McBSP_B_Regs()
{
GEL_WatchAdd("*0x5040,x","McBSPB DRR2");
GEL_WatchAdd("*0x5041,x","McBSPB DRR1");
GEL_WatchAdd("*0x5042,x","McBSPB DXR2");
GEL_WatchAdd("*0x5043,x","McBSPB DXR1");
GEL_WatchAdd("*0x5044,x","McBSPB SPCR2");
GEL_WatchAdd("*0x5045,x","McBSPB SPCR1");
GEL_WatchAdd("*0x5046,x","McBSPB RCR2");
GEL_WatchAdd("*0x5047,x","McBSPB RCR1");
GEL_WatchAdd("*0x5048,x","McBSPB XCR2");
GEL_WatchAdd("*0x5049,x","McBSPB XCR1");
GEL_WatchAdd("*0x504A,x","McBSPB SRGR2");
GEL_WatchAdd("*0x504B,x","McBSPB SRGR1");
GEL_WatchAdd("*0x504C,x","McBSPB MCR2");
GEL_WatchAdd("*0x504D,x","McBSPB MCR1");
GEL_WatchAdd("*0x504E,x","McBSPB RCERA");
GEL_WatchAdd("*0x504F,x","McBSPB RCERB");
GEL_WatchAdd("*0x5050,x","McBSPB XCERA");
GEL_WatchAdd("*0x5051,x","McBSPB XCERB");
GEL_WatchAdd("*0x5052,x","McBSPB PCR1");
GEL_WatchAdd("*0x5053,x","McBSPB RCERC");
GEL_WatchAdd("*0x5054,x","McBSPB RCERD");
GEL_WatchAdd("*0x5055,x","McBSPB XCERC");
GEL_WatchAdd("*0x5056,x","McBSPB XCERD");
GEL_WatchAdd("*0x5057,x","McBSPB RCERE");
GEL_WatchAdd("*0x5058,x","McBSPB RCERF");
GEL_WatchAdd("*0x5059,x","McBSPB XCERE");
GEL_WatchAdd("*0x505A,x","McBSPB XCERF");
GEL_WatchAdd("*0x505B,x","McBSPB RCERG");
GEL_WatchAdd("*0x505C,x","McBSPB RCERH");
GEL_WatchAdd("*0x505D,x","McBSPB XCERG");
GEL_WatchAdd("*0x505E,x","McBSPB XCERH");
GEL_WatchAdd("*0x5063,x","McBSPB MFFINT");
GEL_WatchAdd("*0x506F,x","McBSPB Revision");
}
/********************************************************************/
/* I2C Registers */
/********************************************************************/
menuitem "Watch I2C Registers";
hotmenu All_I2C_Regs()
{
GEL_WatchAdd("*0x7900,x","I2COAR");
GEL_WatchAdd("*0x7901,x","I2CIER");
GEL_WatchAdd("*0x7902,x","I2CSTR");
GEL_WatchAdd("*0x7903,x","I2CCLKL");
GEL_WatchAdd("*0x7904,x","I2CCLKH");
GEL_WatchAdd("*0x7905,x","I2CCNT");
GEL_WatchAdd("*0x7906,x","I2CDRR");
GEL_WatchAdd("*0x7907,x","I2CSAR");
GEL_WatchAdd("*0x7908,x","I2CDXR");
GEL_WatchAdd("*0x7909,x","I2CMDR");
GEL_WatchAdd("*0x790A,x","I2CISRC");
GEL_WatchAdd("*0x790C,x","I2CPSC");
GEL_WatchAdd("*0x7920,x","I2CFFTX");
GEL_WatchAdd("*0x7921,x","I2CFFRX");
}
/********************************************************************/
/* Peripheral Interrupt Expansion Registers */
/********************************************************************/
menuitem "Watch Peripheral Interrupt Expansion Registers";
hotmenu All_PIE_Regs()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
GEL_WatchAdd("*0x0CE1,x","PIEACK");
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
hotmenu PIECTRL()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
}
hotmenu PIEACK()
{
GEL_WatchAdd("*0x0CE1,x","PIEACK");
}
hotmenu PIEIER1_and_PIEIFR1()
{
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
}
hotmenu PIEIER2_and_PIEIFR2()
{
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
}
hotmenu PIEIER3_and_PIEIFR3()
{
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
}
hotmenu PIEIER4_and_PIEIFR4()
{
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
}
hotmenu PIEIER5_and_PIEIFR5()
{
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
}
hotmenu PIEIER6_and_PIEIFR6()
{
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
}
hotmenu PIEIER7_and_PIEIFR7()
{
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
}
hotmenu PIEIER8_and_PIEIFR8()
{
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
}
hotmenu PIEIER9_and_PIEIFR9()
{
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
}
hotmenu PIEIFR10_and_PIEIFR10()
{
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
}
hotmenu PIEIER11_and_PIEIFR11()
{
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
}
hotmenu PIEIER12_and_PIEIFR12()
{
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
/********************************************************************/
/* Serial Communication Interface Registers */
/********************************************************************/
menuitem "Watch SCI Registers";
hotmenu SCI_A_All_Regs()
{
GEL_WatchAdd("*0x7050,x","SCICCRA");
GEL_WatchAdd("*0x7051,x","SCICTL1A");
GEL_WatchAdd("*0x7052,x","SCIHBAUDA");
GEL_WatchAdd("*0x7053,x","SCILBAUDA");
GEL_WatchAdd("*0x7054,x","SCICTL2A");
GEL_WatchAdd("*0x7055,x","SCIRXSTA");
GEL_WatchAdd("*0x7056,x","SCIRXEMUA");
GEL_WatchAdd("*0x7057,x","SCIRXBUFA");
GEL_WatchAdd("*0x7059,x","SCITXBUFA");
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
GEL_WatchAdd("*0x705F,x","SCIPRIA");
}
hotmenu SCI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
}
hotmenu SCI_B_All_Regs()
{
GEL_WatchAdd("*0x7750,x","SCICCRB");
GEL_WatchAdd("*0x7751,x","SCICTL1B");
GEL_WatchAdd("*0x7752,x","SCIHBAUDB");
GEL_WatchAdd("*0x7753,x","SCILBAUDB");
GEL_WatchAdd("*0x7754,x","SCICTL2B");
GEL_WatchAdd("*0x7755,x","SCIRXSTB");
GEL_WatchAdd("*0x7756,x","SCIRXEMUB");
GEL_WatchAdd("*0x7757,x","SCIRXBUFB");
GEL_WatchAdd("*0x7759,x","SCITXBUFB");
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
GEL_WatchAdd("*0x775F,x","SCIPRIB");
}
hotmenu SCI_B_FIFO_Registers()
{
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
}
hotmenu SCI_C_All_Regs()
{
GEL_WatchAdd("*0x7770,x","SCICCRC");
GEL_WatchAdd("*0x7771,x","SCICTL1C");
GEL_WatchAdd("*0x7772,x","SCIHBAUDC");
GEL_WatchAdd("*0x7773,x","SCILBAUDC");
GEL_WatchAdd("*0x7774,x","SCICTL2C");
GEL_WatchAdd("*0x7775,x","SCIRXSTC");
GEL_WatchAdd("*0x7776,x","SCIRXEMUC");
GEL_WatchAdd("*0x7777,x","SCIRXBUFC");
GEL_WatchAdd("*0x7779,x","SCITXBUFC");
GEL_WatchAdd("*0x777A,x","SCIFFTXC");
GEL_WatchAdd("*0x777B,x","SCIFFRXC");
GEL_WatchAdd("*0x777C,x","SCIFFCTC");
GEL_WatchAdd("*0x777F,x","SCIPRIC");
}
hotmenu SCI_C_FIFO_Registers()
{
GEL_WatchAdd("*0x777A,x","SCIFFTXC");
GEL_WatchAdd("*0x777B,x","SCIFFRXC");
GEL_WatchAdd("*0x777C,x","SCIFFCTC");
}
/********************************************************************/
/* Serial Peripheral Interface Registers */
/********************************************************************/
menuitem "Watch SPI Registers";
hotmenu SPI_A_All_Regs()
{
GEL_WatchAdd("*0x7040,x","SPIA SPICCR");
GEL_WatchAdd("*0x7041,x","SPIA SPICTL");
GEL_WatchAdd("*0x7042,x","SPIA SPIST");
GEL_WatchAdd("*0x7044,x","SPIA SPIBRR");
GEL_WatchAdd("*0x7046,x","SPIA SPIEMU");
GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF");
GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF");
GEL_WatchAdd("*0x7049,x","SPIA SPIDAT");
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
GEL_WatchAdd("*0x704F,x","SPIA SPIPRI");
}
hotmenu SPI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
}
/********************************************************************/
/* Watchdog Timer Registers */
/********************************************************************/
menuitem "Watch Watchdog Timer Registers";
hotmenu All_Watchdog_Regs()
{
GEL_WatchAdd("*0x7023,x","WDCNTR");
GEL_WatchAdd("*0x7025,x","WDKEY");
GEL_WatchAdd("*0x7029,x","WDCR");
GEL_WatchAdd("*0x7022,x","SCSR");
}
/********************************************************************/
/*** End of file ***/

2939
v120/DSP2833x_common/gel/f28235.gel Normal file
View File

@@ -0,0 +1,2939 @@
/********************************************************************/
/* f28235.gel */
/* Version 3.30.2 */
/* */
/* This GEL file is to be used with the TMS320F28235 DSP. */
/* Changes may be required to support specific hardware designs. */
/* */
/* Code Composer Studio supports six reserved GEL functions that */
/* automatically get executed if they are defined. They are: */
/* */
/* StartUp() - Executed whenever CCS is invoked */
/* OnReset() - Executed after Debug->Reset CPU */
/* OnRestart() - Executed after Debug->Restart */
/* OnPreFileLoaded() - Executed before File->Load Program */
/* OnFileLoaded() - Executed after File->Load Program */
/* OnTargetConnect() - Executed after Debug->Connect */
/* */
/********************************************************************/
StartUp()
{
/* The next line automatically loads the .gel file that comes */
/* with the DSP2833x Peripheral Header Files download. To use, */
/* uncomment, and adjust the directory path as needed. */
// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel");
}
OnReset(int nErrorCode)
{
C28x_Mode();
Unlock_CSM();
ADC_Cal();
}
OnRestart(int nErrorCode)
{
/* CCS will call OnRestart() when you do a Debug->Restart and */
/* after you load a new file. Between running interrupt based */
/* programs, this function will clear interrupts and help keep */
/* the processor from going off into invalid memory. */
C28x_Mode();
IER = 0;
IFR = 0;
ADC_Cal();
}
int TxtOutCtl=0;
OnPreFileLoaded()
{
XINTF_Enable();
if (TxtOutCtl==0)
{
GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use.");
TxtOutCtl=1;
}
}
OnFileLoaded(int nErrorCode, int bSymbolsOnly)
{
ADC_Cal();
}
OnTargetConnect()
{
C28x_Mode();
F28235_Memory_Map(); /* Initialize the CCS memory map */
/* Check to see if CCS has been started-up with the DSP already */
/* running in real-time mode. The user can add whatever */
/* custom initialization stuff they want to each case. */
if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */
{
}
else /* Do stop-mode target initialization */
{
GEL_Reset(); /* Reset DSP */
}
}
/********************************************************************/
/* These functions are launched by the GEL_Toolbar button plugin */
/********************************************************************/
GEL_Toolbar1()
{
Run_Realtime_with_Reset();
}
GEL_Toolbar2()
{
Run_Realtime_with_Restart();
}
GEL_Toolbar3()
{
Full_Halt();
}
GEL_Toolbar4()
{
Full_Halt_with_Reset();
}
int GEL_Toolbar5_Toggle = 0;
GEL_Toolbar5()
{
if(GEL_Toolbar5_Toggle == 0)
{
GEL_Toolbar5_Toggle = 1;
GEL_OpenWindow("GEL_Buttons",1,4);
GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0);
GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1);
GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2);
GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3);
}
else
{
GEL_Toolbar5_Toggle = 0;
GEL_CloseWindow("GEL_Buttons");
}
}
/********************************************************************/
/* These functions are useful to engage/dis-enagage realtime */
/* emulation mode during debug. They save the user from having to */
/* manually perform these steps in CCS. */
/********************************************************************/
menuitem "Realtime Emulation Control";
hotmenu Run_Realtime_with_Reset()
{
GEL_Reset(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Run_Realtime_with_Restart()
{
GEL_Restart(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Full_Halt()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
}
hotmenu Full_Halt_with_Reset()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
GEL_Reset(); /* Reset the DSP */
}
/********************************************************************/
/* F28235 Memory Map */
/* */
/* Note: M0M1MAP and VMAP signals tied high on F28235 core */
/* */
/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */
/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */
/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */
/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */
/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */
/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */
/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */
/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */
/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */
/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */
/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */
/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */
/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */
/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */
/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */
/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */
/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data */
/* 0x300000 - 0x33ffff Flash (Prog and Data) */
/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */
/* 0x380090 - 0x380090 PARTID value (Prog and Data) */
/* 0x380400 - 0x3807ff OTP (Prog and Data) */
/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */
/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */
/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */
/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */
/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */
/********************************************************************/
menuitem "Initialize Memory Map";
hotmenu F28235_Memory_Map()
{
GEL_MapReset();
GEL_MapOn();
/* Program memory map */
GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */
GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */
GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x300000,0,0x40000,1,0); /* FLASH */
GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */
GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */
/* Data memory map */
GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */
GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */
GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */
GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */
GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */
GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */
GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x300000,1,0x40000,1,0); /* FLASH */
GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */
GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */
}
/********************************************************************/
/* The ESTOP0 fill functions are useful for debug. They fill the */
/* RAM with software breakpoints that will trap runaway code. */
/********************************************************************/
hotmenu Fill_F28235_RAM_with_ESTOP0()
{
GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */
GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */
GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */
GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */
GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */
}
/********************************************************************/
menuitem "Watchdog";
hotmenu Disable_WD()
{
*0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */
*0x7025 = 0x0055; /* Service the WD */
*0x7025 = 0x00AA; /* once to be safe. */
GEL_TextOut("\nWatchdog Timer Disabled");
}
/********************************************************************/
menuitem "Code Security Module"
hotmenu Unlock_CSM()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
/* Write passwords to the KEY registers. 0xFFFF's are dummy passwords.
User should replace them with the correct password for their DSP */
*0xAE0 = 0xFFFF;
*0xAE1 = 0xFFFF;
*0xAE2 = 0xFFFF;
*0xAE3 = 0xFFFF;
*0xAE4 = 0xFFFF;
*0xAE5 = 0xFFFF;
*0xAE6 = 0xFFFF;
*0xAE7 = 0xFFFF;
}
/********************************************************************/
menuitem "Addressing Modes";
hotmenu C28x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C24x_Mode()
{
ST1 = ST1 | 0x0100; /* AMODE = 1 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C27x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */
}
/********************************************************************/
/* PLL Ratios */
/* */
/* The following table describes the PLL clocking ratios (0..10) */
/* */
/* Ratio CLKIN Description */
/* ----- -------------- ------------ */
/* 0 OSCCLK/2 PLL bypassed */
/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */
/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */
/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */
/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */
/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */
/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */
/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */
/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */
/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */
/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */
/********************************************************************/
menuitem "Set PLL Ratio";
hotmenu Bypass()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */
PLL_Wait();
}
hotmenu OSCCLK_x1_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x2_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x3_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x4_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x5_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x6_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x7_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x8_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x9_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x10_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */
PLL_Wait();
}
// hotmenu OSCCLK_x1_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x2_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x3_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x4_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x5_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x6_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x7_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x8_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x9_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x10_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */
// PLL_Wait();
// }
/********************************************************************/
/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */
/********************************************************************/
DIVSEL_div2()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
temp = *PLLSTS;
temp &= 0xFE7F; /* Clear bits 7 & 8 */
temp |= 2 << 7; /* Set bit 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
/********************************************************************/
/* For F2823x devices, DIVSEL is 1/4 by default. Switch it to /1 */
/********************************************************************/
DIVSEL_div1()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */
wait();
temp = *PLLSTS;
temp |= 3 << 7; /* Set bits 7 & 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
wait()
{
int delay = 0;
for (delay = 0; delay <= 5; delay ++)
{}
}
/********************************************************************/
/* For F2823x devices, check the PLLOCKS bit for PLL lock. */
/********************************************************************/
PLL_Wait()
{
int PLLSTS;
int delay = 0;
PLLSTS = 0x7011;
while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001)
{
delay++;
GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
/********************************************************************/
/* Load the ADC Calibration values from TI OTP */
/********************************************************************/
menuitem "ADC Calibration"
hotmenu ADC_Cal()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
if(((*0x0AEF) & 0x0001) == 0)
{
XAR0 = *0x701C;
*0x701C |= 0x0008;
*0x711C = *0x380083;
*0x711D = *0x380085;
*0x701C = XAR0;
XAR0 = 0;
}
else
{
GEL_TextOut("\nADC Calibration not complete, check if device is unlocked and recalibrate.");
}
}
/********************************************************************/
/* Enable the XINTF and configure GPIOs for XINTF function */
/********************************************************************/
menuitem "XINTF Enable"
hotmenu XINTF_Enable()
{
/* enable XINTF clock (XTIMCLK) */
*0x7020 = 0x3700;
/* GPBMUX1: XA0-XA7, XA16, XZCS0, */
/* XZCS7, XREADY, XRNW, XWE0 */
/* GPAMUX2: XA17-XA19, XZCS6 */
/* GPCMUX2: XA8-XA15 */
/* GPCMUX1: XD0-XD15 */
*(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */
*(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */
*(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */
*(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */
/* Uncomment for x32 data bus */
/* GPBMUX2: XD16-XD31 */
// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */
/* Zone timing.
/* Each zone can be configured seperately */
/* Uncomment the x16 or the x32 timing */
/* depending on the data bus width for */
/* the zone */
/* x16 Timing */
*(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */
*(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */
*(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */
/* x32 Timing:
// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */
}
/********************************************************************/
/* The below are used to display the symbolic names of the F28235 */
/* memory mapped registers in the watch window. To view these */
/* registers, click on the GEL menu button in Code Composer Studio, */
/* then select which registers or groups of registers you want to */
/* view. They will appear in the watch window under the Watch1 tab. */
/********************************************************************/
/* Add a space line to the GEL menu */
menuitem "______________________________________";
hotmenu __() {}
/********************************************************************/
/* A/D Converter Registers */
/********************************************************************/
menuitem "Watch ADC Registers";
hotmenu All_ADC_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
hotmenu ADC_Control_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
}
hotmenu ADCCHSELSEQx_Regs()
{
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
}
hotmenu ADCRESULT_0_to_7()
{
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
}
hotmenu ADCRESULT_8_to_15()
{
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
}
hotmenu ADCRESULT_Mirror_0_to_7()
{
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
}
hotmenu ADCRESULT_Mirror_8_to_15()
{
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
/********************************************************************/
/* Clocking and Low-Power Registers */
/********************************************************************/
menuitem "Watch Clocking and Low-Power Registers";
hotmenu All_Clocking_and_Low_Power_Regs()
{
GEL_WatchAdd("*0x7010,x","XCLK");
GEL_WatchAdd("*0x7011,x","PLLSTS");
GEL_WatchAdd("*0x701A,x","HISPCP");
GEL_WatchAdd("*0x701B,x","LOSPCP");
GEL_WatchAdd("*0x701C,x","PCLKCR0");
GEL_WatchAdd("*0x701D,x","PCLKCR1");
GEL_WatchAdd("*0x701E,x","LPMCR0");
GEL_WatchAdd("*0x7020,x","PCLKCR3");
GEL_WatchAdd("*0x7021,x","PLLCR");
}
/********************************************************************/
/* Code Security Module Registers */
/********************************************************************/
menuitem "Watch Code Security Module Registers";
hotmenu CSMSCR()
{
GEL_WatchAdd("*0x0AEF,x","CSMSCR");
GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit");
GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit");
}
hotmenu PWL_Locations()
{
GEL_WatchAdd("*0x33FFF8,x","PWL0");
GEL_WatchAdd("*0x33FFF9,x","PWL1");
GEL_WatchAdd("*0x33FFFA,x","PWL2");
GEL_WatchAdd("*0x33FFFB,x","PWL3");
GEL_WatchAdd("*0x33FFFC,x","PWL4");
GEL_WatchAdd("*0x33FFFD,x","PWL5");
GEL_WatchAdd("*0x33FFFE,x","PWL6");
GEL_WatchAdd("*0x33FFFF,x","PWL7");
}
/********************************************************************/
/* CPU Timer Registers */
/********************************************************************/
menuitem "Watch CPU Timer Registers";
hotmenu All_CPU_Timer0_Regs()
{
GEL_WatchAdd("*0x0C00,x","TIMER0TIM");
GEL_WatchAdd("*0x0C01,x","TIMER0TIMH");
GEL_WatchAdd("*0x0C02,x","TIMER0PRD");
GEL_WatchAdd("*0x0C03,x","TIMER0PRDH");
GEL_WatchAdd("*0x0C04,x","TIMER0TCR");
GEL_WatchAdd("*0x0C06,x","TIMER0TPR");
GEL_WatchAdd("*0x0C07,x","TIMER0TPRH");
}
hotmenu All_CPU_Timer1_Regs()
{
GEL_WatchAdd("*0x0C08,x","TIMER1TIM");
GEL_WatchAdd("*0x0C09,x","TIMER1TIMH");
GEL_WatchAdd("*0x0C0A,x","TIMER1PRD");
GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH");
GEL_WatchAdd("*0x0C0C,x","TIMER1TCR");
GEL_WatchAdd("*0x0C0E,x","TIMER1TPR");
GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH");
}
hotmenu All_CPU_Timer2_Regs()
{
GEL_WatchAdd("*0x0C10,x","TIMER2TIM");
GEL_WatchAdd("*0x0C11,x","TIMER2TIMH");
GEL_WatchAdd("*0x0C12,x","TIMER2PRD");
GEL_WatchAdd("*0x0C13,x","TIMER2PRDH");
GEL_WatchAdd("*0x0C14,x","TIMER2TCR");
GEL_WatchAdd("*0x0C16,x","TIMER2TPR");
GEL_WatchAdd("*0x0C17,x","TIMER2TPRH");
}
/********************************************************************/
/* Device Emulation Registers */
/********************************************************************/
menuitem "Watch Device Emulation Registers";
hotmenu All_Emulation_Regs()
{
GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF");
GEL_WatchAdd("*0x0882,x","CLASSID");
GEL_WatchAdd("*0x0883,x","REVID");
GEL_WatchAdd("*0x0884,x","PROTSTART");
GEL_WatchAdd("*0x0885,x","PROTRANGE");
GEL_WatchAdd("*0x380090,x","PARTID");
}
/********************************************************************/
/* DMA Registers */
/********************************************************************/
menuitem "Watch DMA Registers";
hotmenu All_DMA_Regs()
{
GEL_WatchAdd("*0x1000,x","DMACTRL");
GEL_WatchAdd("*0x1001,x","DEBUGCTRL");
GEL_WatchAdd("*0x1002,x","REVISION");
GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1");
GEL_WatchAdd("*0x1006,x","PRIORITYSTAT");
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_1_regs()
{
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_2_regs()
{
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_3_regs()
{
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_4_regs()
{
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_5_regs()
{
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_6_regs()
{
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
/********************************************************************/
/* eCAN Registers */
/********************************************************************/
menuitem "Watch eCAN Registers";
hotmenu eCAN_A_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME");
GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD");
GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS");
GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR");
GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA");
GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA");
GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP");
GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML");
GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP");
GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC");
GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC");
GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES");
GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC");
GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC");
GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0");
GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM");
GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1");
GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM");
GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL");
GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC");
GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC");
GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC");
GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT");
GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC");
GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS");
}
hotmenu eCAN_A_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0");
GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0");
GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0");
GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0");
GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0");
GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0");
GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0");
GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1");
GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1");
GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1");
GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1");
GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1");
GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1");
GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1");
}
hotmenu eCAN_A_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2");
GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2");
GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2");
GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2");
GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2");
GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2");
GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2");
GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3");
GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3");
GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3");
GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3");
GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3");
GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3");
GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3");
}
hotmenu eCAN_A_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4");
GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4");
GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4");
GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4");
GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4");
GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4");
GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4");
GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5");
GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5");
GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5");
GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5");
GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5");
GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5");
GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5");
}
hotmenu eCAN_A_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6");
GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6");
GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6");
GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6");
GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6");
GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6");
GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6");
GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7");
GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7");
GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7");
GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7");
GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7");
GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7");
GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7");
}
hotmenu eCAN_A_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8");
GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8");
GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8");
GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8");
GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8");
GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8");
GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8");
GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9");
GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9");
GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9");
GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9");
GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9");
GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9");
GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9");
}
hotmenu eCAN_A_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10");
GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10");
GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10");
GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10");
GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10");
GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10");
GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10");
GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11");
GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11");
GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11");
GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11");
GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11");
GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11");
GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11");
}
hotmenu eCAN_A_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12");
GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12");
GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12");
GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12");
GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12");
GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12");
GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12");
GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13");
GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13");
GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13");
GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13");
GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13");
GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13");
GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13");
}
hotmenu eCAN_A_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14");
GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14");
GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14");
GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14");
GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14");
GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14");
GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14");
GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15");
GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15");
GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15");
GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15");
GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15");
GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15");
GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15");
}
hotmenu eCAN_A_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16");
GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16");
GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16");
GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16");
GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16");
GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16");
GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16");
GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17");
GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17");
GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17");
GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17");
GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17");
GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17");
GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17");
}
hotmenu eCAN_A_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18");
GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18");
GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18");
GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18");
GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18");
GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18");
GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18");
GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19");
GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19");
GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19");
GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19");
GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19");
GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19");
GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19");
}
hotmenu eCAN_A_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20");
GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20");
GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20");
GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20");
GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20");
GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20");
GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20");
GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21");
GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21");
GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21");
GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21");
GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21");
GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21");
GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21");
}
hotmenu eCAN_A_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22");
GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22");
GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22");
GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22");
GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22");
GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22");
GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22");
GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23");
GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23");
GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23");
GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23");
GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23");
GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23");
GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23");
}
hotmenu eCAN_A_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24");
GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24");
GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24");
GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24");
GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24");
GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24");
GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24");
GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25");
GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25");
GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25");
GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25");
GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25");
GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25");
GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25");
}
hotmenu eCAN_A_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26");
GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26");
GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26");
GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26");
GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26");
GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26");
GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26");
GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27");
GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27");
GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27");
GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27");
GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27");
GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27");
GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27");
}
hotmenu eCAN_A_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28");
GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28");
GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28");
GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28");
GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28");
GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28");
GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28");
GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29");
GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29");
GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29");
GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29");
GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29");
GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29");
GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29");
}
hotmenu eCAN_A_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30");
GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30");
GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30");
GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30");
GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30");
GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30");
GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30");
GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31");
GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31");
GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31");
GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31");
GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31");
GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31");
GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31");
}
hotmenu eCAN_B_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME");
GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD");
GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS");
GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR");
GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA");
GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA");
GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP");
GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML");
GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP");
GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC");
GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC");
GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES");
GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC");
GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC");
GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0");
GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM");
GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1");
GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM");
GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL");
GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC");
GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC");
GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC");
GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT");
GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC");
GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS");
}
hotmenu eCAN_B_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0");
GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0");
GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0");
GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0");
GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0");
GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0");
GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0");
GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1");
GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1");
GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1");
GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1");
GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1");
GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1");
GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1");
}
hotmenu eCAN_B_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2");
GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2");
GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2");
GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2");
GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2");
GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2");
GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2");
GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3");
GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3");
GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3");
GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3");
GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3");
GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3");
GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3");
}
hotmenu eCAN_B_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4");
GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4");
GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4");
GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4");
GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4");
GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4");
GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4");
GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5");
GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5");
GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5");
GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5");
GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5");
GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5");
GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5");
}
hotmenu eCAN_B_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6");
GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6");
GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6");
GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6");
GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6");
GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6");
GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6");
GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7");
GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7");
GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7");
GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7");
GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7");
GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7");
GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7");
}
hotmenu eCAN_B_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8");
GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8");
GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8");
GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8");
GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8");
GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8");
GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8");
GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9");
GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9");
GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9");
GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9");
GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9");
GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9");
GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9");
}
hotmenu eCAN_B_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10");
GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10");
GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10");
GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10");
GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10");
GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10");
GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10");
GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11");
GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11");
GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11");
GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11");
GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11");
GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11");
GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11");
}
hotmenu eCAN_B_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12");
GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12");
GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12");
GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12");
GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12");
GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12");
GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12");
GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13");
GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13");
GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13");
GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13");
GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13");
GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13");
GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13");
}
hotmenu eCAN_B_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14");
GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14");
GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14");
GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14");
GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14");
GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14");
GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14");
GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15");
GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15");
GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15");
GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15");
GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15");
GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15");
GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15");
}
hotmenu eCAN_B_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16");
GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16");
GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16");
GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16");
GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16");
GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16");
GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16");
GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17");
GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17");
GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17");
GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17");
GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17");
GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17");
GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17");
}
hotmenu eCAN_B_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18");
GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18");
GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18");
GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18");
GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18");
GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18");
GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18");
GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19");
GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19");
GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19");
GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19");
GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19");
GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19");
GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19");
}
hotmenu eCAN_B_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20");
GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20");
GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20");
GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20");
GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20");
GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20");
GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20");
GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21");
GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21");
GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21");
GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21");
GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21");
GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21");
GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21");
}
hotmenu eCAN_B_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22");
GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22");
GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22");
GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22");
GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22");
GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22");
GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22");
GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23");
GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23");
GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23");
GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23");
GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23");
GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23");
GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23");
}
hotmenu eCAN_B_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24");
GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24");
GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24");
GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24");
GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24");
GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24");
GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24");
GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25");
GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25");
GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25");
GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25");
GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25");
GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25");
GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25");
}
hotmenu eCAN_B_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26");
GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26");
GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26");
GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26");
GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26");
GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26");
GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26");
GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27");
GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27");
GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27");
GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27");
GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27");
GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27");
GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27");
}
hotmenu eCAN_B_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28");
GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28");
GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28");
GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28");
GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28");
GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28");
GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28");
GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29");
GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29");
GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29");
GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29");
GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29");
GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29");
GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29");
}
hotmenu eCAN_B_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30");
GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30");
GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30");
GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30");
GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30");
GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30");
GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30");
GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31");
GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31");
GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31");
GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31");
GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31");
GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31");
GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31");
}
/********************************************************************/
/* Enhanced Capture Registers */
/********************************************************************/
menuitem "Watch eCAP Registers";
hotmenu eCAP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT");
GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS");
GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1");
GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2");
GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3");
GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4");
GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1");
GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2");
GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT");
GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG");
GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR");
GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC");
}
hotmenu eCAP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT");
GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS");
GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1");
GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2");
GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3");
GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4");
GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1");
GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2");
GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT");
GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG");
GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR");
GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC");
}
hotmenu eCAP3_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT");
GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS");
GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1");
GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2");
GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3");
GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4");
GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1");
GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2");
GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT");
GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG");
GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR");
GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC");
}
hotmenu eCAP4_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT");
GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS");
GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1");
GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2");
GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3");
GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4");
GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1");
GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2");
GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT");
GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG");
GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR");
GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC");
}
hotmenu eCAP5_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT");
GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS");
GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1");
GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2");
GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3");
GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4");
GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1");
GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2");
GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT");
GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG");
GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR");
GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC");
}
hotmenu eCAP6_All_Regs()
{
GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT");
GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS");
GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1");
GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2");
GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3");
GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4");
GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1");
GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2");
GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT");
GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG");
GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR");
GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC");
}
/********************************************************************/
/* Enhanced PWM Registers */
/********************************************************************/
menuitem "Watch ePWM Registers";
hotmenu ePWM1_All_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL");
GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG");
}
hotmenu ePWM1_TB_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
}
hotmenu ePWM1_CMP_Regs()
{
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
}
hotmenu ePWM1_AQ_Regs()
{
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
}
hotmenu ePWM1_DB_Regs()
{
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
}
hotmenu ePWM1_TZ_Regs()
{
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
}
hotmenu ePWM1_ET_Regs()
{
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
}
hotmenu ePWM2_All_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL");
GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG");
}
hotmenu ePWM2_TB_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
}
hotmenu ePWM2_CMP_Regs()
{
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
}
hotmenu ePWM2_AQ_Regs()
{
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
}
hotmenu ePWM2_DB_Regs()
{
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
}
hotmenu ePWM2_TZ_Regs()
{
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
}
hotmenu ePWM2_ET_Regs()
{
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
}
hotmenu ePWM3_All_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL");
GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG");
}
hotmenu ePWM3_TB_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
}
hotmenu ePWM3_CMP_Regs()
{
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
}
hotmenu ePWM3_AQ_Regs()
{
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
}
hotmenu ePWM3_DB_Regs()
{
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
}
hotmenu ePWM3_TZ_Regs()
{
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
}
hotmenu ePWM3_ET_Regs()
{
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
}
hotmenu ePWM4_All_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL");
GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG");
}
hotmenu ePWM4_TB_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
}
hotmenu ePWM4_CMP_Regs()
{
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
}
hotmenu ePWM4_AQ_Regs()
{
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
}
hotmenu ePWM4_DB_Regs()
{
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
}
hotmenu ePWM4_TZ_Regs()
{
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
}
hotmenu ePWM4_ET_Regs()
{
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
}
hotmenu ePWM5_All_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL");
GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG");
}
hotmenu ePWM5_TB_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
}
hotmenu ePWM5_CMP_Regs()
{
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
}
hotmenu ePWM5_AQ_Regs()
{
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
}
hotmenu ePWM5_DB_Regs()
{
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
}
hotmenu ePWM5_TZ_Regs()
{
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
}
hotmenu ePWM5_ET_Regs()
{
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
}
hotmenu ePWM6_All_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL");
GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG");
}
hotmenu ePWM6_TB_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
}
hotmenu ePWM6_CMP_Regs()
{
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
}
hotmenu ePWM6_AQ_Regs()
{
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
}
hotmenu ePWM6_DB_Regs()
{
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
}
hotmenu ePWM6_TZ_Regs()
{
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
}
hotmenu ePWM6_ET_Regs()
{
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
}
/********************************************************************/
/* Enhanced EQEP Registers */
/********************************************************************/
menuitem "Watch eQEP"
hotmenu eQEP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT");
GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR");
GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD");
GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR");
GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD");
GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL");
GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL");
GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL");
GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL");
GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT");
GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG");
GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR");
GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC");
GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS");
GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR");
GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD");
GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT");
GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT");
}
hotmenu eQEP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT");
GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR");
GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD");
GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR");
GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD");
GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL");
GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL");
GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL");
GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL");
GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT");
GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG");
GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR");
GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC");
GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS");
GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR");
GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD");
GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT");
GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT");
}
/********************************************************************/
/* External Interface Registers */
/********************************************************************/
menuitem "Watch External Interface Registers";
hotmenu All_External_Interface_Regs()
{
GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0");
GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6");
GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7");
GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2");
GEL_WatchAdd("*0x0B38,x","XBANK");
GEL_WatchAdd("*0x0B3A,x","XREVISION");
GEL_WatchAdd("*0x0B3D,x","XRESET");
}
/********************************************************************/
/* External Interrupt Registers */
/********************************************************************/
menuitem "Watch External Interrupt Registers";
hotmenu All_XINT_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
hotmenu XINT_Control_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
}
hotmenu XINT_Counter_Regs()
{
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
/********************************************************************/
/* GPIO Registers */
/********************************************************************/
menuitem "Watch GPIO Registers";
hotmenu All_GPIO_CONTROL_Regs()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
}
hotmenu All_GPIO_DATA_Regs()
{
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
hotmenu All_GPIO_INTERRUPT_Regs()
{
GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL");
GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL");
GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL");
GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL");
GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL");
GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL");
GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL");
GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL");
GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL");
}
hotmenu All_GPA_Registers()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
}
hotmenu All_GPB_Registers()
{
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
}
hotmenu All_GPC_Registers()
{
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
/********************************************************************/
/* Multichannel Serial Port Registers */
/********************************************************************/
menuitem "Watch McBSP Registers";
hotmenu All_McBSP_A_Regs()
{
GEL_WatchAdd("*0x5000,x","McBSPA DRR2");
GEL_WatchAdd("*0x5001,x","McBSPA DRR1");
GEL_WatchAdd("*0x5002,x","McBSPA DXR2");
GEL_WatchAdd("*0x5003,x","McBSPA DXR1");
GEL_WatchAdd("*0x5004,x","McBSPA SPCR2");
GEL_WatchAdd("*0x5005,x","McBSPA SPCR1");
GEL_WatchAdd("*0x5006,x","McBSPA RCR2");
GEL_WatchAdd("*0x5007,x","McBSPA RCR1");
GEL_WatchAdd("*0x5008,x","McBSPA XCR2");
GEL_WatchAdd("*0x5009,x","McBSPA XCR1");
GEL_WatchAdd("*0x500A,x","McBSPA SRGR2");
GEL_WatchAdd("*0x500B,x","McBSPA SRGR1");
GEL_WatchAdd("*0x500C,x","McBSPA MCR2");
GEL_WatchAdd("*0x500D,x","McBSPA MCR1");
GEL_WatchAdd("*0x500E,x","McBSPA RCERA");
GEL_WatchAdd("*0x500F,x","McBSPA RCERB");
GEL_WatchAdd("*0x5010,x","McBSPA XCERA");
GEL_WatchAdd("*0x5011,x","McBSPA XCERB");
GEL_WatchAdd("*0x5012,x","McBSPA PCR1");
GEL_WatchAdd("*0x5013,x","McBSPA RCERC");
GEL_WatchAdd("*0x5014,x","McBSPA RCERD");
GEL_WatchAdd("*0x5015,x","McBSPA XCERC");
GEL_WatchAdd("*0x5016,x","McBSPA XCERD");
GEL_WatchAdd("*0x5017,x","McBSPA RCERE");
GEL_WatchAdd("*0x5018,x","McBSPA RCERF");
GEL_WatchAdd("*0x5019,x","McBSPA XCERE");
GEL_WatchAdd("*0x501A,x","McBSPA XCERF");
GEL_WatchAdd("*0x501B,x","McBSPA RCERG");
GEL_WatchAdd("*0x501C,x","McBSPA RCERH");
GEL_WatchAdd("*0x501D,x","McBSPA XCERG");
GEL_WatchAdd("*0x501E,x","McBSPA XCERH");
GEL_WatchAdd("*0x5023,x","McBSPA MFFINT");
GEL_WatchAdd("*0x503F,x","McBSPA Revision");
}
hotmenu All_McBSP_B_Regs()
{
GEL_WatchAdd("*0x5040,x","McBSPB DRR2");
GEL_WatchAdd("*0x5041,x","McBSPB DRR1");
GEL_WatchAdd("*0x5042,x","McBSPB DXR2");
GEL_WatchAdd("*0x5043,x","McBSPB DXR1");
GEL_WatchAdd("*0x5044,x","McBSPB SPCR2");
GEL_WatchAdd("*0x5045,x","McBSPB SPCR1");
GEL_WatchAdd("*0x5046,x","McBSPB RCR2");
GEL_WatchAdd("*0x5047,x","McBSPB RCR1");
GEL_WatchAdd("*0x5048,x","McBSPB XCR2");
GEL_WatchAdd("*0x5049,x","McBSPB XCR1");
GEL_WatchAdd("*0x504A,x","McBSPB SRGR2");
GEL_WatchAdd("*0x504B,x","McBSPB SRGR1");
GEL_WatchAdd("*0x504C,x","McBSPB MCR2");
GEL_WatchAdd("*0x504D,x","McBSPB MCR1");
GEL_WatchAdd("*0x504E,x","McBSPB RCERA");
GEL_WatchAdd("*0x504F,x","McBSPB RCERB");
GEL_WatchAdd("*0x5050,x","McBSPB XCERA");
GEL_WatchAdd("*0x5051,x","McBSPB XCERB");
GEL_WatchAdd("*0x5052,x","McBSPB PCR1");
GEL_WatchAdd("*0x5053,x","McBSPB RCERC");
GEL_WatchAdd("*0x5054,x","McBSPB RCERD");
GEL_WatchAdd("*0x5055,x","McBSPB XCERC");
GEL_WatchAdd("*0x5056,x","McBSPB XCERD");
GEL_WatchAdd("*0x5057,x","McBSPB RCERE");
GEL_WatchAdd("*0x5058,x","McBSPB RCERF");
GEL_WatchAdd("*0x5059,x","McBSPB XCERE");
GEL_WatchAdd("*0x505A,x","McBSPB XCERF");
GEL_WatchAdd("*0x505B,x","McBSPB RCERG");
GEL_WatchAdd("*0x505C,x","McBSPB RCERH");
GEL_WatchAdd("*0x505D,x","McBSPB XCERG");
GEL_WatchAdd("*0x505E,x","McBSPB XCERH");
GEL_WatchAdd("*0x5063,x","McBSPB MFFINT");
GEL_WatchAdd("*0x506F,x","McBSPB Revision");
}
/********************************************************************/
/* I2C Registers */
/********************************************************************/
menuitem "Watch I2C Registers";
hotmenu All_I2C_Regs()
{
GEL_WatchAdd("*0x7900,x","I2COAR");
GEL_WatchAdd("*0x7901,x","I2CIER");
GEL_WatchAdd("*0x7902,x","I2CSTR");
GEL_WatchAdd("*0x7903,x","I2CCLKL");
GEL_WatchAdd("*0x7904,x","I2CCLKH");
GEL_WatchAdd("*0x7905,x","I2CCNT");
GEL_WatchAdd("*0x7906,x","I2CDRR");
GEL_WatchAdd("*0x7907,x","I2CSAR");
GEL_WatchAdd("*0x7908,x","I2CDXR");
GEL_WatchAdd("*0x7909,x","I2CMDR");
GEL_WatchAdd("*0x790A,x","I2CISRC");
GEL_WatchAdd("*0x790C,x","I2CPSC");
GEL_WatchAdd("*0x7920,x","I2CFFTX");
GEL_WatchAdd("*0x7921,x","I2CFFRX");
}
/********************************************************************/
/* Peripheral Interrupt Expansion Registers */
/********************************************************************/
menuitem "Watch Peripheral Interrupt Expansion Registers";
hotmenu All_PIE_Regs()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
GEL_WatchAdd("*0x0CE1,x","PIEACK");
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
hotmenu PIECTRL()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
}
hotmenu PIEACK()
{
GEL_WatchAdd("*0x0CE1,x","PIEACK");
}
hotmenu PIEIER1_and_PIEIFR1()
{
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
}
hotmenu PIEIER2_and_PIEIFR2()
{
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
}
hotmenu PIEIER3_and_PIEIFR3()
{
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
}
hotmenu PIEIER4_and_PIEIFR4()
{
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
}
hotmenu PIEIER5_and_PIEIFR5()
{
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
}
hotmenu PIEIER6_and_PIEIFR6()
{
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
}
hotmenu PIEIER7_and_PIEIFR7()
{
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
}
hotmenu PIEIER8_and_PIEIFR8()
{
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
}
hotmenu PIEIER9_and_PIEIFR9()
{
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
}
hotmenu PIEIFR10_and_PIEIFR10()
{
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
}
hotmenu PIEIER11_and_PIEIFR11()
{
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
}
hotmenu PIEIER12_and_PIEIFR12()
{
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
/********************************************************************/
/* Serial Communication Interface Registers */
/********************************************************************/
menuitem "Watch SCI Registers";
hotmenu SCI_A_All_Regs()
{
GEL_WatchAdd("*0x7050,x","SCICCRA");
GEL_WatchAdd("*0x7051,x","SCICTL1A");
GEL_WatchAdd("*0x7052,x","SCIHBAUDA");
GEL_WatchAdd("*0x7053,x","SCILBAUDA");
GEL_WatchAdd("*0x7054,x","SCICTL2A");
GEL_WatchAdd("*0x7055,x","SCIRXSTA");
GEL_WatchAdd("*0x7056,x","SCIRXEMUA");
GEL_WatchAdd("*0x7057,x","SCIRXBUFA");
GEL_WatchAdd("*0x7059,x","SCITXBUFA");
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
GEL_WatchAdd("*0x705F,x","SCIPRIA");
}
hotmenu SCI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
}
hotmenu SCI_B_All_Regs()
{
GEL_WatchAdd("*0x7750,x","SCICCRB");
GEL_WatchAdd("*0x7751,x","SCICTL1B");
GEL_WatchAdd("*0x7752,x","SCIHBAUDB");
GEL_WatchAdd("*0x7753,x","SCILBAUDB");
GEL_WatchAdd("*0x7754,x","SCICTL2B");
GEL_WatchAdd("*0x7755,x","SCIRXSTB");
GEL_WatchAdd("*0x7756,x","SCIRXEMUB");
GEL_WatchAdd("*0x7757,x","SCIRXBUFB");
GEL_WatchAdd("*0x7759,x","SCITXBUFB");
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
GEL_WatchAdd("*0x775F,x","SCIPRIB");
}
hotmenu SCI_B_FIFO_Registers()
{
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
}
hotmenu SCI_C_All_Regs()
{
GEL_WatchAdd("*0x7770,x","SCICCRC");
GEL_WatchAdd("*0x7771,x","SCICTL1C");
GEL_WatchAdd("*0x7772,x","SCIHBAUDC");
GEL_WatchAdd("*0x7773,x","SCILBAUDC");
GEL_WatchAdd("*0x7774,x","SCICTL2C");
GEL_WatchAdd("*0x7775,x","SCIRXSTC");
GEL_WatchAdd("*0x7776,x","SCIRXEMUC");
GEL_WatchAdd("*0x7777,x","SCIRXBUFC");
GEL_WatchAdd("*0x7779,x","SCITXBUFC");
GEL_WatchAdd("*0x777A,x","SCIFFTXC");
GEL_WatchAdd("*0x777B,x","SCIFFRXC");
GEL_WatchAdd("*0x777C,x","SCIFFCTC");
GEL_WatchAdd("*0x777F,x","SCIPRIC");
}
hotmenu SCI_C_FIFO_Registers()
{
GEL_WatchAdd("*0x777A,x","SCIFFTXC");
GEL_WatchAdd("*0x777B,x","SCIFFRXC");
GEL_WatchAdd("*0x777C,x","SCIFFCTC");
}
/********************************************************************/
/* Serial Peripheral Interface Registers */
/********************************************************************/
menuitem "Watch SPI Registers";
hotmenu SPI_A_All_Regs()
{
GEL_WatchAdd("*0x7040,x","SPIA SPICCR");
GEL_WatchAdd("*0x7041,x","SPIA SPICTL");
GEL_WatchAdd("*0x7042,x","SPIA SPIST");
GEL_WatchAdd("*0x7044,x","SPIA SPIBRR");
GEL_WatchAdd("*0x7046,x","SPIA SPIEMU");
GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF");
GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF");
GEL_WatchAdd("*0x7049,x","SPIA SPIDAT");
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
GEL_WatchAdd("*0x704F,x","SPIA SPIPRI");
}
hotmenu SPI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
}
/********************************************************************/
/* Watchdog Timer Registers */
/********************************************************************/
menuitem "Watch Watchdog Timer Registers";
hotmenu All_Watchdog_Regs()
{
GEL_WatchAdd("*0x7023,x","WDCNTR");
GEL_WatchAdd("*0x7025,x","WDKEY");
GEL_WatchAdd("*0x7029,x","WDCR");
GEL_WatchAdd("*0x7022,x","SCSR");
}
/********************************************************************/
/*** End of file ***/

2845
v120/DSP2833x_common/gel/f28332.gel Normal file
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/********************************************************************/
/* f28332.gel */
/* Version 3.30.2 */
/* */
/* This GEL file is to be used with the TMS320F28332 DSP. */
/* Changes may be required to support specific hardware designs. */
/* */
/* Code Composer Studio supports six reserved GEL functions that */
/* automatically get executed if they are defined. They are: */
/* */
/* StartUp() - Executed whenever CCS is invoked */
/* OnReset() - Executed after Debug->Reset CPU */
/* OnRestart() - Executed after Debug->Restart */
/* OnPreFileLoaded() - Executed before File->Load Program */
/* OnFileLoaded() - Executed after File->Load Program */
/* OnTargetConnect() - Executed after Debug->Connect */
/* */
/********************************************************************/
StartUp()
{
/* The next line automatically loads the .gel file that comes */
/* with the DSP2833x Peripheral Header Files download. To use, */
/* uncomment, and adjust the directory path as needed. */
// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel");
}
OnReset(int nErrorCode)
{
C28x_Mode();
Unlock_CSM();
ADC_Cal();
}
OnRestart(int nErrorCode)
{
/* CCS will call OnRestart() when you do a Debug->Restart and */
/* after you load a new file. Between running interrupt based */
/* programs, this function will clear interrupts and help keep */
/* the processor from going off into invalid memory. */
C28x_Mode();
IER = 0;
IFR = 0;
ADC_Cal();
}
int TxtOutCtl=0;
OnPreFileLoaded()
{
XINTF_Enable();
if (TxtOutCtl==0)
{
GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use.");
GEL_TextOut("\nFPU Registers can be found via GEL->Watch FPU Registers.");
TxtOutCtl=1;
}
}
OnFileLoaded(int nErrorCode, int bSymbolsOnly)
{
ADC_Cal();
}
OnTargetConnect()
{
C28x_Mode();
F28332_Memory_Map(); /* Initialize the CCS memory map */
/* Check to see if CCS has been started-up with the DSP already */
/* running in real-time mode. The user can add whatever */
/* custom initialization stuff they want to each case. */
if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */
{
}
else /* Do stop-mode target initialization */
{
GEL_Reset(); /* Reset DSP */
}
}
/********************************************************************/
/* These functions are launched by the GEL_Toolbar button plugin */
/********************************************************************/
GEL_Toolbar1()
{
Run_Realtime_with_Reset();
}
GEL_Toolbar2()
{
Run_Realtime_with_Restart();
}
GEL_Toolbar3()
{
Full_Halt();
}
GEL_Toolbar4()
{
Full_Halt_with_Reset();
}
int GEL_Toolbar5_Toggle = 0;
GEL_Toolbar5()
{
if(GEL_Toolbar5_Toggle == 0)
{
GEL_Toolbar5_Toggle = 1;
GEL_OpenWindow("GEL_Buttons",1,4);
GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0);
GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1);
GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2);
GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3);
}
else
{
GEL_Toolbar5_Toggle = 0;
GEL_CloseWindow("GEL_Buttons");
}
}
/********************************************************************/
/* These functions are useful to engage/dis-enagage realtime */
/* emulation mode during debug. They save the user from having to */
/* manually perform these steps in CCS. */
/********************************************************************/
menuitem "Realtime Emulation Control";
hotmenu Run_Realtime_with_Reset()
{
GEL_Reset(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Run_Realtime_with_Restart()
{
GEL_Restart(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Full_Halt()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
}
hotmenu Full_Halt_with_Reset()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
GEL_Reset(); /* Reset the DSP */
}
/********************************************************************/
/* F28332 Memory Map */
/* */
/* Note: M0M1MAP and VMAP signals tied high on F28332 core */
/* */
/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */
/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */
/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */
/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */
/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */
/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */
/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */
/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */
/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */
/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */
/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */
/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */
/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */
/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */
/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */
/* 0x330000 - 0x33ffff Flash (Prog and Data) */
/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */
/* 0x380090 - 0x380090 PARTID value (Prog and Data) */
/* 0x380400 - 0x3807ff OTP (Prog and Data) */
/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */
/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */
/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */
/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */
/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */
/********************************************************************/
menuitem "Initialize Memory Map";
hotmenu F28332_Memory_Map()
{
GEL_MapReset();
GEL_MapOn();
/* Program memory map */
GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x330000,0,0x10000,1,0); /* FLASH */
GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */
GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */
/* Data memory map */
GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */
GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */
GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */
GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */
GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x330000,1,0x10000,1,0); /* FLASH */
GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */
GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */
}
/********************************************************************/
/* The ESTOP0 fill functions are useful for debug. They fill the */
/* RAM with software breakpoints that will trap runaway code. */
/********************************************************************/
hotmenu Fill_F28332_RAM_with_ESTOP0()
{
GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */
GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */
GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */
GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */
}
/********************************************************************/
menuitem "Watchdog";
hotmenu Disable_WD()
{
*0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */
*0x7025 = 0x0055; /* Service the WD */
*0x7025 = 0x00AA; /* once to be safe. */
GEL_TextOut("\nWatchdog Timer Disabled");
}
/********************************************************************/
menuitem "Code Security Module"
hotmenu Unlock_CSM()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
/* Write passwords to the KEY registers. 0xFFFF's are dummy passwords.
User should replace them with the correct password for their DSP */
*0xAE0 = 0xFFFF;
*0xAE1 = 0xFFFF;
*0xAE2 = 0xFFFF;
*0xAE3 = 0xFFFF;
*0xAE4 = 0xFFFF;
*0xAE5 = 0xFFFF;
*0xAE6 = 0xFFFF;
*0xAE7 = 0xFFFF;
}
/********************************************************************/
menuitem "Addressing Modes";
hotmenu C28x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C24x_Mode()
{
ST1 = ST1 | 0x0100; /* AMODE = 1 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C27x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */
}
/********************************************************************/
/* PLL Ratios */
/* */
/* The following table describes the PLL clocking ratios (0..10) */
/* */
/* Ratio CLKIN Description */
/* ----- -------------- ------------ */
/* 0 OSCCLK/2 PLL bypassed */
/* 1 (OSCCLK * 1)/2 10 Mhz for 20 Mhz CLKIN */
/* 2 (OSCCLK * 2)/2 20 Mhz for 20 Mhz CLKIN */
/* 3 (OSCCLK * 3)/2 30 Mhz for 20 Mhz CLKIN */
/* 4 (OSCCLK * 4)/2 40 Mhz for 20 Mhz CLKIN */
/* 5 (OSCCLK * 5)/2 50 Mhz for 20 Mhz CLKIN */
/* 6 (OSCCLK * 6)/2 60 Mhz for 20 Mhz CLKIN */
/* 7 (OSCCLK * 7)/2 70 Mhz for 20 Mhz CLKIN */
/* 8 (OSCCLK * 8)/2 80 Mhz for 20 Mhz CLKIN */
/* 9 (OSCCLK * 9)/2 90 Mhz for 20 Mhz CLKIN */
/* 10 (OSCCLK * 10)/2 100 Mhz for 20 Mhz CLKIN */
/********************************************************************/
menuitem "Set PLL Ratio";
hotmenu Bypass()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */
PLL_Wait();
}
hotmenu OSCCLK_x1_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x2_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x3_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x4_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x5_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x6_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x7_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x8_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x9_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x10_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */
PLL_Wait();
}
// hotmenu OSCCLK_x1_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x2_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x3_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x4_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x5_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x6_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x7_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x8_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x9_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x10_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */
// PLL_Wait();
// }
/********************************************************************/
/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */
/********************************************************************/
DIVSEL_div2()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
temp = *PLLSTS;
temp &= 0xFE7F; /* Clear bits 7 & 8 */
temp |= 2 << 7; /* Set bit 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
/********************************************************************/
/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to /1 */
/********************************************************************/
DIVSEL_div1()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */
wait();
temp = *PLLSTS;
temp |= 3 << 7; /* Set bits 7 & 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
wait()
{
int delay = 0;
for (delay = 0; delay <= 5; delay ++)
{}
}
/********************************************************************/
/* For F2833x devices, check the PLLOCKS bit for PLL lock. */
/********************************************************************/
PLL_Wait()
{
int PLLSTS;
int delay = 0;
PLLSTS = 0x7011;
while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001)
{
delay++;
GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
/********************************************************************/
/* Load the ADC Calibration values from TI OTP */
/********************************************************************/
menuitem "ADC Calibration"
hotmenu ADC_Cal()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
if(((*0x0AEF) & 0x0001) == 0)
{
XAR0 = *0x701C;
*0x701C |= 0x0008;
*0x711C = *0x380083;
*0x711D = *0x380085;
*0x701C = XAR0;
XAR0 = 0;
}
else
{
GEL_TextOut("\nADC Calibration not complete, device is secure");
}
}
/********************************************************************/
/* Enable the XINTF and configure GPIOs for XINTF function */
/********************************************************************/
menuitem "XINTF Enable"
hotmenu XINTF_Enable()
{
/* enable XINTF clock (XTIMCLK) */
*0x7020 = 0x3700;
/* GPBMUX1: XA0-XA7, XA16, XZCS0, */
/* XZCS7, XREADY, XRNW, XWE0 */
/* GPAMUX2: XA17-XA19, XZCS6 */
/* GPCMUX2: XA8-XA15 */
/* GPCMUX1: XD0-XD15 */
*(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */
*(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */
*(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */
*(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */
/* Uncomment for x32 data bus */
/* GPBMUX2: XD16-XD31 */
// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */
/* Zone timing.
/* Each zone can be configured seperately */
/* Uncomment the x16 or the x32 timing */
/* depending on the data bus width for */
/* the zone */
/* x16 Timing */
*(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */
*(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */
*(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */
/* x32 Timing:
// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */
}
/********************************************************************/
/* The below are used to display the symbolic names of the F28332 */
/* memory mapped registers in the watch window. To view these */
/* registers, click on the GEL menu button in Code Composer Studio, */
/* then select which registers or groups of registers you want to */
/* view. They will appear in the watch window under the Watch1 tab. */
/********************************************************************/
/* Add a space line to the GEL menu */
menuitem "______________________________________";
hotmenu __() {}
/********************************************************************/
/* A/D Converter Registers */
/********************************************************************/
menuitem "Watch ADC Registers";
hotmenu All_ADC_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
hotmenu ADC_Control_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
}
hotmenu ADCCHSELSEQx_Regs()
{
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
}
hotmenu ADCRESULT_0_to_7()
{
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
}
hotmenu ADCRESULT_8_to_15()
{
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
}
hotmenu ADCRESULT_Mirror_0_to_7()
{
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
}
hotmenu ADCRESULT_Mirror_8_to_15()
{
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
/********************************************************************/
/* Clocking and Low-Power Registers */
/********************************************************************/
menuitem "Watch Clocking and Low-Power Registers";
hotmenu All_Clocking_and_Low_Power_Regs()
{
GEL_WatchAdd("*0x7010,x","XCLK");
GEL_WatchAdd("*0x7011,x","PLLSTS");
GEL_WatchAdd("*0x701A,x","HISPCP");
GEL_WatchAdd("*0x701B,x","LOSPCP");
GEL_WatchAdd("*0x701C,x","PCLKCR0");
GEL_WatchAdd("*0x701D,x","PCLKCR1");
GEL_WatchAdd("*0x701E,x","LPMCR0");
GEL_WatchAdd("*0x7020,x","PCLKCR3");
GEL_WatchAdd("*0x7021,x","PLLCR");
}
/********************************************************************/
/* Code Security Module Registers */
/********************************************************************/
menuitem "Watch Code Security Module Registers";
hotmenu CSMSCR()
{
GEL_WatchAdd("*0x0AEF,x","CSMSCR");
GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit");
GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit");
}
hotmenu PWL_Locations()
{
GEL_WatchAdd("*0x33FFF8,x","PWL0");
GEL_WatchAdd("*0x33FFF9,x","PWL1");
GEL_WatchAdd("*0x33FFFA,x","PWL2");
GEL_WatchAdd("*0x33FFFB,x","PWL3");
GEL_WatchAdd("*0x33FFFC,x","PWL4");
GEL_WatchAdd("*0x33FFFD,x","PWL5");
GEL_WatchAdd("*0x33FFFE,x","PWL6");
GEL_WatchAdd("*0x33FFFF,x","PWL7");
}
/********************************************************************/
/* CPU Timer Registers */
/********************************************************************/
menuitem "Watch CPU Timer Registers";
hotmenu All_CPU_Timer0_Regs()
{
GEL_WatchAdd("*0x0C00,x","TIMER0TIM");
GEL_WatchAdd("*0x0C01,x","TIMER0TIMH");
GEL_WatchAdd("*0x0C02,x","TIMER0PRD");
GEL_WatchAdd("*0x0C03,x","TIMER0PRDH");
GEL_WatchAdd("*0x0C04,x","TIMER0TCR");
GEL_WatchAdd("*0x0C06,x","TIMER0TPR");
GEL_WatchAdd("*0x0C07,x","TIMER0TPRH");
}
hotmenu All_CPU_Timer1_Regs()
{
GEL_WatchAdd("*0x0C08,x","TIMER1TIM");
GEL_WatchAdd("*0x0C09,x","TIMER1TIMH");
GEL_WatchAdd("*0x0C0A,x","TIMER1PRD");
GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH");
GEL_WatchAdd("*0x0C0C,x","TIMER1TCR");
GEL_WatchAdd("*0x0C0E,x","TIMER1TPR");
GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH");
}
hotmenu All_CPU_Timer2_Regs()
{
GEL_WatchAdd("*0x0C10,x","TIMER2TIM");
GEL_WatchAdd("*0x0C11,x","TIMER2TIMH");
GEL_WatchAdd("*0x0C12,x","TIMER2PRD");
GEL_WatchAdd("*0x0C13,x","TIMER2PRDH");
GEL_WatchAdd("*0x0C14,x","TIMER2TCR");
GEL_WatchAdd("*0x0C16,x","TIMER2TPR");
GEL_WatchAdd("*0x0C17,x","TIMER2TPRH");
}
/********************************************************************/
/* Device Emulation Registers */
/********************************************************************/
menuitem "Watch Device Emulation Registers";
hotmenu All_Emulation_Regs()
{
GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF");
GEL_WatchAdd("*0x0882,x","CLASSID");
GEL_WatchAdd("*0x0883,x","REVID");
GEL_WatchAdd("*0x0884,x","PROTSTART");
GEL_WatchAdd("*0x0885,x","PROTRANGE");
GEL_WatchAdd("*0x380090,x","PARTID");
}
/********************************************************************/
/* DMA Registers */
/********************************************************************/
menuitem "Watch DMA Registers";
hotmenu All_DMA_Regs()
{
GEL_WatchAdd("*0x1000,x","DMACTRL");
GEL_WatchAdd("*0x1001,x","DEBUGCTRL");
GEL_WatchAdd("*0x1002,x","REVISION");
GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1");
GEL_WatchAdd("*0x1006,x","PRIORITYSTAT");
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_1_regs()
{
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_2_regs()
{
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_3_regs()
{
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_4_regs()
{
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_5_regs()
{
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_6_regs()
{
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
/********************************************************************/
/* eCAN Registers */
/********************************************************************/
menuitem "Watch eCAN Registers";
hotmenu eCAN_A_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME");
GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD");
GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS");
GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR");
GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA");
GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA");
GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP");
GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML");
GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP");
GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC");
GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC");
GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES");
GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC");
GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC");
GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0");
GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM");
GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1");
GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM");
GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL");
GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC");
GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC");
GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC");
GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT");
GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC");
GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS");
}
hotmenu eCAN_A_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0");
GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0");
GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0");
GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0");
GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0");
GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0");
GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0");
GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1");
GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1");
GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1");
GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1");
GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1");
GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1");
GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1");
}
hotmenu eCAN_A_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2");
GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2");
GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2");
GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2");
GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2");
GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2");
GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2");
GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3");
GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3");
GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3");
GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3");
GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3");
GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3");
GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3");
}
hotmenu eCAN_A_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4");
GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4");
GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4");
GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4");
GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4");
GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4");
GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4");
GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5");
GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5");
GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5");
GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5");
GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5");
GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5");
GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5");
}
hotmenu eCAN_A_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6");
GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6");
GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6");
GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6");
GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6");
GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6");
GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6");
GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7");
GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7");
GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7");
GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7");
GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7");
GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7");
GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7");
}
hotmenu eCAN_A_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8");
GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8");
GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8");
GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8");
GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8");
GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8");
GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8");
GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9");
GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9");
GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9");
GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9");
GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9");
GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9");
GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9");
}
hotmenu eCAN_A_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10");
GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10");
GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10");
GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10");
GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10");
GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10");
GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10");
GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11");
GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11");
GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11");
GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11");
GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11");
GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11");
GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11");
}
hotmenu eCAN_A_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12");
GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12");
GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12");
GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12");
GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12");
GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12");
GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12");
GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13");
GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13");
GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13");
GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13");
GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13");
GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13");
GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13");
}
hotmenu eCAN_A_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14");
GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14");
GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14");
GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14");
GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14");
GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14");
GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14");
GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15");
GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15");
GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15");
GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15");
GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15");
GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15");
GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15");
}
hotmenu eCAN_A_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16");
GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16");
GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16");
GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16");
GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16");
GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16");
GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16");
GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17");
GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17");
GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17");
GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17");
GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17");
GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17");
GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17");
}
hotmenu eCAN_A_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18");
GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18");
GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18");
GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18");
GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18");
GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18");
GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18");
GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19");
GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19");
GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19");
GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19");
GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19");
GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19");
GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19");
}
hotmenu eCAN_A_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20");
GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20");
GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20");
GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20");
GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20");
GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20");
GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20");
GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21");
GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21");
GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21");
GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21");
GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21");
GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21");
GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21");
}
hotmenu eCAN_A_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22");
GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22");
GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22");
GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22");
GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22");
GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22");
GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22");
GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23");
GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23");
GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23");
GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23");
GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23");
GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23");
GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23");
}
hotmenu eCAN_A_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24");
GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24");
GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24");
GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24");
GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24");
GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24");
GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24");
GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25");
GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25");
GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25");
GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25");
GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25");
GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25");
GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25");
}
hotmenu eCAN_A_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26");
GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26");
GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26");
GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26");
GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26");
GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26");
GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26");
GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27");
GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27");
GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27");
GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27");
GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27");
GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27");
GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27");
}
hotmenu eCAN_A_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28");
GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28");
GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28");
GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28");
GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28");
GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28");
GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28");
GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29");
GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29");
GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29");
GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29");
GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29");
GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29");
GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29");
}
hotmenu eCAN_A_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30");
GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30");
GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30");
GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30");
GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30");
GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30");
GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30");
GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31");
GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31");
GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31");
GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31");
GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31");
GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31");
GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31");
}
hotmenu eCAN_B_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME");
GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD");
GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS");
GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR");
GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA");
GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA");
GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP");
GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML");
GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP");
GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC");
GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC");
GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES");
GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC");
GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC");
GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0");
GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM");
GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1");
GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM");
GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL");
GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC");
GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC");
GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC");
GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT");
GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC");
GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS");
}
hotmenu eCAN_B_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0");
GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0");
GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0");
GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0");
GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0");
GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0");
GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0");
GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1");
GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1");
GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1");
GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1");
GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1");
GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1");
GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1");
}
hotmenu eCAN_B_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2");
GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2");
GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2");
GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2");
GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2");
GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2");
GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2");
GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3");
GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3");
GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3");
GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3");
GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3");
GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3");
GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3");
}
hotmenu eCAN_B_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4");
GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4");
GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4");
GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4");
GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4");
GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4");
GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4");
GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5");
GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5");
GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5");
GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5");
GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5");
GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5");
GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5");
}
hotmenu eCAN_B_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6");
GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6");
GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6");
GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6");
GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6");
GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6");
GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6");
GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7");
GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7");
GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7");
GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7");
GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7");
GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7");
GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7");
}
hotmenu eCAN_B_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8");
GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8");
GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8");
GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8");
GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8");
GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8");
GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8");
GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9");
GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9");
GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9");
GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9");
GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9");
GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9");
GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9");
}
hotmenu eCAN_B_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10");
GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10");
GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10");
GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10");
GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10");
GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10");
GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10");
GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11");
GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11");
GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11");
GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11");
GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11");
GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11");
GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11");
}
hotmenu eCAN_B_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12");
GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12");
GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12");
GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12");
GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12");
GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12");
GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12");
GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13");
GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13");
GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13");
GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13");
GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13");
GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13");
GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13");
}
hotmenu eCAN_B_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14");
GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14");
GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14");
GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14");
GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14");
GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14");
GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14");
GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15");
GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15");
GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15");
GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15");
GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15");
GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15");
GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15");
}
hotmenu eCAN_B_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16");
GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16");
GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16");
GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16");
GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16");
GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16");
GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16");
GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17");
GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17");
GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17");
GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17");
GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17");
GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17");
GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17");
}
hotmenu eCAN_B_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18");
GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18");
GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18");
GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18");
GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18");
GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18");
GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18");
GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19");
GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19");
GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19");
GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19");
GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19");
GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19");
GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19");
}
hotmenu eCAN_B_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20");
GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20");
GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20");
GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20");
GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20");
GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20");
GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20");
GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21");
GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21");
GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21");
GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21");
GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21");
GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21");
GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21");
}
hotmenu eCAN_B_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22");
GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22");
GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22");
GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22");
GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22");
GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22");
GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22");
GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23");
GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23");
GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23");
GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23");
GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23");
GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23");
GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23");
}
hotmenu eCAN_B_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24");
GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24");
GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24");
GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24");
GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24");
GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24");
GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24");
GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25");
GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25");
GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25");
GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25");
GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25");
GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25");
GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25");
}
hotmenu eCAN_B_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26");
GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26");
GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26");
GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26");
GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26");
GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26");
GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26");
GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27");
GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27");
GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27");
GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27");
GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27");
GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27");
GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27");
}
hotmenu eCAN_B_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28");
GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28");
GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28");
GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28");
GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28");
GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28");
GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28");
GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29");
GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29");
GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29");
GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29");
GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29");
GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29");
GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29");
}
hotmenu eCAN_B_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30");
GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30");
GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30");
GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30");
GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30");
GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30");
GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30");
GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31");
GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31");
GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31");
GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31");
GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31");
GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31");
GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31");
}
/********************************************************************/
/* Enhanced Capture Registers */
/********************************************************************/
menuitem "Watch eCAP Registers";
hotmenu eCAP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT");
GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS");
GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1");
GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2");
GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3");
GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4");
GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1");
GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2");
GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT");
GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG");
GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR");
GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC");
}
hotmenu eCAP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT");
GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS");
GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1");
GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2");
GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3");
GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4");
GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1");
GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2");
GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT");
GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG");
GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR");
GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC");
}
hotmenu eCAP3_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT");
GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS");
GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1");
GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2");
GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3");
GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4");
GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1");
GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2");
GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT");
GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG");
GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR");
GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC");
}
hotmenu eCAP4_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT");
GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS");
GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1");
GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2");
GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3");
GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4");
GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1");
GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2");
GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT");
GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG");
GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR");
GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC");
}
/********************************************************************/
/* Enhanced PWM Registers */
/********************************************************************/
menuitem "Watch ePWM Registers";
hotmenu ePWM1_All_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL");
GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG");
}
hotmenu ePWM1_TB_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
}
hotmenu ePWM1_CMP_Regs()
{
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
}
hotmenu ePWM1_AQ_Regs()
{
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
}
hotmenu ePWM1_DB_Regs()
{
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
}
hotmenu ePWM1_TZ_Regs()
{
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
}
hotmenu ePWM1_ET_Regs()
{
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
}
hotmenu ePWM2_All_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL");
GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG");
}
hotmenu ePWM2_TB_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
}
hotmenu ePWM2_CMP_Regs()
{
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
}
hotmenu ePWM2_AQ_Regs()
{
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
}
hotmenu ePWM2_DB_Regs()
{
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
}
hotmenu ePWM2_TZ_Regs()
{
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
}
hotmenu ePWM2_ET_Regs()
{
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
}
hotmenu ePWM3_All_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL");
GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG");
}
hotmenu ePWM3_TB_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
}
hotmenu ePWM3_CMP_Regs()
{
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
}
hotmenu ePWM3_AQ_Regs()
{
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
}
hotmenu ePWM3_DB_Regs()
{
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
}
hotmenu ePWM3_TZ_Regs()
{
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
}
hotmenu ePWM3_ET_Regs()
{
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
}
hotmenu ePWM4_All_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL");
GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG");
}
hotmenu ePWM4_TB_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
}
hotmenu ePWM4_CMP_Regs()
{
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
}
hotmenu ePWM4_AQ_Regs()
{
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
}
hotmenu ePWM4_DB_Regs()
{
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
}
hotmenu ePWM4_TZ_Regs()
{
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
}
hotmenu ePWM4_ET_Regs()
{
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
}
hotmenu ePWM5_All_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL");
}
hotmenu ePWM5_TB_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
}
hotmenu ePWM5_CMP_Regs()
{
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
}
hotmenu ePWM5_AQ_Regs()
{
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
}
hotmenu ePWM5_DB_Regs()
{
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
}
hotmenu ePWM5_TZ_Regs()
{
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
}
hotmenu ePWM5_ET_Regs()
{
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
}
hotmenu ePWM6_All_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL");
}
hotmenu ePWM6_TB_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
}
hotmenu ePWM6_CMP_Regs()
{
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
}
hotmenu ePWM6_AQ_Regs()
{
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
}
hotmenu ePWM6_DB_Regs()
{
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
}
hotmenu ePWM6_TZ_Regs()
{
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
}
hotmenu ePWM6_ET_Regs()
{
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
}
/********************************************************************/
/* Enhanced EQEP Registers */
/********************************************************************/
menuitem "Watch eQEP"
hotmenu eQEP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT");
GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR");
GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD");
GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR");
GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD");
GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL");
GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL");
GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL");
GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL");
GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT");
GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG");
GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR");
GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC");
GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS");
GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR");
GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD");
GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT");
GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT");
}
hotmenu eQEP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT");
GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR");
GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD");
GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR");
GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD");
GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL");
GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL");
GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL");
GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL");
GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT");
GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG");
GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR");
GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC");
GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS");
GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR");
GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD");
GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT");
GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT");
}
/********************************************************************/
/* External Interface Registers */
/********************************************************************/
menuitem "Watch External Interface Registers";
hotmenu All_External_Interface_Regs()
{
GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0");
GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6");
GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7");
GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2");
GEL_WatchAdd("*0x0B38,x","XBANK");
GEL_WatchAdd("*0x0B3A,x","XREVISION");
GEL_WatchAdd("*0x0B3D,x","XRESET");
}
/********************************************************************/
/* External Interrupt Registers */
/********************************************************************/
menuitem "Watch External Interrupt Registers";
hotmenu All_XINT_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
hotmenu XINT_Control_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
}
hotmenu XINT_Counter_Regs()
{
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
/********************************************************************/
/* FPU Registers */
/********************************************************************/
menuitem "Watch FPU Registers"
hotmenu All_FPU_Single_Precision_Regs()
{
GEL_WatchAdd("RB");
GEL_WatchAdd("STF");
GEL_WatchAdd("R0H");
GEL_WatchAdd("R1H");
GEL_WatchAdd("R2H");
GEL_WatchAdd("R3H");
GEL_WatchAdd("R4H");
GEL_WatchAdd("R5H");
GEL_WatchAdd("R6H");
GEL_WatchAdd("R7H");
}
/********************************************************************/
/* GPIO Registers */
/********************************************************************/
menuitem "Watch GPIO Registers";
hotmenu All_GPIO_CONTROL_Regs()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
}
hotmenu All_GPIO_DATA_Regs()
{
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
hotmenu All_GPIO_INTERRUPT_Regs()
{
GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL");
GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL");
GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL");
GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL");
GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL");
GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL");
GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL");
GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL");
GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL");
}
hotmenu All_GPA_Registers()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
}
hotmenu All_GPB_Registers()
{
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
}
hotmenu All_GPC_Registers()
{
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
/********************************************************************/
/* Multichannel Serial Port Registers */
/********************************************************************/
menuitem "Watch McBSP Registers";
hotmenu All_McBSP_A_Regs()
{
GEL_WatchAdd("*0x5000,x","McBSPA DRR2");
GEL_WatchAdd("*0x5001,x","McBSPA DRR1");
GEL_WatchAdd("*0x5002,x","McBSPA DXR2");
GEL_WatchAdd("*0x5003,x","McBSPA DXR1");
GEL_WatchAdd("*0x5004,x","McBSPA SPCR2");
GEL_WatchAdd("*0x5005,x","McBSPA SPCR1");
GEL_WatchAdd("*0x5006,x","McBSPA RCR2");
GEL_WatchAdd("*0x5007,x","McBSPA RCR1");
GEL_WatchAdd("*0x5008,x","McBSPA XCR2");
GEL_WatchAdd("*0x5009,x","McBSPA XCR1");
GEL_WatchAdd("*0x500A,x","McBSPA SRGR2");
GEL_WatchAdd("*0x500B,x","McBSPA SRGR1");
GEL_WatchAdd("*0x500C,x","McBSPA MCR2");
GEL_WatchAdd("*0x500D,x","McBSPA MCR1");
GEL_WatchAdd("*0x500E,x","McBSPA RCERA");
GEL_WatchAdd("*0x500F,x","McBSPA RCERB");
GEL_WatchAdd("*0x5010,x","McBSPA XCERA");
GEL_WatchAdd("*0x5011,x","McBSPA XCERB");
GEL_WatchAdd("*0x5012,x","McBSPA PCR1");
GEL_WatchAdd("*0x5013,x","McBSPA RCERC");
GEL_WatchAdd("*0x5014,x","McBSPA RCERD");
GEL_WatchAdd("*0x5015,x","McBSPA XCERC");
GEL_WatchAdd("*0x5016,x","McBSPA XCERD");
GEL_WatchAdd("*0x5017,x","McBSPA RCERE");
GEL_WatchAdd("*0x5018,x","McBSPA RCERF");
GEL_WatchAdd("*0x5019,x","McBSPA XCERE");
GEL_WatchAdd("*0x501A,x","McBSPA XCERF");
GEL_WatchAdd("*0x501B,x","McBSPA RCERG");
GEL_WatchAdd("*0x501C,x","McBSPA RCERH");
GEL_WatchAdd("*0x501D,x","McBSPA XCERG");
GEL_WatchAdd("*0x501E,x","McBSPA XCERH");
GEL_WatchAdd("*0x5023,x","McBSPA MFFINT");
GEL_WatchAdd("*0x503F,x","McBSPA Revision");
}
/********************************************************************/
/* I2C Registers */
/********************************************************************/
menuitem "Watch I2C Registers";
hotmenu All_I2C_Regs()
{
GEL_WatchAdd("*0x7900,x","I2COAR");
GEL_WatchAdd("*0x7901,x","I2CIER");
GEL_WatchAdd("*0x7902,x","I2CSTR");
GEL_WatchAdd("*0x7903,x","I2CCLKL");
GEL_WatchAdd("*0x7904,x","I2CCLKH");
GEL_WatchAdd("*0x7905,x","I2CCNT");
GEL_WatchAdd("*0x7906,x","I2CDRR");
GEL_WatchAdd("*0x7907,x","I2CSAR");
GEL_WatchAdd("*0x7908,x","I2CDXR");
GEL_WatchAdd("*0x7909,x","I2CMDR");
GEL_WatchAdd("*0x790A,x","I2CISRC");
GEL_WatchAdd("*0x790C,x","I2CPSC");
GEL_WatchAdd("*0x7920,x","I2CFFTX");
GEL_WatchAdd("*0x7921,x","I2CFFRX");
}
/********************************************************************/
/* Peripheral Interrupt Expansion Registers */
/********************************************************************/
menuitem "Watch Peripheral Interrupt Expansion Registers";
hotmenu All_PIE_Regs()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
GEL_WatchAdd("*0x0CE1,x","PIEACK");
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
hotmenu PIECTRL()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
}
hotmenu PIEACK()
{
GEL_WatchAdd("*0x0CE1,x","PIEACK");
}
hotmenu PIEIER1_and_PIEIFR1()
{
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
}
hotmenu PIEIER2_and_PIEIFR2()
{
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
}
hotmenu PIEIER3_and_PIEIFR3()
{
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
}
hotmenu PIEIER4_and_PIEIFR4()
{
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
}
hotmenu PIEIER5_and_PIEIFR5()
{
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
}
hotmenu PIEIER6_and_PIEIFR6()
{
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
}
hotmenu PIEIER7_and_PIEIFR7()
{
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
}
hotmenu PIEIER8_and_PIEIFR8()
{
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
}
hotmenu PIEIER9_and_PIEIFR9()
{
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
}
hotmenu PIEIFR10_and_PIEIFR10()
{
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
}
hotmenu PIEIER11_and_PIEIFR11()
{
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
}
hotmenu PIEIER12_and_PIEIFR12()
{
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
/********************************************************************/
/* Serial Communication Interface Registers */
/********************************************************************/
menuitem "Watch SCI Registers";
hotmenu SCI_A_All_Regs()
{
GEL_WatchAdd("*0x7050,x","SCICCRA");
GEL_WatchAdd("*0x7051,x","SCICTL1A");
GEL_WatchAdd("*0x7052,x","SCIHBAUDA");
GEL_WatchAdd("*0x7053,x","SCILBAUDA");
GEL_WatchAdd("*0x7054,x","SCICTL2A");
GEL_WatchAdd("*0x7055,x","SCIRXSTA");
GEL_WatchAdd("*0x7056,x","SCIRXEMUA");
GEL_WatchAdd("*0x7057,x","SCIRXBUFA");
GEL_WatchAdd("*0x7059,x","SCITXBUFA");
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
GEL_WatchAdd("*0x705F,x","SCIPRIA");
}
hotmenu SCI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
}
hotmenu SCI_B_All_Regs()
{
GEL_WatchAdd("*0x7750,x","SCICCRB");
GEL_WatchAdd("*0x7751,x","SCICTL1B");
GEL_WatchAdd("*0x7752,x","SCIHBAUDB");
GEL_WatchAdd("*0x7753,x","SCILBAUDB");
GEL_WatchAdd("*0x7754,x","SCICTL2B");
GEL_WatchAdd("*0x7755,x","SCIRXSTB");
GEL_WatchAdd("*0x7756,x","SCIRXEMUB");
GEL_WatchAdd("*0x7757,x","SCIRXBUFB");
GEL_WatchAdd("*0x7759,x","SCITXBUFB");
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
GEL_WatchAdd("*0x775F,x","SCIPRIB");
}
hotmenu SCI_B_FIFO_Registers()
{
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
}
/********************************************************************/
/* Serial Peripheral Interface Registers */
/********************************************************************/
menuitem "Watch SPI Registers";
hotmenu SPI_A_All_Regs()
{
GEL_WatchAdd("*0x7040,x","SPIA SPICCR");
GEL_WatchAdd("*0x7041,x","SPIA SPICTL");
GEL_WatchAdd("*0x7042,x","SPIA SPIST");
GEL_WatchAdd("*0x7044,x","SPIA SPIBRR");
GEL_WatchAdd("*0x7046,x","SPIA SPIEMU");
GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF");
GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF");
GEL_WatchAdd("*0x7049,x","SPIA SPIDAT");
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
GEL_WatchAdd("*0x704F,x","SPIA SPIPRI");
}
hotmenu SPI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
}
/********************************************************************/
/* Watchdog Timer Registers */
/********************************************************************/
menuitem "Watch Watchdog Timer Registers";
hotmenu All_Watchdog_Regs()
{
GEL_WatchAdd("*0x7023,x","WDCNTR");
GEL_WatchAdd("*0x7025,x","WDKEY");
GEL_WatchAdd("*0x7029,x","WDCR");
GEL_WatchAdd("*0x7022,x","SCSR");
}
/********************************************************************/
/*** End of file ***/

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v120/DSP2833x_common/gel/f28334.gel Normal file
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/********************************************************************/
/* f28334.gel */
/* Version 3.30.2 */
/* */
/* This GEL file is to be used with the TMS320F28334 DSP. */
/* Changes may be required to support specific hardware designs. */
/* */
/* Code Composer Studio supports six reserved GEL functions that */
/* automatically get executed if they are defined. They are: */
/* */
/* StartUp() - Executed whenever CCS is invoked */
/* OnReset() - Executed after Debug->Reset CPU */
/* OnRestart() - Executed after Debug->Restart */
/* OnPreFileLoaded() - Executed before File->Load Program */
/* OnFileLoaded() - Executed after File->Load Program */
/* OnTargetConnect() - Executed after Debug->Connect */
/* */
/********************************************************************/
StartUp()
{
/* The next line automatically loads the .gel file that comes */
/* with the DSP2833x Peripheral Header Files download. To use, */
/* uncomment, and adjust the directory path as needed. */
// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel");
}
OnReset(int nErrorCode)
{
C28x_Mode();
Unlock_CSM();
ADC_Cal();
}
OnRestart(int nErrorCode)
{
/* CCS will call OnRestart() when you do a Debug->Restart and */
/* after you load a new file. Between running interrupt based */
/* programs, this function will clear interrupts and help keep */
/* the processor from going off into invalid memory. */
C28x_Mode();
IER = 0;
IFR = 0;
ADC_Cal();
}
int TxtOutCtl=0;
OnPreFileLoaded()
{
XINTF_Enable();
if (TxtOutCtl==0)
{
GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use.");
GEL_TextOut("\nFPU Registers can be found via GEL->Watch FPU Registers.");
TxtOutCtl=1;
}
}
OnFileLoaded(int nErrorCode, int bSymbolsOnly)
{
ADC_Cal();
}
OnTargetConnect()
{
C28x_Mode();
F28334_Memory_Map(); /* Initialize the CCS memory map */
/* Check to see if CCS has been started-up with the DSP already */
/* running in real-time mode. The user can add whatever */
/* custom initialization stuff they want to each case. */
if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */
{
}
else /* Do stop-mode target initialization */
{
GEL_Reset(); /* Reset DSP */
}
}
/********************************************************************/
/* These functions are launched by the GEL_Toolbar button plugin */
/********************************************************************/
GEL_Toolbar1()
{
Run_Realtime_with_Reset();
}
GEL_Toolbar2()
{
Run_Realtime_with_Restart();
}
GEL_Toolbar3()
{
Full_Halt();
}
GEL_Toolbar4()
{
Full_Halt_with_Reset();
}
int GEL_Toolbar5_Toggle = 0;
GEL_Toolbar5()
{
if(GEL_Toolbar5_Toggle == 0)
{
GEL_Toolbar5_Toggle = 1;
GEL_OpenWindow("GEL_Buttons",1,4);
GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0);
GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1);
GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2);
GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3);
}
else
{
GEL_Toolbar5_Toggle = 0;
GEL_CloseWindow("GEL_Buttons");
}
}
/********************************************************************/
/* These functions are useful to engage/dis-enagage realtime */
/* emulation mode during debug. They save the user from having to */
/* manually perform these steps in CCS. */
/********************************************************************/
menuitem "Realtime Emulation Control";
hotmenu Run_Realtime_with_Reset()
{
GEL_Reset(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Run_Realtime_with_Restart()
{
GEL_Restart(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Full_Halt()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
}
hotmenu Full_Halt_with_Reset()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
GEL_Reset(); /* Reset the DSP */
}
/********************************************************************/
/* F28334 Memory Map */
/* */
/* Note: M0M1MAP and VMAP signals tied high on F28334 core */
/* */
/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */
/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */
/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */
/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */
/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */
/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */
/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */
/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */
/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */
/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */
/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */
/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */
/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */
/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */
/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */
/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */
/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data) */
/* 0x320000 - 0x33ffff Flash (Prog and Data) */
/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */
/* 0x380090 - 0x380090 PARTID value (Prog and Data) */
/* 0x380400 - 0x3807ff OTP (Prog and Data) */
/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */
/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */
/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */
/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */
/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */
/********************************************************************/
menuitem "Initialize Memory Map";
hotmenu F28334_Memory_Map()
{
GEL_MapReset();
GEL_MapOn();
/* Program memory map */
GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */
GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */
GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x320000,0,0x20000,1,0); /* FLASH */
GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */
GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */
/* Data memory map */
GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */
GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */
GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */
GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */
GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */
GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */
GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x320000,1,0x20000,1,0); /* FLASH */
GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */
GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */
}
/********************************************************************/
/* The ESTOP0 fill functions are useful for debug. They fill the */
/* RAM with software breakpoints that will trap runaway code. */
/********************************************************************/
hotmenu Fill_F28334_RAM_with_ESTOP0()
{
GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */
GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */
GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */
GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */
GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */
}
/********************************************************************/
menuitem "Watchdog";
hotmenu Disable_WD()
{
*0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */
*0x7025 = 0x0055; /* Service the WD */
*0x7025 = 0x00AA; /* once to be safe. */
GEL_TextOut("\nWatchdog Timer Disabled");
}
/********************************************************************/
menuitem "Code Security Module"
hotmenu Unlock_CSM()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
/* Write passwords to the KEY registers. 0xFFFF's are dummy passwords.
User should replace them with the correct password for their DSP */
*0xAE0 = 0xFFFF;
*0xAE1 = 0xFFFF;
*0xAE2 = 0xFFFF;
*0xAE3 = 0xFFFF;
*0xAE4 = 0xFFFF;
*0xAE5 = 0xFFFF;
*0xAE6 = 0xFFFF;
*0xAE7 = 0xFFFF;
}
/********************************************************************/
menuitem "Addressing Modes";
hotmenu C28x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C24x_Mode()
{
ST1 = ST1 | 0x0100; /* AMODE = 1 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C27x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */
}
/********************************************************************/
/* PLL Ratios */
/* */
/* The following table describes the PLL clocking ratios (0..10) */
/* */
/* Ratio CLKIN Description */
/* ----- -------------- ------------ */
/* 0 OSCCLK/2 PLL bypassed */
/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */
/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */
/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */
/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */
/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */
/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */
/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */
/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */
/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */
/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */
/********************************************************************/
menuitem "Set PLL Ratio";
hotmenu Bypass()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */
PLL_Wait();
}
hotmenu OSCCLK_x1_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x2_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x3_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x4_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x5_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x6_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x7_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x8_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x9_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x10_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */
PLL_Wait();
}
// hotmenu OSCCLK_x1_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x2_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x3_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x4_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x5_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x6_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x7_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x8_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x9_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x10_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */
// PLL_Wait();
// }
/********************************************************************/
/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */
/********************************************************************/
DIVSEL_div2()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
temp = *PLLSTS;
temp &= 0xFE7F; /* Clear bits 7 & 8 */
temp |= 2 << 7; /* Set bit 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
/********************************************************************/
/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to /1 */
/********************************************************************/
DIVSEL_div1()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */
wait();
temp = *PLLSTS;
temp |= 3 << 7; /* Set bits 7 & 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
wait()
{
int delay = 0;
for (delay = 0; delay <= 5; delay ++)
{}
}
/********************************************************************/
/* For F2833x devices, check the PLLOCKS bit for PLL lock. */
/********************************************************************/
PLL_Wait()
{
int PLLSTS;
int delay = 0;
PLLSTS = 0x7011;
while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001)
{
delay++;
GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
/********************************************************************/
/* Load the ADC Calibration values from TI OTP */
/********************************************************************/
menuitem "ADC Calibration"
hotmenu ADC_Cal()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
if(((*0x0AEF) & 0x0001) == 0)
{
XAR0 = *0x701C;
*0x701C |= 0x0008;
*0x711C = *0x380083;
*0x711D = *0x380085;
*0x701C = XAR0;
XAR0 = 0;
}
else
{
GEL_TextOut("\nADC Calibration not complete, device is secure");
}
}
/********************************************************************/
/* Enable the XINTF and configure GPIOs for XINTF function */
/********************************************************************/
menuitem "XINTF Enable"
hotmenu XINTF_Enable()
{
/* enable XINTF clock (XTIMCLK) */
*0x7020 = 0x3700;
/* GPBMUX1: XA0-XA7, XA16, XZCS0, */
/* XZCS7, XREADY, XRNW, XWE0 */
/* GPAMUX2: XA17-XA19, XZCS6 */
/* GPCMUX2: XA8-XA15 */
/* GPCMUX1: XD0-XD15 */
*(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */
*(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */
*(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */
*(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */
/* Uncomment for x32 data bus */
/* GPBMUX2: XD16-XD31 */
// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */
/* Zone timing.
/* Each zone can be configured seperately */
/* Uncomment the x16 or the x32 timing */
/* depending on the data bus width for */
/* the zone */
/* x16 Timing */
*(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */
*(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */
*(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */
/* x32 Timing:
// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */
}
/********************************************************************/
/* The below are used to display the symbolic names of the F28334 */
/* memory mapped registers in the watch window. To view these */
/* registers, click on the GEL menu button in Code Composer Studio, */
/* then select which registers or groups of registers you want to */
/* view. They will appear in the watch window under the Watch1 tab. */
/********************************************************************/
/* Add a space line to the GEL menu */
menuitem "______________________________________";
hotmenu __() {}
/********************************************************************/
/* A/D Converter Registers */
/********************************************************************/
menuitem "Watch ADC Registers";
hotmenu All_ADC_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
hotmenu ADC_Control_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
}
hotmenu ADCCHSELSEQx_Regs()
{
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
}
hotmenu ADCRESULT_0_to_7()
{
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
}
hotmenu ADCRESULT_8_to_15()
{
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
}
hotmenu ADCRESULT_Mirror_0_to_7()
{
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
}
hotmenu ADCRESULT_Mirror_8_to_15()
{
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
/********************************************************************/
/* Clocking and Low-Power Registers */
/********************************************************************/
menuitem "Watch Clocking and Low-Power Registers";
hotmenu All_Clocking_and_Low_Power_Regs()
{
GEL_WatchAdd("*0x7010,x","XCLK");
GEL_WatchAdd("*0x7011,x","PLLSTS");
GEL_WatchAdd("*0x701A,x","HISPCP");
GEL_WatchAdd("*0x701B,x","LOSPCP");
GEL_WatchAdd("*0x701C,x","PCLKCR0");
GEL_WatchAdd("*0x701D,x","PCLKCR1");
GEL_WatchAdd("*0x701E,x","LPMCR0");
GEL_WatchAdd("*0x7020,x","PCLKCR3");
GEL_WatchAdd("*0x7021,x","PLLCR");
}
/********************************************************************/
/* Code Security Module Registers */
/********************************************************************/
menuitem "Watch Code Security Module Registers";
hotmenu CSMSCR()
{
GEL_WatchAdd("*0x0AEF,x","CSMSCR");
GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit");
GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit");
}
hotmenu PWL_Locations()
{
GEL_WatchAdd("*0x33FFF8,x","PWL0");
GEL_WatchAdd("*0x33FFF9,x","PWL1");
GEL_WatchAdd("*0x33FFFA,x","PWL2");
GEL_WatchAdd("*0x33FFFB,x","PWL3");
GEL_WatchAdd("*0x33FFFC,x","PWL4");
GEL_WatchAdd("*0x33FFFD,x","PWL5");
GEL_WatchAdd("*0x33FFFE,x","PWL6");
GEL_WatchAdd("*0x33FFFF,x","PWL7");
}
/********************************************************************/
/* CPU Timer Registers */
/********************************************************************/
menuitem "Watch CPU Timer Registers";
hotmenu All_CPU_Timer0_Regs()
{
GEL_WatchAdd("*0x0C00,x","TIMER0TIM");
GEL_WatchAdd("*0x0C01,x","TIMER0TIMH");
GEL_WatchAdd("*0x0C02,x","TIMER0PRD");
GEL_WatchAdd("*0x0C03,x","TIMER0PRDH");
GEL_WatchAdd("*0x0C04,x","TIMER0TCR");
GEL_WatchAdd("*0x0C06,x","TIMER0TPR");
GEL_WatchAdd("*0x0C07,x","TIMER0TPRH");
}
hotmenu All_CPU_Timer1_Regs()
{
GEL_WatchAdd("*0x0C08,x","TIMER1TIM");
GEL_WatchAdd("*0x0C09,x","TIMER1TIMH");
GEL_WatchAdd("*0x0C0A,x","TIMER1PRD");
GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH");
GEL_WatchAdd("*0x0C0C,x","TIMER1TCR");
GEL_WatchAdd("*0x0C0E,x","TIMER1TPR");
GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH");
}
hotmenu All_CPU_Timer2_Regs()
{
GEL_WatchAdd("*0x0C10,x","TIMER2TIM");
GEL_WatchAdd("*0x0C11,x","TIMER2TIMH");
GEL_WatchAdd("*0x0C12,x","TIMER2PRD");
GEL_WatchAdd("*0x0C13,x","TIMER2PRDH");
GEL_WatchAdd("*0x0C14,x","TIMER2TCR");
GEL_WatchAdd("*0x0C16,x","TIMER2TPR");
GEL_WatchAdd("*0x0C17,x","TIMER2TPRH");
}
/********************************************************************/
/* Device Emulation Registers */
/********************************************************************/
menuitem "Watch Device Emulation Registers";
hotmenu All_Emulation_Regs()
{
GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF");
GEL_WatchAdd("*0x0882,x","CLASSID");
GEL_WatchAdd("*0x0883,x","REVID");
GEL_WatchAdd("*0x0884,x","PROTSTART");
GEL_WatchAdd("*0x0885,x","PROTRANGE");
GEL_WatchAdd("*0x380090,x","PARTID");
}
/********************************************************************/
/* DMA Registers */
/********************************************************************/
menuitem "Watch DMA Registers";
hotmenu All_DMA_Regs()
{
GEL_WatchAdd("*0x1000,x","DMACTRL");
GEL_WatchAdd("*0x1001,x","DEBUGCTRL");
GEL_WatchAdd("*0x1002,x","REVISION");
GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1");
GEL_WatchAdd("*0x1006,x","PRIORITYSTAT");
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_1_regs()
{
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_2_regs()
{
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_3_regs()
{
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_4_regs()
{
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_5_regs()
{
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_6_regs()
{
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
/********************************************************************/
/* eCAN Registers */
/********************************************************************/
menuitem "Watch eCAN Registers";
hotmenu eCAN_A_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME");
GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD");
GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS");
GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR");
GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA");
GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA");
GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP");
GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML");
GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP");
GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC");
GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC");
GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES");
GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC");
GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC");
GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0");
GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM");
GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1");
GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM");
GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL");
GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC");
GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC");
GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC");
GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT");
GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC");
GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS");
}
hotmenu eCAN_A_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0");
GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0");
GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0");
GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0");
GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0");
GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0");
GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0");
GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1");
GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1");
GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1");
GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1");
GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1");
GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1");
GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1");
}
hotmenu eCAN_A_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2");
GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2");
GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2");
GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2");
GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2");
GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2");
GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2");
GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3");
GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3");
GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3");
GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3");
GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3");
GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3");
GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3");
}
hotmenu eCAN_A_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4");
GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4");
GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4");
GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4");
GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4");
GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4");
GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4");
GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5");
GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5");
GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5");
GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5");
GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5");
GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5");
GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5");
}
hotmenu eCAN_A_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6");
GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6");
GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6");
GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6");
GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6");
GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6");
GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6");
GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7");
GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7");
GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7");
GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7");
GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7");
GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7");
GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7");
}
hotmenu eCAN_A_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8");
GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8");
GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8");
GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8");
GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8");
GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8");
GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8");
GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9");
GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9");
GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9");
GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9");
GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9");
GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9");
GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9");
}
hotmenu eCAN_A_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10");
GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10");
GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10");
GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10");
GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10");
GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10");
GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10");
GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11");
GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11");
GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11");
GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11");
GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11");
GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11");
GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11");
}
hotmenu eCAN_A_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12");
GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12");
GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12");
GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12");
GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12");
GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12");
GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12");
GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13");
GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13");
GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13");
GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13");
GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13");
GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13");
GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13");
}
hotmenu eCAN_A_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14");
GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14");
GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14");
GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14");
GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14");
GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14");
GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14");
GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15");
GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15");
GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15");
GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15");
GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15");
GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15");
GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15");
}
hotmenu eCAN_A_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16");
GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16");
GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16");
GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16");
GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16");
GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16");
GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16");
GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17");
GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17");
GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17");
GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17");
GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17");
GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17");
GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17");
}
hotmenu eCAN_A_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18");
GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18");
GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18");
GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18");
GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18");
GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18");
GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18");
GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19");
GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19");
GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19");
GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19");
GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19");
GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19");
GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19");
}
hotmenu eCAN_A_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20");
GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20");
GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20");
GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20");
GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20");
GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20");
GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20");
GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21");
GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21");
GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21");
GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21");
GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21");
GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21");
GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21");
}
hotmenu eCAN_A_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22");
GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22");
GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22");
GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22");
GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22");
GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22");
GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22");
GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23");
GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23");
GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23");
GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23");
GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23");
GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23");
GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23");
}
hotmenu eCAN_A_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24");
GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24");
GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24");
GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24");
GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24");
GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24");
GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24");
GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25");
GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25");
GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25");
GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25");
GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25");
GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25");
GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25");
}
hotmenu eCAN_A_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26");
GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26");
GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26");
GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26");
GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26");
GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26");
GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26");
GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27");
GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27");
GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27");
GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27");
GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27");
GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27");
GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27");
}
hotmenu eCAN_A_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28");
GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28");
GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28");
GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28");
GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28");
GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28");
GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28");
GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29");
GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29");
GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29");
GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29");
GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29");
GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29");
GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29");
}
hotmenu eCAN_A_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30");
GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30");
GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30");
GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30");
GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30");
GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30");
GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30");
GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31");
GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31");
GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31");
GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31");
GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31");
GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31");
GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31");
}
hotmenu eCAN_B_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME");
GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD");
GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS");
GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR");
GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA");
GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA");
GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP");
GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML");
GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP");
GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC");
GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC");
GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES");
GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC");
GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC");
GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0");
GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM");
GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1");
GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM");
GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL");
GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC");
GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC");
GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC");
GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT");
GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC");
GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS");
}
hotmenu eCAN_B_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0");
GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0");
GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0");
GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0");
GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0");
GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0");
GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0");
GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1");
GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1");
GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1");
GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1");
GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1");
GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1");
GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1");
}
hotmenu eCAN_B_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2");
GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2");
GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2");
GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2");
GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2");
GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2");
GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2");
GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3");
GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3");
GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3");
GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3");
GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3");
GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3");
GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3");
}
hotmenu eCAN_B_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4");
GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4");
GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4");
GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4");
GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4");
GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4");
GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4");
GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5");
GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5");
GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5");
GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5");
GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5");
GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5");
GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5");
}
hotmenu eCAN_B_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6");
GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6");
GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6");
GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6");
GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6");
GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6");
GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6");
GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7");
GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7");
GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7");
GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7");
GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7");
GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7");
GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7");
}
hotmenu eCAN_B_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8");
GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8");
GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8");
GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8");
GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8");
GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8");
GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8");
GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9");
GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9");
GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9");
GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9");
GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9");
GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9");
GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9");
}
hotmenu eCAN_B_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10");
GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10");
GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10");
GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10");
GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10");
GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10");
GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10");
GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11");
GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11");
GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11");
GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11");
GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11");
GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11");
GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11");
}
hotmenu eCAN_B_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12");
GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12");
GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12");
GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12");
GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12");
GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12");
GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12");
GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13");
GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13");
GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13");
GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13");
GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13");
GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13");
GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13");
}
hotmenu eCAN_B_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14");
GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14");
GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14");
GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14");
GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14");
GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14");
GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14");
GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15");
GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15");
GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15");
GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15");
GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15");
GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15");
GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15");
}
hotmenu eCAN_B_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16");
GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16");
GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16");
GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16");
GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16");
GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16");
GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16");
GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17");
GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17");
GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17");
GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17");
GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17");
GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17");
GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17");
}
hotmenu eCAN_B_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18");
GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18");
GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18");
GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18");
GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18");
GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18");
GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18");
GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19");
GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19");
GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19");
GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19");
GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19");
GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19");
GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19");
}
hotmenu eCAN_B_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20");
GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20");
GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20");
GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20");
GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20");
GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20");
GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20");
GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21");
GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21");
GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21");
GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21");
GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21");
GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21");
GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21");
}
hotmenu eCAN_B_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22");
GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22");
GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22");
GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22");
GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22");
GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22");
GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22");
GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23");
GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23");
GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23");
GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23");
GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23");
GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23");
GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23");
}
hotmenu eCAN_B_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24");
GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24");
GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24");
GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24");
GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24");
GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24");
GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24");
GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25");
GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25");
GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25");
GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25");
GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25");
GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25");
GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25");
}
hotmenu eCAN_B_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26");
GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26");
GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26");
GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26");
GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26");
GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26");
GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26");
GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27");
GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27");
GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27");
GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27");
GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27");
GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27");
GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27");
}
hotmenu eCAN_B_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28");
GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28");
GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28");
GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28");
GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28");
GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28");
GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28");
GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29");
GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29");
GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29");
GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29");
GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29");
GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29");
GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29");
}
hotmenu eCAN_B_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30");
GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30");
GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30");
GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30");
GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30");
GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30");
GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30");
GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31");
GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31");
GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31");
GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31");
GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31");
GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31");
GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31");
}
/********************************************************************/
/* Enhanced Capture Registers */
/********************************************************************/
menuitem "Watch eCAP Registers";
hotmenu eCAP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT");
GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS");
GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1");
GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2");
GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3");
GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4");
GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1");
GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2");
GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT");
GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG");
GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR");
GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC");
}
hotmenu eCAP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT");
GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS");
GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1");
GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2");
GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3");
GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4");
GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1");
GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2");
GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT");
GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG");
GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR");
GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC");
}
hotmenu eCAP3_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT");
GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS");
GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1");
GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2");
GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3");
GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4");
GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1");
GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2");
GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT");
GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG");
GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR");
GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC");
}
hotmenu eCAP4_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT");
GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS");
GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1");
GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2");
GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3");
GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4");
GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1");
GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2");
GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT");
GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG");
GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR");
GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC");
}
hotmenu eCAP5_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT");
GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS");
GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1");
GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2");
GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3");
GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4");
GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1");
GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2");
GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT");
GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG");
GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR");
GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC");
}
hotmenu eCAP6_All_Regs()
{
GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT");
GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS");
GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1");
GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2");
GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3");
GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4");
GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1");
GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2");
GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT");
GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG");
GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR");
GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC");
}
/********************************************************************/
/* Enhanced PWM Registers */
/********************************************************************/
menuitem "Watch ePWM Registers";
hotmenu ePWM1_All_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL");
GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG");
}
hotmenu ePWM1_TB_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
}
hotmenu ePWM1_CMP_Regs()
{
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
}
hotmenu ePWM1_AQ_Regs()
{
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
}
hotmenu ePWM1_DB_Regs()
{
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
}
hotmenu ePWM1_TZ_Regs()
{
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
}
hotmenu ePWM1_ET_Regs()
{
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
}
hotmenu ePWM2_All_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL");
GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG");
}
hotmenu ePWM2_TB_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
}
hotmenu ePWM2_CMP_Regs()
{
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
}
hotmenu ePWM2_AQ_Regs()
{
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
}
hotmenu ePWM2_DB_Regs()
{
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
}
hotmenu ePWM2_TZ_Regs()
{
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
}
hotmenu ePWM2_ET_Regs()
{
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
}
hotmenu ePWM3_All_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL");
GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG");
}
hotmenu ePWM3_TB_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
}
hotmenu ePWM3_CMP_Regs()
{
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
}
hotmenu ePWM3_AQ_Regs()
{
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
}
hotmenu ePWM3_DB_Regs()
{
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
}
hotmenu ePWM3_TZ_Regs()
{
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
}
hotmenu ePWM3_ET_Regs()
{
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
}
hotmenu ePWM4_All_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL");
GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG");
}
hotmenu ePWM4_TB_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
}
hotmenu ePWM4_CMP_Regs()
{
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
}
hotmenu ePWM4_AQ_Regs()
{
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
}
hotmenu ePWM4_DB_Regs()
{
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
}
hotmenu ePWM4_TZ_Regs()
{
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
}
hotmenu ePWM4_ET_Regs()
{
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
}
hotmenu ePWM5_All_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL");
GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG");
}
hotmenu ePWM5_TB_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
}
hotmenu ePWM5_CMP_Regs()
{
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
}
hotmenu ePWM5_AQ_Regs()
{
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
}
hotmenu ePWM5_DB_Regs()
{
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
}
hotmenu ePWM5_TZ_Regs()
{
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
}
hotmenu ePWM5_ET_Regs()
{
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
}
hotmenu ePWM6_All_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL");
GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG");
}
hotmenu ePWM6_TB_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
}
hotmenu ePWM6_CMP_Regs()
{
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
}
hotmenu ePWM6_AQ_Regs()
{
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
}
hotmenu ePWM6_DB_Regs()
{
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
}
hotmenu ePWM6_TZ_Regs()
{
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
}
hotmenu ePWM6_ET_Regs()
{
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
}
/********************************************************************/
/* Enhanced EQEP Registers */
/********************************************************************/
menuitem "Watch eQEP"
hotmenu eQEP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT");
GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR");
GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD");
GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR");
GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD");
GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL");
GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL");
GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL");
GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL");
GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT");
GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG");
GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR");
GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC");
GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS");
GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR");
GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD");
GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT");
GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT");
}
hotmenu eQEP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT");
GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR");
GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD");
GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR");
GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD");
GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL");
GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL");
GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL");
GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL");
GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT");
GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG");
GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR");
GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC");
GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS");
GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR");
GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD");
GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT");
GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT");
}
/********************************************************************/
/* External Interface Registers */
/********************************************************************/
menuitem "Watch External Interface Registers";
hotmenu All_External_Interface_Regs()
{
GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0");
GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6");
GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7");
GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2");
GEL_WatchAdd("*0x0B38,x","XBANK");
GEL_WatchAdd("*0x0B3A,x","XREVISION");
GEL_WatchAdd("*0x0B3D,x","XRESET");
}
/********************************************************************/
/* External Interrupt Registers */
/********************************************************************/
menuitem "Watch External Interrupt Registers";
hotmenu All_XINT_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
hotmenu XINT_Control_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
}
hotmenu XINT_Counter_Regs()
{
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
/********************************************************************/
/* FPU Registers */
/********************************************************************/
menuitem "Watch FPU Registers"
hotmenu All_FPU_Single_Precision_Regs()
{
GEL_WatchAdd("RB");
GEL_WatchAdd("STF");
GEL_WatchAdd("R0H");
GEL_WatchAdd("R1H");
GEL_WatchAdd("R2H");
GEL_WatchAdd("R3H");
GEL_WatchAdd("R4H");
GEL_WatchAdd("R5H");
GEL_WatchAdd("R6H");
GEL_WatchAdd("R7H");
}
/********************************************************************/
/* GPIO Registers */
/********************************************************************/
menuitem "Watch GPIO Registers";
hotmenu All_GPIO_CONTROL_Regs()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
}
hotmenu All_GPIO_DATA_Regs()
{
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
hotmenu All_GPIO_INTERRUPT_Regs()
{
GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL");
GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL");
GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL");
GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL");
GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL");
GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL");
GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL");
GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL");
GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL");
}
hotmenu All_GPA_Registers()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
}
hotmenu All_GPB_Registers()
{
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
}
hotmenu All_GPC_Registers()
{
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
/********************************************************************/
/* Multichannel Serial Port Registers */
/********************************************************************/
menuitem "Watch McBSP Registers";
hotmenu All_McBSP_A_Regs()
{
GEL_WatchAdd("*0x5000,x","McBSPA DRR2");
GEL_WatchAdd("*0x5001,x","McBSPA DRR1");
GEL_WatchAdd("*0x5002,x","McBSPA DXR2");
GEL_WatchAdd("*0x5003,x","McBSPA DXR1");
GEL_WatchAdd("*0x5004,x","McBSPA SPCR2");
GEL_WatchAdd("*0x5005,x","McBSPA SPCR1");
GEL_WatchAdd("*0x5006,x","McBSPA RCR2");
GEL_WatchAdd("*0x5007,x","McBSPA RCR1");
GEL_WatchAdd("*0x5008,x","McBSPA XCR2");
GEL_WatchAdd("*0x5009,x","McBSPA XCR1");
GEL_WatchAdd("*0x500A,x","McBSPA SRGR2");
GEL_WatchAdd("*0x500B,x","McBSPA SRGR1");
GEL_WatchAdd("*0x500C,x","McBSPA MCR2");
GEL_WatchAdd("*0x500D,x","McBSPA MCR1");
GEL_WatchAdd("*0x500E,x","McBSPA RCERA");
GEL_WatchAdd("*0x500F,x","McBSPA RCERB");
GEL_WatchAdd("*0x5010,x","McBSPA XCERA");
GEL_WatchAdd("*0x5011,x","McBSPA XCERB");
GEL_WatchAdd("*0x5012,x","McBSPA PCR1");
GEL_WatchAdd("*0x5013,x","McBSPA RCERC");
GEL_WatchAdd("*0x5014,x","McBSPA RCERD");
GEL_WatchAdd("*0x5015,x","McBSPA XCERC");
GEL_WatchAdd("*0x5016,x","McBSPA XCERD");
GEL_WatchAdd("*0x5017,x","McBSPA RCERE");
GEL_WatchAdd("*0x5018,x","McBSPA RCERF");
GEL_WatchAdd("*0x5019,x","McBSPA XCERE");
GEL_WatchAdd("*0x501A,x","McBSPA XCERF");
GEL_WatchAdd("*0x501B,x","McBSPA RCERG");
GEL_WatchAdd("*0x501C,x","McBSPA RCERH");
GEL_WatchAdd("*0x501D,x","McBSPA XCERG");
GEL_WatchAdd("*0x501E,x","McBSPA XCERH");
GEL_WatchAdd("*0x5023,x","McBSPA MFFINT");
GEL_WatchAdd("*0x503F,x","McBSPA Revision");
}
hotmenu All_McBSP_B_Regs()
{
GEL_WatchAdd("*0x5040,x","McBSPB DRR2");
GEL_WatchAdd("*0x5041,x","McBSPB DRR1");
GEL_WatchAdd("*0x5042,x","McBSPB DXR2");
GEL_WatchAdd("*0x5043,x","McBSPB DXR1");
GEL_WatchAdd("*0x5044,x","McBSPB SPCR2");
GEL_WatchAdd("*0x5045,x","McBSPB SPCR1");
GEL_WatchAdd("*0x5046,x","McBSPB RCR2");
GEL_WatchAdd("*0x5047,x","McBSPB RCR1");
GEL_WatchAdd("*0x5048,x","McBSPB XCR2");
GEL_WatchAdd("*0x5049,x","McBSPB XCR1");
GEL_WatchAdd("*0x504A,x","McBSPB SRGR2");
GEL_WatchAdd("*0x504B,x","McBSPB SRGR1");
GEL_WatchAdd("*0x504C,x","McBSPB MCR2");
GEL_WatchAdd("*0x504D,x","McBSPB MCR1");
GEL_WatchAdd("*0x504E,x","McBSPB RCERA");
GEL_WatchAdd("*0x504F,x","McBSPB RCERB");
GEL_WatchAdd("*0x5050,x","McBSPB XCERA");
GEL_WatchAdd("*0x5051,x","McBSPB XCERB");
GEL_WatchAdd("*0x5052,x","McBSPB PCR1");
GEL_WatchAdd("*0x5053,x","McBSPB RCERC");
GEL_WatchAdd("*0x5054,x","McBSPB RCERD");
GEL_WatchAdd("*0x5055,x","McBSPB XCERC");
GEL_WatchAdd("*0x5056,x","McBSPB XCERD");
GEL_WatchAdd("*0x5057,x","McBSPB RCERE");
GEL_WatchAdd("*0x5058,x","McBSPB RCERF");
GEL_WatchAdd("*0x5059,x","McBSPB XCERE");
GEL_WatchAdd("*0x505A,x","McBSPB XCERF");
GEL_WatchAdd("*0x505B,x","McBSPB RCERG");
GEL_WatchAdd("*0x505C,x","McBSPB RCERH");
GEL_WatchAdd("*0x505D,x","McBSPB XCERG");
GEL_WatchAdd("*0x505E,x","McBSPB XCERH");
GEL_WatchAdd("*0x5063,x","McBSPB MFFINT");
GEL_WatchAdd("*0x506F,x","McBSPB Revision");
}
/********************************************************************/
/* I2C Registers */
/********************************************************************/
menuitem "Watch I2C Registers";
hotmenu All_I2C_Regs()
{
GEL_WatchAdd("*0x7900,x","I2COAR");
GEL_WatchAdd("*0x7901,x","I2CIER");
GEL_WatchAdd("*0x7902,x","I2CSTR");
GEL_WatchAdd("*0x7903,x","I2CCLKL");
GEL_WatchAdd("*0x7904,x","I2CCLKH");
GEL_WatchAdd("*0x7905,x","I2CCNT");
GEL_WatchAdd("*0x7906,x","I2CDRR");
GEL_WatchAdd("*0x7907,x","I2CSAR");
GEL_WatchAdd("*0x7908,x","I2CDXR");
GEL_WatchAdd("*0x7909,x","I2CMDR");
GEL_WatchAdd("*0x790A,x","I2CISRC");
GEL_WatchAdd("*0x790C,x","I2CPSC");
GEL_WatchAdd("*0x7920,x","I2CFFTX");
GEL_WatchAdd("*0x7921,x","I2CFFRX");
}
/********************************************************************/
/* Peripheral Interrupt Expansion Registers */
/********************************************************************/
menuitem "Watch Peripheral Interrupt Expansion Registers";
hotmenu All_PIE_Regs()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
GEL_WatchAdd("*0x0CE1,x","PIEACK");
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
hotmenu PIECTRL()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
}
hotmenu PIEACK()
{
GEL_WatchAdd("*0x0CE1,x","PIEACK");
}
hotmenu PIEIER1_and_PIEIFR1()
{
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
}
hotmenu PIEIER2_and_PIEIFR2()
{
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
}
hotmenu PIEIER3_and_PIEIFR3()
{
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
}
hotmenu PIEIER4_and_PIEIFR4()
{
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
}
hotmenu PIEIER5_and_PIEIFR5()
{
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
}
hotmenu PIEIER6_and_PIEIFR6()
{
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
}
hotmenu PIEIER7_and_PIEIFR7()
{
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
}
hotmenu PIEIER8_and_PIEIFR8()
{
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
}
hotmenu PIEIER9_and_PIEIFR9()
{
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
}
hotmenu PIEIFR10_and_PIEIFR10()
{
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
}
hotmenu PIEIER11_and_PIEIFR11()
{
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
}
hotmenu PIEIER12_and_PIEIFR12()
{
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
/********************************************************************/
/* Serial Communication Interface Registers */
/********************************************************************/
menuitem "Watch SCI Registers";
hotmenu SCI_A_All_Regs()
{
GEL_WatchAdd("*0x7050,x","SCICCRA");
GEL_WatchAdd("*0x7051,x","SCICTL1A");
GEL_WatchAdd("*0x7052,x","SCIHBAUDA");
GEL_WatchAdd("*0x7053,x","SCILBAUDA");
GEL_WatchAdd("*0x7054,x","SCICTL2A");
GEL_WatchAdd("*0x7055,x","SCIRXSTA");
GEL_WatchAdd("*0x7056,x","SCIRXEMUA");
GEL_WatchAdd("*0x7057,x","SCIRXBUFA");
GEL_WatchAdd("*0x7059,x","SCITXBUFA");
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
GEL_WatchAdd("*0x705F,x","SCIPRIA");
}
hotmenu SCI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
}
hotmenu SCI_B_All_Regs()
{
GEL_WatchAdd("*0x7750,x","SCICCRB");
GEL_WatchAdd("*0x7751,x","SCICTL1B");
GEL_WatchAdd("*0x7752,x","SCIHBAUDB");
GEL_WatchAdd("*0x7753,x","SCILBAUDB");
GEL_WatchAdd("*0x7754,x","SCICTL2B");
GEL_WatchAdd("*0x7755,x","SCIRXSTB");
GEL_WatchAdd("*0x7756,x","SCIRXEMUB");
GEL_WatchAdd("*0x7757,x","SCIRXBUFB");
GEL_WatchAdd("*0x7759,x","SCITXBUFB");
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
GEL_WatchAdd("*0x775F,x","SCIPRIB");
}
hotmenu SCI_B_FIFO_Registers()
{
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
}
hotmenu SCI_C_All_Regs()
{
GEL_WatchAdd("*0x7770,x","SCICCRC");
GEL_WatchAdd("*0x7771,x","SCICTL1C");
GEL_WatchAdd("*0x7772,x","SCIHBAUDC");
GEL_WatchAdd("*0x7773,x","SCILBAUDC");
GEL_WatchAdd("*0x7774,x","SCICTL2C");
GEL_WatchAdd("*0x7775,x","SCIRXSTC");
GEL_WatchAdd("*0x7776,x","SCIRXEMUC");
GEL_WatchAdd("*0x7777,x","SCIRXBUFC");
GEL_WatchAdd("*0x7779,x","SCITXBUFC");
GEL_WatchAdd("*0x777A,x","SCIFFTXC");
GEL_WatchAdd("*0x777B,x","SCIFFRXC");
GEL_WatchAdd("*0x777C,x","SCIFFCTC");
GEL_WatchAdd("*0x777F,x","SCIPRIC");
}
hotmenu SCI_C_FIFO_Registers()
{
GEL_WatchAdd("*0x777A,x","SCIFFTXC");
GEL_WatchAdd("*0x777B,x","SCIFFRXC");
GEL_WatchAdd("*0x777C,x","SCIFFCTC");
}
/********************************************************************/
/* Serial Peripheral Interface Registers */
/********************************************************************/
menuitem "Watch SPI Registers";
hotmenu SPI_A_All_Regs()
{
GEL_WatchAdd("*0x7040,x","SPIA SPICCR");
GEL_WatchAdd("*0x7041,x","SPIA SPICTL");
GEL_WatchAdd("*0x7042,x","SPIA SPIST");
GEL_WatchAdd("*0x7044,x","SPIA SPIBRR");
GEL_WatchAdd("*0x7046,x","SPIA SPIEMU");
GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF");
GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF");
GEL_WatchAdd("*0x7049,x","SPIA SPIDAT");
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
GEL_WatchAdd("*0x704F,x","SPIA SPIPRI");
}
hotmenu SPI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
}
/********************************************************************/
/* Watchdog Timer Registers */
/********************************************************************/
menuitem "Watch Watchdog Timer Registers";
hotmenu All_Watchdog_Regs()
{
GEL_WatchAdd("*0x7023,x","WDCNTR");
GEL_WatchAdd("*0x7025,x","WDKEY");
GEL_WatchAdd("*0x7029,x","WDCR");
GEL_WatchAdd("*0x7022,x","SCSR");
}
/********************************************************************/
/*** End of file ***/

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v120/DSP2833x_common/gel/f28335.gel Normal file
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/********************************************************************/
/* f28335.gel */
/* Version 3.30.2 */
/* */
/* This GEL file is to be used with the TMS320F28335 DSP. */
/* Changes may be required to support specific hardware designs. */
/* */
/* Code Composer Studio supports six reserved GEL functions that */
/* automatically get executed if they are defined. They are: */
/* */
/* StartUp() - Executed whenever CCS is invoked */
/* OnReset() - Executed after Debug->Reset CPU */
/* OnRestart() - Executed after Debug->Restart */
/* OnPreFileLoaded() - Executed before File->Load Program */
/* OnFileLoaded() - Executed after File->Load Program */
/* OnTargetConnect() - Executed after Debug->Connect */
/* */
/********************************************************************/
StartUp()
{
/* The next line automatically loads the .gel file that comes */
/* with the DSP2833x Peripheral Header Files download. To use, */
/* uncomment, and adjust the directory path as needed. */
// GEL_LoadGel("c:\\CCStudio_v3.3\\cc\\gel\\DSP2833x_Peripheral.gel");
}
OnReset(int nErrorCode)
{
C28x_Mode();
Unlock_CSM();
ADC_Cal();
}
OnRestart(int nErrorCode)
{
/* CCS will call OnRestart() when you do a Debug->Restart and */
/* after you load a new file. Between running interrupt based */
/* programs, this function will clear interrupts and help keep */
/* the processor from going off into invalid memory. */
C28x_Mode();
IER = 0;
IFR = 0;
ADC_Cal();
}
int TxtOutCtl=0;
OnPreFileLoaded()
{
XINTF_Enable();
if (TxtOutCtl==0)
{
GEL_TextOut("\nNOTES:\nGel will enable XINTFx16 during Debug only.\nEnable XINTF in code prior to use.");
GEL_TextOut("\nFPU Registers can be found via GEL->Watch FPU Registers.");
TxtOutCtl=1;
}
}
OnFileLoaded(int nErrorCode, int bSymbolsOnly)
{
ADC_Cal();
}
OnTargetConnect()
{
C28x_Mode();
F28335_Memory_Map(); /* Initialize the CCS memory map */
/* Check to see if CCS has been started-up with the DSP already */
/* running in real-time mode. The user can add whatever */
/* custom initialization stuff they want to each case. */
if (GEL_IsInRealtimeMode()) /* Do real-time mode target initialization */
{
}
else /* Do stop-mode target initialization */
{
GEL_Reset(); /* Reset DSP */
}
}
/********************************************************************/
/* These functions are launched by the GEL_Toolbar button plugin */
/********************************************************************/
GEL_Toolbar1()
{
Run_Realtime_with_Reset();
}
GEL_Toolbar2()
{
Run_Realtime_with_Restart();
}
GEL_Toolbar3()
{
Full_Halt();
}
GEL_Toolbar4()
{
Full_Halt_with_Reset();
}
int GEL_Toolbar5_Toggle = 0;
GEL_Toolbar5()
{
if(GEL_Toolbar5_Toggle == 0)
{
GEL_Toolbar5_Toggle = 1;
GEL_OpenWindow("GEL_Buttons",1,4);
GEL_TextOut("Button 1: Run_Realtime_with_Reset()","GEL_Buttons",0,0);
GEL_TextOut("Button 2: Run_Realtime_with_Restart()","GEL_Buttons",0,1);
GEL_TextOut("Button 3: Full_Halt()", "GEL_Buttons",0,2);
GEL_TextOut("Button 4: Full_Halt_with_Reset()","GEL_Buttons",0,3);
}
else
{
GEL_Toolbar5_Toggle = 0;
GEL_CloseWindow("GEL_Buttons");
}
}
/********************************************************************/
/* These functions are useful to engage/dis-enagage realtime */
/* emulation mode during debug. They save the user from having to */
/* manually perform these steps in CCS. */
/********************************************************************/
menuitem "Realtime Emulation Control";
hotmenu Run_Realtime_with_Reset()
{
GEL_Reset(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Run_Realtime_with_Restart()
{
GEL_Restart(); /* Reset the DSP */
ST1 = ST1 & 0xFFFD; /* clear DBGM bit in ST1 */
GEL_EnableRealtime(); /* Enable Realtime mode */
GEL_Run(); /* Run the DSP */
}
hotmenu Full_Halt()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
}
hotmenu Full_Halt_with_Reset()
{
GEL_DisableRealtime(); /* Disable Realtime mode */
GEL_Halt(); /* Halt the DSP */
GEL_Reset(); /* Reset the DSP */
}
/********************************************************************/
/* F28335 Memory Map */
/* */
/* Note: M0M1MAP and VMAP signals tied high on F28335 core */
/* */
/* 0x000000 - 0x0003ff M0 SARAM (Prog and Data) */
/* 0x000400 - 0x0007ff M1 SARAM (Prog and Data) */
/* 0x000800 - 0x001fff Peripheral Frame0 (PF0) (Data only) */
/* 0x004000 - 0x004fff XINTF Zone 0 (Prog and Data) */
/* 0x005000 - 0x005fff Peripheral Frame3 (PF3) (Data only) */
/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */
/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */
/* 0x008000 - 0x008fff L0 SARAM (Prog and Data) */
/* 0x009000 - 0x009fff L1 SARAM (Prog and Data) */
/* 0x00A000 - 0x00Afff L2 SARAM (Prog and Data) */
/* 0x00B000 - 0x00Bfff L3 SARAM (Prog and Data) */
/* 0x00C000 - 0x00Cfff L4 SARAM (Prog and Data) */
/* 0x00D000 - 0x00Dfff L5 SARAM (Prog and Data) */
/* 0x00E000 - 0x00Efff L6 SARAM (Prog and Data) */
/* 0x00F000 - 0x00Ffff L7 SARAM (Prog and Data) */
/* 0x100000 - 0x1fffff XINTF Zone 6 (Prog and Data) */
/* 0x200000 - 0x2fffff XINTF Zone 7 (Prog and Data */
/* 0x300000 - 0x33ffff Flash (Prog and Data) */
/* 0x380080 - 0x380088 ADC_cal function (Prog and Data) */
/* 0x380090 - 0x380090 PARTID value (Prog and Data) */
/* 0x380400 - 0x3807ff OTP (Prog and Data) */
/* 0x3f8000 - 0x3f8fff L0 SARAM (Prog and Data) */
/* 0x3f9000 - 0x3f9fff L1 SARAM (Prog and Data) */
/* 0x3fA000 - 0x3fAfff L2 SARAM (Prog and Data) */
/* 0x3fB000 - 0x3fBfff L3 SARAM (Prog and Data) */
/* 0x3fe000 - 0x3fffff BOOT ROM (Prog and Data) */
/********************************************************************/
menuitem "Initialize Memory Map";
hotmenu F28335_Memory_Map()
{
GEL_MapReset();
GEL_MapOn();
/* Program memory map */
GEL_MapAdd(0x0,0,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,0,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x4000,0,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x8000,0,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,0,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,0,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,0,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,0,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,0,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0xE000,0,0x1000,1,1); /* L6 SARAM */
GEL_MapAdd(0xF000,0,0x1000,1,1); /* L7 SARAM */
GEL_MapAdd(0x100000,0,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,0,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x300000,0,0x40000,1,0); /* FLASH */
GEL_MapAdd(0x380080,0,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,0,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x380400,0,0x00400,1,0); /* OTP */
GEL_MapAdd(0x3f8000,0,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,0,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,0,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,0,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,0,0x2000,1,0); /* BOOT ROM */
/* Data memory map */
GEL_MapAdd(0x000,1,0x400,1,1); /* M0 SARAM */
GEL_MapAdd(0x400,1,0x400,1,1); /* M1 SARAM */
GEL_MapAdd(0x800,1,0x1800,1,1); /* PF0 */
GEL_MapAdd(0x4000,1,0x1000,1,1); /* Zone 0 */
GEL_MapAdd(0x5000,1,0x1000,1,1); /* PF3 */
GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */
GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */
GEL_MapAdd(0x8000,1,0x1000,1,1); /* L0 SARAM */
GEL_MapAdd(0x9000,1,0x1000,1,1); /* L1 SARAM */
GEL_MapAdd(0xA000,1,0x1000,1,1); /* L2 SARAM */
GEL_MapAdd(0xB000,1,0x1000,1,1); /* L3 SARAM */
GEL_MapAdd(0xC000,1,0x1000,1,1); /* L4 SARAM */
GEL_MapAdd(0xD000,1,0x1000,1,1); /* L5 SARAM */
GEL_MapAdd(0xE000,1,0x1000,1,1); /* L6 SARAM */
GEL_MapAdd(0xF000,1,0x1000,1,1); /* L7 SARAM */
GEL_MapAdd(0x100000,1,0x100000,1,1); /* Zone 6 */
GEL_MapAdd(0x200000,1,0x100000,1,1); /* Zone 7 */
GEL_MapAdd(0x300000,1,0x40000,1,0); /* FLASH */
GEL_MapAdd(0x380400,1,0x00400,1,0); /* OTP */
GEL_MapAdd(0x380080,1,0x00009,1,0); /* ADC_cal function*/
GEL_MapAdd(0x380090,1,0x00001,1,0); /* PARTID value */
GEL_MapAdd(0x3f8000,1,0x1000,1,1); /* L0 SARAM Mirror */
GEL_MapAdd(0x3f9000,1,0x1000,1,1); /* L1 SARAM Mirror */
GEL_MapAdd(0x3fA000,1,0x1000,1,1); /* L2 SARAM Mirror */
GEL_MapAdd(0x3fb000,1,0x1000,1,1); /* L3 SARAM Mirror */
GEL_MapAdd(0x3fe000,1,0x2000,1,0); /* BOOT ROM */
}
/********************************************************************/
/* The ESTOP0 fill functions are useful for debug. They fill the */
/* RAM with software breakpoints that will trap runaway code. */
/********************************************************************/
hotmenu Fill_F28335_RAM_with_ESTOP0()
{
GEL_MemoryFill(0x000000,1,0x000800,0x7625); /* Fill M0/M1 */
GEL_MemoryFill(0x008000,1,0x002000,0x7625); /* Fill L0/L1 */
GEL_MemoryFill(0x00A000,1,0x002000,0x7625); /* Fill L2/L3 */
GEL_MemoryFill(0x00C000,1,0x002000,0x7625); /* Fill L4/L5 */
GEL_MemoryFill(0x00E000,1,0x002000,0x7625); /* Fill L6/L7 */
}
/********************************************************************/
menuitem "Watchdog";
hotmenu Disable_WD()
{
*0x7029 = *0x7029 | 0x0068; /* Set the WDDIS bit */
*0x7025 = 0x0055; /* Service the WD */
*0x7025 = 0x00AA; /* once to be safe. */
GEL_TextOut("\nWatchdog Timer Disabled");
}
/********************************************************************/
menuitem "Code Security Module"
hotmenu Unlock_CSM()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
/* Write passwords to the KEY registers. 0xFFFF's are dummy passwords.
User should replace them with the correct password for their DSP */
*0xAE0 = 0xFFFF;
*0xAE1 = 0xFFFF;
*0xAE2 = 0xFFFF;
*0xAE3 = 0xFFFF;
*0xAE4 = 0xFFFF;
*0xAE5 = 0xFFFF;
*0xAE6 = 0xFFFF;
*0xAE7 = 0xFFFF;
}
/********************************************************************/
menuitem "Addressing Modes";
hotmenu C28x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C24x_Mode()
{
ST1 = ST1 | 0x0100; /* AMODE = 1 */
ST1 = ST1 | 0x0200; /* OBJMODE = 1 */
}
hotmenu C27x_Mode()
{
ST1 = ST1 & (~0x0100); /* AMODE = 0 */
ST1 = ST1 & (~0x0200); /* OBJMODE = 0 */
}
/********************************************************************/
/* PLL Ratios */
/* */
/* The following table describes the PLL clocking ratios (0..10) */
/* */
/* Ratio CLKIN Description */
/* ----- -------------- ------------ */
/* 0 OSCCLK/2 PLL bypassed */
/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */
/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */
/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */
/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */
/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */
/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */
/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */
/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */
/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */
/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */
/********************************************************************/
menuitem "Set PLL Ratio";
hotmenu Bypass()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */
PLL_Wait();
}
hotmenu OSCCLK_x1_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x2_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x3_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x4_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x5_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x6_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x7_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x8_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x9_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x10_divided_by_2()
{
DIVSEL_div2(); /* DIVSEL = 1/2 */
*0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */
PLL_Wait();
}
// hotmenu OSCCLK_x1_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 1; /* CLKIN = (OSCCLK * 1)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x2_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 2; /* CLKIN = (OSCCLK * 2)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x3_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 3; /* CLKIN = (OSCCLK * 3)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x4_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 4; /* CLKIN = (OSCCLK * 4)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x5_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 5; /* CLKIN = (OSCCLK * 5)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x6_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 6; /* CLKIN = (OSCCLK * 6)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x7_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 7; /* CLKIN = (OSCCLK * 7)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x8_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 8; /* CLKIN = (OSCCLK * 8)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x9_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 9; /* CLKIN = (OSCCLK * 9)/1 */
// PLL_Wait();
// }
// hotmenu OSCCLK_x10_divided_by_1()
// {
// DIVSEL_div1(); /* DIVSEL = 1/1 */
// *0x7021 = 10; /* CLKIN = (OSCCLK * 10)/1 */
// PLL_Wait();
// }
/********************************************************************/
/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to 1/2 */
/********************************************************************/
DIVSEL_div2()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
temp = *PLLSTS;
temp &= 0xFE7F; /* Clear bits 7 & 8 */
temp |= 2 << 7; /* Set bit 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
/********************************************************************/
/* For F2833x devices, DIVSEL is 1/4 by default. Switch it to /1 */
/********************************************************************/
DIVSEL_div1()
{
int temp;
int PLLSTS;
PLLSTS = 0x7011;
DIVSEL_div2(); /* First switch DIVSEL to 1/2 and wait */
wait();
temp = *PLLSTS;
temp |= 3 << 7; /* Set bits 7 & 8 */
*PLLSTS = temp; /* Switch to 1/2 */
}
wait()
{
int delay = 0;
for (delay = 0; delay <= 5; delay ++)
{}
}
/********************************************************************/
/* For F2833x devices, check the PLLOCKS bit for PLL lock. */
/********************************************************************/
PLL_Wait()
{
int PLLSTS;
int delay = 0;
PLLSTS = 0x7011;
while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001)
{
delay++;
GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}
/********************************************************************/
/* Load the ADC Calibration values from TI OTP */
/********************************************************************/
menuitem "ADC Calibration"
hotmenu ADC_Cal()
{
/* Perform dummy reads of the password locations */
XAR0 = *0x33FFF8;
XAR0 = *0x33FFF9;
XAR0 = *0x33FFFA;
XAR0 = *0x33FFFB;
XAR0 = *0x33FFFC;
XAR0 = *0x33FFFD;
XAR0 = *0x33FFFE;
XAR0 = *0x33FFFF;
if(((*0x0AEF) & 0x0001) == 0)
{
XAR0 = *0x701C;
*0x701C |= 0x0008;
*0x711C = *0x380083;
*0x711D = *0x380085;
*0x701C = XAR0;
XAR0 = 0;
}
else
{
GEL_TextOut("\nADC Calibration not complete, check if device is unlocked and recalibrate.");
}
}
/********************************************************************/
/* Enable the XINTF and configure GPIOs for XINTF function */
/********************************************************************/
menuitem "XINTF Enable"
hotmenu XINTF_Enable()
{
/* enable XINTF clock (XTIMCLK) */
*0x7020 = 0x3700;
/* GPBMUX1: XA0-XA7, XA16, XZCS0, */
/* XZCS7, XREADY, XRNW, XWE0 */
/* GPAMUX2: XA17-XA19, XZCS6 */
/* GPCMUX2: XA8-XA15 */
/* GPCMUX1: XD0-XD15 */
*(unsigned long *)0x6F96 = 0xFFFFFFC0; /* GPBMUX1 */
*(unsigned long *)0x6f88 = 0xFF000000; /* GPAMUX2 */
*(unsigned long *)0x6FA8 = 0x0000AAAA; /* GPCMUX2 */
*(unsigned long *)0x6FA6 = 0xAAAAAAAA; /* GPCMUX1 */
/* Uncomment for x32 data bus */
/* GPBMUX2: XD16-XD31 */
// *(unsigned long *)0x6F98 = 0xFFFFFFFF; /* GPBMUX2 */
/* Zone timing.
/* Each zone can be configured seperately */
/* Uncomment the x16 or the x32 timing */
/* depending on the data bus width for */
/* the zone */
/* x16 Timing */
*(unsigned long *)0x0B20 = 0x0043FFFF; /* Zone0 */
*(unsigned long *)0x0B2C = 0x0043FFFF; /* Zone6 */
*(unsigned long *)0x0B2E = 0x0043FFFF; /* Zone7 */
/* x32 Timing:
// *(unsigned long *)0x0B20 = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2C = 0x0041FFFF; /* x32 */
// *(unsigned long *)0x0B2E = 0x0041FFFF; /* x32 */
}
/********************************************************************/
/* The below are used to display the symbolic names of the F28335 */
/* memory mapped registers in the watch window. To view these */
/* registers, click on the GEL menu button in Code Composer Studio, */
/* then select which registers or groups of registers you want to */
/* view. They will appear in the watch window under the Watch1 tab. */
/********************************************************************/
/* Add a space line to the GEL menu */
menuitem "______________________________________";
hotmenu __() {}
/********************************************************************/
/* A/D Converter Registers */
/********************************************************************/
menuitem "Watch ADC Registers";
hotmenu All_ADC_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
hotmenu ADC_Control_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
GEL_WatchAdd("*0x711C,x","ADCREFSEL");
GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
}
hotmenu ADCCHSELSEQx_Regs()
{
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
}
hotmenu ADCRESULT_0_to_7()
{
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
}
hotmenu ADCRESULT_8_to_15()
{
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
}
hotmenu ADCRESULT_Mirror_0_to_7()
{
GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
}
hotmenu ADCRESULT_Mirror_8_to_15()
{
GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
/********************************************************************/
/* Clocking and Low-Power Registers */
/********************************************************************/
menuitem "Watch Clocking and Low-Power Registers";
hotmenu All_Clocking_and_Low_Power_Regs()
{
GEL_WatchAdd("*0x7010,x","XCLK");
GEL_WatchAdd("*0x7011,x","PLLSTS");
GEL_WatchAdd("*0x701A,x","HISPCP");
GEL_WatchAdd("*0x701B,x","LOSPCP");
GEL_WatchAdd("*0x701C,x","PCLKCR0");
GEL_WatchAdd("*0x701D,x","PCLKCR1");
GEL_WatchAdd("*0x701E,x","LPMCR0");
GEL_WatchAdd("*0x7020,x","PCLKCR3");
GEL_WatchAdd("*0x7021,x","PLLCR");
}
/********************************************************************/
/* Code Security Module Registers */
/********************************************************************/
menuitem "Watch Code Security Module Registers";
hotmenu CSMSCR()
{
GEL_WatchAdd("*0x0AEF,x","CSMSCR");
GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit");
GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit");
}
hotmenu PWL_Locations()
{
GEL_WatchAdd("*0x33FFF8,x","PWL0");
GEL_WatchAdd("*0x33FFF9,x","PWL1");
GEL_WatchAdd("*0x33FFFA,x","PWL2");
GEL_WatchAdd("*0x33FFFB,x","PWL3");
GEL_WatchAdd("*0x33FFFC,x","PWL4");
GEL_WatchAdd("*0x33FFFD,x","PWL5");
GEL_WatchAdd("*0x33FFFE,x","PWL6");
GEL_WatchAdd("*0x33FFFF,x","PWL7");
}
/********************************************************************/
/* CPU Timer Registers */
/********************************************************************/
menuitem "Watch CPU Timer Registers";
hotmenu All_CPU_Timer0_Regs()
{
GEL_WatchAdd("*0x0C00,x","TIMER0TIM");
GEL_WatchAdd("*0x0C01,x","TIMER0TIMH");
GEL_WatchAdd("*0x0C02,x","TIMER0PRD");
GEL_WatchAdd("*0x0C03,x","TIMER0PRDH");
GEL_WatchAdd("*0x0C04,x","TIMER0TCR");
GEL_WatchAdd("*0x0C06,x","TIMER0TPR");
GEL_WatchAdd("*0x0C07,x","TIMER0TPRH");
}
hotmenu All_CPU_Timer1_Regs()
{
GEL_WatchAdd("*0x0C08,x","TIMER1TIM");
GEL_WatchAdd("*0x0C09,x","TIMER1TIMH");
GEL_WatchAdd("*0x0C0A,x","TIMER1PRD");
GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH");
GEL_WatchAdd("*0x0C0C,x","TIMER1TCR");
GEL_WatchAdd("*0x0C0E,x","TIMER1TPR");
GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH");
}
hotmenu All_CPU_Timer2_Regs()
{
GEL_WatchAdd("*0x0C10,x","TIMER2TIM");
GEL_WatchAdd("*0x0C11,x","TIMER2TIMH");
GEL_WatchAdd("*0x0C12,x","TIMER2PRD");
GEL_WatchAdd("*0x0C13,x","TIMER2PRDH");
GEL_WatchAdd("*0x0C14,x","TIMER2TCR");
GEL_WatchAdd("*0x0C16,x","TIMER2TPR");
GEL_WatchAdd("*0x0C17,x","TIMER2TPRH");
}
/********************************************************************/
/* Device Emulation Registers */
/********************************************************************/
menuitem "Watch Device Emulation Registers";
hotmenu All_Emulation_Regs()
{
GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF");
GEL_WatchAdd("*0x0882,x","CLASSID");
GEL_WatchAdd("*0x0883,x","REVID");
GEL_WatchAdd("*0x0884,x","PROTSTART");
GEL_WatchAdd("*0x0885,x","PROTRANGE");
GEL_WatchAdd("*0x380090,x","PARTID");
}
/********************************************************************/
/* DMA Registers */
/********************************************************************/
menuitem "Watch DMA Registers";
hotmenu All_DMA_Regs()
{
GEL_WatchAdd("*0x1000,x","DMACTRL");
GEL_WatchAdd("*0x1001,x","DEBUGCTRL");
GEL_WatchAdd("*0x1002,x","REVISION");
GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1");
GEL_WatchAdd("*0x1006,x","PRIORITYSTAT");
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_1_regs()
{
GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_2_regs()
{
GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_3_regs()
{
GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_4_regs()
{
GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_5_regs()
{
GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_6_regs()
{
GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}
/********************************************************************/
/* eCAN Registers */
/********************************************************************/
menuitem "Watch eCAN Registers";
hotmenu eCAN_A_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME");
GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD");
GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS");
GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR");
GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA");
GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA");
GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP");
GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML");
GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP");
GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC");
GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC");
GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES");
GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC");
GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC");
GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0");
GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM");
GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1");
GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM");
GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL");
GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC");
GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC");
GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC");
GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT");
GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC");
GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS");
}
hotmenu eCAN_A_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0");
GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0");
GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0");
GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0");
GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0");
GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0");
GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0");
GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1");
GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1");
GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1");
GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1");
GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1");
GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1");
GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1");
}
hotmenu eCAN_A_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2");
GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2");
GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2");
GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2");
GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2");
GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2");
GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2");
GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3");
GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3");
GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3");
GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3");
GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3");
GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3");
GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3");
}
hotmenu eCAN_A_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4");
GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4");
GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4");
GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4");
GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4");
GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4");
GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4");
GEL_WatchAdd("*(long *)0x604A,x","eCANA LAM5");
GEL_WatchAdd("*(long *)0x608A,x","eCANA MOTS5");
GEL_WatchAdd("*(long *)0x60CA,x","eCANA MOTO5");
GEL_WatchAdd("*(long *)0x6128,x","eCANA MID5");
GEL_WatchAdd("*(long *)0x612A,x","eCANA MCF5");
GEL_WatchAdd("*(long *)0x612C,x","eCANA MDL5");
GEL_WatchAdd("*(long *)0x612E,x","eCANA MDH5");
}
hotmenu eCAN_A_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x604C,x","eCANA LAM6");
GEL_WatchAdd("*(long *)0x608C,x","eCANA MOTS6");
GEL_WatchAdd("*(long *)0x60CC,x","eCANA MOTO6");
GEL_WatchAdd("*(long *)0x6130,x","eCANA MID6");
GEL_WatchAdd("*(long *)0x6132,x","eCANA MCF6");
GEL_WatchAdd("*(long *)0x6134,x","eCANA MDL6");
GEL_WatchAdd("*(long *)0x6136,x","eCANA MDH6");
GEL_WatchAdd("*(long *)0x604E,x","eCANA LAM7");
GEL_WatchAdd("*(long *)0x608E,x","eCANA MOTS7");
GEL_WatchAdd("*(long *)0x60CE,x","eCANA MOTO7");
GEL_WatchAdd("*(long *)0x6138,x","eCANA MID7");
GEL_WatchAdd("*(long *)0x613A,x","eCANA MCF7");
GEL_WatchAdd("*(long *)0x613C,x","eCANA MDL7");
GEL_WatchAdd("*(long *)0x613E,x","eCANA MDH7");
}
hotmenu eCAN_A_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6050,x","eCANA LAM8");
GEL_WatchAdd("*(long *)0x6090,x","eCANA MOTS8");
GEL_WatchAdd("*(long *)0x60D0,x","eCANA MOTO8");
GEL_WatchAdd("*(long *)0x6140,x","eCANA MID8");
GEL_WatchAdd("*(long *)0x6142,x","eCANA MCF8");
GEL_WatchAdd("*(long *)0x6144,x","eCANA MDL8");
GEL_WatchAdd("*(long *)0x6146,x","eCANA MDH8");
GEL_WatchAdd("*(long *)0x6052,x","eCANA LAM9");
GEL_WatchAdd("*(long *)0x6092,x","eCANA MOTS9");
GEL_WatchAdd("*(long *)0x60D2,x","eCANA MOTO9");
GEL_WatchAdd("*(long *)0x6148,x","eCANA MID9");
GEL_WatchAdd("*(long *)0x614A,x","eCANA MCF9");
GEL_WatchAdd("*(long *)0x614C,x","eCANA MDL9");
GEL_WatchAdd("*(long *)0x614E,x","eCANA MDH9");
}
hotmenu eCAN_A_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6054,x","eCANA LAM10");
GEL_WatchAdd("*(long *)0x6094,x","eCANA MOTS10");
GEL_WatchAdd("*(long *)0x60D4,x","eCANA MOTO10");
GEL_WatchAdd("*(long *)0x6150,x","eCANA MID10");
GEL_WatchAdd("*(long *)0x6152,x","eCANA MCF10");
GEL_WatchAdd("*(long *)0x6154,x","eCANA MDL10");
GEL_WatchAdd("*(long *)0x6156,x","eCANA MDH10");
GEL_WatchAdd("*(long *)0x6056,x","eCANA LAM11");
GEL_WatchAdd("*(long *)0x6096,x","eCANA MOTS11");
GEL_WatchAdd("*(long *)0x60D6,x","eCANA MOTO11");
GEL_WatchAdd("*(long *)0x6158,x","eCANA MID11");
GEL_WatchAdd("*(long *)0x615A,x","eCANA MCF11");
GEL_WatchAdd("*(long *)0x615C,x","eCANA MDL11");
GEL_WatchAdd("*(long *)0x615E,x","eCANA MDH11");
}
hotmenu eCAN_A_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6058,x","eCANA LAM12");
GEL_WatchAdd("*(long *)0x6098,x","eCANA MOTS12");
GEL_WatchAdd("*(long *)0x60D8,x","eCANA MOTO12");
GEL_WatchAdd("*(long *)0x6160,x","eCANA MID12");
GEL_WatchAdd("*(long *)0x6162,x","eCANA MCF12");
GEL_WatchAdd("*(long *)0x6164,x","eCANA MDL12");
GEL_WatchAdd("*(long *)0x6166,x","eCANA MDH12");
GEL_WatchAdd("*(long *)0x605A,x","eCANA LAM13");
GEL_WatchAdd("*(long *)0x609A,x","eCANA MOTS13");
GEL_WatchAdd("*(long *)0x60DA,x","eCANA MOTO13");
GEL_WatchAdd("*(long *)0x6168,x","eCANA MID13");
GEL_WatchAdd("*(long *)0x616A,x","eCANA MCF13");
GEL_WatchAdd("*(long *)0x616C,x","eCANA MDL13");
GEL_WatchAdd("*(long *)0x616E,x","eCANA MDH13");
}
hotmenu eCAN_A_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x605C,x","eCANA LAM14");
GEL_WatchAdd("*(long *)0x609C,x","eCANA MOTS14");
GEL_WatchAdd("*(long *)0x60DC,x","eCANA MOTO14");
GEL_WatchAdd("*(long *)0x6170,x","eCANA MID14");
GEL_WatchAdd("*(long *)0x6172,x","eCANA MCF14");
GEL_WatchAdd("*(long *)0x6174,x","eCANA MDL14");
GEL_WatchAdd("*(long *)0x6176,x","eCANA MDH14");
GEL_WatchAdd("*(long *)0x605E,x","eCANA LAM15");
GEL_WatchAdd("*(long *)0x609E,x","eCANA MOTS15");
GEL_WatchAdd("*(long *)0x60DE,x","eCANA MOTO15");
GEL_WatchAdd("*(long *)0x6178,x","eCANA MID15");
GEL_WatchAdd("*(long *)0x617A,x","eCANA MCF15");
GEL_WatchAdd("*(long *)0x617C,x","eCANA MDL15");
GEL_WatchAdd("*(long *)0x617E,x","eCANA MDH15");
}
hotmenu eCAN_A_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6060,x","eCANA LAM16");
GEL_WatchAdd("*(long *)0x60A0,x","eCANA MOTS16");
GEL_WatchAdd("*(long *)0x60E0,x","eCANA MOTO16");
GEL_WatchAdd("*(long *)0x6180,x","eCANA MID16");
GEL_WatchAdd("*(long *)0x6182,x","eCANA MCF16");
GEL_WatchAdd("*(long *)0x6184,x","eCANA MDL16");
GEL_WatchAdd("*(long *)0x6186,x","eCANA MDH16");
GEL_WatchAdd("*(long *)0x6062,x","eCANA LAM17");
GEL_WatchAdd("*(long *)0x60A2,x","eCANA MOTS17");
GEL_WatchAdd("*(long *)0x60E2,x","eCANA MOTO17");
GEL_WatchAdd("*(long *)0x6188,x","eCANA MID17");
GEL_WatchAdd("*(long *)0x618A,x","eCANA MCF17");
GEL_WatchAdd("*(long *)0x618C,x","eCANA MDL17");
GEL_WatchAdd("*(long *)0x618E,x","eCANA MDH17");
}
hotmenu eCAN_A_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6064,x","eCANA LAM18");
GEL_WatchAdd("*(long *)0x60A4,x","eCANA MOTS18");
GEL_WatchAdd("*(long *)0x60E4,x","eCANA MOTO18");
GEL_WatchAdd("*(long *)0x6190,x","eCANA MID18");
GEL_WatchAdd("*(long *)0x6192,x","eCANA MCF18");
GEL_WatchAdd("*(long *)0x6194,x","eCANA MDL18");
GEL_WatchAdd("*(long *)0x6196,x","eCANA MDH18");
GEL_WatchAdd("*(long *)0x6066,x","eCANA LAM19");
GEL_WatchAdd("*(long *)0x60A6,x","eCANA MOTS19");
GEL_WatchAdd("*(long *)0x60E6,x","eCANA MOTO19");
GEL_WatchAdd("*(long *)0x6198,x","eCANA MID19");
GEL_WatchAdd("*(long *)0x619A,x","eCANA MCF19");
GEL_WatchAdd("*(long *)0x619C,x","eCANA MDL19");
GEL_WatchAdd("*(long *)0x619E,x","eCANA MDH19");
}
hotmenu eCAN_A_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6068,x","eCANA LAM20");
GEL_WatchAdd("*(long *)0x60A8,x","eCANA MOTS20");
GEL_WatchAdd("*(long *)0x60E8,x","eCANA MOTO20");
GEL_WatchAdd("*(long *)0x61A0,x","eCANA MID20");
GEL_WatchAdd("*(long *)0x61A2,x","eCANA MCF20");
GEL_WatchAdd("*(long *)0x61A4,x","eCANA MDL20");
GEL_WatchAdd("*(long *)0x61A6,x","eCANA MDH20");
GEL_WatchAdd("*(long *)0x606A,x","eCANA LAM21");
GEL_WatchAdd("*(long *)0x60AA,x","eCANA MOTS21");
GEL_WatchAdd("*(long *)0x60EA,x","eCANA MOTO21");
GEL_WatchAdd("*(long *)0x61A8,x","eCANA MID21");
GEL_WatchAdd("*(long *)0x61AA,x","eCANA MCF21");
GEL_WatchAdd("*(long *)0x61AC,x","eCANA MDL21");
GEL_WatchAdd("*(long *)0x61AE,x","eCANA MDH21");
}
hotmenu eCAN_A_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x606C,x","eCANA LAM22");
GEL_WatchAdd("*(long *)0x60AC,x","eCANA MOTS22");
GEL_WatchAdd("*(long *)0x60EC,x","eCANA MOTO22");
GEL_WatchAdd("*(long *)0x61B0,x","eCANA MID22");
GEL_WatchAdd("*(long *)0x61B2,x","eCANA MCF22");
GEL_WatchAdd("*(long *)0x61B4,x","eCANA MDL22");
GEL_WatchAdd("*(long *)0x61B6,x","eCANA MDH22");
GEL_WatchAdd("*(long *)0x606E,x","eCANA LAM23");
GEL_WatchAdd("*(long *)0x60AE,x","eCANA MOTS23");
GEL_WatchAdd("*(long *)0x60EE,x","eCANA MOTO23");
GEL_WatchAdd("*(long *)0x61B8,x","eCANA MID23");
GEL_WatchAdd("*(long *)0x61BA,x","eCANA MCF23");
GEL_WatchAdd("*(long *)0x61BC,x","eCANA MDL23");
GEL_WatchAdd("*(long *)0x61BE,x","eCANA MDH23");
}
hotmenu eCAN_A_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6070,x","eCANA LAM24");
GEL_WatchAdd("*(long *)0x60B0,x","eCANA MOTS24");
GEL_WatchAdd("*(long *)0x60F0,x","eCANA MOTO24");
GEL_WatchAdd("*(long *)0x61C0,x","eCANA MID24");
GEL_WatchAdd("*(long *)0x61C2,x","eCANA MCF24");
GEL_WatchAdd("*(long *)0x61C4,x","eCANA MDL24");
GEL_WatchAdd("*(long *)0x61C6,x","eCANA MDH24");
GEL_WatchAdd("*(long *)0x6072,x","eCANA LAM25");
GEL_WatchAdd("*(long *)0x60B2,x","eCANA MOTS25");
GEL_WatchAdd("*(long *)0x60F2,x","eCANA MOTO25");
GEL_WatchAdd("*(long *)0x61C8,x","eCANA MID25");
GEL_WatchAdd("*(long *)0x61CA,x","eCANA MCF25");
GEL_WatchAdd("*(long *)0x61CC,x","eCANA MDL25");
GEL_WatchAdd("*(long *)0x61CE,x","eCANA MDH25");
}
hotmenu eCAN_A_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6074,x","eCANA LAM26");
GEL_WatchAdd("*(long *)0x60B4,x","eCANA MOTS26");
GEL_WatchAdd("*(long *)0x60F4,x","eCANA MOTO26");
GEL_WatchAdd("*(long *)0x61D0,x","eCANA MID26");
GEL_WatchAdd("*(long *)0x61D2,x","eCANA MCF26");
GEL_WatchAdd("*(long *)0x61D4,x","eCANA MDL26");
GEL_WatchAdd("*(long *)0x61D6,x","eCANA MDH26");
GEL_WatchAdd("*(long *)0x6076,x","eCANA LAM27");
GEL_WatchAdd("*(long *)0x60B6,x","eCANA MOTS27");
GEL_WatchAdd("*(long *)0x60F6,x","eCANA MOTO27");
GEL_WatchAdd("*(long *)0x61D8,x","eCANA MID27");
GEL_WatchAdd("*(long *)0x61DA,x","eCANA MCF27");
GEL_WatchAdd("*(long *)0x61DC,x","eCANA MDL27");
GEL_WatchAdd("*(long *)0x61DE,x","eCANA MDH27");
}
hotmenu eCAN_A_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6078,x","eCANA LAM28");
GEL_WatchAdd("*(long *)0x60B8,x","eCANA MOTS28");
GEL_WatchAdd("*(long *)0x60F8,x","eCANA MOTO28");
GEL_WatchAdd("*(long *)0x61E0,x","eCANA MID28");
GEL_WatchAdd("*(long *)0x61E2,x","eCANA MCF28");
GEL_WatchAdd("*(long *)0x61E4,x","eCANA MDL28");
GEL_WatchAdd("*(long *)0x61E6,x","eCANA MDH28");
GEL_WatchAdd("*(long *)0x607A,x","eCANA LAM29");
GEL_WatchAdd("*(long *)0x60BA,x","eCANA MOTS29");
GEL_WatchAdd("*(long *)0x60FA,x","eCANA MOTO29");
GEL_WatchAdd("*(long *)0x61E8,x","eCANA MID29");
GEL_WatchAdd("*(long *)0x61EA,x","eCANA MCF29");
GEL_WatchAdd("*(long *)0x61EC,x","eCANA MDL29");
GEL_WatchAdd("*(long *)0x61EE,x","eCANA MDH29");
}
hotmenu eCAN_A_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x607C,x","eCANA LAM30");
GEL_WatchAdd("*(long *)0x60BC,x","eCANA MOTS30");
GEL_WatchAdd("*(long *)0x60FC,x","eCANA MOTO30");
GEL_WatchAdd("*(long *)0x61F0,x","eCANA MID30");
GEL_WatchAdd("*(long *)0x61F2,x","eCANA MCF30");
GEL_WatchAdd("*(long *)0x61F4,x","eCANA MDL30");
GEL_WatchAdd("*(long *)0x61F6,x","eCANA MDH30");
GEL_WatchAdd("*(long *)0x607E,x","eCANA LAM31");
GEL_WatchAdd("*(long *)0x60BE,x","eCANA MOTS31");
GEL_WatchAdd("*(long *)0x60FE,x","eCANA MOTO31");
GEL_WatchAdd("*(long *)0x61F8,x","eCANA MID31");
GEL_WatchAdd("*(long *)0x61FA,x","eCANA MCF31");
GEL_WatchAdd("*(long *)0x61FC,x","eCANA MDL31");
GEL_WatchAdd("*(long *)0x61FE,x","eCANA MDH31");
}
hotmenu eCAN_B_Global_Regs()
{
GEL_WatchAdd("*(long *)0x6200,x","eCANB CANME");
GEL_WatchAdd("*(long *)0x6202,x","eCANB CANMD");
GEL_WatchAdd("*(long *)0x6204,x","eCANB CANTRS");
GEL_WatchAdd("*(long *)0x6206,x","eCANB CANTRR");
GEL_WatchAdd("*(long *)0x6208,x","eCANB CANTA");
GEL_WatchAdd("*(long *)0x620A,x","eCANB CANAA");
GEL_WatchAdd("*(long *)0x620C,x","eCANB CANRMP");
GEL_WatchAdd("*(long *)0x620E,x","eCANB CANRML");
GEL_WatchAdd("*(long *)0x6210,x","eCANB CANRFP");
GEL_WatchAdd("*(long *)0x6214,x","eCANB CANMC");
GEL_WatchAdd("*(long *)0x6216,x","eCANB CANBTC");
GEL_WatchAdd("*(long *)0x6218,x","eCANB CANES");
GEL_WatchAdd("*(long *)0x621A,x","eCANB CANTEC");
GEL_WatchAdd("*(long *)0x621C,x","eCANB CANREC");
GEL_WatchAdd("*(long *)0x621E,x","eCANB CANGIF0");
GEL_WatchAdd("*(long *)0x6220,x","eCANB CANGIM");
GEL_WatchAdd("*(long *)0x6222,x","eCANB CANGIF1");
GEL_WatchAdd("*(long *)0x6224,x","eCANB CANMIM");
GEL_WatchAdd("*(long *)0x6226,x","eCANB CANMIL");
GEL_WatchAdd("*(long *)0x6228,x","eCANB CANOPC");
GEL_WatchAdd("*(long *)0x622A,x","eCANB CANTIOC");
GEL_WatchAdd("*(long *)0x622C,x","eCANB CANRIOC");
GEL_WatchAdd("*(long *)0x622E,x","eCANB CANLNT");
GEL_WatchAdd("*(long *)0x6230,x","eCANB CANTOC");
GEL_WatchAdd("*(long *)0x6232,x","eCANB CANTOS");
}
hotmenu eCAN_B_Mailbox_0_to_1_Regs()
{
GEL_WatchAdd("*(long *)0x6240,x","eCANB LAM0");
GEL_WatchAdd("*(long *)0x6280,x","eCANB MOTS0");
GEL_WatchAdd("*(long *)0x62C0,x","eCANB MOTO0");
GEL_WatchAdd("*(long *)0x6300,x","eCANB MID0");
GEL_WatchAdd("*(long *)0x6302,x","eCANB MCF0");
GEL_WatchAdd("*(long *)0x6304,x","eCANB MDL0");
GEL_WatchAdd("*(long *)0x6306,x","eCANB MDH0");
GEL_WatchAdd("*(long *)0x6242,x","eCANB LAM1");
GEL_WatchAdd("*(long *)0x6282,x","eCANB MOTS1");
GEL_WatchAdd("*(long *)0x62C2,x","eCANB MOTO1");
GEL_WatchAdd("*(long *)0x6308,x","eCANB MID1");
GEL_WatchAdd("*(long *)0x630A,x","eCANB MCF1");
GEL_WatchAdd("*(long *)0x630C,x","eCANB MDL1");
GEL_WatchAdd("*(long *)0x630E,x","eCANB MDH1");
}
hotmenu eCAN_B_Mailbox_2_to_3_Regs()
{
GEL_WatchAdd("*(long *)0x6244,x","eCANB LAM2");
GEL_WatchAdd("*(long *)0x6284,x","eCANB MOTS2");
GEL_WatchAdd("*(long *)0x62C4,x","eCANB MOTO2");
GEL_WatchAdd("*(long *)0x6310,x","eCANB MID2");
GEL_WatchAdd("*(long *)0x6312,x","eCANB MCF2");
GEL_WatchAdd("*(long *)0x6314,x","eCANB MDL2");
GEL_WatchAdd("*(long *)0x6316,x","eCANB MDH2");
GEL_WatchAdd("*(long *)0x6246,x","eCANB LAM3");
GEL_WatchAdd("*(long *)0x6286,x","eCANB MOTS3");
GEL_WatchAdd("*(long *)0x62C6,x","eCANB MOTO3");
GEL_WatchAdd("*(long *)0x6318,x","eCANB MID3");
GEL_WatchAdd("*(long *)0x631A,x","eCANB MCF3");
GEL_WatchAdd("*(long *)0x631C,x","eCANB MDL3");
GEL_WatchAdd("*(long *)0x631E,x","eCANB MDH3");
}
hotmenu eCAN_B_Mailbox_4_to_5_Regs()
{
GEL_WatchAdd("*(long *)0x6248,x","eCANB LAM4");
GEL_WatchAdd("*(long *)0x6288,x","eCANB MOTS4");
GEL_WatchAdd("*(long *)0x62C8,x","eCANB MOTO4");
GEL_WatchAdd("*(long *)0x6320,x","eCANB MID4");
GEL_WatchAdd("*(long *)0x6322,x","eCANB MCF4");
GEL_WatchAdd("*(long *)0x6324,x","eCANB MDL4");
GEL_WatchAdd("*(long *)0x6326,x","eCANB MDH4");
GEL_WatchAdd("*(long *)0x624A,x","eCANB LAM5");
GEL_WatchAdd("*(long *)0x628A,x","eCANB MOTS5");
GEL_WatchAdd("*(long *)0x62CA,x","eCANB MOTO5");
GEL_WatchAdd("*(long *)0x6328,x","eCANB MID5");
GEL_WatchAdd("*(long *)0x632A,x","eCANB MCF5");
GEL_WatchAdd("*(long *)0x632C,x","eCANB MDL5");
GEL_WatchAdd("*(long *)0x632E,x","eCANB MDH5");
}
hotmenu eCAN_B_Mailbox_6_to_7_Regs()
{
GEL_WatchAdd("*(long *)0x624C,x","eCANB LAM6");
GEL_WatchAdd("*(long *)0x628C,x","eCANB MOTS6");
GEL_WatchAdd("*(long *)0x62CC,x","eCANB MOTO6");
GEL_WatchAdd("*(long *)0x6330,x","eCANB MID6");
GEL_WatchAdd("*(long *)0x6332,x","eCANB MCF6");
GEL_WatchAdd("*(long *)0x6334,x","eCANB MDL6");
GEL_WatchAdd("*(long *)0x6336,x","eCANB MDH6");
GEL_WatchAdd("*(long *)0x624E,x","eCANB LAM7");
GEL_WatchAdd("*(long *)0x628E,x","eCANB MOTS7");
GEL_WatchAdd("*(long *)0x62CE,x","eCANB MOTO7");
GEL_WatchAdd("*(long *)0x6338,x","eCANB MID7");
GEL_WatchAdd("*(long *)0x633A,x","eCANB MCF7");
GEL_WatchAdd("*(long *)0x633C,x","eCANB MDL7");
GEL_WatchAdd("*(long *)0x633E,x","eCANB MDH7");
}
hotmenu eCAN_B_Mailbox_8_to_9_Regs()
{
GEL_WatchAdd("*(long *)0x6250,x","eCANB LAM8");
GEL_WatchAdd("*(long *)0x6290,x","eCANB MOTS8");
GEL_WatchAdd("*(long *)0x62D0,x","eCANB MOTO8");
GEL_WatchAdd("*(long *)0x6340,x","eCANB MID8");
GEL_WatchAdd("*(long *)0x6342,x","eCANB MCF8");
GEL_WatchAdd("*(long *)0x6344,x","eCANB MDL8");
GEL_WatchAdd("*(long *)0x6346,x","eCANB MDH8");
GEL_WatchAdd("*(long *)0x6252,x","eCANB LAM9");
GEL_WatchAdd("*(long *)0x6292,x","eCANB MOTS9");
GEL_WatchAdd("*(long *)0x62D2,x","eCANB MOTO9");
GEL_WatchAdd("*(long *)0x6348,x","eCANB MID9");
GEL_WatchAdd("*(long *)0x634A,x","eCANB MCF9");
GEL_WatchAdd("*(long *)0x634C,x","eCANB MDL9");
GEL_WatchAdd("*(long *)0x634E,x","eCANB MDH9");
}
hotmenu eCAN_B_Mailbox_10_to_11_Regs()
{
GEL_WatchAdd("*(long *)0x6254,x","eCANB LAM10");
GEL_WatchAdd("*(long *)0x6294,x","eCANB MOTS10");
GEL_WatchAdd("*(long *)0x62D4,x","eCANB MOTO10");
GEL_WatchAdd("*(long *)0x6350,x","eCANB MID10");
GEL_WatchAdd("*(long *)0x6352,x","eCANB MCF10");
GEL_WatchAdd("*(long *)0x6354,x","eCANB MDL10");
GEL_WatchAdd("*(long *)0x6356,x","eCANB MDH10");
GEL_WatchAdd("*(long *)0x6256,x","eCANB LAM11");
GEL_WatchAdd("*(long *)0x6296,x","eCANB MOTS11");
GEL_WatchAdd("*(long *)0x62D6,x","eCANB MOTO11");
GEL_WatchAdd("*(long *)0x6358,x","eCANB MID11");
GEL_WatchAdd("*(long *)0x635A,x","eCANB MCF11");
GEL_WatchAdd("*(long *)0x635C,x","eCANB MDL11");
GEL_WatchAdd("*(long *)0x635E,x","eCANB MDH11");
}
hotmenu eCAN_B_Mailbox_12_to_13_Regs()
{
GEL_WatchAdd("*(long *)0x6258,x","eCANB LAM12");
GEL_WatchAdd("*(long *)0x6298,x","eCANB MOTS12");
GEL_WatchAdd("*(long *)0x62D8,x","eCANB MOTO12");
GEL_WatchAdd("*(long *)0x6360,x","eCANB MID12");
GEL_WatchAdd("*(long *)0x6362,x","eCANB MCF12");
GEL_WatchAdd("*(long *)0x6364,x","eCANB MDL12");
GEL_WatchAdd("*(long *)0x6366,x","eCANB MDH12");
GEL_WatchAdd("*(long *)0x625A,x","eCANB LAM13");
GEL_WatchAdd("*(long *)0x629A,x","eCANB MOTS13");
GEL_WatchAdd("*(long *)0x62DA,x","eCANB MOTO13");
GEL_WatchAdd("*(long *)0x6368,x","eCANB MID13");
GEL_WatchAdd("*(long *)0x636A,x","eCANB MCF13");
GEL_WatchAdd("*(long *)0x636C,x","eCANB MDL13");
GEL_WatchAdd("*(long *)0x636E,x","eCANB MDH13");
}
hotmenu eCAN_B_Mailbox_14_to_15_Regs()
{
GEL_WatchAdd("*(long *)0x625C,x","eCANB LAM14");
GEL_WatchAdd("*(long *)0x629C,x","eCANB MOTS14");
GEL_WatchAdd("*(long *)0x62DC,x","eCANB MOTO14");
GEL_WatchAdd("*(long *)0x6370,x","eCANB MID14");
GEL_WatchAdd("*(long *)0x6372,x","eCANB MCF14");
GEL_WatchAdd("*(long *)0x6374,x","eCANB MDL14");
GEL_WatchAdd("*(long *)0x6376,x","eCANB MDH14");
GEL_WatchAdd("*(long *)0x625E,x","eCANB LAM15");
GEL_WatchAdd("*(long *)0x629E,x","eCANB MOTS15");
GEL_WatchAdd("*(long *)0x62DE,x","eCANB MOTO15");
GEL_WatchAdd("*(long *)0x6378,x","eCANB MID15");
GEL_WatchAdd("*(long *)0x637A,x","eCANB MCF15");
GEL_WatchAdd("*(long *)0x637C,x","eCANB MDL15");
GEL_WatchAdd("*(long *)0x637E,x","eCANB MDH15");
}
hotmenu eCAN_B_Mailbox_16_to_17_Regs()
{
GEL_WatchAdd("*(long *)0x6260,x","eCANB LAM16");
GEL_WatchAdd("*(long *)0x62A0,x","eCANB MOTS16");
GEL_WatchAdd("*(long *)0x62E0,x","eCANB MOTO16");
GEL_WatchAdd("*(long *)0x6380,x","eCANB MID16");
GEL_WatchAdd("*(long *)0x6382,x","eCANB MCF16");
GEL_WatchAdd("*(long *)0x6384,x","eCANB MDL16");
GEL_WatchAdd("*(long *)0x6386,x","eCANB MDH16");
GEL_WatchAdd("*(long *)0x6262,x","eCANB LAM17");
GEL_WatchAdd("*(long *)0x62A2,x","eCANB MOTS17");
GEL_WatchAdd("*(long *)0x62E2,x","eCANB MOTO17");
GEL_WatchAdd("*(long *)0x6388,x","eCANB MID17");
GEL_WatchAdd("*(long *)0x638A,x","eCANB MCF17");
GEL_WatchAdd("*(long *)0x638C,x","eCANB MDL17");
GEL_WatchAdd("*(long *)0x638E,x","eCANB MDH17");
}
hotmenu eCAN_B_Mailbox_18_to_19_Regs()
{
GEL_WatchAdd("*(long *)0x6264,x","eCANB LAM18");
GEL_WatchAdd("*(long *)0x62A4,x","eCANB MOTS18");
GEL_WatchAdd("*(long *)0x62E4,x","eCANB MOTO18");
GEL_WatchAdd("*(long *)0x6390,x","eCANB MID18");
GEL_WatchAdd("*(long *)0x6392,x","eCANB MCF18");
GEL_WatchAdd("*(long *)0x6394,x","eCANB MDL18");
GEL_WatchAdd("*(long *)0x6396,x","eCANB MDH18");
GEL_WatchAdd("*(long *)0x6266,x","eCANB LAM19");
GEL_WatchAdd("*(long *)0x62A6,x","eCANB MOTS19");
GEL_WatchAdd("*(long *)0x62E6,x","eCANB MOTO19");
GEL_WatchAdd("*(long *)0x6398,x","eCANB MID19");
GEL_WatchAdd("*(long *)0x639A,x","eCANB MCF19");
GEL_WatchAdd("*(long *)0x639C,x","eCANB MDL19");
GEL_WatchAdd("*(long *)0x639E,x","eCANB MDH19");
}
hotmenu eCAN_B_Mailbox_20_to_21_Regs()
{
GEL_WatchAdd("*(long *)0x6268,x","eCANB LAM20");
GEL_WatchAdd("*(long *)0x62A8,x","eCANB MOTS20");
GEL_WatchAdd("*(long *)0x62E8,x","eCANB MOTO20");
GEL_WatchAdd("*(long *)0x63A0,x","eCANB MID20");
GEL_WatchAdd("*(long *)0x63A2,x","eCANB MCF20");
GEL_WatchAdd("*(long *)0x63A4,x","eCANB MDL20");
GEL_WatchAdd("*(long *)0x63A6,x","eCANB MDH20");
GEL_WatchAdd("*(long *)0x626A,x","eCANB LAM21");
GEL_WatchAdd("*(long *)0x62AA,x","eCANB MOTS21");
GEL_WatchAdd("*(long *)0x62EA,x","eCANB MOTO21");
GEL_WatchAdd("*(long *)0x63A8,x","eCANB MID21");
GEL_WatchAdd("*(long *)0x63AA,x","eCANB MCF21");
GEL_WatchAdd("*(long *)0x63AC,x","eCANB MDL21");
GEL_WatchAdd("*(long *)0x63AE,x","eCANB MDH21");
}
hotmenu eCAN_B_Mailbox_22_to_23_Regs()
{
GEL_WatchAdd("*(long *)0x626C,x","eCANB LAM22");
GEL_WatchAdd("*(long *)0x62AC,x","eCANB MOTS22");
GEL_WatchAdd("*(long *)0x62EC,x","eCANB MOTO22");
GEL_WatchAdd("*(long *)0x63B0,x","eCANB MID22");
GEL_WatchAdd("*(long *)0x63B2,x","eCANB MCF22");
GEL_WatchAdd("*(long *)0x63B4,x","eCANB MDL22");
GEL_WatchAdd("*(long *)0x63B6,x","eCANB MDH22");
GEL_WatchAdd("*(long *)0x626E,x","eCANB LAM23");
GEL_WatchAdd("*(long *)0x62AE,x","eCANB MOTS23");
GEL_WatchAdd("*(long *)0x62EE,x","eCANB MOTO23");
GEL_WatchAdd("*(long *)0x63B8,x","eCANB MID23");
GEL_WatchAdd("*(long *)0x63BA,x","eCANB MCF23");
GEL_WatchAdd("*(long *)0x63BC,x","eCANB MDL23");
GEL_WatchAdd("*(long *)0x63BE,x","eCANB MDH23");
}
hotmenu eCAN_B_Mailbox_24_to_25_Regs()
{
GEL_WatchAdd("*(long *)0x6270,x","eCANB LAM24");
GEL_WatchAdd("*(long *)0x62B0,x","eCANB MOTS24");
GEL_WatchAdd("*(long *)0x62F0,x","eCANB MOTO24");
GEL_WatchAdd("*(long *)0x63C0,x","eCANB MID24");
GEL_WatchAdd("*(long *)0x63C2,x","eCANB MCF24");
GEL_WatchAdd("*(long *)0x63C4,x","eCANB MDL24");
GEL_WatchAdd("*(long *)0x63C6,x","eCANB MDH24");
GEL_WatchAdd("*(long *)0x6272,x","eCANB LAM25");
GEL_WatchAdd("*(long *)0x62B2,x","eCANB MOTS25");
GEL_WatchAdd("*(long *)0x62F2,x","eCANB MOTO25");
GEL_WatchAdd("*(long *)0x63C8,x","eCANB MID25");
GEL_WatchAdd("*(long *)0x63CA,x","eCANB MCF25");
GEL_WatchAdd("*(long *)0x63CC,x","eCANB MDL25");
GEL_WatchAdd("*(long *)0x63CE,x","eCANB MDH25");
}
hotmenu eCAN_B_Mailbox_26_to_27_Regs()
{
GEL_WatchAdd("*(long *)0x6274,x","eCANB LAM26");
GEL_WatchAdd("*(long *)0x62B4,x","eCANB MOTS26");
GEL_WatchAdd("*(long *)0x62F4,x","eCANB MOTO26");
GEL_WatchAdd("*(long *)0x63D0,x","eCANB MID26");
GEL_WatchAdd("*(long *)0x63D2,x","eCANB MCF26");
GEL_WatchAdd("*(long *)0x63D4,x","eCANB MDL26");
GEL_WatchAdd("*(long *)0x63D6,x","eCANB MDH26");
GEL_WatchAdd("*(long *)0x6276,x","eCANB LAM27");
GEL_WatchAdd("*(long *)0x62B6,x","eCANB MOTS27");
GEL_WatchAdd("*(long *)0x62F6,x","eCANB MOTO27");
GEL_WatchAdd("*(long *)0x63D8,x","eCANB MID27");
GEL_WatchAdd("*(long *)0x63DA,x","eCANB MCF27");
GEL_WatchAdd("*(long *)0x63DC,x","eCANB MDL27");
GEL_WatchAdd("*(long *)0x63DE,x","eCANB MDH27");
}
hotmenu eCAN_B_Mailbox_28_to_29_Regs()
{
GEL_WatchAdd("*(long *)0x6278,x","eCANB LAM28");
GEL_WatchAdd("*(long *)0x62B8,x","eCANB MOTS28");
GEL_WatchAdd("*(long *)0x62F8,x","eCANB MOTO28");
GEL_WatchAdd("*(long *)0x63E0,x","eCANB MID28");
GEL_WatchAdd("*(long *)0x63E2,x","eCANB MCF28");
GEL_WatchAdd("*(long *)0x63E4,x","eCANB MDL28");
GEL_WatchAdd("*(long *)0x63E6,x","eCANB MDH28");
GEL_WatchAdd("*(long *)0x627A,x","eCANB LAM29");
GEL_WatchAdd("*(long *)0x62BA,x","eCANB MOTS29");
GEL_WatchAdd("*(long *)0x62FA,x","eCANB MOTO29");
GEL_WatchAdd("*(long *)0x63E8,x","eCANB MID29");
GEL_WatchAdd("*(long *)0x63EA,x","eCANB MCF29");
GEL_WatchAdd("*(long *)0x63EC,x","eCANB MDL29");
GEL_WatchAdd("*(long *)0x63EE,x","eCANB MDH29");
}
hotmenu eCAN_B_Mailbox_30_to_31_Regs()
{
GEL_WatchAdd("*(long *)0x627C,x","eCANB LAM30");
GEL_WatchAdd("*(long *)0x62BC,x","eCANB MOTS30");
GEL_WatchAdd("*(long *)0x62FC,x","eCANB MOTO30");
GEL_WatchAdd("*(long *)0x63F0,x","eCANB MID30");
GEL_WatchAdd("*(long *)0x63F2,x","eCANB MCF30");
GEL_WatchAdd("*(long *)0x63F4,x","eCANB MDL30");
GEL_WatchAdd("*(long *)0x63F6,x","eCANB MDH30");
GEL_WatchAdd("*(long *)0x627E,x","eCANB LAM31");
GEL_WatchAdd("*(long *)0x62BE,x","eCANB MOTS31");
GEL_WatchAdd("*(long *)0x62FE,x","eCANB MOTO31");
GEL_WatchAdd("*(long *)0x63F8,x","eCANB MID31");
GEL_WatchAdd("*(long *)0x63FA,x","eCANB MCF31");
GEL_WatchAdd("*(long *)0x63FC,x","eCANB MDL31");
GEL_WatchAdd("*(long *)0x63FE,x","eCANB MDH31");
}
/********************************************************************/
/* Enhanced Capture Registers */
/********************************************************************/
menuitem "Watch eCAP Registers";
hotmenu eCAP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A00,x","eCAP1 TSCNT");
GEL_WatchAdd("*(long *)0x6A02,x","eCAP1 CNTPHS");
GEL_WatchAdd("*(long *)0x6A04,x","eCAP1 CAP1");
GEL_WatchAdd("*(long *)0x6A06,x","eCAP1 CAP2");
GEL_WatchAdd("*(long *)0x6A08,x","eCAP1 CAP3");
GEL_WatchAdd("*(long *)0x6A0A,x","eCAP1 CAP4");
GEL_WatchAdd("*0x6A14,x","eCAP1 ECCTL1");
GEL_WatchAdd("*0x6A15,x","eCAP1 ECCTL2");
GEL_WatchAdd("*0x6A16,x","eCAP1 ECEINT");
GEL_WatchAdd("*0x6A17,x","eCAP1 ECFLG");
GEL_WatchAdd("*0x6A18,x","eCAP1 ECCLR");
GEL_WatchAdd("*0x6A19,x","eCAP1 ECFRC");
}
hotmenu eCAP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A20,x","eCAP2 TSCNT");
GEL_WatchAdd("*(long *)0x6A22,x","eCAP2 CNTPHS");
GEL_WatchAdd("*(long *)0x6A24,x","eCAP2 CAP1");
GEL_WatchAdd("*(long *)0x6A26,x","eCAP2 CAP2");
GEL_WatchAdd("*(long *)0x6A28,x","eCAP2 CAP3");
GEL_WatchAdd("*(long *)0x6A2A,x","eCAP2 CAP4");
GEL_WatchAdd("*0x6A34,x","eCAP2 ECCTL1");
GEL_WatchAdd("*0x6A35,x","eCAP2 ECCTL2");
GEL_WatchAdd("*0x6A36,x","eCAP2 ECEINT");
GEL_WatchAdd("*0x6A37,x","eCAP2 ECFLG");
GEL_WatchAdd("*0x6A38,x","eCAP2 ECCLR");
GEL_WatchAdd("*0x6A39,x","eCAP2 ECFRC");
}
hotmenu eCAP3_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A40,x","eCAP3 TSCNT");
GEL_WatchAdd("*(long *)0x6A42,x","eCAP3 CNTPHS");
GEL_WatchAdd("*(long *)0x6A44,x","eCAP3 CAP1");
GEL_WatchAdd("*(long *)0x6A46,x","eCAP3 CAP2");
GEL_WatchAdd("*(long *)0x6A48,x","eCAP3 CAP3");
GEL_WatchAdd("*(long *)0x6A4A,x","eCAP3 CAP4");
GEL_WatchAdd("*0x6A54,x","eCAP3 ECCTL1");
GEL_WatchAdd("*0x6A55,x","eCAP3 ECCTL2");
GEL_WatchAdd("*0x6A56,x","eCAP3 ECEINT");
GEL_WatchAdd("*0x6A57,x","eCAP3 ECFLG");
GEL_WatchAdd("*0x6A58,x","eCAP3 ECCLR");
GEL_WatchAdd("*0x6A59,x","eCAP3 ECFRC");
}
hotmenu eCAP4_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A60,x","eCAP4 TSCNT");
GEL_WatchAdd("*(long *)0x6A62,x","eCAP4 CNTPHS");
GEL_WatchAdd("*(long *)0x6A64,x","eCAP4 CAP1");
GEL_WatchAdd("*(long *)0x6A66,x","eCAP4 CAP2");
GEL_WatchAdd("*(long *)0x6A68,x","eCAP4 CAP3");
GEL_WatchAdd("*(long *)0x6A6A,x","eCAP4 CAP4");
GEL_WatchAdd("*0x6A74,x","eCAP4 ECCTL1");
GEL_WatchAdd("*0x6A75,x","eCAP4 ECCTL2");
GEL_WatchAdd("*0x6A76,x","eCAP4 ECEINT");
GEL_WatchAdd("*0x6A77,x","eCAP4 ECFLG");
GEL_WatchAdd("*0x6A78,x","eCAP4 ECCLR");
GEL_WatchAdd("*0x6A79,x","eCAP4 ECFRC");
}
hotmenu eCAP5_All_Regs()
{
GEL_WatchAdd("*(long *)0x6A80,x","eCAP5 TSCNT");
GEL_WatchAdd("*(long *)0x6A82,x","eCAP5 CNTPHS");
GEL_WatchAdd("*(long *)0x6A84,x","eCAP5 CAP1");
GEL_WatchAdd("*(long *)0x6A86,x","eCAP5 CAP2");
GEL_WatchAdd("*(long *)0x6A88,x","eCAP5 CAP3");
GEL_WatchAdd("*(long *)0x6A8A,x","eCAP5 CAP4");
GEL_WatchAdd("*0x6A94,x","eCAP5 ECCTL1");
GEL_WatchAdd("*0x6A95,x","eCAP5 ECCTL2");
GEL_WatchAdd("*0x6A96,x","eCAP5 ECEINT");
GEL_WatchAdd("*0x6A97,x","eCAP5 ECFLG");
GEL_WatchAdd("*0x6A98,x","eCAP5 ECCLR");
GEL_WatchAdd("*0x6A99,x","eCAP5 ECFRC");
}
hotmenu eCAP6_All_Regs()
{
GEL_WatchAdd("*(long *)0x6AA0,x","eCAP6 TSCNT");
GEL_WatchAdd("*(long *)0x6AA2,x","eCAP6 CNTPHS");
GEL_WatchAdd("*(long *)0x6AA4,x","eCAP6 CAP1");
GEL_WatchAdd("*(long *)0x6AA6,x","eCAP6 CAP2");
GEL_WatchAdd("*(long *)0x6AA8,x","eCAP6 CAP3");
GEL_WatchAdd("*(long *)0x6AAA,x","eCAP6 CAP4");
GEL_WatchAdd("*0x6AB4,x","eCAP6 ECCTL1");
GEL_WatchAdd("*0x6AB5,x","eCAP6 ECCTL2");
GEL_WatchAdd("*0x6AB6,x","eCAP6 ECEINT");
GEL_WatchAdd("*0x6AB7,x","eCAP6 ECFLG");
GEL_WatchAdd("*0x6AB8,x","eCAP6 ECCLR");
GEL_WatchAdd("*0x6AB9,x","eCAP6 ECFRC");
}
/********************************************************************/
/* Enhanced PWM Registers */
/********************************************************************/
menuitem "Watch ePWM Registers";
hotmenu ePWM1_All_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6813,x","ePWM1 TZDCSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
GEL_WatchAdd("*0x681E,x","ePWM1 PCCTL");
GEL_WatchAdd("*0x6820,x","ePWM1 HRCNFG");
}
hotmenu ePWM1_TB_Regs()
{
GEL_WatchAdd("*0x6800,x","ePWM1 TBCTL");
GEL_WatchAdd("*0x6801,x","ePWM1 TBSTS");
GEL_WatchAdd("*0x6802,x","ePWM1 TBPHSHR");
GEL_WatchAdd("*0x6803,x","ePWM1 TBPHS");
GEL_WatchAdd("*0x6804,x","ePWM1 TBCTR");
GEL_WatchAdd("*0x6805,x","ePWM1 TBPRD");
}
hotmenu ePWM1_CMP_Regs()
{
GEL_WatchAdd("*0x6807,x","ePWM1 CMPCTL");
GEL_WatchAdd("*0x6808,x","ePWM1 CMPAHR");
GEL_WatchAdd("*0x6809,x","ePWM1 CMPA");
GEL_WatchAdd("*0x680A,x","ePWM1 CMPB");
}
hotmenu ePWM1_AQ_Regs()
{
GEL_WatchAdd("*0x680B,x","ePWM1 AQCTLA");
GEL_WatchAdd("*0x680C,x","ePWM1 AQCTLB");
GEL_WatchAdd("*0x680D,x","ePWM1 AQSFRC");
GEL_WatchAdd("*0x680E,x","ePWM1 AQCSFRC");
}
hotmenu ePWM1_DB_Regs()
{
GEL_WatchAdd("*0x680F,x","ePWM1 DBCTL");
GEL_WatchAdd("*0x6810,x","ePWM1 DBRED");
GEL_WatchAdd("*0x6811,x","ePWM1 DBFED");
}
hotmenu ePWM1_TZ_Regs()
{
GEL_WatchAdd("*0x6812,x","ePWM1 TZSEL");
GEL_WatchAdd("*0x6814,x","ePWM1 TZCTL");
GEL_WatchAdd("*0x6815,x","ePWM1 TZEINT");
GEL_WatchAdd("*0x6816,x","ePWM1 TZFLG");
GEL_WatchAdd("*0x6817,x","ePWM1 TZCLR");
GEL_WatchAdd("*0x6818,x","ePWM1 TZFRC");
}
hotmenu ePWM1_ET_Regs()
{
GEL_WatchAdd("*0x6819,x","ePWM1 ETSEL");
GEL_WatchAdd("*0x681A,x","ePWM1 ETPS");
GEL_WatchAdd("*0x681B,x","ePWM1 ETFLG");
GEL_WatchAdd("*0x681C,x","ePWM1 ETCLR");
GEL_WatchAdd("*0x681D,x","ePWM1 ETFRC");
}
hotmenu ePWM2_All_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6853,x","ePWM2 TZDCSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
GEL_WatchAdd("*0x685E,x","ePWM2 PCCTL");
GEL_WatchAdd("*0x6860,x","ePWM2 HRCNFG");
}
hotmenu ePWM2_TB_Regs()
{
GEL_WatchAdd("*0x6840,x","ePWM2 TBCTL");
GEL_WatchAdd("*0x6841,x","ePWM2 TBSTS");
GEL_WatchAdd("*0x6842,x","ePWM2 TBPHSHR");
GEL_WatchAdd("*0x6843,x","ePWM2 TBPHS");
GEL_WatchAdd("*0x6844,x","ePWM2 TBCTR");
GEL_WatchAdd("*0x6845,x","ePWM2 TBPRD");
}
hotmenu ePWM2_CMP_Regs()
{
GEL_WatchAdd("*0x6847,x","ePWM2 CMPCTL");
GEL_WatchAdd("*0x6848,x","ePWM2 CMPAHR");
GEL_WatchAdd("*0x6849,x","ePWM2 CMPA");
GEL_WatchAdd("*0x684A,x","ePWM2 CMPB");
}
hotmenu ePWM2_AQ_Regs()
{
GEL_WatchAdd("*0x684B,x","ePWM2 AQCTLA");
GEL_WatchAdd("*0x684C,x","ePWM2 AQCTLB");
GEL_WatchAdd("*0x684D,x","ePWM2 AQSFRC");
GEL_WatchAdd("*0x684E,x","ePWM2 AQCSFRC");
}
hotmenu ePWM2_DB_Regs()
{
GEL_WatchAdd("*0x684F,x","ePWM2 DBCTL");
GEL_WatchAdd("*0x6850,x","ePWM2 DBRED");
GEL_WatchAdd("*0x6851,x","ePWM2 DBFED");
}
hotmenu ePWM2_TZ_Regs()
{
GEL_WatchAdd("*0x6852,x","ePWM2 TZSEL");
GEL_WatchAdd("*0x6854,x","ePWM2 TZCTL");
GEL_WatchAdd("*0x6855,x","ePWM2 TZEINT");
GEL_WatchAdd("*0x6856,x","ePWM2 TZFLG");
GEL_WatchAdd("*0x6857,x","ePWM2 TZCLR");
GEL_WatchAdd("*0x6858,x","ePWM2 TZFRC");
}
hotmenu ePWM2_ET_Regs()
{
GEL_WatchAdd("*0x6859,x","ePWM2 ETSEL");
GEL_WatchAdd("*0x685A,x","ePWM2 ETPS");
GEL_WatchAdd("*0x685B,x","ePWM2 ETFLG");
GEL_WatchAdd("*0x685C,x","ePWM2 ETCLR");
GEL_WatchAdd("*0x685D,x","ePWM2 ETFRC");
}
hotmenu ePWM3_All_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6893,x","ePWM3 TZDCSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
GEL_WatchAdd("*0x689E,x","ePWM3 PCCTL");
GEL_WatchAdd("*0x68A0,x","ePWM3 HRCNFG");
}
hotmenu ePWM3_TB_Regs()
{
GEL_WatchAdd("*0x6880,x","ePWM3 TBCTL");
GEL_WatchAdd("*0x6881,x","ePWM3 TBSTS");
GEL_WatchAdd("*0x6882,x","ePWM3 TBPHSHR");
GEL_WatchAdd("*0x6883,x","ePWM3 TBPHS");
GEL_WatchAdd("*0x6884,x","ePWM3 TBCTR");
GEL_WatchAdd("*0x6885,x","ePWM3 TBPRD");
}
hotmenu ePWM3_CMP_Regs()
{
GEL_WatchAdd("*0x6887,x","ePWM3 CMPCTL");
GEL_WatchAdd("*0x6888,x","ePWM3 CMPAHR");
GEL_WatchAdd("*0x6889,x","ePWM3 CMPA");
GEL_WatchAdd("*0x688A,x","ePWM3 CMPB");
}
hotmenu ePWM3_AQ_Regs()
{
GEL_WatchAdd("*0x688B,x","ePWM3 AQCTLA");
GEL_WatchAdd("*0x688C,x","ePWM3 AQCTLB");
GEL_WatchAdd("*0x688D,x","ePWM3 AQSFRC");
GEL_WatchAdd("*0x688E,x","ePWM3 AQCSFRC");
}
hotmenu ePWM3_DB_Regs()
{
GEL_WatchAdd("*0x688F,x","ePWM3 DBCTL");
GEL_WatchAdd("*0x6890,x","ePWM3 DBRED");
GEL_WatchAdd("*0x6891,x","ePWM3 DBFED");
}
hotmenu ePWM3_TZ_Regs()
{
GEL_WatchAdd("*0x6892,x","ePWM3 TZSEL");
GEL_WatchAdd("*0x6894,x","ePWM3 TZCTL");
GEL_WatchAdd("*0x6895,x","ePWM3 TZEINT");
GEL_WatchAdd("*0x6896,x","ePWM3 TZFLG");
GEL_WatchAdd("*0x6897,x","ePWM3 TZCLR");
GEL_WatchAdd("*0x6898,x","ePWM3 TZFRC");
}
hotmenu ePWM3_ET_Regs()
{
GEL_WatchAdd("*0x6899,x","ePWM3 ETSEL");
GEL_WatchAdd("*0x689A,x","ePWM3 ETPS");
GEL_WatchAdd("*0x689B,x","ePWM3 ETFLG");
GEL_WatchAdd("*0x689C,x","ePWM3 ETCLR");
GEL_WatchAdd("*0x689D,x","ePWM3 ETFRC");
}
hotmenu ePWM4_All_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D3,x","ePWM4 TZDCSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
GEL_WatchAdd("*0x68DE,x","ePWM4 PCCTL");
GEL_WatchAdd("*0x68E0,x","ePWM4 HRCNFG");
}
hotmenu ePWM4_TB_Regs()
{
GEL_WatchAdd("*0x68C0,x","ePWM4 TBCTL");
GEL_WatchAdd("*0x68C1,x","ePWM4 TBSTS");
GEL_WatchAdd("*0x68C2,x","ePWM4 TBPHSHR");
GEL_WatchAdd("*0x68C3,x","ePWM4 TBPHS");
GEL_WatchAdd("*0x68C4,x","ePWM4 TBCTR");
GEL_WatchAdd("*0x68C5,x","ePWM4 TBPRD");
}
hotmenu ePWM4_CMP_Regs()
{
GEL_WatchAdd("*0x68C7,x","ePWM4 CMPCTL");
GEL_WatchAdd("*0x68C8,x","ePWM4 CMPAHR");
GEL_WatchAdd("*0x68C9,x","ePWM4 CMPA");
GEL_WatchAdd("*0x68CA,x","ePWM4 CMPB");
}
hotmenu ePWM4_AQ_Regs()
{
GEL_WatchAdd("*0x68CB,x","ePWM4 AQCTLA");
GEL_WatchAdd("*0x68CC,x","ePWM4 AQCTLB");
GEL_WatchAdd("*0x68CD,x","ePWM4 AQSFRC");
GEL_WatchAdd("*0x68CE,x","ePWM4 AQCSFRC");
}
hotmenu ePWM4_DB_Regs()
{
GEL_WatchAdd("*0x68CF,x","ePWM4 DBCTL");
GEL_WatchAdd("*0x68D0,x","ePWM4 DBRED");
GEL_WatchAdd("*0x68D1,x","ePWM4 DBFED");
}
hotmenu ePWM4_TZ_Regs()
{
GEL_WatchAdd("*0x68D2,x","ePWM4 TZSEL");
GEL_WatchAdd("*0x68D4,x","ePWM4 TZCTL");
GEL_WatchAdd("*0x68D5,x","ePWM4 TZEINT");
GEL_WatchAdd("*0x68D6,x","ePWM4 TZFLG");
GEL_WatchAdd("*0x68D7,x","ePWM4 TZCLR");
GEL_WatchAdd("*0x68D8,x","ePWM4 TZFRC");
}
hotmenu ePWM4_ET_Regs()
{
GEL_WatchAdd("*0x68D9,x","ePWM4 ETSEL");
GEL_WatchAdd("*0x68DA,x","ePWM4 ETPS");
GEL_WatchAdd("*0x68DB,x","ePWM4 ETFLG");
GEL_WatchAdd("*0x68DC,x","ePWM4 ETCLR");
GEL_WatchAdd("*0x68DD,x","ePWM4 ETFRC");
}
hotmenu ePWM5_All_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6913,x","ePWM5 TZDCSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
GEL_WatchAdd("*0x691E,x","ePWM5 PCCTL");
GEL_WatchAdd("*0x6920,x","ePWM5 HRCNFG");
}
hotmenu ePWM5_TB_Regs()
{
GEL_WatchAdd("*0x6900,x","ePWM5 TBCTL");
GEL_WatchAdd("*0x6901,x","ePWM5 TBSTS");
GEL_WatchAdd("*0x6902,x","ePWM5 TBPHSHR");
GEL_WatchAdd("*0x6903,x","ePWM5 TBPHS");
GEL_WatchAdd("*0x6904,x","ePWM5 TBCTR");
GEL_WatchAdd("*0x6905,x","ePWM5 TBPRD");
}
hotmenu ePWM5_CMP_Regs()
{
GEL_WatchAdd("*0x6907,x","ePWM5 CMPCTL");
GEL_WatchAdd("*0x6908,x","ePWM5 CMPAHR");
GEL_WatchAdd("*0x6909,x","ePWM5 CMPA");
GEL_WatchAdd("*0x690A,x","ePWM5 CMPB");
}
hotmenu ePWM5_AQ_Regs()
{
GEL_WatchAdd("*0x690B,x","ePWM5 AQCTLA");
GEL_WatchAdd("*0x690C,x","ePWM5 AQCTLB");
GEL_WatchAdd("*0x690D,x","ePWM5 AQSFRC");
GEL_WatchAdd("*0x690E,x","ePWM5 AQCSFRC");
}
hotmenu ePWM5_DB_Regs()
{
GEL_WatchAdd("*0x690F,x","ePWM5 DBCTL");
GEL_WatchAdd("*0x6910,x","ePWM5 DBRED");
GEL_WatchAdd("*0x6911,x","ePWM5 DBFED");
}
hotmenu ePWM5_TZ_Regs()
{
GEL_WatchAdd("*0x6912,x","ePWM5 TZSEL");
GEL_WatchAdd("*0x6914,x","ePWM5 TZCTL");
GEL_WatchAdd("*0x6915,x","ePWM5 TZEINT");
GEL_WatchAdd("*0x6916,x","ePWM5 TZFLG");
GEL_WatchAdd("*0x6917,x","ePWM5 TZCLR");
GEL_WatchAdd("*0x6918,x","ePWM5 TZFRC");
}
hotmenu ePWM5_ET_Regs()
{
GEL_WatchAdd("*0x6919,x","ePWM5 ETSEL");
GEL_WatchAdd("*0x691A,x","ePWM5 ETPS");
GEL_WatchAdd("*0x691B,x","ePWM5 ETFLG");
GEL_WatchAdd("*0x691C,x","ePWM5 ETCLR");
GEL_WatchAdd("*0x691D,x","ePWM5 ETFRC");
}
hotmenu ePWM6_All_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6953,x","ePWM6 TZDCSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
GEL_WatchAdd("*0x695E,x","ePWM6 PCCTL");
GEL_WatchAdd("*0x6960,x","ePWM6 HRCNFG");
}
hotmenu ePWM6_TB_Regs()
{
GEL_WatchAdd("*0x6940,x","ePWM6 TBCTL");
GEL_WatchAdd("*0x6941,x","ePWM6 TBSTS");
GEL_WatchAdd("*0x6942,x","ePWM6 TBPHSHR");
GEL_WatchAdd("*0x6943,x","ePWM6 TBPHS");
GEL_WatchAdd("*0x6944,x","ePWM6 TBCTR");
GEL_WatchAdd("*0x6945,x","ePWM6 TBPRD");
}
hotmenu ePWM6_CMP_Regs()
{
GEL_WatchAdd("*0x6947,x","ePWM6 CMPCTL");
GEL_WatchAdd("*0x6948,x","ePWM6 CMPAHR");
GEL_WatchAdd("*0x6949,x","ePWM6 CMPA");
GEL_WatchAdd("*0x694A,x","ePWM6 CMPB");
}
hotmenu ePWM6_AQ_Regs()
{
GEL_WatchAdd("*0x694B,x","ePWM6 AQCTLA");
GEL_WatchAdd("*0x694C,x","ePWM6 AQCTLB");
GEL_WatchAdd("*0x694D,x","ePWM6 AQSFRC");
GEL_WatchAdd("*0x694E,x","ePWM6 AQCSFRC");
}
hotmenu ePWM6_DB_Regs()
{
GEL_WatchAdd("*0x694F,x","ePWM6 DBCTL");
GEL_WatchAdd("*0x6950,x","ePWM6 DBRED");
GEL_WatchAdd("*0x6951,x","ePWM6 DBFED");
}
hotmenu ePWM6_TZ_Regs()
{
GEL_WatchAdd("*0x6952,x","ePWM6 TZSEL");
GEL_WatchAdd("*0x6954,x","ePWM6 TZCTL");
GEL_WatchAdd("*0x6955,x","ePWM6 TZEINT");
GEL_WatchAdd("*0x6956,x","ePWM6 TZFLG");
GEL_WatchAdd("*0x6957,x","ePWM6 TZCLR");
GEL_WatchAdd("*0x6958,x","ePWM6 TZFRC");
}
hotmenu ePWM6_ET_Regs()
{
GEL_WatchAdd("*0x6959,x","ePWM6 ETSEL");
GEL_WatchAdd("*0x695A,x","ePWM6 ETPS");
GEL_WatchAdd("*0x695B,x","ePWM6 ETFLG");
GEL_WatchAdd("*0x695C,x","ePWM6 ETCLR");
GEL_WatchAdd("*0x695D,x","ePWM6 ETFRC");
}
/********************************************************************/
/* Enhanced EQEP Registers */
/********************************************************************/
menuitem "Watch eQEP"
hotmenu eQEP1_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B00,x","eQEP1 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B02,x","eQEP1 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B04,x","eQEP1 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B06,x","eQEP1 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B08,x","eQEP1 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B0A,x","eQEP1 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B0C,x","eQEP1 QPOSLAT");
GEL_WatchAdd("*(long *)0x6B0E,x","eQEP1 QUTMR");
GEL_WatchAdd("*(long *)0x6B10,x","eQEP1 QUPRD");
GEL_WatchAdd("*0x6B12,x","eQEP1 QWDTMR");
GEL_WatchAdd("*0x6B13,x","eQEP1 QWDPRD");
GEL_WatchAdd("*0x6B14,x","eQEP1 QDECCTL");
GEL_WatchAdd("*0x6B15,x","eQEP1 QEPCTL");
GEL_WatchAdd("*0x6B16,x","eQEP1 QCAPCTL");
GEL_WatchAdd("*0x6B17,x","eQEP1 QPOSCTL");
GEL_WatchAdd("*0x6B18,x","eQEP1 QEINT");
GEL_WatchAdd("*0x6B19,x","eQEP1 QFLG");
GEL_WatchAdd("*0x6B1A,x","eQEP1 QCLR");
GEL_WatchAdd("*0x6B1B,x","eQEP1 QFRC");
GEL_WatchAdd("*0x6B1C,x","eQEP1 QEPSTS");
GEL_WatchAdd("*0x6B1D,x","eQEP1 QCTMR");
GEL_WatchAdd("*0x6B1E,x","eQEP1 QCPRD");
GEL_WatchAdd("*0x6B1F,x","eQEP1 QCTMRLAT");
GEL_WatchAdd("*0x6B20,x","eQEP1 QCPRDLAT");
}
hotmenu eQEP2_All_Regs()
{
GEL_WatchAdd("*(long *)0x6B40,x","eQEP2 QPOSCNT");
GEL_WatchAdd("*(long *)0x6B42,x","eQEP2 QPOSINIT");
GEL_WatchAdd("*(long *)0x6B44,x","eQEP2 QPOSMAX");
GEL_WatchAdd("*(long *)0x6B46,x","eQEP2 QPOSCMP");
GEL_WatchAdd("*(long *)0x6B48,x","eQEP2 QPOSILAT");
GEL_WatchAdd("*(long *)0x6B4A,x","eQEP2 QPOSSLAT");
GEL_WatchAdd("*(long *)0x6B4C,x","eQEP2 QPOSLAT");
GEL_WatchAdd("(long *)*0x6B4E,x","eQEP2 QUTMR");
GEL_WatchAdd("*(long *)0x6B50,x","eQEP2 QUPRD");
GEL_WatchAdd("*0x6B52,x","eQEP2 QWDTMR");
GEL_WatchAdd("*0x6B53,x","eQEP2 QWDPRD");
GEL_WatchAdd("*0x6B54,x","eQEP2 QDECCTL");
GEL_WatchAdd("*0x6B55,x","eQEP2 QEPCTL");
GEL_WatchAdd("*0x6B56,x","eQEP2 QCAPCTL");
GEL_WatchAdd("*0x6B57,x","eQEP2 QPOSCTL");
GEL_WatchAdd("*0x6B58,x","eQEP2 QEINT");
GEL_WatchAdd("*0x6B59,x","eQEP2 QFLG");
GEL_WatchAdd("*0x6B5A,x","eQEP2 QCLR");
GEL_WatchAdd("*0x6B5B,x","eQEP2 QFRC");
GEL_WatchAdd("*0x6B5C,x","eQEP2 QEPSTS");
GEL_WatchAdd("*0x6B5D,x","eQEP2 QCTMR");
GEL_WatchAdd("*0x6B5E,x","eQEP2 QCPRD");
GEL_WatchAdd("*0x6B5F,x","eQEP2 QCTMRLAT");
GEL_WatchAdd("*0x6B60,x","eQEP2 QCPRDLAT");
}
/********************************************************************/
/* External Interface Registers */
/********************************************************************/
menuitem "Watch External Interface Registers";
hotmenu All_External_Interface_Regs()
{
GEL_WatchAdd("*(long *)0x0B20,x","XTIMING0");
GEL_WatchAdd("*(long *)0x0B2C,x","XTIMING6");
GEL_WatchAdd("*(long *)0x0B2E,x","XTIMING7");
GEL_WatchAdd("*(long *)0x0B34,x","XINTCNF2");
GEL_WatchAdd("*0x0B38,x","XBANK");
GEL_WatchAdd("*0x0B3A,x","XREVISION");
GEL_WatchAdd("*0x0B3D,x","XRESET");
}
/********************************************************************/
/* External Interrupt Registers */
/********************************************************************/
menuitem "Watch External Interrupt Registers";
hotmenu All_XINT_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
hotmenu XINT_Control_Regs()
{
GEL_WatchAdd("*0x7070,x","XINT1CR");
GEL_WatchAdd("*0x7071,x","XINT2CR");
GEL_WatchAdd("*0x7072,x","XINT3CR");
GEL_WatchAdd("*0x7073,x","XINT4CR");
GEL_WatchAdd("*0x7074,x","XINT5CR");
GEL_WatchAdd("*0x7075,x","XINT6CR");
GEL_WatchAdd("*0x7076,x","XINT7CR");
GEL_WatchAdd("*0x7077,x","XNMICR");
}
hotmenu XINT_Counter_Regs()
{
GEL_WatchAdd("*0x7078,x","XINT1CTR");
GEL_WatchAdd("*0x7079,x","XINT2CTR");
GEL_WatchAdd("*0x707F,x","XNMICTR");
}
/********************************************************************/
/* FPU Registers */
/********************************************************************/
menuitem "Watch FPU Registers"
hotmenu All_FPU_Single_Precision_Regs()
{
GEL_WatchAdd("RB");
GEL_WatchAdd("STF");
GEL_WatchAdd("R0H");
GEL_WatchAdd("R1H");
GEL_WatchAdd("R2H");
GEL_WatchAdd("R3H");
GEL_WatchAdd("R4H");
GEL_WatchAdd("R5H");
GEL_WatchAdd("R6H");
GEL_WatchAdd("R7H");
}
/********************************************************************/
/* GPIO Registers */
/********************************************************************/
menuitem "Watch GPIO Registers";
hotmenu All_GPIO_CONTROL_Regs()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
}
hotmenu All_GPIO_DATA_Regs()
{
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
hotmenu All_GPIO_INTERRUPT_Regs()
{
GEL_WatchAdd("*0x6FE0,x","GPIOXINT1SEL");
GEL_WatchAdd("*0x6FE1,x","GPIOXINT2SEL");
GEL_WatchAdd("*0x6FE2,x","GPIOXNMISEL");
GEL_WatchAdd("*0x6FE3,x","GPIOXINT3SEL");
GEL_WatchAdd("*0x6FE4,x","GPIOXINT4SEL");
GEL_WatchAdd("*0x6FE5,x","GPIOXINT5SEL");
GEL_WatchAdd("*0x6FE6,x","GPIOXINT6SEL");
GEL_WatchAdd("*0x6FE7,x","GPIOXINT7SEL");
GEL_WatchAdd("*(long *)0x6FE8,x","GPIOLPMSEL");
}
hotmenu All_GPA_Registers()
{
GEL_WatchAdd("*(long *)0x6F80,x","GPACTRL");
GEL_WatchAdd("*(long *)0x6F82,x","GPAQSEL1");
GEL_WatchAdd("*(long *)0x6F84,x","GPAQSEL2");
GEL_WatchAdd("*(long *)0x6F86,x","GPAMUX1");
GEL_WatchAdd("*(long *)0x6F88,x","GPAMUX2");
GEL_WatchAdd("*(long *)0x6F8A,x","GPADIR");
GEL_WatchAdd("*(long *)0x6F8C,x","GPAPUD");
GEL_WatchAdd("*(long *)0x6FC0,x","GPADAT");
GEL_WatchAdd("*(long *)0x6FC2,x","GPASET");
GEL_WatchAdd("*(long *)0x6FC4,x","GPACLEAR");
GEL_WatchAdd("*(long *)0x6FC6,x","GPATOGGLE");
}
hotmenu All_GPB_Registers()
{
GEL_WatchAdd("*(long *)0x6F90,x","GPBCTRL");
GEL_WatchAdd("*(long *)0x6F92,x","GPBQSEL1");
GEL_WatchAdd("*(long *)0x6F94,x","GPBQSEL2");
GEL_WatchAdd("*(long *)0x6F96,x","GPBMUX1");
GEL_WatchAdd("*(long *)0x6F98,x","GPBMUX2");
GEL_WatchAdd("*(long *)0x6F9A,x","GPBDIR");
GEL_WatchAdd("*(long *)0x6F9C,x","GPBPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
}
hotmenu All_GPC_Registers()
{
GEL_WatchAdd("*(long *)0x6FA6,x","GPCMUX1");
GEL_WatchAdd("*(long *)0x6FA8,x","GPCMUX2");
GEL_WatchAdd("*(long *)0x6FAA,x","GPCDIR");
GEL_WatchAdd("*(long *)0x6FAC,x","GPCPUD");
GEL_WatchAdd("*(long *)0x6FC8,x","GPBDAT");
GEL_WatchAdd("*(long *)0x6FCA,x","GPBSET");
GEL_WatchAdd("*(long *)0x6FCC,x","GPBCLEAR");
GEL_WatchAdd("*(long *)0x6FCE,x","GPBTOGGLE");
GEL_WatchAdd("*(long *)0x6FD0,x","GPCDAT");
GEL_WatchAdd("*(long *)0x6FD2,x","GPCSET");
GEL_WatchAdd("*(long *)0x6FD4,x","GPCCLEAR");
GEL_WatchAdd("*(long *)0x6FD6,x","GPCTOGGLE");
}
/********************************************************************/
/* Multichannel Serial Port Registers */
/********************************************************************/
menuitem "Watch McBSP Registers";
hotmenu All_McBSP_A_Regs()
{
GEL_WatchAdd("*0x5000,x","McBSPA DRR2");
GEL_WatchAdd("*0x5001,x","McBSPA DRR1");
GEL_WatchAdd("*0x5002,x","McBSPA DXR2");
GEL_WatchAdd("*0x5003,x","McBSPA DXR1");
GEL_WatchAdd("*0x5004,x","McBSPA SPCR2");
GEL_WatchAdd("*0x5005,x","McBSPA SPCR1");
GEL_WatchAdd("*0x5006,x","McBSPA RCR2");
GEL_WatchAdd("*0x5007,x","McBSPA RCR1");
GEL_WatchAdd("*0x5008,x","McBSPA XCR2");
GEL_WatchAdd("*0x5009,x","McBSPA XCR1");
GEL_WatchAdd("*0x500A,x","McBSPA SRGR2");
GEL_WatchAdd("*0x500B,x","McBSPA SRGR1");
GEL_WatchAdd("*0x500C,x","McBSPA MCR2");
GEL_WatchAdd("*0x500D,x","McBSPA MCR1");
GEL_WatchAdd("*0x500E,x","McBSPA RCERA");
GEL_WatchAdd("*0x500F,x","McBSPA RCERB");
GEL_WatchAdd("*0x5010,x","McBSPA XCERA");
GEL_WatchAdd("*0x5011,x","McBSPA XCERB");
GEL_WatchAdd("*0x5012,x","McBSPA PCR1");
GEL_WatchAdd("*0x5013,x","McBSPA RCERC");
GEL_WatchAdd("*0x5014,x","McBSPA RCERD");
GEL_WatchAdd("*0x5015,x","McBSPA XCERC");
GEL_WatchAdd("*0x5016,x","McBSPA XCERD");
GEL_WatchAdd("*0x5017,x","McBSPA RCERE");
GEL_WatchAdd("*0x5018,x","McBSPA RCERF");
GEL_WatchAdd("*0x5019,x","McBSPA XCERE");
GEL_WatchAdd("*0x501A,x","McBSPA XCERF");
GEL_WatchAdd("*0x501B,x","McBSPA RCERG");
GEL_WatchAdd("*0x501C,x","McBSPA RCERH");
GEL_WatchAdd("*0x501D,x","McBSPA XCERG");
GEL_WatchAdd("*0x501E,x","McBSPA XCERH");
GEL_WatchAdd("*0x5023,x","McBSPA MFFINT");
GEL_WatchAdd("*0x503F,x","McBSPA Revision");
}
hotmenu All_McBSP_B_Regs()
{
GEL_WatchAdd("*0x5040,x","McBSPB DRR2");
GEL_WatchAdd("*0x5041,x","McBSPB DRR1");
GEL_WatchAdd("*0x5042,x","McBSPB DXR2");
GEL_WatchAdd("*0x5043,x","McBSPB DXR1");
GEL_WatchAdd("*0x5044,x","McBSPB SPCR2");
GEL_WatchAdd("*0x5045,x","McBSPB SPCR1");
GEL_WatchAdd("*0x5046,x","McBSPB RCR2");
GEL_WatchAdd("*0x5047,x","McBSPB RCR1");
GEL_WatchAdd("*0x5048,x","McBSPB XCR2");
GEL_WatchAdd("*0x5049,x","McBSPB XCR1");
GEL_WatchAdd("*0x504A,x","McBSPB SRGR2");
GEL_WatchAdd("*0x504B,x","McBSPB SRGR1");
GEL_WatchAdd("*0x504C,x","McBSPB MCR2");
GEL_WatchAdd("*0x504D,x","McBSPB MCR1");
GEL_WatchAdd("*0x504E,x","McBSPB RCERA");
GEL_WatchAdd("*0x504F,x","McBSPB RCERB");
GEL_WatchAdd("*0x5050,x","McBSPB XCERA");
GEL_WatchAdd("*0x5051,x","McBSPB XCERB");
GEL_WatchAdd("*0x5052,x","McBSPB PCR1");
GEL_WatchAdd("*0x5053,x","McBSPB RCERC");
GEL_WatchAdd("*0x5054,x","McBSPB RCERD");
GEL_WatchAdd("*0x5055,x","McBSPB XCERC");
GEL_WatchAdd("*0x5056,x","McBSPB XCERD");
GEL_WatchAdd("*0x5057,x","McBSPB RCERE");
GEL_WatchAdd("*0x5058,x","McBSPB RCERF");
GEL_WatchAdd("*0x5059,x","McBSPB XCERE");
GEL_WatchAdd("*0x505A,x","McBSPB XCERF");
GEL_WatchAdd("*0x505B,x","McBSPB RCERG");
GEL_WatchAdd("*0x505C,x","McBSPB RCERH");
GEL_WatchAdd("*0x505D,x","McBSPB XCERG");
GEL_WatchAdd("*0x505E,x","McBSPB XCERH");
GEL_WatchAdd("*0x5063,x","McBSPB MFFINT");
GEL_WatchAdd("*0x506F,x","McBSPB Revision");
}
/********************************************************************/
/* I2C Registers */
/********************************************************************/
menuitem "Watch I2C Registers";
hotmenu All_I2C_Regs()
{
GEL_WatchAdd("*0x7900,x","I2COAR");
GEL_WatchAdd("*0x7901,x","I2CIER");
GEL_WatchAdd("*0x7902,x","I2CSTR");
GEL_WatchAdd("*0x7903,x","I2CCLKL");
GEL_WatchAdd("*0x7904,x","I2CCLKH");
GEL_WatchAdd("*0x7905,x","I2CCNT");
GEL_WatchAdd("*0x7906,x","I2CDRR");
GEL_WatchAdd("*0x7907,x","I2CSAR");
GEL_WatchAdd("*0x7908,x","I2CDXR");
GEL_WatchAdd("*0x7909,x","I2CMDR");
GEL_WatchAdd("*0x790A,x","I2CISRC");
GEL_WatchAdd("*0x790C,x","I2CPSC");
GEL_WatchAdd("*0x7920,x","I2CFFTX");
GEL_WatchAdd("*0x7921,x","I2CFFRX");
}
/********************************************************************/
/* Peripheral Interrupt Expansion Registers */
/********************************************************************/
menuitem "Watch Peripheral Interrupt Expansion Registers";
hotmenu All_PIE_Regs()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
GEL_WatchAdd("*0x0CE1,x","PIEACK");
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
hotmenu PIECTRL()
{
GEL_WatchAdd("*0x0CE0,x","PIECTRL");
}
hotmenu PIEACK()
{
GEL_WatchAdd("*0x0CE1,x","PIEACK");
}
hotmenu PIEIER1_and_PIEIFR1()
{
GEL_WatchAdd("*0x0CE2,x","PIEIER1");
GEL_WatchAdd("*0x0CE3,x","PIEIFR1");
}
hotmenu PIEIER2_and_PIEIFR2()
{
GEL_WatchAdd("*0x0CE4,x","PIEIER2");
GEL_WatchAdd("*0x0CE5,x","PIEIFR2");
}
hotmenu PIEIER3_and_PIEIFR3()
{
GEL_WatchAdd("*0x0CE6,x","PIEIER3");
GEL_WatchAdd("*0x0CE7,x","PIEIFR3");
}
hotmenu PIEIER4_and_PIEIFR4()
{
GEL_WatchAdd("*0x0CE8,x","PIEIER4");
GEL_WatchAdd("*0x0CE9,x","PIEIFR4");
}
hotmenu PIEIER5_and_PIEIFR5()
{
GEL_WatchAdd("*0x0CEA,x","PIEIER5");
GEL_WatchAdd("*0x0CEB,x","PIEIFR5");
}
hotmenu PIEIER6_and_PIEIFR6()
{
GEL_WatchAdd("*0x0CEC,x","PIEIER6");
GEL_WatchAdd("*0x0CED,x","PIEIFR6");
}
hotmenu PIEIER7_and_PIEIFR7()
{
GEL_WatchAdd("*0x0CEE,x","PIEIER7");
GEL_WatchAdd("*0x0CEF,x","PIEIFR7");
}
hotmenu PIEIER8_and_PIEIFR8()
{
GEL_WatchAdd("*0x0CF0,x","PIEIER8");
GEL_WatchAdd("*0x0CF1,x","PIEIFR8");
}
hotmenu PIEIER9_and_PIEIFR9()
{
GEL_WatchAdd("*0x0CF2,x","PIEIER9");
GEL_WatchAdd("*0x0CF3,x","PIEIFR9");
}
hotmenu PIEIFR10_and_PIEIFR10()
{
GEL_WatchAdd("*0x0CF4,x","PIEIER10");
GEL_WatchAdd("*0x0CF5,x","PIEIFR10");
}
hotmenu PIEIER11_and_PIEIFR11()
{
GEL_WatchAdd("*0x0CF6,x","PIEIER11");
GEL_WatchAdd("*0x0CF7,x","PIEIFR11");
}
hotmenu PIEIER12_and_PIEIFR12()
{
GEL_WatchAdd("*0x0CF8,x","PIEIER12");
GEL_WatchAdd("*0x0CF9,x","PIEIFR12");
}
/********************************************************************/
/* Serial Communication Interface Registers */
/********************************************************************/
menuitem "Watch SCI Registers";
hotmenu SCI_A_All_Regs()
{
GEL_WatchAdd("*0x7050,x","SCICCRA");
GEL_WatchAdd("*0x7051,x","SCICTL1A");
GEL_WatchAdd("*0x7052,x","SCIHBAUDA");
GEL_WatchAdd("*0x7053,x","SCILBAUDA");
GEL_WatchAdd("*0x7054,x","SCICTL2A");
GEL_WatchAdd("*0x7055,x","SCIRXSTA");
GEL_WatchAdd("*0x7056,x","SCIRXEMUA");
GEL_WatchAdd("*0x7057,x","SCIRXBUFA");
GEL_WatchAdd("*0x7059,x","SCITXBUFA");
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
GEL_WatchAdd("*0x705F,x","SCIPRIA");
}
hotmenu SCI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x705A,x","SCIFFTXA");
GEL_WatchAdd("*0x705B,x","SCIFFRXA");
GEL_WatchAdd("*0x705C,x","SCIFFCTA");
}
hotmenu SCI_B_All_Regs()
{
GEL_WatchAdd("*0x7750,x","SCICCRB");
GEL_WatchAdd("*0x7751,x","SCICTL1B");
GEL_WatchAdd("*0x7752,x","SCIHBAUDB");
GEL_WatchAdd("*0x7753,x","SCILBAUDB");
GEL_WatchAdd("*0x7754,x","SCICTL2B");
GEL_WatchAdd("*0x7755,x","SCIRXSTB");
GEL_WatchAdd("*0x7756,x","SCIRXEMUB");
GEL_WatchAdd("*0x7757,x","SCIRXBUFB");
GEL_WatchAdd("*0x7759,x","SCITXBUFB");
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
GEL_WatchAdd("*0x775F,x","SCIPRIB");
}
hotmenu SCI_B_FIFO_Registers()
{
GEL_WatchAdd("*0x775A,x","SCIFFTXB");
GEL_WatchAdd("*0x775B,x","SCIFFRXB");
GEL_WatchAdd("*0x775C,x","SCIFFCTB");
}
hotmenu SCI_C_All_Regs()
{
GEL_WatchAdd("*0x7770,x","SCICCRC");
GEL_WatchAdd("*0x7771,x","SCICTL1C");
GEL_WatchAdd("*0x7772,x","SCIHBAUDC");
GEL_WatchAdd("*0x7773,x","SCILBAUDC");
GEL_WatchAdd("*0x7774,x","SCICTL2C");
GEL_WatchAdd("*0x7775,x","SCIRXSTC");
GEL_WatchAdd("*0x7776,x","SCIRXEMUC");
GEL_WatchAdd("*0x7777,x","SCIRXBUFC");
GEL_WatchAdd("*0x7779,x","SCITXBUFC");
GEL_WatchAdd("*0x777A,x","SCIFFTXC");
GEL_WatchAdd("*0x777B,x","SCIFFRXC");
GEL_WatchAdd("*0x777C,x","SCIFFCTC");
GEL_WatchAdd("*0x777F,x","SCIPRIC");
}
hotmenu SCI_C_FIFO_Registers()
{
GEL_WatchAdd("*0x777A,x","SCIFFTXC");
GEL_WatchAdd("*0x777B,x","SCIFFRXC");
GEL_WatchAdd("*0x777C,x","SCIFFCTC");
}
/********************************************************************/
/* Serial Peripheral Interface Registers */
/********************************************************************/
menuitem "Watch SPI Registers";
hotmenu SPI_A_All_Regs()
{
GEL_WatchAdd("*0x7040,x","SPIA SPICCR");
GEL_WatchAdd("*0x7041,x","SPIA SPICTL");
GEL_WatchAdd("*0x7042,x","SPIA SPIST");
GEL_WatchAdd("*0x7044,x","SPIA SPIBRR");
GEL_WatchAdd("*0x7046,x","SPIA SPIEMU");
GEL_WatchAdd("*0x7047,x","SPIA SPIRXBUF");
GEL_WatchAdd("*0x7048,x","SPIA SPITXBUF");
GEL_WatchAdd("*0x7049,x","SPIA SPIDAT");
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
GEL_WatchAdd("*0x704F,x","SPIA SPIPRI");
}
hotmenu SPI_A_FIFO_Registers()
{
GEL_WatchAdd("*0x704A,x","SPIA SPIFFTX");
GEL_WatchAdd("*0x704B,x","SPIA SPIFFRX");
GEL_WatchAdd("*0x704C,x","SPIA SPIFFCT");
}
/********************************************************************/
/* Watchdog Timer Registers */
/********************************************************************/
menuitem "Watch Watchdog Timer Registers";
hotmenu All_Watchdog_Regs()
{
GEL_WatchAdd("*0x7023,x","WDCNTR");
GEL_WatchAdd("*0x7025,x","WDKEY");
GEL_WatchAdd("*0x7029,x","WDCR");
GEL_WatchAdd("*0x7022,x","SCSR");
}
/********************************************************************/
/*** End of file ***/

147
v120/DSP2833x_common/include/DSP2833x_DefaultIsr.h Normal file
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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:45:37 $
//###########################################################################
//
// FILE: DSP2833x_DefaultIsr.h
//
// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_DEFAULT_ISR_H
#define DSP2833x_DEFAULT_ISR_H
#ifdef __cplusplus
extern "C" {
#endif
//---------------------------------------------------------------------------
// Default Interrupt Service Routine Declarations:
//
// The following function prototypes are for the
// default ISR routines used with the default PIE vector table.
// This default vector table is found in the DSP2833x_PieVect.h
// file.
//
// Non-Peripheral Interrupts:
interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1
interrupt void INT14_ISR(void); // CPU-Timer2
interrupt void DATALOG_ISR(void); // Datalogging interrupt
interrupt void RTOSINT_ISR(void); // RTOS interrupt
interrupt void EMUINT_ISR(void); // Emulation interrupt
interrupt void NMI_ISR(void); // Non-maskable interrupt
interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP
interrupt void USER1_ISR(void); // User Defined trap 1
interrupt void USER2_ISR(void); // User Defined trap 2
interrupt void USER3_ISR(void); // User Defined trap 3
interrupt void USER4_ISR(void); // User Defined trap 4
interrupt void USER5_ISR(void); // User Defined trap 5
interrupt void USER6_ISR(void); // User Defined trap 6
interrupt void USER7_ISR(void); // User Defined trap 7
interrupt void USER8_ISR(void); // User Defined trap 8
interrupt void USER9_ISR(void); // User Defined trap 9
interrupt void USER10_ISR(void); // User Defined trap 10
interrupt void USER11_ISR(void); // User Defined trap 11
interrupt void USER12_ISR(void); // User Defined trap 12
// Group 1 PIE Interrupt Service Routines:
interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR
interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR
interrupt void XINT1_ISR(void); // External interrupt 1
interrupt void XINT2_ISR(void); // External interrupt 2
interrupt void ADCINT_ISR(void); // ADC
interrupt void TINT0_ISR(void); // Timer 0
interrupt void WAKEINT_ISR(void); // WD
// Group 2 PIE Interrupt Service Routines:
interrupt void EPWM1_TZINT_ISR(void); // EPWM-1
interrupt void EPWM2_TZINT_ISR(void); // EPWM-2
interrupt void EPWM3_TZINT_ISR(void); // EPWM-3
interrupt void EPWM4_TZINT_ISR(void); // EPWM-4
interrupt void EPWM5_TZINT_ISR(void); // EPWM-5
interrupt void EPWM6_TZINT_ISR(void); // EPWM-6
// Group 3 PIE Interrupt Service Routines:
interrupt void EPWM1_INT_ISR(void); // EPWM-1
interrupt void EPWM2_INT_ISR(void); // EPWM-2
interrupt void EPWM3_INT_ISR(void); // EPWM-3
interrupt void EPWM4_INT_ISR(void); // EPWM-4
interrupt void EPWM5_INT_ISR(void); // EPWM-5
interrupt void EPWM6_INT_ISR(void); // EPWM-6
// Group 4 PIE Interrupt Service Routines:
interrupt void ECAP1_INT_ISR(void); // ECAP-1
interrupt void ECAP2_INT_ISR(void); // ECAP-2
interrupt void ECAP3_INT_ISR(void); // ECAP-3
interrupt void ECAP4_INT_ISR(void); // ECAP-4
interrupt void ECAP5_INT_ISR(void); // ECAP-5
interrupt void ECAP6_INT_ISR(void); // ECAP-6
// Group 5 PIE Interrupt Service Routines:
interrupt void EQEP1_INT_ISR(void); // EQEP-1
interrupt void EQEP2_INT_ISR(void); // EQEP-2
// Group 6 PIE Interrupt Service Routines:
interrupt void SPIRXINTA_ISR(void); // SPI-A
interrupt void SPITXINTA_ISR(void); // SPI-A
interrupt void MRINTA_ISR(void); // McBSP-A
interrupt void MXINTA_ISR(void); // McBSP-A
interrupt void MRINTB_ISR(void); // McBSP-B
interrupt void MXINTB_ISR(void); // McBSP-B
// Group 7 PIE Interrupt Service Routines:
interrupt void DINTCH1_ISR(void); // DMA-Channel 1
interrupt void DINTCH2_ISR(void); // DMA-Channel 2
interrupt void DINTCH3_ISR(void); // DMA-Channel 3
interrupt void DINTCH4_ISR(void); // DMA-Channel 4
interrupt void DINTCH5_ISR(void); // DMA-Channel 5
interrupt void DINTCH6_ISR(void); // DMA-Channel 6
// Group 8 PIE Interrupt Service Routines:
interrupt void I2CINT1A_ISR(void); // I2C-A
interrupt void I2CINT2A_ISR(void); // I2C-A
interrupt void SCIRXINTC_ISR(void); // SCI-C
interrupt void SCITXINTC_ISR(void); // SCI-C
// Group 9 PIE Interrupt Service Routines:
interrupt void SCIRXINTA_ISR(void); // SCI-A
interrupt void SCITXINTA_ISR(void); // SCI-A
interrupt void SCIRXINTB_ISR(void); // SCI-B
interrupt void SCITXINTB_ISR(void); // SCI-B
interrupt void ECAN0INTA_ISR(void); // eCAN-A
interrupt void ECAN1INTA_ISR(void); // eCAN-A
interrupt void ECAN0INTB_ISR(void); // eCAN-B
interrupt void ECAN1INTB_ISR(void); // eCAN-B
// Group 10 PIE Interrupt Service Routines:
// Group 11 PIE Interrupt Service Routines:
// Group 12 PIE Interrupt Service Routines:
interrupt void XINT3_ISR(void); // External interrupt 3
interrupt void XINT4_ISR(void); // External interrupt 4
interrupt void XINT5_ISR(void); // External interrupt 5
interrupt void XINT6_ISR(void); // External interrupt 6
interrupt void XINT7_ISR(void); // External interrupt 7
interrupt void LVF_ISR(void); // Latched overflow flag
interrupt void LUF_ISR(void); // Latched underflow flag
// Catch-all for Reserved Locations For testing purposes:
interrupt void PIE_RESERVED(void); // Reserved for test
interrupt void rsvd_ISR(void); // for test
interrupt void INT_NOTUSED_ISR(void); // for unused interrupts
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DEFAULT_ISR_H definition
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_common/include/DSP2833x_Dma_defines.h Normal file
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// TI File $Revision: /main/2 $
// Checkin $Date: August 14, 2007 16:32:29 $
//###########################################################################
//
// FILE: DSP2833x_Dma_defines.h
//
// TITLE: #defines used in DMA examples
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_DMA_DEFINES_H
#define DSP2833x_DMA_DEFINES_H
#ifdef __cplusplus
extern "C" {
#endif
// MODE
//==========================
// PERINTSEL bits
#define DMA_SEQ1INT 1
#define DMA_SEQ2INT 2
#define DMA_XINT1 3
#define DMA_XINT2 4
#define DMA_XINT3 5
#define DMA_XINT4 6
#define DMA_XINT5 7
#define DMA_XINT6 8
#define DMA_XINT7 9
#define DMA_XINT13 10
#define DMA_TINT0 11
#define DMA_TINT1 12
#define DMA_TINT2 13
#define DMA_MXEVTA 14
#define DMA_MREVTA 15
#define DMA_MXREVTB 16
#define DMA_MREVTB 17
// OVERINTE bit
#define OVRFLOW_DISABLE 0x0
#define OVEFLOW_ENABLE 0x1
// PERINTE bit
#define PERINT_DISABLE 0x0
#define PERINT_ENABLE 0x1
// CHINTMODE bits
#define CHINT_BEGIN 0x0
#define CHINT_END 0x1
// ONESHOT bits
#define ONESHOT_DISABLE 0x0
#define ONESHOT_ENABLE 0x1
// CONTINOUS bit
#define CONT_DISABLE 0x0
#define CONT_ENABLE 0x1
// SYNCE bit
#define SYNC_DISABLE 0x0
#define SYNC_ENABLE 0x1
// SYNCSEL bit
#define SYNC_SRC 0x0
#define SYNC_DST 0x1
// DATASIZE bit
#define SIXTEEN_BIT 0x0
#define THIRTYTWO_BIT 0x1
// CHINTE bit
#define CHINT_DISABLE 0x0
#define CHINT_ENABLE 0x1
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_EPWM_DEFINES_H
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:45:39 $
//###########################################################################
//
// FILE: DSP2833x_EPwm_defines.h
//
// TITLE: #defines used in ePWM examples examples
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_EPWM_DEFINES_H
#define DSP2833x_EPWM_DEFINES_H
#ifdef __cplusplus
extern "C" {
#endif
// TBCTL (Time-Base Control)
//==========================
// CTRMODE bits
#define TB_COUNT_UP 0x0
#define TB_COUNT_DOWN 0x1
#define TB_COUNT_UPDOWN 0x2
#define TB_FREEZE 0x3
// PHSEN bit
#define TB_DISABLE 0x0
#define TB_ENABLE 0x1
// PRDLD bit
#define TB_SHADOW 0x0
#define TB_IMMEDIATE 0x1
// SYNCOSEL bits
#define TB_SYNC_IN 0x0
#define TB_CTR_ZERO 0x1
#define TB_CTR_CMPB 0x2
#define TB_SYNC_DISABLE 0x3
// HSPCLKDIV and CLKDIV bits
#define TB_DIV1 0x0
#define TB_DIV2 0x1
#define TB_DIV4 0x2
// PHSDIR bit
#define TB_DOWN 0x0
#define TB_UP 0x1
// CMPCTL (Compare Control)
//==========================
// LOADAMODE and LOADBMODE bits
#define CC_CTR_ZERO 0x0
#define CC_CTR_PRD 0x1
#define CC_CTR_ZERO_PRD 0x2
#define CC_LD_DISABLE 0x3
// SHDWAMODE and SHDWBMODE bits
#define CC_SHADOW 0x0
#define CC_IMMEDIATE 0x1
// AQCTLA and AQCTLB (Action Qualifier Control)
//=============================================
// ZRO, PRD, CAU, CAD, CBU, CBD bits
#define AQ_NO_ACTION 0x0
#define AQ_CLEAR 0x1
#define AQ_SET 0x2
#define AQ_TOGGLE 0x3
// DBCTL (Dead-Band Control)
//==========================
// OUT MODE bits
#define DB_DISABLE 0x0
#define DBA_ENABLE 0x1
#define DBB_ENABLE 0x2
#define DB_FULL_ENABLE 0x3
// POLSEL bits
#define DB_ACTV_HI 0x0
#define DB_ACTV_LOC 0x1
#define DB_ACTV_HIC 0x2
#define DB_ACTV_LO 0x3
// IN MODE
#define DBA_ALL 0x0
#define DBB_RED_DBA_FED 0x1
#define DBA_RED_DBB_FED 0x2
#define DBB_ALL 0x3
// CHPCTL (chopper control)
//==========================
// CHPEN bit
#define CHP_DISABLE 0x0
#define CHP_ENABLE 0x1
// CHPFREQ bits
#define CHP_DIV1 0x0
#define CHP_DIV2 0x1
#define CHP_DIV3 0x2
#define CHP_DIV4 0x3
#define CHP_DIV5 0x4
#define CHP_DIV6 0x5
#define CHP_DIV7 0x6
#define CHP_DIV8 0x7
// CHPDUTY bits
#define CHP1_8TH 0x0
#define CHP2_8TH 0x1
#define CHP3_8TH 0x2
#define CHP4_8TH 0x3
#define CHP5_8TH 0x4
#define CHP6_8TH 0x5
#define CHP7_8TH 0x6
// TZSEL (Trip Zone Select)
//==========================
// CBCn and OSHTn bits
#define TZ_DISABLE 0x0
#define TZ_ENABLE 0x1
// TZCTL (Trip Zone Control)
//==========================
// TZA and TZB bits
#define TZ_HIZ 0x0
#define TZ_FORCE_HI 0x1
#define TZ_FORCE_LO 0x2
#define TZ_NO_CHANGE 0x3
// ETSEL (Event Trigger Select)
//=============================
#define ET_CTR_ZERO 0x1
#define ET_CTR_PRD 0x2
#define ET_CTRU_CMPA 0x4
#define ET_CTRD_CMPA 0x5
#define ET_CTRU_CMPB 0x6
#define ET_CTRD_CMPB 0x7
// ETPS (Event Trigger Pre-scale)
//===============================
// INTPRD, SOCAPRD, SOCBPRD bits
#define ET_DISABLE 0x0
#define ET_1ST 0x1
#define ET_2ND 0x2
#define ET_3RD 0x3
//--------------------------------
// HRPWM (High Resolution PWM)
//================================
// HRCNFG
#define HR_Disable 0x0
#define HR_REP 0x1
#define HR_FEP 0x2
#define HR_BEP 0x3
#define HR_CMP 0x0
#define HR_PHS 0x1
#define HR_CTR_ZERO 0x0
#define HR_CTR_PRD 0x1
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_EPWM_DEFINES_H
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/9 $
// Checkin $Date: July 2, 2008 14:31:12 $
//###########################################################################
//
// FILE: DSP2833x_Examples.h
//
// TITLE: DSP2833x Device Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_EXAMPLES_H
#define DSP2833x_EXAMPLES_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------------------------
Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
-----------------------------------------------------------------------------*/
//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT
#define DSP28_PLLCR 10
//#define DSP28_PLLCR 9
//#define DSP28_PLLCR 8
//#define DSP28_PLLCR 7
//#define DSP28_PLLCR 6
//#define DSP28_PLLCR 5
//#define DSP28_PLLCR 4
//#define DSP28_PLLCR 3
//#define DSP28_PLLCR 2
//#define DSP28_PLLCR 1
//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
//----------------------------------------------------------------------------
/*-----------------------------------------------------------------------------
Specify the clock rate of the CPU (SYSCLKOUT) in nS.
Take into account the input clock frequency and the PLL multiplier
selected in step 1.
Use one of the values provided, or define your own.
The trailing L is required tells the compiler to treat
the number as a 64-bit value.
Only one statement should be uncommented.
Example 1:150 MHz devices:
CLKIN is a 30MHz crystal.
In step 1 the user specified PLLCR = 0xA for a
150Mhz CPU clock (SYSCLKOUT = 150MHz).
In this case, the CPU_RATE will be 6.667L
Uncomment the line: #define CPU_RATE 6.667L
Example 2: 100 MHz devices:
CLKIN is a 20MHz crystal.
In step 1 the user specified PLLCR = 0xA for a
100Mhz CPU clock (SYSCLKOUT = 100MHz).
In this case, the CPU_RATE will be 10.000L
Uncomment the line: #define CPU_RATE 10.000L
-----------------------------------------------------------------------------*/
#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
//----------------------------------------------------------------------------
/*-----------------------------------------------------------------------------
Target device (in DSP2833x_Device.h) determines CPU frequency
(for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
(for 28332). User does not have to change anything here.
-----------------------------------------------------------------------------*/
#if DSP28_28332 // DSP28_28332 device only
#define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq)
#define CPU_FRQ_150MHZ 0
#else
#define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334
#define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
#endif
//---------------------------------------------------------------------------
// Include Example Header Files:
//
#include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the
// .c files.
#include "DSP2833x_ePwm_defines.h" // Macros used for PWM examples.
#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples.
#include "DSP2833x_I2C_defines.h" // Macros used for I2C examples.
#define PARTNO_28335 0xEF
#define PARTNO_28334 0xEE
#define PARTNO_28332 0xED
#define PARTNO_28235 0xE8
#define PARTNO_28234 0xE7
#define PARTNO_28232 0xE6
// Include files not used with DSP/BIOS
#ifndef DSP28_BIOS
#include "DSP2833x_DefaultISR.h"
#endif
// DO NOT MODIFY THIS LINE.
#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L)
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EXAMPLES_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/11 $
// Checkin $Date: May 12, 2008 14:30:08 $
//###########################################################################
//
// FILE: DSP2833x_GlobalPrototypes.h
//
// TITLE: Global prototypes for DSP2833x Examples
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_GLOBALPROTOTYPES_H
#define DSP2833x_GLOBALPROTOTYPES_H
#ifdef __cplusplus
extern "C" {
#endif
/*---- shared global function prototypes -----------------------------------*/
extern void InitAdc(void);
extern void DMAInitialize(void);
// DMA Channel 1
extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH1(void);
// DMA Channel 2
extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH2(void);
// DMA Channel 3
extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH3(void);
// DMA Channel 4
extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH4(void);
// DMA Channel 5
extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH5(void);
// DMA Channel 6
extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source);
extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep);
extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep);
extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte);
extern void StartDMACH6(void);
extern void InitPeripherals(void);
#if DSP28_ECANA
extern void InitECan(void);
extern void InitECana(void);
extern void InitECanGpio(void);
extern void InitECanaGpio(void);
#endif // endif DSP28_ECANA
#if DSP28_ECANB
extern void InitECanb(void);
extern void InitECanbGpio(void);
#endif // endif DSP28_ECANB
extern void InitECap(void);
extern void InitECapGpio(void);
extern void InitECap1Gpio(void);
extern void InitECap2Gpio(void);
#if DSP28_ECAP3
extern void InitECap3Gpio(void);
#endif // endif DSP28_ECAP3
#if DSP28_ECAP4
extern void InitECap4Gpio(void);
#endif // endif DSP28_ECAP4
#if DSP28_ECAP5
extern void InitECap5Gpio(void);
#endif // endif DSP28_ECAP5
#if DSP28_ECAP6
extern void InitECap6Gpio(void);
#endif // endif DSP28_ECAP6
extern void InitEPwm(void);
extern void InitEPwmGpio(void);
extern void InitEPwm1Gpio(void);
extern void InitEPwm2Gpio(void);
extern void InitEPwm3Gpio(void);
#if DSP28_EPWM4
extern void InitEPwm4Gpio(void);
#endif // endif DSP28_EPWM4
#if DSP28_EPWM5
extern void InitEPwm5Gpio(void);
#endif // endif DSP28_EPWM5
#if DSP28_EPWM6
extern void InitEPwm6Gpio(void);
#endif // endif DSP28_EPWM6
#if DSP28_EQEP1
extern void InitEQep(void);
extern void InitEQepGpio(void);
extern void InitEQep1Gpio(void);
#endif // if DSP28_EQEP1
#if DSP28_EQEP2
extern void InitEQep2Gpio(void);
#endif // endif DSP28_EQEP2
extern void InitGpio(void);
extern void InitI2CGpio(void);
extern void InitMcbsp(void);
extern void InitMcbspa(void);
extern void delay_loop(void);
extern void InitMcbspaGpio(void);
extern void InitMcbspa8bit(void);
extern void InitMcbspa12bit(void);
extern void InitMcbspa16bit(void);
extern void InitMcbspa20bit(void);
extern void InitMcbspa24bit(void);
extern void InitMcbspa32bit(void);
#if DSP28_MCBSPB
extern void InitMcbspb(void);
extern void InitMcbspbGpio(void);
extern void InitMcbspb8bit(void);
extern void InitMcbspb12bit(void);
extern void InitMcbspb16bit(void);
extern void InitMcbspb20bit(void);
extern void InitMcbspb24bit(void);
extern void InitMcbspb32bit(void);
#endif // endif DSP28_MCBSPB
extern void InitPieCtrl(void);
extern void InitPieVectTable(void);
extern void InitSci(void);
extern void InitSciGpio(void);
extern void InitSciaGpio(void);
#if DSP28_SCIB
extern void InitScibGpio(void);
#endif // endif DSP28_SCIB
#if DSP28_SCIC
extern void InitScicGpio(void);
#endif
extern void InitSpi(void);
extern void InitSpiGpio(void);
extern void InitSpiaGpio(void);
extern void InitSysCtrl(void);
extern void InitTzGpio(void);
extern void InitXIntrupt(void);
extern void XintfInit(void);
extern void InitXintf16Gpio();
extern void InitXintf32Gpio();
extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
extern void InitPeripheralClocks(void);
extern void EnableInterrupts(void);
extern void DSP28x_usDelay(Uint32 Count);
extern void ADC_cal (void);
#define KickDog ServiceDog // For compatiblity with previous versions
extern void ServiceDog(void);
extern void DisableDog(void);
extern Uint16 CsmUnlock(void);
// DSP28_DBGIER.asm
extern void SetDBGIER(Uint16 dbgier);
// CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results
extern void InitFlash(void);
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
//---------------------------------------------------------------------------
// External symbols created by the linker cmd file
// DSP28 examples will use these to relocate code from one LOAD location
// in either Flash or XINTF to a different RUN location in internal
// RAM
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsRunStart;
extern Uint16 XintffuncsLoadStart;
extern Uint16 XintffuncsLoadEnd;
extern Uint16 XintffuncsRunStart;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_GLOBALPROTOTYPES_H
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/2 $
// Checkin $Date: April 16, 2008 17:16:47 $
//###########################################################################
//
// FILE: DSP2833x_I2cExample.h
//
// TITLE: 2833x I2C Example Code Definitions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP2833x_I2C_DEFINES_H
#define DSP2833x_I2C_DEFINES_H
//--------------------------------------------
// Defines
//--------------------------------------------
// Error Messages
#define I2C_ERROR 0xFFFF
#define I2C_ARB_LOST_ERROR 0x0001
#define I2C_NACK_ERROR 0x0002
#define I2C_BUS_BUSY_ERROR 0x1000
#define I2C_STP_NOT_READY_ERROR 0x5555
#define I2C_NO_FLAGS 0xAAAA
#define I2C_SUCCESS 0x0000
// Clear Status Flags
#define I2C_CLR_AL_BIT 0x0001
#define I2C_CLR_NACK_BIT 0x0002
#define I2C_CLR_ARDY_BIT 0x0004
#define I2C_CLR_RRDY_BIT 0x0008
#define I2C_CLR_SCD_BIT 0x0020
// Interrupt Source Messages
#define I2C_NO_ISRC 0x0000
#define I2C_ARB_ISRC 0x0001
#define I2C_NACK_ISRC 0x0002
#define I2C_ARDY_ISRC 0x0003
#define I2C_RX_ISRC 0x0004
#define I2C_TX_ISRC 0x0005
#define I2C_SCD_ISRC 0x0006
#define I2C_AAS_ISRC 0x0007
// I2CMSG structure defines
#define I2C_NO_STOP 0
#define I2C_YES_STOP 1
#define I2C_RECEIVE 0
#define I2C_TRANSMIT 1
#define I2C_MAX_BUFFER_SIZE 16
// I2C Slave State defines
#define I2C_NOTSLAVE 0
#define I2C_ADDR_AS_SLAVE 1
#define I2C_ST_MSG_READY 2
// I2C Slave Receiver messages defines
#define I2C_SND_MSG1 1
#define I2C_SND_MSG2 2
// I2C State defines
#define I2C_IDLE 0
#define I2C_SLAVE_RECEIVER 1
#define I2C_SLAVE_TRANSMITTER 2
#define I2C_MASTER_RECEIVER 3
#define I2C_MASTER_TRANSMITTER 4
// I2C Message Commands for I2CMSG struct
#define I2C_MSGSTAT_INACTIVE 0x0000
#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
#define I2C_MSGSTAT_WRITE_BUSY 0x0011
#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
#define I2C_MSGSTAT_RESTART 0x0022
#define I2C_MSGSTAT_READ_BUSY 0x0023
// Generic defines
#define I2C_TRUE 1
#define I2C_FALSE 0
#define I2C_YES 1
#define I2C_NO 0
#define I2C_DUMMY_BYTE 0
//--------------------------------------------
// Structures
//--------------------------------------------
// I2C Message Structure
struct I2CMSG {
Uint16 MsgStatus; // Word stating what state msg is in:
// I2C_MSGCMD_INACTIVE = do not send msg
// I2C_MSGCMD_BUSY = msg start has been sent,
// awaiting stop
// I2C_MSGCMD_SEND_WITHSTOP = command to send
// master trans msg complete with a stop bit
// I2C_MSGCMD_SEND_NOSTOP = command to send
// master trans msg without the stop bit
// I2C_MSGCMD_RESTART = command to send a restart
// as a master receiver with a stop bit
Uint16 SlaveAddress; // I2C address of slave msg is intended for
Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer)
Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte)
Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte)
Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that
// MAX_BUFFER_SIZE can be is 16 due to
// the FIFO's
};
#endif // end of DSP2833x_I2C_DEFINES_H definition
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: April 22, 2008 14:35:56 $
//###########################################################################
//
// FILE: DSP28x_Project.h
//
// TITLE: DSP28x Project Headerfile and Examples Include File
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#ifndef DSP28x_PROJECT_H
#define DSP28x_PROJECT_H
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
#endif // end of DSP28x_PROJECT_H definition

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// TI File $Revision: /main/2 $
// Checkin $Date: July 10, 2008 10:59:52 $
//###########################################################################
//
// FILE: IQmathLib.h
//
// TITLE: IQ Math library functions definitions.
//
//###########################################################################
//
// Ver | dd-mmm-yyyy | Who | Description of changes
// =====|=============|=======|==============================================
// 1.3 | 19 Nov 2001 | A. T. | Original Release.
// -----|-------------|-------|----------------------------------------------
// 1.4 | 17 May 2002 | A. T. | Added new functions and support for
// | | | intrinsics IQmpy, IQxmpy, IQsat.
// -----|-------------|-------|----------------------------------------------
// 1.4a| 12 Jun 2002 | A. T. | Fixed problem with _IQ() operation on
// | | | variables.
// -----|-------------|-------|----------------------------------------------
// 1.4b| 18 Jun 2002 | A. T. | Fixed bug with _IQtoIQN() and _IQNtoIQ()
// | | | operations.
// -----|-------------|-------|----------------------------------------------
// 1.4d| 30 Mar 2003 | DA/SD | 1. Added macro parameters in parentheses
// | | | in number of places where it matters
// | | | 2. Added macro definition to include header
// | | | file multiple times in the program.
// -----|-------------|-------|----------------------------------------------
// 1.4e| 17 Jun 2004 | AT/DA | Added IQexp function.
// | | | Added IQasin & IQacos functions (thanks DA).
// -----|-------------|-------|----------------------------------------------
// 1.4f| 10 Mar 2005 | AT | Fixed Bug In IQexp function.
// -----|-------------|-------|----------------------------------------------
// 1.5 | 30 Jan 2008 | LH | 1. Changed the definion of the _IQatan2PU(A,B)
// | | | macro for FLOAT_MATH so that a call to
// | | | divide will not occur.
// | | | 2. If MATH_TYPE == FLOAT_MATH, then include the
// | | | following standard headers: math.h
// | | | stdlib.h.
// | | | 3. Added missing #defines for the non-global
// | | | _IQatanN() function
// | | | 4. Adding missing definitions for absolute
// | | | value when MATH_TYPE == FLOAT_MATH
// | | | 5. Included limits.h and changed the definition
// | | | of MAX_IQ_NEG to LONG_MIN and MAX_IQ_POS
// | | | to LONG_MAX
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
//
// User needs to configure "MATH_TYPE" and "GLOBAL_Q" values:
//
//---------------------------------------------------------------------------
// Select math type, IQ_MATH or FLOAT_MATH:
//
#ifndef __IQMATHLIB_H_INCLUDED__
#define __IQMATHLIB_H_INCLUDED__
#define FLOAT_MATH 1
#define IQ_MATH 0
#ifndef MATH_TYPE
#define MATH_TYPE IQ_MATH
#endif
//---------------------------------------------------------------------------
// Select global Q value and scaling. The Q value is limited to the
// following range for all functions:
//
// 30 <= GLOBAL_Q <= 1
//
#ifndef GLOBAL_Q
#define GLOBAL_Q 24
#endif
//---------------------------------------------------------------------------
// If using FLOAT_MATH, include standard headers to avoid conversion issues
//
#if MATH_TYPE == FLOAT_MATH
#include <math.h>
#include <stdlib.h>
#endif
#include <limits.h>
//---------------------------------------------------------------------------
// Various Usefull Constant Definitions:
//
#define QG GLOBAL_Q
#define Q30 30
#define Q29 29
#define Q28 28
#define Q27 27
#define Q26 26
#define Q25 25
#define Q24 24
#define Q23 23
#define Q22 22
#define Q21 21
#define Q20 20
#define Q19 19
#define Q18 18
#define Q17 17
#define Q16 16
#define Q15 15
#define Q14 14
#define Q13 13
#define Q12 12
#define Q11 11
#define Q10 10
#define Q9 9
#define Q8 8
#define Q7 7
#define Q6 6
#define Q5 5
#define Q4 4
#define Q3 3
#define Q2 2
#define Q1 1
#define MAX_IQ_POS LONG_MAX
#define MAX_IQ_NEG LONG_MIN
#define MIN_IQ_POS 1
#define MIN_IQ_NEG -1
//###########################################################################
#if MATH_TYPE == IQ_MATH
//###########################################################################
// If IQ_MATH is used, the following IQmath library function definitions
// are used:
//===========================================================================
typedef long _iq;
typedef long _iq30;
typedef long _iq29;
typedef long _iq28;
typedef long _iq27;
typedef long _iq26;
typedef long _iq25;
typedef long _iq24;
typedef long _iq23;
typedef long _iq22;
typedef long _iq21;
typedef long _iq20;
typedef long _iq19;
typedef long _iq18;
typedef long _iq17;
typedef long _iq16;
typedef long _iq15;
typedef long _iq14;
typedef long _iq13;
typedef long _iq12;
typedef long _iq11;
typedef long _iq10;
typedef long _iq9;
typedef long _iq8;
typedef long _iq7;
typedef long _iq6;
typedef long _iq5;
typedef long _iq4;
typedef long _iq3;
typedef long _iq2;
typedef long _iq1;
//---------------------------------------------------------------------------
#define _IQ30(A) (long) ((A) * 1073741824.0L)
#define _IQ29(A) (long) ((A) * 536870912.0L)
#define _IQ28(A) (long) ((A) * 268435456.0L)
#define _IQ27(A) (long) ((A) * 134217728.0L)
#define _IQ26(A) (long) ((A) * 67108864.0L)
#define _IQ25(A) (long) ((A) * 33554432.0L)
#define _IQ24(A) (long) ((A) * 16777216.0L)
#define _IQ23(A) (long) ((A) * 8388608.0L)
#define _IQ22(A) (long) ((A) * 4194304.0L)
#define _IQ21(A) (long) ((A) * 2097152.0L)
#define _IQ20(A) (long) ((A) * 1048576.0L)
#define _IQ19(A) (long) ((A) * 524288.0L)
#define _IQ18(A) (long) ((A) * 262144.0L)
#define _IQ17(A) (long) ((A) * 131072.0L)
#define _IQ16(A) (long) ((A) * 65536.0L)
#define _IQ15(A) (long) ((A) * 32768.0L)
#define _IQ14(A) (long) ((A) * 16384.0L)
#define _IQ13(A) (long) ((A) * 8192.0L)
#define _IQ12(A) (long) ((A) * 4096.0L)
#define _IQ11(A) (long) ((A) * 2048.0L)
#define _IQ10(A) (long) ((A) * 1024.0L)
#define _IQ9(A) (long) ((A) * 512.0L)
#define _IQ8(A) (long) ((A) * 256.0L)
#define _IQ7(A) (long) ((A) * 128.0L)
#define _IQ6(A) (long) ((A) * 64.0L)
#define _IQ5(A) (long) ((A) * 32.0L)
#define _IQ4(A) (long) ((A) * 16.0L)
#define _IQ3(A) (long) ((A) * 8.0L)
#define _IQ2(A) (long) ((A) * 4.0L)
#define _IQ1(A) (long) ((A) * 2.0L)
#if GLOBAL_Q == 30
#define _IQ(A) _IQ30(A)
#endif
#if GLOBAL_Q == 29
#define _IQ(A) _IQ29(A)
#endif
#if GLOBAL_Q == 28
#define _IQ(A) _IQ28(A)
#endif
#if GLOBAL_Q == 27
#define _IQ(A) _IQ27(A)
#endif
#if GLOBAL_Q == 26
#define _IQ(A) _IQ26(A)
#endif
#if GLOBAL_Q == 25
#define _IQ(A) _IQ25(A)
#endif
#if GLOBAL_Q == 24
#define _IQ(A) _IQ24(A)
#endif
#if GLOBAL_Q == 23
#define _IQ(A) _IQ23(A)
#endif
#if GLOBAL_Q == 22
#define _IQ(A) _IQ22(A)
#endif
#if GLOBAL_Q == 21
#define _IQ(A) _IQ21(A)
#endif
#if GLOBAL_Q == 20
#define _IQ(A) _IQ20(A)
#endif
#if GLOBAL_Q == 19
#define _IQ(A) _IQ19(A)
#endif
#if GLOBAL_Q == 18
#define _IQ(A) _IQ18(A)
#endif
#if GLOBAL_Q == 17
#define _IQ(A) _IQ17(A)
#endif
#if GLOBAL_Q == 16
#define _IQ(A) _IQ16(A)
#endif
#if GLOBAL_Q == 15
#define _IQ(A) _IQ15(A)
#endif
#if GLOBAL_Q == 14
#define _IQ(A) _IQ14(A)
#endif
#if GLOBAL_Q == 13
#define _IQ(A) _IQ13(A)
#endif
#if GLOBAL_Q == 12
#define _IQ(A) _IQ12(A)
#endif
#if GLOBAL_Q == 11
#define _IQ(A) _IQ11(A)
#endif
#if GLOBAL_Q == 10
#define _IQ(A) _IQ10(A)
#endif
#if GLOBAL_Q == 9
#define _IQ(A) _IQ9(A)
#endif
#if GLOBAL_Q == 8
#define _IQ(A) _IQ8(A)
#endif
#if GLOBAL_Q == 7
#define _IQ(A) _IQ7(A)
#endif
#if GLOBAL_Q == 6
#define _IQ(A) _IQ6(A)
#endif
#if GLOBAL_Q == 5
#define _IQ(A) _IQ5(A)
#endif
#if GLOBAL_Q == 4
#define _IQ(A) _IQ4(A)
#endif
#if GLOBAL_Q == 3
#define _IQ(A) _IQ3(A)
#endif
#if GLOBAL_Q == 2
#define _IQ(A) _IQ2(A)
#endif
#if GLOBAL_Q == 1
#define _IQ(A) _IQ1(A)
#endif
//---------------------------------------------------------------------------
extern float _IQ30toF(long A);
extern float _IQ29toF(long A);
extern float _IQ28toF(long A);
extern float _IQ27toF(long A);
extern float _IQ26toF(long A);
extern float _IQ25toF(long A);
extern float _IQ24toF(long A);
extern float _IQ23toF(long A);
extern float _IQ22toF(long A);
extern float _IQ21toF(long A);
extern float _IQ20toF(long A);
extern float _IQ19toF(long A);
extern float _IQ18toF(long A);
extern float _IQ17toF(long A);
extern float _IQ16toF(long A);
extern float _IQ15toF(long A);
extern float _IQ14toF(long A);
extern float _IQ13toF(long A);
extern float _IQ12toF(long A);
extern float _IQ11toF(long A);
extern float _IQ10toF(long A);
extern float _IQ9toF(long A);
extern float _IQ8toF(long A);
extern float _IQ7toF(long A);
extern float _IQ6toF(long A);
extern float _IQ5toF(long A);
extern float _IQ4toF(long A);
extern float _IQ3toF(long A);
extern float _IQ2toF(long A);
extern float _IQ1toF(long A);
#if GLOBAL_Q == 30
#define _IQtoF(A) _IQ30toF(A)
#endif
#if GLOBAL_Q == 29
#define _IQtoF(A) _IQ29toF(A)
#endif
#if GLOBAL_Q == 28
#define _IQtoF(A) _IQ28toF(A)
#endif
#if GLOBAL_Q == 27
#define _IQtoF(A) _IQ27toF(A)
#endif
#if GLOBAL_Q == 26
#define _IQtoF(A) _IQ26toF(A)
#endif
#if GLOBAL_Q == 25
#define _IQtoF(A) _IQ25toF(A)
#endif
#if GLOBAL_Q == 24
#define _IQtoF(A) _IQ24toF(A)
#endif
#if GLOBAL_Q == 23
#define _IQtoF(A) _IQ23toF(A)
#endif
#if GLOBAL_Q == 22
#define _IQtoF(A) _IQ22toF(A)
#endif
#if GLOBAL_Q == 21
#define _IQtoF(A) _IQ21toF(A)
#endif
#if GLOBAL_Q == 20
#define _IQtoF(A) _IQ20toF(A)
#endif
#if GLOBAL_Q == 19
#define _IQtoF(A) _IQ19toF(A)
#endif
#if GLOBAL_Q == 18
#define _IQtoF(A) _IQ18toF(A)
#endif
#if GLOBAL_Q == 17
#define _IQtoF(A) _IQ17toF(A)
#endif
#if GLOBAL_Q == 16
#define _IQtoF(A) _IQ16toF(A)
#endif
#if GLOBAL_Q == 15
#define _IQtoF(A) _IQ15toF(A)
#endif
#if GLOBAL_Q == 14
#define _IQtoF(A) _IQ14toF(A)
#endif
#if GLOBAL_Q == 13
#define _IQtoF(A) _IQ13toF(A)
#endif
#if GLOBAL_Q == 12
#define _IQtoF(A) _IQ12toF(A)
#endif
#if GLOBAL_Q == 11
#define _IQtoF(A) _IQ11toF(A)
#endif
#if GLOBAL_Q == 10
#define _IQtoF(A) _IQ10toF(A)
#endif
#if GLOBAL_Q == 9
#define _IQtoF(A) _IQ9toF(A)
#endif
#if GLOBAL_Q == 8
#define _IQtoF(A) _IQ8toF(A)
#endif
#if GLOBAL_Q == 7
#define _IQtoF(A) _IQ7toF(A)
#endif
#if GLOBAL_Q == 6
#define _IQtoF(A) _IQ6toF(A)
#endif
#if GLOBAL_Q == 5
#define _IQtoF(A) _IQ5toF(A)
#endif
#if GLOBAL_Q == 4
#define _IQtoF(A) _IQ4toF(A)
#endif
#if GLOBAL_Q == 3
#define _IQtoF(A) _IQ3toF(A)
#endif
#if GLOBAL_Q == 2
#define _IQtoF(A) _IQ2toF(A)
#endif
#if GLOBAL_Q == 1
#define _IQtoF(A) _IQ1toF(A)
#endif
//---------------------------------------------------------------------------
#define _IQsat(A, Pos, Neg) __IQsat(A, Pos, Neg)
//---------------------------------------------------------------------------
#define _IQtoIQ30(A) ((long) (A) << (30 - GLOBAL_Q))
#define _IQ30toIQ(A) ((long) (A) >> (30 - GLOBAL_Q))
#if (GLOBAL_Q >= 29)
#define _IQtoIQ29(A) ((long) (A) >> (GLOBAL_Q - 29))
#define _IQ29toIQ(A) ((long) (A) << (GLOBAL_Q - 29))
#else
#define _IQtoIQ29(A) ((long) (A) << (29 - GLOBAL_Q))
#define _IQ29toIQ(A) ((long) (A) >> (29 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 28)
#define _IQtoIQ28(A) ((long) (A) >> (GLOBAL_Q - 28))
#define _IQ28toIQ(A) ((long) (A) << (GLOBAL_Q - 28))
#else
#define _IQtoIQ28(A) ((long) (A) << (28 - GLOBAL_Q))
#define _IQ28toIQ(A) ((long) (A) >> (28 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 27)
#define _IQtoIQ27(A) ((long) (A) >> (GLOBAL_Q - 27))
#define _IQ27toIQ(A) ((long) (A) << (GLOBAL_Q - 27))
#else
#define _IQtoIQ27(A) ((long) (A) << (27 - GLOBAL_Q))
#define _IQ27toIQ(A) ((long) (A) >> (27 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 26)
#define _IQtoIQ26(A) ((long) (A) >> (GLOBAL_Q - 26))
#define _IQ26toIQ(A) ((long) (A) << (GLOBAL_Q - 26))
#else
#define _IQtoIQ26(A) ((long) (A) << (26 - GLOBAL_Q))
#define _IQ26toIQ(A) ((long) (A) >> (26 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 25)
#define _IQtoIQ25(A) ((long) (A) >> (GLOBAL_Q - 25))
#define _IQ25toIQ(A) ((long) (A) << (GLOBAL_Q - 25))
#else
#define _IQtoIQ25(A) ((long) (A) << (25 - GLOBAL_Q))
#define _IQ25toIQ(A) ((long) (A) >> (25 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 24)
#define _IQtoIQ24(A) ((long) (A) >> (GLOBAL_Q - 24))
#define _IQ24toIQ(A) ((long) (A) << (GLOBAL_Q - 24))
#else
#define _IQtoIQ24(A) ((long) (A) << (24 - GLOBAL_Q))
#define _IQ24toIQ(A) ((long) (A) >> (24 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 23)
#define _IQtoIQ23(A) ((long) (A) >> (GLOBAL_Q - 23))
#define _IQ23toIQ(A) ((long) (A) << (GLOBAL_Q - 23))
#else
#define _IQtoIQ23(A) ((long) (A) << (23 - GLOBAL_Q))
#define _IQ23toIQ(A) ((long) (A) >> (23 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 22)
#define _IQtoIQ22(A) ((long) (A) >> (GLOBAL_Q - 22))
#define _IQ22toIQ(A) ((long) (A) << (GLOBAL_Q - 22))
#else
#define _IQtoIQ22(A) ((long) (A) << (22 - GLOBAL_Q))
#define _IQ22toIQ(A) ((long) (A) >> (22 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 21)
#define _IQtoIQ21(A) ((long) (A) >> (GLOBAL_Q - 21))
#define _IQ21toIQ(A) ((long) (A) << (GLOBAL_Q - 21))
#else
#define _IQtoIQ21(A) ((long) (A) << (21 - GLOBAL_Q))
#define _IQ21toIQ(A) ((long) (A) >> (21 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 20)
#define _IQtoIQ20(A) ((long) (A) >> (GLOBAL_Q - 20))
#define _IQ20toIQ(A) ((long) (A) << (GLOBAL_Q - 20))
#else
#define _IQtoIQ20(A) ((long) (A) << (20 - GLOBAL_Q))
#define _IQ20toIQ(A) ((long) (A) >> (20 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 19)
#define _IQtoIQ19(A) ((long) (A) >> (GLOBAL_Q - 19))
#define _IQ19toIQ(A) ((long) (A) << (GLOBAL_Q - 19))
#else
#define _IQtoIQ19(A) ((long) (A) << (19 - GLOBAL_Q))
#define _IQ19toIQ(A) ((long) (A) >> (19 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 18)
#define _IQtoIQ18(A) ((long) (A) >> (GLOBAL_Q - 18))
#define _IQ18toIQ(A) ((long) (A) << (GLOBAL_Q - 18))
#else
#define _IQtoIQ18(A) ((long) (A) << (18 - GLOBAL_Q))
#define _IQ18toIQ(A) ((long) (A) >> (18 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 17)
#define _IQtoIQ17(A) ((long) (A) >> (GLOBAL_Q - 17))
#define _IQ17toIQ(A) ((long) (A) << (GLOBAL_Q - 17))
#else
#define _IQtoIQ17(A) ((long) (A) << (17 - GLOBAL_Q))
#define _IQ17toIQ(A) ((long) (A) >> (17 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 16)
#define _IQtoIQ16(A) ((long) (A) >> (GLOBAL_Q - 16))
#define _IQ16toIQ(A) ((long) (A) << (GLOBAL_Q - 16))
#else
#define _IQtoIQ16(A) ((long) (A) << (16 - GLOBAL_Q))
#define _IQ16toIQ(A) ((long) (A) >> (16 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 15)
#define _IQtoIQ15(A) ((long) (A) >> (GLOBAL_Q - 15))
#define _IQ15toIQ(A) ((long) (A) << (GLOBAL_Q - 15))
#define _IQtoQ15(A) ((long) (A) >> (GLOBAL_Q - 15))
#define _Q15toIQ(A) ((long) (A) << (GLOBAL_Q - 15))
#else
#define _IQtoIQ15(A) ((long) (A) << (15 - GLOBAL_Q))
#define _IQ15toIQ(A) ((long) (A) >> (15 - GLOBAL_Q))
#define _IQtoQ15(A) ((long) (A) << (15 - GLOBAL_Q))
#define _Q15toIQ(A) ((long) (A) >> (15 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 14)
#define _IQtoIQ14(A) ((long) (A) >> (GLOBAL_Q - 14))
#define _IQ14toIQ(A) ((long) (A) << (GLOBAL_Q - 14))
#define _IQtoQ14(A) ((long) (A) >> (GLOBAL_Q - 14))
#define _Q14toIQ(A) ((long) (A) << (GLOBAL_Q - 14))
#else
#define _IQtoIQ14(A) ((long) (A) << (14 - GLOBAL_Q))
#define _IQ14toIQ(A) ((long) (A) >> (14 - GLOBAL_Q))
#define _IQtoQ14(A) ((long) (A) << (14 - GLOBAL_Q))
#define _Q14toIQ(A) ((long) (A) >> (14 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 13)
#define _IQtoIQ13(A) ((long) (A) >> (GLOBAL_Q - 13))
#define _IQ13toIQ(A) ((long) (A) << (GLOBAL_Q - 13))
#define _IQtoQ13(A) ((long) (A) >> (GLOBAL_Q - 13))
#define _Q13toIQ(A) ((long) (A) << (GLOBAL_Q - 13))
#else
#define _IQtoIQ13(A) ((long) (A) << (13 - GLOBAL_Q))
#define _IQ13toIQ(A) ((long) (A) >> (13 - GLOBAL_Q))
#define _IQtoQ13(A) ((long) (A) << (13 - GLOBAL_Q))
#define _Q13toIQ(A) ((long) (A) >> (13 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 12)
#define _IQtoIQ12(A) ((long) (A) >> (GLOBAL_Q - 12))
#define _IQ12toIQ(A) ((long) (A) << (GLOBAL_Q - 12))
#define _IQtoQ12(A) ((long) (A) >> (GLOBAL_Q - 12))
#define _Q12toIQ(A) ((long) (A) << (GLOBAL_Q - 12))
#else
#define _IQtoIQ12(A) ((long) (A) << (12 - GLOBAL_Q))
#define _IQ12toIQ(A) ((long) (A) >> (12 - GLOBAL_Q))
#define _IQtoQ12(A) ((long) (A) << (12 - GLOBAL_Q))
#define _Q12toIQ(A) ((long) (A) >> (12 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 11)
#define _IQtoIQ11(A) ((long) (A) >> (GLOBAL_Q - 11))
#define _IQ11toIQ(A) ((long) (A) << (GLOBAL_Q - 11))
#define _IQtoQ11(A) ((long) (A) >> (GLOBAL_Q - 11))
#define _Q11toIQ(A) ((long) (A) << (GLOBAL_Q - 11))
#else
#define _IQtoIQ11(A) ((long) (A) << (11 - GLOBAL_Q))
#define _IQ11toIQ(A) ((long) (A) >> (11 - GLOBAL_Q))
#define _IQtoQ11(A) ((long) (A) << (11 - GLOBAL_Q))
#define _Q11toIQ(A) ((long) (A) >> (11 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 10)
#define _IQtoIQ10(A) ((long) (A) >> (GLOBAL_Q - 10))
#define _IQ10toIQ(A) ((long) (A) << (GLOBAL_Q - 10))
#define _IQtoQ10(A) ((long) (A) >> (GLOBAL_Q - 10))
#define _Q10toIQ(A) ((long) (A) << (GLOBAL_Q - 10))
#else
#define _IQtoIQ10(A) ((long) (A) << (10 - GLOBAL_Q))
#define _IQ10toIQ(A) ((long) (A) >> (10 - GLOBAL_Q))
#define _IQtoQ10(A) ((long) (A) << (10 - GLOBAL_Q))
#define _Q10toIQ(A) ((long) (A) >> (10 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 9)
#define _IQtoIQ9(A) ((long) (A) >> (GLOBAL_Q - 9))
#define _IQ9toIQ(A) ((long) (A) << (GLOBAL_Q - 9))
#define _IQtoQ9(A) ((long) (A) >> (GLOBAL_Q - 9))
#define _Q9toIQ(A) ((long) (A) << (GLOBAL_Q - 9))
#else
#define _IQtoIQ9(A) ((long) (A) << (9 - GLOBAL_Q))
#define _IQ9toIQ(A) ((long) (A) >> (9 - GLOBAL_Q))
#define _IQtoQ9(A) ((long) (A) << (9 - GLOBAL_Q))
#define _Q9toIQ(A) ((long) (A) >> (9 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 8)
#define _IQtoIQ8(A) ((long) (A) >> (GLOBAL_Q - 8))
#define _IQ8toIQ(A) ((long) (A) << (GLOBAL_Q - 8))
#define _IQtoQ8(A) ((long) (A) >> (GLOBAL_Q - 8))
#define _Q8toIQ(A) ((long) (A) << (GLOBAL_Q - 8))
#else
#define _IQtoIQ8(A) ((long) (A) << (8 - GLOBAL_Q))
#define _IQ8toIQ(A) ((long) (A) >> (8 - GLOBAL_Q))
#define _IQtoQ8(A) ((long) (A) << (8 - GLOBAL_Q))
#define _Q8toIQ(A) ((long) (A) >> (8 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 7)
#define _IQtoIQ7(A) ((long) (A) >> (GLOBAL_Q - 7))
#define _IQ7toIQ(A) ((long) (A) << (GLOBAL_Q - 7))
#define _IQtoQ7(A) ((long) (A) >> (GLOBAL_Q - 7))
#define _Q7toIQ(A) ((long) (A) << (GLOBAL_Q - 7))
#else
#define _IQtoIQ7(A) ((long) (A) << (7 - GLOBAL_Q))
#define _IQ7toIQ(A) ((long) (A) >> (7 - GLOBAL_Q))
#define _IQtoQ7(A) ((long) (A) << (7 - GLOBAL_Q))
#define _Q7toIQ(A) ((long) (A) >> (7 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 6)
#define _IQtoIQ6(A) ((long) (A) >> (GLOBAL_Q - 6))
#define _IQ6toIQ(A) ((long) (A) << (GLOBAL_Q - 6))
#define _IQtoQ6(A) ((long) (A) >> (GLOBAL_Q - 6))
#define _Q6toIQ(A) ((long) (A) << (GLOBAL_Q - 6))
#else
#define _IQtoIQ6(A) ((long) (A) << (6 - GLOBAL_Q))
#define _IQ6toIQ(A) ((long) (A) >> (6 - GLOBAL_Q))
#define _IQtoQ6(A) ((long) (A) << (6 - GLOBAL_Q))
#define _Q6toIQ(A) ((long) (A) >> (6 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 5)
#define _IQtoIQ5(A) ((long) (A) >> (GLOBAL_Q - 5))
#define _IQ5toIQ(A) ((long) (A) << (GLOBAL_Q - 5))
#define _IQtoQ5(A) ((long) (A) >> (GLOBAL_Q - 5))
#define _Q5toIQ(A) ((long) (A) << (GLOBAL_Q - 5))
#else
#define _IQtoIQ5(A) ((long) (A) << (5 - GLOBAL_Q))
#define _IQ5toIQ(A) ((long) (A) >> (5 - GLOBAL_Q))
#define _IQtoQ5(A) ((long) (A) << (5 - GLOBAL_Q))
#define _Q5toIQ(A) ((long) (A) >> (5 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 4)
#define _IQtoIQ4(A) ((long) (A) >> (GLOBAL_Q - 4))
#define _IQ4toIQ(A) ((long) (A) << (GLOBAL_Q - 4))
#define _IQtoQ4(A) ((long) (A) >> (GLOBAL_Q - 4))
#define _Q4toIQ(A) ((long) (A) << (GLOBAL_Q - 4))
#else
#define _IQtoIQ4(A) ((long) (A) << (4 - GLOBAL_Q))
#define _IQ4toIQ(A) ((long) (A) >> (4 - GLOBAL_Q))
#define _IQtoQ4(A) ((long) (A) << (4 - GLOBAL_Q))
#define _Q4toIQ(A) ((long) (A) >> (4 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 3)
#define _IQtoIQ3(A) ((long) (A) >> (GLOBAL_Q - 3))
#define _IQ3toIQ(A) ((long) (A) << (GLOBAL_Q - 3))
#define _IQtoQ3(A) ((long) (A) >> (GLOBAL_Q - 3))
#define _Q3toIQ(A) ((long) (A) << (GLOBAL_Q - 3))
#else
#define _IQtoIQ3(A) ((long) (A) << (3 - GLOBAL_Q))
#define _IQ3toIQ(A) ((long) (A) >> (3 - GLOBAL_Q))
#define _IQtoQ3(A) ((long) (A) << (3 - GLOBAL_Q))
#define _Q3toIQ(A) ((long) (A) >> (3 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 2)
#define _IQtoIQ2(A) ((long) (A) >> (GLOBAL_Q - 2))
#define _IQ2toIQ(A) ((long) (A) << (GLOBAL_Q - 2))
#define _IQtoQ2(A) ((long) (A) >> (GLOBAL_Q - 2))
#define _Q2toIQ(A) ((long) (A) << (GLOBAL_Q - 2))
#else
#define _IQtoIQ2(A) ((long) (A) << (2 - GLOBAL_Q))
#define _IQ2toIQ(A) ((long) (A) >> (2 - GLOBAL_Q))
#define _IQtoQ2(A) ((long) (A) << (2 - GLOBAL_Q))
#define _Q2toIQ(A) ((long) (A) >> (2 - GLOBAL_Q))
#endif
#if (GLOBAL_Q >= 1)
#define _IQtoQ1(A) ((long) (A) >> (GLOBAL_Q - 1))
#define _Q1toIQ(A) ((long) (A) << (GLOBAL_Q - 1))
#else
#define _IQtoQ1(A) ((long) (A) << (1 - GLOBAL_Q))
#define _Q1toIQ(A) ((long) (A) >> (1 - GLOBAL_Q))
#endif
#define _IQtoIQ1(A) ((long) (A) >> (GLOBAL_Q - 1))
#define _IQ1toIQ(A) ((long) (A) << (GLOBAL_Q - 1))
//---------------------------------------------------------------------------
#define _IQmpy(A,B) __IQmpy(A,B,GLOBAL_Q)
#define _IQ30mpy(A,B) __IQmpy(A,B,30)
#define _IQ29mpy(A,B) __IQmpy(A,B,29)
#define _IQ28mpy(A,B) __IQmpy(A,B,28)
#define _IQ27mpy(A,B) __IQmpy(A,B,27)
#define _IQ26mpy(A,B) __IQmpy(A,B,26)
#define _IQ25mpy(A,B) __IQmpy(A,B,25)
#define _IQ24mpy(A,B) __IQmpy(A,B,24)
#define _IQ23mpy(A,B) __IQmpy(A,B,23)
#define _IQ22mpy(A,B) __IQmpy(A,B,22)
#define _IQ21mpy(A,B) __IQmpy(A,B,21)
#define _IQ20mpy(A,B) __IQmpy(A,B,20)
#define _IQ19mpy(A,B) __IQmpy(A,B,19)
#define _IQ18mpy(A,B) __IQmpy(A,B,18)
#define _IQ17mpy(A,B) __IQmpy(A,B,17)
#define _IQ16mpy(A,B) __IQmpy(A,B,16)
#define _IQ15mpy(A,B) __IQmpy(A,B,15)
#define _IQ14mpy(A,B) __IQmpy(A,B,14)
#define _IQ13mpy(A,B) __IQmpy(A,B,13)
#define _IQ12mpy(A,B) __IQmpy(A,B,12)
#define _IQ11mpy(A,B) __IQmpy(A,B,11)
#define _IQ10mpy(A,B) __IQmpy(A,B,10)
#define _IQ9mpy(A,B) __IQmpy(A,B,9)
#define _IQ8mpy(A,B) __IQmpy(A,B,8)
#define _IQ7mpy(A,B) __IQmpy(A,B,7)
#define _IQ6mpy(A,B) __IQmpy(A,B,6)
#define _IQ5mpy(A,B) __IQmpy(A,B,5)
#define _IQ4mpy(A,B) __IQmpy(A,B,4)
#define _IQ3mpy(A,B) __IQmpy(A,B,3)
#define _IQ2mpy(A,B) __IQmpy(A,B,2)
#define _IQ1mpy(A,B) __IQmpy(A,B,1)
//---------------------------------------------------------------------------
extern long _IQ30rmpy(long A, long B);
extern long _IQ29rmpy(long A, long B);
extern long _IQ28rmpy(long A, long B);
extern long _IQ27rmpy(long A, long B);
extern long _IQ26rmpy(long A, long B);
extern long _IQ25rmpy(long A, long B);
extern long _IQ24rmpy(long A, long B);
extern long _IQ23rmpy(long A, long B);
extern long _IQ22rmpy(long A, long B);
extern long _IQ21rmpy(long A, long B);
extern long _IQ20rmpy(long A, long B);
extern long _IQ19rmpy(long A, long B);
extern long _IQ18rmpy(long A, long B);
extern long _IQ17rmpy(long A, long B);
extern long _IQ16rmpy(long A, long B);
extern long _IQ15rmpy(long A, long B);
extern long _IQ14rmpy(long A, long B);
extern long _IQ13rmpy(long A, long B);
extern long _IQ12rmpy(long A, long B);
extern long _IQ11rmpy(long A, long B);
extern long _IQ10rmpy(long A, long B);
extern long _IQ9rmpy(long A, long B);
extern long _IQ8rmpy(long A, long B);
extern long _IQ7rmpy(long A, long B);
extern long _IQ6rmpy(long A, long B);
extern long _IQ5rmpy(long A, long B);
extern long _IQ4rmpy(long A, long B);
extern long _IQ3rmpy(long A, long B);
extern long _IQ2rmpy(long A, long B);
extern long _IQ1rmpy(long A, long B);
#if GLOBAL_Q == 30
#define _IQrmpy(A,B) _IQ30rmpy(A,B)
#endif
#if GLOBAL_Q == 29
#define _IQrmpy(A,B) _IQ29rmpy(A,B)
#endif
#if GLOBAL_Q == 28
#define _IQrmpy(A,B) _IQ28rmpy(A,B)
#endif
#if GLOBAL_Q == 27
#define _IQrmpy(A,B) _IQ27rmpy(A,B)
#endif
#if GLOBAL_Q == 26
#define _IQrmpy(A,B) _IQ26rmpy(A,B)
#endif
#if GLOBAL_Q == 25
#define _IQrmpy(A,B) _IQ25rmpy(A,B)
#endif
#if GLOBAL_Q == 24
#define _IQrmpy(A,B) _IQ24rmpy(A,B)
#endif
#if GLOBAL_Q == 23
#define _IQrmpy(A,B) _IQ23rmpy(A,B)
#endif
#if GLOBAL_Q == 22
#define _IQrmpy(A,B) _IQ22rmpy(A,B)
#endif
#if GLOBAL_Q == 21
#define _IQrmpy(A,B) _IQ21rmpy(A,B)
#endif
#if GLOBAL_Q == 20
#define _IQrmpy(A,B) _IQ20rmpy(A,B)
#endif
#if GLOBAL_Q == 19
#define _IQrmpy(A,B) _IQ19rmpy(A,B)
#endif
#if GLOBAL_Q == 18
#define _IQrmpy(A,B) _IQ18rmpy(A,B)
#endif
#if GLOBAL_Q == 17
#define _IQrmpy(A,B) _IQ17rmpy(A,B)
#endif
#if GLOBAL_Q == 16
#define _IQrmpy(A,B) _IQ16rmpy(A,B)
#endif
#if GLOBAL_Q == 15
#define _IQrmpy(A,B) _IQ15rmpy(A,B)
#endif
#if GLOBAL_Q == 14
#define _IQrmpy(A,B) _IQ14rmpy(A,B)
#endif
#if GLOBAL_Q == 13
#define _IQrmpy(A,B) _IQ13rmpy(A,B)
#endif
#if GLOBAL_Q == 12
#define _IQrmpy(A,B) _IQ12rmpy(A,B)
#endif
#if GLOBAL_Q == 11
#define _IQrmpy(A,B) _IQ11rmpy(A,B)
#endif
#if GLOBAL_Q == 10
#define _IQrmpy(A,B) _IQ10rmpy(A,B)
#endif
#if GLOBAL_Q == 9
#define _IQrmpy(A,B) _IQ9rmpy(A,B)
#endif
#if GLOBAL_Q == 8
#define _IQrmpy(A,B) _IQ8rmpy(A,B)
#endif
#if GLOBAL_Q == 7
#define _IQrmpy(A,B) _IQ7rmpy(A,B)
#endif
#if GLOBAL_Q == 6
#define _IQrmpy(A,B) _IQ6rmpy(A,B)
#endif
#if GLOBAL_Q == 5
#define _IQrmpy(A,B) _IQ5rmpy(A,B)
#endif
#if GLOBAL_Q == 4
#define _IQrmpy(A,B) _IQ4rmpy(A,B)
#endif
#if GLOBAL_Q == 3
#define _IQrmpy(A,B) _IQ3rmpy(A,B)
#endif
#if GLOBAL_Q == 2
#define _IQrmpy(A,B) _IQ2rmpy(A,B)
#endif
#if GLOBAL_Q == 1
#define _IQrmpy(A,B) _IQ1rmpy(A,B)
#endif
//---------------------------------------------------------------------------
extern long _IQ30rsmpy(long A, long B);
extern long _IQ29rsmpy(long A, long B);
extern long _IQ28rsmpy(long A, long B);
extern long _IQ27rsmpy(long A, long B);
extern long _IQ26rsmpy(long A, long B);
extern long _IQ25rsmpy(long A, long B);
extern long _IQ24rsmpy(long A, long B);
extern long _IQ23rsmpy(long A, long B);
extern long _IQ22rsmpy(long A, long B);
extern long _IQ21rsmpy(long A, long B);
extern long _IQ20rsmpy(long A, long B);
extern long _IQ19rsmpy(long A, long B);
extern long _IQ18rsmpy(long A, long B);
extern long _IQ17rsmpy(long A, long B);
extern long _IQ16rsmpy(long A, long B);
extern long _IQ15rsmpy(long A, long B);
extern long _IQ14rsmpy(long A, long B);
extern long _IQ13rsmpy(long A, long B);
extern long _IQ12rsmpy(long A, long B);
extern long _IQ11rsmpy(long A, long B);
extern long _IQ10rsmpy(long A, long B);
extern long _IQ9rsmpy(long A, long B);
extern long _IQ8rsmpy(long A, long B);
extern long _IQ7rsmpy(long A, long B);
extern long _IQ6rsmpy(long A, long B);
extern long _IQ5rsmpy(long A, long B);
extern long _IQ4rsmpy(long A, long B);
extern long _IQ3rsmpy(long A, long B);
extern long _IQ2rsmpy(long A, long B);
extern long _IQ1rsmpy(long A, long B);
#if GLOBAL_Q == 30
#define _IQrsmpy(A,B) _IQ30rsmpy(A,B)
#endif
#if GLOBAL_Q == 29
#define _IQrsmpy(A,B) _IQ29rsmpy(A,B)
#endif
#if GLOBAL_Q == 28
#define _IQrsmpy(A,B) _IQ28rsmpy(A,B)
#endif
#if GLOBAL_Q == 27
#define _IQrsmpy(A,B) _IQ27rsmpy(A,B)
#endif
#if GLOBAL_Q == 26
#define _IQrsmpy(A,B) _IQ26rsmpy(A,B)
#endif
#if GLOBAL_Q == 25
#define _IQrsmpy(A,B) _IQ25rsmpy(A,B)
#endif
#if GLOBAL_Q == 24
#define _IQrsmpy(A,B) _IQ24rsmpy(A,B)
#endif
#if GLOBAL_Q == 23
#define _IQrsmpy(A,B) _IQ23rsmpy(A,B)
#endif
#if GLOBAL_Q == 22
#define _IQrsmpy(A,B) _IQ22rsmpy(A,B)
#endif
#if GLOBAL_Q == 21
#define _IQrsmpy(A,B) _IQ21rsmpy(A,B)
#endif
#if GLOBAL_Q == 20
#define _IQrsmpy(A,B) _IQ20rsmpy(A,B)
#endif
#if GLOBAL_Q == 19
#define _IQrsmpy(A,B) _IQ19rsmpy(A,B)
#endif
#if GLOBAL_Q == 18
#define _IQrsmpy(A,B) _IQ18rsmpy(A,B)
#endif
#if GLOBAL_Q == 17
#define _IQrsmpy(A,B) _IQ17rsmpy(A,B)
#endif
#if GLOBAL_Q == 16
#define _IQrsmpy(A,B) _IQ16rsmpy(A,B)
#endif
#if GLOBAL_Q == 15
#define _IQrsmpy(A,B) _IQ15rsmpy(A,B)
#endif
#if GLOBAL_Q == 14
#define _IQrsmpy(A,B) _IQ14rsmpy(A,B)
#endif
#if GLOBAL_Q == 13
#define _IQrsmpy(A,B) _IQ13rsmpy(A,B)
#endif
#if GLOBAL_Q == 12
#define _IQrsmpy(A,B) _IQ12rsmpy(A,B)
#endif
#if GLOBAL_Q == 11
#define _IQrsmpy(A,B) _IQ11rsmpy(A,B)
#endif
#if GLOBAL_Q == 10
#define _IQrsmpy(A,B) _IQ10rsmpy(A,B)
#endif
#if GLOBAL_Q == 9
#define _IQrsmpy(A,B) _IQ9rsmpy(A,B)
#endif
#if GLOBAL_Q == 8
#define _IQrsmpy(A,B) _IQ8rsmpy(A,B)
#endif
#if GLOBAL_Q == 7
#define _IQrsmpy(A,B) _IQ7rsmpy(A,B)
#endif
#if GLOBAL_Q == 6
#define _IQrsmpy(A,B) _IQ6rsmpy(A,B)
#endif
#if GLOBAL_Q == 5
#define _IQrsmpy(A,B) _IQ5rsmpy(A,B)
#endif
#if GLOBAL_Q == 4
#define _IQrsmpy(A,B) _IQ4rsmpy(A,B)
#endif
#if GLOBAL_Q == 3
#define _IQrsmpy(A,B) _IQ3rsmpy(A,B)
#endif
#if GLOBAL_Q == 2
#define _IQrsmpy(A,B) _IQ2rsmpy(A,B)
#endif
#if GLOBAL_Q == 1
#define _IQrsmpy(A,B) _IQ1rsmpy(A,B)
#endif
//---------------------------------------------------------------------------
extern long _IQ30div(long A, long B);
extern long _IQ29div(long A, long B);
extern long _IQ28div(long A, long B);
extern long _IQ27div(long A, long B);
extern long _IQ26div(long A, long B);
extern long _IQ25div(long A, long B);
extern long _IQ24div(long A, long B);
extern long _IQ23div(long A, long B);
extern long _IQ22div(long A, long B);
extern long _IQ21div(long A, long B);
extern long _IQ20div(long A, long B);
extern long _IQ19div(long A, long B);
extern long _IQ18div(long A, long B);
extern long _IQ17div(long A, long B);
extern long _IQ16div(long A, long B);
extern long _IQ15div(long A, long B);
extern long _IQ14div(long A, long B);
extern long _IQ13div(long A, long B);
extern long _IQ12div(long A, long B);
extern long _IQ11div(long A, long B);
extern long _IQ10div(long A, long B);
extern long _IQ9div(long A, long B);
extern long _IQ8div(long A, long B);
extern long _IQ7div(long A, long B);
extern long _IQ6div(long A, long B);
extern long _IQ5div(long A, long B);
extern long _IQ4div(long A, long B);
extern long _IQ3div(long A, long B);
extern long _IQ2div(long A, long B);
extern long _IQ1div(long A, long B);
#if GLOBAL_Q == 30
#define _IQdiv(A,B) _IQ30div(A,B)
#endif
#if GLOBAL_Q == 29
#define _IQdiv(A,B) _IQ29div(A,B)
#endif
#if GLOBAL_Q == 28
#define _IQdiv(A,B) _IQ28div(A,B)
#endif
#if GLOBAL_Q == 27
#define _IQdiv(A,B) _IQ27div(A,B)
#endif
#if GLOBAL_Q == 26
#define _IQdiv(A,B) _IQ26div(A,B)
#endif
#if GLOBAL_Q == 25
#define _IQdiv(A,B) _IQ25div(A,B)
#endif
#if GLOBAL_Q == 24
#define _IQdiv(A,B) _IQ24div(A,B)
#endif
#if GLOBAL_Q == 23
#define _IQdiv(A,B) _IQ23div(A,B)
#endif
#if GLOBAL_Q == 22
#define _IQdiv(A,B) _IQ22div(A,B)
#endif
#if GLOBAL_Q == 21
#define _IQdiv(A,B) _IQ21div(A,B)
#endif
#if GLOBAL_Q == 20
#define _IQdiv(A,B) _IQ20div(A,B)
#endif
#if GLOBAL_Q == 19
#define _IQdiv(A,B) _IQ19div(A,B)
#endif
#if GLOBAL_Q == 18
#define _IQdiv(A,B) _IQ18div(A,B)
#endif
#if GLOBAL_Q == 17
#define _IQdiv(A,B) _IQ17div(A,B)
#endif
#if GLOBAL_Q == 16
#define _IQdiv(A,B) _IQ16div(A,B)
#endif
#if GLOBAL_Q == 15
#define _IQdiv(A,B) _IQ15div(A,B)
#endif
#if GLOBAL_Q == 14
#define _IQdiv(A,B) _IQ14div(A,B)
#endif
#if GLOBAL_Q == 13
#define _IQdiv(A,B) _IQ13div(A,B)
#endif
#if GLOBAL_Q == 12
#define _IQdiv(A,B) _IQ12div(A,B)
#endif
#if GLOBAL_Q == 11
#define _IQdiv(A,B) _IQ11div(A,B)
#endif
#if GLOBAL_Q == 10
#define _IQdiv(A,B) _IQ10div(A,B)
#endif
#if GLOBAL_Q == 9
#define _IQdiv(A,B) _IQ9div(A,B)
#endif
#if GLOBAL_Q == 8
#define _IQdiv(A,B) _IQ8div(A,B)
#endif
#if GLOBAL_Q == 7
#define _IQdiv(A,B) _IQ7div(A,B)
#endif
#if GLOBAL_Q == 6
#define _IQdiv(A,B) _IQ6div(A,B)
#endif
#if GLOBAL_Q == 5
#define _IQdiv(A,B) _IQ5div(A,B)
#endif
#if GLOBAL_Q == 4
#define _IQdiv(A,B) _IQ4div(A,B)
#endif
#if GLOBAL_Q == 3
#define _IQdiv(A,B) _IQ3div(A,B)
#endif
#if GLOBAL_Q == 2
#define _IQdiv(A,B) _IQ2div(A,B)
#endif
#if GLOBAL_Q == 1
#define _IQdiv(A,B) _IQ1div(A,B)
#endif
//---------------------------------------------------------------------------
extern long _IQ30sin(long A);
extern long _IQ29sin(long A);
extern long _IQ28sin(long A);
extern long _IQ27sin(long A);
extern long _IQ26sin(long A);
extern long _IQ25sin(long A);
extern long _IQ24sin(long A);
extern long _IQ23sin(long A);
extern long _IQ22sin(long A);
extern long _IQ21sin(long A);
extern long _IQ20sin(long A);
extern long _IQ19sin(long A);
extern long _IQ18sin(long A);
extern long _IQ17sin(long A);
extern long _IQ16sin(long A);
extern long _IQ15sin(long A);
extern long _IQ14sin(long A);
extern long _IQ13sin(long A);
extern long _IQ12sin(long A);
extern long _IQ11sin(long A);
extern long _IQ10sin(long A);
extern long _IQ9sin(long A);
extern long _IQ8sin(long A);
extern long _IQ7sin(long A);
extern long _IQ6sin(long A);
extern long _IQ5sin(long A);
extern long _IQ4sin(long A);
extern long _IQ3sin(long A);
extern long _IQ2sin(long A);
extern long _IQ1sin(long A);
#if GLOBAL_Q == 30
#define _IQsin(A) _IQ30sin(A)
#endif
#if GLOBAL_Q == 29
#define _IQsin(A) _IQ29sin(A)
#endif
#if GLOBAL_Q == 28
#define _IQsin(A) _IQ28sin(A)
#endif
#if GLOBAL_Q == 27
#define _IQsin(A) _IQ27sin(A)
#endif
#if GLOBAL_Q == 26
#define _IQsin(A) _IQ26sin(A)
#endif
#if GLOBAL_Q == 25
#define _IQsin(A) _IQ25sin(A)
#endif
#if GLOBAL_Q == 24
#define _IQsin(A) _IQ24sin(A)
#endif
#if GLOBAL_Q == 23
#define _IQsin(A) _IQ23sin(A)
#endif
#if GLOBAL_Q == 22
#define _IQsin(A) _IQ22sin(A)
#endif
#if GLOBAL_Q == 21
#define _IQsin(A) _IQ21sin(A)
#endif
#if GLOBAL_Q == 20
#define _IQsin(A) _IQ20sin(A)
#endif
#if GLOBAL_Q == 19
#define _IQsin(A) _IQ19sin(A)
#endif
#if GLOBAL_Q == 18
#define _IQsin(A) _IQ18sin(A)
#endif
#if GLOBAL_Q == 17
#define _IQsin(A) _IQ17sin(A)
#endif
#if GLOBAL_Q == 16
#define _IQsin(A) _IQ16sin(A)
#endif
#if GLOBAL_Q == 15
#define _IQsin(A) _IQ15sin(A)
#endif
#if GLOBAL_Q == 14
#define _IQsin(A) _IQ14sin(A)
#endif
#if GLOBAL_Q == 13
#define _IQsin(A) _IQ13sin(A)
#endif
#if GLOBAL_Q == 12
#define _IQsin(A) _IQ12sin(A)
#endif
#if GLOBAL_Q == 11
#define _IQsin(A) _IQ11sin(A)
#endif
#if GLOBAL_Q == 10
#define _IQsin(A) _IQ10sin(A)
#endif
#if GLOBAL_Q == 9
#define _IQsin(A) _IQ9sin(A)
#endif
#if GLOBAL_Q == 8
#define _IQsin(A) _IQ8sin(A)
#endif
#if GLOBAL_Q == 7
#define _IQsin(A) _IQ7sin(A)
#endif
#if GLOBAL_Q == 6
#define _IQsin(A) _IQ6sin(A)
#endif
#if GLOBAL_Q == 5
#define _IQsin(A) _IQ5sin(A)
#endif
#if GLOBAL_Q == 4
#define _IQsin(A) _IQ4sin(A)
#endif
#if GLOBAL_Q == 3
#define _IQsin(A) _IQ3sin(A)
#endif
#if GLOBAL_Q == 2
#define _IQsin(A) _IQ2sin(A)
#endif
#if GLOBAL_Q == 1
#define _IQsin(A) _IQ1sin(A)
#endif
//---------------------------------------------------------------------------
extern long _IQ30sinPU(long A);
extern long _IQ29sinPU(long A);
extern long _IQ28sinPU(long A);
extern long _IQ27sinPU(long A);
extern long _IQ26sinPU(long A);
extern long _IQ25sinPU(long A);
extern long _IQ24sinPU(long A);
extern long _IQ23sinPU(long A);
extern long _IQ22sinPU(long A);
extern long _IQ21sinPU(long A);
extern long _IQ20sinPU(long A);
extern long _IQ19sinPU(long A);
extern long _IQ18sinPU(long A);
extern long _IQ17sinPU(long A);
extern long _IQ16sinPU(long A);
extern long _IQ15sinPU(long A);
extern long _IQ14sinPU(long A);
extern long _IQ13sinPU(long A);
extern long _IQ12sinPU(long A);
extern long _IQ11sinPU(long A);
extern long _IQ10sinPU(long A);
extern long _IQ9sinPU(long A);
extern long _IQ8sinPU(long A);
extern long _IQ7sinPU(long A);
extern long _IQ6sinPU(long A);
extern long _IQ5sinPU(long A);
extern long _IQ4sinPU(long A);
extern long _IQ3sinPU(long A);
extern long _IQ2sinPU(long A);
extern long _IQ1sinPU(long A);
#if GLOBAL_Q == 30
#define _IQsinPU(A) _IQ30sinPU(A)
#endif
#if GLOBAL_Q == 29
#define _IQsinPU(A) _IQ29sinPU(A)
#endif
#if GLOBAL_Q == 28
#define _IQsinPU(A) _IQ28sinPU(A)
#endif
#if GLOBAL_Q == 27
#define _IQsinPU(A) _IQ27sinPU(A)
#endif
#if GLOBAL_Q == 26
#define _IQsinPU(A) _IQ26sinPU(A)
#endif
#if GLOBAL_Q == 25
#define _IQsinPU(A) _IQ25sinPU(A)
#endif
#if GLOBAL_Q == 24
#define _IQsinPU(A) _IQ24sinPU(A)
#endif
#if GLOBAL_Q == 23
#define _IQsinPU(A) _IQ23sinPU(A)
#endif
#if GLOBAL_Q == 22
#define _IQsinPU(A) _IQ22sinPU(A)
#endif
#if GLOBAL_Q == 21
#define _IQsinPU(A) _IQ21sinPU(A)
#endif
#if GLOBAL_Q == 20
#define _IQsinPU(A) _IQ20sinPU(A)
#endif
#if GLOBAL_Q == 19
#define _IQsinPU(A) _IQ19sinPU(A)
#endif
#if GLOBAL_Q == 18
#define _IQsinPU(A) _IQ18sinPU(A)
#endif
#if GLOBAL_Q == 17
#define _IQsinPU(A) _IQ17sinPU(A)
#endif
#if GLOBAL_Q == 16
#define _IQsinPU(A) _IQ16sinPU(A)
#endif
#if GLOBAL_Q == 15
#define _IQsinPU(A) _IQ15sinPU(A)
#endif
#if GLOBAL_Q == 14
#define _IQsinPU(A) _IQ14sinPU(A)
#endif
#if GLOBAL_Q == 13
#define _IQsinPU(A) _IQ13sinPU(A)
#endif
#if GLOBAL_Q == 12
#define _IQsinPU(A) _IQ12sinPU(A)
#endif
#if GLOBAL_Q == 11
#define _IQsinPU(A) _IQ11sinPU(A)
#endif
#if GLOBAL_Q == 10
#define _IQsinPU(A) _IQ10sinPU(A)
#endif
#if GLOBAL_Q == 9
#define _IQsinPU(A) _IQ9sinPU(A)
#endif
#if GLOBAL_Q == 8
#define _IQsinPU(A) _IQ8sinPU(A)
#endif
#if GLOBAL_Q == 7
#define _IQsinPU(A) _IQ7sinPU(A)
#endif
#if GLOBAL_Q == 6
#define _IQsinPU(A) _IQ6sinPU(A)
#endif
#if GLOBAL_Q == 5
#define _IQsinPU(A) _IQ5sinPU(A)
#endif
#if GLOBAL_Q == 4
#define _IQsinPU(A) _IQ4sinPU(A)
#endif
#if GLOBAL_Q == 3
#define _IQsinPU(A) _IQ3sinPU(A)
#endif
#if GLOBAL_Q == 2
#define _IQsinPU(A) _IQ2sinPU(A)
#endif
#if GLOBAL_Q == 1
#define _IQsinPU(A) _IQ1sinPU(A)
#endif
//---------------------------------------------------------------------------
extern long _IQ30asin(long A);
extern long _IQ29asin(long A);
extern long _IQ28asin(long A);
extern long _IQ27asin(long A);
extern long _IQ26asin(long A);
extern long _IQ25asin(long A);
extern long _IQ24asin(long A);
extern long _IQ23asin(long A);
extern long _IQ22asin(long A);
extern long _IQ21asin(long A);
extern long _IQ20asin(long A);
extern long _IQ19asin(long A);
extern long _IQ18asin(long A);
extern long _IQ17asin(long A);
extern long _IQ16asin(long A);
extern long _IQ15asin(long A);
extern long _IQ14asin(long A);
extern long _IQ13asin(long A);
extern long _IQ12asin(long A);
extern long _IQ11asin(long A);
extern long _IQ10asin(long A);
extern long _IQ9asin(long A);
extern long _IQ8asin(long A);
extern long _IQ7asin(long A);
extern long _IQ6asin(long A);
extern long _IQ5asin(long A);
extern long _IQ4asin(long A);
extern long _IQ3asin(long A);
extern long _IQ2asin(long A);
extern long _IQ1asin(long A);
#if GLOBAL_Q == 30
#define _IQasin(A) _IQ30asin(A)
#endif
#if GLOBAL_Q == 29
#define _IQasin(A) _IQ29asin(A)
#endif
#if GLOBAL_Q == 28
#define _IQasin(A) _IQ28asin(A)
#endif
#if GLOBAL_Q == 27
#define _IQasin(A) _IQ27asin(A)
#endif
#if GLOBAL_Q == 26
#define _IQasin(A) _IQ26asin(A)
#endif
#if GLOBAL_Q == 25
#define _IQasin(A) _IQ25asin(A)
#endif
#if GLOBAL_Q == 24
#define _IQasin(A) _IQ24asin(A)
#endif
#if GLOBAL_Q == 23
#define _IQasin(A) _IQ23asin(A)
#endif
#if GLOBAL_Q == 22
#define _IQasin(A) _IQ22asin(A)
#endif
#if GLOBAL_Q == 21
#define _IQasin(A) _IQ21asin(A)
#endif
#if GLOBAL_Q == 20
#define _IQasin(A) _IQ20asin(A)
#endif
#if GLOBAL_Q == 19
#define _IQasin(A) _IQ19asin(A)
#endif
#if GLOBAL_Q == 18
#define _IQasin(A) _IQ18asin(A)
#endif
#if GLOBAL_Q == 17
#define _IQasin(A) _IQ17asin(A)
#endif
#if GLOBAL_Q == 16
#define _IQasin(A) _IQ16asin(A)
#endif
#if GLOBAL_Q == 15
#define _IQasin(A) _IQ15asin(A)
#endif
#if GLOBAL_Q == 14
#define _IQasin(A) _IQ14asin(A)
#endif
#if GLOBAL_Q == 13
#define _IQasin(A) _IQ13asin(A)
#endif
#if GLOBAL_Q == 12
#define _IQasin(A) _IQ12asin(A)
#endif
#if GLOBAL_Q == 11
#define _IQasin(A) _IQ11asin(A)
#endif
#if GLOBAL_Q == 10
#define _IQasin(A) _IQ10asin(A)
#endif
#if GLOBAL_Q == 9
#define _IQasin(A) _IQ9asin(A)
#endif
#if GLOBAL_Q == 8
#define _IQasin(A) _IQ8asin(A)
#endif
#if GLOBAL_Q == 7
#define _IQasin(A) _IQ7asin(A)
#endif
#if GLOBAL_Q == 6
#define _IQasin(A) _IQ6asin(A)
#endif
#if GLOBAL_Q == 5
#define _IQasin(A) _IQ5asin(A)
#endif
#if GLOBAL_Q == 4
#define _IQasin(A) _IQ4asin(A)
#endif
#if GLOBAL_Q == 3
#define _IQasin(A) _IQ3asin(A)
#endif
#if GLOBAL_Q == 2
#define _IQasin(A) _IQ2asin(A)
#endif
#if GLOBAL_Q == 1
#define _IQasin(A) _IQ1asin(A)
#endif
//---------------------------------------------------------------------------
extern long _IQ30cos(long A);
extern long _IQ29cos(long A);
extern long _IQ28cos(long A);
extern long _IQ27cos(long A);
extern long _IQ26cos(long A);
extern long _IQ25cos(long A);
extern long _IQ24cos(long A);
extern long _IQ23cos(long A);
extern long _IQ22cos(long A);
extern long _IQ21cos(long A);
extern long _IQ20cos(long A);
extern long _IQ19cos(long A);
extern long _IQ18cos(long A);
extern long _IQ17cos(long A);
extern long _IQ16cos(long A);
extern long _IQ15cos(long A);
extern long _IQ14cos(long A);
extern long _IQ13cos(long A);
extern long _IQ12cos(long A);
extern long _IQ11cos(long A);
extern long _IQ10cos(long A);
extern long _IQ9cos(long A);
extern long _IQ8cos(long A);
extern long _IQ7cos(long A);
extern long _IQ6cos(long A);
extern long _IQ5cos(long A);
extern long _IQ4cos(long A);
extern long _IQ3cos(long A);
extern long _IQ2cos(long A);
extern long _IQ1cos(long A);
#if GLOBAL_Q == 30
#define _IQcos(A) _IQ30cos(A)
#endif
#if GLOBAL_Q == 29
#define _IQcos(A) _IQ29cos(A)
#endif
#if GLOBAL_Q == 28
#define _IQcos(A) _IQ28cos(A)
#endif
#if GLOBAL_Q == 27
#define _IQcos(A) _IQ27cos(A)
#endif
#if GLOBAL_Q == 26
#define _IQcos(A) _IQ26cos(A)
#endif
#if GLOBAL_Q == 25
#define _IQcos(A) _IQ25cos(A)
#endif
#if GLOBAL_Q == 24
#define _IQcos(A) _IQ24cos(A)
#endif
#if GLOBAL_Q == 23
#define _IQcos(A) _IQ23cos(A)
#endif
#if GLOBAL_Q == 22
#define _IQcos(A) _IQ22cos(A)
#endif
#if GLOBAL_Q == 21
#define _IQcos(A) _IQ21cos(A)
#endif
#if GLOBAL_Q == 20
#define _IQcos(A) _IQ20cos(A)
#endif
#if GLOBAL_Q == 19
#define _IQcos(A) _IQ19cos(A)
#endif
#if GLOBAL_Q == 18
#define _IQcos(A) _IQ18cos(A)
#endif
#if GLOBAL_Q == 17
#define _IQcos(A) _IQ17cos(A)
#endif
#if GLOBAL_Q == 16
#define _IQcos(A) _IQ16cos(A)
#endif
#if GLOBAL_Q == 15
#define _IQcos(A) _IQ15cos(A)
#endif
#if GLOBAL_Q == 14
#define _IQcos(A) _IQ14cos(A)
#endif
#if GLOBAL_Q == 13
#define _IQcos(A) _IQ13cos(A)
#endif
#if GLOBAL_Q == 12
#define _IQcos(A) _IQ12cos(A)
#endif
#if GLOBAL_Q == 11
#define _IQcos(A) _IQ11cos(A)
#endif
#if GLOBAL_Q == 10
#define _IQcos(A) _IQ10cos(A)
#endif
#if GLOBAL_Q == 9
#define _IQcos(A) _IQ9cos(A)
#endif
#if GLOBAL_Q == 8
#define _IQcos(A) _IQ8cos(A)
#endif
#if GLOBAL_Q == 7
#define _IQcos(A) _IQ7cos(A)
#endif
#if GLOBAL_Q == 6
#define _IQcos(A) _IQ6cos(A)
#endif
#if GLOBAL_Q == 5
#define _IQcos(A) _IQ5cos(A)
#endif
#if GLOBAL_Q == 4
#define _IQcos(A) _IQ4cos(A)
#endif
#if GLOBAL_Q == 3
#define _IQcos(A) _IQ3cos(A)
#endif
#if GLOBAL_Q == 2
#define _IQcos(A) _IQ2cos(A)
#endif
#if GLOBAL_Q == 1
#define _IQcos(A) _IQ1cos(A)
#endif
//---------------------------------------------------------------------------
extern long _IQ30cosPU(long A);
extern long _IQ29cosPU(long A);
extern long _IQ28cosPU(long A);
extern long _IQ27cosPU(long A);
extern long _IQ26cosPU(long A);
extern long _IQ25cosPU(long A);
extern long _IQ24cosPU(long A);
extern long _IQ23cosPU(long A);
extern long _IQ22cosPU(long A);
extern long _IQ21cosPU(long A);
extern long _IQ20cosPU(long A);
extern long _IQ19cosPU(long A);
extern long _IQ18cosPU(long A);
extern long _IQ17cosPU(long A);
extern long _IQ16cosPU(long A);
extern long _IQ15cosPU(long A);
extern long _IQ14cosPU(long A);
extern long _IQ13cosPU(long A);
extern long _IQ12cosPU(long A);
extern long _IQ11cosPU(long A);
extern long _IQ10cosPU(long A);
extern long _IQ9cosPU(long A);
extern long _IQ8cosPU(long A);
extern long _IQ7cosPU(long A);
extern long _IQ6cosPU(long A);
extern long _IQ5cosPU(long A);
extern long _IQ4cosPU(long A);
extern long _IQ3cosPU(long A);
extern long _IQ2cosPU(long A);
extern long _IQ1cosPU(long A);
#if GLOBAL_Q == 30
#define _IQcosPU(A) _IQ30cosPU(A)
#endif
#if GLOBAL_Q == 29
#define _IQcosPU(A) _IQ29cosPU(A)
#endif
#if GLOBAL_Q == 28
#define _IQcosPU(A) _IQ28cosPU(A)
#endif
#if GLOBAL_Q == 27
#define _IQcosPU(A) _IQ27cosPU(A)
#endif
#if GLOBAL_Q == 26
#define _IQcosPU(A) _IQ26cosPU(A)
#endif
#if GLOBAL_Q == 25
#define _IQcosPU(A) _IQ25cosPU(A)
#endif
#if GLOBAL_Q == 24
#define _IQcosPU(A) _IQ24cosPU(A)
#endif
#if GLOBAL_Q == 23
#define _IQcosPU(A) _IQ23cosPU(A)
#endif
#if GLOBAL_Q == 22
#define _IQcosPU(A) _IQ22cosPU(A)
#endif
#if GLOBAL_Q == 21
#define _IQcosPU(A) _IQ21cosPU(A)
#endif
#if GLOBAL_Q == 20
#define _IQcosPU(A) _IQ20cosPU(A)
#endif
#if GLOBAL_Q == 19
#define _IQcosPU(A) _IQ19cosPU(A)
#endif
#if GLOBAL_Q == 18
#define _IQcosPU(A) _IQ18cosPU(A)
#endif
#if GLOBAL_Q == 17
#define _IQcosPU(A) _IQ17cosPU(A)
#endif
#if GLOBAL_Q == 16
#define _IQcosPU(A) _IQ16cosPU(A)
#endif
#if GLOBAL_Q == 15
#define _IQcosPU(A) _IQ15cosPU(A)
#endif
#if GLOBAL_Q == 14
#define _IQcosPU(A) _IQ14cosPU(A)
#endif
#if GLOBAL_Q == 13
#define _IQcosPU(A) _IQ13cosPU(A)
#endif
#if GLOBAL_Q == 12
#define _IQcosPU(A) _IQ12cosPU(A)
#endif
#if GLOBAL_Q == 11
#define _IQcosPU(A) _IQ11cosPU(A)
#endif
#if GLOBAL_Q == 10
#define _IQcosPU(A) _IQ10cosPU(A)
#endif
#if GLOBAL_Q == 9
#define _IQcosPU(A) _IQ9cosPU(A)
#endif
#if GLOBAL_Q == 8
#define _IQcosPU(A) _IQ8cosPU(A)
#endif
#if GLOBAL_Q == 7
#define _IQcosPU(A) _IQ7cosPU(A)
#endif
#if GLOBAL_Q == 6
#define _IQcosPU(A) _IQ6cosPU(A)
#endif
#if GLOBAL_Q == 5
#define _IQcosPU(A) _IQ5cosPU(A)
#endif
#if GLOBAL_Q == 4
#define _IQcosPU(A) _IQ4cosPU(A)
#endif
#if GLOBAL_Q == 3
#define _IQcosPU(A) _IQ3cosPU(A)
#endif
#if GLOBAL_Q == 2
#define _IQcosPU(A) _IQ2cosPU(A)
#endif
#if GLOBAL_Q == 1
#define _IQcosPU(A) _IQ1cosPU(A)
#endif
//---------------------------------------------------------------------------
extern long _IQ30acos(long A);
extern long _IQ29acos(long A);
extern long _IQ28acos(long A);
extern long _IQ27acos(long A);
extern long _IQ26acos(long A);
extern long _IQ25acos(long A);
extern long _IQ24acos(long A);
extern long _IQ23acos(long A);
extern long _IQ22acos(long A);
extern long _IQ21acos(long A);
extern long _IQ20acos(long A);
extern long _IQ19acos(long A);
extern long _IQ18acos(long A);
extern long _IQ17acos(long A);
extern long _IQ16acos(long A);
extern long _IQ15acos(long A);
extern long _IQ14acos(long A);
extern long _IQ13acos(long A);
extern long _IQ12acos(long A);
extern long _IQ11acos(long A);
extern long _IQ10acos(long A);
extern long _IQ9acos(long A);
extern long _IQ8acos(long A);
extern long _IQ7acos(long A);
extern long _IQ6acos(long A);
extern long _IQ5acos(long A);
extern long _IQ4acos(long A);
extern long _IQ3acos(long A);
extern long _IQ2acos(long A);
extern long _IQ1acos(long A);
#if GLOBAL_Q == 30
#define _IQacos(A) _IQ30acos(A)
#endif
#if GLOBAL_Q == 29
#define _IQacos(A) _IQ29acos(A)
#endif
#if GLOBAL_Q == 28
#define _IQacos(A) _IQ28acos(A)
#endif
#if GLOBAL_Q == 27
#define _IQacos(A) _IQ27acos(A)
#endif
#if GLOBAL_Q == 26
#define _IQacos(A) _IQ26acos(A)
#endif
#if GLOBAL_Q == 25
#define _IQacos(A) _IQ25acos(A)
#endif
#if GLOBAL_Q == 24
#define _IQacos(A) _IQ24acos(A)
#endif
#if GLOBAL_Q == 23
#define _IQacos(A) _IQ23acos(A)
#endif
#if GLOBAL_Q == 22
#define _IQacos(A) _IQ22acos(A)
#endif
#if GLOBAL_Q == 21
#define _IQacos(A) _IQ21acos(A)
#endif
#if GLOBAL_Q == 20
#define _IQacos(A) _IQ20acos(A)
#endif
#if GLOBAL_Q == 19
#define _IQacos(A) _IQ19acos(A)
#endif
#if GLOBAL_Q == 18
#define _IQacos(A) _IQ18acos(A)
#endif
#if GLOBAL_Q == 17
#define _IQacos(A) _IQ17acos(A)
#endif
#if GLOBAL_Q == 16
#define _IQacos(A) _IQ16acos(A)
#endif
#if GLOBAL_Q == 15
#define _IQacos(A) _IQ15acos(A)
#endif
#if GLOBAL_Q == 14
#define _IQacos(A) _IQ14acos(A)
#endif
#if GLOBAL_Q == 13
#define _IQacos(A) _IQ13acos(A)
#endif
#if GLOBAL_Q == 12
#define _IQacos(A) _IQ12acos(A)
#endif
#if GLOBAL_Q == 11
#define _IQacos(A) _IQ11acos(A)
#endif
#if GLOBAL_Q == 10
#define _IQacos(A) _IQ10acos(A)
#endif
#if GLOBAL_Q == 9
#define _IQacos(A) _IQ9acos(A)
#endif
#if GLOBAL_Q == 8
#define _IQacos(A) _IQ8acos(A)
#endif
#if GLOBAL_Q == 7
#define _IQacos(A) _IQ7acos(A)
#endif
#if GLOBAL_Q == 6
#define _IQacos(A) _IQ6acos(A)
#endif
#if GLOBAL_Q == 5
#define _IQacos(A) _IQ5acos(A)
#endif
#if GLOBAL_Q == 4
#define _IQacos(A) _IQ4acos(A)
#endif
#if GLOBAL_Q == 3
#define _IQacos(A) _IQ3acos(A)
#endif
#if GLOBAL_Q == 2
#define _IQacos(A) _IQ2acos(A)
#endif
#if GLOBAL_Q == 1
#define _IQacos(A) _IQ1acos(A)
#endif
//---------------------------------------------------------------------------
extern long _IQ30atan2(long A, long B);
extern long _IQ29atan2(long A, long B);
extern long _IQ28atan2(long A, long B);
extern long _IQ27atan2(long A, long B);
extern long _IQ26atan2(long A, long B);
extern long _IQ25atan2(long A, long B);
extern long _IQ24atan2(long A, long B);
extern long _IQ23atan2(long A, long B);
extern long _IQ22atan2(long A, long B);
extern long _IQ21atan2(long A, long B);
extern long _IQ20atan2(long A, long B);
extern long _IQ19atan2(long A, long B);
extern long _IQ18atan2(long A, long B);
extern long _IQ17atan2(long A, long B);
extern long _IQ16atan2(long A, long B);
extern long _IQ15atan2(long A, long B);
extern long _IQ14atan2(long A, long B);
extern long _IQ13atan2(long A, long B);
extern long _IQ12atan2(long A, long B);
extern long _IQ11atan2(long A, long B);
extern long _IQ10atan2(long A, long B);
extern long _IQ9atan2(long A, long B);
extern long _IQ8atan2(long A, long B);
extern long _IQ7atan2(long A, long B);
extern long _IQ6atan2(long A, long B);
extern long _IQ5atan2(long A, long B);
extern long _IQ4atan2(long A, long B);
extern long _IQ3atan2(long A, long B);
extern long _IQ2atan2(long A, long B);
extern long _IQ1atan2(long A, long B);
#if GLOBAL_Q == 30
#define _IQatan2(A,B) _IQ30atan2(A,B)
#endif
#if GLOBAL_Q == 29
#define _IQatan2(A,B) _IQ29atan2(A,B)
#endif
#if GLOBAL_Q == 28
#define _IQatan2(A,B) _IQ28atan2(A,B)
#endif
#if GLOBAL_Q == 27
#define _IQatan2(A,B) _IQ27atan2(A,B)
#endif
#if GLOBAL_Q == 26
#define _IQatan2(A,B) _IQ26atan2(A,B)
#endif
#if GLOBAL_Q == 25
#define _IQatan2(A,B) _IQ25atan2(A,B)
#endif
#if GLOBAL_Q == 24
#define _IQatan2(A,B) _IQ24atan2(A,B)
#endif
#if GLOBAL_Q == 23
#define _IQatan2(A,B) _IQ23atan2(A,B)
#endif
#if GLOBAL_Q == 22
#define _IQatan2(A,B) _IQ22atan2(A,B)
#endif
#if GLOBAL_Q == 21
#define _IQatan2(A,B) _IQ21atan2(A,B)
#endif
#if GLOBAL_Q == 20
#define _IQatan2(A,B) _IQ20atan2(A,B)
#endif
#if GLOBAL_Q == 19
#define _IQatan2(A,B) _IQ19atan2(A,B)
#endif
#if GLOBAL_Q == 18
#define _IQatan2(A,B) _IQ18atan2(A,B)
#endif
#if GLOBAL_Q == 17
#define _IQatan2(A,B) _IQ17atan2(A,B)
#endif
#if GLOBAL_Q == 16
#define _IQatan2(A,B) _IQ16atan2(A,B)
#endif
#if GLOBAL_Q == 15
#define _IQatan2(A,B) _IQ15atan2(A,B)
#endif
#if GLOBAL_Q == 14
#define _IQatan2(A,B) _IQ14atan2(A,B)
#endif
#if GLOBAL_Q == 13
#define _IQatan2(A,B) _IQ13atan2(A,B)
#endif
#if GLOBAL_Q == 12
#define _IQatan2(A,B) _IQ12atan2(A,B)
#endif
#if GLOBAL_Q == 11
#define _IQatan2(A,B) _IQ11atan2(A,B)
#endif
#if GLOBAL_Q == 10
#define _IQatan2(A,B) _IQ10atan2(A,B)
#endif
#if GLOBAL_Q == 9
#define _IQatan2(A,B) _IQ9atan2(A,B)
#endif
#if GLOBAL_Q == 8
#define _IQatan2(A,B) _IQ8atan2(A,B)
#endif
#if GLOBAL_Q == 7
#define _IQatan2(A,B) _IQ7atan2(A,B)
#endif
#if GLOBAL_Q == 6
#define _IQatan2(A,B) _IQ6atan2(A,B)
#endif
#if GLOBAL_Q == 5
#define _IQatan2(A,B) _IQ5atan2(A,B)
#endif
#if GLOBAL_Q == 4
#define _IQatan2(A,B) _IQ4atan2(A,B)
#endif
#if GLOBAL_Q == 3
#define _IQatan2(A,B) _IQ3atan2(A,B)
#endif
#if GLOBAL_Q == 2
#define _IQatan2(A,B) _IQ2atan2(A,B)
#endif
#if GLOBAL_Q == 1
#define _IQatan2(A,B) _IQ1atan2(A,B)
#endif
//---------------------------------------------------------------------------
extern long _IQ30atan2PU(long A, long B);
extern long _IQ29atan2PU(long A, long B);
extern long _IQ28atan2PU(long A, long B);
extern long _IQ27atan2PU(long A, long B);
extern long _IQ26atan2PU(long A, long B);
extern long _IQ25atan2PU(long A, long B);
extern long _IQ24atan2PU(long A, long B);
extern long _IQ23atan2PU(long A, long B);
extern long _IQ22atan2PU(long A, long B);
extern long _IQ21atan2PU(long A, long B);
extern long _IQ20atan2PU(long A, long B);
extern long _IQ19atan2PU(long A, long B);
extern long _IQ18atan2PU(long A, long B);
extern long _IQ17atan2PU(long A, long B);
extern long _IQ16atan2PU(long A, long B);
extern long _IQ15atan2PU(long A, long B);
extern long _IQ14atan2PU(long A, long B);
extern long _IQ13atan2PU(long A, long B);
extern long _IQ12atan2PU(long A, long B);
extern long _IQ11atan2PU(long A, long B);
extern long _IQ10atan2PU(long A, long B);
extern long _IQ9atan2PU(long A, long B);
extern long _IQ8atan2PU(long A, long B);
extern long _IQ7atan2PU(long A, long B);
extern long _IQ6atan2PU(long A, long B);
extern long _IQ5atan2PU(long A, long B);
extern long _IQ4atan2PU(long A, long B);
extern long _IQ3atan2PU(long A, long B);
extern long _IQ2atan2PU(long A, long B);
extern long _IQ1atan2PU(long A, long B);
#if GLOBAL_Q == 30
#define _IQatan2PU(A,B) _IQ30atan2PU(A,B)
#endif
#if GLOBAL_Q == 29
#define _IQatan2PU(A,B) _IQ29atan2PU(A,B)
#endif
#if GLOBAL_Q == 28
#define _IQatan2PU(A,B) _IQ28atan2PU(A,B)
#endif
#if GLOBAL_Q == 27
#define _IQatan2PU(A,B) _IQ27atan2PU(A,B)
#endif
#if GLOBAL_Q == 26
#define _IQatan2PU(A,B) _IQ26atan2PU(A,B)
#endif
#if GLOBAL_Q == 25
#define _IQatan2PU(A,B) _IQ25atan2PU(A,B)
#endif
#if GLOBAL_Q == 24
#define _IQatan2PU(A,B) _IQ24atan2PU(A,B)
#endif
#if GLOBAL_Q == 23
#define _IQatan2PU(A,B) _IQ23atan2PU(A,B)
#endif
#if GLOBAL_Q == 22
#define _IQatan2PU(A,B) _IQ22atan2PU(A,B)
#endif
#if GLOBAL_Q == 21
#define _IQatan2PU(A,B) _IQ21atan2PU(A,B)
#endif
#if GLOBAL_Q == 20
#define _IQatan2PU(A,B) _IQ20atan2PU(A,B)
#endif
#if GLOBAL_Q == 19
#define _IQatan2PU(A,B) _IQ19atan2PU(A,B)
#endif
#if GLOBAL_Q == 18
#define _IQatan2PU(A,B) _IQ18atan2PU(A,B)
#endif
#if GLOBAL_Q == 17
#define _IQatan2PU(A,B) _IQ17atan2PU(A,B)
#endif
#if GLOBAL_Q == 16
#define _IQatan2PU(A,B) _IQ16atan2PU(A,B)
#endif
#if GLOBAL_Q == 15
#define _IQatan2PU(A,B) _IQ15atan2PU(A,B)
#endif
#if GLOBAL_Q == 14
#define _IQatan2PU(A,B) _IQ14atan2PU(A,B)
#endif
#if GLOBAL_Q == 13
#define _IQatan2PU(A,B) _IQ13atan2PU(A,B)
#endif
#if GLOBAL_Q == 12
#define _IQatan2PU(A,B) _IQ12atan2PU(A,B)
#endif
#if GLOBAL_Q == 11
#define _IQatan2PU(A,B) _IQ11atan2PU(A,B)
#endif
#if GLOBAL_Q == 10
#define _IQatan2PU(A,B) _IQ10atan2PU(A,B)
#endif
#if GLOBAL_Q == 9
#define _IQatan2PU(A,B) _IQ9atan2PU(A,B)
#endif
#if GLOBAL_Q == 8
#define _IQatan2PU(A,B) _IQ8atan2PU(A,B)
#endif
#if GLOBAL_Q == 7
#define _IQatan2PU(A,B) _IQ7atan2PU(A,B)
#endif
#if GLOBAL_Q == 6
#define _IQatan2PU(A,B) _IQ6atan2PU(A,B)
#endif
#if GLOBAL_Q == 5
#define _IQatan2PU(A,B) _IQ5atan2PU(A,B)
#endif
#if GLOBAL_Q == 4
#define _IQatan2PU(A,B) _IQ4atan2PU(A,B)
#endif
#if GLOBAL_Q == 3
#define _IQatan2PU(A,B) _IQ3atan2PU(A,B)
#endif
#if GLOBAL_Q == 2
#define _IQatan2PU(A,B) _IQ2atan2PU(A,B)
#endif
#if GLOBAL_Q == 1
#define _IQatan2PU(A,B) _IQ1atan2PU(A,B)
#endif
//---------------------------------------------------------------------------
#define _IQ30atan(A) _IQ30atan2(A,_IQ30(1.0))
#define _IQ29atan(A) _IQ29atan2(A,_IQ29(1.0))
#define _IQ28atan(A) _IQ28atan2(A,_IQ28(1.0))
#define _IQ27atan(A) _IQ27atan2(A,_IQ27(1.0))
#define _IQ26atan(A) _IQ26atan2(A,_IQ26(1.0))
#define _IQ25atan(A) _IQ25atan2(A,_IQ25(1.0))
#define _IQ24atan(A) _IQ24atan2(A,_IQ24(1.0))
#define _IQ23atan(A) _IQ23atan2(A,_IQ23(1.0))
#define _IQ22atan(A) _IQ22atan2(A,_IQ22(1.0))
#define _IQ21atan(A) _IQ21atan2(A,_IQ21(1.0))
#define _IQ20atan(A) _IQ20atan2(A,_IQ20(1.0))
#define _IQ19atan(A) _IQ19atan2(A,_IQ19(1.0))
#define _IQ18atan(A) _IQ18atan2(A,_IQ18(1.0))
#define _IQ17atan(A) _IQ17atan2(A,_IQ17(1.0))
#define _IQ16atan(A) _IQ16atan2(A,_IQ16(1.0))
#define _IQ15atan(A) _IQ15atan2(A,_IQ15(1.0))
#define _IQ14atan(A) _IQ14atan2(A,_IQ14(1.0))
#define _IQ13atan(A) _IQ13atan2(A,_IQ13(1.0))
#define _IQ12atan(A) _IQ12atan2(A,_IQ12(1.0))
#define _IQ11atan(A) _IQ11atan2(A,_IQ11(1.0))
#define _IQ10atan(A) _IQ10atan2(A,_IQ10(1.0))
#define _IQ9atan(A) _IQ9atan2(A,_IQ9(1.0))
#define _IQ8atan(A) _IQ8atan2(A,_IQ8(1.0))
#define _IQ7atan(A) _IQ7atan2(A,_IQ7(1.0))
#define _IQ6atan(A) _IQ6atan2(A,_IQ6(1.0))
#define _IQ5atan(A) _IQ5atan2(A,_IQ5(1.0))
#define _IQ4atan(A) _IQ4atan2(A,_IQ4(1.0))
#define _IQ3atan(A) _IQ3atan2(A,_IQ3(1.0))
#define _IQ2atan(A) _IQ2atan2(A,_IQ2(1.0))
#define _IQ1atan(A) _IQ1atan2(A,_IQ1(1.0))
#if GLOBAL_Q == 30
#define _IQatan(A) _IQ30atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 29
#define _IQatan(A) _IQ29atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 28
#define _IQatan(A) _IQ28atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 27
#define _IQatan(A) _IQ27atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 26
#define _IQatan(A) _IQ26atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 25
#define _IQatan(A) _IQ25atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 24
#define _IQatan(A) _IQ24atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 23
#define _IQatan(A) _IQ23atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 22
#define _IQatan(A) _IQ22atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 21
#define _IQatan(A) _IQ21atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 20
#define _IQatan(A) _IQ20atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 19
#define _IQatan(A) _IQ19atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 18
#define _IQatan(A) _IQ18atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 17
#define _IQatan(A) _IQ17atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 16
#define _IQatan(A) _IQ16atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 15
#define _IQatan(A) _IQ15atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 14
#define _IQatan(A) _IQ14atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 13
#define _IQatan(A) _IQ13atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 12
#define _IQatan(A) _IQ12atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 11
#define _IQatan(A) _IQ11atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 10
#define _IQatan(A) _IQ10atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 9
#define _IQatan(A) _IQ9atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 8
#define _IQatan(A) _IQ8atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 7
#define _IQatan(A) _IQ7atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 6
#define _IQatan(A) _IQ6atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 5
#define _IQatan(A) _IQ5atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 4
#define _IQatan(A) _IQ4atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 3
#define _IQatan(A) _IQ3atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 2
#define _IQatan(A) _IQ2atan2(A,_IQ(1.0))
#endif
#if GLOBAL_Q == 1
#define _IQatan(A) _IQ1atan2(A,_IQ(1.0))
#endif
//---------------------------------------------------------------------------
extern long _IQ30sqrt(long A);
extern long _IQ29sqrt(long A);
extern long _IQ28sqrt(long A);
extern long _IQ27sqrt(long A);
extern long _IQ26sqrt(long A);
extern long _IQ25sqrt(long A);
extern long _IQ24sqrt(long A);
extern long _IQ23sqrt(long A);
extern long _IQ22sqrt(long A);
extern long _IQ21sqrt(long A);
extern long _IQ20sqrt(long A);
extern long _IQ19sqrt(long A);
extern long _IQ18sqrt(long A);
extern long _IQ17sqrt(long A);
extern long _IQ16sqrt(long A);
extern long _IQ15sqrt(long A);
extern long _IQ14sqrt(long A);
extern long _IQ13sqrt(long A);
extern long _IQ12sqrt(long A);
extern long _IQ11sqrt(long A);
extern long _IQ10sqrt(long A);
extern long _IQ9sqrt(long A);
extern long _IQ8sqrt(long A);
extern long _IQ7sqrt(long A);
extern long _IQ6sqrt(long A);
extern long _IQ5sqrt(long A);
extern long _IQ4sqrt(long A);
extern long _IQ3sqrt(long A);
extern long _IQ2sqrt(long A);
extern long _IQ1sqrt(long A);
#if GLOBAL_Q == 30
#define _IQsqrt(A) _IQ30sqrt(A)
#endif
#if GLOBAL_Q == 29
#define _IQsqrt(A) _IQ29sqrt(A)
#endif
#if GLOBAL_Q == 28
#define _IQsqrt(A) _IQ28sqrt(A)
#endif
#if GLOBAL_Q == 27
#define _IQsqrt(A) _IQ27sqrt(A)
#endif
#if GLOBAL_Q == 26
#define _IQsqrt(A) _IQ26sqrt(A)
#endif
#if GLOBAL_Q == 25
#define _IQsqrt(A) _IQ25sqrt(A)
#endif
#if GLOBAL_Q == 24
#define _IQsqrt(A) _IQ24sqrt(A)
#endif
#if GLOBAL_Q == 23
#define _IQsqrt(A) _IQ23sqrt(A)
#endif
#if GLOBAL_Q == 22
#define _IQsqrt(A) _IQ22sqrt(A)
#endif
#if GLOBAL_Q == 21
#define _IQsqrt(A) _IQ21sqrt(A)
#endif
#if GLOBAL_Q == 20
#define _IQsqrt(A) _IQ20sqrt(A)
#endif
#if GLOBAL_Q == 19
#define _IQsqrt(A) _IQ19sqrt(A)
#endif
#if GLOBAL_Q == 18
#define _IQsqrt(A) _IQ18sqrt(A)
#endif
#if GLOBAL_Q == 17
#define _IQsqrt(A) _IQ17sqrt(A)
#endif
#if GLOBAL_Q == 16
#define _IQsqrt(A) _IQ16sqrt(A)
#endif
#if GLOBAL_Q == 15
#define _IQsqrt(A) _IQ15sqrt(A)
#endif
#if GLOBAL_Q == 14
#define _IQsqrt(A) _IQ14sqrt(A)
#endif
#if GLOBAL_Q == 13
#define _IQsqrt(A) _IQ13sqrt(A)
#endif
#if GLOBAL_Q == 12
#define _IQsqrt(A) _IQ12sqrt(A)
#endif
#if GLOBAL_Q == 11
#define _IQsqrt(A) _IQ11sqrt(A)
#endif
#if GLOBAL_Q == 10
#define _IQsqrt(A) _IQ10sqrt(A)
#endif
#if GLOBAL_Q == 9
#define _IQsqrt(A) _IQ9sqrt(A)
#endif
#if GLOBAL_Q == 8
#define _IQsqrt(A) _IQ8sqrt(A)
#endif
#if GLOBAL_Q == 7
#define _IQsqrt(A) _IQ7sqrt(A)
#endif
#if GLOBAL_Q == 6
#define _IQsqrt(A) _IQ6sqrt(A)
#endif
#if GLOBAL_Q == 5
#define _IQsqrt(A) _IQ5sqrt(A)
#endif
#if GLOBAL_Q == 4
#define _IQsqrt(A) _IQ4sqrt(A)
#endif
#if GLOBAL_Q == 3
#define _IQsqrt(A) _IQ3sqrt(A)
#endif
#if GLOBAL_Q == 2
#define _IQsqrt(A) _IQ2sqrt(A)
#endif
#if GLOBAL_Q == 1
#define _IQsqrt(A) _IQ1sqrt(A)
#endif
//---------------------------------------------------------------------------
extern long _IQ30isqrt(long A);
extern long _IQ29isqrt(long A);
extern long _IQ28isqrt(long A);
extern long _IQ27isqrt(long A);
extern long _IQ26isqrt(long A);
extern long _IQ25isqrt(long A);
extern long _IQ24isqrt(long A);
extern long _IQ23isqrt(long A);
extern long _IQ22isqrt(long A);
extern long _IQ21isqrt(long A);
extern long _IQ20isqrt(long A);
extern long _IQ19isqrt(long A);
extern long _IQ18isqrt(long A);
extern long _IQ17isqrt(long A);
extern long _IQ16isqrt(long A);
extern long _IQ15isqrt(long A);
extern long _IQ14isqrt(long A);
extern long _IQ13isqrt(long A);
extern long _IQ12isqrt(long A);
extern long _IQ11isqrt(long A);
extern long _IQ10isqrt(long A);
extern long _IQ9isqrt(long A);
extern long _IQ8isqrt(long A);
extern long _IQ7isqrt(long A);
extern long _IQ6isqrt(long A);
extern long _IQ5isqrt(long A);
extern long _IQ4isqrt(long A);
extern long _IQ3isqrt(long A);
extern long _IQ2isqrt(long A);
extern long _IQ1isqrt(long A);
#if GLOBAL_Q == 30
#define _IQisqrt(A) _IQ30isqrt(A)
#endif
#if GLOBAL_Q == 29
#define _IQisqrt(A) _IQ29isqrt(A)
#endif
#if GLOBAL_Q == 28
#define _IQisqrt(A) _IQ28isqrt(A)
#endif
#if GLOBAL_Q == 27
#define _IQisqrt(A) _IQ27isqrt(A)
#endif
#if GLOBAL_Q == 26
#define _IQisqrt(A) _IQ26isqrt(A)
#endif
#if GLOBAL_Q == 25
#define _IQisqrt(A) _IQ25isqrt(A)
#endif
#if GLOBAL_Q == 24
#define _IQisqrt(A) _IQ24isqrt(A)
#endif
#if GLOBAL_Q == 23
#define _IQisqrt(A) _IQ23isqrt(A)
#endif
#if GLOBAL_Q == 22
#define _IQisqrt(A) _IQ22isqrt(A)
#endif
#if GLOBAL_Q == 21
#define _IQisqrt(A) _IQ21isqrt(A)
#endif
#if GLOBAL_Q == 20
#define _IQisqrt(A) _IQ20isqrt(A)
#endif
#if GLOBAL_Q == 19
#define _IQisqrt(A) _IQ19isqrt(A)
#endif
#if GLOBAL_Q == 18
#define _IQisqrt(A) _IQ18isqrt(A)
#endif
#if GLOBAL_Q == 17
#define _IQisqrt(A) _IQ17isqrt(A)
#endif
#if GLOBAL_Q == 16
#define _IQisqrt(A) _IQ16isqrt(A)
#endif
#if GLOBAL_Q == 15
#define _IQisqrt(A) _IQ15isqrt(A)
#endif
#if GLOBAL_Q == 14
#define _IQisqrt(A) _IQ14isqrt(A)
#endif
#if GLOBAL_Q == 13
#define _IQisqrt(A) _IQ13isqrt(A)
#endif
#if GLOBAL_Q == 12
#define _IQisqrt(A) _IQ12isqrt(A)
#endif
#if GLOBAL_Q == 11
#define _IQisqrt(A) _IQ11isqrt(A)
#endif
#if GLOBAL_Q == 10
#define _IQisqrt(A) _IQ10isqrt(A)
#endif
#if GLOBAL_Q == 9
#define _IQisqrt(A) _IQ9isqrt(A)
#endif
#if GLOBAL_Q == 8
#define _IQisqrt(A) _IQ8isqrt(A)
#endif
#if GLOBAL_Q == 7
#define _IQisqrt(A) _IQ7isqrt(A)
#endif
#if GLOBAL_Q == 6
#define _IQisqrt(A) _IQ6isqrt(A)
#endif
#if GLOBAL_Q == 5
#define _IQisqrt(A) _IQ5isqrt(A)
#endif
#if GLOBAL_Q == 4
#define _IQisqrt(A) _IQ4isqrt(A)
#endif
#if GLOBAL_Q == 3
#define _IQisqrt(A) _IQ3isqrt(A)
#endif
#if GLOBAL_Q == 2
#define _IQisqrt(A) _IQ2isqrt(A)
#endif
#if GLOBAL_Q == 1
#define _IQisqrt(A) _IQ1isqrt(A)
#endif
//---------------------------------------------------------------------------
extern long _IQ30exp(long A);
extern long _IQ29exp(long A);
extern long _IQ28exp(long A);
extern long _IQ27exp(long A);
extern long _IQ26exp(long A);
extern long _IQ25exp(long A);
extern long _IQ24exp(long A);
extern long _IQ23exp(long A);
extern long _IQ22exp(long A);
extern long _IQ21exp(long A);
extern long _IQ20exp(long A);
extern long _IQ19exp(long A);
extern long _IQ18exp(long A);
extern long _IQ17exp(long A);
extern long _IQ16exp(long A);
extern long _IQ15exp(long A);
extern long _IQ14exp(long A);
extern long _IQ13exp(long A);
extern long _IQ12exp(long A);
extern long _IQ11exp(long A);
extern long _IQ10exp(long A);
extern long _IQ9exp(long A);
extern long _IQ8exp(long A);
extern long _IQ7exp(long A);
extern long _IQ6exp(long A);
extern long _IQ5exp(long A);
extern long _IQ4exp(long A);
extern long _IQ3exp(long A);
extern long _IQ2exp(long A);
extern long _IQ1exp(long A);
#if GLOBAL_Q == 30
#define _IQexp(A) _IQ30exp(A)
#endif
#if GLOBAL_Q == 29
#define _IQexp(A) _IQ29exp(A)
#endif
#if GLOBAL_Q == 28
#define _IQexp(A) _IQ28exp(A)
#endif
#if GLOBAL_Q == 27
#define _IQexp(A) _IQ27exp(A)
#endif
#if GLOBAL_Q == 26
#define _IQexp(A) _IQ26exp(A)
#endif
#if GLOBAL_Q == 25
#define _IQexp(A) _IQ25exp(A)
#endif
#if GLOBAL_Q == 24
#define _IQexp(A) _IQ24exp(A)
#endif
#if GLOBAL_Q == 23
#define _IQexp(A) _IQ23exp(A)
#endif
#if GLOBAL_Q == 22
#define _IQexp(A) _IQ22exp(A)
#endif
#if GLOBAL_Q == 21
#define _IQexp(A) _IQ21exp(A)
#endif
#if GLOBAL_Q == 20
#define _IQexp(A) _IQ20exp(A)
#endif
#if GLOBAL_Q == 19
#define _IQexp(A) _IQ19exp(A)
#endif
#if GLOBAL_Q == 18
#define _IQexp(A) _IQ18exp(A)
#endif
#if GLOBAL_Q == 17
#define _IQexp(A) _IQ17exp(A)
#endif
#if GLOBAL_Q == 16
#define _IQexp(A) _IQ16exp(A)
#endif
#if GLOBAL_Q == 15
#define _IQexp(A) _IQ15exp(A)
#endif
#if GLOBAL_Q == 14
#define _IQexp(A) _IQ14exp(A)
#endif
#if GLOBAL_Q == 13
#define _IQexp(A) _IQ13exp(A)
#endif
#if GLOBAL_Q == 12
#define _IQexp(A) _IQ12exp(A)
#endif
#if GLOBAL_Q == 11
#define _IQexp(A) _IQ11exp(A)
#endif
#if GLOBAL_Q == 10
#define _IQexp(A) _IQ10exp(A)
#endif
#if GLOBAL_Q == 9
#define _IQexp(A) _IQ9exp(A)
#endif
#if GLOBAL_Q == 8
#define _IQexp(A) _IQ8exp(A)
#endif
#if GLOBAL_Q == 7
#define _IQexp(A) _IQ7exp(A)
#endif
#if GLOBAL_Q == 6
#define _IQexp(A) _IQ6exp(A)
#endif
#if GLOBAL_Q == 5
#define _IQexp(A) _IQ5exp(A)
#endif
#if GLOBAL_Q == 4
#define _IQexp(A) _IQ4exp(A)
#endif
#if GLOBAL_Q == 3
#define _IQexp(A) _IQ3exp(A)
#endif
#if GLOBAL_Q == 2
#define _IQexp(A) _IQ2exp(A)
#endif
#if GLOBAL_Q == 1
#define _IQexp(A) _IQ1exp(A)
#endif
//---------------------------------------------------------------------------
extern long _IQ30int(long A);
extern long _IQ29int(long A);
extern long _IQ28int(long A);
extern long _IQ27int(long A);
extern long _IQ26int(long A);
extern long _IQ25int(long A);
extern long _IQ24int(long A);
extern long _IQ23int(long A);
extern long _IQ22int(long A);
extern long _IQ21int(long A);
extern long _IQ20int(long A);
extern long _IQ19int(long A);
extern long _IQ18int(long A);
extern long _IQ17int(long A);
extern long _IQ16int(long A);
extern long _IQ15int(long A);
extern long _IQ14int(long A);
extern long _IQ13int(long A);
extern long _IQ12int(long A);
extern long _IQ11int(long A);
extern long _IQ10int(long A);
extern long _IQ9int(long A);
extern long _IQ8int(long A);
extern long _IQ7int(long A);
extern long _IQ6int(long A);
extern long _IQ5int(long A);
extern long _IQ4int(long A);
extern long _IQ3int(long A);
extern long _IQ2int(long A);
extern long _IQ1int(long A);
#if GLOBAL_Q == 30
#define _IQint(A) _IQ30int(A)
#endif
#if GLOBAL_Q == 29
#define _IQint(A) _IQ29int(A)
#endif
#if GLOBAL_Q == 28
#define _IQint(A) _IQ28int(A)
#endif
#if GLOBAL_Q == 27
#define _IQint(A) _IQ27int(A)
#endif
#if GLOBAL_Q == 26
#define _IQint(A) _IQ26int(A)
#endif
#if GLOBAL_Q == 25
#define _IQint(A) _IQ25int(A)
#endif
#if GLOBAL_Q == 24
#define _IQint(A) _IQ24int(A)
#endif
#if GLOBAL_Q == 23
#define _IQint(A) _IQ23int(A)
#endif
#if GLOBAL_Q == 22
#define _IQint(A) _IQ22int(A)
#endif
#if GLOBAL_Q == 21
#define _IQint(A) _IQ21int(A)
#endif
#if GLOBAL_Q == 20
#define _IQint(A) _IQ20int(A)
#endif
#if GLOBAL_Q == 19
#define _IQint(A) _IQ19int(A)
#endif
#if GLOBAL_Q == 18
#define _IQint(A) _IQ18int(A)
#endif
#if GLOBAL_Q == 17
#define _IQint(A) _IQ17int(A)
#endif
#if GLOBAL_Q == 16
#define _IQint(A) _IQ16int(A)
#endif
#if GLOBAL_Q == 15
#define _IQint(A) _IQ15int(A)
#endif
#if GLOBAL_Q == 14
#define _IQint(A) _IQ14int(A)
#endif
#if GLOBAL_Q == 13
#define _IQint(A) _IQ13int(A)
#endif
#if GLOBAL_Q == 12
#define _IQint(A) _IQ12int(A)
#endif
#if GLOBAL_Q == 11
#define _IQint(A) _IQ11int(A)
#endif
#if GLOBAL_Q == 10
#define _IQint(A) _IQ10int(A)
#endif
#if GLOBAL_Q == 9
#define _IQint(A) _IQ9int(A)
#endif
#if GLOBAL_Q == 8
#define _IQint(A) _IQ8int(A)
#endif
#if GLOBAL_Q == 7
#define _IQint(A) _IQ7int(A)
#endif
#if GLOBAL_Q == 6
#define _IQint(A) _IQ6int(A)
#endif
#if GLOBAL_Q == 5
#define _IQint(A) _IQ5int(A)
#endif
#if GLOBAL_Q == 4
#define _IQint(A) _IQ4int(A)
#endif
#if GLOBAL_Q == 3
#define _IQint(A) _IQ3int(A)
#endif
#if GLOBAL_Q == 2
#define _IQint(A) _IQ2int(A)
#endif
#if GLOBAL_Q == 1
#define _IQint(A) _IQ1int(A)
#endif
//---------------------------------------------------------------------------
extern long _IQ30frac(long A);
extern long _IQ29frac(long A);
extern long _IQ28frac(long A);
extern long _IQ27frac(long A);
extern long _IQ26frac(long A);
extern long _IQ25frac(long A);
extern long _IQ24frac(long A);
extern long _IQ23frac(long A);
extern long _IQ22frac(long A);
extern long _IQ21frac(long A);
extern long _IQ20frac(long A);
extern long _IQ19frac(long A);
extern long _IQ18frac(long A);
extern long _IQ17frac(long A);
extern long _IQ16frac(long A);
extern long _IQ15frac(long A);
extern long _IQ14frac(long A);
extern long _IQ13frac(long A);
extern long _IQ12frac(long A);
extern long _IQ11frac(long A);
extern long _IQ10frac(long A);
extern long _IQ9frac(long A);
extern long _IQ8frac(long A);
extern long _IQ7frac(long A);
extern long _IQ6frac(long A);
extern long _IQ5frac(long A);
extern long _IQ4frac(long A);
extern long _IQ3frac(long A);
extern long _IQ2frac(long A);
extern long _IQ1frac(long A);
#if GLOBAL_Q == 30
#define _IQfrac(A) _IQ30frac(A)
#endif
#if GLOBAL_Q == 29
#define _IQfrac(A) _IQ29frac(A)
#endif
#if GLOBAL_Q == 28
#define _IQfrac(A) _IQ28frac(A)
#endif
#if GLOBAL_Q == 27
#define _IQfrac(A) _IQ27frac(A)
#endif
#if GLOBAL_Q == 26
#define _IQfrac(A) _IQ26frac(A)
#endif
#if GLOBAL_Q == 25
#define _IQfrac(A) _IQ25frac(A)
#endif
#if GLOBAL_Q == 24
#define _IQfrac(A) _IQ24frac(A)
#endif
#if GLOBAL_Q == 23
#define _IQfrac(A) _IQ23frac(A)
#endif
#if GLOBAL_Q == 22
#define _IQfrac(A) _IQ22frac(A)
#endif
#if GLOBAL_Q == 21
#define _IQfrac(A) _IQ21frac(A)
#endif
#if GLOBAL_Q == 20
#define _IQfrac(A) _IQ20frac(A)
#endif
#if GLOBAL_Q == 19
#define _IQfrac(A) _IQ19frac(A)
#endif
#if GLOBAL_Q == 18
#define _IQfrac(A) _IQ18frac(A)
#endif
#if GLOBAL_Q == 17
#define _IQfrac(A) _IQ17frac(A)
#endif
#if GLOBAL_Q == 16
#define _IQfrac(A) _IQ16frac(A)
#endif
#if GLOBAL_Q == 15
#define _IQfrac(A) _IQ15frac(A)
#endif
#if GLOBAL_Q == 14
#define _IQfrac(A) _IQ14frac(A)
#endif
#if GLOBAL_Q == 13
#define _IQfrac(A) _IQ13frac(A)
#endif
#if GLOBAL_Q == 12
#define _IQfrac(A) _IQ12frac(A)
#endif
#if GLOBAL_Q == 11
#define _IQfrac(A) _IQ11frac(A)
#endif
#if GLOBAL_Q == 10
#define _IQfrac(A) _IQ10frac(A)
#endif
#if GLOBAL_Q == 9
#define _IQfrac(A) _IQ9frac(A)
#endif
#if GLOBAL_Q == 8
#define _IQfrac(A) _IQ8frac(A)
#endif
#if GLOBAL_Q == 7
#define _IQfrac(A) _IQ7frac(A)
#endif
#if GLOBAL_Q == 6
#define _IQfrac(A) _IQ6frac(A)
#endif
#if GLOBAL_Q == 5
#define _IQfrac(A) _IQ5frac(A)
#endif
#if GLOBAL_Q == 4
#define _IQfrac(A) _IQ4frac(A)
#endif
#if GLOBAL_Q == 3
#define _IQfrac(A) _IQ3frac(A)
#endif
#if GLOBAL_Q == 2
#define _IQfrac(A) _IQ2frac(A)
#endif
#if GLOBAL_Q == 1
#define _IQfrac(A) _IQ1frac(A)
#endif
//---------------------------------------------------------------------------
#define _IQmpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (GLOBAL_Q + 32 - IQA - IQB))
#define _IQ30mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (30 + 32 - IQA - IQB))
#define _IQ29mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (29 + 32 - IQA - IQB))
#define _IQ28mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (28 + 32 - IQA - IQB))
#define _IQ27mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (27 + 32 - IQA - IQB))
#define _IQ26mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (26 + 32 - IQA - IQB))
#define _IQ25mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (25 + 32 - IQA - IQB))
#define _IQ24mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (24 + 32 - IQA - IQB))
#define _IQ23mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (23 + 32 - IQA - IQB))
#define _IQ22mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (22 + 32 - IQA - IQB))
#define _IQ21mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (21 + 32 - IQA - IQB))
#define _IQ20mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (20 + 32 - IQA - IQB))
#define _IQ19mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (19 + 32 - IQA - IQB))
#define _IQ18mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (18 + 32 - IQA - IQB))
#define _IQ17mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (17 + 32 - IQA - IQB))
#define _IQ16mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (16 + 32 - IQA - IQB))
#define _IQ15mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (15 + 32 - IQA - IQB))
#define _IQ14mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (14 + 32 - IQA - IQB))
#define _IQ13mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (13 + 32 - IQA - IQB))
#define _IQ12mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (12 + 32 - IQA - IQB))
#define _IQ11mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (11 + 32 - IQA - IQB))
#define _IQ10mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (10 + 32 - IQA - IQB))
#define _IQ9mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (9 + 32 - IQA - IQB))
#define _IQ8mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (8 + 32 - IQA - IQB))
#define _IQ7mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (7 + 32 - IQA - IQB))
#define _IQ6mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (6 + 32 - IQA - IQB))
#define _IQ5mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (5 + 32 - IQA - IQB))
#define _IQ4mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (4 + 32 - IQA - IQB))
#define _IQ3mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (3 + 32 - IQA - IQB))
#define _IQ2mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (2 + 32 - IQA - IQB))
#define _IQ1mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (1 + 32 - IQA - IQB))
//---------------------------------------------------------------------------
#define _IQmpyI32(A,B) ((A)*(B))
#define _IQ30mpyI32(A,B) ((A)*(B))
#define _IQ29mpyI32(A,B) ((A)*(B))
#define _IQ28mpyI32(A,B) ((A)*(B))
#define _IQ27mpyI32(A,B) ((A)*(B))
#define _IQ26mpyI32(A,B) ((A)*(B))
#define _IQ25mpyI32(A,B) ((A)*(B))
#define _IQ24mpyI32(A,B) ((A)*(B))
#define _IQ23mpyI32(A,B) ((A)*(B))
#define _IQ22mpyI32(A,B) ((A)*(B))
#define _IQ21mpyI32(A,B) ((A)*(B))
#define _IQ20mpyI32(A,B) ((A)*(B))
#define _IQ19mpyI32(A,B) ((A)*(B))
#define _IQ18mpyI32(A,B) ((A)*(B))
#define _IQ17mpyI32(A,B) ((A)*(B))
#define _IQ16mpyI32(A,B) ((A)*(B))
#define _IQ15mpyI32(A,B) ((A)*(B))
#define _IQ14mpyI32(A,B) ((A)*(B))
#define _IQ13mpyI32(A,B) ((A)*(B))
#define _IQ12mpyI32(A,B) ((A)*(B))
#define _IQ11mpyI32(A,B) ((A)*(B))
#define _IQ10mpyI32(A,B) ((A)*(B))
#define _IQ9mpyI32(A,B) ((A)*(B))
#define _IQ8mpyI32(A,B) ((A)*(B))
#define _IQ7mpyI32(A,B) ((A)*(B))
#define _IQ6mpyI32(A,B) ((A)*(B))
#define _IQ5mpyI32(A,B) ((A)*(B))
#define _IQ4mpyI32(A,B) ((A)*(B))
#define _IQ3mpyI32(A,B) ((A)*(B))
#define _IQ2mpyI32(A,B) ((A)*(B))
#define _IQ1mpyI32(A,B) ((A)*(B))
//---------------------------------------------------------------------------
extern long _IQ30mpyI32int(long A, long B);
extern long _IQ29mpyI32int(long A, long B);
extern long _IQ28mpyI32int(long A, long B);
extern long _IQ27mpyI32int(long A, long B);
extern long _IQ26mpyI32int(long A, long B);
extern long _IQ25mpyI32int(long A, long B);
extern long _IQ24mpyI32int(long A, long B);
extern long _IQ23mpyI32int(long A, long B);
extern long _IQ22mpyI32int(long A, long B);
extern long _IQ21mpyI32int(long A, long B);
extern long _IQ20mpyI32int(long A, long B);
extern long _IQ19mpyI32int(long A, long B);
extern long _IQ18mpyI32int(long A, long B);
extern long _IQ17mpyI32int(long A, long B);
extern long _IQ16mpyI32int(long A, long B);
extern long _IQ15mpyI32int(long A, long B);
extern long _IQ14mpyI32int(long A, long B);
extern long _IQ13mpyI32int(long A, long B);
extern long _IQ12mpyI32int(long A, long B);
extern long _IQ11mpyI32int(long A, long B);
extern long _IQ10mpyI32int(long A, long B);
extern long _IQ9mpyI32int(long A, long B);
extern long _IQ8mpyI32int(long A, long B);
extern long _IQ7mpyI32int(long A, long B);
extern long _IQ6mpyI32int(long A, long B);
extern long _IQ5mpyI32int(long A, long B);
extern long _IQ4mpyI32int(long A, long B);
extern long _IQ3mpyI32int(long A, long B);
extern long _IQ2mpyI32int(long A, long B);
extern long _IQ1mpyI32int(long A, long B);
#if GLOBAL_Q == 30
#define _IQmpyI32int(A, B) _IQ30mpyI32int(A, B)
#endif
#if GLOBAL_Q == 29
#define _IQmpyI32int(A, B) _IQ29mpyI32int(A, B)
#endif
#if GLOBAL_Q == 28
#define _IQmpyI32int(A, B) _IQ28mpyI32int(A, B)
#endif
#if GLOBAL_Q == 27
#define _IQmpyI32int(A, B) _IQ27mpyI32int(A, B)
#endif
#if GLOBAL_Q == 26
#define _IQmpyI32int(A, B) _IQ26mpyI32int(A, B)
#endif
#if GLOBAL_Q == 25
#define _IQmpyI32int(A, B) _IQ25mpyI32int(A, B)
#endif
#if GLOBAL_Q == 24
#define _IQmpyI32int(A, B) _IQ24mpyI32int(A, B)
#endif
#if GLOBAL_Q == 23
#define _IQmpyI32int(A, B) _IQ23mpyI32int(A, B)
#endif
#if GLOBAL_Q == 22
#define _IQmpyI32int(A, B) _IQ22mpyI32int(A, B)
#endif
#if GLOBAL_Q == 21
#define _IQmpyI32int(A, B) _IQ21mpyI32int(A, B)
#endif
#if GLOBAL_Q == 20
#define _IQmpyI32int(A, B) _IQ20mpyI32int(A, B)
#endif
#if GLOBAL_Q == 19
#define _IQmpyI32int(A, B) _IQ19mpyI32int(A, B)
#endif
#if GLOBAL_Q == 18
#define _IQmpyI32int(A, B) _IQ18mpyI32int(A, B)
#endif
#if GLOBAL_Q == 17
#define _IQmpyI32int(A, B) _IQ17mpyI32int(A, B)
#endif
#if GLOBAL_Q == 16
#define _IQmpyI32int(A, B) _IQ16mpyI32int(A, B)
#endif
#if GLOBAL_Q == 15
#define _IQmpyI32int(A, B) _IQ15mpyI32int(A, B)
#endif
#if GLOBAL_Q == 14
#define _IQmpyI32int(A, B) _IQ14mpyI32int(A, B)
#endif
#if GLOBAL_Q == 13
#define _IQmpyI32int(A, B) _IQ13mpyI32int(A, B)
#endif
#if GLOBAL_Q == 12
#define _IQmpyI32int(A, B) _IQ12mpyI32int(A, B)
#endif
#if GLOBAL_Q == 11
#define _IQmpyI32int(A, B) _IQ11mpyI32int(A, B)
#endif
#if GLOBAL_Q == 10
#define _IQmpyI32int(A, B) _IQ10mpyI32int(A, B)
#endif
#if GLOBAL_Q == 9
#define _IQmpyI32int(A, B) _IQ9mpyI32int(A, B)
#endif
#if GLOBAL_Q == 8
#define _IQmpyI32int(A, B) _IQ8mpyI32int(A, B)
#endif
#if GLOBAL_Q == 7
#define _IQmpyI32int(A, B) _IQ7mpyI32int(A, B)
#endif
#if GLOBAL_Q == 6
#define _IQmpyI32int(A, B) _IQ6mpyI32int(A, B)
#endif
#if GLOBAL_Q == 5
#define _IQmpyI32int(A, B) _IQ5mpyI32int(A, B)
#endif
#if GLOBAL_Q == 4
#define _IQmpyI32int(A, B) _IQ4mpyI32int(A, B)
#endif
#if GLOBAL_Q == 3
#define _IQmpyI32int(A, B) _IQ3mpyI32int(A, B)
#endif
#if GLOBAL_Q == 2
#define _IQmpyI32int(A, B) _IQ2mpyI32int(A, B)
#endif
#if GLOBAL_Q == 1
#define _IQmpyI32int(A, B) _IQ1mpyI32int(A, B)
#endif
//---------------------------------------------------------------------------
extern long _IQ30mpyI32frac(long A, long B);
extern long _IQ29mpyI32frac(long A, long B);
extern long _IQ28mpyI32frac(long A, long B);
extern long _IQ27mpyI32frac(long A, long B);
extern long _IQ26mpyI32frac(long A, long B);
extern long _IQ25mpyI32frac(long A, long B);
extern long _IQ24mpyI32frac(long A, long B);
extern long _IQ23mpyI32frac(long A, long B);
extern long _IQ22mpyI32frac(long A, long B);
extern long _IQ21mpyI32frac(long A, long B);
extern long _IQ20mpyI32frac(long A, long B);
extern long _IQ19mpyI32frac(long A, long B);
extern long _IQ18mpyI32frac(long A, long B);
extern long _IQ17mpyI32frac(long A, long B);
extern long _IQ16mpyI32frac(long A, long B);
extern long _IQ15mpyI32frac(long A, long B);
extern long _IQ14mpyI32frac(long A, long B);
extern long _IQ13mpyI32frac(long A, long B);
extern long _IQ12mpyI32frac(long A, long B);
extern long _IQ11mpyI32frac(long A, long B);
extern long _IQ10mpyI32frac(long A, long B);
extern long _IQ9mpyI32frac(long A, long B);
extern long _IQ8mpyI32frac(long A, long B);
extern long _IQ7mpyI32frac(long A, long B);
extern long _IQ6mpyI32frac(long A, long B);
extern long _IQ5mpyI32frac(long A, long B);
extern long _IQ4mpyI32frac(long A, long B);
extern long _IQ3mpyI32frac(long A, long B);
extern long _IQ2mpyI32frac(long A, long B);
extern long _IQ1mpyI32frac(long A, long B);
#if GLOBAL_Q == 30
#define _IQmpyI32frac(A, B) _IQ30mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 29
#define _IQmpyI32frac(A, B) _IQ29mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 28
#define _IQmpyI32frac(A, B) _IQ28mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 27
#define _IQmpyI32frac(A, B) _IQ27mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 26
#define _IQmpyI32frac(A, B) _IQ26mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 25
#define _IQmpyI32frac(A, B) _IQ25mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 24
#define _IQmpyI32frac(A, B) _IQ24mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 23
#define _IQmpyI32frac(A, B) _IQ23mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 22
#define _IQmpyI32frac(A, B) _IQ22mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 21
#define _IQmpyI32frac(A, B) _IQ21mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 20
#define _IQmpyI32frac(A, B) _IQ20mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 19
#define _IQmpyI32frac(A, B) _IQ19mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 18
#define _IQmpyI32frac(A, B) _IQ18mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 17
#define _IQmpyI32frac(A, B) _IQ17mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 16
#define _IQmpyI32frac(A, B) _IQ16mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 15
#define _IQmpyI32frac(A, B) _IQ15mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 14
#define _IQmpyI32frac(A, B) _IQ14mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 13
#define _IQmpyI32frac(A, B) _IQ13mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 12
#define _IQmpyI32frac(A, B) _IQ12mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 11
#define _IQmpyI32frac(A, B) _IQ11mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 10
#define _IQmpyI32frac(A, B) _IQ10mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 9
#define _IQmpyI32frac(A, B) _IQ9mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 8
#define _IQmpyI32frac(A, B) _IQ8mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 7
#define _IQmpyI32frac(A, B) _IQ7mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 6
#define _IQmpyI32frac(A, B) _IQ6mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 5
#define _IQmpyI32frac(A, B) _IQ5mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 4
#define _IQmpyI32frac(A, B) _IQ4mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 3
#define _IQmpyI32frac(A, B) _IQ3mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 2
#define _IQmpyI32frac(A, B) _IQ2mpyI32frac(A, B)
#endif
#if GLOBAL_Q == 1
#define _IQmpyI32frac(A, B) _IQ1mpyI32frac(A, B)
#endif
//---------------------------------------------------------------------------
extern long _IQ30mag(long A, long B);
extern long _IQ29mag(long A, long B);
extern long _IQ28mag(long A, long B);
extern long _IQ27mag(long A, long B);
extern long _IQ26mag(long A, long B);
extern long _IQ25mag(long A, long B);
extern long _IQ24mag(long A, long B);
extern long _IQ23mag(long A, long B);
extern long _IQ22mag(long A, long B);
extern long _IQ21mag(long A, long B);
extern long _IQ20mag(long A, long B);
extern long _IQ19mag(long A, long B);
extern long _IQ18mag(long A, long B);
extern long _IQ17mag(long A, long B);
extern long _IQ16mag(long A, long B);
extern long _IQ15mag(long A, long B);
extern long _IQ14mag(long A, long B);
extern long _IQ13mag(long A, long B);
extern long _IQ12mag(long A, long B);
extern long _IQ11mag(long A, long B);
extern long _IQ10mag(long A, long B);
extern long _IQ9mag(long A, long B);
extern long _IQ8mag(long A, long B);
extern long _IQ7mag(long A, long B);
extern long _IQ6mag(long A, long B);
extern long _IQ5mag(long A, long B);
extern long _IQ4mag(long A, long B);
extern long _IQ3mag(long A, long B);
extern long _IQ2mag(long A, long B);
extern long _IQ1mag(long A, long B);
#if GLOBAL_Q == 30
#define _IQmag(A, B) _IQ30mag(A, B)
#endif
#if GLOBAL_Q == 29
#define _IQmag(A, B) _IQ29mag(A, B)
#endif
#if GLOBAL_Q == 28
#define _IQmag(A, B) _IQ28mag(A, B)
#endif
#if GLOBAL_Q == 27
#define _IQmag(A, B) _IQ27mag(A, B)
#endif
#if GLOBAL_Q == 26
#define _IQmag(A, B) _IQ26mag(A, B)
#endif
#if GLOBAL_Q == 25
#define _IQmag(A, B) _IQ25mag(A, B)
#endif
#if GLOBAL_Q == 24
#define _IQmag(A, B) _IQ24mag(A, B)
#endif
#if GLOBAL_Q == 23
#define _IQmag(A, B) _IQ23mag(A, B)
#endif
#if GLOBAL_Q == 22
#define _IQmag(A, B) _IQ22mag(A, B)
#endif
#if GLOBAL_Q == 21
#define _IQmag(A, B) _IQ21mag(A, B)
#endif
#if GLOBAL_Q == 20
#define _IQmag(A, B) _IQ20mag(A, B)
#endif
#if GLOBAL_Q == 19
#define _IQmag(A, B) _IQ19mag(A, B)
#endif
#if GLOBAL_Q == 18
#define _IQmag(A, B) _IQ18mag(A, B)
#endif
#if GLOBAL_Q == 17
#define _IQmag(A, B) _IQ17mag(A, B)
#endif
#if GLOBAL_Q == 16
#define _IQmag(A, B) _IQ16mag(A, B)
#endif
#if GLOBAL_Q == 15
#define _IQmag(A, B) _IQ15mag(A, B)
#endif
#if GLOBAL_Q == 14
#define _IQmag(A, B) _IQ14mag(A, B)
#endif
#if GLOBAL_Q == 13
#define _IQmag(A, B) _IQ13mag(A, B)
#endif
#if GLOBAL_Q == 12
#define _IQmag(A, B) _IQ12mag(A, B)
#endif
#if GLOBAL_Q == 11
#define _IQmag(A, B) _IQ11mag(A, B)
#endif
#if GLOBAL_Q == 10
#define _IQmag(A, B) _IQ10mag(A, B)
#endif
#if GLOBAL_Q == 9
#define _IQmag(A, B) _IQ9mag(A, B)
#endif
#if GLOBAL_Q == 8
#define _IQmag(A, B) _IQ8mag(A, B)
#endif
#if GLOBAL_Q == 7
#define _IQmag(A, B) _IQ7mag(A, B)
#endif
#if GLOBAL_Q == 6
#define _IQmag(A, B) _IQ6mag(A, B)
#endif
#if GLOBAL_Q == 5
#define _IQmag(A, B) _IQ5mag(A, B)
#endif
#if GLOBAL_Q == 4
#define _IQmag(A, B) _IQ4mag(A, B)
#endif
#if GLOBAL_Q == 3
#define _IQmag(A, B) _IQ3mag(A, B)
#endif
#if GLOBAL_Q == 2
#define _IQmag(A, B) _IQ2mag(A, B)
#endif
#if GLOBAL_Q == 1
#define _IQmag(A, B) _IQ1mag(A, B)
#endif
//---------------------------------------------------------------------------
extern long _atoIQN(const char *A, long q_value);
#define _atoIQ(A) _atoIQN(A, GLOBAL_Q)
#define _atoIQ30(A) _atoIQN(A, 30)
#define _atoIQ29(A) _atoIQN(A, 29)
#define _atoIQ28(A) _atoIQN(A, 28)
#define _atoIQ27(A) _atoIQN(A, 27)
#define _atoIQ26(A) _atoIQN(A, 26)
#define _atoIQ25(A) _atoIQN(A, 25)
#define _atoIQ24(A) _atoIQN(A, 24)
#define _atoIQ23(A) _atoIQN(A, 23)
#define _atoIQ22(A) _atoIQN(A, 22)
#define _atoIQ21(A) _atoIQN(A, 21)
#define _atoIQ20(A) _atoIQN(A, 20)
#define _atoIQ19(A) _atoIQN(A, 19)
#define _atoIQ18(A) _atoIQN(A, 18)
#define _atoIQ17(A) _atoIQN(A, 17)
#define _atoIQ16(A) _atoIQN(A, 16)
#define _atoIQ15(A) _atoIQN(A, 15)
#define _atoIQ14(A) _atoIQN(A, 14)
#define _atoIQ13(A) _atoIQN(A, 13)
#define _atoIQ12(A) _atoIQN(A, 12)
#define _atoIQ11(A) _atoIQN(A, 11)
#define _atoIQ10(A) _atoIQN(A, 10)
#define _atoIQ9(A) _atoIQN(A, 9)
#define _atoIQ8(A) _atoIQN(A, 8)
#define _atoIQ7(A) _atoIQN(A, 7)
#define _atoIQ6(A) _atoIQN(A, 6)
#define _atoIQ5(A) _atoIQN(A, 5)
#define _atoIQ4(A) _atoIQN(A, 4)
#define _atoIQ3(A) _atoIQN(A, 3)
#define _atoIQ2(A) _atoIQN(A, 2)
#define _atoIQ1(A) _atoIQN(A, 1)
//---------------------------------------------------------------------------
extern int __IQNtoa(char *A, const char *B, long C, int D);
extern int _IQ30toa(char *A, const char *B, long C);
extern int _IQ29toa(char *A, const char *B, long C);
extern int _IQ28toa(char *A, const char *B, long C);
extern int _IQ27toa(char *A, const char *B, long C);
extern int _IQ26toa(char *A, const char *B, long C);
extern int _IQ25toa(char *A, const char *B, long C);
extern int _IQ24toa(char *A, const char *B, long C);
extern int _IQ23toa(char *A, const char *B, long C);
extern int _IQ22toa(char *A, const char *B, long C);
extern int _IQ21toa(char *A, const char *B, long C);
extern int _IQ20toa(char *A, const char *B, long C);
extern int _IQ19toa(char *A, const char *B, long C);
extern int _IQ18toa(char *A, const char *B, long C);
extern int _IQ17toa(char *A, const char *B, long C);
extern int _IQ16toa(char *A, const char *B, long C);
extern int _IQ15toa(char *A, const char *B, long C);
extern int _IQ14toa(char *A, const char *B, long C);
extern int _IQ13toa(char *A, const char *B, long C);
extern int _IQ12toa(char *A, const char *B, long C);
extern int _IQ11toa(char *A, const char *B, long C);
extern int _IQ10toa(char *A, const char *B, long C);
extern int _IQ9toa(char *A, const char *B, long C);
extern int _IQ8toa(char *A, const char *B, long C);
extern int _IQ7toa(char *A, const char *B, long C);
extern int _IQ6toa(char *A, const char *B, long C);
extern int _IQ5toa(char *A, const char *B, long C);
extern int _IQ4toa(char *A, const char *B, long C);
extern int _IQ3toa(char *A, const char *B, long C);
extern int _IQ2toa(char *A, const char *B, long C);
extern int _IQ1toa(char *A, const char *B, long C);
#define _IQ30toa(A, B, C) __IQNtoa(A, B, C, 30);
#define _IQ29toa(A, B, C) __IQNtoa(A, B, C, 29);
#define _IQ28toa(A, B, C) __IQNtoa(A, B, C, 28);
#define _IQ27toa(A, B, C) __IQNtoa(A, B, C, 27);
#define _IQ26toa(A, B, C) __IQNtoa(A, B, C, 26);
#define _IQ25toa(A, B, C) __IQNtoa(A, B, C, 25);
#define _IQ24toa(A, B, C) __IQNtoa(A, B, C, 24);
#define _IQ23toa(A, B, C) __IQNtoa(A, B, C, 23);
#define _IQ21toa(A, B, C) __IQNtoa(A, B, C, 21);
#define _IQ22toa(A, B, C) __IQNtoa(A, B, C, 22);
#define _IQ20toa(A, B, C) __IQNtoa(A, B, C, 20);
#define _IQ19toa(A, B, C) __IQNtoa(A, B, C, 19);
#define _IQ18toa(A, B, C) __IQNtoa(A, B, C, 18);
#define _IQ17toa(A, B, C) __IQNtoa(A, B, C, 17);
#define _IQ16toa(A, B, C) __IQNtoa(A, B, C, 16);
#define _IQ15toa(A, B, C) __IQNtoa(A, B, C, 15);
#define _IQ14toa(A, B, C) __IQNtoa(A, B, C, 14);
#define _IQ13toa(A, B, C) __IQNtoa(A, B, C, 13);
#define _IQ12toa(A, B, C) __IQNtoa(A, B, C, 12);
#define _IQ11toa(A, B, C) __IQNtoa(A, B, C, 11);
#define _IQ10toa(A, B, C) __IQNtoa(A, B, C, 10);
#define _IQ9toa(A, B, C) __IQNtoa(A, B, C, 9);
#define _IQ8toa(A, B, C) __IQNtoa(A, B, C, 8);
#define _IQ7toa(A, B, C) __IQNtoa(A, B, C, 7);
#define _IQ6toa(A, B, C) __IQNtoa(A, B, C, 6);
#define _IQ5toa(A, B, C) __IQNtoa(A, B, C, 5);
#define _IQ4toa(A, B, C) __IQNtoa(A, B, C, 4);
#define _IQ3toa(A, B, C) __IQNtoa(A, B, C, 3);
#define _IQ2toa(A, B, C) __IQNtoa(A, B, C, 2);
#define _IQ1toa(A, B, C) __IQNtoa(A, B, C, 1);
#if GLOBAL_Q == 30
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 30)
#endif
#if GLOBAL_Q == 29
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 29)
#endif
#if GLOBAL_Q == 28
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 28)
#endif
#if GLOBAL_Q == 27
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 27)
#endif
#if GLOBAL_Q == 26
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 26)
#endif
#if GLOBAL_Q == 25
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 25)
#endif
#if GLOBAL_Q == 24
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 24)
#endif
#if GLOBAL_Q == 23
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 23)
#endif
#if GLOBAL_Q == 22
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 22)
#endif
#if GLOBAL_Q == 21
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 21)
#endif
#if GLOBAL_Q == 20
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 20)
#endif
#if GLOBAL_Q == 19
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 19)
#endif
#if GLOBAL_Q == 18
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 18)
#endif
#if GLOBAL_Q == 17
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 17)
#endif
#if GLOBAL_Q == 16
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 16)
#endif
#if GLOBAL_Q == 15
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 15)
#endif
#if GLOBAL_Q == 14
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 14)
#endif
#if GLOBAL_Q == 13
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 13)
#endif
#if GLOBAL_Q == 12
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 12)
#endif
#if GLOBAL_Q == 11
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 11)
#endif
#if GLOBAL_Q == 10
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 10)
#endif
#if GLOBAL_Q == 9
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 9)
#endif
#if GLOBAL_Q == 8
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 8)
#endif
#if GLOBAL_Q == 7
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 7)
#endif
#if GLOBAL_Q == 6
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 6)
#endif
#if GLOBAL_Q == 5
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 5)
#endif
#if GLOBAL_Q == 4
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 4)
#endif
#if GLOBAL_Q == 3
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 3)
#endif
#if GLOBAL_Q == 2
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 2)
#endif
#if GLOBAL_Q == 1
#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 1)
#endif
//---------------------------------------------------------------------------
#define _IQabs(A) labs(A)
#define _IQ30abs(A) labs(A)
#define _IQ29abs(A) labs(A)
#define _IQ28abs(A) labs(A)
#define _IQ27abs(A) labs(A)
#define _IQ26abs(A) labs(A)
#define _IQ25abs(A) labs(A)
#define _IQ24abs(A) labs(A)
#define _IQ23abs(A) labs(A)
#define _IQ22abs(A) labs(A)
#define _IQ21abs(A) labs(A)
#define _IQ20abs(A) labs(A)
#define _IQ19abs(A) labs(A)
#define _IQ18abs(A) labs(A)
#define _IQ17abs(A) labs(A)
#define _IQ16abs(A) labs(A)
#define _IQ15abs(A) labs(A)
#define _IQ14abs(A) labs(A)
#define _IQ13abs(A) labs(A)
#define _IQ12abs(A) labs(A)
#define _IQ11abs(A) labs(A)
#define _IQ10abs(A) labs(A)
#define _IQ9abs(A) labs(A)
#define _IQ8abs(A) labs(A)
#define _IQ7abs(A) labs(A)
#define _IQ6abs(A) labs(A)
#define _IQ5abs(A) labs(A)
#define _IQ4abs(A) labs(A)
#define _IQ3abs(A) labs(A)
#define _IQ2abs(A) labs(A)
#define _IQ1abs(A) labs(A)
//###########################################################################
#else // MATH_TYPE == FLOAT_MATH
//###########################################################################
// If FLOAT_MATH is used, the IQmath library function are replaced by
// equivalent floating point operations:
//===========================================================================
typedef float _iq;
typedef float _iq30;
typedef float _iq29;
typedef float _iq28;
typedef float _iq27;
typedef float _iq26;
typedef float _iq25;
typedef float _iq24;
typedef float _iq23;
typedef float _iq22;
typedef float _iq21;
typedef float _iq20;
typedef float _iq19;
typedef float _iq18;
typedef float _iq17;
typedef float _iq16;
typedef float _iq15;
typedef float _iq14;
typedef float _iq13;
typedef float _iq12;
typedef float _iq11;
typedef float _iq10;
typedef float _iq9;
typedef float _iq8;
typedef float _iq7;
typedef float _iq6;
typedef float _iq5;
typedef float _iq4;
typedef float _iq3;
typedef float _iq2;
typedef float _iq1;
//---------------------------------------------------------------------------
#define _IQ(A) (A)
#define _IQ30(A) (A)
#define _IQ29(A) (A)
#define _IQ28(A) (A)
#define _IQ27(A) (A)
#define _IQ26(A) (A)
#define _IQ25(A) (A)
#define _IQ24(A) (A)
#define _IQ23(A) (A)
#define _IQ22(A) (A)
#define _IQ21(A) (A)
#define _IQ20(A) (A)
#define _IQ19(A) (A)
#define _IQ18(A) (A)
#define _IQ17(A) (A)
#define _IQ16(A) (A)
#define _IQ15(A) (A)
#define _IQ14(A) (A)
#define _IQ13(A) (A)
#define _IQ12(A) (A)
#define _IQ10(A) (A)
#define _IQ9(A) (A)
#define _IQ8(A) (A)
#define _IQ7(A) (A)
#define _IQ6(A) (A)
#define _IQ5(A) (A)
#define _IQ4(A) (A)
#define _IQ3(A) (A)
#define _IQ2(A) (A)
#define _IQ1(A) (A)
//---------------------------------------------------------------------------
#define _IQtoF(A) (A)
#define _IQ30toF(A) (A)
#define _IQ29toF(A) (A)
#define _IQ28toF(A) (A)
#define _IQ27toF(A) (A)
#define _IQ26toF(A) (A)
#define _IQ25toF(A) (A)
#define _IQ24toF(A) (A)
#define _IQ23toF(A) (A)
#define _IQ22toF(A) (A)
#define _IQ21toF(A) (A)
#define _IQ20toF(A) (A)
#define _IQ19toF(A) (A)
#define _IQ18toF(A) (A)
#define _IQ17toF(A) (A)
#define _IQ16toF(A) (A)
#define _IQ15toF(A) (A)
#define _IQ14toF(A) (A)
#define _IQ13toF(A) (A)
#define _IQ12toF(A) (A)
#define _IQ11toF(A) (A)
#define _IQ10toF(A) (A)
#define _IQ9toF(A) (A)
#define _IQ8toF(A) (A)
#define _IQ7toF(A) (A)
#define _IQ6toF(A) (A)
#define _IQ5toF(A) (A)
#define _IQ4toF(A) (A)
#define _IQ3toF(A) (A)
#define _IQ2toF(A) (A)
#define _IQ1toF(A) (A)
//---------------------------------------------------------------------------
extern float _satf(float A, float Pos, float Neg);
#define _IQsat(A, Pos, Neg) _satf(A, Pos, Neg)
//---------------------------------------------------------------------------
#define _IQtoIQ30(A) (A)
#define _IQtoIQ29(A) (A)
#define _IQtoIQ28(A) (A)
#define _IQtoIQ27(A) (A)
#define _IQtoIQ26(A) (A)
#define _IQtoIQ25(A) (A)
#define _IQtoIQ24(A) (A)
#define _IQtoIQ23(A) (A)
#define _IQtoIQ22(A) (A)
#define _IQtoIQ21(A) (A)
#define _IQtoIQ20(A) (A)
#define _IQtoIQ19(A) (A)
#define _IQtoIQ18(A) (A)
#define _IQtoIQ17(A) (A)
#define _IQtoIQ16(A) (A)
#define _IQtoIQ15(A) (A)
#define _IQtoIQ14(A) (A)
#define _IQtoIQ13(A) (A)
#define _IQtoIQ12(A) (A)
#define _IQtoIQ11(A) (A)
#define _IQtoIQ10(A) (A)
#define _IQtoIQ9(A) (A)
#define _IQtoIQ8(A) (A)
#define _IQtoIQ7(A) (A)
#define _IQtoIQ6(A) (A)
#define _IQtoIQ5(A) (A)
#define _IQtoIQ4(A) (A)
#define _IQtoIQ3(A) (A)
#define _IQtoIQ2(A) (A)
#define _IQtoIQ1(A) (A)
//---------------------------------------------------------------------------
#define _IQ30toIQ(A) (A)
#define _IQ29toIQ(A) (A)
#define _IQ28toIQ(A) (A)
#define _IQ27toIQ(A) (A)
#define _IQ26toIQ(A) (A)
#define _IQ25toIQ(A) (A)
#define _IQ24toIQ(A) (A)
#define _IQ23toIQ(A) (A)
#define _IQ22toIQ(A) (A)
#define _IQ21toIQ(A) (A)
#define _IQ20toIQ(A) (A)
#define _IQ19toIQ(A) (A)
#define _IQ18toIQ(A) (A)
#define _IQ17toIQ(A) (A)
#define _IQ16toIQ(A) (A)
#define _IQ15toIQ(A) (A)
#define _IQ14toIQ(A) (A)
#define _IQ13toIQ(A) (A)
#define _IQ12toIQ(A) (A)
#define _IQ11toIQ(A) (A)
#define _IQ10toIQ(A) (A)
#define _IQ9toIQ(A) (A)
#define _IQ8toIQ(A) (A)
#define _IQ7toIQ(A) (A)
#define _IQ6toIQ(A) (A)
#define _IQ5toIQ(A) (A)
#define _IQ4toIQ(A) (A)
#define _IQ3toIQ(A) (A)
#define _IQ2toIQ(A) (A)
#define _IQ1toIQ(A) (A)
//---------------------------------------------------------------------------
#define _IQtoQ15(A) (short) ((long)((A) * 32768.0L))
#define _IQtoQ14(A) (short) ((long)((A) * 16384.0L))
#define _IQtoQ13(A) (short) ((long)((A) * 8192.0L))
#define _IQtoQ12(A) (short) ((long)((A) * 4096.0L))
#define _IQtoQ11(A) (short) ((long)((A) * 2048.0L))
#define _IQtoQ10(A) (short) ((long)((A) * 1024.0L))
#define _IQtoQ9(A) (short) ((long)((A) * 512.0L))
#define _IQtoQ8(A) (short) ((long)((A) * 256.0L))
#define _IQtoQ7(A) (short) ((long)((A) * 128.0L))
#define _IQtoQ6(A) (short) ((long)((A) * 64.0L))
#define _IQtoQ5(A) (short) ((long)((A) * 32.0L))
#define _IQtoQ4(A) (short) ((long)((A) * 16.0L))
#define _IQtoQ3(A) (short) ((long)((A) * 8.0L))
#define _IQtoQ2(A) (short) ((long)((A) * 4.0L))
#define _IQtoQ1(A) (short) ((long)((A) * 2.0L))
//---------------------------------------------------------------------------
#define _Q15toIQ(A) (((float) (A)) * 0.000030518)
#define _Q14toIQ(A) (((float) (A)) * 0.000061035)
#define _Q13toIQ(A) (((float) (A)) * 0.000122070)
#define _Q12toIQ(A) (((float) (A)) * 0.000244141)
#define _Q11toIQ(A) (((float) (A)) * 0.000488281)
#define _Q10toIQ(A) (((float) (A)) * 0.000976563)
#define _Q9toIQ(A) (((float) (A)) * 0.001953125)
#define _Q8toIQ(A) (((float) (A)) * 0.003906250)
#define _Q7toIQ(A) (((float) (A)) * 0.007812500)
#define _Q6toIQ(A) (((float) (A)) * 0.015625000)
#define _Q5toIQ(A) (((float) (A)) * 0.031250000)
#define _Q4toIQ(A) (((float) (A)) * 0.062500000)
#define _Q3toIQ(A) (((float) (A)) * 0.125000000)
#define _Q2toIQ(A) (((float) (A)) * 0.250000000)
#define _Q1toIQ(A) (((float) (A)) * 0.500000000)
//---------------------------------------------------------------------------
#define _IQmpy(A,B) ((A) * (B))
#define _IQ30mpy(A,B) ((A) * (B))
#define _IQ29mpy(A,B) ((A) * (B))
#define _IQ28mpy(A,B) ((A) * (B))
#define _IQ27mpy(A,B) ((A) * (B))
#define _IQ26mpy(A,B) ((A) * (B))
#define _IQ25mpy(A,B) ((A) * (B))
#define _IQ24mpy(A,B) ((A) * (B))
#define _IQ23mpy(A,B) ((A) * (B))
#define _IQ22mpy(A,B) ((A) * (B))
#define _IQ21mpy(A,B) ((A) * (B))
#define _IQ20mpy(A,B) ((A) * (B))
#define _IQ19mpy(A,B) ((A) * (B))
#define _IQ18mpy(A,B) ((A) * (B))
#define _IQ17mpy(A,B) ((A) * (B))
#define _IQ16mpy(A,B) ((A) * (B))
#define _IQ15mpy(A,B) ((A) * (B))
#define _IQ14mpy(A,B) ((A) * (B))
#define _IQ13mpy(A,B) ((A) * (B))
#define _IQ12mpy(A,B) ((A) * (B))
#define _IQ11mpy(A,B) ((A) * (B))
#define _IQ10mpy(A,B) ((A) * (B))
#define _IQ9mpy(A,B) ((A) * (B))
#define _IQ8mpy(A,B) ((A) * (B))
#define _IQ7mpy(A,B) ((A) * (B))
#define _IQ6mpy(A,B) ((A) * (B))
#define _IQ5mpy(A,B) ((A) * (B))
#define _IQ4mpy(A,B) ((A) * (B))
#define _IQ3mpy(A,B) ((A) * (B))
#define _IQ2mpy(A,B) ((A) * (B))
#define _IQ1mpy(A,B) ((A) * (B))
//---------------------------------------------------------------------------
#define _IQrmpy(A,B) ((A) * (B))
#define _IQ30rmpy(A,B) ((A) * (B))
#define _IQ29rmpy(A,B) ((A) * (B))
#define _IQ28rmpy(A,B) ((A) * (B))
#define _IQ27rmpy(A,B) ((A) * (B))
#define _IQ26rmpy(A,B) ((A) * (B))
#define _IQ25rmpy(A,B) ((A) * (B))
#define _IQ24rmpy(A,B) ((A) * (B))
#define _IQ23rmpy(A,B) ((A) * (B))
#define _IQ22rmpy(A,B) ((A) * (B))
#define _IQ21rmpy(A,B) ((A) * (B))
#define _IQ20rmpy(A,B) ((A) * (B))
#define _IQ19rmpy(A,B) ((A) * (B))
#define _IQ18rmpy(A,B) ((A) * (B))
#define _IQ17rmpy(A,B) ((A) * (B))
#define _IQ16rmpy(A,B) ((A) * (B))
#define _IQ15rmpy(A,B) ((A) * (B))
#define _IQ14rmpy(A,B) ((A) * (B))
#define _IQ13rmpy(A,B) ((A) * (B))
#define _IQ12rmpy(A,B) ((A) * (B))
#define _IQ11rmpy(A,B) ((A) * (B))
#define _IQ10rmpy(A,B) ((A) * (B))
#define _IQ9rmpy(A,B) ((A) * (B))
#define _IQ8rmpy(A,B) ((A) * (B))
#define _IQ7rmpy(A,B) ((A) * (B))
#define _IQ6rmpy(A,B) ((A) * (B))
#define _IQ5rmpy(A,B) ((A) * (B))
#define _IQ4rmpy(A,B) ((A) * (B))
#define _IQ3rmpy(A,B) ((A) * (B))
#define _IQ2rmpy(A,B) ((A) * (B))
#define _IQ1rmpy(A,B) ((A) * (B))
//---------------------------------------------------------------------------
#define _IQrsmpy(A,B) ((A) * (B))
#define _IQ30rsmpy(A,B) ((A) * (B))
#define _IQ29rsmpy(A,B) ((A) * (B))
#define _IQ28rsmpy(A,B) ((A) * (B))
#define _IQ27rsmpy(A,B) ((A) * (B))
#define _IQ26rsmpy(A,B) ((A) * (B))
#define _IQ25rsmpy(A,B) ((A) * (B))
#define _IQ24rsmpy(A,B) ((A) * (B))
#define _IQ23rsmpy(A,B) ((A) * (B))
#define _IQ22rsmpy(A,B) ((A) * (B))
#define _IQ21rsmpy(A,B) ((A) * (B))
#define _IQ20rsmpy(A,B) ((A) * (B))
#define _IQ19rsmpy(A,B) ((A) * (B))
#define _IQ18rsmpy(A,B) ((A) * (B))
#define _IQ17rsmpy(A,B) ((A) * (B))
#define _IQ16rsmpy(A,B) ((A) * (B))
#define _IQ15rsmpy(A,B) ((A) * (B))
#define _IQ14rsmpy(A,B) ((A) * (B))
#define _IQ13rsmpy(A,B) ((A) * (B))
#define _IQ12rsmpy(A,B) ((A) * (B))
#define _IQ11rsmpy(A,B) ((A) * (B))
#define _IQ10rsmpy(A,B) ((A) * (B))
#define _IQ9rsmpy(A,B) ((A) * (B))
#define _IQ8rsmpy(A,B) ((A) * (B))
#define _IQ7rsmpy(A,B) ((A) * (B))
#define _IQ6rsmpy(A,B) ((A) * (B))
#define _IQ5rsmpy(A,B) ((A) * (B))
#define _IQ4rsmpy(A,B) ((A) * (B))
#define _IQ3rsmpy(A,B) ((A) * (B))
#define _IQ2rsmpy(A,B) ((A) * (B))
#define _IQ1rsmpy(A,B) ((A) * (B))
//---------------------------------------------------------------------------
#define _IQdiv(A,B) ((A) / (B))
#define _IQ30div(A,B) ((A) / (B))
#define _IQ29div(A,B) ((A) / (B))
#define _IQ28div(A,B) ((A) / (B))
#define _IQ27div(A,B) ((A) / (B))
#define _IQ26div(A,B) ((A) / (B))
#define _IQ25div(A,B) ((A) / (B))
#define _IQ24div(A,B) ((A) / (B))
#define _IQ23div(A,B) ((A) / (B))
#define _IQ22div(A,B) ((A) / (B))
#define _IQ21div(A,B) ((A) / (B))
#define _IQ20div(A,B) ((A) / (B))
#define _IQ19div(A,B) ((A) / (B))
#define _IQ18div(A,B) ((A) / (B))
#define _IQ17div(A,B) ((A) / (B))
#define _IQ16div(A,B) ((A) / (B))
#define _IQ15div(A,B) ((A) / (B))
#define _IQ14div(A,B) ((A) / (B))
#define _IQ13div(A,B) ((A) / (B))
#define _IQ12div(A,B) ((A) / (B))
#define _IQ11div(A,B) ((A) / (B))
#define _IQ10div(A,B) ((A) / (B))
#define _IQ9div(A,B) ((A) / (B))
#define _IQ8div(A,B) ((A) / (B))
#define _IQ7div(A,B) ((A) / (B))
#define _IQ6div(A,B) ((A) / (B))
#define _IQ5div(A,B) ((A) / (B))
#define _IQ4div(A,B) ((A) / (B))
#define _IQ3div(A,B) ((A) / (B))
#define _IQ2div(A,B) ((A) / (B))
#define _IQ1div(A,B) ((A) / (B))
//---------------------------------------------------------------------------
#define _IQsin(A) sin(A)
#define _IQ30sin(A) sin(A)
#define _IQ29sin(A) sin(A)
#define _IQ28sin(A) sin(A)
#define _IQ27sin(A) sin(A)
#define _IQ26sin(A) sin(A)
#define _IQ25sin(A) sin(A)
#define _IQ24sin(A) sin(A)
#define _IQ23sin(A) sin(A)
#define _IQ22sin(A) sin(A)
#define _IQ21sin(A) sin(A)
#define _IQ20sin(A) sin(A)
#define _IQ19sin(A) sin(A)
#define _IQ18sin(A) sin(A)
#define _IQ17sin(A) sin(A)
#define _IQ16sin(A) sin(A)
#define _IQ15sin(A) sin(A)
#define _IQ14sin(A) sin(A)
#define _IQ13sin(A) sin(A)
#define _IQ12sin(A) sin(A)
#define _IQ11sin(A) sin(A)
#define _IQ10sin(A) sin(A)
#define _IQ9sin(A) sin(A)
#define _IQ8sin(A) sin(A)
#define _IQ7sin(A) sin(A)
#define _IQ6sin(A) sin(A)
#define _IQ5sin(A) sin(A)
#define _IQ4sin(A) sin(A)
#define _IQ3sin(A) sin(A)
#define _IQ2sin(A) sin(A)
#define _IQ1sin(A) sin(A)
//---------------------------------------------------------------------------
#define _IQsinPU(A) sin((A)*6.283185307)
#define _IQ30sinPU(A) sin((A)*6.283185307)
#define _IQ29sinPU(A) sin((A)*6.283185307)
#define _IQ28sinPU(A) sin((A)*6.283185307)
#define _IQ27sinPU(A) sin((A)*6.283185307)
#define _IQ26sinPU(A) sin((A)*6.283185307)
#define _IQ25sinPU(A) sin((A)*6.283185307)
#define _IQ24sinPU(A) sin((A)*6.283185307)
#define _IQ23sinPU(A) sin((A)*6.283185307)
#define _IQ22sinPU(A) sin((A)*6.283185307)
#define _IQ21sinPU(A) sin((A)*6.283185307)
#define _IQ20sinPU(A) sin((A)*6.283185307)
#define _IQ19sinPU(A) sin((A)*6.283185307)
#define _IQ18sinPU(A) sin((A)*6.283185307)
#define _IQ17sinPU(A) sin((A)*6.283185307)
#define _IQ16sinPU(A) sin((A)*6.283185307)
#define _IQ15sinPU(A) sin((A)*6.283185307)
#define _IQ14sinPU(A) sin((A)*6.283185307)
#define _IQ13sinPU(A) sin((A)*6.283185307)
#define _IQ12sinPU(A) sin((A)*6.283185307)
#define _IQ11sinPU(A) sin((A)*6.283185307)
#define _IQ10sinPU(A) sin((A)*6.283185307)
#define _IQ9sinPU(A) sin((A)*6.283185307)
#define _IQ8sinPU(A) sin((A)*6.283185307)
#define _IQ7sinPU(A) sin((A)*6.283185307)
#define _IQ6sinPU(A) sin((A)*6.283185307)
#define _IQ5sinPU(A) sin((A)*6.283185307)
#define _IQ4sinPU(A) sin((A)*6.283185307)
#define _IQ3sinPU(A) sin((A)*6.283185307)
#define _IQ2sinPU(A) sin((A)*6.283185307)
#define _IQ1sinPU(A) sin((A)*6.283185307)
//---------------------------------------------------------------------------
#define _IQasin(A) asin(A)
#define _IQ29asin(A) asin(A)
#define _IQ28asin(A) asin(A)
#define _IQ27asin(A) asin(A)
#define _IQ26asin(A) asin(A)
#define _IQ25asin(A) asin(A)
#define _IQ24asin(A) asin(A)
#define _IQ23asin(A) asin(A)
#define _IQ22asin(A) asin(A)
#define _IQ21asin(A) asin(A)
#define _IQ20asin(A) asin(A)
#define _IQ19asin(A) asin(A)
#define _IQ18asin(A) asin(A)
#define _IQ17asin(A) asin(A)
#define _IQ16asin(A) asin(A)
#define _IQ15asin(A) asin(A)
#define _IQ14asin(A) asin(A)
#define _IQ13asin(A) asin(A)
#define _IQ12asin(A) asin(A)
#define _IQ11asin(A) asin(A)
#define _IQ10asin(A) asin(A)
#define _IQ9asin(A) asin(A)
#define _IQ8asin(A) asin(A)
#define _IQ7asin(A) asin(A)
#define _IQ6asin(A) asin(A)
#define _IQ5asin(A) asin(A)
#define _IQ4asin(A) asin(A)
#define _IQ3asin(A) asin(A)
#define _IQ2asin(A) asin(A)
#define _IQ1asin(A) asin(A)
//---------------------------------------------------------------------------
#define _IQcos(A) cos(A)
#define _IQ30cos(A) cos(A)
#define _IQ29cos(A) cos(A)
#define _IQ28cos(A) cos(A)
#define _IQ27cos(A) cos(A)
#define _IQ26cos(A) cos(A)
#define _IQ25cos(A) cos(A)
#define _IQ24cos(A) cos(A)
#define _IQ23cos(A) cos(A)
#define _IQ22cos(A) cos(A)
#define _IQ21cos(A) cos(A)
#define _IQ20cos(A) cos(A)
#define _IQ19cos(A) cos(A)
#define _IQ18cos(A) cos(A)
#define _IQ17cos(A) cos(A)
#define _IQ16cos(A) cos(A)
#define _IQ15cos(A) cos(A)
#define _IQ14cos(A) cos(A)
#define _IQ13cos(A) cos(A)
#define _IQ12cos(A) cos(A)
#define _IQ11cos(A) cos(A)
#define _IQ10cos(A) cos(A)
#define _IQ9cos(A) cos(A)
#define _IQ8cos(A) cos(A)
#define _IQ7cos(A) cos(A)
#define _IQ6cos(A) cos(A)
#define _IQ5cos(A) cos(A)
#define _IQ4cos(A) cos(A)
#define _IQ3cos(A) cos(A)
#define _IQ2cos(A) cos(A)
#define _IQ1cos(A) cos(A)
//---------------------------------------------------------------------------
#define _IQcosPU(A) cos((A)*6.283185307)
#define _IQ30cosPU(A) cos((A)*6.283185307)
#define _IQ29cosPU(A) cos((A)*6.283185307)
#define _IQ28cosPU(A) cos((A)*6.283185307)
#define _IQ27cosPU(A) cos((A)*6.283185307)
#define _IQ26cosPU(A) cos((A)*6.283185307)
#define _IQ25cosPU(A) cos((A)*6.283185307)
#define _IQ24cosPU(A) cos((A)*6.283185307)
#define _IQ23cosPU(A) cos((A)*6.283185307)
#define _IQ22cosPU(A) cos((A)*6.283185307)
#define _IQ21cosPU(A) cos((A)*6.283185307)
#define _IQ20cosPU(A) cos((A)*6.283185307)
#define _IQ19cosPU(A) cos((A)*6.283185307)
#define _IQ18cosPU(A) cos((A)*6.283185307)
#define _IQ17cosPU(A) cos((A)*6.283185307)
#define _IQ16cosPU(A) cos((A)*6.283185307)
#define _IQ15cosPU(A) cos((A)*6.283185307)
#define _IQ14cosPU(A) cos((A)*6.283185307)
#define _IQ13cosPU(A) cos((A)*6.283185307)
#define _IQ12cosPU(A) cos((A)*6.283185307)
#define _IQ11cosPU(A) cos((A)*6.283185307)
#define _IQ10cosPU(A) cos((A)*6.283185307)
#define _IQ9cosPU(A) cos((A)*6.283185307)
#define _IQ8cosPU(A) cos((A)*6.283185307)
#define _IQ7cosPU(A) cos((A)*6.283185307)
#define _IQ6cosPU(A) cos((A)*6.283185307)
#define _IQ5cosPU(A) cos((A)*6.283185307)
#define _IQ4cosPU(A) cos((A)*6.283185307)
#define _IQ3cosPU(A) cos((A)*6.283185307)
#define _IQ2cosPU(A) cos((A)*6.283185307)
#define _IQ1cosPU(A) cos((A)*6.283185307)
//---------------------------------------------------------------------------
#define _IQacos(A) acos(A)
#define _IQ29acos(A) acos(A)
#define _IQ28acos(A) acos(A)
#define _IQ27acos(A) acos(A)
#define _IQ26acos(A) acos(A)
#define _IQ25acos(A) acos(A)
#define _IQ24acos(A) acos(A)
#define _IQ23acos(A) acos(A)
#define _IQ22acos(A) acos(A)
#define _IQ21acos(A) acos(A)
#define _IQ20acos(A) acos(A)
#define _IQ19acos(A) acos(A)
#define _IQ18acos(A) acos(A)
#define _IQ17acos(A) acos(A)
#define _IQ16acos(A) acos(A)
#define _IQ15acos(A) acos(A)
#define _IQ14acos(A) acos(A)
#define _IQ13acos(A) acos(A)
#define _IQ12acos(A) acos(A)
#define _IQ11acos(A) acos(A)
#define _IQ10acos(A) acos(A)
#define _IQ9acos(A) acos(A)
#define _IQ8acos(A) acos(A)
#define _IQ7acos(A) acos(A)
#define _IQ6acos(A) acos(A)
#define _IQ5acos(A) acos(A)
#define _IQ4acos(A) acos(A)
#define _IQ3acos(A) acos(A)
#define _IQ2acos(A) acos(A)
#define _IQ1acos(A) acos(A)
//---------------------------------------------------------------------------
#define _IQatan(A) atan(A)
#define _IQ30atan(A) atan(A)
#define _IQ29atan(A) atan(A)
#define _IQ28atan(A) atan(A)
#define _IQ27atan(A) atan(A)
#define _IQ26atan(A) atan(A)
#define _IQ25atan(A) atan(A)
#define _IQ24atan(A) atan(A)
#define _IQ23atan(A) atan(A)
#define _IQ22atan(A) atan(A)
#define _IQ21atan(A) atan(A)
#define _IQ20atan(A) atan(A)
#define _IQ19atan(A) atan(A)
#define _IQ18atan(A) atan(A)
#define _IQ17atan(A) atan(A)
#define _IQ16atan(A) atan(A)
#define _IQ15atan(A) atan(A)
#define _IQ14atan(A) atan(A)
#define _IQ13atan(A) atan(A)
#define _IQ12atan(A) atan(A)
#define _IQ11atan(A) atan(A)
#define _IQ10atan(A) atan(A)
#define _IQ9atan(A) atan(A)
#define _IQ8atan(A) atan(A)
#define _IQ7atan(A) atan(A)
#define _IQ6atan(A) atan(A)
#define _IQ5atan(A) atan(A)
#define _IQ4atan(A) atan(A)
#define _IQ3atan(A) atan(A)
#define _IQ2atan(A) atan(A)
#define _IQ1atan(A) atan(A)
//---------------------------------------------------------------------------
#define _IQatan2(A,B) atan2(A,B)
#define _IQ30atan2(A,B) atan2(A,B)
#define _IQ29atan2(A,B) atan2(A,B)
#define _IQ28atan2(A,B) atan2(A,B)
#define _IQ27atan2(A,B) atan2(A,B)
#define _IQ26atan2(A,B) atan2(A,B)
#define _IQ25atan2(A,B) atan2(A,B)
#define _IQ24atan2(A,B) atan2(A,B)
#define _IQ23atan2(A,B) atan2(A,B)
#define _IQ22atan2(A,B) atan2(A,B)
#define _IQ21atan2(A,B) atan2(A,B)
#define _IQ20atan2(A,B) atan2(A,B)
#define _IQ19atan2(A,B) atan2(A,B)
#define _IQ18atan2(A,B) atan2(A,B)
#define _IQ17atan2(A,B) atan2(A,B)
#define _IQ16atan2(A,B) atan2(A,B)
#define _IQ15atan2(A,B) atan2(A,B)
#define _IQ14atan2(A,B) atan2(A,B)
#define _IQ13atan2(A,B) atan2(A,B)
#define _IQ12atan2(A,B) atan2(A,B)
#define _IQ11atan2(A,B) atan2(A,B)
#define _IQ10atan2(A,B) atan2(A,B)
#define _IQ9atan2(A,B) atan2(A,B)
#define _IQ8atan2(A,B) atan2(A,B)
#define _IQ7atan2(A,B) atan2(A,B)
#define _IQ6atan2(A,B) atan2(A,B)
#define _IQ5atan2(A,B) atan2(A,B)
#define _IQ4atan2(A,B) atan2(A,B)
#define _IQ3atan2(A,B) atan2(A,B)
#define _IQ2atan2(A,B) atan2(A,B)
#define _IQ1atan2(A,B) atan2(A,B)
//---------------------------------------------------------------------------
#define _IQatan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ30atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ29atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ28atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ27atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ26atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ25atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ24atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ23atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ22atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ21atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ20atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ19atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ18atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ17atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ16atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ15atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ14atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ13atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ12atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ11atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ10atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ9atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ8atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ7atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ6atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ5atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ4atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ3atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ2atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
#define _IQ1atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307)))
//---------------------------------------------------------------------------
#define _IQsqrt(A) sqrt(A)
#define _IQ30sqrt(A) sqrt(A)
#define _IQ29sqrt(A) sqrt(A)
#define _IQ28sqrt(A) sqrt(A)
#define _IQ27sqrt(A) sqrt(A)
#define _IQ26sqrt(A) sqrt(A)
#define _IQ25sqrt(A) sqrt(A)
#define _IQ24sqrt(A) sqrt(A)
#define _IQ23sqrt(A) sqrt(A)
#define _IQ22sqrt(A) sqrt(A)
#define _IQ21sqrt(A) sqrt(A)
#define _IQ20sqrt(A) sqrt(A)
#define _IQ19sqrt(A) sqrt(A)
#define _IQ18sqrt(A) sqrt(A)
#define _IQ17sqrt(A) sqrt(A)
#define _IQ16sqrt(A) sqrt(A)
#define _IQ15sqrt(A) sqrt(A)
#define _IQ14sqrt(A) sqrt(A)
#define _IQ13sqrt(A) sqrt(A)
#define _IQ12sqrt(A) sqrt(A)
#define _IQ11sqrt(A) sqrt(A)
#define _IQ10sqrt(A) sqrt(A)
#define _IQ9sqrt(A) sqrt(A)
#define _IQ8sqrt(A) sqrt(A)
#define _IQ7sqrt(A) sqrt(A)
#define _IQ6sqrt(A) sqrt(A)
#define _IQ5sqrt(A) sqrt(A)
#define _IQ4sqrt(A) sqrt(A)
#define _IQ3sqrt(A) sqrt(A)
#define _IQ2sqrt(A) sqrt(A)
#define _IQ1sqrt(A) sqrt(A)
//---------------------------------------------------------------------------
#define _IQisqrt(A) (1.0/sqrt(A))
#define _IQ30isqrt(A) (1.0/sqrt(A))
#define _IQ29isqrt(A) (1.0/sqrt(A))
#define _IQ28isqrt(A) (1.0/sqrt(A))
#define _IQ27isqrt(A) (1.0/sqrt(A))
#define _IQ26isqrt(A) (1.0/sqrt(A))
#define _IQ25isqrt(A) (1.0/sqrt(A))
#define _IQ24isqrt(A) (1.0/sqrt(A))
#define _IQ23isqrt(A) (1.0/sqrt(A))
#define _IQ22isqrt(A) (1.0/sqrt(A))
#define _IQ21isqrt(A) (1.0/sqrt(A))
#define _IQ20isqrt(A) (1.0/sqrt(A))
#define _IQ19isqrt(A) (1.0/sqrt(A))
#define _IQ18isqrt(A) (1.0/sqrt(A))
#define _IQ17isqrt(A) (1.0/sqrt(A))
#define _IQ16isqrt(A) (1.0/sqrt(A))
#define _IQ15isqrt(A) (1.0/sqrt(A))
#define _IQ14isqrt(A) (1.0/sqrt(A))
#define _IQ13isqrt(A) (1.0/sqrt(A))
#define _IQ12isqrt(A) (1.0/sqrt(A))
#define _IQ11isqrt(A) (1.0/sqrt(A))
#define _IQ10isqrt(A) (1.0/sqrt(A))
#define _IQ9isqrt(A) (1.0/sqrt(A))
#define _IQ8isqrt(A) (1.0/sqrt(A))
#define _IQ7isqrt(A) (1.0/sqrt(A))
#define _IQ6isqrt(A) (1.0/sqrt(A))
#define _IQ5isqrt(A) (1.0/sqrt(A))
#define _IQ4isqrt(A) (1.0/sqrt(A))
#define _IQ3isqrt(A) (1.0/sqrt(A))
#define _IQ2isqrt(A) (1.0/sqrt(A))
#define _IQ1isqrt(A) (1.0/sqrt(A))
//---------------------------------------------------------------------------
#define _IQexp(A) exp(A)
#define _IQ30exp(A) exp(A)
#define _IQ29exp(A) exp(A)
#define _IQ28exp(A) exp(A)
#define _IQ27exp(A) exp(A)
#define _IQ26exp(A) exp(A)
#define _IQ25exp(A) exp(A)
#define _IQ24exp(A) exp(A)
#define _IQ23exp(A) exp(A)
#define _IQ22exp(A) exp(A)
#define _IQ21exp(A) exp(A)
#define _IQ20exp(A) exp(A)
#define _IQ19exp(A) exp(A)
#define _IQ18exp(A) exp(A)
#define _IQ17exp(A) exp(A)
#define _IQ16exp(A) exp(A)
#define _IQ15exp(A) exp(A)
#define _IQ14exp(A) exp(A)
#define _IQ13exp(A) exp(A)
#define _IQ12exp(A) exp(A)
#define _IQ11exp(A) exp(A)
#define _IQ10exp(A) exp(A)
#define _IQ9exp(A) exp(A)
#define _IQ8exp(A) exp(A)
#define _IQ7exp(A) exp(A)
#define _IQ6exp(A) exp(A)
#define _IQ5exp(A) exp(A)
#define _IQ4exp(A) exp(A)
#define _IQ3exp(A) exp(A)
#define _IQ2exp(A) exp(A)
#define _IQ1exp(A) exp(A)
//---------------------------------------------------------------------------
#define _IQint(A) ((long) (A))
#define _IQ30int(A) ((long) (A))
#define _IQ29int(A) ((long) (A))
#define _IQ28int(A) ((long) (A))
#define _IQ27int(A) ((long) (A))
#define _IQ26int(A) ((long) (A))
#define _IQ25int(A) ((long) (A))
#define _IQ24int(A) ((long) (A))
#define _IQ23int(A) ((long) (A))
#define _IQ22int(A) ((long) (A))
#define _IQ21int(A) ((long) (A))
#define _IQ20int(A) ((long) (A))
#define _IQ19int(A) ((long) (A))
#define _IQ18int(A) ((long) (A))
#define _IQ17int(A) ((long) (A))
#define _IQ16int(A) ((long) (A))
#define _IQ15int(A) ((long) (A))
#define _IQ14int(A) ((long) (A))
#define _IQ13int(A) ((long) (A))
#define _IQ12int(A) ((long) (A))
#define _IQ11int(A) ((long) (A))
#define _IQ10int(A) ((long) (A))
#define _IQ9int(A) ((long) (A))
#define _IQ8int(A) ((long) (A))
#define _IQ7int(A) ((long) (A))
#define _IQ6int(A) ((long) (A))
#define _IQ5int(A) ((long) (A))
#define _IQ4int(A) ((long) (A))
#define _IQ3int(A) ((long) (A))
#define _IQ2int(A) ((long) (A))
#define _IQ1int(A) ((long) (A))
//---------------------------------------------------------------------------
#define _IQfrac(A) ((A) - (float)((long) (A)))
#define _IQ30frac(A) ((A) - (float)((long) (A)))
#define _IQ29frac(A) ((A) - (float)((long) (A)))
#define _IQ28frac(A) ((A) - (float)((long) (A)))
#define _IQ27frac(A) ((A) - (float)((long) (A)))
#define _IQ26frac(A) ((A) - (float)((long) (A)))
#define _IQ25frac(A) ((A) - (float)((long) (A)))
#define _IQ24frac(A) ((A) - (float)((long) (A)))
#define _IQ23frac(A) ((A) - (float)((long) (A)))
#define _IQ22frac(A) ((A) - (float)((long) (A)))
#define _IQ21frac(A) ((A) - (float)((long) (A)))
#define _IQ20frac(A) ((A) - (float)((long) (A)))
#define _IQ19frac(A) ((A) - (float)((long) (A)))
#define _IQ18frac(A) ((A) - (float)((long) (A)))
#define _IQ17frac(A) ((A) - (float)((long) (A)))
#define _IQ16frac(A) ((A) - (float)((long) (A)))
#define _IQ15frac(A) ((A) - (float)((long) (A)))
#define _IQ14frac(A) ((A) - (float)((long) (A)))
#define _IQ13frac(A) ((A) - (float)((long) (A)))
#define _IQ12frac(A) ((A) - (float)((long) (A)))
#define _IQ11frac(A) ((A) - (float)((long) (A)))
#define _IQ10frac(A) ((A) - (float)((long) (A)))
#define _IQ9frac(A) ((A) - (float)((long) (A)))
#define _IQ8frac(A) ((A) - (float)((long) (A)))
#define _IQ7frac(A) ((A) - (float)((long) (A)))
#define _IQ6frac(A) ((A) - (float)((long) (A)))
#define _IQ5frac(A) ((A) - (float)((long) (A)))
#define _IQ4frac(A) ((A) - (float)((long) (A)))
#define _IQ3frac(A) ((A) - (float)((long) (A)))
#define _IQ2frac(A) ((A) - (float)((long) (A)))
#define _IQ1frac(A) ((A) - (float)((long) (A)))
//---------------------------------------------------------------------------
#define _IQmpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ30mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ29mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ28mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ27mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ26mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ25mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ24mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ23mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ22mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ21mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ20mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ19mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ18mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ17mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ16mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ15mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ14mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ13mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ12mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ11mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ10mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ9mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ8mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ7mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ6mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ5mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ4mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ3mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ2mpyIQX(A, IQA, B, IQB) ((A)*(B))
#define _IQ1mpyIQX(A, IQA, B, IQB) ((A)*(B))
//---------------------------------------------------------------------------
#define _IQmpyI32(A,B) ((A) * (float) (B))
#define _IQ30mpyI32(A,B) ((A) * (float) (B))
#define _IQ29mpyI32(A,B) ((A) * (float) (B))
#define _IQ28mpyI32(A,B) ((A) * (float) (B))
#define _IQ27mpyI32(A,B) ((A) * (float) (B))
#define _IQ26mpyI32(A,B) ((A) * (float) (B))
#define _IQ25mpyI32(A,B) ((A) * (float) (B))
#define _IQ24mpyI32(A,B) ((A) * (float) (B))
#define _IQ23mpyI32(A,B) ((A) * (float) (B))
#define _IQ22mpyI32(A,B) ((A) * (float) (B))
#define _IQ21mpyI32(A,B) ((A) * (float) (B))
#define _IQ20mpyI32(A,B) ((A) * (float) (B))
#define _IQ19mpyI32(A,B) ((A) * (float) (B))
#define _IQ18mpyI32(A,B) ((A) * (float) (B))
#define _IQ17mpyI32(A,B) ((A) * (float) (B))
#define _IQ16mpyI32(A,B) ((A) * (float) (B))
#define _IQ15mpyI32(A,B) ((A) * (float) (B))
#define _IQ14mpyI32(A,B) ((A) * (float) (B))
#define _IQ13mpyI32(A,B) ((A) * (float) (B))
#define _IQ12mpyI32(A,B) ((A) * (float) (B))
#define _IQ11mpyI32(A,B) ((A) * (float) (B))
#define _IQ10mpyI32(A,B) ((A) * (float) (B))
#define _IQ9mpyI32(A,B) ((A) * (float) (B))
#define _IQ8mpyI32(A,B) ((A) * (float) (B))
#define _IQ7mpyI32(A,B) ((A) * (float) (B))
#define _IQ6mpyI32(A,B) ((A) * (float) (B))
#define _IQ5mpyI32(A,B) ((A) * (float) (B))
#define _IQ4mpyI32(A,B) ((A) * (float) (B))
#define _IQ3mpyI32(A,B) ((A) * (float) (B))
#define _IQ2mpyI32(A,B) ((A) * (float) (B))
#define _IQ1mpyI32(A,B) ((A) * (float) (B))
//---------------------------------------------------------------------------
#define _IQmpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ30mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ29mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ28mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ27mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ26mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ25mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ24mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ23mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ22mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ21mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ20mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ19mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ18mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ17mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ16mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ15mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ14mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ13mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ12mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ11mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ10mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ9mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ8mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ7mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ6mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ5mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ4mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ3mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ2mpyI32int(A,B) ((long) ((A) * (float) (B)))
#define _IQ1mpyI32int(A,B) ((long) ((A) * (float) (B)))
//---------------------------------------------------------------------------
#define _IQmpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ30mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ29mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ28mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ27mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ26mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ25mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ24mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ23mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ22mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ21mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ20mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ19mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ18mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ17mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ16mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ15mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ14mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ13mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ12mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ11mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ10mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ9mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ8mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ7mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ6mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ5mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ4mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ3mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ2mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
#define _IQ1mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B))))
//---------------------------------------------------------------------------
#define _IQmag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ30mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ29mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ28mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ27mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ26mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ25mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ24mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ23mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ22mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ21mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ20mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ19mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ18mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ17mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ16mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ15mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ14mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ13mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ12mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ11mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ10mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ9mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ8mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ7mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ6mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ5mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ4mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ3mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ2mag(A,B) sqrt((A)*(A) + (B)*(B))
#define _IQ1mag(A,B) sqrt((A)*(A) + (B)*(B))
//---------------------------------------------------------------------------
#define _atoIQ(A) atof(A)
#define _atoIQ30(A) atof(A)
#define _atoIQ29(A) atof(A)
#define _atoIQ28(A) atof(A)
#define _atoIQ27(A) atof(A)
#define _atoIQ26(A) atof(A)
#define _atoIQ25(A) atof(A)
#define _atoIQ24(A) atof(A)
#define _atoIQ23(A) atof(A)
#define _atoIQ22(A) atof(A)
#define _atoIQ21(A) atof(A)
#define _atoIQ20(A) atof(A)
#define _atoIQ19(A) atof(A)
#define _atoIQ18(A) atof(A)
#define _atoIQ17(A) atof(A)
#define _atoIQ16(A) atof(A)
#define _atoIQ15(A) atof(A)
#define _atoIQ14(A) atof(A)
#define _atoIQ13(A) atof(A)
#define _atoIQ12(A) atof(A)
#define _atoIQ11(A) atof(A)
#define _atoIQ10(A) atof(A)
#define _atoIQ9(A) atof(A)
#define _atoIQ8(A) atof(A)
#define _atoIQ7(A) atof(A)
#define _atoIQ6(A) atof(A)
#define _atoIQ5(A) atof(A)
#define _atoIQ4(A) atof(A)
#define _atoIQ3(A) atof(A)
#define _atoIQ2(A) atof(A)
#define _atoIQ1(A) atof(A)
//---------------------------------------------------------------------------
#define _IQtoa(A, B, C) sprintf(A, B, C)
#define _IQ30toa(A, B, C) sprintf(A, B, C)
#define _IQ29toa(A, B, C) sprintf(A, B, C)
#define _IQ28toa(A, B, C) sprintf(A, B, C)
#define _IQ27toa(A, B, C) sprintf(A, B, C)
#define _IQ26toa(A, B, C) sprintf(A, B, C)
#define _IQ25toa(A, B, C) sprintf(A, B, C)
#define _IQ24toa(A, B, C) sprintf(A, B, C)
#define _IQ23toa(A, B, C) sprintf(A, B, C)
#define _IQ22toa(A, B, C) sprintf(A, B, C)
#define _IQ21toa(A, B, C) sprintf(A, B, C)
#define _IQ20toa(A, B, C) sprintf(A, B, C)
#define _IQ19toa(A, B, C) sprintf(A, B, C)
#define _IQ18toa(A, B, C) sprintf(A, B, C)
#define _IQ17toa(A, B, C) sprintf(A, B, C)
#define _IQ16toa(A, B, C) sprintf(A, B, C)
#define _IQ15toa(A, B, C) sprintf(A, B, C)
#define _IQ14toa(A, B, C) sprintf(A, B, C)
#define _IQ13toa(A, B, C) sprintf(A, B, C)
#define _IQ12toa(A, B, C) sprintf(A, B, C)
#define _IQ11toa(A, B, C) sprintf(A, B, C)
#define _IQ10toa(A, B, C) sprintf(A, B, C)
#define _IQ9toa(A, B, C) sprintf(A, B, C)
#define _IQ8toa(A, B, C) sprintf(A, B, C)
#define _IQ7toa(A, B, C) sprintf(A, B, C)
#define _IQ6toa(A, B, C) sprintf(A, B, C)
#define _IQ5toa(A, B, C) sprintf(A, B, C)
#define _IQ4toa(A, B, C) sprintf(A, B, C)
#define _IQ3toa(A, B, C) sprintf(A, B, C)
#define _IQ2toa(A, B, C) sprintf(A, B, C)
#define _IQ1toa(A, B, C) sprintf(A, B, C)
//---------------------------------------------------------------------------
#define _IQabs(A) fabs(A)
#define _IQ30abs(A) fabs(A)
#define _IQ29abs(A) fabs(A)
#define _IQ28abs(A) fabs(A)
#define _IQ27abs(A) fabs(A)
#define _IQ26abs(A) fabs(A)
#define _IQ25abs(A) fabs(A)
#define _IQ24abs(A) fabs(A)
#define _IQ23abs(A) fabs(A)
#define _IQ22abs(A) fabs(A)
#define _IQ21abs(A) fabs(A)
#define _IQ20abs(A) fabs(A)
#define _IQ19abs(A) fabs(A)
#define _IQ18abs(A) fabs(A)
#define _IQ17abs(A) fabs(A)
#define _IQ16abs(A) fabs(A)
#define _IQ15abs(A) fabs(A)
#define _IQ14abs(A) fabs(A)
#define _IQ13abs(A) fabs(A)
#define _IQ12abs(A) fabs(A)
#define _IQ11abs(A) fabs(A)
#define _IQ10abs(A) fabs(A)
#define _IQ9abs(A) fabs(A)
#define _IQ8abs(A) fabs(A)
#define _IQ7abs(A) fabs(A)
#define _IQ6abs(A) fabs(A)
#define _IQ5abs(A) fabs(A)
#define _IQ4abs(A) fabs(A)
#define _IQ3abs(A) fabs(A)
#define _IQ2abs(A) fabs(A)
#define _IQ1abs(A) fabs(A)
//###########################################################################
#endif // No more.
//###########################################################################
#endif /* __IQMATHLIB_H_INCLUDED__ */

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//###########################################################################
//
// FILE: SFO.H
//
// TITLE: Scale Factor Optimizer Library Interface Header
//
//
//###########################################################################
//
// Ver | dd mmm yyyy | Who | Description of changes
// =====|=============|======|===============================================
// 0.01| 09 Jan 2004 | TI | New module
//###########################################################################
//============================================================================
// Description: This header provides the function call interface
// for the scale factor optimizer for the 'F2833x.
//============================================================================
//============================================================================
// Multiple include Guard
//============================================================================
#ifndef __4090522384024n8273240x3438jx43087401r34ru32r0___
#define __4090522384024n8273240x3438jx43087401r34ru32r0___
//============================================================================
// C++ namespace
//============================================================================
#ifdef __cplusplus
extern "C" {
#endif
//============================================================================
// Function prototypes for MEP SFO
//============================================================================
void SFO_MepEn(int nEpwmModule);
void SFO_MepDis(int nEpwmModule);
//============================================================================
// Multiple include Guard
//============================================================================
#endif // End: Multiple include Guard
//============================================================================
// C++ namespace
//============================================================================
#ifdef __cplusplus
}
#endif /* extern "C" */

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//###########################################################################
//
// FILE: SFO_V5.H
//
// TITLE: Scale Factor Optimizer Library V5 Interface Header
//
//
//###########################################################################
//
// Ver | dd mmm yyyy | Who | Description of changes
// =====|=============|======|===============================================
// 0.01| 09 Jan 2004 | TI | New module
// 0.02| 22 Jun 2007 | TI | New version (V5) with support for more channels
//###########################################################################
//============================================================================
// Description: This header provides the function call interface
// for the scale factor optimizer V5. For more
// information on the SFO function usage and
// limitations, see the HRPWM Reference Guide
// (spru924) on the TI website.
//============================================================================
//============================================================================
// Multiple include Guard
//============================================================================
#ifndef _SFO_V5_H
#define _SFO_V5_H
//============================================================================
// C++ namespace
//============================================================================
#ifdef __cplusplus
extern "C" {
#endif
//============================================================================
// USER MUST UPDATE THIS CONSTANT FOR NUMBER OF HRPWM CHANNELS USED + 1
//============================================================================
#define PWM_CH 7 // Equal # of HRPWM channels PLUS 1
// i.e. PWM_CH is 7 for 6 channels, 5 for 4 channels etc.
//============================================================================
// Function prototypes for MEP SFO
//============================================================================
int SFO_MepEn_V5(int nEpwmModule); // MEP-Enable V5 Calibration Function
int SFO_MepDis_V5(int nEpwmModule); // MEP-Disable V5 Calibration Function
//============================================================================
// Useful Defines when Using SFO Functions
//============================================================================
#define SFO_INCOMPLETE 0
#define SFO_COMPLETE 1
#define SFO_OUTRANGE_ERROR 2
//============================================================================
// Multiple include Guard
//============================================================================
#endif // End: Multiple include Guard
//============================================================================
// C++ namespace
//============================================================================
#ifdef __cplusplus
}
#endif /* extern "C" */

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;; TI File $Revision: /main/1 $
;; Checkin $Date: July 30, 2007 10:29:23 $
;;###########################################################################
;;
;; FILE: ADC_cal.asm
;;
;; TITLE: 2833x Boot Rom ADC Cal routine.
;;
;; Functions:
;;
;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers
;; Notes:
;;
;;###########################################################################
;; $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
;; $Release Date: August 1, 2008 $
;;###########################################################################
.def _ADC_cal
.asg "0x711C", ADCREFSEL_LOC
;-----------------------------------------------
; _ADC_cal
;-----------------------------------------------
;-----------------------------------------------
; This is the ADC cal routine.This routine is programmed into
; reserved memory by the factory. 0xAAAA and 0xBBBB are place-
; holders for calibration data.
;The actual values programmed by TI are device specific.
;
; This function assumes that the clocks have been
; enabled to the ADC module.
;-----------------------------------------------
.sect ".adc_cal"
_ADC_cal
MOVW DP, #ADCREFSEL_LOC >> 6
MOV @28, #0xAAAA ; actual value may not be 0xAAAA
MOV @29, #0xBBBB ; actual value may not be 0xBBBB
LRETR
;eof ----------

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v120/DSP2833x_common/source/DSP2833x_Adc.c Normal file
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// TI File $Revision: /main/5 $
// Checkin $Date: October 23, 2007 13:34:09 $
//###########################################################################
//
// FILE: DSP2833x_Adc.c
//
// TITLE: DSP2833x ADC Initialization & Support Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
#define ADC_usDELAY 5000L
//---------------------------------------------------------------------------
// InitAdc:
//---------------------------------------------------------------------------
// This function initializes ADC to a known state.
//
void InitAdc(void)
{
extern void DSP28x_usDelay(Uint32 Count);
// *IMPORTANT*
// The ADC_cal function, which copies the ADC calibration values from TI reserved
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
ADC_cal();
EDIS;
// To powerup the ADC the ADCENCLK bit should be set first to enable
// clocks, followed by powering up the bandgap, reference circuitry, and ADC core.
// Before the first conversion is performed a 5ms delay must be observed
// after power up to give all analog circuits time to power up and settle
// Please note that for the delay function below to operate correctly the
// CPU_RATE define statement in the DSP2833x_Examples.h file must
// contain the correct CPU clock period in nanoseconds.
AdcRegs.ADCREFSEL.bit.REF_SEL = 0x01;
AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits
DELAY_US(ADC_usDELAY); // Delay before converting ADC channels
//pause_us(50L);
}
//===========================================================================
// End of file.
//===========================================================================

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;// TI File $Revision: /main/3 $
;// Checkin $Date: June 26, 2007 16:41:07 $
;//###########################################################################
;//
;// FILE: DSP2833x_CSMPasswords.asm
;//
;// TITLE: DSP2833x Code Security Module Passwords.
;//
;// DESCRIPTION:
;//
;// This file is used to specify password values to
;// program into the CSM password locations in Flash
;// at 0x33FFF8 - 0x33FFFF.
;//
;// In addition, the reserved locations 0x33FF80 - 0X33fff5 are
;// all programmed to 0x0000
;//
;//###########################################################################
;//
;// Original source based on D.A.
;//
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
;// $Release Date: August 1, 2008 $
;//###########################################################################
; The "csmpasswords" section contains the actual CSM passwords that will be
; linked and programmed into to the CSM password locations (PWL) in flash.
; These passwords must be known in order to unlock the CSM module.
; All 0xFFFF's (erased) is the default value for the password locations (PWL).
; It is recommended that all passwords be left as 0xFFFF during code
; development. Passwords of 0xFFFF do not activate code security and dummy
; reads of the CSM PWL registers is all that is required to unlock the CSM.
; When code development is complete, modify the passwords to activate the
; code security module.
.sect "csmpasswds"
.int 0xFFFF ;PWL0 (LSW of 128-bit password)
.int 0xFFFF ;PWL1
.int 0xFFFF ;PWL2
.int 0xFFFF ;PWL3
.int 0xFFFF ;PWL4
.int 0xFFFF ;PWL5
.int 0xFFFF ;PWL6
.int 0xFFFF ;PWL7 (MSW of 128-bit password)
;----------------------------------------------------------------------
; For code security operation, all addresses between 0x33FF80 and
; 0X33fff5 cannot be used as program code or data. These locations
; must be programmed to 0x0000 when the code security password locations
; (PWL) are programmed. If security is not a concern, then these addresses
; can be used for code or data.
; The section "csm_rsvd" can be used to program these locations to 0x0000.
.sect "csm_rsvd"
.loop (33FFF5h - 33FF80h + 1)
.int 0x0000
.endloop
;//===========================================================================
;// End of file.
;//===========================================================================

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v120/DSP2833x_common/source/DSP2833x_CodeStartBranch.asm Normal file
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;// TI File $Revision: /main/1 $
;// Checkin $Date: August 18, 2006 13:45:55 $
;//###########################################################################
;//
;// FILE: DSP2833x_CodeStartBranch.asm
;//
;// TITLE: Branch for redirecting code execution after boot.
;//
;// For these examples, code_start is the first code that is executed after
;// exiting the boot ROM code.
;//
;// The codestart section in the linker cmd file is used to physically place
;// this code at the correct memory location. This section should be placed
;// at the location the BOOT ROM will re-direct the code to. For example,
;// for boot to FLASH this code will be located at 0x3f7ff6.
;//
;// In addition, the example DSP2833x projects are setup such that the codegen
;// entry point is also set to the code_start label. This is done by linker
;// option -e in the project build options. When the debugger loads the code,
;// it will automatically set the PC to the "entry point" address indicated by
;// the -e linker option. In this case the debugger is simply assigning the PC,
;// it is not the same as a full reset of the device.
;//
;// The compiler may warn that the entry point for the project is other then
;// _c_init00. _c_init00 is the C environment setup and is run before
;// main() is entered. The code_start code will re-direct the execution
;// to _c_init00 and thus there is no worry and this warning can be ignored.
;//
;//###########################################################################
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
;// $Release Date: August 1, 2008 $
;//###########################################################################
***********************************************************************
WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0
.ref _c_int00
.global code_start
***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************
.sect "codestart"
code_start:
.if WD_DISABLE == 1
LB wd_disable ;Branch to watchdog disable code
.else
LB _c_int00 ;Branch to start of boot.asm in RTS library
.endif
;end codestart section
***********************************************************************
* Function: wd_disable
*
* Description: Disables the watchdog timer
***********************************************************************
.if WD_DISABLE == 1
.text
wd_disable:
SETC OBJMODE ;Set OBJMODE for 28x object code
EALLOW ;Enable EALLOW protected register access
MOVZ DP, #7029h>>6 ;Set data page for WDCR register
MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
EDIS ;Disable EALLOW protected register access
LB _c_int00 ;Branch to start of boot.asm in RTS library
.endif
;end wd_disable
.end
;//===========================================================================
;// End of file.
;//===========================================================================

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// TI File $Revision: /main/3 $
// Checkin $Date: March 16, 2007 08:37:30 $
//###########################################################################
//
// FILE: DSP2833x_CpuTimers.c
//
// TITLE: CPU 32-bit Timers Initialization & Support Functions.
//
// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
// other realtime operating systems.
//
// Do not use these two timers in your application if you ever plan
// on integrating DSP-BIOS or another realtime OS.
//
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // Headerfile Include File
#include "DSP2833x_Examples.h" // Examples Include File
struct CPUTIMER_VARS CpuTimer0;
// CpuTimer 1 and CpuTimer2 are used by DSP BIOS & other RTOS. Comment out if using DSP BIOS or other RTOS.
struct CPUTIMER_VARS CpuTimer1;
struct CPUTIMER_VARS CpuTimer2;
//---------------------------------------------------------------------------
// InitCpuTimers:
//---------------------------------------------------------------------------
// This function initializes all three CPU timers to a known state.
//
void InitCpuTimers(void)
{
// CPU Timer 0
// Initialize address pointers to respective timer registers:
CpuTimer0.RegsAddr = &CpuTimer0Regs;
// Initialize timer period to maximum:
CpuTimer0Regs.PRD.all = 0xFFFFFFFF;
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
CpuTimer0Regs.TPR.all = 0;
CpuTimer0Regs.TPRH.all = 0;
// Make sure timer is stopped:
CpuTimer0Regs.TCR.bit.TSS = 1;
// Reload all counter register with period value:
CpuTimer0Regs.TCR.bit.TRB = 1;
// Reset interrupt counters:
CpuTimer0.InterruptCount = 0;
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
// Do not use these two timers if you ever plan on integrating
// DSP-BIOS or another realtime OS.
//
// Initialize address pointers to respective timer registers:
CpuTimer1.RegsAddr = &CpuTimer1Regs;
CpuTimer2.RegsAddr = &CpuTimer2Regs;
// Initialize timer period to maximum:
CpuTimer1Regs.PRD.all = 0xFFFFFFFF;
CpuTimer2Regs.PRD.all = 0xFFFFFFFF;
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
CpuTimer1Regs.TPR.all = 0;
CpuTimer1Regs.TPRH.all = 0;
CpuTimer2Regs.TPR.all = 0;
CpuTimer2Regs.TPRH.all = 0;
// Make sure timers are stopped:
CpuTimer1Regs.TCR.bit.TSS = 1;
CpuTimer2Regs.TCR.bit.TSS = 1;
// Reload all counter register with period value:
CpuTimer1Regs.TCR.bit.TRB = 1;
CpuTimer2Regs.TCR.bit.TRB = 1;
// Reset interrupt counters:
CpuTimer1.InterruptCount = 0;
CpuTimer2.InterruptCount = 0;
}
//---------------------------------------------------------------------------
// ConfigCpuTimer:
//---------------------------------------------------------------------------
// This function initializes the selected timer to the period specified
// by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz"
// and the period in "uSeconds". The timer is held in the stopped state
// after configuration.
//
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
{
Uint32 temp;
// Initialize timer period:
Timer->CPUFreqInMHz = Freq;
Timer->PeriodInUSec = Period;
temp = (long) (Freq * Period);
Timer->RegsAddr->PRD.all = temp;
// Set pre-scale counter to divide by 1 (SYSCLKOUT):
Timer->RegsAddr->TPR.all = 0;
Timer->RegsAddr->TPRH.all = 0;
// Initialize timer control register:
Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer
Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
Timer->RegsAddr->TCR.bit.SOFT = 0;
Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled
Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt
// Reset interrupt counter:
Timer->InterruptCount = 0;
}
//===========================================================================
// End of file.
//===========================================================================

28
v120/DSP2833x_common/source/DSP2833x_DBGIER.asm Normal file
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@@ -0,0 +1,28 @@
;// TI File $Revision: /main/1 $
;// Checkin $Date: August 18, 2006 13:46:03 $
;//###########################################################################
;//
;// FILE: DSP2833x_DBGIER.asm
;//
;// TITLE: Set the DBGIER register
;//
;// DESCRIPTION:
;//
;// Function to set the DBGIER register (for realtime emulation).
;// Function Prototype: void SetDBGIER(Uint16)
;// Useage: SetDBGIER(value);
;// Input Parameters: Uint16 value = value to put in DBGIER register.
;// Return Value: none
;//
;//###########################################################################
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
;// $Release Date: August 1, 2008 $
;//###########################################################################
.global _SetDBGIER
.text
_SetDBGIER:
MOV *SP++,AL
POP DBGIER
LRETR

590
v120/DSP2833x_common/source/DSP2833x_DMA.c Normal file
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@@ -0,0 +1,590 @@
//###########################################################################
//
// FILE: DSP2833x_DMA.c
//
// TITLE: DSP2833x Device DMA Initialization & Support Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // Headerfile Include File
#include "DSP2833x_Examples.h" // Examples Include File
// This function initializes the DMA to a known state.
//
void DMAInitialize(void)
{
EALLOW;
// Perform a hard reset on DMA
DmaRegs.DMACTRL.bit.HARDRESET = 1;
asm (" nop"); // one NOP required after HARDRESET
// Allow DMA to run free on emulation suspend
DmaRegs.DEBUGCTRL.bit.FREE = 1;
EDIS;
}
void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
{
EALLOW;
// Set up SOURCE address:
DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
// Set up DESTINATION address:
DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
EDIS;
}
void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
{
EALLOW;
// Set up BURST registers:
DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
EDIS;
}
void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
{
EALLOW;
// Set up TRANSFER registers:
DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
EDIS;
}
void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
{
EALLOW;
// Set up WRAP registers:
DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap
DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap
EDIS;
}
void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
{
EALLOW;
// Set up MODE Register:
DmaRegs.CH1.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH1.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; // Oneshot enable
DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; // Continous enable
DmaRegs.CH1.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
DmaRegs.CH1.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
DmaRegs.CH1.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH1.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
// Clear any spurious flags:
DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE
EDIS;
}
// This function starts DMA Channel 1.
void StartDMACH1(void)
{
EALLOW;
DmaRegs.CH1.CONTROL.bit.RUN = 1;
EDIS;
}
void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
{
EALLOW;
// Set up SOURCE address:
DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
// Set up DESTINATION address:
DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
EDIS;
}
void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
{
EALLOW;
// Set up BURST registers:
DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
EDIS;
}
void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
{
EALLOW;
// Set up TRANSFER registers:
DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
EDIS;
}
void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
{
EALLOW;
// Set up WRAP registers:
DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap
DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap
EDIS;
}
void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
{
EALLOW;
// Set up MODE Register:
DmaRegs.CH2.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH2.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; // Oneshot enable
DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; // Continous enable
DmaRegs.CH2.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
DmaRegs.CH2.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
DmaRegs.CH2.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH2.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
// Clear any spurious flags:
DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable DMA CH2 interrupt in PIE
EDIS;
}
// This function starts DMA Channel 2.
void StartDMACH2(void)
{
EALLOW;
DmaRegs.CH2.CONTROL.bit.RUN = 1;
EDIS;
}
void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
{
EALLOW;
// Set up SOURCE address:
DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
// Set up DESTINATION address:
DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
EDIS;
}
void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
{
EALLOW;
// Set up BURST registers:
DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
EDIS;
}
void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
{
EALLOW;
// Set up TRANSFER registers:
DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
EDIS;
}
void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
{
EALLOW;
// Set up WRAP registers:
DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap
DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap
EDIS;
}
void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
{
EALLOW;
// Set up MODE Register:
DmaRegs.CH3.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH3.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; // Oneshot enable
DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; // Continous enable
DmaRegs.CH3.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
DmaRegs.CH3.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
DmaRegs.CH3.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH3.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
// Clear any spurious flags:
DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
PieCtrlRegs.PIEIER7.bit.INTx3 = 1; // Enable DMA CH3 interrupt in PIE
EDIS;
}
// This function starts DMA Channel 3.
void StartDMACH3(void)
{
EALLOW;
DmaRegs.CH3.CONTROL.bit.RUN = 1;
EDIS;
}
void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
{
EALLOW;
// Set up SOURCE address:
DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
// Set up DESTINATION address:
DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
EDIS;
}
void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
{
EALLOW;
// Set up BURST registers:
DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
EDIS;
}
void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
{
EALLOW;
// Set up TRANSFER registers:
DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
EDIS;
}
void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
{
EALLOW;
// Set up WRAP registers:
DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap
DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap
EDIS;
}
void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
{
EALLOW;
// Set up MODE Register:
DmaRegs.CH4.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH4.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; // Oneshot enable
DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; // Continous enable
DmaRegs.CH4.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
DmaRegs.CH4.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
DmaRegs.CH4.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH4.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
// Clear any spurious flags:
DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH4.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
PieCtrlRegs.PIEIER7.bit.INTx4 = 1; // Enable DMA CH4 interrupt in PIE
EDIS;
}
// This function starts DMA Channel 4.
void StartDMACH4(void)
{
EALLOW;
DmaRegs.CH4.CONTROL.bit.RUN = 1;
EDIS;
}
void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
{
EALLOW;
// Set up SOURCE address:
DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
// Set up DESTINATION address:
DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
EDIS;
}
void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
{
EALLOW;
// Set up BURST registers:
DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
EDIS;
}
void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
{
EALLOW;
// Set up TRANSFER registers:
DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
EDIS;
}
void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
{
EALLOW;
// Set up WRAP registers:
DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap
DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap
EDIS;
}
void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
{
EALLOW;
// Set up MODE Register:
DmaRegs.CH5.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH5.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; // Oneshot enable
DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; // Continous enable
DmaRegs.CH5.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
DmaRegs.CH5.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
DmaRegs.CH5.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH5.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
// Clear any spurious flags:
DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH5.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
PieCtrlRegs.PIEIER7.bit.INTx5 = 1; // Enable DMA CH5 interrupt in PIE
EDIS;
}
// This function starts DMA Channel 5.
void StartDMACH5(void)
{
EALLOW;
DmaRegs.CH5.CONTROL.bit.RUN = 1;
EDIS;
}
void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
{
EALLOW;
// Set up SOURCE address:
DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
// Set up DESTINATION address:
DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
EDIS;
}
void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep)
{
EALLOW;
// Set up BURST registers:
DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
EDIS;
}
void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
{
EALLOW;
// Set up TRANSFER registers:
DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
EDIS;
}
void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
{
EALLOW;
// Set up WRAP registers:
DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap
DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap
EDIS;
}
void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
{
EALLOW;
// Set up MODE Register:
DmaRegs.CH6.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH6.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; // Oneshot enable
DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; // Continous enable
DmaRegs.CH6.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
DmaRegs.CH6.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
DmaRegs.CH6.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH6.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
// Clear any spurious flags:
DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH6.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
PieCtrlRegs.PIEIER7.bit.INTx6 = 1; // Enable DMA CH6 interrupt in PIE
EDIS;
}
// This function starts DMA Channel 6.
void StartDMACH6(void)
{
EALLOW;
DmaRegs.CH6.CONTROL.bit.RUN = 1;
EDIS;
}
//===========================================================================
// No more.
//===========================================================================

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v120/DSP2833x_common/source/DSP2833x_DefaultIsr.c Normal file
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@@ -0,0 +1,1187 @@
// TI File $Revision: /main/2 $
// Checkin $Date: January 14, 2008 11:17:46 $
//###########################################################################
//
// FILE: DSP2833x_DefaultIsr.c
//
// TITLE: DSP2833x Device Default Interrupt Service Routines.
//
// This file contains shell ISR routines for the 2833x PIE vector table.
// Typically these shell ISR routines can be used to populate the entire PIE
// vector table during device debug. In this manner if an interrupt is taken
// during firmware development, there will always be an ISR to catch it.
//
// As develpment progresses, these ISR rotuines can be eliminated and replaced
// with the user's own ISR routines for each interrupt. Since these shell ISRs
// include infinite loops they will typically not be included as-is in the final
// production firmware.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
// Connected to INT13 of CPU (use MINT13 mask):
// Note CPU-Timer1 is reserved for TI use, however XINT13
// ISR can be used by the user.
interrupt void INT13_ISR(void) // INT13 or CPU-Timer1
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// Note CPU-Timer2 is reserved for TI use.
interrupt void INT14_ISR(void) // CPU-Timer2
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void DATALOG_ISR(void) // Datalogging interrupt
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void RTOSINT_ISR(void) // RTOS interrupt
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void EMUINT_ISR(void) // Emulation interrupt
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void NMI_ISR(void) // Non-maskable interrupt
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm(" ESTOP0");
for(;;);
}
interrupt void USER1_ISR(void) // User Defined trap 1
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER2_ISR(void) // User Defined trap 2
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER3_ISR(void) // User Defined trap 3
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER4_ISR(void) // User Defined trap 4
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER5_ISR(void) // User Defined trap 5
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER6_ISR(void) // User Defined trap 6
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER7_ISR(void) // User Defined trap 7
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER8_ISR(void) // User Defined trap 8
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER9_ISR(void) // User Defined trap 9
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER10_ISR(void) // User Defined trap 10
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER11_ISR(void) // User Defined trap 11
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
interrupt void USER12_ISR(void) // User Defined trap 12
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// -----------------------------------------------------------
// PIE Group 1 - MUXed into CPU INT1
// -----------------------------------------------------------
// INT1.1
interrupt void SEQ1INT_ISR(void) //SEQ1 ADC
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT1.2
interrupt void SEQ2INT_ISR(void) //SEQ2 ADC
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm(" ESTOP0");
for(;;);
}
// INT1.3 - Reserved
// INT1.4
interrupt void XINT1_ISR(void)
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT1.5
interrupt void XINT2_ISR(void)
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT1.6
interrupt void ADCINT_ISR(void) // ADC
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT1.7
interrupt void TINT0_ISR(void) // CPU-Timer 0
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT1.8
interrupt void WAKEINT_ISR(void) // WD, LOW Power
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// -----------------------------------------------------------
// PIE Group 2 - MUXed into CPU INT2
// -----------------------------------------------------------
// INT2.1
interrupt void EPWM1_TZINT_ISR(void) // EPWM-1
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT2.2
interrupt void EPWM2_TZINT_ISR(void) // EPWM-2
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT2.3
interrupt void EPWM3_TZINT_ISR(void) // EPWM-3
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT2.4
interrupt void EPWM4_TZINT_ISR(void) // EPWM-4
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT2.5
interrupt void EPWM5_TZINT_ISR(void) // EPWM-5
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT2.6
interrupt void EPWM6_TZINT_ISR(void) // EPWM-6
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT2.7 - Reserved
// INT2.8 - Reserved
// -----------------------------------------------------------
// PIE Group 3 - MUXed into CPU INT3
// -----------------------------------------------------------
// INT 3.1
interrupt void EPWM1_INT_ISR(void) // EPWM-1
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT3.2
interrupt void EPWM2_INT_ISR(void) // EPWM-2
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT3.3
interrupt void EPWM3_INT_ISR(void) // EPWM-3
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT3.4
interrupt void EPWM4_INT_ISR(void) // EPWM-4
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT3.5
interrupt void EPWM5_INT_ISR(void) // EPWM-5
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT3.6
interrupt void EPWM6_INT_ISR(void) // EPWM-6
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT3.7 - Reserved
// INT3.8 - Reserved
// -----------------------------------------------------------
// PIE Group 4 - MUXed into CPU INT4
// -----------------------------------------------------------
// INT 4.1
interrupt void ECAP1_INT_ISR(void) // ECAP-1
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT4.2
interrupt void ECAP2_INT_ISR(void) // ECAP-2
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT4.3
interrupt void ECAP3_INT_ISR(void) // ECAP-3
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT4.4
interrupt void ECAP4_INT_ISR(void) // ECAP-4
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT4.5
interrupt void ECAP5_INT_ISR(void) // ECAP-5
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT4.6
interrupt void ECAP6_INT_ISR(void) // ECAP-6
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT4.7 - Reserved
// INT4.8 - Reserved
// -----------------------------------------------------------
// PIE Group 5 - MUXed into CPU INT5
// -----------------------------------------------------------
// INT 5.1
interrupt void EQEP1_INT_ISR(void) // EQEP-1
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT5.2
interrupt void EQEP2_INT_ISR(void) // EQEP-2
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT5.3 - Reserved
// INT5.4 - Reserved
// INT5.5 - Reserved
// INT5.6 - Reserved
// INT5.7 - Reserved
// INT5.8 - Reserved
// -----------------------------------------------------------
// PIE Group 6 - MUXed into CPU INT6
// -----------------------------------------------------------
// INT6.1
interrupt void SPIRXINTA_ISR(void) // SPI-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT6.2
interrupt void SPITXINTA_ISR(void) // SPI-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT6.3
interrupt void MRINTB_ISR(void) // McBSP-B
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT6.4
interrupt void MXINTB_ISR(void) // McBSP-B
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT6.5
interrupt void MRINTA_ISR(void) // McBSP-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT6.6
interrupt void MXINTA_ISR(void) // McBSP-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT6.7 - Reserved
// INT6.8 - Reserved
// -----------------------------------------------------------
// PIE Group 7 - MUXed into CPU INT7
// -----------------------------------------------------------
// INT7.1
interrupt void DINTCH1_ISR(void) // DMA
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT7.2
interrupt void DINTCH2_ISR(void) // DMA
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT7.3
interrupt void DINTCH3_ISR(void) // DMA
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT7.4
interrupt void DINTCH4_ISR(void) // DMA
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT7.5
interrupt void DINTCH5_ISR(void) // DMA
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT7.6
interrupt void DINTCH6_ISR(void) // DMA
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT7.7 - Reserved
// INT7.8 - Reserved
// -----------------------------------------------------------
// PIE Group 8 - MUXed into CPU INT8
// -----------------------------------------------------------
// INT8.1
interrupt void I2CINT1A_ISR(void) // I2C-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT8.2
interrupt void I2CINT2A_ISR(void) // I2C-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT8.3 - Reserved
// INT8.4 - Reserved
// INT8.5
interrupt void SCIRXINTC_ISR(void) // SCI-C
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT8.6
interrupt void SCITXINTC_ISR(void) // SCI-C
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT8.7 - Reserved
// INT8.8 - Reserved
// -----------------------------------------------------------
// PIE Group 9 - MUXed into CPU INT9
// -----------------------------------------------------------
// INT9.1
interrupt void SCIRXINTA_ISR(void) // SCI-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.2
interrupt void SCITXINTA_ISR(void) // SCI-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.3
interrupt void SCIRXINTB_ISR(void) // SCI-B
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.4
interrupt void SCITXINTB_ISR(void) // SCI-B
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.5
interrupt void ECAN0INTA_ISR(void) // eCAN-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.6
interrupt void ECAN1INTA_ISR(void) // eCAN-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.7
interrupt void ECAN0INTB_ISR(void) // eCAN-B
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.8
interrupt void ECAN1INTB_ISR(void) // eCAN-B
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// -----------------------------------------------------------
// PIE Group 10 - MUXed into CPU INT10
// -----------------------------------------------------------
// INT10.1 - Reserved
// INT10.2 - Reserved
// INT10.3 - Reserved
// INT10.4 - Reserved
// INT10.5 - Reserved
// INT10.6 - Reserved
// INT10.7 - Reserved
// INT10.8 - Reserved
// -----------------------------------------------------------
// PIE Group 11 - MUXed into CPU INT11
// -----------------------------------------------------------
// INT11.1 - Reserved
// INT11.2 - Reserved
// INT11.3 - Reserved
// INT11.4 - Reserved
// INT11.5 - Reserved
// INT11.6 - Reserved
// INT11.7 - Reserved
// INT11.8 - Reserved
// -----------------------------------------------------------
// PIE Group 12 - MUXed into CPU INT12
// -----------------------------------------------------------
// INT12.1
interrupt void XINT3_ISR(void) // External Interrupt
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT12.2
interrupt void XINT4_ISR(void) // External Interrupt
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT12.3
interrupt void XINT5_ISR(void) // External Interrupt
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT12.4
interrupt void XINT6_ISR(void) // External Interrupt
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT12.5
interrupt void XINT7_ISR(void) // External Interrupt
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT12.6 - Reserved
// INT12.7
interrupt void LVF_ISR(void) // Latched overflow
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT12.8
interrupt void LUF_ISR(void) // Latched underflow
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
//---------------------------------------------------------------------------
// Catch All Default ISRs:
//
interrupt void PIE_RESERVED(void) // Reserved space. For test.
{
asm (" ESTOP0");
for(;;);
}
interrupt void rsvd_ISR(void) // For test
{
asm (" ESTOP0");
for(;;);
}
//===========================================================================
// End of file.
//===========================================================================

65
v120/DSP2833x_common/source/DSP2833x_DisInt.asm Normal file
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;// TI File $Revision: /main/1 $
;// Checkin $Date: August 18, 2006 13:46:09 $
;//###########################################################################
;//
;// FILE: DSP2833x_DisInt.asm
;//
;// TITLE: Disable and Restore INTM and DBGM
;//
;// Function Prototypes:
;//
;// Uint16 DSP28x_DisableInt();
;// and void DSP28x_RestoreInt(Uint16 Stat0);
;//
;// Usage:
;//
;// DSP28x_DisableInt() sets both the INTM and DBGM
;// bits to disable maskable interrupts. Before doing
;// this, the current value of ST1 is stored on the stack
;// so that the values can be restored later. The value
;// of ST1 before the masks are set is returned to the
;// user in AL. This is then used to restore their state
;// via the DSP28x_RestoreInt(Uint16 ST1) function.
;//
;// Example
;//
;// Uint16 StatusReg1
;// StatusReg1 = DSP28x_DisableInt();
;//
;// ... May also want to disable INTM here
;//
;// ... code here
;//
;// DSP28x_RestoreInt(StatusReg1);
;//
;// ... Restore INTM enable
;//
;//###########################################################################
;// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
;// $Release Date: August 1, 2008 $
;//###########################################################################
.def _DSP28x_DisableInt
.def _DSP28x_RestoreInt
_DSP28x_DisableInt:
PUSH ST1
SETC INTM,DBGM
MOV AL, *--SP
LRETR
_DSP28x_RestoreInt:
MOV *SP++, AL
POP ST1
LRETR
;//===========================================================================
;// End of file.
;//===========================================================================

404
v120/DSP2833x_common/source/DSP2833x_ECan.c Normal file
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// TI File $Revision: /main/8 $
// Checkin $Date: June 25, 2008 15:19:07 $
//###########################################################################
//
// FILE: DSP2833x_ECan.c
//
// TITLE: DSP2833x Enhanced CAN Initialization & Support Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitECan:
//---------------------------------------------------------------------------
// This function initializes the eCAN module to a known state.
//
void InitECan(void)
{
InitECana();
#if DSP28_ECANB
InitECanb();
#endif // if DSP28_ECANB
}
void InitECana(void) // Initialize eCAN-A module
{
/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents or return
false data. This is especially true while writing to/reading from a bit
(or group of bits) among bits 16 - 31 */
struct ECAN_REGS ECanaShadow;
EALLOW; // EALLOW enables access to protected bits
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters for eCANA*/
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
ECanaShadow.CANBTC.all = 0;
#if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
See Note at End of File */
ECanaShadow.CANBTC.bit.BRPREG = 4;
ECanaShadow.CANBTC.bit.TSEG2REG = 2;
ECanaShadow.CANBTC.bit.TSEG1REG = 10;
#endif
#if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
See Note at End of File */
ECanaShadow.CANBTC.bit.BRPREG = 4;
ECanaShadow.CANBTC.bit.TSEG2REG = 1;
ECanaShadow.CANBTC.bit.TSEG1REG = 6;
#endif
ECanaShadow.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
EDIS;
}
#if (DSP28_ECANB)
void InitECanb(void) // Initialize eCAN-B module
{
/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents or return
false data. This is especially true while writing to/reading from a bit
(or group of bits) among bits 16 - 31 */
struct ECAN_REGS ECanbShadow;
EALLOW; // EALLOW enables access to protected bits
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
ECanbShadow.CANTIOC.bit.TXFUNC = 1;
ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;
ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
ECanbShadow.CANRIOC.bit.RXFUNC = 1;
ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
ECanbShadow.CANMC.bit.SCB = 1;
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
ECanbRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanbRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
ECanbRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanbRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters for eCANB*/
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
do
{
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
} while(ECanbShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be cleared..
ECanbShadow.CANBTC.all = 0;
#if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
See Note at end of file */
ECanbShadow.CANBTC.bit.BRPREG = 4;
ECanbShadow.CANBTC.bit.TSEG2REG = 2;
ECanbShadow.CANBTC.bit.TSEG1REG = 10;
#endif
#if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
See Note at end of file */
ECanbShadow.CANBTC.bit.BRPREG = 4;
ECanbShadow.CANBTC.bit.TSEG2REG = 1;
ECanbShadow.CANBTC.bit.TSEG1REG = 6;
#endif
ECanbShadow.CANBTC.bit.SAM = 1;
ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
do
{
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
} while(ECanbShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs
EDIS;
}
#endif // if DSP28_ECANB
//---------------------------------------------------------------------------
// Example: InitECanGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as eCAN pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
// Caution:
// Only one GPIO pin should be enabled for CANTXA/B operation.
// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
// Comment out other unwanted lines.
void InitECanGpio(void)
{
InitECanaGpio();
#if (DSP28_ECANB)
InitECanbGpio();
#endif // if DSP28_ECANB
}
void InitECanaGpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA)
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA)
// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (CANTXA)
/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA)
/* Configure eCAN-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 for CANRXA operation
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 for CANTXA operation
EDIS;
}
#if (DSP28_ECANB)
void InitECanbGpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up for GPIO8 (CANTXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up for GPIO12 (CANTXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up for GPIO16 (CANTXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up for GPIO20 (CANTXB)
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10 (CANRXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13 (CANRXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17 (CANRXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21 (CANRXB)
/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB)
// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)
/* Configure eCAN-B pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB operation
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB operation
EDIS;
}
#endif // if DSP28_ECANB
/*
Note: Bit timing parameters must be chosen based on the network parameters such
as the sampling point desired and the propagation delay of the network.
The propagation delay is a function of length of the cable, delay introduced by
the transceivers and opto/galvanic-isolators (if any).
The parameters used in this file must be changed taking into account the above
mentioned factors in order to arrive at the bit-timing parameters suitable
for a network.
*/

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v120/DSP2833x_common/source/DSP2833x_ECap.c Normal file
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// TI File $Revision: /main/2 $
// Checkin $Date: March 15, 2007 16:54:36 $
//###########################################################################
//
// FILE: DSP2833x_ECap.c
//
// TITLE: DSP2833x eCAP Initialization & Support Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitECap:
//---------------------------------------------------------------------------
// This function initializes the eCAP(s) to a known state.
//
void InitECap(void)
{
// Initialize eCAP1/2/3
//tbd...
}
//---------------------------------------------------------------------------
// Example: InitECapGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as ECAP pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
// Caution:
// For each eCAP peripheral
// Only one GPIO pin should be enabled for ECAP operation.
// Comment out other unwanted lines.
void InitECapGpio()
{
InitECap1Gpio();
#if (DSP28_ECAP2)
InitECap2Gpio();
#endif // endif DSP28_ECAP2
#if (DSP28_ECAP3)
InitECap3Gpio();
#endif // endif DSP28_ECAP3
#if (DSP28_ECAP4)
InitECap4Gpio();
#endif // endif DSP28_ECAP4
#if (DSP28_ECAP5)
InitECap5Gpio();
#endif // endif DSP28_ECAP5
#if (DSP28_ECAP6)
InitECap6Gpio();
#endif // endif DSP28_ECAP6
}
void InitECap1Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (CAP1)
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (CAP1)
// GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on GPIO34 (CAP1)
// Inputs are synchronized to SYSCLKOUT by default.
// Comment out other unwanted lines.
// GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0; // Synch to SYSCLKOUT GPIO5 (CAP1)
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT GPIO24 (CAP1)
// GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; // Synch to SYSCLKOUT GPIO34 (CAP1)
/* Configure eCAP-1 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAP1 functional pins.
// Comment out other unwanted lines.
// GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Configure GPIO5 as CAP1
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO24 as CAP1
// GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 1; // Configure GPIO24 as CAP1
EDIS;
}
#if DSP28_ECAP2
void InitECap2Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (CAP2)
// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (CAP2)
// GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pull-up on GPIO37 (CAP2)
// Inputs are synchronized to SYSCLKOUT by default.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLKOUT GPIO7 (CAP2)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Synch to SYSCLKOUT GPIO25 (CAP2)
// GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; // Synch to SYSCLKOUT GPIO37 (CAP2)
/* Configure eCAP-2 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAP2 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // Configure GPIO7 as CAP2
// GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO25 as CAP2
// GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // Configure GPIO37 as CAP2
EDIS;
}
#endif // endif DSP28_ECAP2
#if DSP28_ECAP3
void InitECap3Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (CAP3)
// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (CAP3)
// Inputs are synchronized to SYSCLKOUT by default.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Synch to SYSCLKOUT GPIO9 (CAP3)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Synch to SYSCLKOUT GPIO26 (CAP3)
/* Configure eCAP-3 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAP3 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 3; // Configure GPIO9 as CAP3
// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO26 as CAP3
EDIS;
}
#endif // endif DSP28_ECAP3
#if DSP28_ECAP4
void InitECap4Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (CAP4)
// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (CAP4)
// Inputs are synchronized to SYSCLKOUT by default.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Synch to SYSCLKOUT GPIO11 (CAP4)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Synch to SYSCLKOUT GPIO27 (CAP4)
/* Configure eCAP-4 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAP4 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as CAP4
// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO27 as CAP4
EDIS;
}
#endif // endif DSP28_ECAP4
#if DSP28_ECAP5
void InitECap5Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (CAP5)
// GpioCtrlRegs.GPBPUD.bit.GPIO48 = 0; // Enable pull-up on GPIO48 (CAP5)
// Inputs are synchronized to SYSCLKOUT by default.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Synch to SYSCLKOUT GPIO3 (CAP5)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0; // Synch to SYSCLKOUT GPIO48 (CAP5)
/* Configure eCAP-5 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAP5 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as CAP5
// GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 1; // Configure GPIO48 as CAP5
EDIS;
}
#endif // endif DSP28_ECAP5
#if DSP28_ECAP6
void InitECap6Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (CAP6)
// GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0; // Enable pull-up on GPIO49 (CAP6)
// Inputs are synchronized to SYSCLKOUT by default.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Synch to SYSCLKOUT GPIO1 (CAP6)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0; // Synch to SYSCLKOUT GPIO49 (CAP6)
/* Configure eCAP-5 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAP6 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; // Configure GPIO1 as CAP6
// GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 1; // Configure GPIO49 as CAP6
EDIS;
}
#endif // endif DSP28_ECAP6
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:46:19 $
//###########################################################################
//
// FILE: DSP2833x_EPwm.c
//
// TITLE: DSP2833x ePWM Initialization & Support Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitEPwm:
//---------------------------------------------------------------------------
// This function initializes the ePWM(s) to a known state.
//
void InitEPwm(void)
{
// Initialize ePWM1/2/3/4/5/6
//tbd...
}
//---------------------------------------------------------------------------
// Example: InitEPwmGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as ePWM pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
void InitEPwmGpio(void)
{
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
#if DSP28_EPWM4
InitEPwm4Gpio();
#endif // endif DSP28_EPWM4
#if DSP28_EPWM5
InitEPwm5Gpio();
#endif // endif DSP28_EPWM5
#if DSP28_EPWM6
InitEPwm6Gpio();
#endif // endif DSP28_EPWM6
}
void InitEPwm1Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A)
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (EPWM1B)
/* Configure ePWM-1 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be ePWM1 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B
EDIS;
}
void InitEPwm2Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pull-up on GPIO2 (EPWM2A)
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (EPWM3B)
/* Configure ePWM-2 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be ePWM2 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B
EDIS;
}
void InitEPwm3Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pull-up on GPIO4 (EPWM3A)
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (EPWM3B)
/* Configure ePWM-3 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be ePWM3 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B
EDIS;
}
#if DSP28_EPWM4
void InitEPwm4Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWM4A)
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (EPWM4B)
/* Configure ePWM-4 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be ePWM4 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B
EDIS;
}
#endif // endif DSP28_EPWM4
#if DSP28_EPWM5
void InitEPwm5Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up on GPIO8 (EPWM5A)
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (EPWM5B)
/* Configure ePWM-5 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be ePWM5 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B
EDIS;
}
#endif // endif DSP28_EPWM5
#if DSP28_EPWM6
void InitEPwm6Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up on GPIO10 (EPWM6A)
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (EPWM6B)
/* Configure ePWM-6 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be ePWM6 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B
EDIS;
}
#endif // endif DSP28_EPWM6
//---------------------------------------------------------------------------
// Example: InitEPwmSyncGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as ePWM Synch pins
//
void InitEPwmSyncGpio(void)
{
EALLOW;
/* Configure EPWMSYNCI */
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWMSYNCI)
// GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up on GPIO32 (EPWMSYNCI)
/* Set qualification for selected pins to asynch only */
// This will select synch to SYSCLKOUT for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Synch to SYSCLKOUT GPIO6 (EPWMSYNCI)
// GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0; // Synch to SYSCLKOUT GPIO32 (EPWMSYNCI)
/* Configure EPwmSync pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be EPwmSync functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 2; // Enable pull-up on GPIO6 (EPWMSYNCI)
// GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2; // Enable pull-up on GPIO32 (EPWMSYNCI)
/* Configure EPWMSYNC0 */
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
// GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWMSYNC0)
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up on GPIO33 (EPWMSYNC0)
// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3; // Enable pull-up on GPIO6 (EPWMSYNC0)
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2; // Enable pull-up on GPIO33 (EPWMSYNC0)
}
//---------------------------------------------------------------------------
// Example: InitTzGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as Trip Zone (TZ) pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
void InitTzGpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (TZ1)
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (TZ2)
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (TZ3)
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (TZ4)
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (TZ5)
// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up on GPIO28 (TZ5)
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (TZ6)
// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up on GPIO29 (TZ6)
/* Set qualification for selected pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Asynch input GPIO12 (TZ1)
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (TZ2)
GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (TZ3)
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (TZ4)
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (TZ5)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (TZ5)
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (TZ6)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3; // Asynch input GPIO29 (TZ6)
/* Configure TZ pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be TZ functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as TZ1
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as TZ2
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as TZ3
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as TZ4
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as TZ5
// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // Configure GPIO28 as TZ5
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as TZ6
// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // Configure GPIO29 as TZ6
EDIS;
}
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_common/source/DSP2833x_EQep.c Normal file
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// TI File $Revision: /main/3 $
// Checkin $Date: July 27, 2007 11:55:20 $
//###########################################################################
//
// FILE: DSP2833x_EQep.c
//
// TITLE: DSP2833x eQEP Initialization & Support Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitEQep:
//---------------------------------------------------------------------------
// This function initializes the eQEP(s) to a known state.
//
void InitEQep(void)
{
// Initialize eQEP1/2
//tbd...
}
//---------------------------------------------------------------------------
// Example: InitEQepGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as eQEP pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
// Caution:
// For each eQEP peripheral
// Only one GPIO pin should be enabled for EQEPxA operation.
// Only one GPIO pin should be enabled for EQEPxB operation.
// Only one GPIO pin should be enabled for EQEPxS operation.
// Only one GPIO pin should be enabled for EQEPxI operation.
// Comment out other unwanted lines.
void InitEQepGpio()
{
#if DSP28_EQEP1
InitEQep1Gpio();
#endif // endif DSP28_EQEP1
#if DSP28_EQEP2
InitEQep2Gpio();
#endif // endif DSP28_EQEP2
}
#if DSP28_EQEP1
void InitEQep1Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (EQEP1A)
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (EQEP1B)
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (EQEP1S)
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (EQEP1I)
// GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pull-up on GPIO50 (EQEP1A)
// GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pull-up on GPIO51 (EQEP1B)
// GpioCtrlRegs.GPBPUD.bit.GPIO52 = 0; // Enable pull-up on GPIO52 (EQEP1S)
// GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0; // Enable pull-up on GPIO53 (EQEP1I)
// Inputs are synchronized to SYSCLKOUT by default.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync to SYSCLKOUT GPIO20 (EQEP1A)
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync to SYSCLKOUT GPIO21 (EQEP1B)
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync to SYSCLKOUT GPIO22 (EQEP1S)
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync to SYSCLKOUT GPIO23 (EQEP1I)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Sync to SYSCLKOUT GPIO50 (EQEP1A)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Sync to SYSCLKOUT GPIO51 (EQEP1B)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; // Sync to SYSCLKOUT GPIO52 (EQEP1S)
// GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; // Sync to SYSCLKOUT GPIO53 (EQEP1I)
/* Configure eQEP-1 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eQEP1 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I
// GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A
// GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B
// GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S
// GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I
EDIS;
}
#endif // if DSP28_EQEP1
#if DSP28_EQEP2
void InitEQep2Gpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (EQEP2A)
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (EQEP2B)
GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (EQEP2I)
GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (EQEP2S)
// Inputs are synchronized to SYSCLKOUT by default.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync to SYSCLKOUT GPIO24 (EQEP2A)
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync to SYSCLKOUT GPIO25 (EQEP2B)
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync to SYSCLKOUT GPIO26 (EQEP2I)
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync to SYSCLKOUT GPIO27 (EQEP2S)
/* Configure eQEP-2 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eQEP2 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2I
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2S
EDIS;
}
#endif // endif DSP28_EQEP2
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:46:25 $
//###########################################################################
//
// FILE: DSP2833x_Gpio.c
//
// TITLE: DSP2833x General Purpose I/O Initialization & Support Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitGpio:
//---------------------------------------------------------------------------
// This function initializes the Gpio to a known (default) state.
//
// For more details on configuring GPIO's as peripheral functions,
// refer to the individual peripheral examples and/or GPIO setup example.
void InitGpio(void)
{
EALLOW;
// Each GPIO pin can be:
// a) a GPIO input/output
// b) peripheral function 1
// c) peripheral function 2
// d) peripheral function 3
// By default, all are GPIO Inputs
GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15
GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31
GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO39
GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO48-GPIO63
GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79
GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95
GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs
GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs
GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are inputs
// Each input can have different qualification
// a) input synchronized to SYSCLKOUT
// b) input qualified by a sampling window
// c) input sent asynchronously (valid for peripheral inputs only)
GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT
GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT
GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 Synch to SYSCLKOUT
GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 Synch to SYSCLKOUT
// Pull-ups can be enabled or disabled.
GpioCtrlRegs.GPAPUD.all = 0x0000; // Pullup's enabled GPIO0-GPIO31
GpioCtrlRegs.GPBPUD.all = 0x0000; // Pullup's enabled GPIO32-GPIO63
GpioCtrlRegs.GPCPUD.all = 0x0000; // Pullup's enabled GPIO64-GPIO79
//GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31
//GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34
//GpioCtrlRegs.GPCPUD.all = 0xFFFF // Pullup's disabled GPIO64-GPIO79
EDIS;
}
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:46:27 $
//###########################################################################
//
// FILE: DSP2833x_I2C.c
//
// TITLE: DSP2833x SCI Initialization & Support Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitI2C:
//---------------------------------------------------------------------------
// This function initializes the I2C to a known state.
//
void InitI2C(void)
{
// Initialize I2C-A:
//tbd...
}
//---------------------------------------------------------------------------
// Example: InitI2CGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as I2C pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
// Caution:
// Only one GPIO pin should be enabled for SDAA operation.
// Only one GPIO pin shoudl be enabled for SCLA operation.
// Comment out other unwanted lines.
void InitI2CGpio()
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA)
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA)
/* Set qualification for selected pins to asynch only */
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA)
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA)
/* Configure SCI pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be I2C functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 for SDAA operation
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 for SCLA operation
EDIS;
}
//===========================================================================
// End of file.
//===========================================================================

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// TI File $Revision: /main/16 $
// Checkin $Date: October 3, 2007 14:50:19 $
//###########################################################################
//
// FILE: DSP2833x_McBSP.c
//
// TITLE: DSP2833x Device McBSP Initialization & Support Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate
// generator (SRG) cycles required for the Mcbsp initialization routine.
// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock
// generator (CLKG) cycles required for the Mcbsp initialization routine.
// For the functions defined in Mcbsp.c, MCBSP_INIT_DELAY and MCBSP_CLKG_DELAY
// are based off of either a 150 MHz SYSCLKOUT (default) or a 100 MHz SYSCLKOUT.
//
// CPU_FRQ_100MHZ and CPU_FRQ_150MHZ are defined in DSP2833x_Examples.h
//---------------------------------------------------------------------------
#if CPU_FRQ_150MHZ // For 150 MHz SYSCLKOUT(default)
#define CPU_SPD 150E6
#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) for examples
#endif
#if CPU_FRQ_100MHZ // For 100 MHz SYSCLKOUT
#define CPU_SPD 100E6
#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) for examples
#endif
#define CLKGDV_VAL 1
#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ) // # of CPU cycles in 2 SRG cycles-init delay
#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL))) // # of CPU cycles in 2 CLKG cycles-init delay
//---------------------------------------------------------------------------
// InitMcbsp:
//---------------------------------------------------------------------------
// This function initializes the McBSP to a known state.
//
void delay_loop(void); // Delay function used for SRG initialization
void clkg_delay_loop(void); // Delay function used for CLKG initialization
void InitMcbsp(void)
{
InitMcbspa();
#if DSP28_MCBSPB
InitMcbspb();
#endif // end DSP28_MCBSPB
}
void InitMcbspa(void)
{
// McBSP-A register settings
McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
McbspaRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode.
McbspaRegs.MFFINT.all=0x0; // Disable all interrupts
McbspaRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive)
McbspaRegs.RCR1.all=0x0;
McbspaRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit)
McbspaRegs.XCR1.all=0x0;
McbspaRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source
McbspaRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source
McbspaRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods
McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1)
delay_loop(); // Wait at least 2 SRG clock cycles
McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
clkg_delay_loop(); // Wait at least 2 CLKG cycles
McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
}
#if (DSP28_MCBSPB)
void InitMcbspb(void)
{
// McBSP-B register settings
McbspbRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspbRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
McbspbRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode.
McbspbRegs.MFFINT.all=0x0; // Disable all interrupts
McbspbRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive)
McbspbRegs.RCR1.all=0x0;
McbspbRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit)
McbspbRegs.XCR1.all=0x0;
McbspbRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
McbspbRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods
McbspbRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1)
McbspbRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source
McbspbRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source
delay_loop(); // Wait at least 2 SRG clock cycles
McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
clkg_delay_loop(); // Wait at least 2 CLKG cycles
McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
}
#endif // end DSP28_MCBSPB
// McBSP-A Data Lengths
void InitMcbspa8bit(void)
{
McbspaRegs.RCR1.bit.RWDLEN1=0; // 8-bit word
McbspaRegs.XCR1.bit.XWDLEN1=0; // 8-bit word
}
void InitMcbspa12bit(void)
{
McbspaRegs.RCR1.bit.RWDLEN1=1; // 12-bit word
McbspaRegs.XCR1.bit.XWDLEN1=1; // 12-bit word
}
void InitMcbspa16bit(void)
{
McbspaRegs.RCR1.bit.RWDLEN1=2; // 16-bit word
McbspaRegs.XCR1.bit.XWDLEN1=2; // 16-bit word
}
void InitMcbspa20bit(void)
{
McbspaRegs.RCR1.bit.RWDLEN1=3; // 20-bit word
McbspaRegs.XCR1.bit.XWDLEN1=3; // 20-bit word
}
void InitMcbspa24bit(void)
{
McbspaRegs.RCR1.bit.RWDLEN1=4; // 24-bit word
McbspaRegs.XCR1.bit.XWDLEN1=4; // 24-bit word
}
void InitMcbspa32bit(void)
{
McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word
McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word
}
// McBSP-B Data Lengths
#if (DSP28_MCBSPB)
void InitMcbspb8bit(void)
{
McbspbRegs.RCR1.bit.RWDLEN1=0; // 8-bit word
McbspbRegs.XCR1.bit.XWDLEN1=0; // 8-bit word
}
void InitMcbspb12bit(void)
{
McbspbRegs.RCR1.bit.RWDLEN1=1; // 12-bit word
McbspbRegs.XCR1.bit.XWDLEN1=1; // 12-bit word
}
void InitMcbspb16bit(void)
{
McbspbRegs.RCR1.bit.RWDLEN1=2; // 16-bit word
McbspbRegs.XCR1.bit.XWDLEN1=2; // 16-bit word
}
void InitMcbspb20bit(void)
{
McbspbRegs.RCR1.bit.RWDLEN1=3; // 20-bit word
McbspbRegs.XCR1.bit.XWDLEN1=3; // 20-bit word
}
void InitMcbspb24bit(void)
{
McbspbRegs.RCR1.bit.RWDLEN1=4; // 24-bit word
McbspbRegs.XCR1.bit.XWDLEN1=4; // 24-bit word
}
void InitMcbspb32bit(void)
{
McbspbRegs.RCR1.bit.RWDLEN1=5; // 32-bit word
McbspbRegs.XCR1.bit.XWDLEN1=5; // 32-bit word
}
#endif //end DSP28_MCBSPB
void InitMcbspGpio(void)
{
InitMcbspaGpio();
#if DSP28_MCBSPB
InitMcbspbGpio();
#endif // end DSP28_MCBSPB
}
void InitMcbspaGpio(void)
{
EALLOW;
/* Configure McBSP-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be McBSP functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; // GPIO20 is MDXA pin
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; // GPIO21 is MDRA pin
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; // GPIO22 is MCLKXA pin
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; // GPIO7 is MCLKRA pin (Comment as needed)
//GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; // GPIO58 is MCLKRA pin (Comment as needed)
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; // GPIO23 is MFSXA pin
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // GPIO5 is MFSRA pin (Comment as needed)
//GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; // GPIO59 is MFSRA pin (Comment as needed)
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (MDXA)
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (MDRA)
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (MCLKXA)
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (MCLKRA) (Comment as needed)
//GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (MCLKRA) (Comment as needed)
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (MFSXA)
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (MFSRA) (Comment as needed)
//GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (MFSRA) (Comment as needed)
/* Set qualification for selected input pins to asynch only */
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch input GPIO21 (MDRA)
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; // Asynch input GPIO22 (MCLKXA)
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; // Asynch input GPIO7 (MCLKRA) (Comment as needed)
//GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58(MCLKRA) (Comment as needed)
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (MFSXA)
GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (MFSRA) (Comment as needed)
//GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (MFSRA) (Comment as needed)
EDIS;
}
#if DSP28_MCBSPB
void InitMcbspbGpio(void)
{
EALLOW;
/* Configure McBSP-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be McBSP functional pins.
// Comment out other unwanted lines.
//GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // GPIO12 is MDXB pin (Comment as needed)
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; // GPIO24 is MDXB pin (Comment as needed)
//GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // GPIO13 is MDRB pin (Comment as needed)
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; // GPIO25 is MDRB pin (Comment as needed)
//GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // GPIO14 is MCLKXB pin (Comment as needed)
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; // GPIO26 is MCLKXB pin (Comment as needed)
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3; // GPIO3 is MCLKRB pin (Comment as needed)
//GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1; // GPIO60 is MCLKRB pin (Comment as needed)
//GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // GPIO15 is MFSXB pin (Comment as needed)
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; // GPIO27 is MFSXB pin (Comment as needed)
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; // GPIO1 is MFSRB pin (Comment as needed)
//GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1; // GPIO61 is MFSRB pin (Comment as needed)
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (MDXB) (Comment as needed)
//GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (MDXB) (Comment as needed)
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (MDRB) (Comment as needed)
//GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (MDRB) (Comment as needed)
GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (MCLKXB) (Comment as needed)
//GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (MCLKXB) (Comment as needed)
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (MCLKRB) (Comment as needed)
//GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; // Enable pull-up on GPIO60 (MCLKRB) (Comment as needed)
GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (MFSXB) (Comment as needed)
//GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (MFSXB) (Comment as needed)
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (MFSRB) (Comment as needed)
//GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pull-up on GPIO61 (MFSRB) (Comment as needed)
/* Set qualification for selected input pins to asynch only */
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO25 (MDRB) (Comment as needed)
//GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (MDRB) (Comment as needed)
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO26(MCLKXB) (Comment as needed)
//GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (MCLKXB) (Comment as needed)
GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (MCLKRB) (Comment as needed)
//GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO60 (MCLKRB) (Comment as needed)
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO27 (MFSXB) (Comment as needed)
//GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (MFSXB) (Comment as needed)
GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; // Asynch input GPIO1 (MFSRB) (Comment as needed)
//GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO61 (MFSRB) (Comment as needed)
EDIS;
}
#endif // end DSP28_MCBSPB
void delay_loop(void)
{
long i;
for (i = 0; i < MCBSP_INIT_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles
}
void clkg_delay_loop(void)
{
long i;
for (i = 0; i < MCBSP_CLKG_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles
}
//===========================================================================
// No more.
//===========================================================================

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:46:33 $
//###########################################################################
//
// FILE: DSP2833x_MemCopy.c
//
// TITLE: Memory Copy Utility
//
// ASSUMPTIONS:
//
//
//
// DESCRIPTION:
//
// This function will copy the specified memory contents from
// one location to another.
//
// Uint16 *SourceAddr Pointer to the first word to be moved
// SourceAddr < SourceEndAddr
// Uint16* SourceEndAddr Pointer to the last word to be moved
// Uint16* DestAddr Pointer to the first destination word
//
// No checks are made for invalid memory locations or that the
// end address is > then the first start address.
//
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h"
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr)
{
while(SourceAddr < SourceEndAddr)
{
*DestAddr++ = *SourceAddr++;
}
return;
}
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_common/source/DSP2833x_PieCtrl.c Normal file
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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:46:35 $
//###########################################################################
//
// FILE: DSP2833x_PieCtrl.c
//
// TITLE: DSP2833x Device PIE Control Register Initialization Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitPieCtrl:
//---------------------------------------------------------------------------
// This function initializes the PIE control registers to a known state.
//
void InitPieCtrl(void)
{
// Disable Interrupts at the CPU level:
DINT;
// Disable the PIE
PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
// Clear all PIEIER registers:
PieCtrlRegs.PIEIER1.all = 0;
PieCtrlRegs.PIEIER2.all = 0;
PieCtrlRegs.PIEIER3.all = 0;
PieCtrlRegs.PIEIER4.all = 0;
PieCtrlRegs.PIEIER5.all = 0;
PieCtrlRegs.PIEIER6.all = 0;
PieCtrlRegs.PIEIER7.all = 0;
PieCtrlRegs.PIEIER8.all = 0;
PieCtrlRegs.PIEIER9.all = 0;
PieCtrlRegs.PIEIER10.all = 0;
PieCtrlRegs.PIEIER11.all = 0;
PieCtrlRegs.PIEIER12.all = 0;
// Clear all PIEIFR registers:
PieCtrlRegs.PIEIFR1.all = 0;
PieCtrlRegs.PIEIFR2.all = 0;
PieCtrlRegs.PIEIFR3.all = 0;
PieCtrlRegs.PIEIFR4.all = 0;
PieCtrlRegs.PIEIFR5.all = 0;
PieCtrlRegs.PIEIFR6.all = 0;
PieCtrlRegs.PIEIFR7.all = 0;
PieCtrlRegs.PIEIFR8.all = 0;
PieCtrlRegs.PIEIFR9.all = 0;
PieCtrlRegs.PIEIFR10.all = 0;
PieCtrlRegs.PIEIFR11.all = 0;
PieCtrlRegs.PIEIFR12.all = 0;
}
//---------------------------------------------------------------------------
// EnableInterrupts:
//---------------------------------------------------------------------------
// This function enables the PIE module and CPU interrupts
//
void EnableInterrupts()
{
// Enable the PIE
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
// Enables PIE to drive a pulse into the CPU
PieCtrlRegs.PIEACK.all = 0xFFFF;
// Enable Interrupts at the CPU level
EINT;
}
//===========================================================================
// End of file.
//===========================================================================

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v120/DSP2833x_common/source/DSP2833x_PieVect.c Normal file
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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:46:38 $
//###########################################################################
//
// FILE: DSP2833x_PieVect.c
//
// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
const struct PIE_VECT_TABLE PieVectTableInit = {
PIE_RESERVED, // 0 Reserved space
PIE_RESERVED, // 1 Reserved space
PIE_RESERVED, // 2 Reserved space
PIE_RESERVED, // 3 Reserved space
PIE_RESERVED, // 4 Reserved space
PIE_RESERVED, // 5 Reserved space
PIE_RESERVED, // 6 Reserved space
PIE_RESERVED, // 7 Reserved space
PIE_RESERVED, // 8 Reserved space
PIE_RESERVED, // 9 Reserved space
PIE_RESERVED, // 10 Reserved space
PIE_RESERVED, // 11 Reserved space
PIE_RESERVED, // 12 Reserved space
// Non-Peripheral Interrupts
INT13_ISR, // XINT13 or CPU-Timer 1
INT14_ISR, // CPU-Timer2
DATALOG_ISR, // Datalogging interrupt
RTOSINT_ISR, // RTOS interrupt
EMUINT_ISR, // Emulation interrupt
NMI_ISR, // Non-maskable interrupt
ILLEGAL_ISR, // Illegal operation TRAP
USER1_ISR, // User Defined trap 1
USER2_ISR, // User Defined trap 2
USER3_ISR, // User Defined trap 3
USER4_ISR, // User Defined trap 4
USER5_ISR, // User Defined trap 5
USER6_ISR, // User Defined trap 6
USER7_ISR, // User Defined trap 7
USER8_ISR, // User Defined trap 8
USER9_ISR, // User Defined trap 9
USER10_ISR, // User Defined trap 10
USER11_ISR, // User Defined trap 11
USER12_ISR, // User Defined trap 12
// Group 1 PIE Vectors
SEQ1INT_ISR, // 1.1 ADC
SEQ2INT_ISR, // 1.2 ADC
rsvd_ISR, // 1.3
XINT1_ISR, // 1.4
XINT2_ISR, // 1.5
ADCINT_ISR, // 1.6 ADC
TINT0_ISR, // 1.7 Timer 0
WAKEINT_ISR, // 1.8 WD, Low Power
// Group 2 PIE Vectors
EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone
EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone
EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone
EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone
EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone
EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone
rsvd_ISR, // 2.7
rsvd_ISR, // 2.8
// Group 3 PIE Vectors
EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt
EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt
EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt
EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt
EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt
EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt
rsvd_ISR, // 3.7
rsvd_ISR, // 3.8
// Group 4 PIE Vectors
ECAP1_INT_ISR, // 4.1 ECAP-1
ECAP2_INT_ISR, // 4.2 ECAP-2
ECAP3_INT_ISR, // 4.3 ECAP-3
ECAP4_INT_ISR, // 4.4 ECAP-4
ECAP5_INT_ISR, // 4.5 ECAP-5
ECAP6_INT_ISR, // 4.6 ECAP-6
rsvd_ISR, // 4.7
rsvd_ISR, // 4.8
// Group 5 PIE Vectors
EQEP1_INT_ISR, // 5.1 EQEP-1
EQEP2_INT_ISR, // 5.2 EQEP-2
rsvd_ISR, // 5.3
rsvd_ISR, // 5.4
rsvd_ISR, // 5.5
rsvd_ISR, // 5.6
rsvd_ISR, // 5.7
rsvd_ISR, // 5.8
// Group 6 PIE Vectors
SPIRXINTA_ISR, // 6.1 SPI-A
SPITXINTA_ISR, // 6.2 SPI-A
MRINTA_ISR, // 6.3 McBSP-A
MXINTA_ISR, // 6.4 McBSP-A
MRINTB_ISR, // 6.5 McBSP-B
MXINTB_ISR, // 6.6 McBSP-B
rsvd_ISR, // 6.7
rsvd_ISR, // 6.8
// Group 7 PIE Vectors
DINTCH1_ISR, // 7.1 DMA channel 1
DINTCH2_ISR, // 7.2 DMA channel 2
DINTCH3_ISR, // 7.3 DMA channel 3
DINTCH4_ISR, // 7.4 DMA channel 4
DINTCH5_ISR, // 7.5 DMA channel 5
DINTCH6_ISR, // 7.6 DMA channel 6
rsvd_ISR, // 7.7
rsvd_ISR, // 7.8
// Group 8 PIE Vectors
I2CINT1A_ISR, // 8.1 I2C
I2CINT2A_ISR, // 8.2 I2C
rsvd_ISR, // 8.3
rsvd_ISR, // 8.4
SCIRXINTC_ISR, // 8.5 SCI-C
SCITXINTC_ISR, // 8.6 SCI-C
rsvd_ISR, // 8.7
rsvd_ISR, // 8.8
// Group 9 PIE Vectors
SCIRXINTA_ISR, // 9.1 SCI-A
SCITXINTA_ISR, // 9.2 SCI-A
SCIRXINTB_ISR, // 9.3 SCI-B
SCITXINTB_ISR, // 9.4 SCI-B
ECAN0INTA_ISR, // 9.5 eCAN-A
ECAN1INTA_ISR, // 9.6 eCAN-A
ECAN0INTB_ISR, // 9.7 eCAN-B
ECAN1INTB_ISR, // 9.8 eCAN-B
// Group 10 PIE Vectors
rsvd_ISR, // 10.1
rsvd_ISR, // 10.2
rsvd_ISR, // 10.3
rsvd_ISR, // 10.4
rsvd_ISR, // 10.5
rsvd_ISR, // 10.6
rsvd_ISR, // 10.7
rsvd_ISR, // 10.8
// Group 11 PIE Vectors
rsvd_ISR, // 11.1
rsvd_ISR, // 11.2
rsvd_ISR, // 11.3
rsvd_ISR, // 11.4
rsvd_ISR, // 11.5
rsvd_ISR, // 11.6
rsvd_ISR, // 11.7
rsvd_ISR, // 11.8
// Group 12 PIE Vectors
XINT3_ISR, // 12.1
XINT4_ISR, // 12.2
XINT5_ISR, // 12.3
XINT6_ISR, // 12.4
XINT7_ISR, // 12.5
rsvd_ISR, // 12.6
LVF_ISR, // 12.7
LUF_ISR, // 12.8
};
//---------------------------------------------------------------------------
// InitPieVectTable:
//---------------------------------------------------------------------------
// This function initializes the PIE vector table to a known state.
// This function must be executed after boot time.
//
void InitPieVectTable(void)
{
int16 i;
Uint32 *Source = (void *) &PieVectTableInit;
Uint32 *Dest = (void *) &PieVectTable;
EALLOW;
for(i=0; i < 128; i++)
*Dest++ = *Source++;
EDIS;
// Enable the PIE Vector Table
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
}
//===========================================================================
// End of file.
//===========================================================================

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